ahci: mmio_base is a virtual address

Don't store it in a u32.

Don't dereference the bus address as if it were a virtual address
(fixes 284231e49a2b4 ("ahci: Support splitting of read transactions
into multiple chunks")).

Fixes crash on boot in MPC8641HPCN_36BIT target.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index ab4a070f97007bf5d308ad8cc19395ea8282c9ef..f5e1217a710711f0625d61f0f60b0eae04617a84 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -159,6 +159,6 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 void arch_preboot_os(void)
 {
-       ahci_reset(DWC_AHSATA_BASE);
+       ahci_reset((void __iomem *)DWC_AHSATA_BASE);
 }
 #endif

diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
index d18bc50c5abd11a3c9b9f38a03978362c0ade127..2c2d1bce363d8dc8059b0607f568c9d77e9d2fb0 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/sata.c
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -69,7 +69,7 @@ int init_sata(int dev)
        val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
        writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
 
-       ret = ahci_init(DWC_AHSATA_BASE);
+       ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
 
        return ret;
 }
@@ -88,6 +88,6 @@ void scsi_init(void)
 
 void scsi_bus_reset(void)
 {
-       ahci_reset(DWC_AHSATA_BASE);
-       ahci_init(DWC_AHSATA_BASE);
+       ahci_reset((void __iomem *)DWC_AHSATA_BASE);
+       ahci_init((void __iomem *)DWC_AHSATA_BASE);
 }

diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index fc2385cf31a527a7225abe142928edbc6aa4939e..ba1beb5bbc92c3f032aacd32ec4322baefa5e347 100644 (file)
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -57,7 +57,7 @@ void scsi_init(void)
        u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
 
        if (reg & PWRDOM_STAT_SATA) {
-               ahci_init(HB_AHCI_BASE);
+               ahci_init((void __iomem *)HB_AHCI_BASE);
                scsi_scan(1);
        }
 }

diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
index b7f0dda2058eecf97547270a2feac54565b5d7b1..6d51b9b8e95b81ce6b84e1a982ce699b816a16de 100644 (file)
--- a/board/sunxi/ahci.c
+++ b/board/sunxi/ahci.c
@@ -83,5 +83,5 @@ void scsi_init(void)
        if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
                return;
 
-       ahci_init(SUNXI_SATA_BASE);
+       ahci_init((void __iomem *)SUNXI_SATA_BASE);
 }

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 88b90e02035766a00dc624f49a12edb0a4237cd9..65086484eeafab864e43d3dfa75160f69346cb63 100644 (file)
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -137,10 +137,10 @@ static void sunxi_dma_init(volatile u8 *port_mmio)
 }
 #endif
 
-int ahci_reset(u32 base)
+int ahci_reset(void __iomem *base)
 {
        int i = 1000;
-       u32 host_ctl_reg = base + HOST_CTL;
+       u32 __iomem *host_ctl_reg = base + HOST_CTL;
        u32 tmp = readl(host_ctl_reg); /* global controller reset */
 
        if ((tmp & HOST_RESET) == 0)
@@ -419,8 +419,9 @@ static int ahci_init_one(pci_dev_t pdev)
        probe_ent->pio_mask = 0x1f;
        probe_ent->udma_mask = 0x7f;    /*Fixme,assume to support UDMA6 */
 
-       pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
-       debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
+       probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
+                                          PCI_REGION_MEM);
+       debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
 
        /* Take from kernel:
         * JMicron-specific fixup:
@@ -939,7 +940,7 @@ void scsi_low_level_init(int busdevfunc)
 }
 
 #ifdef CONFIG_SCSI_AHCI_PLAT
-int ahci_init(u32 base)
+int ahci_init(void __iomem *base)
 {
        int i, rc = 0;
        u32 linkmap;

diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 30cc4e8cb930718cad68bcc489288b22b1e8afd9..3fa97b865633c461cf914b42c0578d89601079fb 100644 (file)
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -343,7 +343,7 @@ static int ahci_init_one(int pdev)
                                | ATA_FLAG_PIO_DMA
                                | ATA_FLAG_NO_ATAPI;
 
-       probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
+       probe_ent->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
 
        /* initialize adapter */
        rc = ahci_host_init(probe_ent);

diff --git a/include/ahci.h b/include/ahci.h
index 2cfd6cfbd7496263e4585cc3946868ab0d5b038b..c9cd9f1778ee2f0291202a35a9c7830b51876ca3 100644 (file)
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -1,7 +1,4 @@
 /*
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- * Terry Lv <r65388@freescale.com>
- *
  * Copyright (C) Freescale Semiconductor, Inc. 2006.
  * Author: Jason Jin<Jason.jin@freescale.com>
  *         Zhang Wei<wei.zhang@freescale.com>
@@ -15,7 +12,6 @@
 
 #define AHCI_PCI_BAR           0x24
 #define AHCI_MAX_SG            56 /* hardware max is 64K */
-#define AHCI_MAX_CMD_SLOT      32
 #define AHCI_CMD_SLOT_SZ       32
 #define AHCI_MAX_CMD_SLOT      32
 #define AHCI_RX_FIS_SZ         256
@@ -155,8 +151,8 @@ struct ahci_probe_ent {
        u32     hard_port_no;
        u32     host_flags;
        u32     host_set_flags;
-       u32     mmio_base;
-       u32     pio_mask;
+       void __iomem *mmio_base;
+       u32     pio_mask;
        u32     udma_mask;
        u32     flags;
        u32     cap;    /* cache of HOST_CAP register */
@@ -164,7 +160,7 @@ struct ahci_probe_ent {
        u32     link_port_map; /*linkup port map*/
 };
 
-int ahci_init(u32 base);
-int ahci_reset(u32 base);
+int ahci_init(void __iomem *base);
+int ahci_reset(void __iomem *base);
 
 #endif