syslog mechanism; used especially for POST results.
* Patch by Klaus Heydeck, 31 Oct 2002:
Add initial support for kup4k board
Changes since for U-Boot 0.1.0:
======================================================================
+* Add support for log buffer which can be passed to Linux kernel's
+ syslog mechanism; used especially for POST results.
+
+* Patch by Klaus Heydeck, 31 Oct 2002:
+ Add initial support for kup4k board
+
* Patch by Robert Schwebel, 04 Nov 2002:
- use watchdog to reset PXA250 systems
- added progress callbacks to (some of the) ARM code
MVS1 MPC823
+Klaus Heydeck <heydeck@kieback-peter.de>
+
+ KUP4K MPC855
+
Murray Jensen <Murray.Jensen@cmst.csiro.au>
cogent_mpc8xx MPC8xx
GEN860T GENIETV GTH hermes \
IAD210 ICU862_100MHz IP860 IVML24 \
IVML24_128 IVML24_256 IVMS8 IVMS8_128 \
- IVMS8_256 LANTEC lwmon MBX \
- MBX860T MHPC MVS1 NETVIA \
- NX823 pcu_e R360MPI RPXClassic \
- RPXlite RRvision SM850 SPD823TS \
- SXNI855T TQM823L TQM823L_LCD TQM850L \
- TQM855L TQM860L TQM860L_FEC TTTech \
+ IVMS8_256 KUP4K LANTEC lwmon \
+ MBX MBX860T MHPC MVS1 \
+ NETVIA NX823 pcu_e R360MPI \
+ RPXClassic RPXlite RRvision SM850 \
+ SPD823TS SXNI855T TQM823L TQM823L_LCD \
+ TQM850L TQM855L TQM860L TQM860L_FEC \
+ TTTech
"
#########################################################################
}
@./mkconfig -a IVMS8 ppc mpc8xx ivm
+KUP4K_config : unconfig
+ @./mkconfig $(@:_config=) ppc mpc8xx kup4k
+
LANTEC_config : unconfig
@./mkconfig $(@:_config=) ppc mpc8xx lantec
--- /dev/null
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# KUP4K board
+#
+
+TEXT_BASE = 0x40000000
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef CFG_ENV_ADDR
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+#define CONFIG_FLASH_16BIT
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16;
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ vu_short *s_addr=(vu_short*)addr;
+ s_addr[0x5555] = 0x00AA;
+ s_addr[0x2AAA] = 0x0055;
+ s_addr[0x5555] = 0x0090;
+
+ value = s_addr[0];
+ value = value|(value<<16);
+
+ switch (value) {
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = s_addr[1];
+ value = value|(value<<16);
+
+ switch (value) {
+ case FUJI_ID_29F800BA:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ s_addr = (volatile unsigned short *)(info->start[i]);
+ info->protect[i] = s_addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ s_addr = (volatile unsigned short *)info->start[0];
+ *s_addr = 0x00F0; /* reset bank */
+ }
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ int flag, prot, sect;
+ ulong start, now, last;
+#ifdef CONFIG_FLASH_16BIT
+ vu_short *s_addr = (vu_short*)addr;
+#endif
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+/*#ifndef CONFIG_FLASH_16BIT
+ ulong type;
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return;
+ }
+#endif*/
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+#ifdef CONFIG_FLASH_16BIT
+ vu_short *s_sect_addr = (vu_short*)(info->start[sect]);
+#else
+ vu_long *sect_addr = (vu_long*)(info->start[sect]);
+#endif
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+#ifdef CONFIG_FLASH_16BIT
+
+ /*printf("\ns_sect_addr=%x",s_sect_addr);*/
+ s_addr[0x5555] = 0x00AA;
+ s_addr[0x2AAA] = 0x0055;
+ s_addr[0x5555] = 0x0080;
+ s_addr[0x5555] = 0x00AA;
+ s_addr[0x2AAA] = 0x0055;
+ s_sect_addr[0] = 0x0030;
+#else
+ addr[0x5555] = 0x00AA00AA;
+ addr[0x2AAA] = 0x00550055;
+ addr[0x5555] = 0x00800080;
+ addr[0x5555] = 0x00AA00AA;
+ addr[0x2AAA] = 0x00550055;
+ sect_addr[0] = 0x00300030;
+#endif
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+#ifdef CONFIG_FLASH_16BIT
+ while ((s_sect_addr[0] & 0x0080) != 0x0080) {
+#else
+ while ((sect_addr[0] & 0x00800080) != 0x00800080) {
+#endif
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ }
+ }
+
+ /* reset to read mode */
+ addr = (volatile unsigned long *)info->start[0];
+#ifdef CONFIG_FLASH_16BIT
+ s_addr[0] = 0x00F0; /* reset bank */
+#else
+ addr[0] = 0x00F000F0; /* reset bank */
+#endif
+
+ printf (" done\n");
+ return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+
+#ifdef CONFIG_FLASH_16BIT
+ vu_short high_data;
+ vu_short low_data;
+ vu_short *s_addr = (vu_short*)addr;
+#endif
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+#ifdef CONFIG_FLASH_16BIT
+ /* Write the 16 higher-bits */
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ high_data = ((data>>16) & 0x0000ffff);
+
+ s_addr[0x5555] = 0x00AA;
+ s_addr[0x2AAA] = 0x0055;
+ s_addr[0x5555] = 0x00A0;
+
+ *((vu_short *)dest) = high_data;
+
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+
+
+ /* Write the 16 lower-bits */
+#endif
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+#ifdef CONFIG_FLASH_16BIT
+ dest += 0x2;
+ low_data = (data & 0x0000ffff);
+
+ s_addr[0x5555] = 0x00AA;
+ s_addr[0x2AAA] = 0x0055;
+ s_addr[0x5555] = 0x00A0;
+ *((vu_short *)dest) = low_data;
+
+#else
+ addr[0x5555] = 0x00AA00AA;
+ addr[0x2AAA] = 0x00550055;
+ addr[0x5555] = 0x00A000A0;
+ *((vu_long *)dest) = data;
+#endif
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+
+#ifdef CONFIG_FLASH_16BIT
+ while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
+#else
+ while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+#endif
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#ifdef CONFIG_KUP4K_LOGO
+ #include "s1d13706.h"
+#endif
+
+
+typedef struct
+{
+ volatile unsigned char *VmemAddr;
+ volatile unsigned char *RegAddr;
+}FB_INFO_S1D13xxx;
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+static long int dram_size (long int, long int *, long int);
+#endif
+
+#ifdef CONFIG_KUP4K_LOGO
+ void lcd_logo(bd_t *bd);
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x1F07FC04,
+ 0xEEAEFC04,
+ 0x11ADFC04,
+ 0xEFBBBC00,
+ 0x1FF77C47, /* last */
+
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF77C35,
+ 0xEFEABC34,
+ 0x1FB57C35, /* last */
+
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0x1F07FC04,
+ 0xEEAEFC04,
+ 0x10ADFC04,
+ 0xF0AFFC00,
+ 0xF0AFFC00,
+ 0xF1AFFC00,
+ 0xEFBBBC00,
+ 0x1FF77C47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0x1F27FC04,
+ 0xEEAEBC00,
+ 0x01B93C04,
+ 0x1FF77C47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x1F07FC04,
+ 0xEEAEBC00,
+ 0x10AD7C00,
+ 0xF0AFFC00,
+ 0xF0AFFC00,
+ 0xE1BBBC04,
+ 0x1FF77C47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0x1FF5FC84,
+ 0xFFFFFC04,
+ 0xFFFFFC04,
+ 0xFFFFFC04,
+ 0xFFFFFC84,
+ 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+
+ printf ("### No HW ID - assuming KUP4K-Color\n");
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0 = 0;
+ long int size_b1 = 0;
+ long int size_b2 = 0;
+
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+/* memctl->memc_or1 = CFG_OR1_PRELIM; */
+/* memctl->memc_br1 = CFG_BR1_PRELIM; */
+
+/* memctl->memc_or2 = CFG_OR2_PRELIM; */
+/* memctl->memc_br2 = CFG_BR2_PRELIM; */
+
+
+ memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+
+ udelay(200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
+ udelay(1);
+ memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
+ udelay(1);
+ memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
+ udelay(1);
+
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
+ udelay(1);
+ memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
+ udelay(1);
+ memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
+ udelay(1);
+
+ memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
+ udelay(1);
+ memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
+ udelay(1);
+ memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+ udelay(1);
+
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay (1000);
+
+ size_b0 = 0x00800000;
+ size_b1 = 0x00800000;
+ size_b2 = 0x00800000;
+
+
+ memctl->memc_mptpr = CFG_MPTPR;
+ udelay(1000);
+
+ memctl->memc_or1 = 0xFF800A00;
+ memctl->memc_br1 = 0x00000081;
+
+ memctl->memc_or2 = 0xFF000A00;
+ memctl->memc_br2 = 0x00800081;
+
+ memctl->memc_or3 = 0xFE000A00;
+ memctl->memc_br3 = 0x01000081;
+
+ udelay(10000);
+
+
+ return (size_b0 + size_b1 + size_b2);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+#if 0
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ ulong cnt, val;
+ ulong save[32]; /* to make test non-destructive */
+ unsigned char i = 0;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+ *addr = save[--i];
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ return (maxsize);
+}
+#endif
+
+int misc_init_r (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_KUP4K_LOGO
+ bd_t *bd = gd->bd;
+
+
+ lcd_logo(bd);
+#endif /* CONFIG_KUP4K_LOGO */
+ return(0);
+}
+
+#ifdef CONFIG_KUP4K_LOGO
+void lcd_logo(bd_t *bd){
+
+ FB_INFO_S1D13xxx fb_info;
+ S1D_INDEX s1dReg;
+ S1D_VALUE s1dValue;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl;
+ ushort i;
+ uchar *fb;
+ int rs, gs, bs;
+ int r = 8, g = 8, b = 4;
+ int r1,g1,b1;
+
+/*----------------------------------------------------------------------------- */
+/**/
+/* Initialize the chip and the frame buffer driver. */
+/**/
+/*----------------------------------------------------------------------------- */
+ memctl = &immr->im_memctl;
+/* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
+/* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
+
+ memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
+ memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
+
+
+
+
+
+ fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
+ fb_info.RegAddr = (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
+
+ if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
+ {
+ printf("Warning:LCD Controller S1D13706 not found\n");
+ return;
+ }
+
+ /* init controller */
+ for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
+ {
+ s1dReg = aS1DRegs[i].Index;
+ s1dValue = aS1DRegs[i].Value;
+/* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
+ ((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
+ }
+
+#undef MONOCHROME
+#ifdef MONOCHROME
+ switch(bd->bi_busfreq){
+#if 0
+ case 24000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
+ break;
+ case 32000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
+ break;
+#endif
+ case 40000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
+ break;
+ case 48000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
+ break;
+ default:
+ printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
+ case 64000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
+ break;
+ }
+ ((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
+#else
+ switch(bd->bi_busfreq){
+#if 0
+ case 24000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
+ break;
+ case 32000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
+ break;
+#endif
+ case 40000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
+ break;
+ case 48000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
+ break;
+ default:
+ printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
+ case 64000000:
+ ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+ ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
+ break;
+ }
+#endif
+
+
+ /* create and set colormap */
+ rs = 256 / (r - 1);
+ gs = 256 / (g - 1);
+ bs = 256 / (b - 1);
+ for(i=0;i<256;i++){
+ r1=(rs * ((i / (g * b)) % r)) * 255;
+ g1=(gs * ((i / b) % g)) * 255;
+ b1=(bs * ((i) % b)) * 255;
+/* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
+ S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
+ }
+
+ /* copy bitmap */
+ fb = (char *) (fb_info.VmemAddr);
+ memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
+}
+#endif /* CONFIG_KUP4K_LOGO */
+
--- /dev/null
+/*---------------------------------------------------------------------------- */
+/* */
+/* File generated by S1D13706CFG.EXE */
+/* */
+/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */
+/* All rights reserved. */
+/* */
+/*---------------------------------------------------------------------------- */
+
+/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
+
+#define S1D_DISPLAY_WIDTH 320
+#define S1D_DISPLAY_HEIGHT 240
+#define S1D_DISPLAY_BPP 8
+#define S1D_DISPLAY_SCANLINE_BYTES 320
+#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L
+#define S1D_PHYSICAL_VMEM_SIZE 0x14000L
+#define S1D_PHYSICAL_REG_ADDR 0x80080000L
+#define S1D_PHYSICAL_REG_SIZE 0x100
+#define S1D_DISPLAY_PCLK 6250
+#define S1D_PALETTE_SIZE 256
+#define S1D_REGDELAYOFF 0xFFFE
+#define S1D_REGDELAYON 0xFFFF
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b) \
+{ \
+ ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \
+ ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \
+ ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \
+ ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
+}
+
+#define S1D_READ_PALETTE(p,i,r,g,b) \
+{ \
+ ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
+ r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \
+ g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \
+ b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \
+}
+
+typedef unsigned short S1D_INDEX;
+typedef unsigned char S1D_VALUE;
+
+
+typedef struct
+{
+ S1D_INDEX Index;
+ S1D_VALUE Value;
+} S1D_REGS;
+
+static S1D_REGS aS1DRegs[] =
+{
+
+
+ {0x04,0x10}, /* BUSCLK MEMCLK Config Register */
+#if 0
+ {0x05,0x32}, /* PCLK Config Register */
+#endif
+ {0x10,0xD0}, /* PANEL Type Register */
+ {0x11,0x00}, /* MOD Rate Register */
+#if 0
+ {0x12,0x34}, /* Horizontal Total Register */
+#endif
+ {0x14,0x27}, /* Horizontal Display Period Register */
+ {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
+ {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
+ {0x18,0xF0}, /* Vertical Total Register 0 */
+ {0x19,0x00}, /* Vertical Total Register 1 */
+ {0x1C,0xEF}, /* Vertical Display Period Register 0 */
+ {0x1D,0x00}, /* Vertical Display Period Register 1 */
+ {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
+ {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
+ {0x20,0x87}, /* Horizontal Sync Pulse Width Register */
+ {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
+ {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
+ {0x24,0x80}, /* Vertical Sync Pulse Width Register */
+ {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
+ {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
+ {0x70,0x83}, /* Display Mode Register */
+ {0x71,0x00}, /* Special Effects Register */
+ {0x74,0x00}, /* Main Window Display Start Address Register 0 */
+ {0x75,0x00}, /* Main Window Display Start Address Register 1 */
+ {0x76,0x00}, /* Main Window Display Start Address Register 2 */
+ {0x78,0x50}, /* Main Window Address Offset Register 0 */
+ {0x79,0x00}, /* Main Window Address Offset Register 1 */
+ {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
+ {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
+ {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
+ {0x80,0x50}, /* Sub Window Address Offset Register 0 */
+ {0x81,0x00}, /* Sub Window Address Offset Register 1 */
+ {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
+ {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
+ {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
+ {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
+ {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
+ {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
+ {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
+ {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
+ {0xA0,0x00}, /* Power Save Config Register */
+ {0xA1,0x00}, /* CPU Access Control Register */
+ {0xA2,0x00}, /* Software Reset Register */
+ {0xA3,0x00}, /* BIG Endian Support Register */
+ {0xA4,0x00}, /* Scratch Pad Register 0 */
+ {0xA5,0x00}, /* Scratch Pad Register 1 */
+ {0xA8,0x01}, /* GPIO Config Register 0 */
+ {0xA9,0x80}, /* GPIO Config Register 1 */
+ {0xAC,0x01}, /* GPIO Status Control Register 0 */
+ {0xAD,0x00}, /* GPIO Status Control Register 1 */
+ {0xB0,0x00}, /* PWM CV Clock Control Register */
+ {0xB1,0x00}, /* PWM CV Clock Config Register */
+ {0xB2,0x00}, /* CV Clock Burst Length Register */
+ {0xB3,0x00}, /* PWM Clock Duty Cycle Register */
+ {0xAD,0x80}, /* reset seq */
+ {0x70,0x03}, /* */
+};
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ common/dlmalloc.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ . = env_offset;
+ common/environment.o (.ppcenv)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
cmd_dcr.o cmd_diag.o cmd_doc.o cmd_dtt.o \
cmd_eeprom.o cmd_elf.o cmd_fdc.o cmd_flash.o \
cmd_fpga.o cmd_i2c.o cmd_ide.o cmd_immap.o \
- cmd_jffs2.o cmd_mem.o cmd_mii.o cmd_misc.o \
+ cmd_jffs2.o cmd_log.o cmd_mem.o cmd_mii.o cmd_misc.o \
cmd_net.o cmd_nvedit.o env_common.o \
env_flash.o env_eeprom.o env_nvram.o env_nowhere.o \
cmd_pci.o cmd_pcmcia.o \
initrd_high = ~0;
}
+#ifdef CONFIG_LOGBUFFER
+ kbd=gd->bd;
+ if ((s = getenv ("logstart")) != NULL) {
+ kbd->bi_sramstart = simple_strtoul(s, NULL, 16);
+ /* Prevent initrd from overwriting logbuffer */
+ if (initrd_high < kbd->bi_sramstart)
+ initrd_high = kbd->bi_sramstart-1024;
+ }
+ debug ("## Logbuffer at 0x%08lX ", kbd->bi_sramstart);
+#endif
+
/*
* Booting a (Linux) kernel image
*
asm( "mr %0,1": "=r"(sp) : );
-#ifdef DEBUG
- printf ("## Current stack ends at 0x%08lX ", sp);
-#endif
+ debug ("## Current stack ends at 0x%08lX ", sp);
+
sp -= 2048; /* just to be sure */
if (sp > CFG_BOOTMAPSZ)
sp = CFG_BOOTMAPSZ;
sp &= ~0xF;
-#ifdef DEBUG
- printf ("=> set upper limit to 0x%08lX\n", sp);
-#endif
+ debug ("=> set upper limit to 0x%08lX\n", sp);
+
cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF);
kbd = (bd_t *)(((ulong)cmdline - sizeof(bd_t)) & ~0xF);
len = data = 0;
}
-#ifdef DEBUG
if (!data) {
- printf ("No initrd\n");
+ debug ("No initrd\n");
}
-#endif
if (data) {
initrd_start = (ulong)kbd - len;
}
SHOW_BOOT_PROGRESS (12);
-#ifdef DEBUG
- printf ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
+
+ debug ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
data, data + len - 1, len, len);
-#endif
+
initrd_end = initrd_start + len;
printf (" Loading Ramdisk to %08lx, end %08lx ... ",
initrd_start, initrd_end);
initrd_end = 0;
}
-#ifdef DEBUG
- printf ("## Transferring control to Linux (at address %08lx) ...\n",
+
+ debug ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)kernel);
-#endif
+
SHOW_BOOT_PROGRESS (15);
#ifdef CFG_INIT_RAM_LOCK
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Logbuffer handling routines
+ */
+
+#include <common.h>
+#include <command.h>
+#include <devices.h>
+#include <logbuff.h>
+
+#if defined(CONFIG_LOGBUFFER)
+
+#define LOG_BUF_LEN (16384)
+#define LOG_BUF_MASK (LOG_BUF_LEN-1)
+
+/* Local prototypes */
+static void logbuff_putc (const char c);
+static void logbuff_puts (const char *s);
+static int logbuff_printk(const char *line);
+
+static char buf[1024];
+
+static unsigned console_loglevel = 3;
+static unsigned default_message_loglevel = 4;
+static unsigned long log_size;
+static unsigned char *log_buf=NULL;
+static unsigned long *ext_log_start, *ext_logged_chars;
+#define log_start (*ext_log_start)
+#define logged_chars (*ext_logged_chars)
+
+/* Forced by code, eh! */
+#define LOGBUFF_MAGIC 0xc0de4ced
+
+int drv_logbuff_init (void)
+{
+ device_t logdev;
+ int rc;
+
+ /* Device initialization */
+ memset (&logdev, 0, sizeof (logdev));
+
+ strcpy (logdev.name, "logbuff");
+ logdev.ext = 0; /* No extensions */
+ logdev.flags = DEV_FLAGS_OUTPUT; /* Output only */
+ logdev.putc = logbuff_putc; /* 'putc' function */
+ logdev.puts = logbuff_puts; /* 'puts' function */
+
+ rc = device_register (&logdev);
+
+ return (rc == 0) ? 1 : rc;
+}
+
+static void logbuff_putc (const char c)
+{
+ char buf[2];
+ buf[0]=c;
+ buf[1]='\0';
+ logbuff_printk(buf);
+}
+
+static void logbuff_puts (const char *s)
+{
+ char buf[512];
+
+ sprintf(buf, "%s\n", s);
+ logbuff_printk(buf);
+}
+
+void logbuff_log(char *msg)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (gd->flags & GD_FLG_RELOC) {
+ logbuff_printk(msg);
+ } else {
+ puts(msg);
+ }
+}
+
+void logbuff_reset (void)
+{
+ char *s;
+ unsigned long *ext_tag;
+
+ if ((s = getenv ("logstart")) != NULL) {
+ log_buf = (unsigned char *)simple_strtoul(s, NULL, 16);
+ ext_tag=(unsigned long *)(log_buf)-3;
+ ext_log_start=(unsigned long *)(log_buf)-2;
+ ext_logged_chars=(unsigned long *)(log_buf)-1;
+// if (*ext_tag!=LOGBUFF_MAGIC) {
+ logged_chars=log_start=0;
+ *ext_tag=LOGBUFF_MAGIC;
+// }
+ log_size=logged_chars;
+ }
+}
+
+/*
+ * Subroutine: do_log
+ *
+ * Description: Handler for 'log' command..
+ *
+ * Inputs: argv[1] contains the subcommand
+ *
+ * Return: None
+ *
+ */
+int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char *s;
+ unsigned long i;
+
+ if (log_buf==NULL) {
+ printf ("No logbuffer defined! Set 'logstart' to use this feature.\n");
+ return 1;
+ }
+
+ switch (argc) {
+
+ case 2:
+ if (strcmp(argv[1],"show") == 0) {
+ for (i=0; i<logged_chars; i++) {
+ s=log_buf+((log_start+i)&LOG_BUF_MASK);
+ putc(*s);
+ }
+ return 0;
+ } else if (strcmp(argv[1],"reset") == 0) {
+ log_start=0;
+ logged_chars=0;
+ log_size=0;
+ return 0;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+
+ case 3:
+ if (strcmp(argv[1],"append") == 0) {
+ logbuff_puts(argv[2]);
+ return 0;
+
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+
+ default:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+}
+
+static int logbuff_printk(const char *line)
+{
+ int i;
+ char *msg, *p, *buf_end;
+ int line_feed;
+ static signed char msg_level = -1;
+
+ strcpy(buf + 3, line);
+ i = strlen(line);
+ buf_end = buf + 3 + i;
+ for (p = buf + 3; p < buf_end; p++) {
+ msg = p;
+ if (msg_level < 0) {
+ if (
+ p[0] != '<' ||
+ p[1] < '0' ||
+ p[1] > '7' ||
+ p[2] != '>'
+ ) {
+ p -= 3;
+ p[0] = '<';
+ p[1] = default_message_loglevel + '0';
+ p[2] = '>';
+ } else
+ msg += 3;
+ msg_level = p[1] - '0';
+ }
+ line_feed = 0;
+ for (; p < buf_end; p++) {
+ log_buf[(log_start+log_size) & LOG_BUF_MASK] = *p;
+ if (log_size < LOG_BUF_LEN)
+ log_size++;
+ else
+ log_start++;
+
+ logged_chars++;
+ if (*p == '\n') {
+ line_feed = 1;
+ break;
+ }
+ }
+ if (msg_level < console_loglevel) {
+ printf("%s", msg);
+ }
+ if (line_feed)
+ msg_level = -1;
+ }
+ return i;
+}
+
+#endif /* (CONFIG_LOGBUFFER) */
#endif /* R360MPI */
+/* ---------------------------------------------------------------------------- */
+/* KUP4K Board */
+/* ---------------------------------------------------------------------------- */
+#if defined(CONFIG_KUP4K)
+
+#define PCMCIA_BOARD_MSG "KUP4K"
+
+#define KUP4K_PCMCIA_B_3V3 (0x00020000)
+
+static int hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /* disable interrupts & DMA */
+ PCMCIA_PGCRX(_slot_) = 0;
+
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Port B pins for
+ * 3 Volts enable
+ */
+ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
+ cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
+ /* remove all power */
+ cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & 0x00001800) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+ if ((reg & mask) == mask) {
+ puts (" 5.0V card found: NOT SUPPORTED !!!\n");
+ } else {
+ cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
+ puts (" 3.3V card found: ");
+ }
+#if 0
+ /* VCC switch error flag, PCMCIA slot INPACK_ pin */
+ cp->cp_pbdir &= ~(0x0020 | 0x0010);
+ cp->cp_pbpar &= ~(0x0020 | 0x0010);
+ udelay(500000);
+#endif
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+static int hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /* remove all power */
+ cp->cp_pbdat |= DDC4000_PCMCIA_B_3V3;
+
+ /* Configure PCMCIA General Control Register */
+ PCMCIA_PGCRX(_slot_) = 0;
+
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("voltage_set: " \
+ PCMCIA_BOARD_MSG \
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("PCMCIA power OFF\n");
+ /*
+ * Configure Port B pins for
+ * 3 Volts enable
+ */
+ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
+ cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
+ /* remove all power */
+ cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
+
+ switch(vcc) {
+ case 0: break;
+ case 33:
+ cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
+ debug ("PCMCIA powered at 3.3V\n");
+ break;
+ case 50:
+ debug ("PCMCIA: 5Volt vcc not supported\n");
+ break;
+ default:
+ puts("PCMCIA: vcc not supported");
+ break;
+ }
+
+ /* Checking supported voltages */
+
+ debug ("PIPR: 0x%x --> %s\n",
+ pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000)
+ ? "only 5 V --> NOT SUPPORTED"
+ : "can do 3.3V");
+
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* KUP4K */
+
+
+
+
/* ---------------------------------------------------------------------------- */
/* End of Board Specific Stuff */
#include <cmd_dtt.h>
#include <cmd_vfd.h> /* load a bitmap to the VFDs on TRAB */
+#include <cmd_log.h>
/*
* HELP command
CMD_TBL_KGDB
CMD_TBL_LOADB
CMD_TBL_LOADS
+ CMD_TBL_LOG
CMD_TBL_LOOP
CMD_TBL_JFFS2_LS
CMD_TBL_MCCINFO
#endif
#ifdef CONFIG_WL_4PPM_KEYBOARD
drv_wlkbd_init ();
+#endif
+#ifdef CONFIG_LOGBUFFER
+ drv_logbuff_init ();
#endif
drv_system_init ();
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CMD_LOG_H_
+#define _CMD_LOG_H_
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_LOGBUFFER)
+
+#define LOG_BUF_LEN 16843
+#define LOG_BU_MASK ~(LOG_BUF_LEN-1)
+
+#define CMD_TBL_LOG MK_CMD_TBL_ENTRY( \
+ "log", 3, 3, 1, do_log, \
+ "log - manipulate logbuffer\n", \
+ "log reset - clear contents\n" \
+ "log show - show contents\n" \
+ "log append <msg> - append <msg> to the logbuffer\n" \
+),
+int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+#else
+#define CMD_TBL_LOG
+#endif /* CONFIG_LOGBUFFER */
+/* ----------------------------------------------------------------------------*/
+#endif /* _CMD_LOG_H_ */
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
+/*** KUP4K *********************************************************/
+/* The KUP4K uses the FEC on a MPC855T for Ethernet */
+
+#if defined(CONFIG_KUP4K)
+
+#define FEC_ENET /* use FEC for EThernet */
+#undef SCC_ENET
+
+#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
+
+#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
+
+#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
+#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
+#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
+#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
+#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
+#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
+#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
+#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
+#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
+#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
+#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
+#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
+#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
+
+#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
+
+#endif /* CONFIG_KUP4K */
+
+
/*** LANTEC *********************************************************/
#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
+#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
+#endif
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#if 0
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#endif
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "dhcp ;"\
+ "setenv bootargs root=/dev/nfs ro nfsroot=$(nfsip):$(rootpath) "\
+ "ip=$(ipaddr):$(nfsip):$(gatewayip):"\
+ "$(netmask):heydeck.eva:eth0:off; "\
+ "bootm 100000"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "diskboot 100000 0:1; "\
+ "setenv bootargs root=/dev/hda2 panic=1 "\
+ "ip=192.168.0.71:192.168.0.100:192.168.0.2:255.255.255.0; "\
+ "bootm"
+
+#define CONFIG_BOOTCOMMAND \
+ "run ramboot "\
+ "run nfsboot"
+
+#define CONFIG_MISC_INIT_R 1
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
+#define CONFIG_KUP4K_LOGO 0x40040000 /* Address of logo bitmap */
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_IDE | \
+ CFG_CMD_DATE )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x8000
+
+/* Address and size of Redundant Environment Sector */
+#if 0
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#if 0
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#define CFG_PLPRCR ( (3-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF00
+#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+
+#define CONFIG_PCMCIA_SLOT_B 1 /* KUP4K use SLOT_B */
+
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_2_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
+#define SDRAM_BASE3_PRELIM 0x30000000 /* SDRAM bank #2 */
+#define SDRAM_MAX_SIZE 0x04000000 /* max 648 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM 0x00000A00
+
+#if 0
+#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#endif
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock!)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider = 98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA 156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA 129
+#else /* 50 MHz */
+#define CFG_MAMR_PTA 98
+#endif /*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
+#define CFG_MPTPR 0x400
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CFG_MAMR 0x80802114
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#if 0
+#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
+#endif
+#define CONFIG_AUTOBOOT_STOP_STR "2" /* easy to stop for now */
+
+#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+/* External logbuffer support */
+#define CONFIG_LOGBUFFER
+
+/* Reserve space for the logbuffer */
+#ifdef CONFIG_LOGBUFFER
+#define CONFIG_PRAM 20
+#endif
+
/*
* High Level Configuration Options
* (easy to change)
#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
+#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
+#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
+
#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Detlev Zundel, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _LOGBUFF_H
+#define _LOGBUFF_H
+
+#ifdef CONFIG_LOGBUFFER
+
+#define LOGBUFF_TEST0 0x01
+
+int drv_logbuff_init (void);
+void logbuff_log(char *msg);
+void logbuff_reset (void);
+
+#endif /* CONFIG_LOGBUFFER */
+
+#endif /* _LOGBUFF_H */
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+/***** KUP4K ********************************************************/
+#elif defined(CONFIG_KUP4K)
+
+# define STATUS_LED_PAR im_ioport.iop_papar
+# define STATUS_LED_DIR im_ioport.iop_padir
+# define STATUS_LED_ODR im_ioport.iop_paodr
+# define STATUS_LED_DAT im_ioport.iop_padat
+
+# define STATUS_LED_BIT 0x00000300 /* green + red PA[8]=yellow, PA[7]=red, PA[6]=green */
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
/************************************************************************/
#else
# error Status LED configuration missing
#if defined(CONFIG_POST)
#include <post.h>
#endif
+#if defined(CONFIG_LOGBUFFER)
+#include <logbuff.h>
+#endif
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
void doc_init (void);
WATCHDOG_RESET ();
+#ifdef CONFIG_LOGBUFFER
+ logbuff_reset ();
+#endif
#ifdef CONFIG_POST
post_reloc ();
#endif
defined(CONFIG_CPCI405) || \
defined(CONFIG_EVB64260) || \
defined(CONFIG_HYMOD) || \
+ defined(CONFIG_KUP4K) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_W7O) || \
#include <watchdog.h>
#include <post.h>
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+
#ifdef CONFIG_POST
#define POST_MAX_NUMBER 32
post_bootmode_test_on (i);
}
- post_log ("START %s\n", test->cmd);
+ post_log ("POST %s ", test->cmd);
}
if ((*test->test) (flags) != 0)
i = vsprintf (printbuffer, format, args);
va_end (args);
+#ifdef CONFIG_LOGBUFFER
+ logbuff_log (printbuffer);
+#else
/* Send to the stdout file */
puts (printbuffer);
+#endif
return 0;
}
projects / karo-tx-uboot.git / commitdiff