Merge branch 'master' of git://www.denx.de/git/u-boot-imx
authorTom Rini <trini@ti.com>
Fri, 29 Aug 2014 15:06:51 +0000 (11:06 -0400)
committerTom Rini <trini@ti.com>
Fri, 29 Aug 2014 15:06:51 +0000 (11:06 -0400)
395 files changed:
CREDITS
Kconfig
MAINTAINERS [new file with mode: 0644]
MAKEALL
Makefile
README
api/api_net.c
arch/arm/Kconfig
arch/arm/cpu/armv7/sunxi/dram.c
arch/arm/include/asm/arch-sunxi/dram.h
arch/arm/include/asm/emif.h
arch/blackfin/config.mk
arch/blackfin/cpu/cpu.c
arch/blackfin/cpu/start.S
arch/blackfin/cpu/u-boot.lds
arch/blackfin/include/asm/clock.h
arch/blackfin/include/asm/config.h
arch/blackfin/include/asm/mach-bf609/BF609_def.h
arch/blackfin/include/asm/u-boot.h
arch/blackfin/lib/Makefile
arch/blackfin/lib/board.c [deleted file]
arch/blackfin/lib/sections.c [new file with mode: 0644]
arch/nios2/Kconfig
arch/nios2/config.mk
arch/nios2/cpu/Makefile
arch/nios2/cpu/cpu.c
arch/nios2/cpu/epcs.c [deleted file]
arch/nios2/cpu/start.S
arch/nios2/include/asm/config.h
arch/nios2/include/asm/posix_types.h
arch/nios2/include/asm/u-boot.h
arch/nios2/lib/Makefile
arch/nios2/lib/board.c [deleted file]
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc8xx/Kconfig
arch/powerpc/cpu/mpc8xx/cpu_init.c
arch/powerpc/lib/board.c
board/davinci/dm355evm/MAINTAINERS
board/davinci/dm355leopard/MAINTAINERS
board/davinci/dm365evm/MAINTAINERS
board/davinci/dm6467evm/MAINTAINERS
board/flagadm/Kconfig [deleted file]
board/flagadm/MAINTAINERS [deleted file]
board/flagadm/Makefile [deleted file]
board/flagadm/flagadm.c [deleted file]
board/flagadm/flash.c [deleted file]
board/flagadm/u-boot.lds [deleted file]
board/flagadm/u-boot.lds.debug [deleted file]
board/freescale/common/Makefile
board/freescale/common/diu_ch7301.c [new file with mode: 0644]
board/freescale/common/diu_ch7301.h [new file with mode: 0644]
board/freescale/t1040qds/diu.c
board/freescale/t104xrdb/Makefile
board/freescale/t104xrdb/diu.c [new file with mode: 0644]
board/freescale/t104xrdb/spl.c
board/freescale/t4qds/README [moved from doc/README.t4240qds with 86% similarity]
board/freescale/t4qds/eth.c
board/gen860t/Kconfig [deleted file]
board/gen860t/MAINTAINERS [deleted file]
board/gen860t/Makefile [deleted file]
board/gen860t/README [deleted file]
board/gen860t/beeper.c [deleted file]
board/gen860t/beeper.h [deleted file]
board/gen860t/flash.c [deleted file]
board/gen860t/fpga.c [deleted file]
board/gen860t/fpga.h [deleted file]
board/gen860t/gen860t.c [deleted file]
board/gen860t/ioport.c [deleted file]
board/gen860t/ioport.h [deleted file]
board/gen860t/u-boot-flashenv.lds [deleted file]
board/gen860t/u-boot.lds [deleted file]
board/keymile/kmp204x/kmp204x.c
board/prodrive/alpr/nand.c
board/psyent/common/AMDLV065D.c [deleted file]
board/psyent/pci5441/Kconfig [deleted file]
board/psyent/pci5441/MAINTAINERS [deleted file]
board/psyent/pci5441/Makefile [deleted file]
board/psyent/pci5441/config.mk [deleted file]
board/psyent/pci5441/pci5441.c [deleted file]
board/psyent/pk1c20/Kconfig [deleted file]
board/psyent/pk1c20/MAINTAINERS [deleted file]
board/psyent/pk1c20/Makefile [deleted file]
board/psyent/pk1c20/config.mk [deleted file]
board/psyent/pk1c20/led.c [deleted file]
board/psyent/pk1c20/pk1c20.c [deleted file]
board/samsung/common/Makefile
board/samsung/common/gadget.c [moved from board/samsung/common/thor.c with 77% similarity]
board/sixnet/Kconfig [deleted file]
board/sixnet/MAINTAINERS [deleted file]
board/sixnet/Makefile [deleted file]
board/sixnet/flash.c [deleted file]
board/sixnet/fpgadata.c [deleted file]
board/sixnet/sixnet.c [deleted file]
board/sixnet/sixnet.h [deleted file]
board/sixnet/u-boot.lds [deleted file]
board/socrates/nand.c
board/stx/stxxtc/Kconfig [deleted file]
board/stx/stxxtc/MAINTAINERS [deleted file]
board/stx/stxxtc/Makefile [deleted file]
board/stx/stxxtc/README.stxxtc [deleted file]
board/stx/stxxtc/stxxtc.c [deleted file]
board/stx/stxxtc/u-boot.lds [deleted file]
board/stx/stxxtc/u-boot.lds.debug [deleted file]
board/sunxi/Kconfig
board/svm_sc8xx/Kconfig [deleted file]
board/svm_sc8xx/MAINTAINERS [deleted file]
board/svm_sc8xx/Makefile [deleted file]
board/svm_sc8xx/flash.c [deleted file]
board/svm_sc8xx/svm_sc8xx.c [deleted file]
board/svm_sc8xx/u-boot.lds [deleted file]
board/svm_sc8xx/u-boot.lds.debug [deleted file]
board/ti/omap5912osk/Kconfig [deleted file]
board/ti/omap5912osk/MAINTAINERS [deleted file]
board/ti/omap5912osk/Makefile [deleted file]
board/ti/omap5912osk/config.mk [deleted file]
board/ti/omap5912osk/lowlevel_init.S [deleted file]
board/ti/omap5912osk/omap5912osk.c [deleted file]
board/tqc/tqm8272/nand.c
common/board_f.c
common/board_r.c
common/bootm.c
common/cli_simple.c
common/cmd_dfu.c
common/cmd_ext4.c
common/cmd_fat.c
common/cmd_fdt.c
common/cmd_fs.c
common/cmd_mtdparts.c
common/cmd_pxe.c
common/cmd_thordown.c
common/cmd_ubi.c
common/cmd_ubifs.c
common/env_fat.c
common/fdt_support.c
common/image-fdt.c
common/image-fit.c
common/image.c
common/lcd.c
configs/A10-OLinuXino-Lime_defconfig
configs/A10s-OLinuXino-M_defconfig
configs/A13-OLinuXinoM_defconfig
configs/A13-OLinuXino_defconfig
configs/A20-OLinuXino_MICRO_defconfig
configs/Auxtek-T004_defconfig
configs/Bananapi_defconfig
configs/Cubieboard2_FEL_defconfig
configs/Cubieboard2_defconfig
configs/Cubieboard_defconfig
configs/Cubietruck_FEL_defconfig
configs/Cubietruck_defconfig
configs/FLAGADM_defconfig [deleted file]
configs/GEN860T_SC_defconfig [deleted file]
configs/GEN860T_defconfig [deleted file]
configs/Linksprite_pcDuino3_defconfig
configs/Mele_A1000G_defconfig
configs/Mele_A1000_defconfig
configs/Mini-X-1Gb_defconfig
configs/Mini-X_defconfig
configs/PCI5441_defconfig [deleted file]
configs/PK1C20_defconfig [deleted file]
configs/SXNI855T_defconfig [deleted file]
configs/ba10_tv_box_defconfig
configs/i12-tvbox_defconfig
configs/omap5912osk_defconfig [deleted file]
configs/qt840a_defconfig
configs/r7-tv-dongle_defconfig
configs/stxxtc_defconfig [deleted file]
configs/svm_sc8xx_defconfig [deleted file]
doc/README.android-fastboot
doc/README.kconfig [new file with mode: 0644]
doc/README.scrapyard
doc/git-mailrc
doc/uImage.FIT/signature.txt
drivers/dfu/Makefile
drivers/dfu/dfu.c
drivers/dfu/dfu_mmc.c
drivers/dfu/dfu_nand.c
drivers/dfu/dfu_ram.c
drivers/dfu/dfu_sf.c [new file with mode: 0644]
drivers/dma/Makefile
drivers/dma/omap3_dma.c [deleted file]
drivers/mtd/mtdconcat.c
drivers/mtd/mtdcore.c
drivers/mtd/mtdcore.h [new file with mode: 0644]
drivers/mtd/mtdpart.c
drivers/mtd/nand/fsl_elbc_nand.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsl_upm.c
drivers/mtd/nand/mpc5121_nfc.c
drivers/mtd/nand/mxc_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_bbt.c
drivers/mtd/nand/nand_ids.c
drivers/mtd/nand/nand_util.c
drivers/mtd/nand/ndfc.c
drivers/mtd/onenand/onenand_base.c
drivers/mtd/onenand/onenand_bbt.c
drivers/mtd/onenand/samsung.c
drivers/mtd/ubi/Makefile
drivers/mtd/ubi/attach.c [new file with mode: 0644]
drivers/mtd/ubi/build.c
drivers/mtd/ubi/crc32.c
drivers/mtd/ubi/crc32table.h
drivers/mtd/ubi/debug.c
drivers/mtd/ubi/debug.h
drivers/mtd/ubi/eba.c
drivers/mtd/ubi/fastmap.c [new file with mode: 0644]
drivers/mtd/ubi/io.c
drivers/mtd/ubi/kapi.c
drivers/mtd/ubi/misc.c
drivers/mtd/ubi/scan.c [deleted file]
drivers/mtd/ubi/scan.h [deleted file]
drivers/mtd/ubi/ubi-media.h
drivers/mtd/ubi/ubi.h
drivers/mtd/ubi/upd.c
drivers/mtd/ubi/vmt.c
drivers/mtd/ubi/vtbl.c
drivers/mtd/ubi/wl.c
drivers/net/Makefile
drivers/net/cpsw.c
drivers/net/e1000.c
drivers/net/e1000.h
drivers/net/fm/t4240.c
drivers/net/phy/Makefile
drivers/net/phy/icplus.c [deleted file]
drivers/net/phy/phy.c
drivers/net/phy/vitesse.c
drivers/net/plb2800_eth.c [deleted file]
drivers/pci/pci.c
drivers/pcmcia/tqm8xx_pcmcia.c
drivers/qe/qe.c
drivers/rtc/Makefile
drivers/rtc/ds1307.c
drivers/serial/ns16550.c
drivers/serial/serial_ns16550.c
drivers/serial/serial_sh.c
drivers/serial/serial_sh.h
drivers/serial/usbtty.h
drivers/usb/gadget/Makefile
drivers/usb/gadget/ether.c
drivers/usb/gadget/f_dfu.c
drivers/usb/gadget/f_thor.c
drivers/usb/gadget/omap1510_udc.c [deleted file]
drivers/usb/gadget/storage_common.c
drivers/usb/host/ehci-rmobile.c
drivers/usb/musb-new/linux-compat.h
drivers/video/Makefile
drivers/video/am335x-fb.c [new file with mode: 0644]
drivers/video/am335x-fb.h [new file with mode: 0644]
drivers/video/exynos_dp.c
drivers/video/exynos_mipi_dsi.c
drivers/video/ipu.h
drivers/video/ipu_disp.c
drivers/video/ipu_regs.h
fs/ext4/ext4fs.c
fs/fat/fat.c
fs/fs.c
fs/sandbox/sandboxfs.c
fs/ubifs/budget.c
fs/ubifs/debug.c
fs/ubifs/debug.h
fs/ubifs/io.c
fs/ubifs/key.h
fs/ubifs/log.c
fs/ubifs/lprops.c
fs/ubifs/lpt.c
fs/ubifs/lpt_commit.c
fs/ubifs/master.c
fs/ubifs/misc.h
fs/ubifs/orphan.c
fs/ubifs/recovery.c
fs/ubifs/replay.c
fs/ubifs/sb.c
fs/ubifs/scan.c
fs/ubifs/super.c
fs/ubifs/tnc.c
fs/ubifs/tnc_misc.c
fs/ubifs/ubifs-media.h
fs/ubifs/ubifs.c
fs/ubifs/ubifs.h
fs/yaffs2/ydirectenv.h
include/cli.h
include/common.h
include/commproc.h
include/config_distro_bootcmd.h [new file with mode: 0644]
include/configs/FLAGADM.h [deleted file]
include/configs/GEN860T.h [deleted file]
include/configs/PCI5441.h [deleted file]
include/configs/PK1C20.h [deleted file]
include/configs/SXNI855T.h [deleted file]
include/configs/T1040QDS.h
include/configs/T104xRDB.h
include/configs/bf506f-ezkit.h
include/configs/bf533-stamp.h
include/configs/bf538f-ezkit.h
include/configs/exynos4-dt.h
include/configs/km/km-powerpc.h
include/configs/koelsch.h
include/configs/lager.h
include/configs/nios2-generic.h
include/configs/omap1510.h [deleted file]
include/configs/omap5912osk.h [deleted file]
include/configs/openrd.h
include/configs/rpi_b.h
include/configs/s5p_goni.h
include/configs/stxxtc.h [deleted file]
include/configs/sunxi-common.h
include/configs/svm_sc8xx.h [deleted file]
include/configs/tegra-common-post.h
include/configs/trats.h
include/configs/trats2.h
include/dfu.h
include/ext4fs.h
include/fat.h
include/fdt_support.h
include/fs.h
include/image.h
include/lcd.h
include/libfdt.h
include/linux/compat.h
include/linux/err.h
include/linux/list_sort.h [new file with mode: 0644]
include/linux/mtd/bbm.h
include/linux/mtd/concat.h
include/linux/mtd/flashchip.h [new file with mode: 0644]
include/linux/mtd/mtd.h
include/linux/mtd/nand.h
include/linux/mtd/partitions.h
include/linux/mtd/ubi.h
include/linux/rbtree.h
include/linux/rbtree_augmented.h [new file with mode: 0644]
include/linux/usb/gadget.h
include/mtd/mtd-abi.h
include/mtd/ubi-user.h
include/netdev.h
include/nios2-epcs.h [deleted file]
include/ns16550.h
include/pci_ids.h
include/pcmcia.h
include/sandboxfs.h
include/sparse_format.h [new file with mode: 0644]
include/status_led.h
include/u-boot/rsa.h
include/ubi_uboot.h
include/usb/lin_gadget_compat.h
include/usb/udc.h
include/watchdog.h
lib/Makefile
lib/libfdt/Makefile
lib/libfdt/fdt_addresses.c [new file with mode: 0644]
lib/libfdt/fdt_rw.c
lib/libfdt/fdt_sw.c
lib/libfdt/libfdt_internal.h
lib/linux_compat.c [new file with mode: 0644]
lib/list_sort.c [new file with mode: 0644]
lib/lmb.c
lib/rbtree.c
lib/rsa/rsa-sign.c
lib/rsa/rsa-verify.c
net/bootp.c
net/bootp.h
net/net.c
scripts/Lindent [new file with mode: 0755]
scripts/Makefile.build
scripts/Makefile.extrawarn [new file with mode: 0644]
scripts/get_maintainer.pl [new file with mode: 0755]
scripts/mailmapper
scripts/mkmakefile
scripts/multiconfig.py [deleted file]
scripts/multiconfig.sh [new file with mode: 0644]
scripts/objdiff
scripts/setlocalversion
test/dfu/README [new file with mode: 0644]
test/dfu/dfu_gadget_test.sh [new file with mode: 0755]
test/dfu/dfu_gadget_test_init.sh [new file with mode: 0755]
test/image/test-fit.py
test/ums/README [new file with mode: 0644]
test/ums/ums_gadget_test.sh [new file with mode: 0755]
test/vboot/vboot_test.sh
tools/buildman/README
tools/buildman/board.py
tools/buildman/builder.py
tools/buildman/builderthread.py [new file with mode: 0644]
tools/buildman/buildman.py
tools/buildman/control.py
tools/buildman/test.py
tools/fit_info.c
tools/genboardscfg.py
tools/image-host.c
tools/mkimage.c
tools/patman/checkpatch.py
tools/patman/gitutil.py
tools/patman/patchstream.py
tools/patman/patman.py

diff --git a/CREDITS b/CREDITS
index 3e5fb7b..43d4764 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -126,7 +126,7 @@ D: Palmtreo680 board, docg4 nand flash driver
 
 N: Dave Ellis
 E: DGE@sixnetio.com
-D: EEPROM Speedup, SXNI855T port
+D: EEPROM Speedup
 
 N: Daniel Engstr?m
 E: daniel@omicron.se
diff --git a/Kconfig b/Kconfig
index 9e77a6e..cbb691e 100644 (file)
--- a/Kconfig
+++ b/Kconfig
@@ -12,13 +12,53 @@ config KCONFIG_OBJDIR
        string
        option env="KCONFIG_OBJDIR"
 
-config DEFCONFIG_LIST
-       string
+menu "General setup"
+
+config LOCALVERSION
+       string "Local version - append to U-Boot release"
        depends on !SPL_BUILD
-       option defconfig_list
-       default "configs/sandbox_defconfig"
+       help
+         Append an extra string to the end of your U-Boot version.
+         This will show up on your boot log, for example.
+         The string you set here will be appended after the contents of
+         any files with a filename matching localversion* in your
+         object and source tree, in that order.  Your total string can
+         be a maximum of 64 characters.
 
-menu "General setup"
+config LOCALVERSION_AUTO
+       bool "Automatically append version information to the version string"
+       depends on !SPL_BUILD
+       default y
+       help
+         This will try to automatically determine if the current tree is a
+         release tree by looking for git tags that belong to the current
+         top of tree revision.
+
+         A string of the format -gxxxxxxxx will be added to the localversion
+         if a git-based tree is found.  The string generated by this will be
+         appended after any matching localversion* files, and after the value
+         set in CONFIG_LOCALVERSION.
+
+         (The actual string used here is the first eight characters produced
+         by running the command:
+
+           $ git rev-parse --verify HEAD
+
+         which is done within the script "scripts/setlocalversion".)
+
+config CC_OPTIMIZE_FOR_SIZE
+       bool "Optimize for size"
+       depends on !SPL_BUILD
+       default y
+       help
+         Enabling this option will pass "-Os" instead of "-O2" to gcc
+         resulting in a smaller U-Boot image.
+
+         This option is enabled by default for U-Boot.
+
+endmenu                # General setup
+
+menu "Boot images"
 
 config SPL_BUILD
        bool
@@ -60,6 +100,6 @@ config SYS_EXTRA_OPTIONS
          configuration to Kconfig. Since this option will be removed sometime,
          new boards should not use this option.
 
-endmenu                # General setup
+endmenu                # Boot images
 
 source "arch/Kconfig"
diff --git a/MAINTAINERS b/MAINTAINERS
new file mode 100644 (file)
index 0000000..af194ca
--- /dev/null
@@ -0,0 +1,405 @@
+Descriptions of section entries:
+
+       P: Person (obsolete)
+       M: Mail patches to: FullName <address@domain>
+       L: Mailing list that is relevant to this area
+       W: Web-page with status/info
+       Q: Patchwork web based patch tracking system site
+       T: SCM tree type and location.
+          Type is one of: git, hg, quilt, stgit, topgit
+       S: Status, one of the following:
+          Supported:   Someone is actually paid to look after this.
+          Maintained:  Someone actually looks after it.
+          Odd Fixes:   It has a maintainer but they don't have time to do
+                       much other than throw the odd patch in. See below..
+          Orphan:      No current maintainer [but maybe you could take the
+                       role as you write your new code].
+          Obsolete:    Old code. Something tagged obsolete generally means
+                       it has been replaced by a better system and you
+                       should be using that.
+       F: Files and directories with wildcard patterns.
+          A trailing slash includes all files and subdirectory files.
+          F:   drivers/net/    all files in and below drivers/net
+          F:   drivers/net/*   all files in drivers/net, but not below
+          F:   */net/*         all files in "any top level directory"/net
+          One pattern per line.  Multiple F: lines acceptable.
+       N: Files and directories with regex patterns.
+          N:   [^a-z]tegra     all files whose path contains the word tegra
+          One pattern per line.  Multiple N: lines acceptable.
+          scripts/get_maintainer.pl has different behavior for files that
+          match F: pattern and matches of N: patterns.  By default,
+          get_maintainer will not look at git log history when an F: pattern
+          match occurs.  When an N: match occurs, git log history is used
+          to also notify the people that have git commit signatures.
+       X: Files and directories that are NOT maintained, same rules as F:
+          Files exclusions are tested before file matches.
+          Can be useful for excluding a specific subdirectory, for instance:
+          F:   net/
+          X:   net/ipv6/
+          matches all files in and below net excluding net/ipv6/
+       K: Keyword perl extended regex pattern to match content in a
+          patch or file.  For instance:
+          K: of_get_profile
+             matches patches or files that contain "of_get_profile"
+          K: \b(printk|pr_(info|err))\b
+             matches patches or files that contain one or more of the words
+             printk, pr_info or pr_err
+          One regex pattern per line.  Multiple K: lines acceptable.
+
+Note: For the hard of thinking, this list is meant to remain in alphabetical
+order. If you could add yourselves to it in alphabetical order that would be
+so much easier [Ed]
+
+Maintainers List (try to look for most precise areas first)
+
+               -----------------------------------
+ARC
+M:     Alexey Brodkin <alexey.brodkin@synopsys.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-arc.git
+F:     arch/arc/
+
+ARM
+M:     Albert Aribaud <albert.u.boot@aribaud.net>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-arm.git
+F:     arch/arm/
+
+ARM ATMEL AT91
+M:     Andreas Bießmann <andreas.devel@googlemail.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-atmel.git
+F:     arch/arm/cpu/armv7/at91/
+F:     arch/arm/cpu/at91-common/
+F:     arch/arm/include/asm/arch-at91/
+
+ARM FREESCALE IMX
+M:     Stefano Babic <sbabic@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-imx.git
+F:     arch/arm/cpu/arm1136/mx*/
+F:     arch/arm/cpu/arm926ejs/mx*/
+F:     arch/arm/cpu/arm926ejs/imx/
+F:     arch/arm/cpu/armv7/mx*/
+F:     arch/arm/cpu/armv7/vf610/
+F:     arch/arm/cpu/imx-common/
+F:     arch/arm/include/asm/arch-imx/
+F:     arch/arm/include/asm/arch-mx*/
+F:     arch/arm/include/asm/arch-vf610/
+F:     arch/arm/include/asm/imx-common/
+
+ARM MARVELL KIRKWOOD
+M:     Prafulla Wadaskar <prafulla@marvell.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-marvell.git
+F:     arch/arm/cpu/arm926ejs/kirkwood/
+F:     arch/arm/include/asm/arch-kirkwood/
+
+ARM MARVELL PXA
+M:     Marek Vasut <marex@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-pxa.git
+F:     arch/arm/cpu/pxa/
+F:     arch/arm/include/asm/arch-pxa/
+
+ARM SAMSUNG
+M:     Minkyu Kang <mk7.kang@samsung.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-samsung.git
+F:     arch/arm/cpu/arm920t/s3c24x0/
+F:     arch/arm/cpu/armv7/exynos/
+F:     arch/arm/cpu/armv7/s5pc1xx/
+F:     arch/arm/cpu/armv7/s5p-common/
+F:     arch/arm/include/asm/arch-exynos/
+F:     arch/arm/include/asm/arch-s3c24x0/
+F:     arch/arm/include/asm/arch-s5pc1xx/
+
+ARM STM SPEAR
+M:     Vipin Kumar <vipin.kumar@st.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-stm.git
+F:     arch/arm/cpu/arm926ejs/spear/
+F:     arch/arm/include/asm/arch-spear/
+
+ARM SUNXI
+M:     Ian Campbell <ijc@hellion.org.uk>
+M:     Hans De Goede <hdegoede@redhat.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-sunxi.git
+F:     arch/arm/cpu/armv7/sunxi/
+F:     arch/arm/include/asm/arch-sunxi/
+
+ARM TEGRA
+M:     Tom Warren <twarren@nvidia.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-tegra.git
+F:     arch/arm/cpu/arm720t/tegra*/
+F:     arch/arm/cpu/armv7/tegra*/
+F:     arch/arm/cpu/tegra*/
+F:     arch/arm/include/asm/arch-tegra*/
+
+ARM TI
+M:     Tom Rini <trini@ti.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-ti.git
+F:     arch/arm/cpu/arm926ejs/davinci/
+F:     arch/arm/cpu/arm926ejs/omap/
+F:     arch/arm/cpu/armv7/omap*/
+F:     arch/arm/include/asm/arch-davinci/
+F:     arch/arm/include/asm/arch-omap*/
+F:     arch/arm/include/asm/ti-common/
+
+ARM ZYNQ
+M:     Michal Simek <monstr@monstr.eu>
+S:     Maintained
+F:     arch/arm/cpu/armv7/zynq/
+F:     arch/arm/include/asm/arch-zynq/
+
+AVR32
+M:     Andreas Bießmann <andreas.devel@googlemail.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-avr32.git
+F:     arch/avr32/
+
+BLACKFIN
+M:     Sonic Zhang <sonic.adi@gmail.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-blackfin.git
+F:     arch/blackfin/
+
+BUILDMAN
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+F:     tools/buildman/
+
+CFI FLASH
+M:     Stefan Roese <sr@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-cfi-flash.git
+F:     drivers/mtd/*
+
+COLDFIRE
+M:     Jason Jin <jason.jin@freescale.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-coldfire.git
+F:     arch/m68k/
+
+DFU
+M:     Lukasz Majewski <l.majewski@samsung.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-dfu.git
+F:     drivers/dfu/
+
+DRIVER MODEL
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+F:     drivers/core/
+F:     include/dm/
+F:     test/dm/
+
+FLATTENED DEVICE TREE
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-fdt.git
+F:     lib/fdtdec*
+F:     lib/libfdt/
+F:     include/fdt*
+F:     include/libfdt*
+F.     common/cmd_fdt.c
+F:     common/fdt_support.c
+
+FREEBSD
+M:     Rafal Jaworowski <raj@semihalf.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-freebsd.git
+
+FREESCALE QORIQ
+M:     York Sun <yorksun@freescale.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-fsl-qoriq.git
+
+I2C
+M:     Heiko Schocher <hs@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-i2c.git
+F:     drivers/i2c/
+
+MICROBLAZE
+M:     Michal Simek <monstr@monstr.eu>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-microblaze.git
+F:     arch/microblaze/
+
+MIPS
+M:     Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mips.git
+F:     arch/mips/
+
+MMC
+M:     Pantelis Antoniou <panto.antoniou-consulting.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mmc.git
+F:     drivers/mmc/
+
+OPENRISC
+M:     Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+S:     Maintained
+F:     arch/openrisc/
+
+PATMAN
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+F:     tools/patman/
+
+POWERPC
+M:     Wolfgang Denk <wd@denx.de>
+S:     Maintained
+F:     arch/powerpc/
+
+POWERPC MPC5XXX
+M:     Wolfgang Denk <wd@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mpc5xxx.git
+F:     arch/powerpc/cpu/mpc5*/
+
+POWERPC MPC8XX
+M:     Wolfgang Denk <wd@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mpc8xx.git
+F:     arch/powerpc/cpu/mpc8xx/
+
+POWERPC MPC82XX
+M:     Wolfgang Denk <wd@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mpc82xx.git
+F:     arch/powerpc/cpu/mpc82*/
+
+POWERPC MPC83XX
+M:     Kim Phillips <kim.phillips@freescale.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mpc83xx.git
+F:     arch/powerpc/cpu/mpc83xx/
+F:     arch/powerpc/include/asm/arch-mpc83xx/
+
+POWERPC MPC85XX
+M:     York Sun <yorksun@freescale.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mpc85xx.git
+F:     arch/powerpc/cpu/mpc85xx/
+
+POWERPC MPC86XX
+M:     York Sun <yorksun@freescale.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-mpc86xx.git
+F:     arch/powerpc/cpu/mpc86xx/
+
+POWERPC PPC74XX PPC7XX
+M:     Wolfgang Denk <wd@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-74xx-7xx.git
+F:     arch/powerpc/cpu/74xx_7xx/
+
+POWERPC PPC4XX
+M:     Stefan Roese <sr@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-ppc4xx.git
+F:     arch/powerpc/cpu/ppc4xx/
+
+NETWORK
+M:     Joe Hershberger <joe.hershberger@gmail.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-net.git
+F:     drivers/net/
+
+NAND FLASH
+M:     Scott Wood <scottwood@freescale.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-nand-flash.git
+F:     drivers/mtd/nand/
+
+NDS32
+M:     Macpaul Lin <macpaul@andestech.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-nds32.git
+F:     arch/nds32/
+
+NIOS
+M:     Thomas Chou <thomas@wytron.com.tw>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-nios.git
+F:     arch/nios2/
+
+ONENAND
+M:     Lukasz Majewski <l.majewski@samsung.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-onenand.git
+F:     drivers/mtd/onenand/
+
+SANDBOX
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+F:     arch/sandbox/
+
+SH
+M:     Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-sh.git
+F:     arch/sh/
+
+SPARC
+M:     Daniel Hellstrom <daniel@gaisler.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-sparc.git
+F:     arch/sparc/
+
+SPI
+M:     Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-spi.git
+F:     drivers/mtd/spi/
+F:     drivers/spi/
+F:     include/spi*
+
+TESTING
+M:     Detlev Zundel <dzu@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-testing.git
+
+TQ GROUP
+M:     Martin Krause <martin.krause@tq-systems.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-tq-group.git
+
+UBI
+M:     Kyungmin Park <kmpark@infradead.org>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-ubi.git
+F:     drivers/mtd/ubi/
+
+USB
+M:     Marek Vasut <marex@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-usb.git
+F:     drivers/usb/
+
+VIDEO
+M:     Anatolij Gustschin <agust@denx.de>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-video.git
+F:     drivers/video/
+
+X86
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-x86.git
+F:     arch/x86/
+
+THE REST
+M:     Tom Rini <trini@ti.com>
+L:     u-boot@lists.denx.de
+Q:     http://patchwork.ozlabs.org/project/uboot/list/
+S:     Maintained
+T:     git git://git.denx.de/u-boot.git
+F:     *
+F:     */
diff --git a/MAKEALL b/MAKEALL
index 929fe88..7c16319 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -171,13 +171,10 @@ GNU_MAKE=$(scripts/show-gnu-make) || {
 # echo "Remaining arguments:"
 # for arg do echo '--> '"\`$arg'" ; done
 
-if [ ! -r boards.cfg ]; then
-       echo "Could not find boards.cfg"
-       tools/genboardscfg.py || {
-               echo "Failed to generate boards.cfg" >&2
-               exit 1
-       }
-fi
+tools/genboardscfg.py || {
+       echo "Failed to generate boards.cfg" >&2
+       exit 1
+}
 
 FILTER="\$1 !~ /^#/"
 [ "$opt_a" ] && FILTER="${FILTER} && $opt_a"
@@ -658,7 +655,7 @@ build_target() {
                MAKE="${MAKE} O=${output_dir}"
        fi
 
-       ${MAKE} distclean >/dev/null
+       ${MAKE} mrproper >/dev/null
 
        echo "Building ${target} board..."
        ${MAKE} -s ${target}_defconfig >/dev/null
index 666d291..9646859 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -109,10 +109,6 @@ ifeq ("$(origin O)", "command line")
   KBUILD_OUTPUT := $(O)
 endif
 
-ifeq ("$(origin W)", "command line")
-  export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
-endif
-
 # That's our default target when none is given on the command line
 PHONY := _all
 _all:
@@ -441,12 +437,12 @@ ifeq ($(mixed-targets),1)
 # We're called with mixed targets (*config and build targets).
 # Handle them one by one.
 
-PHONY += $(MAKECMDGOALS) build-one-by-one
+PHONY += $(MAKECMDGOALS) __build_one_by_one
 
-$(MAKECMDGOALS): build-one-by-one
+$(filter-out __build_one_by_one, $(MAKECMDGOALS)): __build_one_by_one
        @:
 
-build-one-by-one:
+__build_one_by_one:
        $(Q)set -e; \
        for i in $(MAKECMDGOALS); do \
                $(MAKE) -f $(srctree)/Makefile $$i; \
@@ -462,10 +458,10 @@ KBUILD_DEFCONFIG := sandbox_defconfig
 export KBUILD_DEFCONFIG KBUILD_KCONFIG
 
 config: scripts_basic outputmakefile FORCE
-       +$(Q)$(PYTHON) $(srctree)/scripts/multiconfig.py $@
+       (Q)$(MAKE) $(build)=scripts/kconfig $@
 
 %config: scripts_basic outputmakefile FORCE
-       +$(Q)$(PYTHON) $(srctree)/scripts/multiconfig.py $@
+       +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
 
 else
 # ===========================================================================
@@ -533,7 +529,11 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
-KBUILD_CFLAGS += -Os #-fomit-frame-pointer
+ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
+KBUILD_CFLAGS  += -Os
+else
+KBUILD_CFLAGS  += -O2
+endif
 
 ifdef BUILD_TAG
 KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
@@ -569,6 +569,8 @@ endif
 
 export CONFIG_SYS_TEXT_BASE
 
+include $(srctree)/scripts/Makefile.extrawarn
+
 # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
 KBUILD_CPPFLAGS += $(KCPPFLAGS)
 KBUILD_AFLAGS += $(KAFLAGS)
@@ -802,14 +804,15 @@ u-boot.hex u-boot.srec: u-boot FORCE
 
 OBJCOPYFLAGS_u-boot.bin := -O binary
 
-binary_size_check: u-boot.bin System.map FORCE
-       @file_size=`stat -c %s u-boot.bin` ; \
-       map_size=$(shell cat System.map | \
+binary_size_check: u-boot.bin FORCE
+       @file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
+       map_size=$(shell cat u-boot.map | \
                awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \
+               | sed 's/0X//g' \
                | bc); \
        if [ "" != "$$map_size" ]; then \
                if test $$map_size -ne $$file_size; then \
-                       echo "System.map shows a binary size of $$map_size" >&2 ; \
+                       echo "u-boot.map shows a binary size of $$map_size" >&2 ; \
                        echo "  but u-boot.bin shows $$file_size" >&2 ; \
                        exit 1; \
                fi \
@@ -1005,13 +1008,17 @@ quiet_cmd_u-boot__ ?= LD      $@
       --start-group $(u-boot-main) --end-group                 \
       $(PLATFORM_LIBS) -Map u-boot.map
 
-u-boot:        $(u-boot-init) $(u-boot-main) u-boot.lds
-       $(call if_changed,u-boot__)
-ifeq ($(CONFIG_KALLSYMS),y)
+quiet_cmd_smap = GEN     common/system_map.o
+cmd_smap = \
        smap=`$(call SYSTEM_MAP,u-boot) | \
                awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
        $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
                -c $(srctree)/common/system_map.c -o common/system_map.o
+
+u-boot:        $(u-boot-init) $(u-boot-main) u-boot.lds
+       $(call if_changed,u-boot__)
+ifeq ($(CONFIG_KALLSYMS),y)
+       $(call cmd,smap)
        $(call cmd,u-boot__) common/system_map.o
 endif
 
@@ -1286,6 +1293,7 @@ distclean: mrproper
                -o -name '.*.rej' -o -name '*%' -o -name 'core' \
                -o -name '*.pyc' \) \
                -type f -print | xargs rm -f
+       @rm -f boards.cfg
 
 backup:
        F=`basename $(srctree)` ; cd .. ; \
diff --git a/README b/README
index 5928495..517b0b4 100644 (file)
--- a/README
+++ b/README
@@ -1152,6 +1152,7 @@ The following options need to be configured:
                CONFIG_RTC_DS1307       - use Maxim, Inc. DS1307 RTC
                CONFIG_RTC_DS1337       - use Maxim, Inc. DS1337 RTC
                CONFIG_RTC_DS1338       - use Maxim, Inc. DS1338 RTC
+               CONFIG_RTC_DS1339       - use Maxim, Inc. DS1339 RTC
                CONFIG_RTC_DS164x       - use Dallas DS164x RTC
                CONFIG_RTC_ISL1208      - use Intersil ISL1208 RTC
                CONFIG_RTC_MAX6900      - use Maxim, Inc. MAX6900 RTC
@@ -2040,6 +2041,24 @@ CBFS (Coreboot Filesystem) support
                4th and following
                BOOTP requests:         delay 0 ... 8 sec
 
+               CONFIG_BOOTP_ID_CACHE_SIZE
+
+               BOOTP packets are uniquely identified using a 32-bit ID. The
+               server will copy the ID from client requests to responses and
+               U-Boot will use this to determine if it is the destination of
+               an incoming response. Some servers will check that addresses
+               aren't in use before handing them out (usually using an ARP
+               ping) and therefore take up to a few hundred milliseconds to
+               respond. Network congestion may also influence the time it
+               takes for a response to make it back to the client. If that
+               time is too long, U-Boot will retransmit requests. In order
+               to allow earlier responses to still be accepted after these
+               retransmissions, U-Boot's BOOTP client keeps a small cache of
+               IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
+               cache. The default is to keep IDs for up to four outstanding
+               requests. Increasing this will allow U-Boot to accept offers
+               from a BOOTP client in networks with unusually high latency.
+
 - DHCP Advanced Options:
                You can fine tune the DHCP functionality by defining
                CONFIG_BOOTP_* symbols:
@@ -3334,6 +3353,9 @@ FIT uImage format:
                Adds the MTD partitioning infrastructure from the Linux
                kernel. Needed for UBI support.
 
+               CONFIG_MTD_NAND_VERIFY_WRITE
+               verify if the written data is correct reread.
+
 - UBI support
                CONFIG_CMD_UBI
 
@@ -3347,6 +3369,64 @@ FIT uImage format:
                Make the verbose messages from UBI stop printing.  This leaves
                warnings and errors enabled.
 
+
+               CONFIG_MTD_UBI_WL_THRESHOLD
+               This parameter defines the maximum difference between the highest
+               erase counter value and the lowest erase counter value of eraseblocks
+               of UBI devices. When this threshold is exceeded, UBI starts performing
+               wear leveling by means of moving data from eraseblock with low erase
+               counter to eraseblocks with high erase counter.
+
+               The default value should be OK for SLC NAND flashes, NOR flashes and
+               other flashes which have eraseblock life-cycle 100000 or more.
+               However, in case of MLC NAND flashes which typically have eraseblock
+               life-cycle less than 10000, the threshold should be lessened (e.g.,
+               to 128 or 256, although it does not have to be power of 2).
+
+               default: 4096
+               
+               CONFIG_MTD_UBI_BEB_LIMIT
+               This option specifies the maximum bad physical eraseblocks UBI
+               expects on the MTD device (per 1024 eraseblocks). If the
+               underlying flash does not admit of bad eraseblocks (e.g. NOR
+               flash), this value is ignored.
+
+               NAND datasheets often specify the minimum and maximum NVM
+               (Number of Valid Blocks) for the flashes' endurance lifetime.
+               The maximum expected bad eraseblocks per 1024 eraseblocks
+               then can be calculated as "1024 * (1 - MinNVB / MaxNVB)",
+               which gives 20 for most NANDs (MaxNVB is basically the total
+               count of eraseblocks on the chip).
+
+               To put it differently, if this value is 20, UBI will try to
+               reserve about 1.9% of physical eraseblocks for bad blocks
+               handling. And that will be 1.9% of eraseblocks on the entire
+               NAND chip, not just the MTD partition UBI attaches. This means
+               that if you have, say, a NAND flash chip admits maximum 40 bad
+               eraseblocks, and it is split on two MTD partitions of the same
+               size, UBI will reserve 40 eraseblocks when attaching a
+               partition.
+
+               default: 20
+
+               CONFIG_MTD_UBI_FASTMAP
+               Fastmap is a mechanism which allows attaching an UBI device
+               in nearly constant time. Instead of scanning the whole MTD device it
+               only has to locate a checkpoint (called fastmap) on the device.
+               The on-flash fastmap contains all information needed to attach
+               the device. Using fastmap makes only sense on large devices where
+               attaching by scanning takes long. UBI will not automatically install
+               a fastmap on old images, but you can set the UBI parameter
+               CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT to 1 if you want so. Please note
+               that fastmap-enabled images are still usable with UBI implementations
+               without fastmap support. On typical flash devices the whole fastmap
+               fits into one PEB. UBI will reserve PEBs to hold two fastmaps.
+
+               CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT
+               Set this parameter to enable fastmap automatically on images
+               without a fastmap.
+               default: 0
+
 - UBIFS support
                CONFIG_CMD_UBIFS
 
@@ -4385,6 +4465,11 @@ use the "saveenv" command to store a valid environment.
                later, once stdio is running and output goes to the LCD, if
                present.
 
+- CONFIG_BOARD_SIZE_LIMIT:
+               Maximum size of the U-Boot image. When defined, the
+               build system checks that the actual size does not
+               exceed it.
+
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 
index 3f52d71..7b3805e 100644 (file)
@@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
 
+#ifdef CONFIG_CMD_NET
 
 static int dev_valid_net(void *cookie)
 {
@@ -85,3 +86,32 @@ int dev_read_net(void *cookie, void *buf, int len)
 
        return eth_receive(buf, len);
 }
+
+#else
+
+int dev_open_net(void *cookie)
+{
+       return API_ENODEV;
+}
+
+int dev_close_net(void *cookie)
+{
+       return API_ENODEV;
+}
+
+int dev_enum_net(struct device_info *di)
+{
+       return 0;
+}
+
+int dev_write_net(void *cookie, void *buf, int len)
+{
+       return API_ENODEV;
+}
+
+int dev_read_net(void *cookie, void *buf, int len)
+{
+       return API_ENODEV;
+}
+
+#endif
index f01ff8f..1794296 100644 (file)
@@ -287,9 +287,6 @@ config TARGET_SC_SPS_1
 config TARGET_NHK8815
        bool "Support nhk8815"
 
-config TARGET_OMAP5912OSK
-       bool "Support omap5912osk"
-
 config TARGET_EDMINIV2
        bool "Support edminiv2"
 
@@ -985,7 +982,6 @@ source "board/ti/beagle/Kconfig"
 source "board/ti/dra7xx/Kconfig"
 source "board/ti/evm/Kconfig"
 source "board/ti/ks2_evm/Kconfig"
-source "board/ti/omap5912osk/Kconfig"
 source "board/ti/omap5_uevm/Kconfig"
 source "board/ti/panda/Kconfig"
 source "board/ti/sdp3430/Kconfig"
index 0f1ceec..584f742 100644 (file)
 #define CPU_CFG_CHIP_REV_B 0x3
 
 /*
- * Wait up to 1s for mask to be clear in given reg.
+ * Wait up to 1s for value to be set in given part of reg.
  */
-static void await_completion(u32 *reg, u32 mask)
+static void await_completion(u32 *reg, u32 mask, u32 val)
 {
        unsigned long tmo = timer_get_us() + 1000000;
 
-       while (readl(reg) & mask) {
+       while ((readl(reg) & mask) != val) {
                if (timer_get_us() > tmo)
                        panic("Timeout initialising DRAM\n");
        }
 }
 
+/*
+ * Wait up to 1s for mask to be clear in given reg.
+ */
+static inline void await_bits_clear(u32 *reg, u32 mask)
+{
+       await_completion(reg, mask, 0);
+}
+
+/*
+ * Wait up to 1s for mask to be set in given reg.
+ */
+static inline void await_bits_set(u32 *reg, u32 mask)
+{
+       await_completion(reg, mask, mask);
+}
+
+/*
+ * This performs the external DRAM reset by driving the RESET pin low and
+ * then high again. According to the DDR3 spec, the RESET pin needs to be
+ * kept low for at least 200 us.
+ */
 static void mctl_ddr3_reset(void)
 {
        struct sunxi_dram_reg *dram =
@@ -64,15 +85,28 @@ static void mctl_ddr3_reset(void)
        if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
            CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
                setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-               udelay(2);
+               udelay(200);
                clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
        } else
 #endif
        {
                clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-               udelay(2);
+               udelay(200);
                setbits_le32(&dram->mcr, DRAM_MCR_RESET);
        }
+       /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
+        * for additional 500 us before driving the CKE pin (Clock Enable)
+        * high. The duration of this delay can be configured in the SDR_IDCR
+        * (Initialization Delay Configuration Register) and applied
+        * automatically by the DRAM controller during the DDR3 initialization
+        * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
+        * can't provide sufficient delay at DRAM clock frequencies higher than
+        * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
+        * 533 MHz according to the datasheet). Additionally, there is no
+        * official documentation for the SDR_IDCR register anywhere, and
+        * there is always a chance that we are interpreting it wrong.
+        * Better be safe than sorry, so add an explicit delay here. */
+       udelay(500);
 }
 
 static void mctl_set_drive(void)
@@ -102,6 +136,14 @@ static void mctl_itm_enable(void)
        clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
 }
 
+static void mctl_itm_reset(void)
+{
+       mctl_itm_disable();
+       udelay(1); /* ITM reset needs a bit of delay */
+       mctl_itm_enable();
+       udelay(1);
+}
+
 static void mctl_enable_dll0(u32 phase)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -118,23 +160,28 @@ static void mctl_enable_dll0(u32 phase)
        udelay(22);
 }
 
+/* Get the number of DDR byte lanes */
+static u32 mctl_get_number_of_lanes(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
+                               DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
+               return 4;
+       else
+               return 2;
+}
+
 /*
  * Note: This differs from pm/standby in that it checks the bus width
  */
 static void mctl_enable_dllx(u32 phase)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-       u32 i, n, bus_width;
+       u32 i, number_of_lanes;
 
-       bus_width = readl(&dram->dcr);
+       number_of_lanes = mctl_get_number_of_lanes();
 
-       if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
-           DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
-               n = DRAM_DCR_NR_DLLCR_32BIT;
-       else
-               n = DRAM_DCR_NR_DLLCR_16BIT;
-
-       for (i = 1; i < n; i++) {
+       for (i = 1; i <= number_of_lanes; i++) {
                clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
                                (phase & 0xf) << 14);
                clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
@@ -143,12 +190,12 @@ static void mctl_enable_dllx(u32 phase)
        }
        udelay(2);
 
-       for (i = 1; i < n; i++)
+       for (i = 1; i <= number_of_lanes; i++)
                clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
                             DRAM_DLLCR_DISABLE);
        udelay(22);
 
-       for (i = 1; i < n; i++)
+       for (i = 1; i <= number_of_lanes; i++)
                clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
                                DRAM_DLLCR_NRESET);
        udelay(22);
@@ -201,11 +248,20 @@ static void mctl_configure_hostport(void)
                writel(hpcr_value[i], &dram->hpcr[i]);
 }
 
-static void mctl_setup_dram_clock(u32 clk)
+static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 {
        u32 reg_val;
        struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+       /* PLL5P and PLL6 are the potential clock sources for MBUS */
+       u32 pll6x_div, pll5p_div;
+       u32 pll6x_clk = clock_get_pll6() / 1000000;
+       u32 pll5p_clk = clk / 24 * 48;
+       u32 pll5p_rate, pll6x_rate;
+#ifdef CONFIG_SUN7I
+       pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+
        /* setup DRAM PLL */
        reg_val = readl(&ccm->pll5_cfg);
        reg_val &= ~CCM_PLL5_CTRL_M_MASK;               /* set M to 0 (x1) */
@@ -213,41 +269,40 @@ static void mctl_setup_dram_clock(u32 clk)
        reg_val &= ~CCM_PLL5_CTRL_N_MASK;               /* set N to 0 (x0) */
        reg_val &= ~CCM_PLL5_CTRL_P_MASK;               /* set P to 0 (x1) */
        if (clk >= 540 && clk < 552) {
-               /* dram = 540MHz, pll5p = 540MHz */
+               /* dram = 540MHz, pll5p = 1080MHz */
+               pll5p_clk = 1080;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
-               reg_val |= CCM_PLL5_CTRL_P(1);
        } else if (clk >= 512 && clk < 528) {
-               /* dram = 512MHz, pll5p = 384MHz */
+               /* dram = 512MHz, pll5p = 1536MHz */
+               pll5p_clk = 1536;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
-               reg_val |= CCM_PLL5_CTRL_P(2);
        } else if (clk >= 496 && clk < 504) {
-               /* dram = 496MHz, pll5p = 372MHz */
+               /* dram = 496MHz, pll5p = 1488MHz */
+               pll5p_clk = 1488;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
-               reg_val |= CCM_PLL5_CTRL_P(2);
        } else if (clk >= 468 && clk < 480) {
-               /* dram = 468MHz, pll5p = 468MHz */
+               /* dram = 468MHz, pll5p = 936MHz */
+               pll5p_clk = 936;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
-               reg_val |= CCM_PLL5_CTRL_P(1);
        } else if (clk >= 396 && clk < 408) {
-               /* dram = 396MHz, pll5p = 396MHz */
+               /* dram = 396MHz, pll5p = 792MHz */
+               pll5p_clk = 792;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
-               reg_val |= CCM_PLL5_CTRL_P(1);
        } else  {
                /* any other frequency that is a multiple of 24 */
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
-               reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
        }
        reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;             /* PLL VCO Gain off */
        reg_val |= CCM_PLL5_CTRL_EN;                    /* PLL On */
@@ -264,20 +319,30 @@ static void mctl_setup_dram_clock(u32 clk)
        clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
 #endif
 
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
        /* setup MBUS clock */
-       reg_val = CCM_MBUS_CTRL_GATE |
-#ifdef CONFIG_SUN7I
-                 CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
-                 CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
-                 CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
-#else /* defined(CONFIG_SUN5I) */
-                 CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
-                 CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
-                 CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
-#endif
+       if (!mbus_clk)
+               mbus_clk = 300;
+       pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
+       pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
+       pll6x_rate = pll6x_clk / pll6x_div;
+       pll5p_rate = pll5p_clk / pll5p_div;
+
+       if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) {
+               /* use PLL6 as the MBUS clock source */
+               reg_val = CCM_MBUS_CTRL_GATE |
+                         CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
+                         CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+                         CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div));
+       } else if (pll5p_div <= 16) {
+               /* use PLL5P as the MBUS clock source */
+               reg_val = CCM_MBUS_CTRL_GATE |
+                         CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+                         CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+                         CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div));
+       } else {
+               panic("Bad mbus_clk\n");
+       }
        writel(reg_val, &ccm->mbus_clk_cfg);
-#endif
 
        /*
         * open DRAMC AHB & DLL register clock
@@ -299,19 +364,48 @@ static void mctl_setup_dram_clock(u32 clk)
        udelay(22);
 }
 
+/*
+ * The data from rslrX and rdgrX registers (X=rank) is stored
+ * in a single 32-bit value using the following format:
+ *   bits [31:26] - DQS gating system latency for byte lane 3
+ *   bits [25:24] - DQS gating phase select for byte lane 3
+ *   bits [23:18] - DQS gating system latency for byte lane 2
+ *   bits [17:16] - DQS gating phase select for byte lane 2
+ *   bits [15:10] - DQS gating system latency for byte lane 1
+ *   bits [ 9:8 ] - DQS gating phase select for byte lane 1
+ *   bits [ 7:2 ] - DQS gating system latency for byte lane 0
+ *   bits [ 1:0 ] - DQS gating phase select for byte lane 0
+ */
+static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 lane, number_of_lanes = mctl_get_number_of_lanes();
+       /* rank0 gating system latency (3 bits per lane: cycles) */
+       u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);
+       /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
+       u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
+       for (lane = 0; lane < number_of_lanes; lane++) {
+               u32 tmp = dqs_gating_delay >> (lane * 8);
+               slr &= ~(7 << (lane * 3));
+               slr |= ((tmp >> 2) & 7) << (lane * 3);
+               dgr &= ~(3 << (lane * 2));
+               dgr |= (tmp & 3) << (lane * 2);
+       }
+       writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);
+       writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
+}
+
 static int dramc_scan_readpipe(void)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
        u32 reg_val;
 
        /* data training trigger */
-#ifdef CONFIG_SUN7I
        clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
-#endif
        setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 
        /* check whether data training process has completed */
-       await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+       await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 
        /* check data training result */
        reg_val = readl(&dram->csr);
@@ -321,117 +415,6 @@ static int dramc_scan_readpipe(void)
        return 0;
 }
 
-static int dramc_scan_dll_para(void)
-{
-       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-       const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
-       const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
-                                0x02, 0x01, 0x00, 0x08, 0x10,
-                                0x18, 0x20, 0x28, 0x30, 0x38};
-       u32 clk_dqs_count[15];
-       u32 dqs_i, clk_i, cr_i;
-       u32 max_val, min_val;
-       u32 dqs_index, clk_index;
-
-       /* Find DQS_DLY Pass Count for every CLK_DLY */
-       for (clk_i = 0; clk_i < 15; clk_i++) {
-               clk_dqs_count[clk_i] = 0;
-               clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
-                               (clk_dly[clk_i] & 0x3f) << 6);
-               for (dqs_i = 0; dqs_i < 7; dqs_i++) {
-                       for (cr_i = 1; cr_i < 5; cr_i++) {
-                               clrsetbits_le32(&dram->dllcr[cr_i],
-                                               0x4f << 14,
-                                               (dqs_dly[dqs_i] & 0x4f) << 14);
-                       }
-                       udelay(2);
-                       if (dramc_scan_readpipe() == 0)
-                               clk_dqs_count[clk_i]++;
-               }
-       }
-       /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
-       for (dqs_i = 15; dqs_i > 0; dqs_i--) {
-               max_val = 15;
-               min_val = 15;
-               for (clk_i = 0; clk_i < 15; clk_i++) {
-                       if (clk_dqs_count[clk_i] == dqs_i) {
-                               max_val = clk_i;
-                               if (min_val == 15)
-                                       min_val = clk_i;
-                       }
-               }
-               if (max_val < 15)
-                       break;
-       }
-
-       /* Check if Find a CLK_DLY failed */
-       if (!dqs_i)
-               goto fail;
-
-       /* Find the middle index of CLK_DLY */
-       clk_index = (max_val + min_val) >> 1;
-       if ((max_val == (15 - 1)) && (min_val > 0))
-               /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
-                * value can be more close to the max_val
-                */
-               clk_index = (15 + clk_index) >> 1;
-       else if ((max_val < (15 - 1)) && (min_val == 0))
-               /* if CLK_DLY[0] is very good, then the middle value can be more
-                * close to the min_val
-                */
-               clk_index >>= 1;
-       if (clk_dqs_count[clk_index] < dqs_i)
-               clk_index = min_val;
-
-       /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
-        * read pipe again
-        */
-       clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
-                       (clk_dly[clk_index] & 0x3f) << 6);
-       max_val = 7;
-       min_val = 7;
-       for (dqs_i = 0; dqs_i < 7; dqs_i++) {
-               clk_dqs_count[dqs_i] = 0;
-               for (cr_i = 1; cr_i < 5; cr_i++) {
-                       clrsetbits_le32(&dram->dllcr[cr_i],
-                                       0x4f << 14,
-                                       (dqs_dly[dqs_i] & 0x4f) << 14);
-               }
-               udelay(2);
-               if (dramc_scan_readpipe() == 0) {
-                       clk_dqs_count[dqs_i] = 1;
-                       max_val = dqs_i;
-                       if (min_val == 7)
-                               min_val = dqs_i;
-               }
-       }
-
-       if (max_val < 7) {
-               dqs_index = (max_val + min_val) >> 1;
-               if ((max_val == (7-1)) && (min_val > 0))
-                       dqs_index = (7 + dqs_index) >> 1;
-               else if ((max_val < (7-1)) && (min_val == 0))
-                       dqs_index >>= 1;
-               if (!clk_dqs_count[dqs_index])
-                       dqs_index = min_val;
-               for (cr_i = 1; cr_i < 5; cr_i++) {
-                       clrsetbits_le32(&dram->dllcr[cr_i],
-                                       0x4f << 14,
-                                       (dqs_dly[dqs_index] & 0x4f) << 14);
-               }
-               udelay(2);
-               return dramc_scan_readpipe();
-       }
-
-fail:
-       clrbits_le32(&dram->dllcr[0], 0x3f << 6);
-       for (cr_i = 1; cr_i < 5; cr_i++)
-               clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
-       udelay(2);
-
-       return dramc_scan_readpipe();
-}
-
 static void dramc_clock_output_en(u32 on)
 {
 #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
@@ -451,48 +434,164 @@ static void dramc_clock_output_en(u32 on)
 #endif
 }
 
-static const u16 tRFC_table[2][6] = {
-       /*       256Mb    512Mb    1Gb      2Gb      4Gb      8Gb      */
-       /* DDR2  75ns     105ns    127.5ns  195ns    327.5ns  invalid  */
-       {        77,      108,     131,     200,     336,     336 },
-       /* DDR3  invalid  90ns     110ns    160ns    300ns    350ns    */
-       {        93,      93,      113,     164,     308,     359 }
+/* tRFC in nanoseconds for different densities (from the DDR3 spec) */
+static const u16 tRFC_DDR3_table[6] = {
+       /* 256Mb    512Mb    1Gb      2Gb      4Gb      8Gb */
+          90,      90,      110,     160,     300,     350
 };
 
-static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
+static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
        u32 tRFC, tREFI;
 
-       tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
+       tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
        tREFI = (7987 * clk) >> 10;     /* <= 7.8us */
 
        writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
 }
 
-unsigned long dramc_init(struct dram_para *para)
+/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
+static u32 ddr3_write_recovery(u32 clk)
+{
+       u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
+       u32 twr_ck = (twr_ns * clk + 999) / 1000;
+       if (twr_ck < 5)
+               return 1;
+       else if (twr_ck <= 8)
+               return twr_ck - 4;
+       else if (twr_ck <= 10)
+               return 5;
+       else
+               return 6;
+}
+
+/*
+ * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
+ * means that DRAM is currently in self-refresh mode and retaining the old
+ * data. Since we have no idea what to do in this situation yet, just set this
+ * register to 0 and initialize DRAM in the same way as on any normal reboot
+ * (discarding whatever was stored there).
+ *
+ * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
+ * value for this write operation to have any effect. On sun5i hadware this
+ * magic value is not necessary. And on sun4i hardware the writes to this
+ * register seem to have no effect at all.
+ */
+static void mctl_disable_power_save(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       writel(0x16510000, &dram->ppwrsctl);
+}
+
+/*
+ * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
+ * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
+ * (SDR_IDCR) register appears to configure this delay, which gets applied
+ * right at the time when the DRAM initialization is activated in the
+ * 'mctl_ddr3_initialize' function.
+ */
+static void mctl_set_cke_delay(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       /* The CKE delay is represented in DRAM clock cycles, multiplied by N
+        * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
+        * the maximum possible value 0x1ffff, just like in the Allwinner's
+        * boot0 bootloader. The resulting delay value is somewhere between
+        * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
+        * with 360 MHz DRAM clock speed). */
+       setbits_le32(&dram->idcr, 0x1ffff);
+}
+
+/*
+ * This triggers the DRAM initialization. It performs sending the mode registers
+ * to the DRAM among other things. Very likely the ZQCL command is also getting
+ * executed (to do the initial impedance calibration on the DRAM side of the
+ * wire). The memory controller and the PHY must be already configured before
+ * calling this function.
+ */
+static void mctl_ddr3_initialize(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       setbits_le32(&dram->ccr, DRAM_CCR_INIT);
+       await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
+}
+
+/*
+ * Perform impedance calibration on the DRAM controller side of the wire.
+ */
+static void mctl_set_impedance(u32 zq, u32 odt_en)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 reg_val;
+       u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
+
+#ifndef CONFIG_SUN7I
+       /* Appears that some kind of automatically initiated default
+        * ZQ calibration is already in progress at this point on sun4i/sun5i
+        * hardware, but not on sun7i. So it is reasonable to wait for its
+        * completion before doing anything else. */
+       await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
+#endif
+
+       /* ZQ calibration is not really useful unless ODT is enabled */
+       if (!odt_en)
+               return;
+
+#ifdef CONFIG_SUN7I
+       /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
+        * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
+        * SDR_ZQCR1 register, but there are hints indicating that it might
+        * be related to periodic impedance re-calibration. This particular
+        * magic value is borrowed from the Allwinner boot0 bootloader, and
+        * using it helps to avoid troubles */
+       writel((1 << 24) | (1 << 1), &dram->zqcr1);
+#endif
+
+       /* Needed at least for sun5i, because it does not self clear there */
+       clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
+
+       if (zdata) {
+               /* Set the user supplied impedance data */
+               reg_val = DRAM_ZQCR0_ZDEN | zdata;
+               writel(reg_val, &dram->zqcr0);
+               /* no need to wait, this takes effect immediately */
+       } else {
+               /* Do the calibration using the external resistor */
+               reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
+               writel(reg_val, &dram->zqcr0);
+               /* Wait for the new impedance configuration to settle */
+               await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
+       }
+
+       /* Needed at least for sun5i, because it does not self clear there */
+       clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
+
+       /* Set I/O configure register */
+       writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr);
+}
+
+static unsigned long dramc_init_helper(struct dram_para *para)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
        u32 reg_val;
        u32 density;
        int ret_val;
 
-       /* check input dram parameter structure */
-       if (!para)
+       /*
+        * only single rank DDR3 is supported by this code even though the
+        * hardware can theoretically support DDR2 and up to two ranks
+        */
+       if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
                return 0;
 
        /* setup DRAM relative clock */
-       mctl_setup_dram_clock(para->clock);
+       mctl_setup_dram_clock(para->clock, para->mbus_clock);
 
-#ifdef CONFIG_SUN5I
        /* Disable any pad power save control */
-       writel(0, &dram->ppwrsctl);
-#endif
+       mctl_disable_power_save();
 
-       /* reset external DRAM */
-#ifndef CONFIG_SUN7I
-       mctl_ddr3_reset();
-#endif
        mctl_set_drive();
 
        /* dram clock off */
@@ -507,9 +606,7 @@ unsigned long dramc_init(struct dram_para *para)
        mctl_enable_dll0(para->tpr3);
 
        /* configure external DRAM */
-       reg_val = 0x0;
-       if (para->type == DRAM_MEMORY_TYPE_DDR3)
-               reg_val |= DRAM_DCR_TYPE_DDR3;
+       reg_val = DRAM_DCR_TYPE_DDR3;
        reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
 
        if (para->density == 256)
@@ -534,85 +631,41 @@ unsigned long dramc_init(struct dram_para *para)
        reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
        writel(reg_val, &dram->dcr);
 
-#ifdef CONFIG_SUN7I
-       setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
-       if (para->tpr4 & 0x2)
-               clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
        dramc_clock_output_en(1);
-#endif
 
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
-       /* set odt impendance divide ratio */
-       reg_val = ((para->zq) >> 8) & 0xfffff;
-       reg_val |= ((para->zq) & 0xff) << 20;
-       reg_val |= (para->zq) & 0xf0000000;
-       writel(reg_val, &dram->zqcr0);
-#endif
+       mctl_set_impedance(para->zq, para->odt_en);
 
-#ifdef CONFIG_SUN7I
-       /* Set CKE Delay to about 1ms */
-       setbits_le32(&dram->idcr, 0x1ffff);
-#endif
+       mctl_set_cke_delay();
 
-#ifdef CONFIG_SUN7I
-       if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
-               mctl_ddr3_reset();
-       else
-               setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-#else
-       /* dram clock on */
-       dramc_clock_output_en(1);
-#endif
+       mctl_ddr3_reset();
 
        udelay(1);
 
-       await_completion(&dram->ccr, DRAM_CCR_INIT);
+       await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
 
        mctl_enable_dllx(para->tpr3);
 
-#ifdef CONFIG_SUN4I
-       /* set odt impedance divide ratio */
-       reg_val = ((para->zq) >> 8) & 0xfffff;
-       reg_val |= ((para->zq) & 0xff) << 20;
-       reg_val |= (para->zq) & 0xf0000000;
-       writel(reg_val, &dram->zqcr0);
-#endif
-
-#ifdef CONFIG_SUN4I
-       /* set I/O configure register */
-       reg_val = 0x00cc0000;
-       reg_val |= (para->odt_en) & 0x3;
-       reg_val |= ((para->odt_en) & 0x3) << 30;
-       writel(reg_val, &dram->iocr);
-#endif
-
        /* set refresh period */
-       dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
+       dramc_set_autorefresh_cycle(para->clock, density);
 
        /* set timing parameters */
        writel(para->tpr0, &dram->tpr0);
        writel(para->tpr1, &dram->tpr1);
        writel(para->tpr2, &dram->tpr2);
 
-       if (para->type == DRAM_MEMORY_TYPE_DDR3) {
-               reg_val = DRAM_MR_BURST_LENGTH(0x0);
+       reg_val = DRAM_MR_BURST_LENGTH(0x0);
 #if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
-               reg_val |= DRAM_MR_POWER_DOWN;
+       reg_val |= DRAM_MR_POWER_DOWN;
 #endif
-               reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
-               reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
-       } else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
-               reg_val = DRAM_MR_BURST_LENGTH(0x2);
-               reg_val |= DRAM_MR_CAS_LAT(para->cas);
-               reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
-       }
+       reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
+       reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
        writel(reg_val, &dram->mr);
 
        writel(para->emr1, &dram->emr);
        writel(para->emr2, &dram->emr2);
        writel(para->emr3, &dram->emr3);
 
-       /* set DQS window mode */
+       /* disable drift compensation and set passive DQS window mode */
        clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
 
 #ifdef CONFIG_SUN7I
@@ -620,70 +673,78 @@ unsigned long dramc_init(struct dram_para *para)
        if (para->tpr4 & 0x1)
                setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
 #endif
-       /* reset external DRAM */
-       setbits_le32(&dram->ccr, DRAM_CCR_INIT);
-       await_completion(&dram->ccr, DRAM_CCR_INIT);
+       /* initialize external DRAM */
+       mctl_ddr3_initialize();
 
-#ifdef CONFIG_SUN7I
-       /* setup zq calibration manual */
-       reg_val = readl(&dram->ppwrsctl);
-       if ((reg_val & 0x1) == 1) {
-               /* super_standby_flag = 1 */
-
-               reg_val = readl(0x01c20c00 + 0x120); /* rtc */
-               reg_val &= 0x000fffff;
-               reg_val |= 0x17b00000;
-               writel(reg_val, &dram->zqcr0);
+       /* scan read pipe value */
+       mctl_itm_enable();
 
-               /* exit self-refresh state */
-               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
-               /* check whether command has been executed */
-               await_completion(&dram->dcr, 0x1 << 31);
+       /* Hardware DQS gate training */
+       ret_val = dramc_scan_readpipe();
 
-               udelay(2);
+       if (ret_val < 0)
+               return 0;
 
-               /* dram pad hold off */
-               setbits_le32(&dram->ppwrsctl, 0x16510000);
+       /* allow to override the DQS training results with a custom delay */
+       if (para->dqs_gating_delay)
+               mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
 
-               await_completion(&dram->ppwrsctl, 0x1);
+       /* set the DQS gating window type */
+       if (para->active_windowing)
+               clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
+       else
+               setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
 
-               /* exit self-refresh state */
-               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
+       mctl_itm_reset();
 
-               /* check whether command has been executed */
-               await_completion(&dram->dcr, 0x1 << 31);
+       /* configure all host port */
+       mctl_configure_hostport();
 
-               udelay(2);
+       return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+}
 
-               /* issue a refresh command */
-               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
-               await_completion(&dram->dcr, 0x1 << 31);
+unsigned long dramc_init(struct dram_para *para)
+{
+       unsigned long dram_size, actual_density;
 
-               udelay(2);
-       }
+       /* If the dram configuration is not provided, use a default */
+       if (!para)
+               return 0;
+
+       /* if everything is known, then autodetection is not necessary */
+       if (para->io_width && para->bus_width && para->density)
+               return dramc_init_helper(para);
+
+       /* try to autodetect the DRAM bus width and density */
+       para->io_width  = 16;
+       para->bus_width = 32;
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+       /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
+       para->density = 4096;
+#else
+       /* all A0-A15 address lines on A20, which allow density 8192 */
+       para->density = 8192;
 #endif
 
-       /* scan read pipe value */
-       mctl_itm_enable();
-       if (para->tpr3 & (0x1 << 31)) {
-               ret_val = dramc_scan_dll_para();
-               if (ret_val == 0)
-                       para->tpr3 =
-                               (((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
-                               (((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
-                               (((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
-                               (((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
-                               (((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
-                               );
-       } else {
-               ret_val = dramc_scan_readpipe();
+       dram_size = dramc_init_helper(para);
+       if (!dram_size) {
+               /* if 32-bit bus width failed, try 16-bit bus width instead */
+               para->bus_width = 16;
+               dram_size = dramc_init_helper(para);
+               if (!dram_size) {
+                       /* if 16-bit bus width also failed, then bail out */
+                       return dram_size;
+               }
        }
 
-       if (ret_val < 0)
-               return 0;
+       /* check if we need to adjust the density */
+       actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
 
-       /* configure all host port */
-       mctl_configure_hostport();
+       if (actual_density != para->density) {
+               /* update the density and re-initialize DRAM again */
+               para->density = actual_density;
+               dram_size = dramc_init_helper(para);
+       }
 
-       return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+       return dram_size;
 }
index 67fbfad..1945f75 100644 (file)
@@ -69,6 +69,7 @@ struct sunxi_dram_reg {
 
 struct dram_para {
        u32 clock;
+       u32 mbus_clock;
        u32 type;
        u32 rank_num;
        u32 density;
@@ -87,6 +88,8 @@ struct dram_para {
        u32 emr1;
        u32 emr2;
        u32 emr3;
+       u32 dqs_gating_delay;
+       u32 active_windowing;
 };
 
 #define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
@@ -121,9 +124,6 @@ struct dram_para {
 #define DRAM_DCR_BUS_WIDTH_32BIT 0x3
 #define DRAM_DCR_BUS_WIDTH_16BIT 0x1
 #define DRAM_DCR_BUS_WIDTH_8BIT 0x0
-#define DRAM_DCR_NR_DLLCR_32BIT 5
-#define DRAM_DCR_NR_DLLCR_16BIT 3
-#define DRAM_DCR_NR_DLLCR_8BIT 2
 #define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
 #define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
 #define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
@@ -132,7 +132,9 @@ struct dram_para {
 #define DRAM_DCR_MODE_SEQ 0x0
 #define DRAM_DCR_MODE_INTERLEAVE 0x1
 
-#define DRAM_CSR_FAILED (0x1 << 20)
+#define DRAM_CSR_DTERR  (0x1 << 20)
+#define DRAM_CSR_DTIERR (0x1 << 21)
+#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
 
 #define DRAM_DRR_TRFC(n) ((n) & 0xff)
 #define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
@@ -159,6 +161,10 @@ struct dram_para {
 
 #define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
 #define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
+#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
+#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
+
+#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
 
 #define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
 #define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
index b8d6bdc..2fe5776 100644 (file)
@@ -878,7 +878,6 @@ struct dmm_lisa_map_regs {
        ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
        ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
                        & EMIF_REG_LP_MODE_MASK) |\
        ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
@@ -889,8 +888,6 @@ struct dmm_lisa_map_regs {
                        & EMIF_REG_CS_TIM_SHDW_MASK) |\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
                        & EMIF_REG_SR_TIM_SHDW_MASK) |\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
-                       & EMIF_REG_PD_TIM_SHDW_MASK) |\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
                        & EMIF_REG_PD_TIM_SHDW_MASK))
 
index 7b17b75..584b38b 100644 (file)
@@ -20,6 +20,9 @@ CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%))
 endif
 CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%))
 
+# Support generic board on Blackfin
+__HAVE_ARCH_GENERIC_BOARD := y
+
 PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
 
 LDFLAGS_FINAL += --gc-sections
index 2409c30..b7f1188 100644 (file)
 
 #include <common.h>
 #include <command.h>
+#include <serial.h>
+#include <version.h>
+#include <i2c.h>
+
 #include <asm/blackfin.h>
 #include <asm/cplb.h>
+#include <asm/clock.h>
 #include <asm/mach-common/bits/core.h>
 #include <asm/mach-common/bits/ebiu.h>
 #include <asm/mach-common/bits/trace.h>
-#include <asm/serial.h>
 
 #include "cpu.h"
 #include "initcode.h"
 
 ulong bfin_poweron_retx;
+DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
 void bfin_core1_start(void)
@@ -48,6 +53,252 @@ void bfin_core1_start(void)
 }
 #endif
 
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+       serial_puts("Early: ");
+       serial_puts(s);
+#endif
+}
+
+static int global_board_data_init(void)
+{
+#ifndef CONFIG_SYS_GBL_DATA_ADDR
+# define CONFIG_SYS_GBL_DATA_ADDR 0
+#endif
+#ifndef CONFIG_SYS_BD_INFO_ADDR
+# define CONFIG_SYS_BD_INFO_ADDR 0
+#endif
+
+       bd_t *bd;
+
+       if (CONFIG_SYS_GBL_DATA_ADDR) {
+               gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR);
+               memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+       } else {
+               static gd_t _bfin_gd;
+               gd = &_bfin_gd;
+       }
+       if (CONFIG_SYS_BD_INFO_ADDR) {
+               bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR);
+               memset(bd, 0, GENERATED_BD_INFO_SIZE);
+       } else {
+               static bd_t _bfin_bd;
+               bd = &_bfin_bd;
+       }
+
+       gd->bd = bd;
+
+       bd->bi_r_version = version_string;
+       bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
+       bd->bi_board_name = CONFIG_SYS_BOARD;
+       bd->bi_vco = get_vco();
+       bd->bi_cclk = get_cclk();
+       bd->bi_sclk = get_sclk();
+       bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+       bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+
+       gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE;
+
+       return 0;
+}
+
+static void display_global_data(void)
+{
+       bd_t *bd;
+
+#ifndef CONFIG_DEBUG_EARLY_SERIAL
+       return;
+#endif
+
+       bd = gd->bd;
+       printf(" gd: %p\n", gd);
+       printf(" |-flags: %lx\n", gd->flags);
+       printf(" |-board_type: %lx\n", gd->arch.board_type);
+       printf(" |-baudrate: %u\n", gd->baudrate);
+       printf(" |-have_console: %lx\n", gd->have_console);
+       printf(" |-ram_size: %lx\n", gd->ram_size);
+       printf(" |-env_addr: %lx\n", gd->env_addr);
+       printf(" |-env_valid: %lx\n", gd->env_valid);
+       printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
+       printf(" \\-bd: %p\n", gd->bd);
+       printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
+       printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
+       printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
+       printf("   |-bi_flashstart: %lx\n", bd->bi_flashstart);
+       printf("   |-bi_flashsize: %lx\n", bd->bi_flashsize);
+       printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
+}
+
+#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
+#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
+#if defined(__ADSPBF60x__)
+#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
+#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
+#else
+#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
+#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
+#endif
+void init_cplbtables(void)
+{
+       uint32_t *ICPLB_ADDR, *ICPLB_DATA;
+       uint32_t *DCPLB_ADDR, *DCPLB_DATA;
+       uint32_t extern_memory;
+       size_t i;
+
+       void icplb_add(uint32_t addr, uint32_t data)
+       {
+               bfin_write32(ICPLB_ADDR + i, addr);
+               bfin_write32(ICPLB_DATA + i, data);
+       }
+       void dcplb_add(uint32_t addr, uint32_t data)
+       {
+               bfin_write32(DCPLB_ADDR + i, addr);
+               bfin_write32(DCPLB_DATA + i, data);
+       }
+
+       /* populate a few common entries ... we'll let
+        * the memory map and cplb exception handler do
+        * the rest of the work.
+        */
+       i = 0;
+       ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
+       ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
+       DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
+       DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
+
+       icplb_add(0xFFA00000, L1_IMEMORY);
+       dcplb_add(0xFF800000, L1_DMEMORY);
+       ++i;
+#if defined(__ADSPBF60x__)
+       icplb_add(0x0, 0x0);
+       dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
+               CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
+       ++i;
+#endif
+
+       if (CONFIG_MEM_SIZE) {
+               uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
+               uint32_t mend  = mbase + CONFIG_SYS_MONITOR_LEN - 1;
+               mbase &= CPLB_PAGE_MASK;
+               mend &= CPLB_PAGE_MASK;
+
+               icplb_add(mbase, SDRAM_IKERNEL);
+               dcplb_add(mbase, SDRAM_DKERNEL);
+               ++i;
+
+               /*
+                * If the monitor crosses a 4 meg boundary, we'll need
+                * to lock two entries for it.  We assume it doesn't
+                * cross two 4 meg boundaries ...
+                */
+               if (mbase != mend) {
+                       icplb_add(mend, SDRAM_IKERNEL);
+                       dcplb_add(mend, SDRAM_DKERNEL);
+                       ++i;
+               }
+       }
+
+#ifndef __ADSPBF60x__
+       icplb_add(0x20000000, SDRAM_INON_CHBL);
+       dcplb_add(0x20000000, SDRAM_EBIU);
+       ++i;
+#endif
+
+       /* Add entries for the rest of external RAM up to the bootrom */
+       extern_memory = 0;
+
+#ifdef CONFIG_DEBUG_NULL_PTR
+       icplb_add(extern_memory,
+                 (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
+       dcplb_add(extern_memory,
+                 (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
+       ++i;
+       icplb_add(extern_memory, SDRAM_IKERNEL);
+       dcplb_add(extern_memory, SDRAM_DKERNEL);
+       extern_memory += CPLB_PAGE_SIZE;
+       ++i;
+#endif
+
+       while (i < 16 && extern_memory <
+               (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
+               icplb_add(extern_memory, SDRAM_IGENERIC);
+               dcplb_add(extern_memory, SDRAM_DGENERIC);
+               extern_memory += CPLB_EX_PAGE_SIZE;
+               ++i;
+       }
+       while (i < 16) {
+               icplb_add(0, 0);
+               dcplb_add(0, 0);
+               ++i;
+       }
+}
+
+int print_cpuinfo(void)
+{
+       char buf[32];
+
+       printf("CPU:   ADSP %s (Detected Rev: 0.%d) (%s boot)\n",
+              gd->bd->bi_cpu,
+              bfin_revid(),
+              get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
+
+       printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
+       printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
+#if defined(__ADSPBF60x__)
+       printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
+       printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
+       printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
+#else
+       printf("System: %s MHz\n", strmhz(buf, get_sclk()));
+#endif
+
+       return 0;
+}
+
+int exception_init(void)
+{
+       bfin_write_EVT3(trap);
+       return 0;
+}
+
+int irq_init(void)
+{
+#ifdef SIC_IMASK0
+       bfin_write_SIC_IMASK0(0);
+       bfin_write_SIC_IMASK1(0);
+# ifdef SIC_IMASK2
+       bfin_write_SIC_IMASK2(0);
+# endif
+#elif defined(SICA_IMASK0)
+       bfin_write_SICA_IMASK0(0);
+       bfin_write_SICA_IMASK1(0);
+#elif defined(SIC_IMASK)
+       bfin_write_SIC_IMASK(0);
+#endif
+       /* Set up a dummy NMI handler if needed.  */
+       if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
+               bfin_write_EVT2(evt_nmi);       /* NMI */
+       bfin_write_EVT5(evt_default);   /* hardware error */
+       bfin_write_EVT6(evt_default);   /* core timer */
+       bfin_write_EVT7(evt_default);
+       bfin_write_EVT8(evt_default);
+       bfin_write_EVT9(evt_default);
+       bfin_write_EVT10(evt_default);
+       bfin_write_EVT11(evt_default);
+       bfin_write_EVT12(evt_default);
+       bfin_write_EVT13(evt_default);
+       bfin_write_EVT14(evt_default);
+       bfin_write_EVT15(evt_default);
+       bfin_write_ILAT(0);
+       CSYNC();
+       /* enable hardware error irq */
+       irq_flags = 0x3f;
+       local_irq_enable();
+       return 0;
+}
+
 __attribute__ ((__noreturn__))
 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 {
@@ -102,51 +353,62 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
        bfin_core1_start();
 #endif
 
-       serial_early_puts("Board init flash\n");
-       board_init_f(bootflag);
+       serial_early_puts("Init global data\n");
+       global_board_data_init();
+
+       board_init_f(0);
 
        /* should not be reached */
        while (1);
 }
 
-int exception_init(void)
+int arch_cpu_init(void)
 {
-       bfin_write_EVT3(trap);
+       serial_early_puts("Init CPLB tables\n");
+       init_cplbtables();
+
+       serial_early_puts("Exceptions setup\n");
+       exception_init();
+
+#ifndef CONFIG_ICACHE_OFF
+       serial_early_puts("Turn on ICACHE\n");
+       icache_enable();
+#endif
+#ifndef CONFIG_DCACHE_OFF
+       serial_early_puts("Turn on DCACHE\n");
+       dcache_enable();
+#endif
+
+#ifdef DEBUG
+       if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
+               hang();
+#endif
+
+       /* Initialize */
+       serial_early_puts("IRQ init\n");
+       irq_init();
+
        return 0;
 }
 
-int irq_init(void)
+int arch_misc_init(void)
 {
-#ifdef SIC_IMASK0
-       bfin_write_SIC_IMASK0(0);
-       bfin_write_SIC_IMASK1(0);
-# ifdef SIC_IMASK2
-       bfin_write_SIC_IMASK2(0);
-# endif
-#elif defined(SICA_IMASK0)
-       bfin_write_SICA_IMASK0(0);
-       bfin_write_SICA_IMASK1(0);
-#elif defined(SIC_IMASK)
-       bfin_write_SIC_IMASK(0);
+#if defined(CONFIG_SYS_I2C)
+       i2c_reloc_fixup();
 #endif
-       /* Set up a dummy NMI handler if needed.  */
-       if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
-               bfin_write_EVT2(evt_nmi);       /* NMI */
-       bfin_write_EVT5(evt_default);   /* hardware error */
-       bfin_write_EVT6(evt_default);   /* core timer */
-       bfin_write_EVT7(evt_default);
-       bfin_write_EVT8(evt_default);
-       bfin_write_EVT9(evt_default);
-       bfin_write_EVT10(evt_default);
-       bfin_write_EVT11(evt_default);
-       bfin_write_EVT12(evt_default);
-       bfin_write_EVT13(evt_default);
-       bfin_write_EVT14(evt_default);
-       bfin_write_EVT15(evt_default);
-       bfin_write_ILAT(0);
-       CSYNC();
-       /* enable hardware error irq */
-       irq_flags = 0x3f;
-       local_irq_enable();
+
+       display_global_data();
+
+       if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
+               puts("\nLog buffer from operating system:\n");
+               bfin_os_log_dump();
+               puts("\n");
+       }
+
+       return 0;
+}
+
+int interrupt_init(void)
+{
        return 0;
 }
index 29a7c23..f31abfa 100644 (file)
@@ -196,8 +196,8 @@ ENTRY(_start)
         * takes care of clearing things for us.
         */
        serial_early_puts("Zero BSS");
-       r0.l = __bss_vma;
-       r0.h = __bss_vma;
+       r0.l = __bss_start;
+       r0.h = __bss_start;
        r1 = 0 (x);
        r2.l = __bss_len;
        r2.h = __bss_len;
@@ -251,3 +251,13 @@ LENTRY(_get_pc)
 #endif
        rts;
 ENDPROC(_get_pc)
+
+ENTRY(_relocate_code)
+       /* Fake relocate code. Setup the new stack only */
+       sp = r0;
+       fp = sp;
+       r0 = p3;
+       r1.h = 0x2000;
+       r1.l = 0x10;
+       jump.l _board_init_r
+ENDPROC(_relocate_code)
index 7f0411f..ae1b813 100644 (file)
@@ -135,6 +135,8 @@ SECTIONS
                *(COMMON)
                . = ALIGN(4);
        } >ram_data
-       __bss_vma = ADDR(.bss);
+       __bss_end = .;
+       __bss_start = ADDR(.bss);
        __bss_len = SIZEOF(.bss);
+       __init_end = .;
 }
index 59d3faa..05ae03c 100644 (file)
@@ -78,7 +78,7 @@ extern u_long get_sclk1(void);
 extern u_long get_dclk(void);
 # define get_uart_clk get_sclk0
 # define get_i2c_clk get_sclk0
-# define get_spi_clk get_sclk0
+# define get_spi_clk get_sclk1
 #else
 # define get_uart_clk get_sclk
 # define get_i2c_clk get_sclk
index 1da386e..836658a 100644 (file)
        }
 #endif
 
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_ARCH_MISC_INIT
+
 #endif
index 02b81d3..fd0d86d 100644 (file)
 #define WDOG1_CNT         0xFFC17804 /* WDOG1 Count Register */
 #define WDOG1_STAT        0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
 
+#define SDU0_MSG_SET      0xFFC1F084 /* SDU0 Message Set Register */
+
 #define EMAC0_MACCFG      0xFFC20000 /* EMAC0 MAC Configuration Register */
 #define EMAC1_MACCFG      0xFFC22000 /* EMAC1 MAC Configuration Register */
 
index acaeee9..7b5cf6a 100644 (file)
@@ -25,9 +25,12 @@ typedef struct bd_info {
        unsigned long bi_vco;
        unsigned long bi_cclk;
        unsigned long bi_sclk;
+       unsigned char bi_enetaddr[6];
 } bd_t;
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_BLACKFIN
 
+int    arch_misc_init(void);
+
 #endif /* _U_BOOT_H_ */
index 4ba7bf6..b534a98 100644 (file)
@@ -9,11 +9,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-# Unnecessary.
-# Use CONFIG_SYS_BOARD instead of BFIN_BOARD_NAME
-# and delete this.
-ccflags-y += -DBFIN_BOARD_NAME='"$(BOARD)"'
-
 obj-y  += ins.o
 obj-y  += memcmp.o
 obj-y  += memcpy.o
@@ -21,7 +16,6 @@ obj-y += memmove.o
 obj-y  += memset.o
 obj-y  += outs.o
 obj-$(CONFIG_CMD_KGDB) += __kgdb.o
-obj-y  += board.o
 obj-y  += boot.o
 obj-y  += cache.o
 obj-y  += clocks.o
@@ -30,3 +24,4 @@ obj-$(CONFIG_CMD_KGDB) += kgdb.o
 obj-y  += muldi3.o
 obj-$(CONFIG_HAS_POST) += post.o
 obj-y  += string.o
+obj-y  += sections.o
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
deleted file mode 100644 (file)
index 8784255..0000000
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * U-boot - board.c First C file to be called contains init routines
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <stdio_dev.h>
-#include <serial.h>
-#include <environment.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <net.h>
-#include <status_led.h>
-#include <version.h>
-#include <watchdog.h>
-
-#include <asm/cplb.h>
-#include <asm/mach-common/bits/mpu.h>
-#include <asm/clock.h>
-#include <kgdb.h>
-
-#ifdef CONFIG_CMD_NAND
-#include <nand.h>      /* cannot even include nand.h if it isnt configured */
-#endif
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-#if defined(CONFIG_POST)
-#include <post.h>
-int post_flag;
-#endif
-
-#if defined(CONFIG_SYS_I2C)
-#include <i2c.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__attribute__((always_inline))
-static inline void serial_early_puts(const char *s)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-       serial_puts("Early: ");
-       serial_puts(s);
-#endif
-}
-
-static int display_banner(void)
-{
-       display_options();
-       printf("CPU:   ADSP %s "
-               "(Detected Rev: 0.%d) "
-               "(%s boot)\n",
-               gd->bd->bi_cpu,
-               bfin_revid(),
-               get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
-       return 0;
-}
-
-static int init_baudrate(void)
-{
-       gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-       return 0;
-}
-
-static void display_global_data(void)
-{
-       bd_t *bd;
-
-#ifndef CONFIG_DEBUG_EARLY_SERIAL
-       return;
-#endif
-
-       bd = gd->bd;
-       printf(" gd: %p\n", gd);
-       printf(" |-flags: %lx\n", gd->flags);
-       printf(" |-board_type: %lx\n", gd->arch.board_type);
-       printf(" |-baudrate: %u\n", gd->baudrate);
-       printf(" |-have_console: %lx\n", gd->have_console);
-       printf(" |-ram_size: %lx\n", gd->ram_size);
-       printf(" |-env_addr: %lx\n", gd->env_addr);
-       printf(" |-env_valid: %lx\n", gd->env_valid);
-       printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
-       printf(" \\-bd: %p\n", gd->bd);
-       printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
-       printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
-       printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
-       printf("   |-bi_flashstart: %lx\n", bd->bi_flashstart);
-       printf("   |-bi_flashsize: %lx\n", bd->bi_flashsize);
-       printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
-}
-
-#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
-#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
-#if defined(__ADSPBF60x__)
-#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
-#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
-#else
-#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
-#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
-#endif
-void init_cplbtables(void)
-{
-       volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA;
-       volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA;
-       uint32_t extern_memory;
-       size_t i;
-
-       void icplb_add(uint32_t addr, uint32_t data)
-       {
-               *(ICPLB_ADDR + i) = addr;
-               *(ICPLB_DATA + i) = data;
-       }
-       void dcplb_add(uint32_t addr, uint32_t data)
-       {
-               *(DCPLB_ADDR + i) = addr;
-               *(DCPLB_DATA + i) = data;
-       }
-
-       /* populate a few common entries ... we'll let
-        * the memory map and cplb exception handler do
-        * the rest of the work.
-        */
-       i = 0;
-       ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
-       ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
-       DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
-       DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
-
-       icplb_add(0xFFA00000, L1_IMEMORY);
-       dcplb_add(0xFF800000, L1_DMEMORY);
-       ++i;
-#if defined(__ADSPBF60x__)
-       icplb_add(0x0, 0x0);
-       dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
-               CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
-       ++i;
-#endif
-
-       if (CONFIG_MEM_SIZE) {
-               uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
-               uint32_t mend  = mbase + CONFIG_SYS_MONITOR_LEN;
-               mbase &= CPLB_PAGE_MASK;
-               mend &= CPLB_PAGE_MASK;
-
-               icplb_add(mbase, SDRAM_IKERNEL);
-               dcplb_add(mbase, SDRAM_DKERNEL);
-               ++i;
-
-               /*
-                * If the monitor crosses a 4 meg boundary, we'll need
-                * to lock two entries for it.  We assume it doesn't
-                * cross two 4 meg boundaries ...
-                */
-               if (mbase != mend) {
-                       icplb_add(mend, SDRAM_IKERNEL);
-                       dcplb_add(mend, SDRAM_DKERNEL);
-                       ++i;
-               }
-       }
-
-#ifndef __ADSPBF60x__
-       icplb_add(0x20000000, SDRAM_INON_CHBL);
-       dcplb_add(0x20000000, SDRAM_EBIU);
-       ++i;
-#endif
-
-       /* Add entries for the rest of external RAM up to the bootrom */
-       extern_memory = 0;
-
-#ifdef CONFIG_DEBUG_NULL_PTR
-       icplb_add(extern_memory, (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
-       dcplb_add(extern_memory, (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
-       ++i;
-       icplb_add(extern_memory, SDRAM_IKERNEL);
-       dcplb_add(extern_memory, SDRAM_DKERNEL);
-       extern_memory += CPLB_PAGE_SIZE;
-       ++i;
-#endif
-
-       while (i < 16 && extern_memory <
-               (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
-               icplb_add(extern_memory, SDRAM_IGENERIC);
-               dcplb_add(extern_memory, SDRAM_DGENERIC);
-               extern_memory += CPLB_EX_PAGE_SIZE;
-               ++i;
-       }
-       while (i < 16) {
-               icplb_add(0, 0);
-               dcplb_add(0, 0);
-               ++i;
-       }
-}
-
-static int global_board_data_init(void)
-{
-#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR 0
-#endif
-#ifndef CONFIG_SYS_BD_INFO_ADDR
-# define CONFIG_SYS_BD_INFO_ADDR 0
-#endif
-
-       bd_t *bd;
-
-       if (CONFIG_SYS_GBL_DATA_ADDR) {
-               gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
-               memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-       } else {
-               static gd_t _bfin_gd;
-               gd = &_bfin_gd;
-       }
-
-       if (CONFIG_SYS_BD_INFO_ADDR) {
-               bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR);
-               memset(bd, 0, GENERATED_BD_INFO_SIZE);
-       } else {
-               static bd_t _bfin_bd;
-               bd = &_bfin_bd;
-       }
-       gd->bd = bd;
-
-       bd->bi_r_version = version_string;
-       bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
-       bd->bi_board_name = BFIN_BOARD_NAME;
-       bd->bi_vco = get_vco();
-       bd->bi_cclk = get_cclk();
-       bd->bi_sclk = get_sclk();
-       bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-       bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
-
-       return 0;
-}
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-
-extern int watchdog_init(void);
-extern int exception_init(void);
-extern int irq_init(void);
-extern int timer_init(void);
-
-void board_init_f(ulong bootflag)
-{
-       char buf[32];
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-       serial_early_puts("Board early init flash\n");
-       board_early_init_f();
-#endif
-
-       serial_early_puts("Init CPLB tables\n");
-       init_cplbtables();
-
-       serial_early_puts("Exceptions setup\n");
-       exception_init();
-
-#ifndef CONFIG_ICACHE_OFF
-       serial_early_puts("Turn on ICACHE\n");
-       icache_enable();
-#endif
-#ifndef CONFIG_DCACHE_OFF
-       serial_early_puts("Turn on DCACHE\n");
-       dcache_enable();
-#endif
-
-#ifdef CONFIG_HW_WATCHDOG
-       serial_early_puts("Setting up external watchdog\n");
-       hw_watchdog_init();
-#endif
-
-#ifdef DEBUG
-       if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
-               hang();
-#endif
-       serial_early_puts("Init global data\n");
-
-       global_board_data_init();
-
-       /* Initialize */
-       serial_early_puts("IRQ init\n");
-       irq_init();
-       serial_early_puts("Environment init\n");
-       env_init();
-       serial_early_puts("Baudrate init\n");
-       init_baudrate();
-       serial_early_puts("Serial init\n");
-       serial_init();
-       serial_initialize();
-       serial_early_puts("Console init flash\n");
-       console_init_f();
-       serial_early_puts("End of early debugging\n");
-       display_banner();
-
-       checkboard();
-       timer_init();
-
-       printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
-       printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
-#if defined(__ADSPBF60x__)
-       printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
-       printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
-       printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
-#else
-       printf("System: %s MHz\n", strmhz(buf, get_sclk()));
-#endif
-
-       if (CONFIG_MEM_SIZE) {
-               printf("RAM:   ");
-               print_size(gd->bd->bi_memsize, "\n");
-       }
-
-#if defined(CONFIG_POST)
-       post_init_f();
-       post_bootmode_init();
-       post_run(NULL, POST_ROM | post_bootmode_get(0));
-#endif
-
-       board_init_r((gd_t *) gd, 0x20000010);
-}
-
-static void board_net_init_r(bd_t *bd)
-{
-#ifdef CONFIG_BITBANGMII
-       bb_miiphy_init();
-#endif
-#ifdef CONFIG_CMD_NET
-       printf("Net:   ");
-       eth_initialize(bd);
-#endif
-}
-
-void board_init_r(gd_t * id, ulong dest_addr)
-{
-       bd_t *bd;
-       gd = id;
-       gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */
-       bd = gd->bd;
-
-#if defined(CONFIG_POST)
-       post_output_backlog();
-#endif
-
-       /* initialize malloc() area */
-       mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-
-#if    !defined(CONFIG_SYS_NO_FLASH)
-       /* Initialize the flash and protect u-boot by default */
-       extern flash_info_t flash_info[];
-       puts("Flash: ");
-       ulong size = flash_init();
-       print_size(size, "\n");
-       flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE,
-               CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-               &flash_info[0]);
-       bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-       bd->bi_flashsize = size;
-       bd->bi_flashoffset = 0;
-#else
-       bd->bi_flashstart = 0;
-       bd->bi_flashsize = 0;
-       bd->bi_flashoffset = 0;
-#endif
-
-#ifdef CONFIG_CMD_NAND
-       puts("NAND:  ");
-       nand_init();            /* go init the NAND */
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-       puts("MMC:   ");
-       mmc_initialize(bd);
-#endif
-
-#if defined(CONFIG_SYS_I2C)
-       i2c_reloc_fixup();
-#endif
-       /* relocate environment function pointers etc. */
-       env_relocate();
-
-       /* Initialize stdio devices */
-       stdio_init();
-       jumptable_init();
-
-       /* Initialize the console (after the relocation and devices init) */
-       console_init_r();
-
-#ifdef CONFIG_CMD_KGDB
-       puts("KGDB:  ");
-       kgdb_init();
-#endif
-
-#ifdef CONFIG_STATUS_LED
-       status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
-       status_led_set(STATUS_LED_CRASH, STATUS_LED_OFF);
-#endif
-
-       /* Initialize from environment */
-       load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#if defined(CONFIG_MISC_INIT_R)
-       /* miscellaneous platform dependent initialisations */
-       misc_init_r();
-#endif
-
-       board_net_init_r(bd);
-
-       display_global_data();
-
-#if defined(CONFIG_POST)
-       if (post_flag)
-               post_run(NULL, POST_RAM | post_bootmode_get(0));
-#endif
-
-       if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
-               puts("\nLog buffer from operating system:\n");
-               bfin_os_log_dump();
-               puts("\n");
-       }
-
-       /* main_loop() can return to retry autoboot, if so just run it again. */
-       for (;;)
-               main_loop();
-}
diff --git a/arch/blackfin/lib/sections.c b/arch/blackfin/lib/sections.c
new file mode 100644 (file)
index 0000000..b50f30a
--- /dev/null
@@ -0,0 +1,11 @@
+/*
+ * U-boot - section.c
+ *
+ * Copyright (c) 2014 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __init_end[0] __attribute__((section(".__init_end")));
index b703646..0cba45b 100644 (file)
@@ -11,16 +11,8 @@ choice
 config TARGET_NIOS2_GENERIC
        bool "Support nios2-generic"
 
-config TARGET_PCI5441
-       bool "Support PCI5441"
-
-config TARGET_PK1C20
-       bool "Support PK1C20"
-
 endchoice
 
 source "board/altera/nios2-generic/Kconfig"
-source "board/psyent/pci5441/Kconfig"
-source "board/psyent/pk1c20/Kconfig"
 
 endmenu
index 82bd887..9b7c56d 100644 (file)
@@ -17,3 +17,5 @@ PLATFORM_CPPFLAGS += -G0
 
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
+__HAVE_ARCH_GENERIC_BOARD := y
index bdd983d..3fe7847 100644 (file)
@@ -7,5 +7,5 @@
 
 extra-y        = start.o
 obj-y  = exceptions.o
-obj-y  += cpu.o interrupts.o sysid.o traps.o epcs.o
+obj-y  += cpu.o interrupts.o sysid.o traps.o
 obj-y  += fdt.o
index e0dcbc2..86f94b7 100644 (file)
 #include <nios2-io.h>
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined (CONFIG_SYS_NIOS_SYSID_BASE)
 extern void display_sysid (void);
 #endif /* CONFIG_SYS_NIOS_SYSID_BASE */
 
-int checkcpu (void)
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
 {
        printf ("CPU   : Nios-II\n");
 #if !defined(CONFIG_SYS_NIOS_SYSID_BASE)
@@ -24,6 +27,7 @@ int checkcpu (void)
 #endif
        return (0);
 }
+#endif /* CONFIG_DISPLAY_CPUINFO */
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -47,3 +51,11 @@ void dcache_disable(void)
 {
        flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
 }
+
+int arch_cpu_init(void)
+{
+       gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
diff --git a/arch/nios2/cpu/epcs.c b/arch/nios2/cpu/epcs.c
deleted file mode 100644 (file)
index 9758552..0000000
+++ /dev/null
@@ -1,717 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_SYS_NIOS_EPCSBASE)
-#include <command.h>
-#include <asm/io.h>
-#include <nios2-io.h>
-#include <nios2-epcs.h>
-
-
-/*-----------------------------------------------------------------------*/
-#define SHORT_HELP\
-       "epcs    - read/write Cyclone EPCS configuration device.\n"
-
-#define LONG_HELP\
-       "\n"\
-       "epcs erase start [end]\n"\
-       "    - erase sector start or sectors start through end.\n"\
-       "epcs info\n"\
-       "    - display EPCS device information.\n"\
-       "epcs protect on | off\n"\
-       "    - turn device protection on or off.\n"\
-       "epcs read addr offset count\n"\
-       "    - read count bytes from offset to addr.\n"\
-       "epcs write addr offset count\n"\
-       "    - write count bytes to offset from addr.\n"\
-       "epcs verify addr offset count\n"\
-       "    - verify count bytes at offset from addr."
-
-
-/*-----------------------------------------------------------------------*/
-/* Operation codes for serial configuration devices
- */
-#define EPCS_WRITE_ENA         0x06    /* Write enable */
-#define EPCS_WRITE_DIS         0x04    /* Write disable */
-#define EPCS_READ_STAT         0x05    /* Read status */
-#define EPCS_READ_BYTES                0x03    /* Read bytes */
-#define EPCS_READ_ID           0xab    /* Read silicon id */
-#define EPCS_WRITE_STAT                0x01    /* Write status */
-#define EPCS_WRITE_BYTES       0x02    /* Write bytes */
-#define EPCS_ERASE_BULK                0xc7    /* Erase entire device */
-#define EPCS_ERASE_SECT                0xd8    /* Erase sector */
-
-/* Device status register bits
- */
-#define EPCS_STATUS_WIP                (1<<0)  /* Write in progress */
-#define EPCS_STATUS_WEL                (1<<1)  /* Write enable latch */
-
-/* Misc
- */
-#define EPCS_TIMEOUT           100     /* 100 msec timeout */
-
-static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE;
-
-/***********************************************************************
- * Device access
- ***********************************************************************/
-static int epcs_cs (int assert)
-{
-       ulong start;
-       unsigned tmp;
-
-
-       if (assert) {
-               tmp = readl (&epcs->control);
-               writel (tmp | NIOS_SPI_SSO, &epcs->control);
-       } else {
-               /* Let all bits shift out */
-               start = get_timer (0);
-               while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0)
-                       if (get_timer (start) > EPCS_TIMEOUT)
-                               return (-1);
-               tmp = readl (&epcs->control);
-               writel (tmp & ~NIOS_SPI_SSO, &epcs->control);
-       }
-       return (0);
-}
-
-static int epcs_tx (unsigned char c)
-{
-       ulong start;
-
-       start = get_timer (0);
-       while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0)
-               if (get_timer (start) > EPCS_TIMEOUT)
-                       return (-1);
-       writel (c, &epcs->txdata);
-       return (0);
-}
-
-static int epcs_rx (void)
-{
-       ulong start;
-
-       start = get_timer (0);
-       while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0)
-               if (get_timer (start) > EPCS_TIMEOUT)
-                       return (-1);
-       return (readl (&epcs->rxdata));
-}
-
-static unsigned char bitrev[] = {
-       0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e,
-       0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
-};
-
-static unsigned char epcs_bitrev (unsigned char c)
-{
-       unsigned char val;
-
-       val  = bitrev[c>>4];
-       val |= bitrev[c & 0x0f]<<4;
-       return (val);
-}
-
-static void epcs_rcv (unsigned char *dst, int len)
-{
-       while (len--) {
-               epcs_tx (0);
-               *dst++ = epcs_rx ();
-       }
-}
-
-static void epcs_rrcv (unsigned char *dst, int len)
-{
-       while (len--) {
-               epcs_tx (0);
-               *dst++ = epcs_bitrev (epcs_rx ());
-       }
-}
-
-static void epcs_snd (unsigned char *src, int len)
-{
-       while (len--) {
-               epcs_tx (*src++);
-               epcs_rx ();
-       }
-}
-
-static void epcs_rsnd (unsigned char *src, int len)
-{
-       while (len--) {
-               epcs_tx (epcs_bitrev (*src++));
-               epcs_rx ();
-       }
-}
-
-static void epcs_wr_enable (void)
-{
-       epcs_cs (1);
-       epcs_tx (EPCS_WRITE_ENA);
-       epcs_rx ();
-       epcs_cs (0);
-}
-
-static unsigned char epcs_status_rd (void)
-{
-       unsigned char status;
-
-       epcs_cs (1);
-       epcs_tx (EPCS_READ_STAT);
-       epcs_rx ();
-       epcs_tx (0);
-       status = epcs_rx ();
-       epcs_cs (0);
-       return (status);
-}
-
-static void epcs_status_wr (unsigned char status)
-{
-       epcs_wr_enable ();
-       epcs_cs (1);
-       epcs_tx (EPCS_WRITE_STAT);
-       epcs_rx ();
-       epcs_tx (status);
-       epcs_rx ();
-       epcs_cs (0);
-       return;
-}
-
-/***********************************************************************
- * Device information
- ***********************************************************************/
-
-static struct epcs_devinfo_t devinfo[] = {
-       { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c },
-       { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c },
-       { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c },
-       { "EPCS64", 0x16, 23,128, 16, 8, 0x1c },
-       { 0, 0, 0, 0, 0, 0 }
-};
-
-int epcs_reset (void)
-{
-       /* When booting from an epcs controller, the epcs bootrom
-        * code may leave the slave select in an asserted state.
-        * This causes two problems: (1) The initial epcs access
-        * will fail -- not a big deal, and (2) a software reset
-        * will cause the bootrom code to hang since it does not
-        * ensure the select is negated prior to first access -- a
-        * big deal. Here we just negate chip select and everything
-        * gets better :-)
-        */
-       epcs_cs (0); /* Negate chip select */
-       return (0);
-}
-
-epcs_devinfo_t *epcs_dev_find (void)
-{
-       unsigned char buf[4];
-       unsigned char id;
-       int i;
-       struct epcs_devinfo_t *dev = NULL;
-
-       /* Read silicon id requires 3 "dummy bytes" before it's put
-        * on the wire.
-        */
-       buf[0] = EPCS_READ_ID;
-       buf[1] = 0;
-       buf[2] = 0;
-       buf[3] = 0;
-
-       epcs_cs (1);
-       epcs_snd (buf,4);
-       epcs_rcv (buf,1);
-       if (epcs_cs (0) == -1)
-               return (NULL);
-       id = buf[0];
-
-       /* Find the info struct */
-       i = 0;
-       while (devinfo[i].name) {
-               if (id == devinfo[i].id) {
-                       dev = &devinfo[i];
-                       break;
-               }
-               i++;
-       }
-
-       return (dev);
-}
-
-/***********************************************************************
- * Misc Utilities
- ***********************************************************************/
-int epcs_cfgsz (void)
-{
-       int sz = 0;
-       unsigned char buf[128];
-       unsigned char *p;
-       struct epcs_devinfo_t *dev = epcs_dev_find ();
-
-       if (!dev)
-               return (-1);
-
-       /* Read in the first 128 bytes of the device */
-       buf[0] = EPCS_READ_BYTES;
-       buf[1] = 0;
-       buf[2] = 0;
-       buf[3] = 0;
-
-       epcs_cs (1);
-       epcs_snd (buf,4);
-       epcs_rrcv (buf, sizeof(buf));
-       epcs_cs (0);
-
-       /* Search for the starting 0x6a which is followed by the
-        * 4-byte 'register' and 4-byte bit-count.
-        */
-       p = buf;
-       while (p < buf + sizeof(buf)-8) {
-               if ( *p == 0x6a ) {
-                       /* Point to bit count and extract */
-                       p += 5;
-                       sz = *p++;
-                       sz |= *p++ << 8;
-                       sz |= *p++ << 16;
-                       sz |= *p++ << 24;
-                       /* Convert to byte count */
-                       sz += 7;
-                       sz >>= 3;
-               } else if (*p == 0xff) {
-                       /* 0xff is ok ... just skip */
-                       p++;
-                       continue;
-               } else {
-                       /* Not 0xff or 0x6a ... something's not
-                        * right ... report 'unknown' (sz=0).
-                        */
-                       break;
-               }
-       }
-       return (sz);
-}
-
-int epcs_erase (unsigned start, unsigned end)
-{
-       unsigned off, sectsz;
-       unsigned char buf[4];
-       struct epcs_devinfo_t *dev = epcs_dev_find ();
-
-       if (!dev || (start>end))
-               return (-1);
-
-       /* Erase the requested sectors. An address is required
-        * that lies within the requested sector -- we'll just
-        * use the first address in the sector.
-        */
-       printf ("epcs erasing sector %d ", start);
-       if (start != end)
-               printf ("to %d ", end);
-       sectsz = (1 << dev->sz_sect);
-       while (start <= end) {
-               off = start * sectsz;
-               start++;
-
-               buf[0] = EPCS_ERASE_SECT;
-               buf[1] = off >> 16;
-               buf[2] = off >> 8;
-               buf[3] = off;
-
-               epcs_wr_enable ();
-               epcs_cs (1);
-               epcs_snd (buf,4);
-               epcs_cs (0);
-
-               printf ("."); /* Some user feedback */
-
-               /* Wait for erase to complete */
-               while (epcs_status_rd() & EPCS_STATUS_WIP)
-                       ;
-       }
-       printf (" done.\n");
-       return (0);
-}
-
-int epcs_read (ulong addr, ulong off, ulong cnt)
-{
-       unsigned char buf[4];
-       struct epcs_devinfo_t *dev = epcs_dev_find ();
-
-       if (!dev)
-               return (-1);
-
-       buf[0] = EPCS_READ_BYTES;
-       buf[1] = off >> 16;
-       buf[2] = off >> 8;
-       buf[3] = off;
-
-       epcs_cs (1);
-       epcs_snd (buf,4);
-       epcs_rrcv ((unsigned char *)addr, cnt);
-       epcs_cs (0);
-
-       return (0);
-}
-
-int epcs_write (ulong addr, ulong off, ulong cnt)
-{
-       ulong wrcnt;
-       unsigned pgsz;
-       unsigned char buf[4];
-       struct epcs_devinfo_t *dev = epcs_dev_find ();
-
-       if (!dev)
-               return (-1);
-
-       pgsz = (1<<dev->sz_page);
-       while (cnt) {
-               if (off % pgsz)
-                       wrcnt = pgsz - (off % pgsz);
-               else
-                       wrcnt = pgsz;
-               wrcnt = (wrcnt > cnt) ? cnt : wrcnt;
-
-               buf[0] = EPCS_WRITE_BYTES;
-               buf[1] = off >> 16;
-               buf[2] = off >> 8;
-               buf[3] = off;
-
-               epcs_wr_enable ();
-               epcs_cs (1);
-               epcs_snd (buf,4);
-               epcs_rsnd ((unsigned char *)addr, wrcnt);
-               epcs_cs (0);
-
-               /* Wait for write to complete */
-               while (epcs_status_rd() & EPCS_STATUS_WIP)
-                       ;
-
-               cnt -= wrcnt;
-               off += wrcnt;
-               addr += wrcnt;
-       }
-
-       return (0);
-}
-
-int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err)
-{
-       ulong rdcnt;
-       unsigned char buf[256];
-       unsigned char *start,*end;
-       int i;
-
-       start = end = (unsigned char *)addr;
-       while (cnt) {
-               rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt;
-               epcs_read ((ulong)buf, off, rdcnt);
-               for (i=0; i<rdcnt; i++) {
-                       if (*end != buf[i]) {
-                               *err = end - start;
-                               return(-1);
-                       }
-                       end++;
-               }
-               cnt -= rdcnt;
-               off += rdcnt;
-       }
-       return (0);
-}
-
-static int epcs_sect_erased (int sect, unsigned *offset,
-               struct epcs_devinfo_t *dev)
-{
-       unsigned char buf[128];
-       unsigned off, end;
-       unsigned sectsz;
-       int i;
-
-       sectsz = (1 << dev->sz_sect);
-       off = sectsz * sect;
-       end = off + sectsz;
-
-       while (off < end) {
-               epcs_read ((ulong)buf, off, sizeof(buf));
-               for (i=0; i < sizeof(buf); i++) {
-                       if (buf[i] != 0xff) {
-                               *offset = off + i;
-                               return (0);
-                       }
-               }
-               off += sizeof(buf);
-       }
-       return (1);
-}
-
-
-/***********************************************************************
- * Commands
- ***********************************************************************/
-static
-void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char * const argv[])
-{
-       int i;
-       unsigned char stat;
-       unsigned tmp;
-       int erased;
-
-       /* Basic device info */
-       printf ("%s: %d kbytes (%d sectors x %d kbytes,"
-               " %d bytes/page)\n",
-               dev->name, 1 << (dev->size-10),
-               dev->num_sects, 1 << (dev->sz_sect-10),
-               1 << dev->sz_page );
-
-       /* Status -- for now protection is all-or-nothing */
-       stat = epcs_status_rd();
-       printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n",
-               stat,
-               (stat & EPCS_STATUS_WIP) ? 1 : 0,
-               (stat & EPCS_STATUS_WEL) ? 1 : 0,
-               (stat & dev->prot_mask) ? "on" : "off" );
-
-       /* Configuration  */
-       tmp = epcs_cfgsz ();
-       if (tmp) {
-               printf ("config: 0x%06x (%d) bytes\n", tmp, tmp );
-       } else {
-               printf ("config: unknown\n" );
-       }
-
-       /* Sector info */
-       for (i=0; (i < dev->num_sects) && (argc > 1); i++) {
-               erased = epcs_sect_erased (i, &tmp, dev);
-               if ((i & 0x03) == 0) printf ("\n");
-               printf ("%4d: %07x ",
-                       i, i*(1<<dev->sz_sect) );
-               if (erased)
-                       printf ("E ");
-               else
-                       printf ("  ");
-       }
-       printf ("\n");
-
-       return;
-}
-
-static
-void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char * const argv[])
-{
-       unsigned start,end;
-
-       if ((argc < 3) || (argc > 4)) {
-               printf ("USAGE: epcs erase sect [end]\n");
-               return;
-       }
-       if ((epcs_status_rd() & dev->prot_mask) != 0) {
-               printf ( "epcs: device protected.\n");
-               return;
-       }
-
-       start = simple_strtoul (argv[2], NULL, 10);
-       if (argc > 3)
-               end = simple_strtoul (argv[3], NULL, 10);
-       else
-               end = start;
-       if ((start >= dev->num_sects) || (start > end)) {
-               printf ("epcs: invalid sector range: [%d:%d]\n",
-                       start, end );
-               return;
-       }
-
-       epcs_erase (start, end);
-
-       return;
-}
-
-static
-void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char * const argv[])
-{
-       unsigned char stat;
-
-       /* For now protection is all-or-nothing to keep things
-        * simple. The protection bits don't map in a linear
-        * fashion ... and we would rather protect the bottom
-        * of the device since it contains the config data and
-        * leave the top unprotected for app use. But unfortunately
-        * protection works from top-to-bottom so it does
-        * really help very much from a software app point-of-view.
-        */
-       if (argc < 3) {
-               printf ("USAGE: epcs protect on | off\n");
-               return;
-       }
-       if (!dev)
-               return;
-
-       /* Protection on/off is just a matter of setting/clearing
-        * all protection bits in the status register.
-        */
-       stat = epcs_status_rd ();
-       if (strcmp ("on", argv[2]) == 0) {
-               stat |= dev->prot_mask;
-       } else if (strcmp ("off", argv[2]) == 0 ) {
-               stat &= ~dev->prot_mask;
-       } else {
-               printf ("epcs: unknown protection: %s\n", argv[2]);
-               return;
-       }
-       epcs_status_wr (stat);
-       return;
-}
-
-static
-void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char * const argv[])
-{
-       ulong addr,off,cnt;
-       ulong sz;
-
-       if (argc < 5) {
-               printf ("USAGE: epcs read addr offset count\n");
-               return;
-       }
-
-       sz = 1 << dev->size;
-       addr = simple_strtoul (argv[2], NULL, 16);
-       off  = simple_strtoul (argv[3], NULL, 16);
-       cnt  = simple_strtoul (argv[4], NULL, 16);
-       if (off > sz) {
-               printf ("offset is greater than device size"
-                       "... aborting.\n");
-               return;
-       }
-       if ((off + cnt) > sz) {
-               printf ("request exceeds device size"
-                       "... truncating.\n");
-               cnt = sz - off;
-       }
-       printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n",
-                       addr, off, cnt);
-       epcs_read (addr, off, cnt);
-
-       return;
-}
-
-static
-void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char * const argv[])
-{
-       ulong addr,off,cnt;
-       ulong sz;
-       ulong err;
-
-       if (argc < 5) {
-               printf ("USAGE: epcs write addr offset count\n");
-               return;
-       }
-       if ((epcs_status_rd() & dev->prot_mask) != 0) {
-               printf ( "epcs: device protected.\n");
-               return;
-       }
-
-       sz = 1 << dev->size;
-       addr = simple_strtoul (argv[2], NULL, 16);
-       off  = simple_strtoul (argv[3], NULL, 16);
-       cnt  = simple_strtoul (argv[4], NULL, 16);
-       if (off > sz) {
-               printf ("offset is greater than device size"
-                       "... aborting.\n");
-               return;
-       }
-       if ((off + cnt) > sz) {
-               printf ("request exceeds device size"
-                       "... truncating.\n");
-               cnt = sz - off;
-       }
-       printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n",
-                       addr, off, cnt);
-       epcs_write (addr, off, cnt);
-       if (epcs_verify (addr, off, cnt, &err) != 0)
-               printf ("epcs: write error at offset %06lx\n", err);
-
-       return;
-}
-
-static
-void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char * const argv[])
-{
-       ulong addr,off,cnt;
-       ulong sz;
-       ulong err;
-
-       if (argc < 5) {
-               printf ("USAGE: epcs verify addr offset count\n");
-               return;
-       }
-
-       sz = 1 << dev->size;
-       addr = simple_strtoul (argv[2], NULL, 16);
-       off  = simple_strtoul (argv[3], NULL, 16);
-       cnt  = simple_strtoul (argv[4], NULL, 16);
-       if (off > sz) {
-               printf ("offset is greater than device size"
-                       "... aborting.\n");
-               return;
-       }
-       if ((off + cnt) > sz) {
-               printf ("request exceeds device size"
-                       "... truncating.\n");
-               cnt = sz - off;
-       }
-       printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n",
-                       addr, off, cnt);
-       if (epcs_verify (addr, off, cnt, &err) != 0)
-               printf ("epcs: verify error at offset %06lx\n", err);
-
-       return;
-}
-
-/*-----------------------------------------------------------------------*/
-int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       int len;
-       struct epcs_devinfo_t *dev = epcs_dev_find ();
-
-       if (!dev) {
-               printf ("epcs: device not found.\n");
-               return (-1);
-       }
-
-       if (argc < 2) {
-               do_epcs_info (dev, argc, argv);
-               return (0);
-       }
-
-       len = strlen (argv[1]);
-       if (strncmp ("info", argv[1], len) == 0) {
-               do_epcs_info (dev, argc, argv);
-       } else if (strncmp ("erase", argv[1], len) == 0) {
-               do_epcs_erase (dev, argc, argv);
-       } else if (strncmp ("protect", argv[1], len) == 0) {
-               do_epcs_protect (dev, argc, argv);
-       } else if (strncmp ("read", argv[1], len) == 0) {
-               do_epcs_read (dev, argc, argv);
-       } else if (strncmp ("write", argv[1], len) == 0) {
-               do_epcs_write (dev, argc, argv);
-       } else if (strncmp ("verify", argv[1], len) == 0) {
-               do_epcs_verify (dev, argc, argv);
-       } else {
-               printf ("epcs: unknown operation: %s\n", argv[1]);
-       }
-
-       return (0);
-}
-
-/*-----------------------------------------------------------------------*/
-
-
-U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP );
-
-#endif /* CONFIG_NIOS_EPCS */
index 7ce0d34..6af9b4e 100644 (file)
@@ -134,11 +134,12 @@ _reloc:
        mov     fp, sp
 
        /*
-        * Call board_init -- never returns
+        * Call board_init_f -- never returns
         */
-       movhi   r4, %hi(board_init@h)
-       ori     r4, r4, %lo(board_init@h)
-       callr   r4
+       mov     r4, r0
+       movhi   r2, %hi(board_init_f@h)
+       ori     r2, r2, %lo(board_init_f@h)
+       callr   r2
 
        /* NEVER RETURNS -- but branch to the _start just
         * in case ;-)
@@ -146,6 +147,31 @@ _reloc:
        br      _start
 
 
+
+/*
+ * relocate_code -- Nios2 handles the relocation above. But
+ * the generic board code monkeys with the heap, stack, etc.
+ * (it makes some assumptions that may not be appropriate
+ * for Nios). Nevertheless, we capitulate here.
+ *
+ * We'll call the board_init_r from here since this isn't
+ * supposed to return.
+ *
+ * void relocate_code (ulong sp, gd_t *global_data,
+ *                     ulong reloc_addr)
+ *                     __attribute__ ((noreturn));
+ */
+       .text
+       .global relocate_code
+
+relocate_code:
+       mov     sp, r4          /* Set the new sp */
+       mov     r4, r5
+       movhi   r8, %hi(board_init_r@h)
+       ori     r8, r8, %lo(board_init_r@h)
+       callr   r8
+       ret
+
 /*
  * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in
  * the core. For simple delay loops, we do our best by counting
index cd29734..476a32b 100644 (file)
@@ -7,4 +7,7 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
 #endif
index 6733640..6b6c39b 100644 (file)
@@ -16,7 +16,11 @@ typedef int          __kernel_pid_t;
 typedef unsigned short __kernel_ipc_pid_t;
 typedef unsigned short __kernel_uid_t;
 typedef unsigned short __kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__  __kernel_size_t;
+#else
 typedef unsigned long  __kernel_size_t;
+#endif
 typedef long           __kernel_ssize_t;
 typedef int            __kernel_ptrdiff_t;
 typedef long           __kernel_time_t;
index 51f6c30..cb02e98 100644 (file)
 #ifndef __ASM_NIOS2_U_BOOT_H_
 #define __ASM_NIOS2_U_BOOT_H_
 
-typedef struct bd_info {
-       unsigned long   bi_memstart;    /* start of DRAM memory */
-       phys_size_t     bi_memsize;     /* size  of DRAM memory in bytes */
-       unsigned long   bi_flashstart;  /* start of FLASH memory */
-       unsigned long   bi_flashsize;   /* size  of FLASH memory */
-       unsigned long   bi_flashoffset; /* reserved area for startup monitor */
-       unsigned long   bi_sramstart;   /* start of SRAM memory */
-       unsigned long   bi_sramsize;    /* size  of SRAM memory */
-} bd_t;
+#include <asm-generic/u-boot.h>
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_NIOS2
index 7cb25c0..079378a 100644 (file)
@@ -6,7 +6,6 @@
 #
 
 obj-y  += cache.o
-obj-y  += board.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y  += libgcc.o
 obj-y  += time.o
diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
deleted file mode 100644 (file)
index f24218f..0000000
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <stdio_dev.h>
-#include <watchdog.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <net.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#if defined(CONFIG_SYS_NIOS_EPCSBASE)
-#include <nios2-epcs.h>
-#endif
-#ifdef CONFIG_CMD_NAND
-#include <nand.h>      /* cannot even include nand.h if it isnt configured */
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-
-
-typedef int (init_fnc_t) (void);
-
-
-/************************************************************************
- * Initialization sequence                                             *
- ***********************************************************************/
-
-init_fnc_t *init_sequence[] = {
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-       board_early_init_f,     /* Call board-specific init code early.*/
-#endif
-#if defined(CONFIG_SYS_NIOS_EPCSBASE)
-       epcs_reset,
-#endif
-
-       env_init,
-       serial_init,
-       console_init_f,
-       display_options,
-       checkcpu,
-       checkboard,
-       NULL,                   /* Terminate this list */
-};
-
-
-/***********************************************************************/
-void board_init(void)
-{
-       bd_t *bd;
-       init_fnc_t **init_fnc_ptr;
-       static gd_t gd_data;
-       static bd_t bd_data;
-
-       /* Pointer is writable since we allocated a register for it. */
-       gd = &gd_data;
-       /* compiler optimization barrier needed for GCC >= 3.4 */
-       __asm__ __volatile__("" : : : "memory");
-
-       gd->bd = &bd_data;
-       gd->baudrate = CONFIG_BAUDRATE;
-       gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
-       bd = gd->bd;
-       bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-       bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
-       bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if    defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
-       bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
-       bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
-#endif
-
-       for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-               WATCHDOG_RESET();
-               if ((*init_fnc_ptr) () != 0)
-                       hang();
-       }
-
-       WATCHDOG_RESET();
-
-       /* The Malloc area is immediately below the monitor copy in RAM */
-       mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
-       WATCHDOG_RESET();
-       bd->bi_flashsize = flash_init();
-#endif
-
-#ifdef CONFIG_CMD_NAND
-       puts("NAND:  ");
-       nand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-       puts("MMC:   ");
-       mmc_initialize(bd);
-#endif
-
-       WATCHDOG_RESET();
-       env_relocate();
-
-       WATCHDOG_RESET();
-       stdio_init();
-       jumptable_init();
-       console_init_r();
-
-       WATCHDOG_RESET();
-       interrupt_init();
-
-#if defined(CONFIG_BOARD_LATE_INIT)
-       board_late_init();
-#endif
-
-#if defined(CONFIG_CMD_NET)
-       puts("Net:   ");
-       eth_initialize(bd);
-#endif
-
-       /* main_loop */
-       for (;;) {
-               WATCHDOG_RESET();
-               main_loop();
-       }
-}
index b237505..5bfab70 100644 (file)
@@ -254,12 +254,36 @@ static void enable_tdm_law(void)
 void enable_cpc(void)
 {
        int i;
+       int ret;
        u32 size = 0;
-
+       u32 cpccfg0;
+       char buffer[HWCONFIG_BUFFER_SIZE];
+       char cpc_subarg[16];
+       bool have_hwconfig = false;
+       int cpc_args = 0;
        cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
+       /* Extract hwconfig from environment */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0) {
+               /*
+                * If "en_cpc" is not defined in hwconfig then by default all
+                * cpcs are enable. If this config is defined then individual
+                * cpcs which have to be enabled should also be defined.
+                * e.g en_cpc:cpc1,cpc2;
+                */
+               if (hwconfig_f("en_cpc", buffer))
+                       have_hwconfig = true;
+       }
+
        for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
-               u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+               if (have_hwconfig) {
+                       sprintf(cpc_subarg, "cpc%u", i + 1);
+                       cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
+                       if (cpc_args == 0)
+                               continue;
+               }
+               cpccfg0 = in_be32(&cpc->cpccfg0);
                size += CPC_CFG0_SZ_K(cpccfg0);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
index 3665ec6..3222e26 100644 (file)
@@ -134,6 +134,21 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
                        printf("Failed to reserve memory for spin table: %s\n",
                                fdt_strerror(off));
        }
+#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_SPL_MMC_BOOT
+       off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
+               CONFIG_SYS_MMC_U_BOOT_SIZE);
+       if (off < 0)
+               printf("Failed to reserve memory for SD deep sleep: %s\n",
+                      fdt_strerror(off));
+#elif defined(CONFIG_SPL_SPI_BOOT)
+       off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
+               CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
+       if (off < 0)
+               printf("Failed to reserve memory for SPI deep sleep: %s\n",
+                      fdt_strerror(off));
+#endif
+#endif
 }
 #endif
 
index 35608a6..2c39244 100644 (file)
@@ -14,12 +14,6 @@ config TARGET_COGENT_MPC8XX
 config TARGET_ESTEEM192E
        bool "Support ESTEEM192E"
 
-config TARGET_FLAGADM
-       bool "Support FLAGADM"
-
-config TARGET_GEN860T
-       bool "Support GEN860T"
-
 config TARGET_HERMES
        bool "Support hermes"
 
@@ -47,15 +41,9 @@ config TARGET_R360MPI
 config TARGET_RRVISION
        bool "Support RRvision"
 
-config TARGET_SXNI855T
-       bool "Support SXNI855T"
-
 config TARGET_SPD823TS
        bool "Support SPD823TS"
 
-config TARGET_SVM_SC8XX
-       bool "Support svm_sc8xx"
-
 config TARGET_MHPC
        bool "Support MHPC"
 
@@ -74,9 +62,6 @@ config TARGET_ELPT860
 config TARGET_UC100
        bool "Support uc100"
 
-config TARGET_STXXTC
-       bool "Support stxxtc"
-
 config TARGET_FPS850L
        bool "Support FPS850L"
 
@@ -139,8 +124,6 @@ source "board/cogent/Kconfig"
 source "board/eltec/mhpc/Kconfig"
 source "board/emk/top860/Kconfig"
 source "board/esteem192e/Kconfig"
-source "board/flagadm/Kconfig"
-source "board/gen860t/Kconfig"
 source "board/hermes/Kconfig"
 source "board/icu862/Kconfig"
 source "board/ip860/Kconfig"
@@ -151,10 +134,7 @@ source "board/lwmon/Kconfig"
 source "board/manroland/uc100/Kconfig"
 source "board/netvia/Kconfig"
 source "board/r360mpi/Kconfig"
-source "board/sixnet/Kconfig"
 source "board/spd8xx/Kconfig"
-source "board/stx/stxxtc/Kconfig"
-source "board/svm_sc8xx/Kconfig"
 source "board/tqc/tqm8xx/Kconfig"
 
 endmenu
index e51fec7..90c7e61 100644 (file)
@@ -44,11 +44,7 @@ void cpu_init_f (volatile immap_t * immr)
 #endif /* CONFIG_WATCHDOG */
 
        /* SIUMCR - contains debug pin configuration (11-6) */
-#ifndef CONFIG_SVM_SC8xx
        immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
-#else
-       immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
-#endif
        /* initialize timebase status and control register (11-26) */
        /* unlock TBSCRK */
 
index 0296205..6eaab88 100644 (file)
@@ -366,6 +366,8 @@ void board_init_f(ulong bootflag)
        memset((void *) gd, 0, sizeof(gd_t));
 #endif
 
+       gd->flags = bootflag;
+
        for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr)
                if ((*init_fnc_ptr) () != 0)
                        hang();
index b823785..ef586b3 100644 (file)
@@ -1,6 +1,6 @@
 DM355EVM BOARD
 M:     Sandeep Paulraj <s-paulraj@ti.com>
-S:     Maintained
+S:     Orphan (since 2014-08)
 F:     board/davinci/dm355evm/
 F:     include/configs/davinci_dm355evm.h
 F:     configs/davinci_dm355evm_defconfig
index f17fea2..2fc1e00 100644 (file)
@@ -1,6 +1,6 @@
 DM355LEOPARD BOARD
 M:     Sandeep Paulraj <s-paulraj@ti.com>
-S:     Maintained
+S:     Orphan (since 2014-08)
 F:     board/davinci/dm355leopard/
 F:     include/configs/davinci_dm355leopard.h
 F:     configs/davinci_dm355leopard_defconfig
index 5adb4e0..0bfe02d 100644 (file)
@@ -1,6 +1,6 @@
 DM365EVM BOARD
 M:     Sandeep Paulraj <s-paulraj@ti.com>
-S:     Maintained
+S:     Orphan (since 2014-08)
 F:     board/davinci/dm365evm/
 F:     include/configs/davinci_dm365evm.h
 F:     configs/davinci_dm365evm_defconfig
index 4030bf3..bb40536 100644 (file)
@@ -1,6 +1,6 @@
 DM6467EVM BOARD
 M:     Sandeep Paulraj <s-paulraj@ti.com>
-S:     Maintained
+S:     Orphan (since 2014-08)
 F:     board/davinci/dm6467evm/
 F:     include/configs/davinci_dm6467evm.h
 F:     configs/davinci_dm6467evm_defconfig
diff --git a/board/flagadm/Kconfig b/board/flagadm/Kconfig
deleted file mode 100644 (file)
index bc0657e..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_FLAGADM
-
-config SYS_BOARD
-       string
-       default "flagadm"
-
-config SYS_CONFIG_NAME
-       string
-       default "FLAGADM"
-
-endif
diff --git a/board/flagadm/MAINTAINERS b/board/flagadm/MAINTAINERS
deleted file mode 100644 (file)
index 606989c..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-FLAGADM BOARD
-M:     Kári Davíðsson <kd@flaga.is>
-S:     Orphan (since 2014-06)
-F:     board/flagadm/
-F:     include/configs/FLAGADM.h
-F:     configs/FLAGADM_defconfig
diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile
deleted file mode 100644 (file)
index f2377c8..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = flagadm.o flash.o
diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c
deleted file mode 100644 (file)
index 343cb77..0000000
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define        _NOT_USED_      0xFFFFFFFF
-
-/*Orginal table, GPL4 disabled*/
-const uint sdram_table[] =
-{
-       /* single read   (offset 0x00 in upm ram) */
-       0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
-       0x1ff74c47,
-       /* Precharge */
-       0x1FF74C05,
-       _NOT_USED_,
-       _NOT_USED_,
-       /* burst read    (offset 0x08 in upm ram) */
-       0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
-       0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /* single write  (offset 0x18 in upm ram) */
-       0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
-       /* Load moderegister */
-       0x1FF74C34, /*Precharge*/
-       0xEFEA8C34, /*NOP*/
-       0x1FB54C35, /*Load moderegister*/
-       _NOT_USED_,
-
-       /* burst write   (offset 0x20 in upm ram) */
-       0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
-       0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /* refresh       (offset 0x30 in upm ram) */
-       0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
-       0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /* exception     (offset 0x3C in upm ram) */
-       0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* GPL5 driven every cycle */
-/* the display and the DSP */
-const uint dsp_disp_table[] =
-{
-       /* single read   (offset 0x00 in upm ram) */
-       0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
-       0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
-       /* burst read    (offset 0x08 in upm ram) */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /* single write  (offset 0x18 in upm ram) */
-       0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
-       0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
-       /* burst write   (offset 0x20 in upm ram) */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /* refresh       (offset 0x30 in upm ram) */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /* exception     (offset 0x3C in upm ram) */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-int checkboard (void)
-{
-       puts ("Board: FlagaDM V3.0\n");
-       return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-       volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       long int size_b0;
-
-       memctl->memc_or2 = CONFIG_SYS_OR2;
-       memctl->memc_br2 = CONFIG_SYS_BR2;
-
-       udelay(100);
-       upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
-       memctl->memc_mptpr = MPTPR_PTP_DIV16;
-       memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;
-
-       /*Do the initialization of the SDRAM*/
-       /*Start with the precharge cycle*/
-       memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
-                               MCR_MLCF(1) | MCR_MAD(0x5));
-
-       /*Then we need two refresh cycles*/
-       memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;
-       memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
-                               MCR_MLCF(2) | MCR_MAD(0x30));
-
-       /*Mode register programming*/
-       memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
-       memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
-                               MCR_MLCF(1) | MCR_MAD(0x1C));
-
-       /* That should do it, just enable the periodic refresh in burst of 4*/
-       memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;
-       memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
-
-       size_b0 = 16*1024*1024;
-
-       /*
-        * No bank 1 or 3
-        * invalidate bank
-        */
-       memctl->memc_br1 = 0;
-       memctl->memc_br3 = 0;
-
-       upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
-
-       memctl->memc_mbmr = MBMR_GPL_B4DIS;
-
-       memctl->memc_or4 = CONFIG_SYS_OR4;
-       memctl->memc_br4 = CONFIG_SYS_BR4;
-
-       return (size_b0);
-}
diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c
deleted file mode 100644 (file)
index 46a2c9a..0000000
+++ /dev/null
@@ -1,687 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <flash.h>
-
-flash_info_t   flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-ulong flash_recognize (vu_long *base);
-int write_word (flash_info_t *info, ulong dest, ulong data);
-void flash_get_geometry (vu_long *base, flash_info_t *info);
-void flash_unprotect(flash_info_t *info);
-int _flash_real_protect(flash_info_t *info, long idx, int on);
-
-
-unsigned long flash_init (void)
-{
-       volatile immap_t        *immap  = (immap_t *)CONFIG_SYS_IMMR;
-       volatile memctl8xx_t    *memctl = &immap->im_memctl;
-       int i;
-       int rec;
-
-       for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-               flash_info[i].flash_id = FLASH_UNKNOWN;
-       }
-
-       *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
-
-       flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       /* Remap FLASH according to real size */
-       memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000);
-       memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
-               (memctl->memc_br0 & ~(BR_BA_MSK));
-
-       rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE);
-
-       if (rec == FLASH_UNKNOWN) {
-               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-                               flash_info[0].size, flash_info[0].size<<20);
-       }
-
-#if CONFIG_SYS_FLASH_PROTECTION
-       /*Unprotect all the flash memory*/
-       flash_unprotect(&flash_info[0]);
-#endif
-
-       *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
-
-       return (flash_info[0].size);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_SYS_MONITOR_BASE,
-                     CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-                     &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-       /* ENV protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_ENV_OFFSET,
-                     CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1,
-                     &flash_info[0]);
-#endif
-       return (flash_info[0].size);
-}
-
-
-int flash_get_protect_status(flash_info_t * info, long idx)
-{
-       vu_short * base;
-       ushort res;
-
-#ifdef DEBUG
-       printf("\n Attempting to set protection info with %d sectors\n", info->sector_count);
-#endif
-
-
-       base = (vu_short*)info->start[idx];
-
-       *(base) = 0xffff;
-
-       *(base + 0x55) = 0x0098;
-       res = base[0x2];
-
-       *(base) = 0xffff;
-
-       if(res != 0)
-               res = 1;
-       else
-               res = 0;
-
-       return res;
-}
-
-void flash_get_geometry (vu_long *base, flash_info_t *info)
-{
-       int i,j;
-       ulong ner = 0;
-       vu_short * sb  = (vu_short*)base;
-       ulong offset = (ulong)base;
-
-       /* Read Device geometry */
-
-       *sb = 0xffff;
-
-       *sb = 0x0090;
-
-       info->flash_id = ((ulong)base[0x0]);
-#ifdef DEBUG
-       printf("Id is %x\n", (uint)(ulong)info->flash_id);
-#endif
-
-       *sb = 0xffff;
-
-       *(sb+0x55) = 0x0098;
-
-       info->size = 1 << (sb[0x27]); /* Read flash size */
-
-#ifdef DEBUG
-       printf("Size is %x\n", (uint)(ulong)info->size);
-#endif
-
-       *sb = 0xffff;
-
-       *(sb + 0x55) = 0x0098;
-       ner = sb[0x2c] ; /*Number of erase regions*/
-
-#ifdef DEBUG
-       printf("Number of erase regions %x\n", (uint)ner);
-#endif
-
-       info->sector_count = 0;
-
-       for(i = 0; i < ner; i++)
-       {
-               uint s;
-               uint count;
-               uint t1,t2,t3,t4;
-
-               *sb = 0xffff;
-
-               *(sb + 0x55) = 0x0098;
-
-               t1 = sb[0x2d + i*4];
-               t2 = sb[0x2e + i*4];
-               t3 = sb[0x2f + i*4];
-               t4 = sb[0x30 + i*4];
-
-               count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/
-               s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/
-
-#ifdef DEBUG
-               printf("count and size %x, %x\n", count, s);
-               printf("sector count for erase region %d is %d\n", i, count);
-#endif
-               for(j = 0; j < count; j++)
-               {
-#ifdef DEBUG
-                       printf("%x, ", (uint)offset);
-#endif
-                       info->start[ info->sector_count + j] = offset;
-                       offset += s;
-               }
-               info->sector_count += count;
-       }
-
-       if ((offset - (ulong)base) != info->size)
-               printf("WARNING reported size %x does not match to calculted size %x.\n"
-                               , (uint)info->size, (uint)(offset - (ulong)base) );
-
-       /* Next check if there are any sectors protected.*/
-
-       for(i = 0; i < info->sector_count; i++)
-               info->protect[i] = flash_get_protect_status(info, i);
-
-       *sb = 0xffff;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf ("missing or unknown FLASH type\n");
-               return ;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case INTEL_MANUFACT & FLASH_VENDMASK:
-               printf ("Intel ");
-               break;
-       default:
-               printf ("Unknown Vendor ");
-               break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case INTEL_ID_28F320C3B & FLASH_TYPEMASK:
-               printf ("28F320RC3(4 MB)\n");
-               break;
-       case INTEL_ID_28F320J3A:
-               printf("28F320J3A (4 MB)\n");
-               break;
-       default:
-               printf ("Unknown Chip Type\n");
-                       break;
-       }
-
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20, info->sector_count);
-
-       printf ("  Sector Start Addresses:");
-       for (i=0; i<info->sector_count; ++i) {
-               if ((i % 4) == 0)
-                       printf ("\n   ");
-               printf ("  %02d %08lX%s",
-                       i, info->start[i],
-                       info->protect[i]!=0 ? " (RO)" : "     "
-               );
-       }
-       printf ("\n");
-       return ;
-}
-
-ulong flash_recognize (vu_long *base)
-{
-       ulong id;
-       ulong res = FLASH_UNKNOWN;
-       vu_short * sb = (vu_short*)base;
-
-       *sb = 0xffff;
-
-       *sb = 0x0090;
-       id = base[0];
-
-       switch (id & 0x00FF0000)
-       {
-               case (MT_MANUFACT & 0x00FF0000):        /* MT or => Intel */
-               case (INTEL_ALT_MANU & 0x00FF0000):
-               res = FLASH_MAN_INTEL;
-               break;
-       default:
-               res = FLASH_UNKNOWN;
-       }
-
-       *sb = 0xffff;
-
-       return res;
-}
-
-/*-----------------------------------------------------------------------*/
-#define INTEL_FLASH_STATUS_BLS 0x02
-#define INTEL_FLASH_STATUS_PSS 0x04
-#define INTEL_FLASH_STATUS_VPPS        0x08
-#define INTEL_FLASH_STATUS_PS  0x10
-#define INTEL_FLASH_STATUS_ES  0x20
-#define INTEL_FLASH_STATUS_ESS 0x40
-#define INTEL_FLASH_STATUS_WSMS        0x80
-
-int    flash_decode_status_bits(char status)
-{
-       int err = 0;
-
-       if(!(status & INTEL_FLASH_STATUS_WSMS)) {
-               printf("Busy\n");
-               err = -1;
-       }
-
-       if(status & INTEL_FLASH_STATUS_ESS) {
-               printf("Erase suspended\n");
-               err = -1;
-       }
-
-       if(status & INTEL_FLASH_STATUS_ES) {
-               printf("Error in block erase\n");
-               err = -1;
-       }
-
-       if(status & INTEL_FLASH_STATUS_PS) {
-               printf("Error in programming\n");
-               err = -1;
-       }
-
-       if(status & INTEL_FLASH_STATUS_VPPS) {
-               printf("Vpp low, operation aborted\n");
-               err = -1;
-       }
-
-       if(status & INTEL_FLASH_STATUS_PSS) {
-               printf("Program is suspended\n");
-               err = -1;
-       }
-
-       if(status & INTEL_FLASH_STATUS_BLS) {
-               printf("Attempting to program/erase a locked sector\n");
-               err = -1;
-       }
-
-       if((status & INTEL_FLASH_STATUS_PS) &&
-          (status & INTEL_FLASH_STATUS_ES) &&
-          (status & INTEL_FLASH_STATUS_ESS)) {
-               printf("A command sequence error\n");
-               return -1;
-       }
-
-       return err;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int    flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-       vu_short *addr;
-       int flag, prot, sect;
-       ulong start, now;
-       int rcode = 0;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf ("- missing\n");
-               } else {
-                       printf ("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
-               printf ("Can't erase unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect=s_first; sect<=s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf ("- Warning: %d protected sectors will not be erased!\n",
-                       prot);
-       } else {
-               printf ("\n");
-       }
-
-       start = get_timer (0);
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect<=s_last; sect++) {
-               char tmp;
-
-               if (info->protect[sect] == 0) { /* not protected */
-                       addr = (vu_short *)(info->start[sect]);
-
-                       /* Disable interrupts which might cause a timeout here */
-                       flag = disable_interrupts();
-
-                       /* Single Block Erase Command */
-                       *addr = 0x0020;
-                       /* Confirm */
-                       *addr = 0x00D0;
-                       /* Resume Command, as per errata update */
-                       *addr = 0x00D0;
-
-                       /* re-enable interrupts if necessary */
-                       if (flag)
-                               enable_interrupts();
-
-                       *addr = 0x70; /*Read status register command*/
-                       tmp = (short)*addr & 0x00FF; /* Read the status */
-                       while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
-                               if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-                                       *addr = 0x0050; /* Reset the status register */
-                                       *addr = 0xffff;
-                                       printf ("Timeout\n");
-                                       return 1;
-                               }
-                               /* show that we're waiting */
-                               if ((now - start) > 1000) {     /* every second */
-                                       putc ('.');
-                               }
-                               udelay(100000); /* 100 ms */
-                               *addr = 0x0070; /*Read status register command*/
-                               tmp = (short)*addr & 0x00FF; /* Read status */
-                               start = get_timer(0);
-                       }
-                       if( tmp & INTEL_FLASH_STATUS_ES )
-                               flash_decode_status_bits(tmp);
-
-                       *addr = 0x0050; /* Reset the status register */
-                       *addr = 0xffff; /* Reset to read mode */
-               }
-       }
-
-
-       printf (" done\n");
-       return rcode;
-}
-
-void flash_unprotect (flash_info_t *info)
-{
-       /*We can only unprotect the whole flash at once*/
-       /*Therefore we must prevent the _flash_real_protect()*/
-       /*from re-protecting sectors, that ware protected before */
-       /*we called flash_real_protect();*/
-
-       int i;
-
-       for(i = 0; i < info->sector_count; i++)
-               info->protect[i] = 0;
-
-#ifdef CONFIG_SYS_FLASH_PROTECTION
-               _flash_real_protect(info, 0, 0);
-#endif
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-       ulong cp, wp, data;
-       int i, l, rc;
-
-       wp = (addr & ~3);       /* get lower word aligned address */
-
-       /*
-        * handle unaligned start bytes
-        */
-       if ((l = addr - wp) != 0) {
-               data = 0;
-               for (i=0, cp=wp; i<l; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
-               for (; i<4 && cnt>0; ++i) {
-                       data = (data << 8) | *src++;
-                       --cnt;
-                       ++cp;
-               }
-               for (; cnt==0 && i<4; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
-
-               if ((rc = write_word(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += 4;
-       }
-
-       /*
-        * handle word aligned part
-        */
-       while (cnt >= 4) {
-               data = 0;
-               for (i=0; i<4; ++i) {
-                       data = (data << 8) | *src++;
-               }
-               if ((rc = write_word(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp  += 4;
-               cnt -= 4;
-       }
-
-       if (cnt == 0) {
-               return (0);
-       }
-
-       /*
-        * handle unaligned tail bytes
-        */
-       data = 0;
-       for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-               data = (data << 8) | *src++;
-               --cnt;
-       }
-       for (; i<4; ++i, ++cp) {
-               data = (data << 8) | (*(uchar *)cp);
-       }
-
-       return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_word (flash_info_t *info, ulong dest, ulong da)
-{
-       vu_short *addr = (vu_short *)dest;
-       ulong start;
-       char csr;
-       int flag;
-       int i;
-       union {
-               u32 data32;
-               u16 data16[2];
-       } data;
-
-       data.data32 = da;
-
-       /* Check if Flash is (sufficiently) erased */
-       if (((*addr & data.data16[0]) != data.data16[0]) ||
-           ((*(addr+1) & data.data16[1]) != data.data16[1])) {
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       for(i = 0; i < 2; i++)
-       {
-               /* Write Command */
-               *addr = 0x0010;
-
-               /* Write Data */
-               *addr = data.data16[i];
-
-               /* re-enable interrupts if necessary */
-               if (flag)
-                       enable_interrupts();
-
-               /* data polling for D7 */
-               start = get_timer (0);
-               flag  = 0;
-               *addr = 0x0070; /*Read statusregister command */
-               while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) {
-                       if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                               flag = 1;
-                               break;
-                       }
-                       *addr = 0x0070; /*Read statusregister command */
-               }
-               if (csr & INTEL_FLASH_STATUS_PSS) {
-                       printf ("CSR indicates write error (%0x) at %08lx\n",
-                                       csr, (ulong)addr);
-                       flag = 1;
-               }
-
-               /* Clear Status Registers Command */
-               *addr = 0x0050;
-               /* Reset to read array mode */
-               *addr = 0xffff;
-               addr++;
-       }
-
-       return (flag);
-}
-
-int flash_real_protect(flash_info_t *info, long offset, int prot)
-{
-       int i, idx;
-
-       for(idx = 0; idx < info->sector_count; idx++)
-               if(info->start[idx] == offset)
-                       break;
-
-       if(idx==info->sector_count)
-               return -1;
-
-       if(prot == 0) {
-               /* Unprotect one sector, which means unprotect all flash
-                * and reprotect the other protected sectors.
-                */
-               _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/
-               info->protect[idx] = 0;
-
-               for(i = 0; i < info->sector_count; i++)
-                       if(info->protect[i])
-                               _flash_real_protect(info, i, 1);
-               }
-       else {
-               /* We can protect individual sectors */
-               _flash_real_protect(info, idx, 1);
-       }
-
-       for( i = 0; i < info->sector_count; i++)
-               info->protect[i] = flash_get_protect_status(info, i);
-
-       return 0;
-}
-
-int _flash_real_protect(flash_info_t *info, long idx, int prot)
-{
-       vu_short *addr;
-       int flag;
-       ushort cmd;
-       ushort tmp;
-       ulong now, start;
-
-       if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
-               printf ("Can't change protection for unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return -1;
-       }
-
-       if(prot == 0) {
-               /*Unlock the sector*/
-               cmd = 0x00D0;
-       }
-       else {
-               /*Lock the sector*/
-               cmd = 0x0001;
-       }
-
-       addr = (vu_short *)(info->start[idx]);
-
-       /* If chip is busy, wait for it */
-       start = get_timer(0);
-       *addr = 0x0070; /*Read status register command*/
-       tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
-       while(!(tmp & INTEL_FLASH_STATUS_WSMS)) {
-               /*Write State Machine Busy*/
-               /*Wait untill done or timeout.*/
-               if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       *addr = 0x0050; /* Reset the status register */
-                       *addr = 0xffff; /* Reset the chip */
-                       printf ("TTimeout\n");
-                       return 1;
-               }
-               *addr = 0x0070;
-               tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
-               start = get_timer(0);
-       }
-
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       /* Unlock block*/
-       *addr = 0x0060;
-
-       *addr = cmd;
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       start = get_timer(0);
-       *addr = 0x0070; /*Read status register command*/
-       tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */
-       while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
-               /* Write State Machine Busy */
-               if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       *addr = 0x0050; /* Reset the status register */
-                       *addr = 0xffff;
-                       printf ("Timeout\n");
-                       return 1;
-               }
-               /* show that we're waiting */
-               if ((now - start) > 1000) {     /* every second */
-                       putc ('.');
-               }
-               udelay(100000); /* 100 ms */
-               *addr = 0x70; /*Read status register command*/
-               tmp = (short)*addr & 0x00FF; /* Read status */
-               start = get_timer(0);
-       }
-       if( tmp & INTEL_FLASH_STATUS_PS )
-               flash_decode_status_bits(tmp);
-
-       *addr =0x0050; /*Clear status register*/
-
-       /* reset to read mode */
-       *addr = 0xffff;
-
-       return 0;
-}
diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds
deleted file mode 100644 (file)
index 7ae91ff..0000000
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o    (.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o    (.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug
deleted file mode 100644 (file)
index b0091db..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)          }
-  .dynsym        : { *(.dynsym)                }
-  .dynstr        : { *(.dynstr)                }
-  .rel.text      : { *(.rel.text)              }
-  .rela.text     : { *(.rela.text)     }
-  .rel.data      : { *(.rel.data)              }
-  .rela.data     : { *(.rela.data)     }
-  .rel.rodata    : { *(.rel.rodata)    }
-  .rela.rodata   : { *(.rela.rodata)   }
-  .rel.got       : { *(.rel.got)               }
-  .rela.got      : { *(.rela.got)              }
-  .rel.ctors     : { *(.rel.ctors)     }
-  .rela.ctors    : { *(.rela.ctors)    }
-  .rel.dtors     : { *(.rel.dtors)     }
-  .rela.dtors    : { *(.rela.dtors)    }
-  .rel.bss       : { *(.rel.bss)               }
-  .rela.bss      : { *(.rela.bss)              }
-  .rel.plt       : { *(.rel.plt)               }
-  .rela.plt      : { *(.rela.plt)              }
-  .init          : { *(.init)  }
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within */
-    /* the sector layout of our flash chips!   XXX FIXME XXX   */
-
-    arch/powerpc/cpu/mpc8xx/start.o    (.text)
-    common/dlmalloc.o  (.text)
-    lib/vsprintf.o     (.text)
-    lib/crc32.o                (.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
index 22b57cc..50d7731 100644 (file)
@@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL
 obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)   += sdhc_boot.o
 endif
 
+obj-$(CONFIG_FSL_DIU_CH7301)   += diu_ch7301.o
+
 obj-$(CONFIG_MPC8541CDS)       += cds_pci_ft.o
 obj-$(CONFIG_MPC8548CDS)       += cds_pci_ft.o
 obj-$(CONFIG_MPC8555CDS)       += cds_pci_ft.o
diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c
new file mode 100644 (file)
index 0000000..82ce870
--- /dev/null
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *         Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * This file is copied and modified from the original t1040qds/diu.c.
+ * Encoder can be used in T104x and LSx Platform.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <i2c.h>
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG          0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG            0x33
+#define I2C_DVI_PLL_DIVIDER_REG                        0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG            0x35
+#define I2C_DVI_PLL_FILTER_REG                 0x36
+#define I2C_DVI_TEST_PATTERN_REG               0x48
+#define I2C_DVI_POWER_MGMT_REG                 0x49
+#define I2C_DVI_LOCK_STATE_REG                 0x4D
+#define I2C_DVI_SYNC_POLARITY_REG              0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL          0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL     0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL      0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL  0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL      0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL       0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL               0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL                 0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL              0x00
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+       int ret;
+       u8 temp;
+
+       temp = I2C_DVI_TEST_PATTERN_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+                       &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select proper dvi test pattern\n");
+               return ret;
+       }
+       temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+                       1, &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select dvi input data format\n");
+               return ret;
+       }
+
+       /* Set Sync polarity register */
+       temp = I2C_DVI_SYNC_POLARITY_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+                       &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select dvi syc polarity\n");
+               return ret;
+       }
+
+       /* Set PLL registers based on pixel clock rate*/
+       if (pixclock > 65000000) {
+               temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll charge_cntl\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll divider\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll filter\n");
+                       return ret;
+               }
+       } else {
+               temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll charge_cntl\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll divider\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll filter\n");
+                       return ret;
+               }
+       }
+
+       temp = I2C_DVI_POWER_MGMT_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+                       &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select dvi power mgmt\n");
+               return ret;
+       }
+
+       udelay(500);
+
+       return 0;
+}
diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h
new file mode 100644 (file)
index 0000000..8b6ead0
--- /dev/null
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DIU_HDMI_CH7301__
+#define __DIU_HDMI_CH7301__
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock);
+
+#endif
index ffd074b..0214224 100644 (file)
 #include <video_fb.h>
 #include <fsl_diu_fb.h>
 #include "../common/qixis.h"
+#include "../common/diu_ch7301.h"
 #include "t1040qds.h"
 #include "t1040qds_qixis.h"
-#include <i2c.h>
-
-
-#define I2C_DVI_INPUT_DATA_FORMAT_REG          0x1F
-#define I2C_DVI_PLL_CHARGE_CNTL_REG            0x33
-#define I2C_DVI_PLL_DIVIDER_REG                        0x34
-#define I2C_DVI_PLL_SUPPLY_CNTL_REG            0x35
-#define I2C_DVI_PLL_FILTER_REG                 0x36
-#define I2C_DVI_TEST_PATTERN_REG               0x48
-#define I2C_DVI_POWER_MGMT_REG                 0x49
-#define I2C_DVI_LOCK_STATE_REG                 0x4D
-#define I2C_DVI_SYNC_POLARITY_REG              0x56
-
-/*
- * Set VSYNC/HSYNC to active high. This is polarity of sync signals
- * from DIU->DVI. The DIU default is active igh, so DVI is set to
- * active high.
- */
-#define I2C_DVI_INPUT_DATA_FORMAT_VAL          0x98
-
-#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
-#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL     0x26
-#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL      0xA0
-#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL  0x08
-#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL      0x16
-#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL       0x60
-
-/* Clear test pattern */
-#define I2C_DVI_TEST_PATTERN_VAL               0x18
-/* Exit Power-down mode */
-#define I2C_DVI_POWER_MGMT_VAL                 0xC0
-
-/* Monitor polarity is handled via DVI Sync Polarity Register */
-#define I2C_DVI_SYNC_POLARITY_VAL              0x00
 
 /*
  * DIU Area Descriptor
 #define AD_COMP_1_SHIFT                4
 #define AD_COMP_0_SHIFT                0
 
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock)
-{
-       int ret;
-       u8 temp;
-       select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
-
-       temp = I2C_DVI_TEST_PATTERN_VAL;
-       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
-                       &temp, 1);
-       if (ret) {
-               puts("I2C: failed to select proper dvi test pattern\n");
-               return ret;
-       }
-       temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
-       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
-                       1, &temp, 1);
-       if (ret) {
-               puts("I2C: failed to select dvi input data format\n");
-               return ret;
-       }
-
-       /* Set Sync polarity register */
-       temp = I2C_DVI_SYNC_POLARITY_VAL;
-       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
-                       &temp, 1);
-       if (ret) {
-               puts("I2C: failed to select dvi syc polarity\n");
-               return ret;
-       }
-
-       /* Set PLL registers based on pixel clock rate*/
-       if (pixclock > 65000000) {
-               temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
-               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-                               I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
-               if (ret) {
-                       puts("I2C: failed to select dvi pll charge_cntl\n");
-                       return ret;
-               }
-               temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
-               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-                               I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-               if (ret) {
-                       puts("I2C: failed to select dvi pll divider\n");
-                       return ret;
-               }
-               temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
-               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-                               I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-               if (ret) {
-                       puts("I2C: failed to select dvi pll filter\n");
-                       return ret;
-               }
-       } else {
-               temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
-               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-                               I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
-               if (ret) {
-                       puts("I2C: failed to select dvi pll charge_cntl\n");
-                       return ret;
-               }
-               temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
-               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-                               I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-               if (ret) {
-                       puts("I2C: failed to select dvi pll divider\n");
-                       return ret;
-               }
-               temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
-               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-                               I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-               if (ret) {
-                       puts("I2C: failed to select dvi pll filter\n");
-                       return ret;
-               }
-       }
-
-       temp = I2C_DVI_POWER_MGMT_VAL;
-       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
-                       &temp, 1);
-       if (ret) {
-               puts("I2C: failed to select dvi power mgmt\n");
-               return ret;
-       }
-
-       udelay(500);
-
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-       return 0;
-}
-
 void diu_set_pixel_clock(unsigned int pixclock)
 {
        unsigned long speed_ccb, temp;
@@ -172,12 +47,19 @@ void diu_set_pixel_clock(unsigned int pixclock)
        pixval = speed_ccb / temp;
 
        /* Program HDMI encoder */
+       /* Switch channel to DIU */
+       select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+       /* Set dispaly encoder */
        ret = diu_set_dvi_encoder(temp);
        if (ret) {
                puts("Failed to set DVI encoder\n");
                return;
        }
 
+       /* Switch channel to default */
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
        /* Program pixel clock */
        out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
                 ((pixval << PXCK_BITS_START) & PXCK_MASK));
index 6cd304c..b9ef17f 100644 (file)
@@ -11,6 +11,7 @@ obj-y += t104xrdb.o
 obj-y  += cpld.o
 obj-y  += eth.o
 obj-$(CONFIG_PCI)      += pci.o
+obj-$(CONFIG_FSL_DIU_FB)+= diu.o
 endif
 obj-y  += ddr.o
 obj-y  += law.o
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
new file mode 100644 (file)
index 0000000..3285bef
--- /dev/null
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <command.h>
+#include <fsl_diu_fb.h>
+#include <linux/ctype.h>
+#include <video_fb.h>
+
+#include "../common/diu_ch7301.h"
+
+#include "cpld.h"
+#include "t104xrdb.h"
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F              0x10000000
+#define AD_ALPHA_C_SHIFT       25
+#define AD_BLUE_C_SHIFT                23
+#define AD_GREEN_C_SHIFT       21
+#define AD_RED_C_SHIFT         19
+#define AD_PIXEL_S_SHIFT       16
+#define AD_COMP_3_SHIFT                12
+#define AD_COMP_2_SHIFT                8
+#define AD_COMP_1_SHIFT                4
+#define AD_COMP_0_SHIFT                0
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+       unsigned long speed_ccb, temp;
+       u32 pixval;
+       int ret;
+
+       speed_ccb = get_bus_freq(0);
+       temp = 1000000000 / pixclock;
+       temp *= 1000;
+       pixval = speed_ccb / temp;
+
+       /* Program HDMI encoder */
+       ret = diu_set_dvi_encoder(temp);
+       if (ret) {
+               puts("Failed to set DVI encoder\n");
+               return;
+       }
+
+       /* Program pixel clock */
+       out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+                ((pixval << PXCK_BITS_START) & PXCK_MASK));
+
+       /* enable clock*/
+       out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+                ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+       u32 pixel_format;
+       u8 sw;
+
+       /*Configure Display ouput port as HDMI*/
+       sw = CPLD_READ(sfp_ctl_status);
+       CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
+
+       pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+               (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+               (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+               (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+               (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+       printf("DIU: Switching to monitor DVI @ %ux%u\n",  xres, yres);
+
+       return fsl_diu_init(xres, yres, pixel_format, 0);
+}
index c628c95..3822a37 100644 (file)
@@ -11,6 +11,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
+#include <asm/mpc85xx_gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,6 +56,11 @@ void board_init_f(ulong bootflag)
        /* Update GD pointer */
        gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
 
+#ifdef CONFIG_DEEP_SLEEP
+       /* disable the console if boot from deep sleep */
+       if (in_be32(&gur->scrtsr[0]) & (1 << 3))
+               gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
        /* compiler optimization barrier needed for GCC >= 3.4 */
        __asm__ __volatile__("" : : : "memory");
 
@@ -120,3 +126,16 @@ void board_init_r(gd_t *gd, ulong dest_addr)
        nand_boot();
 #endif
 }
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+       void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+       /* does not provide HW signals for power management */
+       clrbits_8(cpld_base + 0x17, 0x40);
+       /* Disable MCKE isolation */
+       gpio_set_value(2, 0);
+       udelay(1);
+}
+#endif
similarity index 86%
rename from doc/README.t4240qds
rename to board/freescale/t4qds/README
index ef8c75f..3962fee 100644 (file)
@@ -79,6 +79,25 @@ Board Features
                - High-speed serial flash
        Two Serial port
        Four I2C ports
+  XFI
+       XFI is supported on T4QDS-XFI board which removed slot3 and routed
+       four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
+       direct attach cable(copper), the copper cable is used to emulate
+       10GBASE-KR scenario.
+       So, for XFI usage, there are two scenarios, one will use fiber cable,
+       another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
+       introduced to indicate a XFI port will use copper cable, and U-boot
+       will fixup the dtb accordingly.
+       It's used as: fsl_10gkr_copper:<10g_mac_name>
+       The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
+       do not have to be coexist in hwconfig. If a MAC is listed in the env
+       "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
+       will be used by default.
+       for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in
+       hwconfig, then both four XFI ports will use copper cable.
+       set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
+       XFI ports will use copper cable, the other two XFI ports will use fiber
+       cable.
 
 Memory map
 ----------
index 6210e46..9b416b1 100644 (file)
@@ -23,6 +23,7 @@
 #include <phy.h>
 #include <asm/fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
+#include <hwconfig.h>
 #include "../common/qixis.h"
 #include "../common/fman.h"
 
@@ -173,6 +174,10 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
                                enum fm_port port, int offset)
 {
        int interface = fm_info_get_enet_if(port);
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+       prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 
        if (interface == PHY_INTERFACE_MODE_SGMII ||
            interface == PHY_INTERFACE_MODE_QSGMII) {
@@ -262,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
                default:
                        break;
                }
+       } else if (interface == PHY_INTERFACE_MODE_XGMII &&
+                 ((prtcl2 == 55) || (prtcl2 == 57))) {
+               /*
+                * if the 10G is XFI, check hwconfig to see what is the
+                * media type, there are two types, fiber or copper,
+                * fix the dtb accordingly.
+                */
+               int media_type = 0;
+               struct fixed_link f_link;
+               char lane_mode[20] = {"10GBASE-KR"};
+               char buf[32] = "serdes-2,";
+               int off;
+
+               switch (port) {
+               case FM1_10GEC1:
+                       if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_xfi1");
+                               sprintf(buf, "%s%s%s", buf, "lane-a,",
+                                       (char *)lane_mode);
+                       }
+                       break;
+               case FM1_10GEC2:
+                       if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_xfi2");
+                               sprintf(buf, "%s%s%s", buf, "lane-b,",
+                                       (char *)lane_mode);
+                       }
+                       break;
+               case FM2_10GEC1:
+                       if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_xfi3");
+                               sprintf(buf, "%s%s%s", buf, "lane-d,",
+                                       (char *)lane_mode);
+                       }
+                       break;
+               case FM2_10GEC2:
+                       if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_xfi4");
+                               sprintf(buf, "%s%s%s", buf, "lane-c,",
+                                       (char *)lane_mode);
+                       }
+                       break;
+               default:
+                       return;
+               }
+
+               if (!media_type) {
+                       /* fixed-link is used for XFI fiber cable */
+                       fdt_delprop(blob, offset, "phy-handle");
+                       f_link.phy_id = port;
+                       f_link.duplex = 1;
+                       f_link.link_speed = 10000;
+                       f_link.pause = 0;
+                       f_link.asym_pause = 0;
+                       fdt_setprop(blob, offset, "fixed-link", &f_link,
+                                   sizeof(f_link));
+               } else {
+                       /* set property for copper cable */
+                       off = fdt_node_offset_by_compat_reg(blob,
+                                       "fsl,fman-memac-mdio", pa + 0x1000);
+                       fdt_setprop_string(blob, off, "lane-instance", buf);
+               }
        }
 }
 
@@ -295,8 +370,23 @@ void fdt_fixup_board_enet(void *fdt)
                        break;
                case PHY_INTERFACE_MODE_XGMII:
                        /* check if it's XFI interface for 10g */
-                       if ((prtcl2 == 56) || (prtcl2 == 57)) {
-                               fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
+                       if ((prtcl2 == 55) || (prtcl2 == 57)) {
+                               if (i == FM1_10GEC1 && hwconfig_sub(
+                                       "fsl_10gkr_copper", "fm1_10g1"))
+                                       fdt_status_okay_by_alias(
+                                       fdt, "xfi_pcs_mdio1");
+                               if (i == FM1_10GEC2 && hwconfig_sub(
+                                       "fsl_10gkr_copper", "fm1_10g2"))
+                                       fdt_status_okay_by_alias(
+                                       fdt, "xfi_pcs_mdio2");
+                               if (i == FM2_10GEC1 && hwconfig_sub(
+                                       "fsl_10gkr_copper", "fm2_10g1"))
+                                       fdt_status_okay_by_alias(
+                                       fdt, "xfi_pcs_mdio3");
+                               if (i == FM2_10GEC2 && hwconfig_sub(
+                                       "fsl_10gkr_copper", "fm2_10g2"))
+                                       fdt_status_okay_by_alias(
+                                       fdt, "xfi_pcs_mdio4");
                                break;
                        }
                        switch (i) {
@@ -460,7 +550,7 @@ int board_eth_init(bd_t *bis)
                fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
                fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
                fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
-               if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+               if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
                        fm_info_set_phy_address(FM1_DTSEC9,
                                                slot_qsgmii_phyaddr[1][3]);
                        fm_info_set_phy_address(FM1_DTSEC10,
@@ -475,7 +565,7 @@ int board_eth_init(bd_t *bis)
                fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
                fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
                fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
-               if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+               if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
                        fm_info_set_phy_address(FM1_DTSEC9,
                                                slot_qsgmii_phyaddr[1][2]);
                        fm_info_set_phy_address(FM1_DTSEC10,
@@ -490,7 +580,7 @@ int board_eth_init(bd_t *bis)
        case 48:
                fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
                fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
-               if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+               if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
                        fm_info_set_phy_address(FM1_DTSEC10,
                                                slot_qsgmii_phyaddr[1][2]);
                        fm_info_set_phy_address(FM1_DTSEC9,
@@ -567,13 +657,18 @@ int board_eth_init(bd_t *bis)
                idx = i - FM1_10GEC1;
                switch (fm_info_get_enet_if(i)) {
                case PHY_INTERFACE_MODE_XGMII:
-                       lane = serdes_get_first_lane(FSL_SRDS_1,
+                       if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
+                               /* A fake PHY address to make U-boot happy */
+                               fm_info_set_phy_address(i, i);
+                       } else {
+                               lane = serdes_get_first_lane(FSL_SRDS_1,
                                                XAUI_FM1_MAC9 + idx);
-                       if (lane < 0)
-                               break;
-                       slot = lane_to_slot_fsm1[lane];
-                       if (QIXIS_READ(present2) & (1 << (slot - 1)))
-                               fm_disable_port(i);
+                               if (lane < 0)
+                                       break;
+                               slot = lane_to_slot_fsm1[lane];
+                               if (QIXIS_READ(present2) & (1 << (slot - 1)))
+                                       fm_disable_port(i);
+                       }
                        mdio_mux[i] = EMI2;
                        fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
                        break;
@@ -666,7 +761,7 @@ int board_eth_init(bd_t *bis)
                fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
                fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
                break;
-       case 56:
+       case 55:
        case 57:
                /* XFI in Slot3, SGMII in Slot4 */
                fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -743,13 +838,18 @@ int board_eth_init(bd_t *bis)
                idx = i - FM2_10GEC1;
                switch (fm_info_get_enet_if(i)) {
                case PHY_INTERFACE_MODE_XGMII:
-                       lane = serdes_get_first_lane(FSL_SRDS_2,
+                       if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
+                               /* A fake PHY address to make U-boot happy */
+                               fm_info_set_phy_address(i, i);
+                       } else {
+                               lane = serdes_get_first_lane(FSL_SRDS_2,
                                                XAUI_FM2_MAC9 + idx);
-                       if (lane < 0)
-                               break;
-                       slot = lane_to_slot_fsm2[lane];
-                       if (QIXIS_READ(present2) & (1 << (slot - 1)))
-                               fm_disable_port(i);
+                               if (lane < 0)
+                                       break;
+                               slot = lane_to_slot_fsm2[lane];
+                               if (QIXIS_READ(present2) & (1 << (slot - 1)))
+                                       fm_disable_port(i);
+                       }
                        mdio_mux[i] = EMI2;
                        fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
                        break;
diff --git a/board/gen860t/Kconfig b/board/gen860t/Kconfig
deleted file mode 100644 (file)
index 438f7cc..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_GEN860T
-
-config SYS_BOARD
-       string
-       default "gen860t"
-
-config SYS_CONFIG_NAME
-       string
-       default "GEN860T"
-
-endif
diff --git a/board/gen860t/MAINTAINERS b/board/gen860t/MAINTAINERS
deleted file mode 100644 (file)
index c5d3da3..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-GEN860T BOARD
-M:     Keith Outwater <Keith_Outwater@mvis.com>
-S:     Orphan (since 2014-06)
-F:     board/gen860t/
-F:     include/configs/GEN860T.h
-F:     configs/GEN860T_defconfig
-F:     configs/GEN860T_SC_defconfig
diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile
deleted file mode 100644 (file)
index 86ae5e8..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = gen860t.o flash.o beeper.o fpga.o ioport.o
diff --git a/board/gen860t/README b/board/gen860t/README
deleted file mode 100644 (file)
index 3ef8ae1..0000000
+++ /dev/null
@@ -1,131 +0,0 @@
-This directory contains board specific code for a generic MPC860T based
-embedded computer, called 'GEN860T'.  The design is generic in the sense that
-common, readily available components are used and that the architecture of the
-system is relatively straightforward:
-
-       One eight bit wide boot (FLASH) memory
-       32 bit main memory using SDRAM
-       DOC 2000+
-       Ethernet PHY
-       Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC.
-       Some other miscellaneous peripherals
-
-NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this
-port.  I guess the computer is not as generic as I first said 8)  However,
-these extras can be safely ignored.
-
-Given the GEN860T files, it should be pretty easy to reverse engineer the
-hardware configuration, if that's useful to you.  Hopefully, this code will
-be useful to someone as a basis for a port to a new system or as a head start
-on a custom design.  If you end up using any of this, I would appreciate
-hearing from you, especially if you discover bugs or find ways to improve the
-quality of this U-Boot port.
-
-Here are the salient features of the system:
-Clock                                          :       33.3 Mhz oscillator
-Processor core frequency       :       66.6 Mhz  if in 1:2:1 mode; can also run 1:1
-Bus frequency                          :       33.3 Mhz
-
-Main memory:
-       Type    : SDRAM
-       Width   : 32 bits
-       Size    : 64 mibibytes
-       Chip    : Two Micron MT48LC16M16A2TG-7E
-       CS              : MPC860T CS1*/UPMA
-       UPMA CONNECTIONS:
-               SDRAM A10       : GPLA0*
-               SDRAM CAS*      : GPLA2*
-               SDRAM WE*       : GPLA3*
-               SDRAM RAS*      : GPLA4*
-
-Boot memory:
-       Type    : FLASH
-       Width   : 8 bits
-       Size    : 16 mibibytes
-       Chip    : One Intel 28F128J3A (StrataFlash)
-       CS              : MPC860T CS0*/GPCM (this is the "boot" chip select)
-
-EEPROM memory:
-       Type    : Serial I2C EEPROM
-       Width   : 8 bits
-       Size    : 32 kibibytes
-       Chip    : One Atmel AT25C256
-       CS              : 0x50 (external I2C address pins on device are tied to GND)
-
-Filesystem memory:
-       Type    : NAND FLASH (Toshiba)
-       Width   : 8 bits (i.e. interface to DOC is 8 bits)
-       Size    : 32 mibibytes
-       Chip    : One DiskOnCHip Millenium Plus (DOC 2000+)
-       CS              : MPC860T CS2*/GPCM
-
-Network support:
-       MAC             : MPC86OT FEC (Fast Ethernet Controller)
-       PHY             : Intel LXT971A
-       MII Addr: 0x0 (hardwired on the board)
-       MII IRQ :
-
-Console:
-       RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter)
-
-Real Time Clock:
-       Type    : Low power, I2C interface
-       Chip    : Maxim DS1337
-       CS              : Address 0x68 on I2C bus
-
-       The MPC860T's internal RTC has a defect in Mask rev D that increases
-       the current drain on the KAPWR line to 10 mA.  Since this is an
-       unreasonable amount of current draw for a RTC, and Motorola does not
-       plan to fix this in future mask revisions, a serial (I2C) RTC that
-       works has been included instead.  NOTE that the DS1337 can be
-       configured to output a 32768 Hz clock while the main power is on.
-       This clock output has been routed to the MPC860T's EXTAL pin to allow
-       the internal RTC to be used.  NOTE also that due to yet another
-       defect in the rev D mask, the RTC does not operate reliably when the
-       internal RTC divisor is set to use a 32768 Hz reference.  So just use
-       the I2C RTC.
-
-Miscellaneous:
-       Xilinx Virtex FPGA on CS3*/GPCM.
-       Virtex FPGA slave SelectMap interface on cs4*/UPMB.
-       Mil-Std 1553 databus interface on CS5*/GPCM.
-       Audio sounder (beeper) with digital volume control connected to SPKROUT.
-
-SC variant:
-       A reduced-feature version of the GEN860T port is also supported: GEN860T_SC.
-       The 'SC' variant only provides support for the Virtex FPGA, SDRAM main
-       memory, EEPROM and flash memory.  The system clock frequency is reduced
-       to 24 MHz.
-
-Issues:
-       The DOC 2000+ returns 0x40 as its device ID when probed using the method
-       desxribed in the DOC datasheet.  Unfortunately, the U-Boot DOC driver
-       does not recognize this device.  As of this writing, it seems that MTD
-       does not support the DOC 2000+ either.
-
-Status:
-       Everything appears to work except DOC support. As of this writing,
-       David Woodhouse has stated on the MTD mailing list that he has no
-       knowledge of the DOC Millineum Plus and therfore there is no support
-       in MTD for this device.  I wish I had known this sooner :(
-
-The GEN860T board specific files and configuration is based on the work
-of others who have contributed to U-Boot. The copyright and license notices
-of these authors have been retained wherever their code has been reused.
-All new code to support the GEN860T board is:
-
-       (C) Copyright 2001-2003
-       Keith Outwater (keith_outwater@mvis.com)
-
-and the following license applies:
-
-SPDX-License-Identifier:       GPL-2.0+
-
-Thanks to Wolfgang Denk for a great software package and to everyone
-who contributed to its development.
-
-Keith Outwater
-Sr. Staff Engineer
-Microvision, Inc.
-<keith_outwater@mvis.com>
-<outwater@eskimo.com>
diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c
deleted file mode 100644 (file)
index 0bebca9..0000000
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * (C) Copyright 2002
- * Keith Outwater, keith_outwater@mvis.com
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <asm/8xx_immap.h>
-#include <linux/ctype.h>
-
-/*
- * Basic beeper support for the GEN860T board.  The GEN860T includes
- * an audio sounder driven by a Phillips TDA8551 amplifier.  The
- * TDA8551 features a digital volume control which uses a "trinary"
- * input (high/high-Z/low) to set volume.  The 860's SPKROUT pin
- * drives the amplifier input.
- */
-
-/*
- * Initialize beeper-related hardware. Initialize timer 1 for use with
- * the beeper. Use 66 MHz internal clock with prescale of 33 to get
- * 1 uS period per count.
- * FIXME: we should really compute the prescale based on the reported
- * core clock frequency.
- */
-void init_beeper (void)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-       immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1;
-       immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK)
-               | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN;
-       immap->im_cpmtimer.cpmt_tcn1 = 0;
-       immap->im_cpmtimer.cpmt_ter1 = 0xffff;
-       immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1;
-}
-
-/*
- * Set beeper frequency.  Max allowed frequency is 2.5 KHz.  This limit
- * is mostly arbitrary, but the beeper isn't really much good beyond this
- * frequency.
- */
-void set_beeper_frequency (uint frequency)
-{
-#define FREQ_LIMIT     2500
-
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-       /*
-        * Compute timer ticks given desired frequency.  The timer is