Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
authorTom Rini <trini@ti.com>
Mon, 1 Jul 2013 14:11:56 +0000 (10:11 -0400)
committerTom Rini <trini@ti.com>
Mon, 1 Jul 2013 14:11:56 +0000 (10:11 -0400)
294 files changed:
.checkpatch.conf
Makefile
README
arch/arm/config.mk
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/cpu/armv7/exynos/Makefile
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/tzpc.c [moved from board/samsung/smdk5250/tzpc_init.c with 69% similarity]
arch/arm/cpu/armv7/s5p-common/Makefile
arch/arm/cpu/armv7/s5p-common/timer.c
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/u-boot-spl.lds
arch/arm/cpu/u-boot.lds
arch/arm/dts/exynos5250.dtsi
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-exynos/cpu.h
arch/arm/include/asm/arch-exynos/dwmmc.h
arch/arm/include/asm/arch-exynos/tmu.h
arch/arm/include/asm/arch-exynos/tzpc.h
arch/arm/lib/Makefile
arch/arm/lib/bootm.c
arch/arm/lib/relocate.S
arch/arm/lib/sections.c [moved from arch/arm/lib/bss.c with 79% similarity]
arch/m68k/cpu/mcf5445x/speed.c
arch/m68k/include/asm/m5235.h
arch/m68k/lib/board.c
arch/microblaze/lib/bootm.c
arch/nios2/lib/bootm.c
arch/openrisc/lib/bootm.c
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
arch/powerpc/cpu/mpc85xx/p1010_serdes.c
arch/powerpc/cpu/mpc85xx/p1021_serdes.c
arch/powerpc/cpu/mpc85xx/p1022_serdes.c
arch/powerpc/cpu/mpc85xx/p1023_serdes.c
arch/powerpc/cpu/mpc85xx/p2020_serdes.c
arch/powerpc/cpu/mpc85xx/p2041_serdes.c
arch/powerpc/cpu/mpc85xx/p3041_serdes.c
arch/powerpc/cpu/mpc85xx/p4080_serdes.c
arch/powerpc/cpu/mpc85xx/p5020_serdes.c
arch/powerpc/cpu/mpc85xx/p5040_serdes.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t1040_serdes.c
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
arch/powerpc/cpu/mpc85xx/u-boot.lds
arch/powerpc/cpu/mpc86xx/cpu.c
arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
arch/powerpc/cpu/mpc8xxx/srio.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_ifc.h
arch/powerpc/include/asm/fsl_law.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/lib/bootm.c
arch/sandbox/cpu/cpu.c
arch/sandbox/cpu/os.c
arch/x86/include/asm/global_data.h
arch/x86/include/asm/msr.h
arch/x86/include/asm/u-boot-x86.h
arch/x86/lib/bootm.c
arch/x86/lib/gcc.c
arch/x86/lib/tsc_timer.c
board/LaCie/common/cpld-gpio-bus.c [new file with mode: 0644]
board/LaCie/common/cpld-gpio-bus.h [new file with mode: 0644]
board/LaCie/net2big_v2/Makefile
board/LaCie/net2big_v2/net2big_v2.c
board/LaCie/net2big_v2/net2big_v2.h
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/atmel/at91sam9n12ek/at91sam9n12ek.c
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/dvlhost/u-boot.lds
board/eltec/elppc/misc.c
board/freescale/b4860qds/tlb.c
board/freescale/bsc9131rdb/Makefile
board/freescale/bsc9131rdb/README
board/freescale/bsc9131rdb/law.c
board/freescale/bsc9131rdb/spl_minimal.c [new file with mode: 0644]
board/freescale/bsc9131rdb/tlb.c
board/freescale/bsc9132qds/Makefile
board/freescale/bsc9132qds/bsc9132qds.c
board/freescale/bsc9132qds/law.c
board/freescale/bsc9132qds/spl_minimal.c [new file with mode: 0644]
board/freescale/bsc9132qds/tlb.c
board/freescale/common/Makefile
board/freescale/common/pixis.c
board/freescale/mx31ads/u-boot.lds
board/freescale/p1010rdb/Makefile
board/freescale/p1010rdb/spl_minimal.c [moved from nand_spl/board/freescale/p1010rdb/nand_boot.c with 95% similarity]
board/freescale/p1010rdb/tlb.c
board/freescale/p1023rdb/Makefile [new file with mode: 0644]
board/freescale/p1023rdb/ddr.c [new file with mode: 0644]
board/freescale/p1023rdb/law.c [new file with mode: 0644]
board/freescale/p1023rdb/p1023rdb.c [new file with mode: 0644]
board/freescale/p1023rdb/tlb.c [new file with mode: 0644]
board/freescale/t4qds/tlb.c
board/ifm/ac14xx/ac14xx.c
board/isee/igep0033/board.c
board/phytec/pcm051/board.c
board/samsung/dts/exynos5250-smdk5250.dts
board/samsung/dts/exynos5250-snow.dts
board/samsung/origen/lowlevel_init.S
board/samsung/origen/origen_setup.h
board/samsung/smdk5250/Makefile
board/samsung/smdk5250/clock_init.c
board/samsung/smdk5250/clock_init.h
board/samsung/smdk5250/exynos5-dt.c [new file with mode: 0644]
board/samsung/smdk5250/lowlevel_init.S
board/samsung/smdk5250/setup.h
board/samsung/smdk5250/smdk5250.c
board/samsung/smdk5250/spl_boot.c
board/samsung/smdkv310/lowlevel_init.S
board/ti/am335x/board.c
board/ti/panda/panda.c
board/ti/ti814x/evm.c
board/vpac270/u-boot-spl.lds
boards.cfg
common/Makefile
common/board_f.c
common/board_r.c
common/bootstage.c
common/cmd_bootm.c
common/cmd_ide.c
common/cmd_mem.c
common/cmd_mmc.c
common/cmd_pxe.c
common/cmd_trace.c [new file with mode: 0644]
common/image-fdt.c
common/image-fit.c
common/image-sig.c [new file with mode: 0644]
common/image.c
common/usb_storage.c
config.mk
doc/README.plan9 [new file with mode: 0644]
doc/README.srio-pcie-boot-corenet
doc/README.trace [new file with mode: 0644]
doc/device-tree-bindings/exynos/dwmmc.txt [new file with mode: 0644]
doc/device-tree-bindings/input/cros-ec-keyb.txt [new file with mode: 0644]
doc/device-tree-bindings/misc/cros-ec.txt [new file with mode: 0644]
doc/mkimage.1
doc/uImage.FIT/sign-configs.its [new file with mode: 0644]
doc/uImage.FIT/sign-images.its [new file with mode: 0644]
doc/uImage.FIT/signature.txt [new file with mode: 0644]
doc/uImage.FIT/verified-boot.txt [new file with mode: 0644]
drivers/hwmon/lm63.c
drivers/input/Makefile
drivers/input/cros_ec_keyb.c [new file with mode: 0644]
drivers/misc/Makefile
drivers/misc/cros_ec.c [new file with mode: 0644]
drivers/misc/cros_ec_i2c.c [new file with mode: 0644]
drivers/misc/cros_ec_lpc.c [new file with mode: 0644]
drivers/misc/cros_ec_spi.c [new file with mode: 0644]
drivers/mmc/dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
drivers/mmc/mmc.c
drivers/mtd/cfi_flash.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/fsl_ifc_spl.c [moved from nand_spl/nand_boot_fsl_ifc.c with 88% similarity]
drivers/mtd/spi/Makefile
drivers/mtd/spi/gigadevice.c [new file with mode: 0644]
drivers/mtd/spi/spansion.c
drivers/mtd/spi/spi_flash.c
drivers/mtd/spi/spi_flash_internal.h
drivers/mtd/spi/stmicro.c
drivers/mtd/spi/winbond.c
drivers/net/Makefile
drivers/net/designware.c
drivers/net/ftgmac100.c
drivers/net/ftmac110.c [new file with mode: 0644]
drivers/net/ftmac110.h [new file with mode: 0644]
drivers/net/ks8851_mll.c [new file with mode: 0644]
drivers/net/ks8851_mll.h [new file with mode: 0644]
drivers/net/macb.c
drivers/net/macb.h
drivers/net/mvgbe.c
drivers/net/mvgbe.h
drivers/net/phy/Makefile
drivers/net/phy/atheros.c
drivers/net/phy/icplus.c [new file with mode: 0644]
drivers/net/phy/marvell.c
drivers/net/phy/micrel.c
drivers/net/phy/natsemi.c
drivers/net/phy/phy.c
drivers/net/sunxi_wemac.c [new file with mode: 0644]
drivers/pci/fsl_pci_init.c
drivers/power/exynos-tmu.c
drivers/serial/serial.c
drivers/serial/serial_s5p.c
drivers/spi/cf_qspi.c
drivers/spi/exynos_spi.c
drivers/spi/mxc_spi.c
drivers/usb/musb/musb_hcd.c
drivers/usb/musb/musb_udc.c
drivers/video/exynos_fb.c
include/asm-generic/global_data.h
include/asm-generic/sections.h
include/command.h
include/common.h
include/configs/B4860QDS.h
include/configs/BSC9131RDB.h
include/configs/BSC9132QDS.h
include/configs/P1010RDB.h
include/configs/P1023RDB.h [new file with mode: 0644]
include/configs/P2041RDB.h
include/configs/P3041DS.h
include/configs/P4080DS.h
include/configs/P5020DS.h
include/configs/a3m071.h
include/configs/ac14xx.h
include/configs/am335x_evm.h
include/configs/at91sam9n12ek.h
include/configs/coreboot.h
include/configs/dra7xx_evm.h
include/configs/exynos5250-dt.h
include/configs/lacie_kw.h
include/configs/omap4_common.h
include/configs/omap5_common.h
include/configs/omap5_uevm.h
include/configs/origen.h
include/configs/pcm051.h
include/configs/sandbox.h
include/configs/smdkv310.h
include/configs/t4qds.h
include/configs/trats.h
include/cros_ec.h [new file with mode: 0644]
include/cros_ec_message.h [new file with mode: 0644]
include/dwmmc.h
include/ec_commands.h [new file with mode: 0644]
include/fdtdec.h
include/ide.h
include/image.h
include/libfdt.h
include/linux/ethtool.h
include/linux/mii.h
include/micrel.h
include/mmc.h
include/net.h
include/netdev.h
include/part.h
include/pci.h
include/phy.h
include/rsa.h [new file with mode: 0644]
include/spi.h
include/spi_flash.h
include/trace.h [new file with mode: 0644]
include/vsprintf.h
lib/Makefile
lib/fdtdec.c
lib/libfdt/fdt_wip.c
lib/rsa/Makefile [new file with mode: 0644]
lib/rsa/rsa-sign.c [new file with mode: 0644]
lib/rsa/rsa-verify.c [new file with mode: 0644]
lib/trace.c [new file with mode: 0644]
lib/vsprintf.c
nand_spl/board/freescale/p1010rdb/Makefile [deleted file]
net/link_local.c
net/net.c
net/nfs.c
net/tftp.c
spl/Makefile
test/image/test-fit.py
test/trace/test-trace.sh [new file with mode: 0755]
test/vboot/.gitignore [new file with mode: 0644]
test/vboot/sandbox-kernel.dts [new file with mode: 0644]
test/vboot/sandbox-u-boot.dts [new file with mode: 0644]
test/vboot/sign-configs.its [new file with mode: 0644]
test/vboot/sign-images.its [new file with mode: 0644]
test/vboot/vboot_test.sh [new file with mode: 0755]
tools/.gitignore
tools/Makefile
tools/fit_image.c
tools/image-host.c
tools/mkimage.c
tools/mkimage.h
tools/pblimage.c
tools/proftool.c [new file with mode: 0644]

index d88af57..35167e1 100644 (file)
@@ -18,3 +18,6 @@
 
 # Not Linux, so we don't recommend usleep_range() over udelay()
 --ignore USLEEP_RANGE
+
+# Ignore networking block comment style
+--ignore NETWORKING_BLOCK_COMMENT_STYLE
index 693b3f2..ba1c10b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
 VERSION = 2013
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -247,6 +247,7 @@ OBJS := $(addprefix $(obj),$(OBJS))
 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
 
 LIBS-y += lib/libgeneric.o
+LIBS-y += lib/rsa/librsa.o
 LIBS-y += lib/lzma/liblzma.o
 LIBS-y += lib/lzo/liblzo.o
 LIBS-y += lib/zlib/libz.o
@@ -743,6 +744,13 @@ tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
        $(MAKE) -C $@ all
 endif  # config.mk
 
+# ARM relocations should all be R_ARM_RELATIVE.
+checkarmreloc: $(obj)u-boot
+       @if test "R_ARM_RELATIVE" != \
+               "`readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
+               then echo "$< contains relocations other than \
+               R_ARM_RELATIVE"; false; fi
+
 $(VERSION_FILE):
                @mkdir -p $(dir $(VERSION_FILE))
                @( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
@@ -824,7 +832,8 @@ clean:
               $(obj)tools/mk{smdk5250,}spl                               \
               $(obj)tools/mxsboot                                        \
               $(obj)tools/ncb             $(obj)tools/ubsha1             \
-              $(obj)tools/kernel-doc/docproc
+              $(obj)tools/kernel-doc/docproc                             \
+              $(obj)tools/proftool
        @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}        \
               $(obj)board/matrix_vision/*/bootscript.img                 \
               $(obj)board/voiceblue/eeprom                               \
diff --git a/README b/README
index cd0336c..5c343da 100644 (file)
--- a/README
+++ b/README
@@ -413,11 +413,22 @@ The following options need to be configured:
                See Freescale App Note 4493 for more information about
                this erratum.
 
+               CONFIG_A003399_NOR_WORKAROUND
+               Enables a workaround for IFC erratum A003399. It is only
+               requred during NOR boot.
+
                CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
                This is the value to write into CCSR offset 0x18600
                according to the A004510 workaround.
 
+               CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+               This value denotes start offset of M2 memory
+               which is directly connected to the DSP core.
+
+               CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+               This value denotes start offset of DSP CCSR space.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -843,7 +854,7 @@ The following options need to be configured:
                CONFIG_CMD_FDOS         * Dos diskette Support
                CONFIG_CMD_FLASH          flinfo, erase, protect
                CONFIG_CMD_FPGA           FPGA device initialization support
-               CONFIG_CMD_FUSE           Device fuse support
+               CONFIG_CMD_FUSE         * Device fuse support
                CONFIG_CMD_GETTIME      * Get time since boot
                CONFIG_CMD_GO           * the 'go' command (exec code)
                CONFIG_CMD_GREPENV      * search environment
@@ -853,7 +864,7 @@ The following options need to be configured:
                CONFIG_CMD_IDE          * IDE harddisk support
                CONFIG_CMD_IMI            iminfo
                CONFIG_CMD_IMLS           List all images found in NOR flash
-               CONFIG_CMD_IMLS_NAND      List all images found in NAND flash
+               CONFIG_CMD_IMLS_NAND    * List all images found in NAND flash
                CONFIG_CMD_IMMAP        * IMMR dump support
                CONFIG_CMD_IMPORTENV    * import an environment
                CONFIG_CMD_INI          * import data from an ini file into the env
@@ -861,23 +872,24 @@ The following options need to be configured:
                CONFIG_CMD_ITEST          Integer/string test of 2 values
                CONFIG_CMD_JFFS2        * JFFS2 Support
                CONFIG_CMD_KGDB         * kgdb
-               CONFIG_CMD_LDRINFO        ldrinfo (display Blackfin loader)
+               CONFIG_CMD_LDRINFO      * ldrinfo (display Blackfin loader)
                CONFIG_CMD_LINK_LOCAL   * link-local IP address auto-configuration
                                          (169.254.*.*)
                CONFIG_CMD_LOADB          loadb
                CONFIG_CMD_LOADS          loads
-               CONFIG_CMD_MD5SUM         print md5 message digest
+               CONFIG_CMD_MD5SUM       * print md5 message digest
                                          (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
                CONFIG_CMD_MEMINFO      * Display detailed memory information
                CONFIG_CMD_MEMORY         md, mm, nm, mw, cp, cmp, crc, base,
                                          loop, loopw
-               CONFIG_CMD_MEMTEST        mtest
+               CONFIG_CMD_MEMTEST      * mtest
                CONFIG_CMD_MISC           Misc functions like sleep etc
                CONFIG_CMD_MMC          * MMC memory mapped support
                CONFIG_CMD_MII          * MII utility commands
                CONFIG_CMD_MTDPARTS     * MTD partition support
                CONFIG_CMD_NAND         * NAND support
                CONFIG_CMD_NET            bootp, tftpboot, rarpboot
+               CONFIG_CMD_NFS            NFS support
                CONFIG_CMD_PCA953X      * PCA953x I2C gpio commands
                CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
                CONFIG_CMD_PCI          * pciinfo
@@ -896,7 +908,7 @@ The following options need to be configured:
                CONFIG_CMD_SETGETDCR      Support for DCR Register access
                                          (4xx only)
                CONFIG_CMD_SF           * Read/write/erase SPI NOR flash
-               CONFIG_CMD_SHA1SUM        print sha1 memory digest
+               CONFIG_CMD_SHA1SUM      * print sha1 memory digest
                                          (requires CONFIG_CMD_MEMORY)
                CONFIG_CMD_SOFTSWITCH   * Soft switch setting command for BF60x
                CONFIG_CMD_SOURCE         "source" command Support
@@ -908,6 +920,7 @@ The following options need to be configured:
                CONFIG_CMD_USB          * USB support
                CONFIG_CMD_CDP          * Cisco Discover Protocol support
                CONFIG_CMD_MFSL         * Microblaze FSL support
+               CONFIG_CMD_XIMG           Load part of Multi Image
 
 
                EXAMPLE: If you want all functions except of network
@@ -1432,6 +1445,11 @@ CBFS (Coreboot Filesystem) support
                Export function i8042_kbd_init, i8042_tstc and i8042_getc
                for cfb_console. Supports cursor blinking.
 
+               CONFIG_CROS_EC_KEYB
+               Enables a Chrome OS keyboard using the CROS_EC interface.
+               This uses CROS_EC to communicate with a second microcontroller
+               which provides key scans on request.
+
 - Video support:
                CONFIG_VIDEO
 
@@ -2509,6 +2527,11 @@ CBFS (Coreboot Filesystem) support
                Define this option to include a destructive SPI flash
                test ('sf test').
 
+               CONFIG_SPI_FLASH_BAR            Ban/Extended Addr Reg
+
+               Define this option to use the Bank addr/Extended addr
+               support on SPI flashes which has size > 16Mbytes.
+
 - SystemACE Support:
                CONFIG_SYSTEMACE
 
@@ -2560,6 +2583,16 @@ CBFS (Coreboot Filesystem) support
                Note: There is also a sha1sum command, which should perhaps
                be deprecated in favour of 'hash sha1'.
 
+- Signing support:
+               CONFIG_RSA
+
+               This enables the RSA algorithm used for FIT image verification
+               in U-Boot. See doc/uImage/signature for more information.
+
+               The signing part is build into mkimage regardless of this
+               option.
+
+
 - Show boot progress:
                CONFIG_SHOW_BOOT_PROGRESS
 
@@ -2784,6 +2817,11 @@ FIT uImage format:
                most specific compatibility entry of U-Boot's fdt's root node.
                The order of entries in the configuration's fdt is ignored.
 
+               CONFIG_FIT_SIGNATURE
+               This option enables signature verification of FIT uImages,
+               using a hash signed and verified using RSA. See
+               doc/uImage.FIT/signature.txt for more details.
+
 - Standalone program support:
                CONFIG_STANDALONE_LOAD_ADDR
 
@@ -3022,6 +3060,14 @@ FIT uImage format:
                CONFIG_SPL_LIBGENERIC_SUPPORT
                Support for lib/libgeneric.o in SPL binary
 
+               CONFIG_SPL_ENV_SUPPORT
+               Support for the environment operating in SPL binary
+
+               CONFIG_SPL_NET_SUPPORT
+               Support for the net/libnet.o in SPL binary.
+               It conflicts with SPL env from storage medium specified by
+               CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
                CONFIG_SPL_PAD_TO
                Image offset to which the SPL should be padded before appending
                the SPL payload. By default, this is defined as
@@ -3964,6 +4010,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_SRIO2:
                Board has SRIO 2 port available
 
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+               Board can support master function for Boot from SRIO and PCIE
+
 - CONFIG_SYS_SRIOn_MEM_VIRT:
                Virtual Address of SRIO port 'n' memory region
 
@@ -4074,6 +4123,11 @@ Low Level (hardware related) configuration options:
                that is executed before the actual U-Boot. E.g. when
                compiling a NAND SPL.
 
+- CONFIG_SYS_MPC85XX_NO_RESETVEC
+               Only for 85xx systems. If this variable is specified, the section
+               .resetvec is not kept and the section .bootpg is placed in the
+               previous 4k of the .text section.
+
 - CONFIG_ARCH_MAP_SYSMEM
                Generally U-Boot (and in particular the md command) uses
                effective address. It is therefore not necessary to regard
index dc64160..e80e1ed 100644 (file)
@@ -109,3 +109,8 @@ ifeq ($(GAS_BUG_12532),y)
 PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
 endif
 endif
+
+# check that only R_ARM_RELATIVE relocations are generated
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y  += checkarmreloc
+endif
index cf55bf7..367c805 100644 (file)
@@ -31,6 +31,7 @@ SECTIONS
        . = ALIGN(4);
        .text      :
        {
+               *(.__image_copy_start)
          arch/arm/cpu/arm920t/start.o  (.text*)
                /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
          . = 0x1000;
@@ -56,7 +57,10 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
 
        __bss_start = .;
        .bss : { *(.bss*) }
index 673c725..f4e7525 100644 (file)
@@ -57,11 +57,6 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       }
-
        .bss : {
                . = ALIGN(4);
                __bss_start = .;
index 967a135..446d095 100644 (file)
@@ -57,11 +57,6 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       }
-
        .bss : {
                . = ALIGN(4);
                __bss_start = .;
index 885fb2d..b935a29 100644 (file)
@@ -149,3 +149,43 @@ int arch_misc_init(void)
 #endif
        return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+       /*
+        * Unlock the RTC's registers.  For more details please see the
+        * RTC_SS section of the TRM.  In order to unlock we need to
+        * write these specific values (keys) in this order.
+        */
+       writel(0x83e70b13, &rtc->kick0r);
+       writel(0x95a4f1e0, &rtc->kick1r);
+
+       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+       writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+#define UART_RESET             (0x1 << 1)
+#define UART_CLK_RUNNING_MASK  0x1
+#define UART_SMART_IDLE_EN     (0x1 << 0x3)
+
+void uart_soft_reset(void)
+{
+       struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+       u32 regval;
+
+       regval = readl(&uart_base->uartsyscfg);
+       regval |= UART_RESET;
+       writel(regval, &uart_base->uartsyscfg);
+       while ((readl(&uart_base->uartsyssts) &
+               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+               ;
+
+       /* Disable smart idle */
+       regval = readl(&uart_base->uartsyscfg);
+       regval |= UART_SMART_IDLE_EN;
+       writel(regval, &uart_base->uartsyscfg);
+}
+#endif
index a1efc75..9c4d0b4 100644 (file)
@@ -246,7 +246,7 @@ static void enable_per_clocks(void)
                ;
 }
 
-static void mpu_pll_config(void)
+void mpu_pll_config_val(int mpull_m)
 {
        u32 clkmode, clksel, div_m2;
 
@@ -260,7 +260,7 @@ static void mpu_pll_config(void)
                ;
 
        clksel = clksel & (~CLK_SEL_MASK);
-       clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+       clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
        writel(clksel, &cmwkup->clkseldpllmpu);
 
        div_m2 = div_m2 & ~CLK_DIV_MASK;
@@ -274,6 +274,11 @@ static void mpu_pll_config(void)
                ;
 }
 
+static void mpu_pll_config(void)
+{
+       mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+}
+
 static void core_pll_config(void)
 {
        u32 clkmode, clksel, div_m4, div_m5, div_m6;
index 9119961..b2f9152 100644 (file)
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS  += clock.o power.o soc.o system.o pinmux.o
+COBJS  += clock.o power.o soc.o system.o pinmux.o tzpc.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
index 223660a..e1c4246 100644 (file)
@@ -116,10 +116,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
                /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
                fout = (m + k / 1024) * (freq / (p * (1 << s)));
        } else {
-               if (s < 1)
-                       s = 1;
-               /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-               fout = m * (freq / (p * (1 << (s - 1))));
+               /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+               fout = m * (freq / (p * (1 << s)));
        }
 
        return fout;
@@ -613,7 +611,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
                (struct exynos4_clock *)samsung_get_base_clock();
        unsigned long uclk, sclk;
        unsigned int sel, ratio, pre_ratio;
-       int shift;
+       int shift = 0;
 
        sel = readl(&clk->src_fsys);
        sel = (sel >> (dev_index << 2)) & 0xf;
@@ -662,7 +660,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
                (struct exynos5_clock *)samsung_get_base_clock();
        unsigned long uclk, sclk;
        unsigned int sel, ratio, pre_ratio;
-       int shift;
+       int shift = 0;
 
        sel = readl(&clk->src_fsys);
        sel = (sel >> (dev_index << 2)) & 0xf;
similarity index 69%
rename from board/samsung/smdk5250/tzpc_init.c
rename to arch/arm/cpu/armv7/exynos/tzpc.c
index c833541..f5e8e9c 100644 (file)
  * MA 02111-1307 USA
  */
 
+#include <common.h>
 #include <asm/arch/tzpc.h>
-#include"setup.h"
+#include <asm/io.h>
 
 /* Setting TZPC[TrustZone Protection Controller] */
 void tzpc_init(void)
 {
        struct exynos_tzpc *tzpc;
-       unsigned int addr;
+       unsigned int addr, start = 0, end = 0;
 
-       for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+       start = samsung_get_base_tzpc();
+
+       if (cpu_is_exynos5())
+               end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+       else if (cpu_is_exynos4())
+               end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+
+       for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
                tzpc = (struct exynos_tzpc *)addr;
 
-               if (addr == TZPC0_BASE)
+               if (addr == start)
                        writel(R0SIZE, &tzpc->r0size);
 
                writel(DECPROTXSET, &tzpc->decprot0set);
                writel(DECPROTXSET, &tzpc->decprot1set);
 
-               if (addr != TZPC9_BASE) {
-                       writel(DECPROTXSET, &tzpc->decprot2set);
-                       writel(DECPROTXSET, &tzpc->decprot3set);
-               }
+               if (cpu_is_exynos5() && (addr == end))
+                       break;
+
+               writel(DECPROTXSET, &tzpc->decprot2set);
+               writel(DECPROTXSET, &tzpc->decprot3set);
        }
 }
index 1705399..0c38bd0 100644 (file)
@@ -26,9 +26,11 @@ include $(TOPDIR)/config.mk
 LIB    = $(obj)libs5p-common.o
 
 COBJS-y                += cpu_info.o
+ifndef CONFIG_SPL_BUILD
 COBJS-y                += timer.o
 COBJS-y                += sromc.o
 COBJS-$(CONFIG_PWM)    += pwm.o
+endif
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
index 4adfaae..637593c 100644 (file)
@@ -95,7 +95,7 @@ unsigned long get_timer(unsigned long base)
        return time_ms - base;
 }
 
-unsigned long timer_get_us(void)
+unsigned long __attribute__((no_instrument_function)) timer_get_us(void)
 {
        static unsigned long base_time_us;
 
index 553589c..54bafda 100644 (file)
@@ -31,6 +31,7 @@ SECTIONS
        . = ALIGN(4);
        .text :
        {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                *(.text*)
        }
@@ -54,17 +55,23 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -88,6 +95,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }
index 1408f03..b6ed25f 100644 (file)
@@ -58,11 +58,6 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       }
-
        _end = .;
 
        .bss __rel_dyn_start (OVERLAY) : {
@@ -72,6 +67,7 @@ SECTIONS
                __bss_end = .;
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }
index d9bbee3..3037885 100644 (file)
@@ -33,7 +33,7 @@ SECTIONS
        . = ALIGN(4);
        .text :
        {
-               __image_copy_start = .;
+               *(.__image_copy_start)
                CPUDIR/start.o (.text*)
                *(.text*)
        }
@@ -57,17 +57,23 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -101,6 +107,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }
index df4b231..2d6dfff 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
        };
+
+       mmc@12200000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12200000 0x1000>;
+               interrupts = <0 75 0>;
+       };
+
+       mmc@12210000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12210000 0x1000>;
+               interrupts = <0 76 0>;
+       };
+
+       mmc@12220000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12220000 0x1000>;
+               interrupts = <0 77 0>;
+       };
+
+       mmc@12230000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12230000 0x1000>;
+               interrupts = <0 78 0>;
+       };
+
+       gpio: gpio {
+       };
 };
index fedc674..307ac28 100644 (file)
@@ -32,6 +32,7 @@ extern struct ctrl_stat *cstat;
 u32 get_device_type(void);
 void save_omap_boot_params(void);
 void setup_clocks_for_console(void);
+void mpu_pll_config_val(int mpull_m);
 void ddr_pll_config(unsigned int ddrpll_M);
 
 void sdelay(unsigned long);
@@ -41,4 +42,7 @@ void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
                        u32 size);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
+
+void rtc32k_enable(void);
+void uart_soft_reset(void);
 #endif
index f76e489..1ff7642 100644 (file)
@@ -38,6 +38,7 @@
 #define EXYNOS4_CLOCK_BASE             0x10030000
 #define EXYNOS4_SYSTIMER_BASE          0x10050000
 #define EXYNOS4_WATCHDOG_BASE          0x10060000
+#define EXYNOS4_TZPC_BASE              0x10110000
 #define EXYNOS4_MIU_BASE               0x10600000
 #define EXYNOS4_DMC0_BASE              0x10400000
 #define EXYNOS4_DMC1_BASE              0x10410000
@@ -74,6 +75,7 @@
 #define EXYNOS4X12_CLOCK_BASE          0x10030000
 #define EXYNOS4X12_SYSTIMER_BASE       0x10050000
 #define EXYNOS4X12_WATCHDOG_BASE       0x10060000
+#define EXYNOS4X12_TZPC_BASE           0x10110000
 #define EXYNOS4X12_DMC0_BASE           0x10600000
 #define EXYNOS4X12_DMC1_BASE           0x10610000
 #define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000
 #define EXYNOS5_POWER_BASE             0x10040000
 #define EXYNOS5_SWRESET                        0x10040400
 #define EXYNOS5_SYSREG_BASE            0x10050000
+#define EXYNOS5_TZPC_BASE              0x10100000
 #define EXYNOS5_WATCHDOG_BASE          0x101D0000
 #define EXYNOS5_ACE_SFR_BASE            0x10830000
 #define EXYNOS5_DMC_PHY0_BASE          0x10C00000
@@ -175,7 +178,7 @@ static inline char *s5p_get_cpu_name(void)
 }
 
 #define IS_SAMSUNG_TYPE(type, id)                      \
-static inline int cpu_is_##type(void)                  \
+static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
 {                                                      \
        return (s5p_cpu_id >> 12) == id;                \
 }
@@ -184,7 +187,8 @@ IS_SAMSUNG_TYPE(exynos4, 0x4)
 IS_SAMSUNG_TYPE(exynos5, 0x5)
 
 #define IS_EXYNOS_TYPE(type, id)                       \
-static inline int proid_is_##type(void)                        \
+static inline int __attribute__((no_instrument_function)) \
+       proid_is_##type(void)                           \
 {                                                      \
        return s5p_cpu_id == id;                        \
 }
@@ -194,9 +198,10 @@ IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 
 #define SAMSUNG_BASE(device, base)                             \
-static inline unsigned int samsung_get_base_##device(void)     \
+static inline unsigned int __attribute__((no_instrument_function)) \
+       samsung_get_base_##device(void) \
 {                                                              \
-       if (cpu_is_exynos4()) {                                 \
+       if (cpu_is_exynos4()) {                         \
                if (proid_is_exynos4412())                      \
                        return EXYNOS4X12_##base;               \
                return EXYNOS4_##base;                          \
@@ -233,6 +238,7 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
 SAMSUNG_BASE(spi, SPI_BASE)
 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
 #endif
 
 #endif /* _EXYNOS4_CPU_H */
index 8acdf9b..3b147b8 100644 (file)
 #define DWMCI_SET_DRV_CLK(x)   ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-       unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-       return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
index 7e0158e..cad3569 100644 (file)
 #define __ASM_ARCH_TMU_H
 
 struct exynos5_tmu_reg {
-       unsigned triminfo;
-       unsigned rsvd1;
-       unsigned rsvd2;
-       unsigned rsvd3;
-       unsigned rsvd4;
-       unsigned triminfo_control;
-       unsigned rsvd5;
-       unsigned rsvd6;
-       unsigned tmu_control;
-       unsigned rsvd7;
-       unsigned tmu_status;
-       unsigned sampling_internal;
-       unsigned counter_value0;
-       unsigned counter_value1;
-       unsigned rsvd8;
-       unsigned rsvd9;
-       unsigned current_temp;
-       unsigned rsvd10;
-       unsigned rsvd11;
-       unsigned rsvd12;
-       unsigned threshold_temp_rise;
-       unsigned threshold_temp_fall;
-       unsigned rsvd13;
-       unsigned rsvd14;
-       unsigned past_temp3_0;
-       unsigned past_temp7_4;
-       unsigned past_temp11_8;
-       unsigned past_temp15_12;
-       unsigned inten;
-       unsigned intstat;
-       unsigned intclear;
-       unsigned rsvd15;
-       unsigned emul_con;
+       u32 triminfo;
+       u32 rsvd1[4];
+       u32 triminfo_control;
+       u32 rsvd5[2];
+       u32 tmu_control;
+       u32 rsvd7;
+       u32 tmu_status;
+       u32 sampling_internal;
+       u32 counter_value0;
+       u32 counter_value1;
+       u32 rsvd8[2];
+       u32 current_temp;
+       u32 rsvd10[3];
+       u32 threshold_temp_rise;
+       u32 threshold_temp_fall;
+       u32 rsvd13[2];
+       u32 past_temp3_0;
+       u32 past_temp7_4;
+       u32 past_temp11_8;
+       u32 past_temp15_12;
+       u32 inten;
+       u32 intstat;
+       u32 intclear;
+       u32 rsvd15;
+       u32 emul_con;
 };
 #endif /* __ASM_ARCH_TMU_H */
index c5eb4b1..4d9c3a3 100644 (file)
@@ -47,6 +47,26 @@ struct exynos_tzpc {
        unsigned int pcellid2;
        unsigned int pcellid3;
 };
+
+#define EXYNOS4_NR_TZPC_BANKS          6
+#define EXYNOS5_NR_TZPC_BANKS          10
+
+/* TZPC : Register Offsets */
+#define TZPC_BASE_OFFSET               0x10000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE                 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET            0xFF
+void tzpc_init(void);
+
 #endif
 
 #endif
index 8ad9f66..9ecafb2 100644 (file)
@@ -43,7 +43,7 @@ SOBJS-y += relocate.o
 ifndef CONFIG_SYS_GENERIC_BOARD
 COBJS-y        += board.o
 endif
-COBJS-y += bss.o
+COBJS-y += sections.o
 
 COBJS-y        += bootm.o
 COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
index 1b6e0ac..b22fbc9 100644 (file)
@@ -68,12 +68,19 @@ void arch_lmb_reserve(struct lmb *lmb)
                    gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
 }
 
-static void announce_and_cleanup(void)
+/**
+ * announce_and_cleanup() - Print message and prepare for kernel boot
+ *
+ * @fake: non-zero to do everything except actually boot
+ */
+static void announce_and_cleanup(int fake)
 {
-       printf("\nStarting kernel ...\n\n");
+       printf("\nStarting kernel ...%s\n\n", fake ?
+               "(fake run for tracing)" : "");
        bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 #ifdef CONFIG_BOOTSTAGE_FDT
-       bootstage_fdt_add_report();
+       if (flag == BOOTM_STATE_OS_FAKE_GO)
+               bootstage_fdt_add_report();
 #endif
 #ifdef CONFIG_BOOTSTAGE_REPORT
        bootstage_report();
@@ -225,12 +232,13 @@ static void boot_prep_linux(bootm_headers_t *images)
 }
 
 /* Subcommand: GO */
-static void boot_jump_linux(bootm_headers_t *images)
+static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
        unsigned long machid = gd->bd->bi_arch_number;
        char *s;
        void (*kernel_entry)(int zero, int arch, uint params);
        unsigned long r2;
+       int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
 
        kernel_entry = (void (*)(int, int, uint))images->ep;
 
@@ -243,14 +251,15 @@ static void boot_jump_linux(bootm_headers_t *images)
        debug("## Transferring control to Linux (at address %08lx)" \
                "...\n", (ulong) kernel_entry);
        bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-       announce_and_cleanup();
+       announce_and_cleanup(fake);
 
        if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
                r2 = (unsigned long)images->ft_addr;
        else
                r2 = gd->bd->bi_boot_params;
 
-       kernel_entry(0, machid, r2);
+       if (!fake)
+               kernel_entry(0, machid, r2);
 }
 
 /* Main Entry point for arm bootm implementation
@@ -270,13 +279,13 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
                return 0;
        }
 
-       if (flag & BOOTM_STATE_OS_GO) {
-               boot_jump_linux(images);
+       if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+               boot_jump_linux(images, flag);
                return 0;
        }
 
        boot_prep_linux(images);
-       boot_jump_linux(images);
+       boot_jump_linux(images, flag);
        return 0;
 }
 
index 4446da9..949b9e8 100644 (file)
  */
 
 ENTRY(relocate_code)
-       mov     r6, r0  /* save addr of destination */
-
-       ldr     r0, =_start             /* r0 <- SRC &_start */
-       subs    r9, r6, r0              /* r9 <- relocation offset */
+       ldr     r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
+       subs    r9, r0, r1              /* r9 <- relocation offset */
        beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy loop */
-       adr     r7, relocate_code       /* r7 <- SRC &relocate_code */
-       ldr     r3, _image_copy_end_ofs /* r3 <- __image_copy_end local ofs */
-       add     r2, r7, r3              /* r2 <- SRC &__image_copy_end */
+       ldr     r2, =__image_copy_end   /* r2 <- SRC &__image_copy_end */
 
 copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
+       ldmia   r1!, {r10-r11}          /* copy from source address [r1]    */
+       stmia   r0!, {r10-r11}          /* copy to   target address [r0]    */
+       cmp     r1, r2                  /* until source end address [r2]    */
        blo     copy_loop
 
        /*
         * fix .rel.dyn relocations
         */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- __dynsym_start local ofs */
-       add     r10, r10, r7            /* r10 <- SRC &__dynsym_start */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- __rel_dyn_start local ofs */
-       add     r2, r2, r7              /* r2 <- SRC &__rel_dyn_start */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- __rel_dyn_end local ofs */
-       add     r3, r3, r7              /* r3 <- SRC &__rel_dyn_end */
+       ldr     r2, =__rel_dyn_start    /* r2 <- SRC &__rel_dyn_start */
+       ldr     r3, =__rel_dyn_end      /* r3 <- SRC &__rel_dyn_end */
 fixloop:
-       ldr     r0, [r2]                /* r0 <- SRC location to fix up */
-       add     r0, r0, r9              /* r0 <- DST location to fix up */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
+       ldmia   r2!, {r0-r1}            /* (r0,r1) <- (SRC location,fixup) */
+       and     r1, r1, #0xff
+       cmp     r1, #23                 /* relative fixup? */
+       bne     fixnext
+
        /* relative fix: increase location by offset */
+       add     r0, r0, r9
        ldr     r1, [r0]
        add     r1, r1, r9
-fixnext:
        str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
+fixnext:
        cmp     r2, r3
        blo     fixloop
 
@@ -100,13 +78,4 @@ relocate_done:
         bx        lr
 #endif
 
-_image_copy_end_ofs:
-       .word __image_copy_end - relocate_code
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - relocate_code
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - relocate_code
-_dynsym_start_ofs:
-       .word __dynsym_start - relocate_code
-
 ENDPROC(relocate_code)
similarity index 79%
rename from arch/arm/lib/bss.c
rename to arch/arm/lib/sections.c
index 99eda59..5921dd8 100644 (file)
@@ -35,5 +35,9 @@
  * aliasing warnings.
  */
 
-char __bss_start[0] __attribute__((used, section(".__bss_start")));
-char __bss_end[0] __attribute__((used, section(".__bss_end")));
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
index aa73e1f..0276d4d 100644 (file)
@@ -122,17 +122,17 @@ void setup_5441x_clocks(void)
 
        vco =  ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
                CONFIG_SYS_INPUT_CLKSRC;
-       gd->vco_clk = vco;
+       gd->arch.vco_clk = vco;
 
-       gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;  /* Input clock */
+       gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC;     /* Input clock */
 
        pdr = in_be32(&pll->pdr);
        temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
        gd->cpu_clk = vco / temp;       /* cpu clock */
-       gd->flb_clk = vco / temp;       /* FlexBus clock */
-       gd->flb_clk >>= 1;
+       gd->arch.flb_clk = vco / temp;  /* FlexBus clock */
+       gd->arch.flb_clk >>= 1;
        if (in_be16(ccm->misccr2) & 2)          /* fsys/4 */
-               gd->flb_clk >>= 1;
+               gd->arch.flb_clk >>= 1;
 
        temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
        gd->bus_clk = vco / temp;       /* bus clock */
index 71a40d3..a573f1c 100644 (file)
 #define SDRAMC_DCR_RC(x)               (((x)&0xFF)<<8)
 
 /* Bit definitions and macros for SDRAMC_DARCn */
-#define SDRAMC_DARCn_BA(x)             (((x)&0xFFFC)<<18)
+#define SDRAMC_DARCn_BA(x)             ((x)&0xFFFC0000)
 #define SDRAMC_DARCn_RE                        (0x00008000)
 #define SDRAMC_DARCn_CASL_MASK         (0x00003000)
 #define SDRAMC_DARCn_CASL_C0           (0x00000000)
index b2e3068..efc9fcc 100644 (file)
@@ -403,14 +403,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
        gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */
 
-       debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
        WATCHDOG_RESET ();
 
        gd->reloc_off =  dest_addr - CONFIG_SYS_MONITOR_BASE;
 
        serial_initialize();
 
+       debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
        monitor_flash_len = (ulong)&__init_end - dest_addr;
 
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
index 3842709..b328f94 100644 (file)
@@ -62,8 +62,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
 
        bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
-       if (!of_flat_tree && argc > 3)
-               of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
+       if (!of_flat_tree && argc > 1)
+               of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
 
        /* fixup the initrd now that we know where it should be */
        if (images->rd_start && images->rd_end && of_flat_tree)
index f32be52..114e146 100644 (file)
@@ -40,8 +40,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
        if (images->ft_len)
                of_flat_tree = images->ft_addr;
 #endif
-       if (!of_flat_tree && argc > 3)
-               of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
+       if (!of_flat_tree && argc > 1)
+               of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
        if (of_flat_tree)
                initrd_end = (ulong)of_flat_tree;
 
index 2c5d9ae..7f716b8 100644 (file)
@@ -63,8 +63,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
 
        show_boot_progress(15);
 
-       if (!of_flat_tree && argc > 3)
-               of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
+       if (!of_flat_tree && argc > 1)
+               of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
 #ifdef DEBUG
        printf("## Transferring control to Linux (at address 0x%08lx) " \
                                "ramdisk 0x%08lx, FDT 0x%08lx...\n",
index 2318064..4669883 100644 (file)
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_P1014) += ddr-gen3.o
 COBJS-$(CONFIG_P1020)  += ddr-gen3.o
 COBJS-$(CONFIG_P1021)  += ddr-gen3.o
 COBJS-$(CONFIG_P1022)  += ddr-gen3.o
+COBJS-$(CONFIG_P1023)  += ddr-gen3.o
 COBJS-$(CONFIG_P1024)  += ddr-gen3.o
 COBJS-$(CONFIG_P1025)  += ddr-gen3.o
 COBJS-$(CONFIG_P2010)  += ddr-gen3.o
index 422782c..a7ed877 100644 (file)
@@ -257,6 +257,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
        puts("Work-around for Erratum USB14 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+       puts("Work-around for Erratum A006593 enabled\n");
 #endif
        return 0;
 }
index 6ce483e..fbee753 100644 (file)
@@ -121,16 +121,16 @@ int checkcpu (void)
        switch(ver) {
        case PVR_VER_E500_V1:
        case PVR_VER_E500_V2:
-               puts("E500");
+               puts("e500");
                break;
        case PVR_VER_E500MC:
-               puts("E500MC");
+               puts("e500mc");
                break;
        case PVR_VER_E5500:
-               puts("E5500");
+               puts("e5500");
                break;
        case PVR_VER_E6500:
-               puts("E6500");
+               puts("e6500");
                break;
        default:
                puts("Unknown");
@@ -341,7 +341,7 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
        return fsl_ddr_sdram_size();
 #else
-       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+       return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
 }
 #else /* CONFIG_SYS_RAMBOOT */
index 4067f05..3c8f59c 100644 (file)
@@ -172,6 +172,9 @@ static void enable_cpc(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
                setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+               setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
+#endif
 
                out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
                /* Read back to sync write */
@@ -564,7 +567,7 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
        srio_init();
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        char *s = getenv("bootmaster");
        if (s) {
                if (!strcmp(s, "SRIO1")) {
index 234fde4..837c034 100644 (file)
@@ -25,7 +25,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
        struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
@@ -99,7 +99,7 @@ void cpu_init_early_f(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
        ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
        u32  *dst, *src;
        void (*setup_ifc_sram)(void);
@@ -138,7 +138,7 @@ void cpu_init_early_f(void)
  * Work Around for IFC Erratum A003399, issue will hit only when execution
  * from NOR Flash
  */
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
 #define SRAM_BASE_ADDR (0x00000000)
        /* TLB for SRAM */
        mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
@@ -180,5 +180,9 @@ void cpu_init_early_f(void)
 
        invalidate_tlb(1);
 
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
+       disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
+#endif
+
        init_tlbs();
 }
index 288f7b2..bb95f3d 100644 (file)
@@ -663,7 +663,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_CORENET
        do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
                "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
-       do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
+       do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
                "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
        do_fixup_by_compat_u32(blob, "fsl,mpic",
                "clock-frequency", get_bus_freq(0)/2, 1);
index 6dadeb8..ec96e81 100644 (file)
@@ -228,7 +228,7 @@ void fsl_serdes_init(void)
                break;
        }
 
-       if (srds1_io_sel > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
                return;
        }
@@ -237,7 +237,7 @@ void fsl_serdes_init(void)
                serdes1_prtcl_map |= (1 << lane_prtcl);
        }
 
-       if (srds2_io_sel > ARRAY_SIZE(serdes2_cfg_tbl)) {
+       if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
                printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
                return;
        }
index 7c49097..3483366 100644 (file)
@@ -68,7 +68,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
@@ -77,7 +77,7 @@ void fsl_serdes_init(void)
                serdes1_prtcl_map |= (1 << lane_prtcl);
        }
 
-       if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index 76288cd..c9eea15 100644 (file)
@@ -53,7 +53,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
 
-       if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
                return ;
        }
index 2582637..49a0290 100644 (file)
@@ -53,7 +53,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index f480c26..7af6aff 100644 (file)
@@ -62,7 +62,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index 2ff5d9a..fcccb52 100644 (file)
@@ -57,7 +57,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index e8a0387..1f7dba0 100644 (file)
@@ -54,7 +54,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
@@ -63,7 +63,7 @@ void fsl_serdes_init(void)
                serdes1_prtcl_map |= (1 << lane_prtcl);
        }
 
-       if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index 1849c16..d6d2696 100644 (file)
@@ -73,7 +73,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index e4c9c22..ed49920 100644 (file)
@@ -93,7 +93,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
@@ -102,7 +102,7 @@ void fsl_serdes_init(void)
                serdes1_prtcl_map |= (1 << lane_prtcl);
        }
 
-       if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index c8ab5d6..0b4ae90 100644 (file)
@@ -41,7 +41,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index 389ff6b..01af333 100644 (file)
@@ -61,7 +61,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index eec4ffe..87335c9 100644 (file)
@@ -90,7 +90,7 @@ int is_serdes_prtcl_valid(u32 prtcl)
        u32 svr = get_svr();
        u32 ver = SVR_SOC_VER(svr);
 
-       if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
                return 0;
 
        /* P2040[e] does not support XAUI */
index fba9ff2..a36dcd5 100644 (file)
@@ -139,7 +139,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 int is_serdes_prtcl_valid(u32 prtcl) {
        int i;
 
-       if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
                return 0;
 
        for (i = 0; i < SRDS_MAX_LANES; i++) {
index 87bd795..94ec445 100644 (file)
@@ -86,7 +86,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 int is_serdes_prtcl_valid(u32 prtcl) {
        int i;
 
-       if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
                return 0;
 
        for (i = 0; i < SRDS_MAX_LANES; i++) {
index fba9ff2..a36dcd5 100644 (file)
@@ -139,7 +139,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 int is_serdes_prtcl_valid(u32 prtcl) {
        int i;
 
-       if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
                return 0;
 
        for (i = 0; i < SRDS_MAX_LANES; i++) {
index 890b88e..d646e85 100644 (file)
@@ -105,7 +105,7 @@ int is_serdes_prtcl_valid(u32 prtcl)
 {
        int i;
 
-       if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
                return 0;
 
        for (i = 0; i < SRDS_MAX_LANES; i++) {
index 4f0480b..2657982 100644 (file)
@@ -1795,7 +1795,7 @@ clear_bss:
        stw     r0,0(r3)
        addi    r3,r3,4
        cmplw   0,r3,r4
-       bne     5b
+       blt     5b
 6:
 
        mr      r3,r9           /* Init Data pointer            */
index 8261e03..19add9f 100644 (file)
@@ -81,7 +81,7 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 {
        int i;
 
-       if (prtcl > (ARRAY_SIZE(serdes_cfg_tbl[serdes])))
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes]))
                return 0;
 
        for (i = 0; i < SRDS_MAX_LANES; i++) {
index f2b7bff..20284ed 100644 (file)
 #include "config.h"    /* CONFIG_BOARDDIR */
 
 OUTPUT_ARCH(powerpc)
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+PHDRS
+{
+       text PT_LOAD;
+       bss PT_LOAD;
+}
+#endif
 SECTIONS
 {
        . = CONFIG_SPL_TEXT_BASE;
@@ -60,7 +67,7 @@ SECTIONS
 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
        .bootpg ADDR(.text) + 0x1000 :
        {
-               start.o (.bootpg)
+               arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
        }
 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
 #elif defined(CONFIG_FSL_ELBC)
@@ -68,9 +75,16 @@ SECTIONS
 #else
 #error unknown NAND controller
 #endif
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+       .bootpg ADDR(.text) - 0x1000 :
+       {
+               KEEP(*(.bootpg))
+       } :text = 0xffff
+#else
        .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
                KEEP(*(.resetvec))
        } = 0xffff
+#endif
 
        /*
         * Make sure that the bss segment isn't linked at 0x0, otherwise its
@@ -78,10 +92,12 @@ SECTIONS
         */
        . |= 0x10;
 
+       . = ALIGN(4);
        __bss_start = .;
        .bss : {
                *(.sbss*)
                *(.bss*)
        }
+       . = ALIGN(4);
        __bss_end = .;
 }
index 0503dce..2643563 100644 (file)
@@ -95,6 +95,13 @@ SECTIONS
   . = ALIGN(256);
   __init_end = .;
 
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+  .bootpg ADDR(.text) - 0x1000 :
+  {
+    KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
+  } :text = 0xffff
+  . = ADDR(.text) + 0x80000;
+#else
   .bootpg RESET_VECTOR_ADDRESS - 0xffc :
   {
     arch/powerpc/cpu/mpc85xx/start.o   (.bootpg)
@@ -116,6 +123,7 @@ SECTIONS
    */
 #if (RESET_VECTOR_ADDRESS == 0xfffffffc)
   . |= 0x10;
+#endif
 #endif
 
   __bss_start = .;
index c553415..5ed3eb2 100644 (file)
@@ -78,7 +78,7 @@ checkcpu(void)
        major = PVR_E600_MAJ(pvr);
        minor = PVR_E600_MIN(pvr);
 
-       printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
+       printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
        if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
                puts("\n    Core1Translation Enabled");
        debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
index 0dc1975..0342e34 100644 (file)
@@ -64,7 +64,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
@@ -73,7 +73,7 @@ void fsl_serdes_init(void)
                serdes1_prtcl_map |= (1 << lane_prtcl);
        }
 
-       if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index 3ae9069..21c5ddb 100644 (file)
@@ -73,7 +73,7 @@ void fsl_serdes_init(void)
 
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-       if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
@@ -82,7 +82,7 @@ void fsl_serdes_init(void)
                serdes1_prtcl_map |= (1 << lane_prtcl);
        }
 
-       if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+       if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
                return;
        }
index 56b319f..4e8a441 100644 (file)
@@ -26,7 +26,7 @@ void print_ifc_regs(void)
        int i, j;
 
        printf("IFC Controller Registers\n");
-       for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+       for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
                printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
                        i, get_ifc_cspr(i), i, get_ifc_amask(i),
                        i, get_ifc_csor(i));
@@ -43,7 +43,7 @@ void init_early_memctl_regs(void)
        set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
        set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
 
-#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
+#ifndef CONFIG_A003399_NOR_WORKAROUND
 #ifdef CONFIG_SYS_CSPR0_EXT
        set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
 #endif
@@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
        set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
        set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
 #endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+       set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+       set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+       set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+       set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+       set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+       set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+       set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+       set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+       set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+       set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+       set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+       set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+       set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+       set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+       set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+       set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+       set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+       set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+       set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+       set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+       set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+       set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+       set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+       set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+       set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+       set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+       set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+       set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+       set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+       set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+       set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+       set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
 }
index 6e6f7dc..90d1065 100644 (file)
@@ -24,7 +24,7 @@
 #include <asm/fsl_srio.h>
 #include <asm/errno.h>
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 #define SRIO_PORT_ACCEPT_ALL 0x10000001
 #define SRIO_IB_ATMU_AR 0x80f55000
 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -299,7 +299,7 @@ void srio_init(void)
        }
 }
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
        struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
index 1009a31..1d46b14 100644 (file)
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT     0xff600000
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  3
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_NUM_DDR_CONTROLLERS     2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  3
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
 #ifdef CONFIG_PPC_B4860
index ba41b73..3baf4cc 100644 (file)
@@ -21,6 +21,7 @@
 #ifndef __ASM_PPC_FSL_IFC_H
 #define __ASM_PPC_FSL_IFC_H
 
+#ifdef CONFIG_FSL_IFC
 #include <config.h>
 #include <common.h>
 
@@ -798,13 +799,15 @@ extern void init_early_memctl_regs(void);
 #define set_ifc_ftim(i, j, v) \
                        (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
 
-#define FSL_IFC_BANK_COUNT     4
-
 enum ifc_chip_sel {
        IFC_CS0,
        IFC_CS1,
        IFC_CS2,
        IFC_CS3,
+       IFC_CS4,
+       IFC_CS5,
+       IFC_CS6,
+       IFC_CS7,
 };
 
 enum ifc_ftims {
@@ -907,6 +910,49 @@ struct fsl_ifc_gpcm {
        u32 res4[0x1F3];
 };
 
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define IFC_CSPR_REG_LEN       148
+#define IFC_AMASK_REG_LEN      144
+#define IFC_CSOR_REG_LEN       144
+#define IFC_FTIM_REG_LEN       576
+
+#define IFC_CSPR_USED_LEN      sizeof(struct fsl_ifc_cspr) * \
+                                       CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_AMASK_USED_LEN     sizeof(struct fsl_ifc_amask) * \
+                                       CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_CSOR_USED_LEN      sizeof(struct fsl_ifc_csor) * \
+                                       CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_FTIM_USED_LEN      sizeof(struct fsl_ifc_ftim) * \
+                                       CONFIG_SYS_FSL_IFC_BANK_COUNT
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
+
+struct fsl_ifc_cspr {
+       u32 cspr_ext;
+       u32 cspr;
+       u32 res;
+};
+
+struct fsl_ifc_amask {
+       u32 amask;
+       u32 res[0x2];
+};
+
+struct fsl_ifc_csor {
+       u32 csor;
+       u32 csor_ext;
+       u32 res;
+};
+
+struct fsl_ifc_ftim {
+       u32 ftim[4];
+       u32 res[0x8];
+};
 
 /*
  * IFC Controller Registers
@@ -914,44 +960,30 @@ struct fsl_ifc_gpcm {
 struct fsl_ifc {
        u32 ifc_rev;
        u32 res1[0x2];
-       struct {
-               u32 cspr_ext;
-               u32 cspr;
-               u32 res2;
-       } cspr_cs[FSL_IFC_BANK_COUNT];
-       u32 res3[0x19];
-       struct {
-               u32 amask;
-               u32 res4[0x2];
-       } amask_cs[FSL_IFC_BANK_COUNT];
-       u32 res5[0x17];
-       struct {
-               u32 csor_ext;
-               u32 csor;
-               u32 res6;
-       } csor_cs[FSL_IFC_BANK_COUNT];
-       u32 res7[0x19];
-       struct {
-               u32 ftim[4];
-               u32 res8[0x8];
-       } ftim_cs[FSL_IFC_BANK_COUNT];
-       u32 res9[0x60];
+       struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+       struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+       struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+       struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
        u32 rb_stat;
-       u32 res10[0x2];
+       u32 res6[0x2];
        u32 ifc_gcr;
-       u32 res11[0x2];
+       u32 res7[0x2];
        u32 cm_evter_stat;
-       u32 res12[0x2];
+       u32 res8[0x2];
        u32 cm_evter_en;
-       u32 res13[0x2];
+       u32 res9[0x2];
        u32 cm_evter_intr_en;
-       u32 res14[0x2];
+       u32 res10[0x2];
        u32 cm_erattr0;
        u32 cm_erattr1;
-       u32 res15[0x2];
+       u32 res11[0x2];
        u32 ifc_ccr;
        u32 ifc_csr;
-       u32 res16[0x2EB];
+       u32 res12[0x2EB];
        struct fsl_ifc_nand ifc_nand;
        struct fsl_ifc_nor ifc_nor;
        struct fsl_ifc_gpcm ifc_gpcm;
@@ -961,6 +993,7 @@ struct fsl_ifc {
 #undef CSPR_MSEL_NOR
 #define CSPR_MSEL_NOR  CSPR_MSEL_GPCM
 #endif
+#endif /* CONFIG_FSL_IFC */
 
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */
index 90b264d..bea1636 100644 (file)
@@ -82,11 +82,16 @@ enum law_trgt_if {
 #ifndef CONFIG_MPC8641
        LAW_TRGT_IF_PCIE_1 = 0x02,
 #endif
+#if defined(CONFIG_BSC9131)
+       LAW_TRGT_IF_OCN_DSP = 0x03,
+#else
 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
        LAW_TRGT_IF_PCIE_3 = 0x03,
+#endif
 #endif
        LAW_TRGT_IF_LBC = 0x04,
        LAW_TRGT_IF_CCSR = 0x08,
+       LAW_TRGT_IF_DSP_CCSR = 0x09,
        LAW_TRGT_IF_DDR_INTRLV = 0x0b,
        LAW_TRGT_IF_RIO = 0x0c,
        LAW_TRGT_IF_RIO_2 = 0x0d,
index 4052037..db70d04 100644 (file)
@@ -1839,11 +1839,13 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT  11
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL                0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT  3
+#define FSL_CORENET_RCWSR6_BOOT_LOC    0x0f800000
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL        0xfe000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL        0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT  16
+#define FSL_CORENET_RCWSR6_BOOT_LOC    0x0f800000
 #elif defined(CONFIG_PPC_T1040)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL        0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
@@ -2160,7 +2162,7 @@ typedef struct ccsr_gur {
        u32     porbmsr;        /* POR boot mode status */
 #define MPC85xx_PORBMSR_HA             0x00070000
 #define MPC85xx_PORBMSR_HA_SHIFT       16
-#define MPC85XX_PORBMSR_ROMLOC_SHIFT   24
+#define MPC85xx_PORBMSR_ROMLOC_SHIFT   24
 #define PORBMSR_ROMLOC_SPI     0x6
 #define PORBMSR_ROMLOC_SDHC    0x7
 #define PORBMSR_ROMLOC_NAND_2K 0x9
index dd6c98c..d4ad323 100644 (file)
@@ -256,11 +256,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
                return 0;
        }
 
-       if (flag & BOOTM_STATE_OS_GO) {
-               boot_jump_linux(images);
-               return 0;
-       }
-
        boot_prep_linux(images);
        ret = boot_body_linux(images);
        if (ret)
index dd8d495..e9385de 100644 (file)
@@ -37,7 +37,7 @@ void __udelay(unsigned long usec)
        os_usleep(usec);
 }
 
-unsigned long timer_get_us(void)
+unsigned long __attribute__((no_instrument_function)) timer_get_us(void)
 {
        return os_get_nsec() / 1000;
 }
index d075407..541e450 100644 (file)
@@ -152,7 +152,7 @@ void os_usleep(unsigned long usec)
        usleep(usec);
 }
 
-u64 os_get_nsec(void)
+u64 __attribute__((no_instrument_function)) os_get_nsec(void)
 {
 #if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK)
        struct timespec tp;
index 4fdb080..9a2056a 100644 (file)
@@ -40,7 +40,7 @@ struct arch_global_data {
 #include <asm-generic/global_data.h>
 
 #ifndef __ASSEMBLY__
-static inline gd_t *get_fs_gd_ptr(void)
+static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
 {
        gd_t *gd_ptr;
 
index 6030633..b459a63 100644 (file)
@@ -85,7 +85,8 @@ static inline unsigned long long native_read_tscp(unsigned int *aux)
 #define EAX_EDX_RET(val, low, high)    "=A" (val)
 #endif
 
-static inline unsigned long long native_read_msr(unsigned int msr)
+static inline __attribute__((no_instrument_function))
+       unsigned long long native_read_msr(unsigned int msr)
 {
        DECLARE_ARGS(val, low, high);
 
index 22e0934..709dc84 100644 (file)
@@ -64,7 +64,7 @@ void  board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
 void   board_init_f_r(void) __attribute__ ((noreturn));
 
 /* Read the time stamp counter */
-static inline uint64_t rdtsc(void)
+static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
 {
        uint32_t high, low;
        __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
index 2520228..0d3250c 100644 (file)
@@ -63,6 +63,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
                }
 #if defined(CONFIG_FIT)
        } else if (images->fit_uname_os) {
+               int ret;
+
                ret = fit_image_get_data(images->fit_hdr_os,
                                        images->fit_noffset_os, &data, &len);
                if (ret) {
index 4043431..497ad75 100644 (file)
@@ -28,7 +28,9 @@
 #define WRAP_LIBGCC_CALL(type, name) \
        type __normal_##name(type a, type b) __attribute__((regparm(0))); \
        type __wrap_##name(type a, type b); \
-       type __wrap_##name(type a, type b) { return __normal_##name(a, b); }
+       type __attribute__((no_instrument_function)) \
+               __wrap_##name(type a, type b) \
+                { return __normal_##name(a, b); }
 
 WRAP_LIBGCC_CALL(long long, __divdi3)
 WRAP_LIBGCC_CALL(unsigned long long, __udivdi3)
index c509801..0688973 100644 (file)
@@ -37,7 +37,7 @@ void timer_set_base(u64 base)
  * restart. This yields a free running counter guaranteed to take almost 6
  * years to wrap around even at 100GHz clock rate.
  */
-u64 get_ticks(void)
+u64 __attribute__((no_instrument_function)) get_ticks(void)
 {
        u64 now_tick = rdtsc();
 
@@ -50,7 +50,7 @@ u64 get_ticks(void)
 #define PLATFORM_INFO_MSR 0xce
 
 /* Get the speed of the TSC timer in MHz */
-unsigned long get_tbclk_mhz(void)
+unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
 {
        u32 ratio;
        u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
@@ -75,7 +75,7 @@ ulong get_timer(ulong base)
        return get_ms_timer() - base;
 }
 
-ulong timer_get_us(void)
+ulong __attribute__((no_instrument_function)) timer_get_us(void)
 {
        return get_ticks() / get_tbclk_mhz();
 }
diff --git a/board/LaCie/common/cpld-gpio-bus.c b/board/LaCie/common/cpld-gpio-bus.c
new file mode 100644 (file)
index 0000000..fb9bf8d
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
+ * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
+ * bus exposes two registers (address and data). Each of this register is made
+ * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
+ * the registers have been updated.
+ *
+ * Mostly this bus is used to configure the LEDs on LaCie boards.
+ *
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/arch/gpio.h>
+#include "cpld-gpio-bus.h"
+
+static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
+{
+       int pin;
+
+       for (pin = 0; pin < bus->num_addr; pin++)
+               kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
+}
+
+static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
+{
+       int pin;
+
+       for (pin = 0; pin < bus->num_data; pin++)
+               kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
+}
+
+static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
+{
+       /* The transfer is enabled on the raising edge. */
+       kw_gpio_set_value(bus->enable, 0);
+       kw_gpio_set_value(bus->enable, 1);
+}
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
+                        unsigned addr, unsigned value)
+{
+       cpld_gpio_bus_set_addr(bus, addr);
+       cpld_gpio_bus_set_data(bus, value);
+       cpld_gpio_bus_enable_select(bus);
+}
diff --git a/board/LaCie/common/cpld-gpio-bus.h b/board/LaCie/common/cpld-gpio-bus.h
new file mode 100644 (file)
index 0000000..e9e9b96
--- /dev/null
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _LACIE_CPLD_GPI0_BUS_H
+#define _LACIE_CPLD_GPI0_BUS_H
+
+struct cpld_gpio_bus {
+       unsigned *addr;
+       unsigned num_addr;
+       unsigned *data;
+       unsigned num_data;
+       unsigned enable;
+};
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
+                        unsigned addr, unsigned value);
+
+#endif /* _LACIE_CPLD_GPI0_BUS_H */
index fbae48e..9a6dfb6 100644 (file)
@@ -28,6 +28,9 @@ endif
 LIB    = $(obj)lib$(BOARD).o
 
 COBJS  := $(BOARD).o ../common/common.o
+ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
+COBJS  += ../common/cpld-gpio-bus.o
+endif
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
index e524f35..b133f7c 100644 (file)
@@ -22,6 +22,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <i2c.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
@@ -29,6 +30,7 @@
 
 #include "net2big_v2.h"
 #include "../common/common.h"
+#include "../common/cpld-gpio-bus.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -60,18 +62,18 @@ int board_early_init_f(void)
                MPP24_GPIO,             /* USB mode select */
                MPP26_GPIO,             /* USB device vbus */
                MPP28_GPIO,             /* USB enable host vbus */
-               MPP29_GPIO,             /* GPIO extension ALE */
+               MPP29_GPIO,             /* CPLD GPIO bus ALE */
                MPP34_GPIO,             /* Rear Push button 0=on 1=off */
                MPP35_GPIO,             /* Inhibit switch power-off */
                MPP36_GPIO,             /* SATA HDD1 presence */
                MPP37_GPIO,             /* SATA HDD2 presence */
                MPP40_GPIO,             /* eSATA presence */
-               MPP44_GPIO,             /* GPIO extension (data 0) */
-               MPP45_GPIO,             /* GPIO extension (data 1) */
-               MPP46_GPIO,             /* GPIO extension (data 2) */
-               MPP47_GPIO,             /* GPIO extension (addr 0) */
-               MPP48_GPIO,             /* GPIO extension (addr 1) */
-               MPP49_GPIO,             /* GPIO extension (addr 2) */
+               MPP44_GPIO,             /* CPLD GPIO bus (data 0) */
+               MPP45_GPIO,             /* CPLD GPIO bus (data 1) */
+               MPP46_GPIO,             /* CPLD GPIO bus (data 2) */
+               MPP47_GPIO,             /* CPLD GPIO bus (addr 0) */
+               MPP48_GPIO,             /* CPLD GPIO bus (addr 1) */
+               MPP49_GPIO,             /* CPLD GPIO bus (addr 2) */
                0
        };
 
@@ -92,8 +94,142 @@ int board_init(void)
 }
 
 #if defined(CONFIG_MISC_INIT_R)
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+/*
+ * Start I2C fan (GMT G762 controller)
+ */
+static void init_fan(void)
+{
+       u8 data;
+
+       i2c_set_bus_num(0);
+
+       /* Enable open-loop and PWM modes */
+       data = 0x20;
+       if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+                     G762_REG_FAN_CMD1, 1, &data, 1) != 0)
+               goto err;
+       data = 0;
+       if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+                     G762_REG_SET_CNT, 1, &data, 1) != 0)
+               goto err;
+       /*
+        * RPM to PWM (set_out register) fan speed conversion array:
+        * 0    0x00
+        * 1500 0x04
+        * 2800 0x08
+        * 3400 0x0C
+        * 3700 0x10
+        * 4400 0x20
+        * 4700 0x30
+        * 4800 0x50
+        * 5200 0x80
+        * 5400 0xC0
+        * 5500 0xFF
+        *
+        * Start fan at low speed (2800 RPM):
+        */
+       data = 0x08;
+       if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+                     G762_REG_SET_OUT, 1, &data, 1) != 0)
+               goto err;
+
+       return;
+err:
+       printf("Error: failed to start I2C fan @%02x\n",
+              CONFIG_SYS_I2C_G762_ADDR);
+}
+#else
+static void init_fan(void) {}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+
+#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
+/*
+ * CPLD GPIO bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register    : bit [0-2] -> GPIO [44-46]
+ * - enable register  : GPIO 29
+ */
+static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
+static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
+
+static struct cpld_gpio_bus cpld_gpio_bus = {
+       .addr           = cpld_gpio_bus_addr,
+       .num_addr       = ARRAY_SIZE(cpld_gpio_bus_addr),
+       .data           = cpld_gpio_bus_data,
+       .num_data       = ARRAY_SIZE(cpld_gpio_bus_data),
+       .enable         = 29,
+};
+
+/*
+ * LEDs configuration:
+ *
+ * The LEDs are controlled by a CPLD and can be configured through
+ * the CPLD GPIO bus.
+ *
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ *   0  | front LED
+ *   1  | front LED brightness
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ *   0  | min (off)
+ *   -  | -
+ *   7  | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | fix blue on
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | SATA activity blink
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | fix blue on
+ */
+static void init_leds(void)
+{
+       /* Enable the front blue LED */
+       cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
+       cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
+
+       /* Configure SATA LEDs to blink in relation with the SATA activity */
+       cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
+       cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
+       cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
+}
+#else
+static void init_leds(void) {}
+#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
+
 int misc_init_r(void)
 {
+       init_fan();
 #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
        if (!getenv("ethaddr")) {
                uchar mac[6];
@@ -101,9 +237,11 @@ int misc_init_r(void)
                        eth_setenv_enetaddr("ethaddr", mac);
        }
 #endif
+       init_leds();
+
        return 0;
 }
-#endif
+#endif /* CONFIG_MISC_INIT_R */
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
 /* Configure and initialize PHY */
index f9778f4..83537d6 100644 (file)
@@ -32,4 +32,9 @@
 /* Buttons */
 #define NET2BIG_V2_GPIO_PUSH_BUTTON    34
 
+/* GMT G762 registers (I2C fan controller) */
+#define G762_REG_SET_CNT               0x00
+#define G762_REG_SET_OUT               0x03
+#define G762_REG_FAN_CMD1              0x04
+
 #endif /* NET2BIG_V2_H */
index ef4a25b..74aec5f 100644 (file)
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/actux1/libactux1.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }
index 00ad8b7..c276501 100644 (file)
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/actux2/libactux2.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }
index 44b990e..5610644 100644 (file)
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/actux3/libactux3.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }
index 1daa1b3..3972685 100644 (file)
@@ -54,11 +54,6 @@ SECTIONS
                __rel_dyn_end = .;
        } >.sram
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       } >.sram
-
        .bss :
        {
                . = ALIGN(4);
index 8752794..3013a42 100644 (file)
@@ -33,6 +33,7 @@
 #include <lcd.h>
 #include <atmel_hlcdc.h>
 #include <atmel_mci.h>
+#include <netdev.h>
 
 #ifdef CONFIG_LCD_INFO
 #include <nand.h>
@@ -190,6 +191,30 @@ int board_mmc_init(bd_t *bd)
 }
 #endif
 
+#ifdef CONFIG_KS8851_MLL
+void at91sam9n12ek_ks8851_hw_init(void)
+{
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+       writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+              AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+              &smc->cs[2].setup);
+       writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+              AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
+              &smc->cs[2].pulse);
+       writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
+              &smc->cs[2].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+              AT91_SMC_MODE_EXNW_DISABLE |
+              AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+              AT91_SMC_MODE_TDF_CYCLE(1),
+              &smc->cs[2].mode);
+
+       /* Configure NCS2 PIN */
+       at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
+}
+#endif
+
 int board_early_init_f(void)
 {
        /* Enable clocks for all PIOs */
@@ -217,9 +242,20 @@ int board_init(void)
        at91_lcd_hw_init();
 #endif
 
+#ifdef CONFIG_KS8851_MLL
+       at91sam9n12ek_ks8851_hw_init();
+#endif
+
        return 0;
 }
 
+#ifdef CONFIG_KS8851_MLL
+int board_eth_init(bd_t *bis)
+{
+       return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
+}
+#endif
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
index b1b8701..6fa4509 100644 (file)
@@ -55,11 +55,6 @@ SECTIONS
                __rel_dyn_end = .;
        } >.sram
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
-       } >.sram
-
        .bss :
        {
                . = ALIGN(4);
index 596a9e0..b452f20 100644 (file)
@@ -61,7 +61,6 @@ SECTIONS
        __image_copy_end = .;
        __rel_dyn_start = .;
        __rel_dyn_end = .;
-       __dynsym_start = .;
 
        __got_start = .;
        . = ALIGN(4);
index 6d4b187..f359112 100644 (file)
@@ -30,6 +30,7 @@ SECTIONS
 
        . = ALIGN (4);
        .text : {
+               *(.__image_copy_start)
                arch/arm/cpu/ixp/start.o(.text*)
                net/libnet.o(.text*)
                board/dvlhost/libdvlhost.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
        . = ALIGN (4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -96,6 +103,7 @@ SECTIONS
                KEEP(*(.__bss_end));
        }
 
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynamic*) }
        /DISCARD/ : { *(.plt*) }
index 89f1b1d..4c3656e 100644 (file)
@@ -207,9 +207,14 @@ int misc_init_r (void)
                buf[4] = eerev.etheraddr[5];
                buf[5] = eerev.etheraddr[4];
 
-               *(unsigned short *) &buf[20] = 0x48B2;
-               *(unsigned short *) &buf[22] = 0x0004;
-               *(unsigned short *) &buf[24] = 0x1433;
+               buf[20] = 0x48;
+               buf[21] = 0xB2;
+
+               buf[22] = 0x00;
+               buf[23] = 0x04;
+
+               buf[24] = 0x14;
+               buf[25] = 0x33;
 
                printf ("\nSRom:  Writing i82559 info ........ ");
                if (eepro100_srom_store ((unsigned short *) buf) == -1)
index 29cc41b..1416f98 100644 (file)
@@ -52,6 +52,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+       /*
+        * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+        * space is at 0xfff00000, it covered the 0xfffff000.
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+                     CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_1M, 1),
 #else
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -137,6 +146,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
                MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 16, BOOKE_PAGESZ_256M, 1),
 #endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+       /*
+        * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+        * fetching ucode and ENV from master
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+                     CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+                     0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 6f4cb26..2e829ad 100644 (file)
@@ -24,12 +24,28 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y        += spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
 #COBJS-y               += bsc9131rdb_mux.o
 
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
index 065faa3..4902b98 100644 (file)
@@ -89,10 +89,14 @@ NAND boot
 Building U-boot
 --------------
 To build the u-boot for BSC9131RDB:
-1. NAND Flash
+1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
        make BSC9131RDB_NAND
-2. SPI Flash
+2. NAND Flash with sysclk 100MHz(J16 on RDB open)
+       make BSC9131RDB_NAND_SYSCLK100
+3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
        make BSC9131RDB_SPIFLASH
+4. SPI Flash with sysclk 100MHz(J16 on RDB open)
+       make BSC9131RDB_SPIFLASH_SYSCLK100
 
 Memory map
 -----------
@@ -107,6 +111,16 @@ Memory map
  0xFF70_0000   0xFF7F_FFFF     PA CCSR                 1M
  0xFF80_0000   0xFFFF_FFFF     Boot Page & NAND Buffer 8M
 
+DDR Memory map
+---------------
+ 0x0000_0000   0x36FF_FFFF     Memory passed onto Linux
+ 0x3700_0000   0x37FF_FFFF     PowerPC-DSP shared control area
+ 0x3800_0000   0x4FFF_FFFF     DSP Private area
+
+ Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
+ data communcation between PowerPC and DSP core.
+ Rest is PowerPC private area.
+
 Flashing Images
 ---------------
 To place a new u-boot image in the NAND flash and then boot
index 201c147..0432780 100644 (file)
 
 struct law_entry law_table[] = {
        SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+       SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+               LAW_TRGT_IF_DSP_CCSR),
+       SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
+               LAW_TRGT_IF_OCN_DSP),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
new file mode 100644 (file)
index 0000000..301115e
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+static void sdram_init(void)
+{
+       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+
+       __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+       __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+       __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+       __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+       __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+
+       __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+       __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+       __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+
+       __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+       __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+       __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+
+       __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+       __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+
+       /* Set, but do not enable the memory */
+       __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+       asm volatile("sync;isync");
+       udelay(500);
+
+       /* Let the controller go */
+       out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+       set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+       u32 plat_ratio;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+       /* initialize selected port with appropriate baud rate */
+       plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+       plat_ratio >>= 1;
+       gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                    gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+       puts("\nNAND boot... ");
+
+       /* Initialize the DDR3 */
+       sdram_init();
+
+       /* copy code to RAM and jump to it - this should not return */
+       /* NOTE - code has to be copied out of NAND buffer before
+        * other blocks can be read.
+        */
+       relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       nand_boot();
+}
+
+void putc(char c)
+{
+       if (c == '\n')
+               NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+       NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+       while (*str)
+               putc(*str++);
+}
index 5b68f4a..c05a556 100644 (file)
@@ -44,15 +44,26 @@ struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 0, BOOKE_PAGESZ_4K, 1),
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+       SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
        /* *I*G* - CCSRBAR (PA) */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 1, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT)
+       /* CCSRBAR (DSP) */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+                     CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if  defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 8, BOOKE_PAGESZ_1G, 1),
index 267400b..72b1917 100644 (file)
@@ -24,11 +24,28 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y        += spl_minimal.o tlb.o law.o
+
+else
+
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
 
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
index 6e1b558..ddc9d0a 100644 (file)
@@ -258,7 +258,7 @@ int misc_init_r(void)
        u8 val;
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        u32 porbmsr = in_be32(&gur->porbmsr);
-       u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+       u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
 
        /*Configure 1588 clock-in source from RF Card*/
        val = QIXIS_READ_I2C(brdcfg[5]);
@@ -360,7 +360,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        u32 porbmsr = in_be32(&gur->porbmsr);
-       u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+       u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
 
        if (!(hwconfig("uart2") && hwconfig("usb1"))) {
                /* If uart2 is there in hwconfig remove usb node from
index dc23658..b4bce99 100644 (file)
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
        SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
-#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
        SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_FPGA_BASE_PHYS
        SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
new file mode 100644 (file)
index 0000000..62dee52
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_init(void)
+{
+       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+#if CONFIG_DDR_CLK_FREQ == 100000000
+       __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+       __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+       __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+       __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
+       __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+       __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+       __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+       __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+       __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+       __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+       __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+
+       __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
+       __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+       __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+       __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+       __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+       __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
+       __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+       __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
+       __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
+       __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
+       __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
+       __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
+       __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
+
+       __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
+       __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#else
+       puts("Not a valid DDR Freq Found! Please Reset\n");
+#endif
+       asm volatile("sync;isync");
+       udelay(500);
+
+       /* Let the controller go */
+       out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+       set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+       u32 plat_ratio;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+       /* initialize selected port with appropriate baud rate */
+       plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+       plat_ratio >>= 1;
+       gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                    gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+       puts("\nNAND boot... ");
+
+       /* Initialize the DDR3 */
+       sdram_init();
+
+       /* copy code to RAM and jump to it - this should not return */
+       /* NOTE - code has to be copied out of NAND buffer before
+        * other blocks can be read.
+        */
+       relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       nand_boot();
+}
+
+void putc(char c)
+{
+       if (c == '\n')
+               NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+       NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+       while (*str)
+               putc(*str++);
+}
index 0e4545f..0ec9a85 100644 (file)
@@ -44,14 +44,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 0, BOOKE_PAGESZ_4K, 1),
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+       SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
        /* *I*G* - CCSRBAR (PA) */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 1, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                        0, 3, BOOKE_PAGESZ_64M, 1),
@@ -61,12 +67,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                        0, 4, BOOKE_PAGESZ_64M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT)
-       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
-                       0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
 #ifdef CONFIG_PCI
        /* *I*G* - PCI */
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
@@ -78,15 +78,26 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 7, BOOKE_PAGESZ_64K, 1),
 #endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
 
+#ifdef CONFIG_SYS_FPGA_BASE
                /* *I*G - Board FPGA  */
        SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 9, BOOKE_PAGESZ_256K, 1),
+#endif
 
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 72bb56c..37236d0 100644 (file)
@@ -29,6 +29,15 @@ endif
 
 LIB    = $(obj)libfreescale.o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifndef MINIMAL
 COBJS-$(CONFIG_FSL_CADMUS)     += cadmus.o
 COBJS-$(CONFIG_FSL_VIA)                += cds_via.o
 COBJS-$(CONFIG_FMAN_ENET)      += fman.o
@@ -68,6 +77,7 @@ SUBLIB-$(CONFIG_P3041DS)      += p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P4080DS)       += p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5020DS)       += p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5040DS)       += p_corenet/libp_corenet.o
+endif
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
index 8d07061..fbb709d 100644 (file)
@@ -480,6 +480,7 @@ static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
            ||  unknown_param) {
 #ifdef CONFIG_SYS_LONGHELP
                puts(cmdtp->help);
+               putc('\n');
 #endif
                return 1;
        }
@@ -512,6 +513,7 @@ static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
                      && set_px_mpxpll(mpxpll))) {
 #ifdef CONFIG_SYS_LONGHELP
                        puts(cmdtp->help);
+                       putc('\n');
 #endif
                        return 1;
                }
index 4969960..963d29f 100644 (file)
@@ -34,6 +34,7 @@ SECTIONS
        . = ALIGN(4);
        .text      :
        {
+               *(.__image_copy_start)
          /* WARNING - the following is hand-optimized to fit within    */
          /* the sector layout of our flash chips!      XXX FIXME XXX   */
 
@@ -65,17 +66,23 @@ SECTIONS
 
        . = ALIGN(4);
 
-       __image_copy_end = .;
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
 
        .rel.dyn : {
-               __rel_dyn_start = .;
                *(.rel*)
-               __rel_dyn_end = .;
        }
 
-       .dynsym : {
-               __dynsym_start = .;
-               *(.dynsym)
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
        }
 
        _end = .;
@@ -100,6 +107,7 @@ SECTIONS
        }
 
        /DISCARD/ : { *(.bss*) }
+       /DISCARD/ : { *(.dynsym) }
        /DISCARD/ : { *(.dynstr*) }
        /DISCARD/ : { *(.dynsym*) }
        /DISCARD/ : { *(.dynamic*) }
index 4c705b6..e6563be 100644 (file)
@@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y        += spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
 
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
similarity index 95%
rename from nand_spl/board/freescale/p1010rdb/nand_boot.c
rename to board/freescale/p1010rdb/spl_minimal.c
index 3c7bc2b..c909e0e 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned long ddr_freq_mhz;
 
 void sdram_init(void)
 {
        ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       u32 ddr_ratio;
+       unsigned long ddr_freq_mhz;
+
+       ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+       ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+       ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
+
        /* mask off E bit */
        u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
 
@@ -81,6 +88,7 @@ void sdram_init(void)
                __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
        }
 
+       asm volatile("sync;isync");
        udelay(500);
 
        /* Let the controller go */
@@ -91,7 +99,7 @@ void sdram_init(void)
 
 void board_init_f(ulong bootflag)
 {
-       u32 plat_ratio, ddr_ratio;
+       u32 plat_ratio;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
        /* initialize selected port with appropriate baud rate */
@@ -99,10 +107,6 @@ void board_init_f(ulong bootflag)
        plat_ratio >>= 1;
        gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
 
-       ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-       ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-       ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
-
        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
                        gd->bus_clk / 16 / CONFIG_BAUDRATE);
 
@@ -115,8 +119,8 @@ void board_init_f(ulong bootflag)
        /* NOTE - code has to be copied out of NAND buffer before
         * other blocks can be read.
         */
-       relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
-                       CONFIG_SYS_NAND_U_BOOT_RELOC);
+
+       relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
 }
 
 void board_init_r(gd_t *gd, ulong dest_addr)
index 4256bf4..078717a 100644 (file)
@@ -44,15 +44,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 0, BOOKE_PAGESZ_4K, 1),
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+       SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
        /* *I*G* - CCSRBAR */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 1, BOOKE_PAGESZ_1M, 1),
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 #ifndef CONFIG_SDCARD
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
@@ -88,7 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 8, BOOKE_PAGESZ_1G, 1)
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
new file mode 100644 (file)
index 0000000..45c4f8b
--- /dev/null
@@ -0,0 +1,33 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS-y        += $(BOARD).o
+COBJS-y        += ddr.o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644 (file)
index 0000000..7ed275a
--- /dev/null
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+       .n_ranks = 1,
+       .rank_density = 536870912u,
+       .capacity = 536870912u,
+       .primary_sdram_width = 32,
+       .ec_sdram_width = 0,
+       .registered_dimm = 0,
+       .mirrored_dimm = 0,
+       .n_row_addr = 14,
+       .n_col_addr = 10,
+       .n_banks_per_sdram_device = 8,
+       .edc_config = 0,
+       .burst_lengths_bitmask = 0x0c,
+
+       .tCKmin_X_ps = 1875,
+       .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
+       .tAA_ps = 13125,
+       .tWR_ps = 18000,
+       .tRCD_ps = 13125,
+       .tRRD_ps = 7500,
+       .tRP_ps = 13125,
+       .tRAS_ps = 37500,
+       .tRC_ps = 50625,
+       .tRFC_ps = 160000,
+       .tWTR_ps = 7500,
+       .tRTP_ps = 7500,
+       .refresh_rate_ps = 7800000,
+       .tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+               unsigned int controller_number,
+               unsigned int dimm_number)
+{
+       const char dimm_model[] = "Fixed DDR on board";
+
+       if ((controller_number == 0) && (dimm_number == 0)) {
+               memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+               memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+               memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+       }
+
+       return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       int i;
+       popts->clk_adjust = 6;
+       popts->cpo_override = 0x1f;
+       popts->write_data_delay = 2;
+       popts->half_strength_driver_enable = 1;
+       /* Write leveling override */
+       popts->wrlvl_en = 1;
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0xf;
+       popts->wrlvl_start = 0x8;
+       popts->trwt_override = 1;
+       popts->trwt = 0;
+
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+               popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+       }
+}
+
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
new file mode 100644 (file)
index 0000000..331662c
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
+               LAW_TRGT_IF_DPAA_SWP_SRAM),
+       SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
new file mode 100644 (file)
index 0000000..918398b
--- /dev/null
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *           Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_portals.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+       fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+       /* Set ABSWP to implement conversion of addresses in the LBC */
+       setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       printf("Board: P1023 RDB\n");
+
+       return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+       fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+       const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+       const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+       /*
+        * Remap Boot flash + PROMJET region to caching-inhibited
+        * so that flash can be erased properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       /* invalidate existing TLB entry for flash + promjet */
+       disable_tlb(flash_esel);
+
+       set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+               MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+       setup_portals();
+
+       return 0;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+       return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+       return gd->mem_clk;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       struct fsl_pq_mdio_info dtsec_mdio_info;
+
+       /*
+        * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
+        * is not correct.
+        */
+       setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
+
+       dtsec_mdio_info.regs =
+               (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+       dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+       /* Register the 1G MDIO bus */
+       fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+       fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+       fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+
+       fm_info_set_mdio(FM1_DTSEC1,
+                        miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+       fm_info_set_mdio(FM1_DTSEC2,
+                        miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+#ifdef CONFIG_FMAN_ENET
+       cpu_eth_init(bis);
+#endif
+
+       return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+
+       ft_cpu_setup(blob, bd);
+
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+       fdt_fixup_dr_usb(blob, bd);
+#endif
+
+       fdt_fixup_fman_ethernet(blob);
+}
+#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
new file mode 100644 (file)
index 0000000..3417c0f
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* TLB 1 */
+       /* *I*** - Covers boot page */
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+
+       /* *I*G* - CCSRBAR */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 1, BOOKE_PAGESZ_4M, 1),
+
+       /* W**G* - Flash, localbus */
+       /* This will be changed to *I*G* after relocation to RAM. */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+                     0, 2, BOOKE_PAGESZ_256M, 1),
+
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 3, BOOKE_PAGESZ_1G, 1),
+
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+                     CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 4, BOOKE_PAGESZ_256M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+                     CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 5, BOOKE_PAGESZ_256M, 1),
+
+       /* *I*G* - PCI I/O */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 6, BOOKE_PAGESZ_256K, 1),
+
+       /* Bman/Qman */
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+                     MAS3_SW|MAS3_SR, 0,
+                     0, 7, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+                     CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 8, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_M,
+                     0, 9, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+                     CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_1M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 11, BOOKE_PAGESZ_16K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+                     CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 12, BOOKE_PAGESZ_256M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+                     CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 92c01cf..a138d5a 100644 (file)
@@ -55,6 +55,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+       /*
+        * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+        * space is at 0xfff00000, it covered the 0xfffff000.
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+                     CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_1M, 1),
 #else
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -130,6 +139,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 17, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+       /*
+        * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+        * fetching ucode and ENV from master
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+                     CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+                     0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
 
 };
 
index 7442591..dc2aff0 100644 (file)
 #include <i2c.h>
 #endif
 
+static int eeprom_diag;
+static int mac_diag;
+static int gpio_diag;
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static void gpio_configure(void)
@@ -37,7 +41,7 @@ static void gpio_configure(void)
 
        /*
         * out_be32(&gpioregs->gpdir, 0xC2293020);
-        * workaround for a hardware affect: configure direction in pieces,
+        * workaround for a hardware effect: configure direction in pieces,
         * setting all outputs at once drops the reset line too low and
         * makes us lose the MII connection (breaks ethernet for us)
         */
@@ -126,8 +130,6 @@ static u32 gpio_querykbd(void)
 
 /* excerpt from the recovery's hw_info.h */
 
-static int eeprom_diag = 1;
-
 struct __attribute__ ((__packed__)) eeprom_layout {
        char    magic[3];       /** 'ifm' */
        u8      len[2];         /** content length without magic/len fields */
@@ -209,6 +211,7 @@ static int read_eeprom(void)
 int mac_read_from_eeprom(void)
 {
        const u8 *mac;
+       const char *mac_txt;
 
        if (read_eeprom()) {
                printf("I2C EEPROM read failed.\n");
@@ -230,8 +233,13 @@ int mac_read_from_eeprom(void)
 
        if (mac && is_valid_ether_addr(mac)) {
                eth_setenv_enetaddr("ethaddr", mac);
-               printf("DIAG: %s() MAC value [%s]\n",
-                       __func__, getenv("ethaddr"));
+               if (mac_diag) {
+                       mac_txt = getenv("ethaddr");
+                       if (mac_txt)
+                               printf("DIAG: MAC value [%s]\n", mac_txt);
+                       else
+                               printf("DIAG: failed to setup MAC env\n");
+               }
        }
 
        return 0;
@@ -326,42 +334,38 @@ int misc_init_r(void)
        gpio_configure();
 
        /*
-        * check the GPIO keyboard,
-        * enforced start of the recovery when
+        * enforce the start of the recovery system when
         * - the appropriate keys were pressed
-        * - a previous installation was aborted or has failed
         * - "some" external software told us to
+        * - a previous installation was aborted or has failed
         */
        want_recovery = 0;
        keys = gpio_querykbd();
-       printf("GPIO keyboard status [0x%08X]\n", keys);
-       /* XXX insist in the _exact_ combination? */
+       if (gpio_diag)
+               printf("GPIO keyboard status [0x%02X]\n", keys);
        if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
-               printf("GPIO keyboard requested RECOVERY\n");
-               /* XXX TODO
-                * refine the logic to detect the first keypress, and
-                * wait to recheck IF it was the recovery combination?
-                */
+               printf("detected recovery request (keyboard)\n");
                want_recovery = 1;
        }
-       s = getenv("install_in_progress");
+       s = getenv("want_recovery");
        if ((s != NULL) && (*s != '\0')) {
-               printf("previous installation aborted, running RECOVERY\n");
+               printf("detected recovery request (environment)\n");
                want_recovery = 1;
        }
-       s = getenv("install_failed");
+       s = getenv("install_in_progress");
        if ((s != NULL) && (*s != '\0')) {
-               printf("previous installation FAILED, running RECOVERY\n");
+               printf("previous installation has not completed\n");
                want_recovery = 1;
        }
-       s = getenv("want_recovery");
+       s = getenv("install_failed");
        if ((s != NULL) && (*s != '\0')) {
-               printf("running RECOVERY according to the request\n");
+               printf("previous installation has failed\n");
                want_recovery = 1;
        }
-
-       if (want_recovery)
+       if (want_recovery) {
+               printf("enforced start of the recovery system\n");
                setenv("bootcmd", "run recovery");
+       }
 
        /*
         * boot the recovery system without waiting; boot the
index 826cead..ea3bea5 100644 (file)
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define RMII_MODE_ENABLE       0x4D
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
        .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
@@ -131,23 +107,9 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regval;
-
        enable_uart0_pin_mux();
 
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_RESET;
-       writel(regval, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) &
-               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_SMART_IDLE_EN;
-       writel(regval, &uart_base->uartsyscfg);
-
+       uart_soft_reset();
        gd = &gdata;
 
        preloader_console_init();
index 93c611d..0cca8d7 100644 (file)
@@ -39,9 +39,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE                0x0
@@ -50,31 +47,11 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
 /* DDR RAM defines */
 #define DDR_CLK_MHZ            303 /* DDR_DPLL_MULT value */
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41J256M8HX15E_RD_DQS,
        .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -141,22 +118,8 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regval;
-
        enable_uart0_pin_mux();
-
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_RESET;
-       writel(regval, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
-               != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_SMART_IDLE_EN;
-       writel(regval, &uart_base->uartsyscfg);
+       uart_soft_reset();
 
        gd = &gdata;
 
index 8da973b..93375a6 100644 (file)
                spi2 = "/spi@12d40000";
                spi3 = "/spi@131a0000";
                spi4 = "/spi@131b0000";
+               mmc0 = "/mmc@12200000";
+               mmc1 = "/mmc@12210000";
+               mmc2 = "/mmc@12220000";
+               mmc3 = "/mmc@12230000";
        };
 
        sromc@12250000 {
                samsung,ycbcr-coeff = <0>;
                samsung,color-depth = <1>;
        };
+
+       mmc@12200000 {
+               samsung,bus-width = <8>;
+               samsung,timing = <1 3 3>;
+               samsung,removable = <0>;
+       };
+
+       mmc@12210000 {
+               status = "disabled";
+       };
+
+       mmc@12220000 {
+               samsung,bus-width = <4>;
+               samsung,timing = <1 2 3>;
+               samsung,removable = <1>;
+       };
+
+       mmc@12230000 {
+               status = "disabled";
+       };
 };
index 24658c1..d2ccc66 100644 (file)
                spi4 = "/spi@131b0000";
        };
 
+       i2c4: i2c@12ca0000 {
+               cros-ec@1e {
+                       reg = <0x1e>;
+                       compatible = "google,cros-ec";
+                       i2c-max-frequency = <100000>;
+                       ec-interrupt = <&gpio 782 1>;
+               };
+
+               power-regulator@48 {
+                       compatible = "ti,tps65090";
+                       reg = <0x48>;
+               };
+       };
+
+       spi@131b0000 {
+               spi-max-frequency = <1000000>;
+               spi-deactivate-delay = <100>;
+               cros-ec@0 {
+                       reg = <0>;
+                       compatible = "google,cros-ec";
+                       spi-max-frequency = <5000000>;
+                       ec-interrupt = <&gpio 782 1>;
+                       optimise-flash-write;
+                       status = "disabled";
+               };
+       };
+
        sound@12d60000 {
                samsung,i2s-epll-clock-frequency = <192000000>;
                samsung,i2s-sampling-rate = <48000>;
                samsung,dc-value        = <25>;
        };
 
+       cros-ec-keyb {
+               compatible = "google,cros-ec-keyb";
+               google,key-rows = <8>;
+               google,key-columns = <13>;
+               google,repeat-delay-ms = <240>;
+               google,repeat-rate-ms = <30>;
+               google,ghost-filter;
+               /*
+                * Keymap entries take the form of 0xRRCCKKKK where
+                * RR=Row CC=Column KKKK=Key Code
+                * The values below are for a US keyboard layout and
+                * are taken from the Linux driver. Note that the
+                * 102ND key is not used for US keyboards.
+                */
+               linux,keymap = <
+                       /* CAPSLCK F1         B          F10     */
+                       0x0001003a 0x0002003b 0x00030030 0x00040044
+                       /* N       =          R_ALT      ESC     */
+                       0x00060031 0x0008000d 0x000a0064 0x01010001
+                       /* F4      G          F7         H       */
+                       0x0102003e 0x01030022 0x01040041 0x01060023
+                       /* '       F9         BKSPACE    L_CTRL  */
+                       0x01080028 0x01090043 0x010b000e 0x0200001d
+                       /* TAB     F3         T          F6      */
+                       0x0201000f 0x0202003d 0x02030014 0x02040040
+                       /* ]       Y          102ND      [       */
+                       0x0205001b 0x02060015 0x02070056 0x0208001a
+                       /* F8      GRAVE      F2         5       */
+                       0x02090042 0x03010029 0x0302003c 0x03030006
+                       /* F5      6          -          \       */
+                       0x0304003f 0x03060007 0x0308000c 0x030b002b
+                       /* R_CTRL  A          D          F       */
+                       0x04000061 0x0401001e 0x04020020 0x04030021
+                       /* S       K          J          ;       */
+                       0x0404001f 0x04050025 0x04060024 0x04080027
+                       /* L       ENTER      Z          C       */
+                       0x04090026 0x040b001c 0x0501002c 0x0502002e
+                       /* V       X          ,          M       */
+                       0x0503002f 0x0504002d 0x05050033 0x05060032
+                       /* L_SHIFT /          .          SPACE   */
+                       0x0507002a 0x05080035 0x05090034 0x050B0039
+                       /* 1       3          4          2       */
+                       0x06010002 0x06020004 0x06030005 0x06040003
+                       /* 8       7          0          9       */
+                       0x06050009 0x06060008 0x0608000b 0x0609000a
+                       /* L_ALT   DOWN       RIGHT      Q       */
+                       0x060a0038 0x060b006c 0x060c006a 0x07010010
+                       /* E       R          W          I       */
+                       0x07020012 0x07030013 0x07040011 0x07050017
+                       /* U       R_SHIFT    P          O       */
+                       0x07060016 0x07070036 0x07080019 0x07090018
+                       /* UP      LEFT    */
+                       0x070b0067 0x070c0069>;
+       };
 };
index 9daa0da..be9d418 100644 (file)
@@ -87,12 +87,14 @@ lowlevel_init:
 1:
        /* for UART */
        bl uart_asm_init
+       bl arch_cpu_init
        bl tzpc_init
        pop     {pc}
 
 wakeup_reset:
        bl system_clock_init
        bl mem_ctrl_asm_init
+       bl arch_cpu_init
        bl tzpc_init
 
 exit_wakeup:
@@ -353,45 +355,3 @@ uart_asm_init:
        nop
        nop
 
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
-       ldr     r0, =TZPC0_BASE
-       mov     r1, #R0SIZE
-       str     r1, [r0]
-       mov     r1, #DECPROTXSET
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC1_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC2_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC3_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC4_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC5_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       mov     pc, lr
index 930b948..926a4cc 100644 (file)
 #define UBRDIV_OFFSET          0x28
 #define UFRACVAL_OFFSET                0x2C
 
-/* TZPC : Register Offsets */
-#define TZPC0_BASE             0x10110000
-#define TZPC1_BASE             0x10120000
-#define TZPC2_BASE             0x10130000
-#define TZPC3_BASE             0x10140000
-#define TZPC4_BASE             0x10150000
-#define TZPC5_BASE             0x10160000
-
-#define TZPC_DECPROT0SET_OFFSET        0x804
-#define TZPC_DECPROT1SET_OFFSET        0x810
-#define TZPC_DECPROT2SET_OFFSET        0x81C
-#define TZPC_DECPROT3SET_OFFSET        0x828
-
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL           0x0
 #define MUX_HPM_SEL_SCLKMPLL           0x1
  * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
  */
 #define UFRACVAL_VAL           0x4
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE                 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET            0xFF
 #endif
index 47c6a5a..f2c32ee 100644 (file)
@@ -28,12 +28,15 @@ SOBJS       := lowlevel_init.o
 
 COBJS  := clock_init.o
 COBJS  += dmc_common.o dmc_init_ddr3.o
-COBJS  += tzpc_init.o
 COBJS  += smdk5250_spl.o
 
 ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_OF_CONTROL
+COBJS  += exynos5-dt.o
+else
 COBJS  += smdk5250.o
 endif
+endif
 
 ifdef CONFIG_SPL_BUILD
 COBJS  += spl_boot.o
index 5b9e82f..b288e66 100644 (file)
 #include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/spl.h>
+#include <asm/arch/dwmmc.h>
 
 #include "clock_init.h"
 #include "setup.h"
 
+#define FSYS1_MMC0_DIV_MASK    0xff0f
+#define FSYS1_MMC0_DIV_VAL     0x0701
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct arm_clk_ratios arm_clk_ratios[] = {
@@ -664,3 +668,17 @@ void clock_init_dp_clock(void)
        /* We run DP at 267 Mhz */
        setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
 }
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+       struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+       unsigned int div_mmc;
+
+       div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
+       div_mmc |= FSYS1_MMC0_DIV_VAL;
+       writel(div_mmc, (unsigned int) &clk->div_fsys1);
+}
index f751bcb..20a1d47 100644 (file)
@@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void);
  * Initialize clock for the device
  */
 void system_clock_init(void);
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ */
+void emmc_boot_clk_div_set(void);
 #endif
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
new file mode 100644 (file)
index 0000000..aacf43e
--- /dev/null
@@ -0,0 +1,468 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/sromc.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <tmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined CONFIG_EXYNOS_TMU
+/*
+ * Boot Time Thermal Analysis for SoC temperature threshold breach
+ */
+static void boot_temp_check(void)
+{
+       int temp;
+
+       switch (tmu_monitor(&temp)) {
+       /* Status TRIPPED ans WARNING means corresponding threshold breach */
+       case TMU_STATUS_TRIPPED:
+               puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+               set_ps_hold_ctrl();
+               hang();
+               break;
+       case TMU_STATUS_WARNING:
+               puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+               break;
+       /*
+        * TMU_STATUS_INIT means something is wrong with temperature sensing
+        * and TMU status was changed back from NORMAL to INIT.
+        */
+       case TMU_STATUS_INIT:
+       default:
+               debug("EXYNOS_TMU: Unknown TMU state\n");
+       }
+}
+#endif
+
+struct local_info {
+       struct cros_ec_dev *cros_ec_dev;        /* Pointer to cros_ec device */
+       int cros_ec_err;                        /* Error for cros_ec, 0 if ok */
+};
+
+static struct local_info local;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_vbus_init(void)
+{
+       struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+                                               samsung_get_base_gpio_part1();
+
+       /* Enable VBUS power switch */
+       s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+
+       /* VBUS turn ON time */
+       mdelay(3);
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_SOUND_MAX98095
+static void  board_enable_audio_codec(void)
+{
+       struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+                                               samsung_get_base_gpio_part1();
+
+       /* Enable MAX98095 Codec */
+       s5p_gpio_direction_output(&gpio1->x1, 7, 1);
+       s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+}
+#endif
+
+struct cros_ec_dev *board_get_cros_ec_dev(void)
+{
+       return local.cros_ec_dev;
+}
+
+static int board_init_cros_ec_devices(const void *blob)
+{
+       local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
+       if (local.cros_ec_err)
+               return -1;  /* Will report in board_late_init() */
+
+       return 0;
+}
+
+int board_init(void)
+{
+       gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+
+#if defined CONFIG_EXYNOS_TMU
+       if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+               debug("%s: Failed to init TMU\n", __func__);
+               return -1;
+       }
+       boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+       spi_init();
+#endif
+
+       if (board_init_cros_ec_devices(gd->fdt_blob))
+               return -1;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+       board_usb_vbus_init();
+#endif
+#ifdef CONFIG_SOUND_MAX98095
+       board_enable_audio_codec();
+#endif
+       return 0;
+}
+
+int dram_init(void)
+{
+       int i;
+       u32 addr;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+       }
+       return 0;
+}
+
+#if defined(CONFIG_POWER)
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+       u32 val;
+       int ret = 0;
+
+       ret = pmic_reg_read(p, reg, &val);
+       if (ret) {
+               debug("%s: PMIC %d register read failed\n", __func__, reg);
+               return -1;
+       }
+       val |= regval;
+       ret = pmic_reg_write(p, reg, val);
+       if (ret) {
+               debug("%s: PMIC %d register write failed\n", __func__, reg);
+               return -1;
+       }
+       return 0;
+}
+
+int power_init_board(void)
+{
+       struct pmic *p;
+
+       set_ps_hold_ctrl();
+
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+       if (pmic_init(I2C_PMIC))
+               return -1;
+
+       p = pmic_get("MAX77686_PMIC");
+       if (!p)
+               return -ENODEV;
+
+       if (pmic_probe(p))
+               return -1;
+
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+               return -1;
+
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+                           MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+               return -1;
+
+       /* VDD_MIF */
+       if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+                          MAX77686_BUCK1OUT_1V)) {
+               debug("%s: PMIC %d register write failed\n", __func__,
+                     MAX77686_REG_PMIC_BUCK1OUT);
+               return -1;
+       }
+
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+                           MAX77686_BUCK1CTRL_EN))
+               return -1;
+
+       /* VDD_ARM */
+       if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+                          MAX77686_BUCK2DVS1_1_3V)) {
+               debug("%s: PMIC %d register write failed\n", __func__,
+                     MAX77686_REG_PMIC_BUCK2DVS1);
+               return -1;
+       }
+
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+                           MAX77686_BUCK2CTRL_ON))
+               return -1;
+
+       /* VDD_INT */
+       if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+                          MAX77686_BUCK3DVS1_1_0125V)) {
+               debug("%s: PMIC %d register write failed\n", __func__,
+                     MAX77686_REG_PMIC_BUCK3DVS1);
+               return -1;
+       }
+
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+                           MAX77686_BUCK3CTRL_ON))
+               return -1;
+
+       /* VDD_G3D */
+       if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+                          MAX77686_BUCK4DVS1_1_2V)) {
+               debug("%s: PMIC %d register write failed\n", __func__,
+                     MAX77686_REG_PMIC_BUCK4DVS1);
+               return -1;
+       }
+
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+                           MAX77686_BUCK3CTRL_ON))
+               return -1;
+
+       /* VDD_LDO2 */
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+                           MAX77686_LD02CTRL1_1_5V | EN_LDO))
+               return -1;
+
+       /* VDD_LDO3 */
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+                           MAX77686_LD03CTRL1_1_8V | EN_LDO))
+               return -1;
+
+       /* VDD_LDO5 */
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+                           MAX77686_LD05CTRL1_1_8V | EN_LDO))
+               return -1;
+
+       /* VDD_LDO10 */
+       if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+                           MAX77686_LD10CTRL1_1_8V | EN_LDO))
+               return -1;
+
+       return 0;
+}
+#endif
+
+void dram_init_banksize(void)
+{
+       int i;
+       u32 addr, size;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+               gd->bd->bi_dram[i].start = addr;
+               gd->bd->bi_dram[i].size = size;
+       }
+}
+
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+       int err;
+       int node;
+
+       node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+       if (node < 0) {
+               debug("Could not find SROMC node\n");
+               return node;
+       }
+
+       config->bank = fdtdec_get_int(blob, node, "bank", 0);
+       config->width = fdtdec_get_int(blob, node, "width", 2);
+
+       err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+                       FDT_SROM_TIMING_COUNT);
+       if (err < 0) {
+               debug("Could not decode SROMC configuration Error: %s\n",
+                     fdt_strerror(err));
+               return -FDT_ERR_NOTFOUND;
+       }
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+       u32 smc_bw_conf, smc_bc_conf;
+       struct fdt_sromc config;
+       fdt_addr_t base_addr;
+       int node;
+
+       node = decode_sromc(gd->fdt_blob, &config);
+       if (node < 0) {
+               debug("%s: Could not find sromc configuration\n", __func__);
+               return 0;
+       }
+       node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+       if (node < 0) {
+               debug("%s: Could not find lan9215 configuration\n", __func__);
+               return 0;
+       }
+
+       /* We now have a node, so any problems from now on are errors */
+       base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+       if (base_addr == FDT_ADDR_T_NONE) {
+               debug("%s: Could not find lan9215 address\n", __func__);
+               return -1;
+       }
+
+       /* Ethernet needs data bus width of 16 bits */
+       if (config.width != 2) {
+               debug("%s: Unsupported bus width %d\n", __func__,
+                     config.width);
+               return -1;
+       }
+       smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+                       | SROMC_BYTE_ENABLE(config.bank);
+
+       smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
+                       SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+                       SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+                       SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+                       SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
+                       SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+                       SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+       /* Select and configure the SROMC bank */
+       exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+       s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+       return smc911x_initialize(0, base_addr);
+#endif
+       return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+       const char *board_name;
+
+       board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+       if (board_name == NULL)
+               printf("\nUnknown Board\n");
+       else
+               printf("\nBoard: %s\n", board_name);
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+       int ret;
+       /* dwmmc initializattion for available channels */
+       ret = exynos_dwmmc_init(gd->fdt_blob);
+       if (ret)
+               debug("dwmmc init failed\n");
+
+       return ret;
+}
+#endif
+
+static int board_uart_init(void)
+{
+       int err, uart_id, ret = 0;
+
+       for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+               err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+               if (err) {
+                       debug("UART%d not configured\n",
+                             (uart_id - PERIPH_ID_UART0));
+                       ret |= err;
+               }
+       }
+       return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+       int err;
+       err = board_uart_init();
+       if (err) {
+               debug("UART init failed\n");
+               return err;
+       }
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+       board_i2c_init(gd->fdt_blob);
+#endif
+       return err;
+}
+#endif
+
+#ifdef CONFIG_LCD
+void exynos_cfg_lcd_gpio(void)
+{
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+       /* For Backlight */
+       s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+       s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+       /* LCD power on */
+       s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+       s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+       /* Set Hotplug detect for DP */
+       s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+void exynos_set_dp_phy(unsigned int onoff)
+{
+       set_dp_phy_ctrl(onoff);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+       stdio_print_current_devices();
+
+       if (local.cros_ec_err) {
+               /* Force console on */
+               gd->flags &= ~GD_FLG_SILENT;
+
+               printf("cros-ec communications failure %d\n",
+                      local.cros_ec_err);
+               puts("\nPlease reset with Power+Refresh\n\n");
+               panic("Cannot init cros-ec device");
+               return -1;
+       }
+       return 0;
+}
+#endif
index bc6cb6f..edc565e 100644 (file)
@@ -75,12 +75,14 @@ lowlevel_init:
        bl      mem_ctrl_init
 
 1:
+       bl      arch_cpu_init
        bl      tzpc_init
        ldmia   r13!, {ip,pc}
 
 wakeup_reset:
        bl      system_clock_init
        bl      mem_ctrl_init
+       bl      arch_cpu_init
        bl      tzpc_init
 
 exit_wakeup:
index 34d8bc3..eb91d13 100644 (file)
 #include <config.h>
 #include <asm/arch/dmc.h>
 
-/* TZPC : Register Offsets */
-#define TZPC0_BASE             0x10100000
-#define TZPC1_BASE             0x10110000
-#define TZPC2_BASE             0x10120000
-#define TZPC3_BASE             0x10130000
-#define TZPC4_BASE             0x10140000
-#define TZPC5_BASE             0x10150000
-#define TZPC6_BASE             0x10160000
-#define TZPC7_BASE             0x10170000
-#define TZPC8_BASE             0x10180000
-#define TZPC9_BASE             0x10190000
-
 /* APLL_CON1   */
 #define APLL_CON1_VAL  (0x00203800)
 
 /* CLK_GATE_IP_DISP1 */
 #define CLK_GATE_DP1_ALLOW     (1 << 4)
 
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE                 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET            0xFF
-
 #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
 #define DDR3PHY_CTRL_PHY_RESET_OFF     (0 << 0)
 
@@ -590,5 +566,4 @@ void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
 void sdelay(unsigned long);
 void mem_ctrl_init(void);
 void system_clock_init(void);
-void tzpc_init(void);
 #endif
index 8b09e1d..276fd41 100644 (file)
@@ -29,6 +29,7 @@
 #include <netdev.h>
 #include <spi.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/dp_info.h>
 #include <power/pmic.h>
 #include <power/max77686_pmic.h>
-#include <tmu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined CONFIG_EXYNOS_TMU
-/*
- * Boot Time Thermal Analysis for SoC temperature threshold breach
- */
-static void boot_temp_check(void)
-{
-       int temp;
-
-       switch (tmu_monitor(&temp)) {
-       /* Status TRIPPED ans WARNING means corresponding threshold breach */
-       case TMU_STATUS_TRIPPED:
-               puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
-               set_ps_hold_ctrl();
-               hang();
-               break;
-       case TMU_STATUS_WARNING:
-               puts("EXYNOS_TMU: WARNING! Temperature very high\n");
-               break;
-       /*
-        * TMU_STATUS_INIT means something is wrong with temperature sensing
-        * and TMU status was changed back from NORMAL to INIT.
-        */
-       case TMU_STATUS_INIT:
-       default:
-               debug("EXYNOS_TMU: Unknown TMU state\n");
-       }
-}
-#endif
-
 #ifdef CONFIG_USB_EHCI_EXYNOS
 int board_usb_vbus_init(void)
 {
@@ -102,14 +73,6 @@ int board_init(void)
 {
        gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 
-#if defined CONFIG_EXYNOS_TMU
-       if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
-               debug("%s: Failed to init TMU\n", __func__);
-               return -1;
-       }
-       boot_temp_check();
-#endif
-
 #ifdef CONFIG_EXYNOS_SPI
        spi_init();
 #endif
@@ -124,14 +87,13 @@ int board_init(void)
 
 int dram_init(void)
 {
-       gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+       int i;
+       u32 addr;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+       }
        return 0;
 }
 
@@ -254,57 +216,15 @@ int power_init_board(void)
 
 void dram_init_banksize(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
-                                                       PHYS_SDRAM_1_SIZE);
-       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-       gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
-                                                       PHYS_SDRAM_2_SIZE);
-       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-       gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
-                                                       PHYS_SDRAM_3_SIZE);
-       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-       gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
-                                                       PHYS_SDRAM_4_SIZE);
-       gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
-       gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
-                                                       PHYS_SDRAM_5_SIZE);
-       gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
-       gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
-                                                       PHYS_SDRAM_6_SIZE);
-       gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
-       gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
-                                                       PHYS_SDRAM_7_SIZE);
-       gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
-       gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
-                                                       PHYS_SDRAM_8_SIZE);
-}
-
-#ifdef CONFIG_OF_CONTROL
-static int decode_sromc(const void *blob, struct fdt_sromc *config)
-{
-       int err;
-       int node;
-
-       node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
-       if (node < 0) {
-               debug("Could not find SROMC node\n");
-               return node;
-       }
-
-       config->bank = fdtdec_get_int(blob, node, "bank", 0);
-       config->width = fdtdec_get_int(blob, node, "width", 2);
-
-       err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
-                       FDT_SROM_TIMING_COUNT);
-       if (err < 0) {
-               debug("Could not decode SROMC configuration\n");
-               return -FDT_ERR_NOTFOUND;
+       int i;
+       u32 addr, size;
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+               gd->bd->bi_dram[i].start = addr;
+               gd->bd->bi_dram[i].size = size;
        }
-
-       return 0;
 }
-#endif
 
 int board_eth_init(bd_t *bis)
 {
@@ -313,27 +233,6 @@ int board_eth_init(bd_t *bis)
        struct fdt_sromc config;
        fdt_addr_t base_addr;
 
-#ifdef CONFIG_OF_CONTROL
-       int node;
-
-       node = decode_sromc(gd->fdt_blob, &config);
-       if (node < 0) {
-               debug("%s: Could not find sromc configuration\n", __func__);
-               return 0;
-       }
-       node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
-       if (node < 0) {
-               debug("%s: Could not find lan9215 configuration\n", __func__);
-               return 0;
-       }
-
-       /* We now have a node, so any problems from now on are errors */
-       base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
-       if (base_addr == FDT_ADDR_T_NONE) {
-               debug("%s: Could not find lan9215 address\n", __func__);
-               return -1;
-       }
-#else
        /* Non-FDT configuration - bank number and timing parameters*/
        config.bank = CONFIG_ENV_SROM_BANK;
        config.width = 2;
@@ -346,7 +245,6 @@ int board_eth_init(bd_t *bis)
        config.timing[FDT_SROM_TACP] = 0x09;
        config.timing[FDT_SROM_PMC] = 0x01;
        base_addr = CONFIG_SMC911X_BASE;
-#endif
 
        /* Ethernet needs data bus width of 16 bits */
        if (config.width != 2) {
@@ -376,17 +274,7 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_DISPLAY_BOARDINFO
 int checkboard(void)
 {
-#ifdef CONFIG_OF_CONTROL
-       const char *board_name;
-
-       board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
-       if (board_name == NULL)
-               printf("\nUnknown Board\n");
-       else
-               printf("\nBoard: %s\n", board_name);
-#else
        printf("\nBoard: SMDK5250\n");
-#endif
        return 0;
 }
 #endif
@@ -394,48 +282,54 @@ int checkboard(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-       int err;
+       int err, ret = 0, index, bus_width;
+       u32 base;
 
        err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-       if (err) {
+       if (err)
                debug("SDMMC0 not configured\n");
-               return err;
-       }
-
-       err = s5p_mmc_init(0, 8);
-       return err;
+       ret |= err;
+
+       /*EMMC: dwmmc Channel-0 with 8 bit bus width */
+       index = 0;
+       base =  samsung_get_base_mmc() + (0x10000 * index);
+       bus_width = 8;
+       err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+       if (err)
+               debug("dwmmc Channel-0 init failed\n");
+       ret |= err;
+
+       err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+       if (err)
+               debug("SDMMC2 not configured\n");
+       ret |= err;
+
+       /*SD: dwmmc Channel-2 with 4 bit bus width */
+       index = 2;
+       base = samsung_get_base_mmc() + (0x10000 * index);
+       bus_width = 4;
+       err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+       if (err)
+               debug("dwmmc Channel-2 init failed\n");
+       ret |= err;
+
+       return ret;
 }
 #endif
 
 static int board_uart_init(void)
 {
-       int err;
-
-       err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
-       if (err) {
-               debug("UART0 not configured\n");
-               return err;
+       int err, uart_id, ret = 0;
+
+       for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+           &nb