ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
authorAlexander Stein <alexanders83@web.de>
Fri, 24 Jul 2015 07:22:11 +0000 (09:22 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:25:46 +0000 (08:25 +0200)
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
include/configs/rpi.h
include/configs/rpi_2.h

index ab2f4db..86422e3 100644 (file)
@@ -7,6 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE              32
+
 #include "rpi-common.h"
 
 #endif
index 2e7e74f..13dc8de 100644 (file)
@@ -9,6 +9,7 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
+#define CONFIG_SYS_CACHELINE_SIZE              64
 
 #include "rpi-common.h"