arm: socfpga: Fix ArriaV SoCDK PLL config
authorMarek Vasut <marex@denx.de>
Wed, 19 Aug 2015 05:46:49 +0000 (07:46 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 08:32:52 +0000 (10:32 +0200)
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
board/altera/arria5-socdk/qts/pll_config.h

index 3d621ed..f6c5c95 100644 (file)
 #define CONFIG_HPS_DBCTRL_STAYOSC1 1
 
 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
 #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
 #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
 #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
 #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
@@ -46,7 +46,7 @@
 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
 
 #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
 #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
 #define CONFIG_HPS_CLK_OSC2_HZ 25000000
 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
 #define CONFIG_HPS_CLK_EMAC1_HZ 250000000
 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
 #define CONFIG_HPS_CLK_NAND_HZ 50000000
 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_QSPI_HZ 350000000
 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
 #define CONFIG_HPS_CLK_CAN0_HZ 100000000
 #define CONFIG_HPS_CLK_CAN1_HZ 100000000
@@ -77,8 +77,8 @@
 #define CONFIG_HPS_CLK_L4_MP_HZ 100000000
 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
 #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3