VERSION = 2014
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
AWK = awk
-RANLIB = $(CROSS_COMPILE)RANLIB
+PERL = perl
DTC = dtc
CHECK = sparse
export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
-export MAKE AWK
+export MAKE AWK PERL
export DTC CHECK CHECKFLAGS
export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
# If there is no specified link script, we look in a number of places for it
ifndef LDSCRIPT
- ifeq ($(CONFIG_NAND_U_BOOT),y)
- LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
- ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
- endif
- endif
ifeq ($(wildcard $(LDSCRIPT)),)
LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
endif
# Always append ALL so that arch config.mk's can add custom ones
ALL-y += u-boot.srec u-boot.bin System.map
-ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
u-boot.lds: $(LDSCRIPT) prepare FORCE
$(call if_changed_dep,cpp_lds)
-PHONY += nand_spl
-nand_spl: prepare
- $(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
- @echo >&2
- @echo >&2 "==================== WARNING ====================="
- @echo >&2 "nand_spl will not be included in v2014.07 release."
- @echo >&2 "Please switch over to SPL."
- @echo >&2 "Otherwise, this board will be removed."
- @echo >&2 "=================================================="
- @echo >&2
-
-nand_spl/u-boot-spl-16k.bin: nand_spl
- @:
-
-u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE
- $(call if_changed,cat)
-
spl/u-boot-spl.bin: spl/u-boot-spl
@:
spl/u-boot-spl: tools prepare
CLOBBER_DIRS += $(patsubst %,spl/%, $(filter-out Makefile, \
$(shell ls -1 spl 2>/dev/null))) \
tpl
-CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
+CLOBBER_FILES += u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated \
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name '*.gcno' \) -type f -print | xargs rm -f
- @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
- -path './nand_spl/*' -type l -print | xargs rm -f
# clobber
#
the LCD display every second with
a "rotator" |\-/|\-/
-- Board flavour: (if CONFIG_MPC8260ADS is defined)
- CONFIG_ADSTYPE
- Possible values are:
- CONFIG_SYS_8260ADS - original MPC8260ADS
- CONFIG_SYS_8266ADS - MPC8266ADS
- CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
- CONFIG_SYS_8272ADS - MPC8272ADS
-
- Marvell Family Member
CONFIG_SYS_MVFS - define it if you want to enable
multiple fs option at one time
filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
and cbfsload.
+- FAT(File Allocation Table) filesystem cluster size:
+ CONFIG_FS_FAT_MAX_CLUSTSIZE
+
+ Define the max cluster size for fat operations else
+ a default value of 65536 will be defined.
+
- Keyboard Support:
CONFIG_ISA_KEYBOARD
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
+- legacy image format:
+ CONFIG_IMAGE_FORMAT_LEGACY
+ enables the legacy image format support in U-Boot.
+
+ Default:
+ enabled if CONFIG_FIT_SIGNATURE is not defined.
+
+ CONFIG_DISABLE_IMAGE_LEGACY
+ disable the legacy image format
+
+ This define is introduced, as the legacy image format is
+ enabled per default for backward compatibility.
+
- FIT image support:
CONFIG_FIT
Enable support for the FIT uImage format.
using a hash signed and verified using RSA. See
doc/uImage.FIT/signature.txt for more details.
+ WARNING: When relying on signed FIT images with required
+ signature check the legacy image format is default
+ disabled. If a board need legacy image format support
+ enable this through CONFIG_IMAGE_FORMAT_LEGACY
+
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_LMB
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * In the case of non-SPL based booting we'll want to call these
+ * functions a tiny bit later as it will require gd to be set and cleared
+ * and that's not true in s_init in this case so we cannot do it there.
+ */
+int board_early_init_f(void)
+{
+ prcm_init();
+ set_mux_conf_regs();
+
+ return 0;
+}
+
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
-#ifdef CONFIG_NOR_BOOT
+#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
gd = &gdata;
preloader_console_init();
#endif
- prcm_init();
- set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
+#ifdef CONFIG_SPL_BUILD
+ board_early_init_f();
sdram_init();
+#endif
}
#endif
};
}
+/*
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first. This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
+ */
+__weak void scale_vcores(void)
+{
+}
+
void prcm_init()
{
enable_basic_clocks();
+ scale_vcores();
setup_dplls();
}
void setup_clocks_for_console(void)
{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+ clkctrl = readl(&cmwkup->wkup_uart0ctrl);
+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ }
}
void enable_basic_clocks(void)
int dram_init(void)
{
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ sdram_init();
+#endif
+
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int addr;
+ unsigned int addr, clear_bit, set_bit;
/*
* CLK_DIV_FSYS1
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
* CLK_DIV_FSYS3
- * MMC4_PRE_RATIO [15:8]
+ * MMC4_RATIO [3:0]
*/
if (dev_index < 2) {
addr = (unsigned int)&clk->div_fsys1;
- } else if (dev_index == 4) {
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
+ } else if (dev_index == 4) {
addr = (unsigned int)&clk->div_fsys3;
dev_index -= 4;
+ /* MMC4 is controlled with the MMC4_RATIO value */
+ clear_bit = MASK_RATIO(dev_index);
+ set_bit = SET_RATIO(dev_index, div);
} else {
addr = (unsigned int)&clk->div_fsys2;
dev_index -= 2;
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
}
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
- * CLK_DIV_FSYS2
- * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
- */
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
+ clrsetbits_le32(addr, clear_bit, set_bit);
}
/* exynos5: set the mmc clock */
else
exynos5_set_mmc_clk(dev_index, div);
} else {
- if (proid_is_exynos4412())
- exynos4x12_set_mmc_clk(dev_index, div);
- else
- exynos4_set_mmc_clk(dev_index, div);
+ exynos4_set_mmc_clk(dev_index, div);
}
}
DO_CLOCKS = 1 << 1,
DO_MEM_RESET = 1 << 2,
DO_UART = 1 << 3,
+ DO_POWER = 1 << 4,
};
int do_lowlevel_init(void)
arch_cpu_init();
+ set_ps_hold_ctrl();
+
reset_status = get_reset_status();
switch (reset_status) {
break;
default:
/* This is a normal boot (not a wake from sleep) */
- actions = DO_CLOCKS | DO_MEM_RESET;
+ actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
}
+ if (actions & DO_POWER)
+ set_ps_hold_ctrl();
+
if (actions & DO_CLOCKS) {
system_clock_init();
mem_ctrl_init(actions & DO_MEM_RESET);
static int exynos4_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4_GPIO_K20;
start_ext = EXYNOS4_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
+ /* SDMMC2 do not use 8bit mode at exynos4 */
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
static int exynos4x12_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4X12_GPIO_K00;
start_ext = EXYNOS4X12_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4X12_GPIO_K20;
start_ext = EXYNOS4X12_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4x12_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
}
+/*
+ * Set ps_hold data driving value high
+ * This enables the machine to stay powered on
+ * after the initial power-on condition goes away
+ * (e.g. power button).
+ */
void set_ps_hold_ctrl(void)
{
if (cpu_is_exynos5())
*/
#include <common.h>
+#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
share_all_segments(11); /* PCIE */
#endif
+ /*
+ * just initialise the COM2 port so that TI specific
+ * UART register PWREMU_MGMT is initialized. Linux UART
+ * driver doesn't handle this.
+ */
+ NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
return 0;
}
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
-#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
- SMNAND_GPMC_CONFIG1,
- SMNAND_GPMC_CONFIG2,
- SMNAND_GPMC_CONFIG3,
- SMNAND_GPMC_CONFIG4,
- SMNAND_GPMC_CONFIG5,
- SMNAND_GPMC_CONFIG6,
- 0,
-};
-#else
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
-#endif
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)
interrupts = <0 78 0>;
};
+ dwmmc@12550000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-dwmmc";
+ reg = <0x12550000 0x1000>;
+ interrupts = <0 131 0>;
+ };
+
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
console = "/serial@13820000";
mmc0 = "sdhci@12510000";
mmc2 = "sdhci@12530000";
+ mmc4 = "dwmmc@12550000";
};
i2c@138d0000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0xB2 0>;
+ status = "disabled";
};
sdhci@12520000 {
sdhci@12540000 {
status = "disabled";
};
+
+ dwmmc@12550000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <2 1 0>;
+ pwr-gpios = <&gpio 0xB2 0>;
+ fifoth_val = <0x203f0040>;
+ bus_hz = <400000000>;
+ div = <0x3>;
+ index = <4>;
+ };
};
mmc@12200000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
};
mmc@12210000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x12210000 0x1000>;
interrupts = <0 76 0>;
};
mmc@12220000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x12220000 0x1000>;
interrupts = <0 77 0>;
};
mmc@12230000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x12230000 0x1000>;
interrupts = <0 78 0>;
};
reg = <0x1e>;
compatible = "google,cros-ec";
i2c-max-frequency = <100000>;
- ec-interrupt = <&gpio 782 1>;
+ ec-interrupt = <&gpio 182 1>;
};
power-regulator@48 {
reg = <0>;
compatible = "google,cros-ec";
spi-max-frequency = <5000000>;
- ec-interrupt = <&gpio 782 1>;
+ ec-interrupt = <&gpio 182 1>;
optimise-flash-write;
status = "disabled";
};
reg = <0x22>;
compatible = "maxim,max98095-codec";
};
+
+ ptn3460-bridge@20 {
+ compatible = "nxp,ptn3460";
+ reg = <0x20>;
+ /*
+ * TODO(sjg@chromium.org): Use GPIOs here
+ * powerdown-gpio = <&gpy2 5 0>;
+ * reset-gpio = <&gpx1 5 0>;
+ * edid-emulation = <5>;
+ * pinctrl-names = "default";
+ * pinctrl-0 = <&ptn3460_gpios>;
+ */
+ };
};
i2c@12c60000 {
/* UP LEFT */
0x070b0067 0x070c0069>;
};
+
+ fimd@14400000 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1366>;
+ samsung,vl-row = <768>;
+ samsung,vl-width = <1366>;
+ samsung,vl-height = <768>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-hsp;
+ samsung,vl-vsp;
+
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <80>;
+ samsung,vl-hfpd = <48>;
+ samsung,vl-vspw = <5>;
+ samsung,vl-vbpd = <14>;
+ samsung,vl-vfpd = <3>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <0>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
+
+ dp@145b0000 {
+ samsung,lt-status = <0>;
+
+ samsung,master-mode = <0>;
+ samsung,bist-mode = <0>;
+ samsung,bist-pattern = <0>;
+ samsung,h-sync-polarity = <0>;
+ samsung,v-sync-polarity = <0>;
+ samsung,interlaced = <0>;
+ samsung,color-space = <0>;
+ samsung,dynamic-range = <0>;
+ samsung,ycbcr-coeff = <0>;
+ samsung,color-depth = <1>;
+ };
+
};
sdhci1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
- usb0 = "/usb@7d008000";
+ usb0 = "/usb@7d000000";
+ usb1 = "/usb@7d008000";
};
memory {
bus-width = <8>;
};
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
+ };
+
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
sdhci1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
- usb0 = "/usb@7d008000";
+ usb0 = "/usb@7d000000";
+ usb1 = "/usb@7d008000";
};
memory {
bus-width = <8>;
};
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
+ };
+
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000000";
- usb0 = "/usb@7d008000";
+ usb0 = "/usb@7d000000";
+ usb1 = "/usb@7d008000";
};
memory {
bus-width = <8>;
};
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,vbus-gpio = <&gpio 238 0>; /* gpio DD6, PEX_L1_CLKREQ */
+ };
+
usb@7d008000 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
status = "okay";
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE)
const struct dpll_params *get_dpll_core_params(void);
const struct dpll_params *get_dpll_per_params(void);
const struct dpll_params *get_dpll_ddr_params(void);
+void scale_vcores(void);
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
void prcm_init(void);
void enable_basic_clocks(void);
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
-
+#define TCLR_CE BIT(6) /* compare mode enable */
+#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
+#define TCLR_TCM BIT(8) /* edge detection of input pin*/
+#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
+#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
+#define TCLR_CAPTMODE BIT(13) /* capture mode */
+#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
+
+#define TCFG_RESET BIT(0) /* software reset */
+#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
+#define TCFG_IDLEMOD_SHIFT (2) /* power management */
/* device type */
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
unsigned int wkctrlclkctrl; /* offset 0x04 */
unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
- unsigned int resv2[4];
+ unsigned int timer0clkctrl; /* offset 0x10 */
+ unsigned int resv2[3];
unsigned int idlestdpllmpu; /* offset 0x20 */
unsigned int resv3[2];
unsigned int clkseldpllmpu; /* offset 0x2c */
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
unsigned int wkup_adctscctrl; /* offset 0xBC */
- unsigned int resv12[6];
+ unsigned int resv12;
+ unsigned int timer1clkctrl; /* offset 0xC4 */
+ unsigned int resv13[4];
unsigned int divm6dpllcore; /* offset 0xD8 */
};
unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
- unsigned int resv8[4];
+ unsigned int resv8[2];
+ unsigned int timer5clkctrl; /* offset 0xEC */
+ unsigned int timer6clkctrl; /* offset 0xF0 */
unsigned int mmc1clkctrl; /* offset 0xF4 */
unsigned int mmc2clkctrl; /* offset 0xF8 */
unsigned int resv9[8];
/* Encapsulating Display pll registers */
struct cm_dpll {
- unsigned int resv1[2];
+ unsigned int resv1;
+ unsigned int clktimer7clk; /* offset 0x04 */
unsigned int clktimer2clk; /* offset 0x08 */
- unsigned int resv2[10];
+ unsigned int clktimer3clk; /* offset 0x0C */
+ unsigned int clktimer4clk; /* offset 0x10 */
+ unsigned int resv2;
+ unsigned int clktimer5clk; /* offset 0x18 */
+ unsigned int clktimer6clk; /* offset 0x1C */
+ unsigned int resv3[2];
+ unsigned int clktimer1clk; /* offset 0x28 */
+ unsigned int resv4[2];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
#else
#define BPLL 5
#define RPLL 6
+#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
+#define MASK_RATIO(x) (0xf << (x << 4))
+#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8))
+#define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
+
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
/* Read the resume function and call it */
void power_exit_wakeup(void);
+
#endif
#define K2HK_LPSC_ARM_SREFLEX 51
#define K2HK_LPSC_TETRIS 52
-#define K2HK_UART0_BASE 0x02530c00
-
/* DDR3A definitions */
#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
+#define KS2_UART0_BASE 0x02530c00
+#define KS2_UART1_BASE 0x02531000
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
#define GPMC_CS_ENABLE 0x1
-#define SMNAND_GPMC_CONFIG1 0x00000800
-#define SMNAND_GPMC_CONFIG2 0x00141400
-#define SMNAND_GPMC_CONFIG3 0x00141400
-#define SMNAND_GPMC_CONFIG4 0x0F010F01
-#define SMNAND_GPMC_CONFIG5 0x010C1414
-#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
-#define SMNAND_GPMC_CONFIG7 0x00000C44
-
#define M_NAND_GPMC_CONFIG1 0x00001800
#define M_NAND_GPMC_CONFIG2 0x00141400
#define M_NAND_GPMC_CONFIG3 0x00141400
gd->mon_len = (ulong)&__bss_end - (ulong)_start;
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
- gd->fdt_blob = __dtb_db_begin;
+ gd->fdt_blob = __dtb_dt_begin;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
gd->fdt_blob = &_end;
/*
* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* (C) Copyright 2011, Julius Baxter <julius@opencores.org>
+ * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
l.ori r3,r0,SPR_SR_SM
l.mtspr r0,r3,SPR_SR
+ l.jal _cur
+ l.nop
+_cur:
+ l.ori r8, r9, 0 /* Get _cur current address */
+
+ l.movhi r3, hi(_cur)
+ l.ori r3, r3, lo(_cur)
+ l.sfeq r8, r3 /* If we are running at the linked address */
+ l.bf _no_vector_reloc /* there is not need for relocation */
+ l.sub r8, r8, r3
+
+ l.mfspr r4, r0, SPR_CPUCFGR
+ l.andi r4, r4, SPR_CPUCFGR_EVBARP /* Exception Vector Base Address Register present ? */
+ l.sfnei r4,0
+ l.bnf _reloc_vectors
+ l.movhi r5, 0 /* Destination */
+
+ l.mfspr r4, r0, SPR_EVBAR
+ l.add r5, r5, r4
+
+_reloc_vectors:
+ /* Relocate vectors*/
+ l.movhi r5, 0 /* Destination */
+ l.movhi r6, hi(__start) /* Length */
+ l.ori r6, r6, lo(__start)
+ l.ori r3, r8, 0
+
+.L_relocvectors:
+ l.lwz r7, 0(r3)
+ l.sw 0(r5), r7
+ l.addi r5, r5, 4
+ l.sfeq r5, r6
+ l.bnf .L_relocvectors
+ l.addi r3, r3, 4
+
+_no_vector_reloc:
+
/* Relocate u-boot */
- l.movhi r3,hi(__start) /* source start address */
+ l.movhi r3,hi(__start) /* source start offset */
l.ori r3,r3,lo(__start)
+ l.add r3,r8,r3
+
l.movhi r4,hi(_stext) /* dest start address */
l.ori r4,r4,lo(_stext)
l.movhi r5,hi(__end) /* dest end address */
l.bf .L_reloc
l.addi r4,r4,4 /* delay slot */
-#ifdef CONFIG_SYS_RELOCATE_VECTORS
- /* Relocate vectors from 0xf0000000 to 0x00000000 */
- l.movhi r4, 0xf000 /* source */
- l.movhi r5, 0 /* destination */
- l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
-.L_relocvectors:
- l.lwz r7, 0(r4)
- l.sw 0(r5), r7
- l.addi r5, r5, 4
- l.sfeq r5,r6
- l.bnf .L_relocvectors
- l.addi r4,r4, 4
-#endif
l.movhi r4,hi(_start)
l.ori r4,r4,lo(_start)
l.jr r4
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_VR2 (SPRGROUP_SYS + 9)
+#define SPR_AVR (SPRGROUP_SYS + 10)
+#define SPR_EVBAR (SPRGROUP_SYS + 11)
+#define SPR_AECR (SPRGROUP_SYS + 12)
+#define SPR_AESR (SPRGROUP_SYS + 13)
#define SPR_NPC (SPRGROUP_SYS + 16)
#define SPR_SR (SPRGROUP_SYS + 17)
#define SPR_PPC (SPRGROUP_SYS + 18)
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
+#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */
+#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */
+#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
+#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
+#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */
+ /* Arithmetic Exception Status Register (AESR) presents */
+#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
/*
* Bit definitions for the Debug configuration register and other
immap->im_siu_conf.sc_siumcr =
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
-#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/* nothing to do for this board here */
#elif defined CONFIG_MPC8272
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
~SIUMCR_BBD &
.globl _start
_start:
-#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
- lis r3, CONFIG_SYS_DEFAULT_IMMR@h
- nop
- lwz r4, 0(r3)
- nop
- rlwinm r4, r4, 0, 8, 5
- nop
- oris r4, r4, 0x0200
- nop
- stw r4, 0(r3)
- nop
-#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
-
mfmsr r5 /* save msr contents */
#if defined(CONFIG_COGENT)
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG ETSEC129 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+ puts("Work-around for Erratum A004508 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts("Work-around for Erratum A004510 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ puts("Work-around for Erratum A007186 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
}
#endif
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+ int ret;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+ int tdm_hwconfig_enabled = 0;
+
+ /*
+ * Extract hwconfig from environment since environment
+ * is not setup properly yet. Search for tdm entry in
+ * hwconfig.
+ */
+ ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+ if (ret > 0) {
+ tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+ /* If tdm is defined in hwconfig, set law for tdm workaround */
+ if (tdm_hwconfig_enabled)
+ set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+ LAW_TRGT_IF_CCSR);
+ }
+}
+#endif
+
static void enable_cpc(void)
{
int i;
disable_cpc_sram();
#endif
enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ enable_tdm_law();
+#endif
#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
#include <linux/ctype.h>
#include <asm/io.h>
#include <asm/fsl_portals.h>
+#include <hwconfig.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ int ret;
+ int tdm_hwconfig_enabled = 0;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
"device_type", "cpu", 4);
}
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define CONFIG_MEM_HOLE_16M 0x1000000
+ /*
+ * Extract hwconfig from environment.
+ * Search for tdm entry in hwconfig.
+ */
+ ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+ if (ret > 0)
+ tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+ /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+ if (tdm_hwconfig_enabled) {
+ off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+ CONFIG_MEM_HOLE_16M);
+ if (off < 0)
+ printf("Failed to reserve memory for tdm: %s\n",
+ fdt_strerror(off));
+ }
+#endif
+
/* Reserve the boot page so OSes dont use it */
if ((u64)bootpg < memory_limit) {
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
return -ENODEV;
}
+#define BC3_SHIFT 9
+#define DC3_SHIFT 6
+#define FC3_SHIFT 0
+#define BC2_SHIFT 19
+#define DC2_SHIFT 16
+#define FC2_SHIFT 10
+#define BC1_SHIFT 29
+#define DC1_SHIFT 26
+#define FC1_SHIFT 20
+#define BC_MASK 0x1
+#define DC_MASK 0x7
+#define FC_MASK 0x3F
+
+#define FUSE_VAL_MASK 0x00000003
+#define FUSE_VAL_SHIFT 30
+#define CR0_DCBIAS_SHIFT 5
+#define CR1_FCAP_SHIFT 15
+#define CR1_BCAP_SHIFT 29
+#define FCAP_MASK 0x001F8000
+#define BCAP_MASK 0x20000000
+#define BCAP_OVD_MASK 0x10000000
+#define BYP_CAL_MASK 0x02000000
+
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ struct ccsr_sfp_regs __iomem *sfp_regs =
+ (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+ u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+ u32 bc_status, fc_status, dc_status, pll_sr2;
+ serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
+ u32 sfp_spfr0, sel;
+#endif
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
/* Is serdes enabled at all? */
return 0;
}
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+ debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+ sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+ if (sel == 0x01 || sel == 0x02) {
+ for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+ /* STEP 1 */
+ /* Read factory pre-set SerDes calibration values
+ * from fuse block(SFP scratch register-sfp_spfr0)
+ */
+ switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+ case SRDS_PLLCR0_FRATE_SEL_3_0:
+ case SRDS_PLLCR0_FRATE_SEL_3_072:
+ debug("A007186: 3.0/3.072 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_125:
+ debug("A007186: 3.125 protocol rate\n");
+ bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_75:
+ debug("A007186: 3.75 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ default:
+ continue;
+ }
+
+ /* STEP 2 */
+ /* Write SRDSxPLLnCR1[11:16] = FC
+ * Write SRDSxPLLnCR1[2] = BC
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+ ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+ /* Write SRDSxPLLnCR0[24:26] = DC
+ */
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+ debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+ pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+ /* Write SRDSxPLLnCR1[3] = 1
+ * Write SRDSxPLLnCR1[6] = 1
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+
+ /* STEP 3 */
+ /* Read the status Registers */
+ /* Verify SRDSxPLLnSR2[8] = BC */
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ debug("A007186: pll_num=%x pllsr2=%x\n",
+ pll_num, pll_sr2);
+ bc_status = (pll_sr2 >> 23) & BC_MASK;
+ if (bc_status != bc)
+ debug("BC mismatch\n");
+ fc_status = (pll_sr2 >> 16) & FC_MASK;
+ if (fc_status != fc)
+ debug("FC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+ 0x02000000);
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ dc_status = (pll_sr2 >> 17) & DC_MASK;
+ if (dc_status != dc)
+ debug("DC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+ 0xfdffffff);
+
+ /* STEP 4 */
+ /* Wait 750us to verify the PLL is locked
+ * by checking SRDSxPLLnCR0[8] = 1.
+ */
+ udelay(750);
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+
+ if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+ printf("A007186 Serdes PLL not locked\n");
+ else
+ debug("A007186 Serdes PLL locked\n");
+ }
+ }
+#endif
+
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
+ SET_TDM_LIODN(560),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM1_MAC1, XFI_FM1_MAC2,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, SGMII_FM1_DTSEC4,
{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#if defined(CONFIG_PPC_T2081)
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
PCIE4, PCIE4, PCIE4, PCIE4} },
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
{}
};
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+ {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, XFI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM2_MAC10, XFI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
};
static const struct serdes_config serdes3_cfg_tbl[] = {
/* SerDes 3 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+ {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+ {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+ {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2}},
+ {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2}},
+ {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
+ {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
+ {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+ {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+ {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+ {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+ {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+ {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+ {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
{}
};
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
+ {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
NONE, NONE} },
+ {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {55, {NONE, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, NONE,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{56, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
};
static const struct serdes_config serdes3_cfg_tbl[] = {
/* SerDes 3 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+ {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+ {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+ {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
+ {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
+ {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
+ {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
+ {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+ {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+ {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
{}
#if defined(SDR0_PINSTP_SHIFT)
printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
-#ifdef CONFIG_NAND_U_BOOT
- puts(", booting from NAND");
-#endif /* CONFIG_NAND_U_BOOT */
putc('\n');
#endif /* SDR0_PINSTP_SHIFT */
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8540)
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8572)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1010)
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1012 is single core version of P1021 */
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1013 is single core version of P1022 */
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1014)
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_A004508
/* P1017 is single core version of P1023 */
#elif defined(CONFIG_P1017)
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1020)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1023)
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P2010 is single core version of P2020 */
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P2020)
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_PPC_C29X)
LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
+ LAW_TRGT_IF_CCSR = 0x1e,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
CONFIG_SYS_MPC85xx_QE_OFFSET)
+#define SET_TDM_LIODN(liodn) \
+ SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+ CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
u32 sata2liodnr; /* SATA 2 LIODN */
u32 sata3liodnr; /* SATA 3 LIODN */
u32 sata4liodnr; /* SATA 4 LIODN */
- u8 res22[24];
+ u8 res22[20];
+ u32 tdmliodnr; /* TDM LIODN */
u32 qeliodnr; /* QE LIODN */
u8 res_57c[4];
u32 dma1liodnr; /* DMA 1 LIODN */
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_PLL_LCK 0x00800000
#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
-#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
-#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
u32 pllcr1; /* PLL Control Register 1 */
u8 res_f4[0xf0c];
};
#endif
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 reserved0[14];
+ u32 srk_hash[8]; /* 0x23c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved2[0x04];
+ u32 ovpr; /* 0xA4 Intent To Secure */
+ u8 reserved4[0x08];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+ u8 reserved5[0x04];
+ u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
+ u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
+};
+#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ * * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET 0x200
+#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET 0xE8000
+#endif
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
#define CONFIG_SYS_PCIE4_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+#define CONFIG_SYS_SFP_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
#if defined(CONFIG_8xx)
#define _machine _MACH_8xx
#define have_of 0
-#elif defined(CONFIG_OAK)
-#define _machine _MACH_oak
-#define have_of 0
#elif defined(CONFIG_WALNUT)
#define _machine _MACH_walnut
#define have_of 0
-#elif defined(CONFIG_APUS)
-#define _machine _MACH_apus
-#define have_of 0
-#elif defined(CONFIG_GEMINI)
-#define _machine _MACH_gemini
-#define have_of 0
#elif defined(CONFIG_MPC8260)
#define _machine _MACH_8260
#define have_of 0
#elif defined(CONFIG_SANDPOINT)
#define _machine _MACH_sandpoint
-#elif defined(CONFIG_HIDDEN_DRAGON)
-#define _machine _MACH_hidden_dragon
-#define have_of 0
#else
#error "Machine not defined correctly"
#endif
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_NAND
gpmc_init();
+#endif
return 0;
}
};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
+
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
{OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
+ /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
*/
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
+ /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO0_20 (DMA_INTR1) - REP-Switch */
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := adder.o
+++ /dev/null
-/*
- * Copyright (C) 2004-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Adder boards family.
- * Tested on AdderII and Adder87x.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#if defined(CONFIG_OF_LIBFDT)
- #include <libfdt.h>
-#endif
-
-/*
- * SDRAM is single Samsung K4S643232F-T70 chip (8MB)
- * or single Micron MT48LC4M32B2TG-7 chip (16MB).
- * Minimal CPU frequency is 40MHz.
- */
-static uint sdram_table[] = {
- /* Single read (offset 0x00 in UPM RAM) */
- 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
- 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
-
- /* Burst read (offset 0x08 in UPM RAM) */
- 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
- 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
- 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
-
- /* Single write (offset 0x18 in UPM RAM) */
- 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
- 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* Burst write (offset 0x20 in UPM RAM) */
- 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* Refresh (offset 0x30 in UPM RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* Exception (offset 0x3C in UPM RAM) */
- 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
-};
-
-phys_size_t initdram (int board_type)
-{
- long int msize;
- volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
-
- /* Configure SDRAM refresh */
- memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
-
- memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
- udelay(200);
-
- /* Run precharge from location 0x15 */
- memctl->memc_mar = 0x0;
- memctl->memc_mcr = 0x80002115;
- udelay(200);
-
- /* Run 8 refresh cycles */
- memctl->memc_mcr = 0x80002830;
- udelay(200);
-
- /* Run MRS pattern from location 0x16 */
- memctl->memc_mar = 0x88;
- memctl->memc_mcr = 0x80002116;
- udelay(200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
- memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
-
- msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
- memctl->memc_or1 |= ~(msize - 1);
-
- return msize;
-}
-
-int checkboard( void )
-{
- puts("Board: Adder");
-#if defined(CONFIG_MPC885_FAMILY)
- puts("87x\n");
-#elif defined(CONFIG_MPC866_FAMILY)
- puts("II\n");
-#endif
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
-ENTRY(_start)
};
static u32 gpmc_nand_config[GPMC_MAX_REG] = {
- SMNAND_GPMC_CONFIG1,
- SMNAND_GPMC_CONFIG2,
- SMNAND_GPMC_CONFIG3,
- SMNAND_GPMC_CONFIG4,
- SMNAND_GPMC_CONFIG5,
- SMNAND_GPMC_CONFIG6,
+ M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6,
0,
};
$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
$(call cmd,awk)
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
-a 0 -e 0 -n bootscript
$(obj)/bootscript.image: $(src)/bootscript.hush
$(call cmd,mkimage)
-clean-files := bootscript.c bootscript.image
\ No newline at end of file
+clean-files := bootscript.c bootscript.image
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ep8248.o
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Embedded Planet EP8248 boards.
- * Tested on EP8248E.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */
- /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
- /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
- /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- }
-};
-
-int board_early_init_f (void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- bcsr[4] |= 0x30; /* Turn the LEDs off */
-
-#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
- bcsr[6] |= 0x10;
-#endif
-#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
- bcsr[7] |= 0x10;
-#endif
-
-#if CONFIG_SYS_FCC1
- bcsr[8] |= 0xC0;
-#endif /* CONFIG_SYS_FCC1 */
-#if CONFIG_SYS_FCC2
- bcsr[8] |= 0x30;
-#endif /* CONFIG_SYS_FCC2 */
-
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
- long int msize = 16L << (bcsr[2] & 3);
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
- uchar c = 0xFF;
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x02;
- immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* Initialise 60x bus SDRAM */
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
- *ramaddr = c;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
- /* Return total 60x bus SDRAM size */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- puts("Board: ");
- switch (bcsr[0]) {
- case 0x0C:
- printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
- break;
- default:
- printf("unknown: ID=%02X\n", bcsr[0]);
- }
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = debris.o flash.o phantom.o
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard (void)
-{
- /*TODO: Check processor type */
-
- puts ( "Board: Debris "
-#ifdef CONFIG_MPC8240
- "8240"
-#endif
-#ifdef CONFIG_MPC8245
- "8245"
-#endif
- " ##Test not implemented yet##\n");
- return 0;
-}
-
-#if 0 /* NOT USED */
-int checkflash (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("## Test not implemented yet ##\n");
-
- return (0);
-}
-#endif
-
-phys_size_t initdram (int board_type)
-{
- int m, row, col, bank, i;
- unsigned long start, end;
- uint32_t mccr1;
- uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
- uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
- uint8_t mber = 0;
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */
- m = i2c_reg_read (0x50, 5); /* # of physical banks */
- row = i2c_reg_read (0x50, 3); /* # of rows */
- col = i2c_reg_read (0x50, 4); /* # of columns */
- bank = i2c_reg_read (0x50, 17); /* # of logical banks */
-
- CONFIG_READ_WORD(MCCR1, mccr1);
- mccr1 &= 0xffff0000;
-
- start = CONFIG_SYS_SDRAM_BASE;
- end = start + (1 << (col + row + 3) ) * bank - 1;
-
- for (i = 0; i < m; i++) {
- mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
- if (i < 4) {
- msar1 |= ((start >> 20) & 0xff) << i * 8;
- emsar1 |= ((start >> 28) & 0xff) << i * 8;
- mear1 |= ((end >> 20) & 0xff) << i * 8;
- emear1 |= ((end >> 28) & 0xff) << i * 8;
- } else {
- msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
- emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
- mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
- emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
- }
- mber |= 1 << i;
- start += (1 << (col + row + 3) ) * bank;
- end += (1 << (col + row + 3) ) * bank;
- }
- for (; i < 8; i++) {
- if (i < 4) {
- msar1 |= 0xff << i * 8;
- emsar1 |= 0x30 << i * 8;
- mear1 |= 0xff << i * 8;
- emear1 |= 0x30 << i * 8;
- } else {
- msar2 |= 0xff << (i-4) * 8;
- emsar2 |= 0x30 << (i-4) * 8;
- mear2 |= 0xff << (i-4) * 8;
- emear2 |= 0x30 << (i-4) * 8;
- }
- }
-
- CONFIG_WRITE_WORD(MCCR1, mccr1);
- CONFIG_WRITE_WORD(MSAR1, msar1);
- CONFIG_WRITE_WORD(EMSAR1, emsar1);
- CONFIG_WRITE_WORD(MEAR1, mear1);
- CONFIG_WRITE_WORD(EMEAR1, emear1);
- CONFIG_WRITE_WORD(MSAR2, msar2);
- CONFIG_WRITE_WORD(EMSAR2, emsar2);
- CONFIG_WRITE_WORD(MEAR2, mear2);
- CONFIG_WRITE_WORD(EMEAR2, emear2);
- CONFIG_WRITE_BYTE(MBER, mber);
-
- return (1 << (col + row + 3) ) * bank * m;
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_debris_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_debris_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
- volatile uchar *d = (volatile uchar*) dest;
- volatile uchar *s = (volatile uchar*) src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
- return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
- volatile uchar *d = (volatile uchar*)dest;
- volatile uchar *s = (volatile uchar*)src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
-}
-
-int misc_init_r(void)
-{
- uchar ethaddr[6];
-
- if (eth_getenv_enetaddr("ethaddr", ethaddr))
- /* Write ethernet addr in NVRAM for VxWorks */
- nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
- ethaddr, 6);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * board/eva/flash.c
- *
- * (C) Copyright 2002
- * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <mpc824x.h>
-#include <asm/mmu.h>
-
-int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
-int (*write_dword)(flash_info_t*, ulong, uint64_t);
-
-typedef uint64_t cfi_word;
-
-#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
-
-#define cfi_write(flash, val, addr) \
- move64((cfi_word*)&val, \
- (cfi_word*)(flash->start[0] + addr))
-
-#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
-
-static void write32(unsigned long addr, uint32_t value)
-{
- *(volatile uint32_t*)(addr) = value;
- asm volatile("sync");
-}
-
-static uint32_t read32(unsigned long addr)
-{
- uint32_t value;
- value = *(volatile uint32_t*)addr;
- asm volatile("sync");
- return value;
-}
-
-static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
-{
- uint32_t base = flash->start[0];
- uint32_t val=(cmd << 16) | cmd;
- addr <<= 3;
- write32(base + addr, val);
- return addr;
-}
-
-static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
-{
- uint32_t base = flash->start[0];
- addr <<= 3;
- return (uint16_t)read32(base + addr);
-}
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static void move64(uint64_t *src, uint64_t *dest)
-{
- asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
- "stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0" ); /* Clobbers fr0 */
- return;
-}
-
-static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
-{
- unsigned long start;
- cfi_word status = 0;
-
- status = cfi_read(flash, dest);
- data &= status;
-
- cfi_cmd(flash, 0x40, 0);
- cfi_write(flash, data, dest);
-
- udelay(10);
- start = get_timer (0);
- for(;;) {
- status = cfi_read(flash, dest);
- status &= CMD(0x80);
- if(status == CMD(0x80))
- break;
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- cfi_cmd(flash, 0xff, 0);
- return 1;
- }
- udelay(1);
- }
- cfi_cmd(flash, 0xff, 0);
-
- return 0;
-}
-
-static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
-{
- ulong start;
- cfi_word status = 0;
-
- status = cfi_read(flash, dest);
- if(status != CMD(0xffff)) return 2;
-
- cfi_cmd(flash, 0xaa, 0x555);
- cfi_cmd(flash, 0x55, 0x2aa);
- cfi_cmd(flash, 0xa0, 0x555);
-
- cfi_write(flash, data, dest);
-
- udelay(10);
- start = get_timer (0);
- status = ~data;
- while(status != data) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return 1;
- status = cfi_read(flash, dest);
- udelay(1);
- }
- return 0;
-}
-
-static __inline__ unsigned long get_msr(void)
-{
- unsigned long msr;
- __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
- return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
- __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
-}
-
-int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
-{
- ulong wp;
- int i, s, l, rc;
- cfi_word data;
- uint8_t *t = (uint8_t*)&data;
- unsigned long base = flash->start[0];
- uint32_t msr;
-
- if (flash->flash_id == FLASH_UNKNOWN)
- return 4;
-
- if (cnt == 0)
- return 0;
-
- addr -= base;
-
- msr = get_msr();
- set_msr(msr|MSR_FP);
-
- wp = (addr & ~7); /* get lower word aligned address */
-
- if((addr-wp) != 0) {
- data = cfi_read(flash, wp);
- s = addr & 7;
- l = ( cnt < (8-s) ) ? cnt : (8-s);
- for(i = 0; i < l; i++)
- t[s+i] = *src++;
- if ((rc = write_dword(flash, wp, data)) != 0)
- goto DONE;
- wp += 8;
- cnt -= l;
- }
-
- while (cnt >= 8) {
- for (i = 0; i < 8; i++)
- t[i] = *src++;
- if ((rc = write_dword(flash, wp, data)) != 0)
- goto DONE;
- wp += 8;
- cnt -= 8;
- }
-
- if (cnt == 0) {
- rc = 0;
- goto DONE;
- }
-
- data = cfi_read(flash, wp);
- for(i = 0; i < cnt; i++)
- t[i] = *src++;
- rc = write_dword(flash, wp, data);
-DONE:
- set_msr(msr);
- return rc;
-}
-
-static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
-{
- int sa;
- int flag;
- ulong start, last, now;
- cfi_word status;
-
- flag = disable_interrupts();
-
- sa = (flash->start[sect] - flash->start[0]);
- write32(flash->start[sect], 0x00200020);
- write32(flash->start[sect], 0x00d000d0);
-
- if (flag)
- enable_interrupts();
-
- udelay(1000);
- start = get_timer (0);
- last = start;
-
- for (;;) {
- status = cfi_read(flash, sa);
- status &= CMD(0x80);
- if (status == CMD(0x80))
- break;
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- cfi_cmd(flash, 0xff, 0);
- printf ("Timeout\n");
- return ERR_TIMOUT;
- }
-
- if ((now - last) > 1000) {
- serial_putc ('.');
- last = now;
- }
- udelay(10);
- }
- cfi_cmd(flash, 0xff, 0);
- return ERR_OK;
-}
-
-static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
- int sect;
- int rc = ERR_OK;
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (flash->protect[sect] == 0) {
- rc = cfi_erase_oneblock(flash, sect);
- if (rc != ERR_OK) break;
- }
- }
- printf (" done\n");
- return rc;
-}
-
-static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
- int sect;
- cfi_word status;
- int sa = -1;
- int flag;
- ulong start, last, now;
-
- flag = disable_interrupts();
-
- cfi_cmd(flash, 0xaa, 0x555);
- cfi_cmd(flash, 0x55, 0x2aa);
- cfi_cmd(flash, 0x80, 0x555);
- cfi_cmd(flash, 0xaa, 0x555);
- cfi_cmd(flash, 0x55, 0x2aa);
- for ( sect = s_first; sect <= s_last; sect++) {
- if (flash->protect[sect] == 0) {
- sa = flash->start[sect] - flash->start[0];
- write32(flash->start[sect], 0x00300030);
- }
- }
- if (flag)
- enable_interrupts();
-
- if (sa < 0)
- goto DONE;
-
- udelay (1000);
- start = get_timer (0);
- last = start;
- for(;;) {
- status = cfi_read(flash, sa);
- if (status == CMD(0xffff))
- break;
-
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return ERR_TIMOUT;
- }
-
- if ((now - last) > 1000) {
- serial_putc ('.');
- last = now;
- }
- udelay(10);
- }
-DONE:
- cfi_cmd(flash, 0xf0, 0);
-
- printf (" done\n");
-
- return ERR_OK;
-}
-
-int flash_erase (flash_info_t *flash, int s_first, int s_last)
-{
- int sect;
- int prot;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (flash->flash_id == FLASH_UNKNOWN)
- printf ("- missing\n");
- else
- printf ("- no sectors to erase\n");
- return ERR_NOT_ERASED;
- }
- if (flash->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return ERR_NOT_ERASED;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++)
- if (flash->protect[sect]) prot++;
-
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- else
- printf ("\n");
-
- return do_flash_erase(flash, s_first, s_last);
-}
-
-struct jedec_flash_info {
- const uint16_t mfr_id;
- const uint16_t dev_id;
- const char *name;
- const int DevSize;
- const int InterfaceDesc;
- const int NumEraseRegions;
- const ulong regions[4];
-};
-
-#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
-
-#define SIZE_1MiB 20
-#define SIZE_2MiB 21
-#define SIZE_4MiB 22
-
-static const struct jedec_flash_info jedec_table[] = {
- {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV800T,
- name: "AMD AM29LV800T",
- DevSize: SIZE_1MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x10000,15),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV800B,
- name: "AMD AM29LV800B",
- DevSize: SIZE_1MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x10000,15),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV160T,
- name: "AMD AM29LV160T",
- DevSize: SIZE_2MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x10000,31),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV160B,
- name: "AMD AM29LV160B",
- DevSize: SIZE_2MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x04000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x10000,31)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV320T,
- name: "AMD AM29LV320T",
- DevSize: SIZE_4MiB,
- NumEraseRegions: 2,
- regions: {ERASEINFO(0x10000,63),
- ERASEINFO(0x02000,8)
- }
-
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV320B,
- name: "AMD AM29LV320B",
- DevSize: SIZE_4MiB,
- NumEraseRegions: 2,
- regions: {ERASEINFO(0x02000,8),
- ERASEINFO(0x10000,63)
- }
- }
-};
-
-static ulong cfi_init(uint32_t base, flash_info_t *flash)
-{
- int sector;
- int block;
- int block_count;
- int offset = 0;
- int reverse = 0;
- int primary;
- int mfr_id;
- int dev_id;
-
- flash->start[0] = base;
- cfi_cmd(flash, 0xF0, 0);
- cfi_cmd(flash, 0x98, 0);
- if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
- cfi_read_query(flash, 0x11) == 'R' &&
- cfi_read_query(flash, 0x12) == 'Y' )) {
- cfi_cmd(flash, 0xff, 0);
- return 0;
- }
-
- flash->size = 1 << cfi_read_query(flash, 0x27);
- flash->size *= 4;
- block_count = cfi_read_query(flash, 0x2c);
- primary = cfi_read_query(flash, 0x15);
- if ( cfi_read_query(flash, primary + 4) == 0x30)
- reverse = (cfi_read_query(flash, 0x1) & 0x01);
- else
- reverse = (cfi_read_query(flash, primary+15) == 3);
-
- flash->sector_count = 0;
-
- for ( block = reverse ? block_count - 1 : 0;
- reverse ? block >= 0 : block < block_count;
- reverse ? block-- : block ++) {
- int sector_size =
- (cfi_read_query(flash, 0x2d + block*4+2) |
- (cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
- int sector_count =
- (cfi_read_query(flash, 0x2d + block*4+0) |
- (cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
- for(sector = 0; sector < sector_count; sector++) {
- flash->start[flash->sector_count++] = base + offset;
- offset += sector_size * 4;
- }
- }
- mfr_id = cfi_read_query(flash, 0x00);
- dev_id = cfi_read_query(flash, 0x01);
-
- cfi_cmd(flash, 0xff, 0);
-
- flash->flash_id = (mfr_id << 16) | dev_id;
-
- for (sector = 0; sector < flash->sector_count; sector++) {
- write32(flash->start[sector], 0x00600060);
- write32(flash->start[sector], 0x00d000d0);
- }
- cfi_cmd(flash, 0xff, 0);
-
- for (sector = 0; sector < flash->sector_count; sector++)
- flash->protect[sector] = 0;
-
- do_flash_erase = cfi_erase;
- write_dword = cfi_write_dword;
-
- return flash->size;
-}
-
-static ulong jedec_init(unsigned long base, flash_info_t *flash)
-{
- int i;
- int block, block_count;
- int sector, offset;
- int mfr_id, dev_id;
- flash->start[0] = base;
- cfi_cmd(flash, 0xF0, 0x000);
- cfi_cmd(flash, 0xAA, 0x555);
- cfi_cmd(flash, 0x55, 0x2AA);
- cfi_cmd(flash, 0x90, 0x555);
- mfr_id = cfi_read_query(flash, 0x000);
- dev_id = cfi_read_query(flash, 0x0001);
- cfi_cmd(flash, 0xf0, 0x000);
-
- for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
- if((jedec_table[i].mfr_id == mfr_id) &&
- (jedec_table[i].dev_id == dev_id)) {
-
- flash->flash_id = (mfr_id << 16) | dev_id;
- flash->size = 1 << jedec_table[0].DevSize;
- flash->size *= 4;
- block_count = jedec_table[i].NumEraseRegions;
- offset = 0;
- flash->sector_count = 0;
- for (block = 0; block < block_count; block++) {
- int sector_size = jedec_table[i].regions[block];
- int sector_count = (sector_size & 0xff) + 1;
- sector_size >>= 8;
- for (sector=0; sector<sector_count; sector++) {
- flash->start[flash->sector_count++] =
- base + offset;
- offset += sector_size * 4;
- }
- }
- break;
- }
- }
-
- for (sector = 0; sector < flash->sector_count; sector++)
- flash->protect[sector] = 0;
-
- do_flash_erase = jedec_erase;
- write_dword = jedec_write_dword;
-
- return flash->size;
-}
-
-inline void mtibat1u(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 530, %0" :: "r" (x));
-}
-
-inline void mtibat1l(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 531, %0" :: "r" (x));
-}
-
-inline void mtdbat1u(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 538, %0" :: "r" (x));
-}
-
-inline void mtdbat1l(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 539, %0" :: "r" (x));
-}
-
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- int i;
- unsigned int msr;
-
- /* BAT1 */
- CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
- CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
- msr = get_msr();
- set_msr(msr & ~(MSR_IR | MSR_DR));
- mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- set_msr(msr);
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
- if (!size)
- size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN)
- printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
-
- return size;
-}
-
-void flash_print_info (flash_info_t *flash)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *p;
-
- if (flash->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- flash_init();
- }
-
- if (flash->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (((flash->flash_id) >> 16) & 0xff) {
- case 0x01:
- printf ("AMD ");
- break;
- case 0x04:
- printf("FUJITSU ");
- break;
- case 0x20:
- printf("STM ");
- break;
- case 0xBF:
- printf("SST ");
- break;
- case 0x89:
- case 0xB0:
- printf("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch ((flash->flash_id) & 0xffff) {
- case (uint16_t)AMD_ID_LV800T:
- printf ("AM29LV800T\n");
- break;
- case (uint16_t)AMD_ID_LV800B:
- printf ("AM29LV800B\n");
- break;
- case (uint16_t)AMD_ID_LV160T:
- printf ("AM29LV160T\n");
- break;
- case (uint16_t)AMD_ID_LV160B:
- printf ("AM29LV160B\n");
- break;
- case (uint16_t)AMD_ID_LV320T:
- printf ("AM29LV320T\n");
- break;
- case (uint16_t)AMD_ID_LV320B:
- printf ("AM29LV320B\n");
- break;
- case (uint16_t)INTEL_ID_28F800C3T:
- printf ("28F800C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F800C3B:
- printf ("28F800C3B\n");
- break;
- case (uint16_t)INTEL_ID_28F160C3T:
- printf ("28F160C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F160C3B:
- printf ("28F160C3B\n");
- break;
- case (uint16_t)INTEL_ID_28F320C3T:
- printf ("28F320C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F320C3B:
- printf ("28F320C3B\n");
- break;
- case (uint16_t)INTEL_ID_28F640C3T:
- printf ("28F640C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F640C3B:
- printf ("28F640C3B\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- if (flash->size >= (1 << 20)) {
- printf (" Size: %ld MB in %d Sectors\n",
- flash->size >> 20, flash->sector_count);
- } else {
- printf (" Size: %ld kB in %d Sectors\n",
- flash->size >> 10, flash->sector_count);
- }
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < flash->sector_count; ++i) {
- /* Check if whole sector is erased*/
- if (i != (flash->sector_count-1))
- size = flash->start[i+1] - flash->start[i];
- else
- size = flash->start[0] + flash->size - flash->start[i];
-
- erased = 1;
- p = (volatile unsigned long *)flash->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++) {
- if (*p++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-
- printf (" %08lX%s%s",
- flash->start[i],
- erased ? " E" : " ",
- flash->protect[i] ? "RO " : " ");
- }
- printf ("\n");
-}
+++ /dev/null
-/*
- * board/eva/phantom.c
- *
- * Phantom RTC device driver for EVA
- *
- * Author: Sangmoon Kim
- * dogoil@etinsys.com
- *
- * Copyright 2002 Etinsys Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
-
-#define RTC_YEAR ( RTC_BASE + 7 )
-#define RTC_MONTH ( RTC_BASE + 6 )
-#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 )
-#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 )
-#define RTC_HOURS ( RTC_BASE + 3 )
-#define RTC_MINUTES ( RTC_BASE + 2 )
-#define RTC_SECONDS ( RTC_BASE + 1 )
-#define RTC_CENTURY ( RTC_BASE + 0 )
-
-#define RTC_CONTROLA RTC_CENTURY
-#define RTC_CONTROLB RTC_SECONDS
-#define RTC_CONTROLC RTC_DAY_OF_WEEK
-
-#define RTC_CA_WRITE 0x80
-#define RTC_CA_READ 0x40
-
-#define RTC_CB_OSC_DISABLE 0x80
-
-#define RTC_CC_BATTERY_FLAG 0x80
-#define RTC_CC_FREQ_TEST 0x40
-
-
-static int phantom_flag = -1;
-static int century_flag = -1;
-
-static uchar rtc_read(unsigned int addr)
-{
- return *(volatile unsigned char *)(addr);
-}
-
-static void rtc_write(unsigned int addr, uchar val)
-{
- *(volatile unsigned char *)(addr) = val;
-}
-
-static unsigned char phantom_rtc_sequence[] = {
- 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
-};
-
-static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
-{
- int i, j;
- unsigned char v;
- unsigned char save = rtc_read(addr);
-
- for (j = 0; j < 8; j++) {
- v = phantom_rtc_sequence[j];
- for (i = 0; i < 8; i++) {
- rtc_write(addr, v & 1);
- v >>= 1;
- }
- }
- for (j = 0; j < 8; j++) {
- v = 0;
- for (i = 0; i < 8; i++) {
- if(rtc_read(addr) & 1)
- v |= 1 << i;
- }
- rtc[j] = v;
- }
- rtc_write(addr, save);
- return rtc;
-}
-
-static void phantom_rtc_write(int addr, unsigned char rtc[8])
-{
- int i, j;
- unsigned char v;
- unsigned char save = rtc_read(addr);
- for (j = 0; j < 8; j++) {
- v = phantom_rtc_sequence[j];
- for (i = 0; i < 8; i++) {
- rtc_write(addr, v & 1);
- v >>= 1;
- }
- }
- for (j = 0; j < 8; j++) {
- v = rtc[j];
- for (i = 0; i < 8; i++) {
- rtc_write(addr, v & 1);
- v >>= 1;
- }
- }
- rtc_write(addr, save);
-}
-
-static int get_phantom_flag(void)
-{
- int i;
- unsigned char rtc[8];
-
- phantom_rtc_read(RTC_BASE, rtc);
-
- for(i = 1; i < 8; i++) {
- if (rtc[i] != rtc[0])
- return 1;
- }
- return 0;
-}
-
-void rtc_reset(void)
-{
- if (phantom_flag < 0)
- phantom_flag = get_phantom_flag();
-
- if (phantom_flag) {
- unsigned char rtc[8];
- phantom_rtc_read(RTC_BASE, rtc);
- if(rtc[4] & 0x30) {
- printf( "real-time-clock was stopped. Now starting...\n" );
- rtc[4] &= 0x07;
- phantom_rtc_write(RTC_BASE, rtc);
- }
- } else {
- uchar reg_a, reg_b, reg_c;
- reg_a = rtc_read( RTC_CONTROLA );
- reg_b = rtc_read( RTC_CONTROLB );
-
- if ( reg_b & RTC_CB_OSC_DISABLE )
- {
- printf( "real-time-clock was stopped. Now starting...\n" );
- reg_a |= RTC_CA_WRITE;
- reg_b &= ~RTC_CB_OSC_DISABLE;
- rtc_write( RTC_CONTROLA, reg_a );
- rtc_write( RTC_CONTROLB, reg_b );
- }
-
- /* make sure read/write clock register bits are cleared */
- reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
- rtc_write( RTC_CONTROLA, reg_a );
-
- reg_c = rtc_read( RTC_CONTROLC );
- if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
- printf( "RTC battery low. Clock setting may not be reliable.\n");
- }
-}
-
-static int get_century_flag(void)
-{
- int flag = 0;
- int bcd, century;
- bcd = rtc_read( RTC_CENTURY );
- century = bcd2bin( bcd & 0x3F );
- rtc_write( RTC_CENTURY, bin2bcd(century+1));
- if (bcd == rtc_read( RTC_CENTURY ))
- flag = 1;
- rtc_write( RTC_CENTURY, bcd);
- return flag;
-}
-
-int rtc_get( struct rtc_time *tmp)
-{
- if (phantom_flag < 0)
- phantom_flag = get_phantom_flag();
-
- if (phantom_flag)
- {
- unsigned char rtc[8];
-
- phantom_rtc_read(RTC_BASE, rtc);
-
- tmp->tm_sec = bcd2bin(rtc[1] & 0x7f);
- tmp->tm_min = bcd2bin(rtc[2] & 0x7f);
- tmp->tm_hour = bcd2bin(rtc[3] & 0x1f);
- tmp->tm_wday = bcd2bin(rtc[4] & 0x7);
- tmp->tm_mday = bcd2bin(rtc[5] & 0x3f);
- tmp->tm_mon = bcd2bin(rtc[6] & 0x1f);
- tmp->tm_year = bcd2bin(rtc[7]) + 1900;
- tmp->tm_yday = 0;
- tmp->tm_isdst = 0;
-
- if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
- if (tmp->tm_year < 1970) tmp->tm_year += 100;
- } else {
- uchar sec, min, hour;
- uchar mday, wday, mon, year;
-
- int century;
-
- uchar reg_a;
-
- if (century_flag < 0)
- century_flag = get_century_flag();
-
- reg_a = rtc_read( RTC_CONTROLA );
- /* lock clock registers for read */
- rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
-
- sec = rtc_read( RTC_SECONDS );
- min = rtc_read( RTC_MINUTES );
- hour = rtc_read( RTC_HOURS );
- mday = rtc_read( RTC_DAY_OF_MONTH );
- wday = rtc_read( RTC_DAY_OF_WEEK );
- mon = rtc_read( RTC_MONTH );
- year = rtc_read( RTC_YEAR );
- century = rtc_read( RTC_CENTURY );
-
- /* unlock clock registers after read */
- rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
-
- tmp->tm_sec = bcd2bin( sec & 0x7F );
- tmp->tm_min = bcd2bin( min & 0x7F );
- tmp->tm_hour = bcd2bin( hour & 0x3F );
- tmp->tm_mday = bcd2bin( mday & 0x3F );
- tmp->tm_mon = bcd2bin( mon & 0x1F );
- tmp->tm_wday = bcd2bin( wday & 0x07 );
-
- if (century_flag) {
- tmp->tm_year = bcd2bin( year ) +
- ( bcd2bin( century & 0x3F ) * 100 );
- } else {
- tmp->tm_year = bcd2bin( year ) + 1900;
- if (tmp->tm_year < 1970) tmp->tm_year += 100;
- }
-
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
- }
-
- return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
- if (phantom_flag < 0)
- phantom_flag = get_phantom_flag();
-
- if (phantom_flag) {
- uint year;
- unsigned char rtc[8];
-
- year = tmp->tm_year;
- year -= (year < 2000) ? 1900 : 2000;
-
- rtc[0] = bin2bcd(0);
- rtc[1] = bin2bcd(tmp->tm_sec);
- rtc[2] = bin2bcd(tmp->tm_min);
- rtc[3] = bin2bcd(tmp->tm_hour);
- rtc[4] = bin2bcd(tmp->tm_wday);
- rtc[5] = bin2bcd(tmp->tm_mday);
- rtc[6] = bin2bcd(tmp->tm_mon);
- rtc[7] = bin2bcd(year);
-
- phantom_rtc_write(RTC_BASE, rtc);
- } else {
- uchar reg_a;
- if (century_flag < 0)
- century_flag = get_century_flag();
-
- /* lock clock registers for write */
- reg_a = rtc_read( RTC_CONTROLA );
- rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
-
- rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
-
- rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
- rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
- rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
- rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
- rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
-
- /* break year up into century and year in century */
- if (century_flag) {
- rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
- rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
- reg_a &= 0xc0;
- reg_a |= bin2bcd( tmp->tm_year / 100 );
- } else {
- rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
- ((tmp->tm_year < 2000) ? 1900 : 2000)));
- }
-
- /* unlock clock registers after read */
- rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
- }
-
- return 0;
-}
-
-#endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = kvme080.o multiverse.o
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-int checkboard(void)
-{
- puts ("Board: KVME080\n");
- return 0;
-}
-
-unsigned long setdram(int m, int row, int col, int bank)
-{
- int i;
- unsigned long start, end;
- uint32_t mccr1;
- uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
- uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
- uint8_t mber = 0;
-
- CONFIG_READ_WORD(MCCR1, mccr1);
- mccr1 &= 0xffff0000;
-
- start = CONFIG_SYS_SDRAM_BASE;
- end = start + (1 << (col + row + 3) ) * bank - 1;
-
- for (i = 0; i < m; i++) {
- mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
- if (i < 4) {
- msar1 |= ((start >> 20) & 0xff) << i * 8;
- emsar1 |= ((start >> 28) & 0xff) << i * 8;
- mear1 |= ((end >> 20) & 0xff) << i * 8;
- emear1 |= ((end >> 28) & 0xff) << i * 8;
- } else {
- msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
- emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
- mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
- emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
- }
- mber |= 1 << i;
- start += (1 << (col + row + 3) ) * bank;
- end += (1 << (col + row + 3) ) * bank;
- }
- for (; i < 8; i++) {
- if (i < 4) {
- msar1 |= 0xff << i * 8;
- emsar1 |= 0x30 << i * 8;
- mear1 |= 0xff << i * 8;
- emear1 |= 0x30 << i * 8;
- } else {
- msar2 |= 0xff << (i-4) * 8;
- emsar2 |= 0x30 << (i-4) * 8;
- mear2 |= 0xff << (i-4) * 8;
- emear2 |= 0x30 << (i-4) * 8;
- }
- }
-
- CONFIG_WRITE_WORD(MCCR1, mccr1);
- CONFIG_WRITE_WORD(MSAR1, msar1);
- CONFIG_WRITE_WORD(EMSAR1, emsar1);
- CONFIG_WRITE_WORD(MEAR1, mear1);
- CONFIG_WRITE_WORD(EMEAR1, emear1);
- CONFIG_WRITE_WORD(MSAR2, msar2);
- CONFIG_WRITE_WORD(EMSAR2, emsar2);
- CONFIG_WRITE_WORD(MEAR2, mear2);
- CONFIG_WRITE_WORD(EMEAR2, emear2);
- CONFIG_WRITE_BYTE(MBER, mber);
-
- return (1 << (col + row + 3) ) * bank * m;
-}
-
-phys_size_t initdram(int board_type)
-{
- unsigned int msr;
- long int size = 0;
-
- msr = mfmsr();
- mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
- mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
- mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
- mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
- mtmsr(msr);
-
- if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
- size = 0x20000000; /* 512MB */
- else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
- size = 0x10000000; /* 256MB */
- else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
- size = 0x10000000; /* 256MB */
- else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
- size = 0x08000000; /* 128MB */
- else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
- size = 0x08000000; /* 128MB */
- else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
- size = 0x04000000; /* 64MB */
-
- msr = mfmsr();
- mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
- mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
- mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
- mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
- mtmsr(msr);
-
- return size;
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_early_init_f(void)
-{
- *(volatile unsigned char *)(0xff080120) = 0xfb;
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- unsigned int msr;
-
- CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
- CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
- CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
-
- msr = mfmsr();
- mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- mtmsr(msr);
-
- return 0;
-}
-
-extern int multiverse_init(void);
-
-int misc_init_r(void)
-{
- multiverse_init();
- return 0;
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
- volatile uchar *d = (volatile uchar*) dest;
- volatile uchar *s = (volatile uchar*) src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
- return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
- volatile uchar *d = (volatile uchar*)dest;
- volatile uchar *s = (volatile uchar*)src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * multiverse.c
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- * dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/compiler.h>
-
-#include "multiverse.h"
-
-static unsigned long vme_asi_addr;
-static unsigned long vme_iack_addr;
-static unsigned long pci_reg_addr;
-static unsigned long vme_reg_addr;
-
-int multiv_reset(unsigned long base)
-{
- writeb(0x09, base + VME_SLAVE32_AM);
- writeb(0x39, base + VME_SLAVE24_AM);
- writeb(0x29, base + VME_SLAVE16_AM);
- writeb(0x2f, base + VME_SLAVE_REG_AM);
- writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
- writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
- writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
-#ifdef A32_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
- base + VME_SLAVE32_MASK);
- writeb(0x01, base + VME_SLAVE32_EN);
- } else {
- writeb(0xff, base + VME_SLAVE32_MASK);
- writeb(0x00, base + VME_SLAVE32_EN);
- }
-#else
- writeb(0xff, base + VME_SLAVE32_MASK);
- writeb(0x00, base + VME_SLAVE32_EN);
-#endif
-#ifdef A24_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
- base + VME_SLAVE24_MASK);
- writeb(0x01, base + VME_SLAVE24_EN);
- } else {
- writeb(0xff, base + VME_SLAVE24_MASK);
- writeb(0x00, base + VME_SLAVE24_EN);
- }
-#else
- writeb(0xff, base + VME_SLAVE24_MASK);
- writeb(0x00, base + VME_SLAVE24_EN);
-#endif
-#ifdef A16_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
- base + VME_SLAVE16_MASK);
- writeb(0x01, base + VME_SLAVE16_EN);
- } else {
- writeb(0xff, base + VME_SLAVE16_MASK);
- writeb(0x00, base + VME_SLAVE16_EN);
- }
-#else
- writeb(0xff, base + VME_SLAVE16_MASK);
- writeb(0x00, base + VME_SLAVE16_EN);
-#endif
-#ifdef REG_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
- base + VME_SLAVE_REG_MASK);
- writeb(0x01, base + VME_SLAVE_REG_EN);
- } else {
- writeb(0xf8, base + VME_SLAVE_REG_MASK);
- }
-#else
- writeb(0xf8, base + VME_SLAVE_REG_MASK);
-#endif
- writeb(0x09, base + VME_MASTER32_AM);
- writeb(0x39, base + VME_MASTER24_AM);
- writeb(0x29, base + VME_MASTER16_AM);
- writeb(0x2f, base + VME_MASTER_REG_AM);
- writel(0x00000000, base + VME_RMW_ADRS);
- writeb(0x00, base + VME_IRQ);
- writeb(0x00, base + VME_INT_EN);
- writel(0x00000000, base + VME_IRQ1_REG);
- writel(0x00000000, base + VME_IRQ2_REG);
- writel(0x00000000, base + VME_IRQ3_REG);
- writel(0x00000000, base + VME_IRQ4_REG);
- writel(0x00000000, base + VME_IRQ5_REG);
- writel(0x00000000, base + VME_IRQ6_REG);
- writel(0x00000000, base + VME_IRQ7_REG);
- return 0;
-}
-
-void multiv_auto_slot_id(unsigned long base)
-{
- __maybe_unused unsigned int vector;
- int slot_id = 1;
- if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
- *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
- writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
- writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
- base + VME_CTRL);
- while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- while (readb(base + VME_INT) & 0x04) {
- vector = *(volatile unsigned int*)
- (vme_iack_addr + VME_IACK2);
- *(unsigned char*)(vme_asi_addr + 0x7ffff)
- = (slot_id << 3) & 0xff;
- slot_id ++;
- if (slot_id > 31)
- break;
- }
- }
- }
-}
-
-int multiverse_init(void)
-{
- int i;
- pci_dev_t pdev;
- unsigned int bar[6];
-
- pdev = pci_find_device(0x1895, 0x0001, 0);
-
- if (pdev == 0)
- return -1;
-
- for (i = 0; i < 6; i++)
- pci_read_config_dword (pdev,
- PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
-
- pci_reg_addr = bar[0];
- vme_reg_addr = bar[1] + 0x00F00000;
- vme_iack_addr = bar[1] + 0x00200000;
- vme_asi_addr = bar[3];
-
- pci_write_config_dword (pdev, PCI_COMMAND,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- writel(0xFF000000, pci_reg_addr + P_TA1);
- writel(0x04, pci_reg_addr + P_IMG_CTRL1);
- writel(0xf0000000, pci_reg_addr + P_TA2);
- writel(0x04, pci_reg_addr + P_IMG_CTRL2);
- writel(0xF1000000, pci_reg_addr + P_TA3);
- writel(0x04, pci_reg_addr + P_IMG_CTRL3);
- writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
- writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
- writel(0x04, pci_reg_addr + P_IMG_CTRL5);
-
- writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
- writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
- writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
- writel(0x04, pci_reg_addr + W_IMG_CTRL1);
-
- writel(0xF0000000, pci_reg_addr + W_BA2);
- writel(0xFF000000, pci_reg_addr + W_AM2);
- writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
- writel(0x04, pci_reg_addr + W_IMG_CTRL2);
-
- writel(0xFF000000, pci_reg_addr + W_BA3);
- writel(0xFF000000, pci_reg_addr + W_AM3);
- writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
- writel(0x04, pci_reg_addr + W_IMG_CTRL3);
-
- writel(0x00000001, pci_reg_addr + W_ERR_CS);
- writel(0x00000001, pci_reg_addr + P_ERR_CS);
-
- multiv_reset(vme_reg_addr);
- writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
- vme_reg_addr + VME_CTRL);
-
- multiv_auto_slot_id(vme_reg_addr);
-
- return 0;
-}
+++ /dev/null
-/*
- * multiverse.h
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- * dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MULTIVERSE_H__
-#define __MULTIVERSE_H__
-
-#define VME_A32_MSTR_BUS 0x90000000
-#define VME_A32_MSTR_SIZE 0x01000000
-
-#define VME_A32_SLV_SIZE 0x01000000
-
-#define VME_A32_SLV_BUS 0x90000000
-#define VME_A24_SLV_BUS 0x00000000
-#define VME_A16_SLV_BUS 0x00000000
-
-#define VME_A32_SLV_LOCAL 0x00000000
-#define VME_A24_SLV_LOCAL 0x00000000
-#define VME_A16_SLV_LOCAL 0x00000000
-
-#define A32_SLV_WINDOW
-#undef A24_SLV_WINDOW
-#undef A16_SLV_WINDOW
-#undef REG_SLV_WINDOW
-
-/* PCI Registers */
-
-#define P_IMG_CTRL0 0x100
-#define P_BA0 0x104
-#define P_AM0 0x108
-#define P_TA0 0x10C
-#define P_IMG_CTRL1 0x110
-#define P_BA1 0x114
-#define P_AM1 0x118
-#define P_TA1 0x11C
-#define P_IMG_CTRL2 0x120
-#define P_BA2 0x124
-#define P_AM2 0x128
-#define P_TA2 0x12C
-#define P_IMG_CTRL3 0x130
-#define P_BA3 0x134
-#define P_AM3 0x138
-#define P_TA3 0x13C
-#define P_IMG_CTRL4 0x140
-#define P_BA4 0x144
-#define P_AM4 0x148
-#define P_TA4 0x14C
-#define P_IMG_CTRL5 0x150
-#define P_BA5 0x154
-#define P_AM5 0x158
-#define P_TA5 0x15C
-#define P_ERR_CS 0x160
-#define P_ERR_ADDR 0x164
-#define P_ERR_DATA 0x168
-
-#define WB_CONF_SPC_BAR 0x180
-#define W_IMG_CTRL1 0x184
-#define W_BA1 0x188
-#define W_AM1 0x18C
-#define W_TA1 0x190
-#define W_IMG_CTRL2 0x194
-#define W_BA2 0x198
-#define W_AM2 0x19C
-#define W_TA2 0x1A0
-#define W_IMG_CTRL3 0x1A4
-#define W_BA3 0x1A8
-#define W_AM3 0x1AC
-#define W_TA3 0x1B0
-#define W_IMG_CTRL4 0x1B4
-#define W_BA4 0x1B8
-#define W_AM4 0x1BC
-#define W_TA4 0x1C0
-#define W_IMG_CTRL5 0x1C4
-#define W_BA5 0x1C8
-#define W_AM5 0x1CC
-#define W_TA5 0x1D0
-#define W_ERR_CS 0x1D4
-#define W_ERR_ADDR 0x1D8
-#define W_ERR_DATA 0x1DC
-#define CNF_ADDR 0x1E0
-#define CNF_DATA 0x1E4
-#define INT_ACK 0x1E8
-#define ICR 0x1EC
-#define ISR 0x1F0
-
-/* VME registers */
-
-#define VME_SLAVE32_AM 0x03
-#define VME_SLAVE24_AM 0x02
-#define VME_SLAVE16_AM 0x01
-#define VME_SLAVE_REG_AM 0x00
-#define VME_SLAVE32_A 0x07
-#define VME_SLAVE24_A 0x06
-#define VME_SLAVE16_A 0x05
-#define VME_SLAVE_REG_A 0x04
-#define VME_SLAVE32_MASK 0x0B
-#define VME_SLAVE24_MASK 0x0A
-#define VME_SLAVE16_MASK 0x09
-#define VME_SLAVE_REG_MASK 0x08
-#define VME_SLAVE32_EN 0x0F
-#define VME_SLAVE24_EN 0x0E
-#define VME_SLAVE16_EN 0x0D
-#define VME_SLAVE_REG_EN 0x0C
-#define VME_MASTER32_AM 0x13
-#define VME_MASTER24_AM 0x12
-#define VME_MASTER16_AM 0x11
-#define VME_MASTER_REG_AM 0x10
-#define VME_RMW_ADRS 0x14
-#define VME_MBOX 0x18
-#define VME_STATUS 0x1E
-#define VME_CTRL 0x1C
-#define VME_IRQ 0x20
-#define VME_INT_EN 0x21
-#define VME_INT 0x22
-#define VME_IRQ1_REG 0x24
-#define VME_IRQ2_REG 0x28
-#define VME_IRQ3_REG 0x2C
-#define VME_IRQ4_REG 0x30
-#define VME_IRQ5_REG 0x34
-#define VME_IRQ6_REG 0x38
-#define VME_IRQ7_REG 0x3C
-
-/* VME control register */
-
-#define VME_CTRL_BRDRST 0x01
-#define VME_CTRL_SYSRST 0x02
-#define VME_CTRL_RMW 0x04
-#define VME_CTRL_SHORT_D 0x08
-#define VME_CTRL_SYSFAIL 0x10
-#define VME_CTRL_VOWN 0x20
-#define VME_CTRL_A16_REG_MODE 0x40
-
-/* VME status register */
-
-#define VME_STATUS_SYSCON 0x01
-#define VME_STATUS_SYSFAIL 0x02
-#define VME_STATUS_ACFAIL 0x04
-#define VME_STATUS_SYSRST 0x08
-#define VME_STATUS_VOWN 0x10
-
-/* Interrupt types */
-
-#define LVL1 0x0002
-#define LVL2 0x0004
-#define LVL3 0x0008
-#define LVL4 0x0010
-#define LVL5 0x0020
-#define LVL6 0x0040
-#define LVL7 0x0080
-#define MULTIVERSE_INTI_INT 0x0100
-#define MULTIVERSE_WB_INT 0x0200
-#define MULTIVERSE_PCI_INT 0x0400
-
-/* interrupt acknowledge */
-
-#define VME_IACK1 0x04
-#define VME_IACK2 0x08
-#define VME_IACK3 0x0c
-#define VME_IACK4 0x10
-#define VME_IACK5 0x14
-#define VME_IACK6 0x18
-#define VME_IACK7 0x1c
-
-#endif /* __MULTIVERSE_H__ */
}
switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
case 0x9E:
case 0x9A:
case 0x98:
* For this SerDes2's Refclk1 need to be set to 100MHz
*/
switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
case 0x9E:
case 0x9A:
case 0xb2:
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc8260ads.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * (C) Copyright 2003 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Re-written to support multi-bank flash SIMMs.
- * Added support for real protection and JFFS2.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT 0x89898989
-#define INTEL_ALT 0xB0B0B0B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x10101010
-#define INTEL_ERASE 0x20202020
-#define INTEL_CLEAR 0x50505050
-#define INTEL_LOCKBIT 0x60606060
-#define INTEL_PROTECT 0x01010101
-#define INTEL_STATUS 0x70707070
-#define INTEL_READID 0x90909090
-#define INTEL_CONFIRM 0xD0D0D0D0
-#define INTEL_RESET 0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x80808080
-#define INTEL_OK 0x80808080
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
- * Up to 32MB of flash supported (up to 4 banks.)
- * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
- *
- * The following code can not run from flash!
- */
-unsigned long flash_init (void)
-{
- ulong size = 0, sect_start, sect_size = 0, bank_size;
- ushort sect_count = 0;
- int i, j, nbanks;
- vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
- switch (bcsr[2] & 0xF) {
- case 0:
- nbanks = 4;
- break;
- case 1:
- nbanks = 2;
- break;
- case 2:
- nbanks = 1;
- break;
- default: /* Unsupported configurations */
- nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
- }
-
- if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
- nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-
- for (i = 0; i < nbanks; i++) {
- *addr = INTEL_READID; /* Read Intelligent Identifier */
- if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
- switch (addr[1]) {
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- sect_count = 32;
- sect_size = 0x40000;
- break;
- default:
- flash_info[i].flash_id = FLASH_UNKNOWN;
- sect_count = CONFIG_SYS_MAX_FLASH_SECT;
- sect_size =
- CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
- }
- }
- else
- flash_info[i].flash_id = FLASH_UNKNOWN;
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
- addr[0], addr[1], (ulong)addr);
- size = 0;
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- break;
- }
- flash_info[i].sector_count = sect_count;
- flash_info[i].size = bank_size = sect_size * sect_count;
- size += bank_size;
- sect_start = (ulong)addr;
- for (j = 0; j < sect_count; j++) {
- addr = (vu_long *)sect_start;
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = (addr[2] == 0x01010101);
- sect_start += sect_size;
- }
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- addr = (vu_long *)sect_start;
- }
-
- if (size == 0) { /* Unknown flash, fill with hard-coded values */
- sect_start = CONFIG_SYS_FLASH_BASE;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
- flash_info[i].sector_count = sect_count;
- for (j = 0; j < sect_count; j++) {
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = 0;
- sect_start += sect_size;
- }
- }
- size = CONFIG_SYS_FLASH_SIZE;
- }
- else
- for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = 0;
- flash_info[i].sector_count = 0;
- }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Clear Status Register */
- *addr = INTEL_CLEAR;
- /* Single Block Erase Command */
- *addr = INTEL_ERASE;
- /* Confirm */
- *addr = INTEL_CONFIRM;
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = INTEL_CONFIRM;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Block erase failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
-
- /* reset to read mode */
- *addr = INTEL_RESET;
- }
- }
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- ulong start;
- int rc = 0;
- int flag;
- vu_long *addr = (vu_long *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
-
- *addr = INTEL_CLEAR; /* Clear status register */
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = INTEL_PROGRAM;
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- printf("Write timed out\n");
- rc = 1;
- break;
- }
- }
- if (*addr != INTEL_OK) {
- printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- rc = write_word(info, wp, data);
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- ulong start;
- int i;
- int rc = 0;
- vu_long *addr = (vu_long *)(info->start[sector]);
- int flag = disable_interrupts();
-
- *addr = INTEL_CLEAR; /* Clear status register */
- if (prot) { /* Set sector lock bit */
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- }
- else { /* Clear sector lock bit */
- *addr = INTEL_LOCKBIT; /* All sectors lock bits */
- *addr = INTEL_CONFIRM; /* clear */
- }
-
- start = get_timer(0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- if (!rc)
- info->protect[sector] = prot;
-
- /*
- * Clear lock bit command clears all sectors lock bits, so
- * we have to restore lock bits of protected sectors.
- */
- if (!prot)
- for (i = 0; i < info->sector_count; i++)
- if (info->protect[i]) {
- addr = (vu_long *)(info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
- }
-
- if (flag)
- enable_interrupts();
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
- /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
- /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
- /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
-#else
- /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
-#else
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-void reset_phy (void)
-{
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
- /* Reset the PHY */
-#if CONFIG_SYS_PHY_ADDR == 0
- bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
- udelay(2);
- bcsr[1] |= FETH1_RST;
-#else
- bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
- udelay(2);
- bcsr[3] |= FETH2_RST;
-#endif /* CONFIG_SYS_PHY_ADDR == 0 */
- udelay(1000);
-#ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
- /*
- * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
- * Enable autonegotiation.
- */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#else
- /*
- * Ethernet PHY is configured (by means of configuration pins)
- * to work at 10Mb/s only. We reconfigure it using MII
- * to advertise all capabilities, including 100Mb/s, and
- * restart autonegotiation.
- */
-
- /* Advertise all capabilities */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
-
- /* Do not bypass Rx/Tx (de)scrambler */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000);
-
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-#endif /* CONFIG_MII */
-}
-
-#ifdef CONFIG_PCI
-typedef struct pci_ic_s {
- unsigned long pci_int_stat;
- unsigned long pci_int_mask;
-}pci_ic_t;
-#endif
-
-int board_early_init_f (void)
-{
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-#ifdef CONFIG_PCI
- volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
-
- /* mask alll the PCI interrupts */
- pci_ic->pci_int_mask |= 0xfff00000;
-#endif
-#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
- bcsr[1] &= ~RS232EN_1;
-#endif
-#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
- bcsr[1] &= ~RS232EN_2;
-#endif
-
-#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
- {
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
- immap->im_siu_conf.sc_siumcr =
- (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
- | SIUMCR_LBPC01;
- }
-#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
-
- return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- long int msize = 32;
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- long int msize = 64;
-#else
- long int msize = 16;
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *ramaddr, c = 0xff;
- uint or;
- uint psdmr;
- uint psrt;
-
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x00000002;
- immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifdef CONFIG_SYS_LSDRAM_BASE
- /*
- Initialise local bus SDRAM only if the pins
- are configured as local bus pins and not as PCI.
- The configuration is determined by the HRCW.
- */
- if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
- memctl->memc_or3 = 0xFF803280;
- memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#else /* CS4 */
- memctl->memc_or4 = 0xFFC01480;
- memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
- ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
- }
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
- /* Init 60x bus SDRAM */
-#ifdef CONFIG_SPD_EEPROM
- {
- spd_eeprom_t spd;
- uint pbi, bsel, rowst, lsb, tmp;
-
- i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
-
- /* Bank-based interleaving is not supported for physical bank
- sizes greater than 128MB which is encoded as 0x20 in SPD
- */
- pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
- msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
- or = ~(msize - 1) << 20; /* SDAM */
- switch (spd.nbanks) { /* BPD */
- case 2:
- bsel = 1;
- break;
- case 4:
- bsel = 2;
- or |= 0x00002000;
- break;
- case 8:
- bsel = 3;
- or |= 0x00004000;
- break;
- }
- lsb = 3; /* For 64-bit port, lsb is 3 bits */
-
- if (pbi) { /* Bus partition depends on interleaving */
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
- or |= (rowst << 9); /* ROWST */
- } else {
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
- or |= ((rowst * 2 - 12) << 9); /* ROWST */
- }
- or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
-
- psdmr = (pbi << 31); /* PBI */
- /* Bus multiplexing parameters */
- tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
- psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
- psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
-
- tmp = (31 - lsb - 10) - tmp;
- /* Pin connected to SDA10 is (31 - lsb - 10).
- rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
- so (rowst + tmp) alternates with AP.
- */
- if (pbi) /* Table 10-7 */
- psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
- else
- psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
-
- /* SDRAM device-specific parameters */
- tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
- switch (tmp) { /* RFRC */
- case 1:
- case 2:
- psdmr |= (1 << 15);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- psdmr |= ((tmp - 2) << 15);
- break;
- default:
- psdmr |= (7 << 15);
- }
- psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
- psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
- /* BL=0 because for 64-bit SDRAM burst length must be 4 */
- /* LDOTOPRE ??? */
- for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- switch (i) { /* WRC */
- case 0:
- case 1:
- psdmr |= (1 << 4);
- break;
- case 2:
- case 3:
- psdmr |= (i << 4);
- break;
- }
- /* EAMUX=0 - no external address multiplexing */
- /* BUFCMD=0 - no external buffers */
- for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- psdmr |= i; /* CL */
-
- switch (spd.refresh & 0x7F) {
- case 1:
- tmp = 3900;
- break;
- case 2:
- tmp = 7800;
- break;
- case 3:
- tmp = 31300;
- break;
- case 4:
- tmp = 62500;
- break;
- case 5:
- tmp = 125000;
- break;
- default:
- tmp = 15625;
- }
- psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
- ((memctl->memc_mptpr >> 8) + 1)) - 1;
-#ifdef SPD_DEBUG
- printf ("\nDIMM type: %-18.18s\n", spd.mpart);
- printf ("SPD size: %d\n", spd.info_size);
- printf ("EEPROM size: %d\n", 1 << spd.chip_size);
- printf ("Memory type: %d\n", spd.mem_type);
- printf ("Row addr: %d\n", spd.nrow_addr);
- printf ("Column addr: %d\n", spd.ncol_addr);
- printf ("# of rows: %d\n", spd.nrows);
- printf ("Row density: %d\n", spd.row_dens);
- printf ("# of banks: %d\n", spd.nbanks);
- printf ("Data width: %d\n",
- 256 * spd.dataw_msb + spd.dataw_lsb);
- printf ("Chip width: %d\n", spd.primw);
- printf ("Refresh rate: %02X\n", spd.refresh);
- printf ("CAS latencies: %02X\n", spd.cas_lat);
- printf ("Write latencies: %02X\n", spd.write_lat);
- printf ("tRP: %d\n", spd.trp);
- printf ("tRCD: %d\n", spd.trcd);
-
- printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
-#endif /* SPD_DEBUG */
- }
-#else /* !CONFIG_SPD_EEPROM */
- or = CONFIG_SYS_OR2;
- psdmr = CONFIG_SYS_PSDMR;
- psrt = CONFIG_SYS_PSRT;
-#endif /* CONFIG_SPD_EEPROM */
- memctl->memc_psrt = psrt;
- memctl->memc_or2 = or;
- memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
- ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
- memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
- *ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /* return total 60x bus SDRAM size */
- return (msize * 1024 * 1024);
-}
-
-int checkboard (void)
-{
-#if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
- puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
- puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- puts ("Board: Motorola MPC8272ADS\n");
-#else
- puts ("Board: unknown\n");
-#endif
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-}
-#endif
fdt_fixup_memory(blob, (u64)base, (u64)size);
- /* By default NOR is on, and NAND is disabled */
-#ifdef CONFIG_NAND_U_BOOT
- do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
- do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
-#endif
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_4M, 1),
-#ifndef CONFIG_NAND_SPL
/* *W*G* - BCSR and NOR flash on local bus*/
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
- {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
- {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
- {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
switch (srds_s1) {
+ case 0x1b:
case 0x1c:
case 0x95:
case 0xa2:
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
+ case 0x50:
case 0x51:
+ case 0x5e:
case 0x5f:
+ case 0x64:
case 0x65:
/* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x66:
+ case 0x67:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
fm_info_set_phy_address(FM1_10GEC3, 6);
fm_info_set_phy_address(FM1_10GEC4, 7);
break;
+ case 0x6a:
case 0x6b:
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
+ case 0x70:
case 0x71:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+ (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
(srds_s1 == 0x71)) {
/* As XFI is in cage intead of a slot, so
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/2133MT/s
12100017 15000000 00000000 00000000
-66160002 00008400 e8104000 c1000000
+66150002 00008400 e8104000 c1000000
00000000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004
/* SerDes1 is not enabled */
break;
#if defined(CONFIG_T2080QDS)
+ case 0x1b:
case 0x1c:
case 0xa2:
/* SD1(A:D) => SLOT3 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x3a);
break;
+ case 0x50:
case 0x51:
/* SD1(A:D) => SLOT3 XAUI
* SD1(E) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xfe);
break;
+ case 0x6a:
case 0x6b:
/* SD1(A:D) => XFI cage
* SD1(E) => SLOT1 PCIe4
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
#elif defined(CONFIG_T2081QDS)
+ case 0x50:
case 0x51:
/* SD1(A:D) => SLOT2 XAUI
* SD1(E) => SLOT1 PCIe4 x1
QIXIS_WRITE(brdcfg[12], 0x98);
QIXIS_WRITE(brdcfg[13], 0x70);
break;
+ case 0x6a:
case 0x6b:
/* SD1(A:D) => XFI SFP Module
* SD1(E) => SLOT1 PCIe4 x1
QIXIS_WRITE(brdcfg[13], 0x70);
break;
case 0x6c:
- /* SD1(A:B) => XFI SFP Module
- * SD1(C:D) => SLOT2 SGMII
- * SD1(E:H) => SLOT1 PCIe4 x4
- */
- QIXIS_WRITE(brdcfg[12], 0xe8);
- QIXIS_WRITE(brdcfg[13], 0x0);
- break;
case 0x6d:
/* SD1(A:B) => XFI SFP Module
* SD1(C:D) => SLOT2 SGMII
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/1600MT/s
120c0017 15000000 00000000 00000000
-66160002 00008400 ec104000 c1000000
+66150002 00008400 ec104000 c1000000
00000000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
break;
+ case 27:
case 28:
+ case 35:
case 36:
/* SGMII in Slot1 and Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
slot_qsgmii_phyaddr[1][2]);
}
break;
+ case 37:
case 38:
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
slot_qsgmii_phyaddr[1][3]);
}
break;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
break;
+ case 6:
case 7:
+ case 12:
case 13:
case 14:
+ case 15:
case 16:
+ case 21:
case 22:
case 23:
+ case 24:
case 25:
case 26:
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
+ case 27:
case 28:
+ case 35:
case 36:
/* SGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
+ case 37:
case 38:
/* QSGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
break;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
+ case 49:
case 50:
+ case 51:
case 52:
+ case 53:
case 54:
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_prtcl_s1) {
+ case 37:
case 38:
/* swap first lane and third lane on slot1 */
vsc3316_fsm1_tx[0][1] = 14;
vsc3316_fsm1_tx[6][1] = 0;
vsc3316_fsm1_rx[1][1] = 2;
vsc3316_fsm1_rx[6][1] = 13;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
/* swap first lane and third lane on slot2 */
vsc3316_fsm1_tx[2][1] = 8;
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
switch (srds_prtcl_s2) {
+ case 37:
case 38:
/* swap first lane and third lane on slot3 */
vsc3316_fsm2_tx[2][1] = 11;
vsc3316_fsm2_tx[5][1] = 4;
vsc3316_fsm2_rx[2][1] = 9;
vsc3316_fsm2_rx[4][1] = 7;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
+ case 49:
case 50:
+ case 51:
case 52:
+ case 53:
case 54:
/* swap first lane and third lane on slot4 */
vsc3316_fsm2_tx[6][1] = 3;
case 0:
/* SerDes3 is not enabled */
break;
+ case 1:
case 2:
case 9:
case 10:
brdcfg |= BRDCFG12_SD3MX_SLOT5;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
+ case 3:
case 4:
+ case 5:
case 6:
+ case 7:
case 8:
+ case 11:
case 12:
+ case 13:
case 14:
+ case 15:
case 16:
case 17:
+ case 18:
case 19:
case 20:
/* SD3(4:7) => SLOT6(0:3) */
case 0:
/* SerDes4 is not enabled */
break;
+ case 1:
case 2:
/* 10b, SD4(0:7) => SLOT7(0:7) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg |= BRDCFG12_SD4MX_SLOT7;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
+ case 3:
case 4:
+ case 5:
case 6:
+ case 7:
case 8:
/* x1b, SD4(4:7) => SLOT8(0:3) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg |= BRDCFG12_SD4MX_SLOT8;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
+ case 9:
case 10:
+ case 11:
case 12:
+ case 13:
case 14:
+ case 15:
case 16:
case 18:
/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 1_28_6_12
+#serdes protocol 1_27_5_11
16070019 18101916 00000000 00000000
-04383060 30548c00 ec020000 f5000000
+04362858 30548c00 ec020000 f5000000
00000000 ee0000ee 00000000 000307fc
00000000 00000000 00000000 00000028
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
- if (srds_prtcl_s1 == 28) {
+ if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 28_56_2_10
+#serdes protocol 27_56_1_9
16070019 18101916 00000000 00000000
-70701050 00448c00 6c020000 f5000000
+6c700848 00448c00 6c020000 f5000000
00000000 ee0000ee 00000000 000287fc
00000000 50000000 00000000 00000028
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hidden_dragon.o flash.o
+++ /dev/null
-U-Boot for Hidden Dragon board
-------------------------------
-
-Hidden Dragon is a MPC824x-based board by Motorola. For the most
-part it is similar to Sandpoint8245 board. So unless otherwise
-mentioned, the codes in this directory are adapted from ../sandpoint
-directory.
-
-Apparently there are very few of this board out there. Even Motorola
-website does not have any info on it.
-
-RAM:
- start = 0x0000 0000
- size = 0x0200 0000 (32 MB)
-
-Flash:
- BANK ONE:
- start = 0xFFE0 0000
- size = 0x0020 0000 (2 MB)
- flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
- flash sectors = 16K, 2x8K, 32K, 31x64K
-
- BANK TWO:
- NONE
-
-The processor interrupt vectors reside on the first 256 bytes
-starting from address 0xFFF00000. The "reset vector" (first
-instruction executed after reset) is located on 0xFFF0 0100.
-
-U-Boot is configured to reside in flash starting at the address of
-0xFFF00000. The environment space is located in flash separately from
-U-Boot, at the second sector of the first flash bank, starting from
-0xFFE04000 until 0xFFE06000 (8KB).
-
-Network:
- - RTL8139 chip on the base board (SUPPORTED)
- - RTL8129 chip on the processor board (NOT SUPPORTED)
-
-Serial:
- - Two NS16550 compatible UART on the processor board (SUPPORTED)
- - One NS16550 compatible UART on the base board (UNTESTED)
-
-Misc:
- VIA686A PCI SuperIO peripheral controller
- - 2 USB ports (UNTESTED)
- - 2 PS2 ports (UNTESTED)
- - Parallel port (UNTESTED)
- - IDE & floppy interface (UNTESTED)
-
- S3 Savage4 video card (UNTESTED)
-
-TODO:
------
-- Support for the VIA686A based peripherals
-- The RTL8139 driver frequently gives rx error.
-- Support for RTL8129 network controller. (Why is the support removed from
- rtl8139.c driver?)
-
-(C) Copyright 2004
-Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <w83c553f.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*flash command address offsets*/
-
-#define ADDR0 (0xAAA)
-#define ADDR1 (0x555)
-#define ADDR3 (0x001)
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
- __attribute__ ((const));
-
-typedef struct {
- FLASH_WORD_SIZE extval;
- unsigned short intval;
-} map_entry;
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-{
- static const map_entry mfct_map[] = {
- {(FLASH_WORD_SIZE) AMD_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
- {(FLASH_WORD_SIZE) FUJ_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
- {(FLASH_WORD_SIZE) STM_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
- {(FLASH_WORD_SIZE) MT_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
- {(FLASH_WORD_SIZE) INTEL_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
- {(FLASH_WORD_SIZE) INTEL_ALT_MANU,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
- };
-
- static const map_entry chip_map[] = {
- {AMD_ID_F040B, FLASH_AM040},
- {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
- };
-
- const map_entry *p;
- unsigned long result = FLASH_UNKNOWN;
-
- /* find chip id */
- for (p = &chip_map[0];
- p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
- if (p->extval == chip) {
- result = FLASH_VENDMASK | p->intval;
- break;
- }
-
- /* find vendor id */
- for (p = &mfct_map[0];
- p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
- if (p->extval == mfct) {
- result &= ~FLASH_VENDMASK;
- result |= (unsigned long) p->intval << 16;
- break;
- }
-
- return result;
-}
-
-unsigned long flash_init (void)
-{
- unsigned long i;
- unsigned char j;
- static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
-
- pflinfo->flash_id = FLASH_UNKNOWN;
- pflinfo->size = 0;
- pflinfo->sector_count = 0;
- }
-
- /* Enable writes to Hidden Dragon flash */
- {
- register unsigned char temp;
-
- CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
- temp);
- temp &= ~0x20; /* clear BIOSWP bit */
- CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
- temp);
- }
-
- for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
- const unsigned long base_address = flash_banks[i];
- volatile FLASH_WORD_SIZE *const flash =
- (FLASH_WORD_SIZE *) base_address;
-
- flash[0xAAA << (3 * i)] = 0xaa;
- flash[0x555 << (3 * i)] = 0x55;
- flash[0xAAA << (3 * i)] = 0x90;
- __asm__ __volatile__ ("sync");
-
- pflinfo->flash_id =
- flash_id (flash[0x0], flash[0x2 + 14 * i]);
-
- switch (pflinfo->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 8;
- for (j = 0; j < 8; j++) {
- pflinfo->start[j] =
- base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_STM800AB:
- pflinfo->size = 0x00100000;
- pflinfo->sector_count = 19;
- pflinfo->start[0] = base_address;
- pflinfo->start[1] = base_address + 0x4000;
- pflinfo->start[2] = base_address + 0x6000;
- pflinfo->start[3] = base_address + 0x8000;
- for (j = 1; j < 16; j++) {
- pflinfo->start[j + 3] =
- base_address + 0x00010000 * j;
- }
- break;
- default:
- /* The chip used is not listed in flash_id
- TODO: Change this to explicitly detect the flash type
- */
- {
- int sector_addr = base_address;
-
- pflinfo->size = 0x00200000;
- pflinfo->sector_count = 35;
- pflinfo->start[0] = sector_addr;
- sector_addr += 0x4000; /* 16K */
- pflinfo->start[1] = sector_addr;
- sector_addr += 0x2000; /* 8K */
- pflinfo->start[2] = sector_addr;
- sector_addr += 0x2000; /* 8K */
- pflinfo->start[3] = sector_addr;
- sector_addr += 0x8000; /* 32K */
-
- for (j = 4; j < 35; j++) {
- pflinfo->start[j] = sector_addr;
- sector_addr += 0x10000; /* 64K */
- }
- }
- break;
- }
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* reset device to read mode */
- flash[0x0000] = 0xf0;
- __asm__ __volatile__ ("sync");
- }
-
- /* only have 1 bank */
- return flash_info[0].size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if (info->flash_id != FLASH_UNKNOWN) {
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- mfct = "AMD";
- break;
- case FLASH_MAN_FUJ:
- mfct = "FUJITSU";
- break;
- case FLASH_MAN_STM:
- mfct = "STM";
- break;
- case FLASH_MAN_SST:
- mfct = "SST";
- break;
- case FLASH_MAN_BM:
- mfct = "Bright Microelectonics";
- break;
- case FLASH_MAN_INTEL:
- mfct = "Intel";
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- type = "AM29F040B (512K * 8, uniform sector size)";
- break;
- case FLASH_AM400B:
- type = "AM29LV400B (4 Mbit, bottom boot sect)";
- break;
- case FLASH_AM400T:
- type = "AM29LV400T (4 Mbit, top boot sector)";
- break;
- case FLASH_AM800B:
- type = "AM29LV800B (8 Mbit, bottom boot sect)";
- break;
- case FLASH_AM800T:
- type = "AM29LV800T (8 Mbit, top boot sector)";
- break;
- case FLASH_AM160T:
- type = "AM29LV160T (16 Mbit, top boot sector)";
- break;
- case FLASH_AM320B:
- type = "AM29LV320B (32 Mbit, bottom boot sect)";
- break;
- case FLASH_AM320T:
- type = "AM29LV320T (32 Mbit, top boot sector)";
- break;
- case FLASH_STM800AB:
- type = "M29W800AB (8 Mbit, bottom boot sect)";
- break;
- case FLASH_SST800A:
- type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
- break;
- case FLASH_SST160A:
- type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
- break;
- }
- }
-
- printf ("\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct, type, info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++) {
- unsigned long size;
- unsigned int erased;
- unsigned long *flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size = (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for (flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size)
- && erased; flash++)
- erased = *flash == ~0x0UL;
-
- printf ("%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ", info->protect[i] ? "RO" : " ");
- }
-
- puts ("\n");
- return;
-}
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned char sh8b;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *) (info->start[0] +
- ((info->start[sect] -
- info->start[0]) << sh8b));
- if (info->flash_id & FLASH_MAN_SST) {
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- udelay (30000); /* wait 30 ms */
- } else
- addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
- info->
- start[0]) << sh8b));
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
- volatile FLASH_WORD_SIZE *dest2;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int flag;
- int i;
- unsigned char sh8b;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
- info->start[0]);
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i << sh8b] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <netdev.h>
-
-int checkboard (void)
-{
- /*TODO: Check processor type */
-
- puts ( "Board: Hidden Dragon "
-#ifdef CONFIG_MPC8240
- "8240"
-#endif
-#ifdef CONFIG_MPC8245
- "8245"
-#endif
- " ##Test not implemented yet##\n");
- /* TODO: Implement board test */
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_hidden_dragon_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_hidden_dragon_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ispan.o
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Interphase iSPAN Communications Controllers
- * (453x and others). Tested on 4532.
- *
- * Derived from iSPAN 4539 port (iphase4539) by
- * Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/io.h>
-
-/*
- * I/O Ports configuration table
- *
- * If conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
- /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
- /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
- /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
- /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
- /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
- /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
- /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
- /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
- /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
- /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
- /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
- /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
- /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
- /* PC18 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
- /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */
- /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */
- /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */
- /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */
- /* PD5 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-#define PSPAN_ADDR 0xF0020000
-#define EEPROM_REG 0x408
-#define EEPROM_READ_CMD 0xA000
-#define PSPAN_WRITE(a,v) \
- *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
-#define PSPAN_READ(a) \
- *((volatile unsigned long *)(PSPAN_ADDR+(a)))
-
-static int seeprom_read (int addr, uchar * data, int size)
-{
- ulong val, cmd;
- int i;
-
- for (i = 0; i < size; i++) {
-
- cmd = EEPROM_READ_CMD;
- cmd |= ((addr + i) << 24) & 0xff000000;
-
- /* Wait for ACT to authorize write */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
-
- /* Write command */
- PSPAN_WRITE (EEPROM_REG, cmd);
-
- /* Wait for data to be valid */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
- /* Do it twice, first read might be erratic */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
-
- /* Read error */
- if (val & 0x00000040) {
- return -1;
- } else {
- data[i] = (val >> 16) & 0xff;
- }
- }
- return 0;
-}
-
-/***************************************************************
- * We take some basic Hardware Configuration Parameter from the
- * Serial EEPROM conected to the PSpan bridge. We keep it as
- * simple as possible.
- */
-#ifdef DEBUG
-static int hwc_flash_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x40, &byte, sizeof (byte))) {
- switch ((byte >> 2) & 0x3) {
- case 0x1:
- return 0x0400000;
- break;
- case 0x2:
- return 0x0800000;
- break;
- case 0x3:
- return 0x1000000;
- default:
- return 0x0100000;
- }
- }
- return -1;
-}
-
-static int hwc_local_sdram_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x40, &byte, sizeof (byte))) {
- switch ((byte & 0x03)) {
- case 0x1:
- return 0x0800000;
- case 0x2:
- return 0x1000000;
- default:
- return 0; /* not present */
- }
- }
- return -1;
-}
-#endif /* DEBUG */
-
-static int hwc_main_sdram_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x41, &byte, sizeof (byte))) {
- return 0x1000000 << ((byte >> 5) & 0x7);
- }
- return -1;
-}
-
-static int hwc_serial_number (void)
-{
- int sn = -1;
-
- if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
- sn = cpu_to_le32 (sn);
- }
- return sn;
-}
-
-static int hwc_mac_address (char *str)
-{
- char mac[6];
-
- if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
- sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- } else {
- strcpy (str, "ERROR");
- return -1;
- }
- return 0;
-}
-
-static int hwc_manufact_date (char *str)
-{
- uchar byte;
- int value;
-
- if (seeprom_read (0x92, &byte, sizeof (byte)))
- goto out;
- value = byte;
- if (seeprom_read (0x93, &byte, sizeof (byte)))
- goto out;
- value += byte << 8;
- sprintf (str, "%02d/%02d/%04d",
- value & 0x1F, (value >> 5) & 0xF,
- 1980 + ((value >> 9) & 0x1FF));
- return 0;
-
-out:
- strcpy (str, "ERROR");
- return -1;
-}
-
-static int hwc_board_type (char **str)
-{
- ushort id = 0;
-
- if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
- switch (id) {
- case 0x9080:
- *str = "4532-002";
- break;
- case 0x9081:
- *str = "4532-001";
- break;
- case 0x9082:
- *str = "4532-000";
- break;
- default:
- *str = "Unknown";
- }
- } else {
- *str = "Unknown";
- }
-
- return id;
-}
-
-phys_size_t initdram (int board_type)
-{
- long maxsize = hwc_main_sdram_size();
-
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE)
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *base;
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x00000026;
- immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
- immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
- immap->im_siu_conf.sc_lcl_acr = 0x00000000;
- immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
- immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
- immap->im_siu_conf.sc_ltescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* Initialise 60x bus SDRAM */
- base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110);
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_60x_OR;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR;
-
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
- *base = 0xFF;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *base = 0xFF;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
- *base = 0xFF;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
-
- /* Initialise local bus SDRAM */
- base = (uchar *)CONFIG_SYS_LSDRAM_BASE;
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
- memctl->memc_or2 = CONFIG_SYS_LOC_OR;
- memctl->memc_br2 = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR;
-
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
- *base = 0xFF;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *base = 0xFF;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
- *base = 0xFF;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
-
- maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
-
- memctl->memc_or1 |= ~(maxsize - 1);
-
- if (maxsize != hwc_main_sdram_size())
- puts("Oops: memory test has not found all memory!\n");
-#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */
-
- /* Return total RAM size (size of 60x SDRAM) */
- return maxsize;
-}
-
-int checkboard(void)
-{
- char string[32], *id;
-
- hwc_manufact_date(string);
- hwc_board_type(&id);
- printf("Board: Interphase iSPAN %s (#%d %s)\n",
- id, hwc_serial_number(), string);
-#ifdef DEBUG
- printf("Manufacturing date: %s\n", string);
- printf("Serial number : %d\n", hwc_serial_number());
- printf("FLASH size : %d MB\n", hwc_flash_size() >> 20);
- printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20);
- printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20);
- hwc_mac_address(string);
- printf("MAC address : %s\n", string);
-#endif
- return 0;
-}
-
-int misc_init_r(void)
-{
- char *s, str[32];
- int num;
-
- if ((s = getenv("serial#")) == NULL &&
- (num = hwc_serial_number()) != -1) {
- sprintf(str, "%06d", num);
- setenv("serial#", str);
- }
- if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
- setenv("ethaddr", str);
- }
-
- return 0;
-}
extra-y := bootscript.img
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
$(obj)/bootscript.img: $(src)/bootscript
extra-y := bootscript.img
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
$(obj)/bootscript.img: $(src)/bootscript
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = quad100hd.o nand.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#if defined(CONFIG_CMD_NAND)
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-static void quad100hd_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE));
- gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE));
- gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE));
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int quad100hd_nand_ready(struct mtd_info *mtd)
-{
- return gpio_read_in_bit(CONFIG_SYS_NAND_RDY);
-}
-
-/*
- * Main initialization routine
- */
-int board_nand_init(struct nand_chip *nand)
-{
- /* Set address of hardware control function */
- nand->cmd_ctrl = quad100hd_hwcontrol;
- nand->dev_ready = quad100hd_nand_ready;
- nand->ecc.mode = NAND_ECC_SOFT;
- /* 15 us command delay time */
- nand->chip_delay = 20;
-
- /* Return happy */
- return 0;
-}
-#endif /* CONFIG_CMD_NAND */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
- *
- * Based in part on board/icecube/icecube.c from PPCBoot
- * (C) Copyright 2003 Intrinsyc Software
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <environment.h>
-#include <logbuff.h>
-#include <post.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* taken from PPCBoot */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000);
- mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */
- mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
-
- mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-#ifdef DISPLAY_BOARD_INFO
- sys_info_t sysinfo;
-#endif
-
- puts("Board: Quad100hd");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
-#ifdef DISPLAY_BOARD_INFO
- /* taken from ppcboot */
- get_sys_info(&sysinfo);
-
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
- 1000000));
- printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
-#endif
-
- return 0;
-}
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := rattler.o
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Rattler boards family.
- * Tested on Rattler8248.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */
- /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
- /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
- /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
- /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
- /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */
- /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- }
-};
-
-phys_size_t initdram(int board_type)
-{
- long int msize = CONFIG_SYS_SDRAM_SIZE;
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
- uchar c = 0xFF;
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x02;
- immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* Initialise 60x bus SDRAM */
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
- *ramaddr = c;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
- /* Return total 60x bus SDRAM size */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
- return 0;
-}
int board_mmc_init(bd_t *bis)
{
int ret;
-
-#ifdef CONFIG_SDHCI
- /* mmc initializattion for available channels */
- ret = exynos_mmc_init(gd->fdt_blob);
- if (ret)
- debug("mmc init failed\n");
-#endif
#ifdef CONFIG_DWMMC
/* dwmmc initializattion for available channels */
ret = exynos_dwmmc_init(gd->fdt_blob);
debug("dwmmc init failed\n");
#endif
+#ifdef CONFIG_SDHCI
+ /* mmc initializattion for available channels */
+ ret = exynos_mmc_init(gd->fdt_blob);
+ if (ret)
+ debug("mmc init failed\n");
+#endif
return ret;
}
#endif
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
#include <samsung/misc.h>
+#include <usb.h>
+#include <usb_mass_storage.h>
DECLARE_GLOBAL_DATA_PTR;
.regs_otg = S5PC110_OTG_BASE,
.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc110_otg_data);
+}
#endif
#ifdef CONFIG_MISC_INIT_R
obj-y += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
-ifdef CONFIG_OF_CONTROL
obj-y += exynos5-dt.o
-else
-obj-y += smdk5250.o
-endif
endif
#include <i2c.h>
#include <netdev.h>
#include <spi.h>
+#include <asm/gpio.h>
#include <asm/arch/cpu.h>
#include <asm/arch/dwmmc.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/arch/sromc.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
+#include <power/tps65090_pmic.h>
#include <tmu.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#if defined(CONFIG_POWER)
+#ifdef CONFIG_POWER_MAX77686
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+ u32 val;
+ int ret = 0;
+
+ ret = pmic_reg_read(p, reg, &val);
+ if (ret) {
+ debug("%s: PMIC %d register read failed\n", __func__, reg);
+ return -1;
+ }
+ val |= regval;
+ ret = pmic_reg_write(p, reg, val);
+ if (ret) {
+ debug("%s: PMIC %d register write failed\n", __func__, reg);
+ return -1;
+ }
+ return 0;
+}
+
+static int max77686_init(void)
+{
+ struct pmic *p;
+
+ if (pmic_init(I2C_PMIC))
+ return -1;
+
+ p = pmic_get("MAX77686_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+ MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+ return -1;
+
+ /* VDD_MIF */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_BUCK1OUT_1V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK1OUT);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+ MAX77686_BUCK1CTRL_EN))
+ return -1;
+
+ /* VDD_ARM */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_BUCK2DVS1_1_3V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK2DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_BUCK2CTRL_ON))
+ return -1;
+
+ /* VDD_INT */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_BUCK3DVS1_1_0125V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK3DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_G3D */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+ MAX77686_BUCK4DVS1_1_2V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK4DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_LDO2 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_LD02CTRL1_1_5V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO3 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_LD03CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO5 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_LD05CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO10 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_LD10CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ return 0;
+}
+#endif /* CONFIG_POWER_MAX77686 */
+
+int exynos_power_init(void)
+{
+ int ret = 0;
+
+#ifdef CONFIG_POWER_MAX77686
+ ret = max77686_init();
+ if (ret)
+ return ret;
+#endif
+#ifdef CONFIG_POWER_TPS65090
+ /*
+ * The TPS65090 may not be in the device tree. If so, it is not
+ * an error.
+ */
+ ret = tps65090_init();
+ if (ret == 0 || ret == -ENODEV)
+ return 0;
+#endif
+
+ return ret;
+}
+#endif /* CONFIG_POWER */
+
#ifdef CONFIG_LCD
+static int board_dp_bridge_setup(void)
+{
+ const int max_tries = 10;
+ int num_tries, node;
+
+ /*
+ * TODO(sjg): Use device tree for GPIOs when exynos GPIO
+ * numbering patch is in mainline.
+ */
+ debug("%s\n", __func__);
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460);
+ if (node < 0) {
+ debug("%s: No node for DP bridge in device tree\n", __func__);
+ return -ENODEV;
+ }
+
+ /* Setup the GPIOs */
+
+ /* PD is ACTIVE_LOW, and initially de-asserted */
+ gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_Y25, 1);
+
+ /* Reset is ACTIVE_LOW */
+ gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_X15, 0);
+
+ udelay(10);
+ gpio_set_value(EXYNOS5_GPIO_X15, 1);
+
+ gpio_direction_input(EXYNOS5_GPIO_X07);
+
+ /*
+ * We need to wait for 90ms after bringing up the bridge since there
+ * is a phantom "high" on the HPD chip during its bootup. The phantom
+ * high comes within 7ms of de-asserting PD and persists for at least
+ * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
+ * phantom high makes it hard for us to know when the NXP chip is up.
+ */
+ mdelay(90);
+
+ for (num_tries = 0; num_tries < max_tries; num_tries++) {
+ /* Check HPD. If it's high, we're all good. */
+ if (gpio_get_value(EXYNOS5_GPIO_X07))
+ return 0;
+
+ debug("%s: eDP bridge failed to come up; try %d of %d\n",
+ __func__, num_tries, max_tries);
+ }
+
+ /* Immediately go into bridge reset if the hp line is not high */
+ return -ENODEV;
+}
+
void exynos_cfg_lcd_gpio(void)
{
/* For Backlight */
{
set_dp_phy_ctrl(onoff);
}
+
+void exynos_backlight_on(unsigned int on)
+{
+ debug("%s(%u)\n", __func__, on);
+
+ if (!on)
+ return;
+
+#ifdef CONFIG_POWER_TPS65090
+ int ret;
+
+ ret = tps65090_fet_enable(1); /* Enable FET1, backlight */
+ if (ret)
+ return;
+
+ /* T5 in the LCD timing spec (defined as > 10ms) */
+ mdelay(10);
+
+ /* board_dp_backlight_pwm */
+ gpio_direction_output(EXYNOS5_GPIO_B20, 1);
+
+ /* T6 in the LCD timing spec (defined as > 10ms) */
+ mdelay(10);
+
+ /* board_dp_backlight_en */
+ gpio_direction_output(EXYNOS5_GPIO_X30, 1);
+#endif
+}
+
+void exynos_lcd_power_on(void)
+{
+ int ret;
+
+ debug("%s\n", __func__);
+
+#ifdef CONFIG_POWER_TPS65090
+ /* board_dp_lcd_vdd */
+ tps65090_fet_enable(6); /* Enable FET6, lcd panel */
+#endif
+
+ ret = board_dp_bridge_setup();
+ if (ret && ret != -ENODEV)
+ printf("LCD bridge failed to enable: %d\n", ret);
+}
+
#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <cros_ec.h>
-#include <fdtdec.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <i2c.h>
-#include <lcd.h>
-#include <netdev.h>
-#include <spi.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dwmmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/power.h>
-#include <asm/arch/sromc.h>
-#include <asm/arch/dp_info.h>
-#include <power/pmic.h>
-#include <power/max77686_pmic.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SOUND_MAX98095
-static void board_enable_audio_codec(void)
-{
- /* Enable MAX98095 Codec */
- gpio_direction_output(EXYNOS5_GPIO_X17, 1);
- gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
-}
-#endif
-
-int exynos_init(void)
-{
-#ifdef CONFIG_SOUND_MAX98095
- board_enable_audio_codec();
-#endif
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SMC911X
- u32 smc_bw_conf, smc_bc_conf;
- struct fdt_sromc config;
- fdt_addr_t base_addr;
-
- /* Non-FDT configuration - bank number and timing parameters*/
- config.bank = CONFIG_ENV_SROM_BANK;
- config.width = 2;
-
- config.timing[FDT_SROM_TACS] = 0x01;
- config.timing[FDT_SROM_TCOS] = 0x01;
- config.timing[FDT_SROM_TACC] = 0x06;
- config.timing[FDT_SROM_TCOH] = 0x01;
- config.timing[FDT_SROM_TAH] = 0x0C;
- config.timing[FDT_SROM_TACP] = 0x09;
- config.timing[FDT_SROM_PMC] = 0x01;
- base_addr = CONFIG_SMC911X_BASE;
-
- /* Ethernet needs data bus width of 16 bits */
- if (config.width != 2) {
- debug("%s: Unsupported bus width %d\n", __func__,
- config.width);
- return -1;
- }
- smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
- | SROMC_BYTE_ENABLE(config.bank);
-
- smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
- SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
- SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
- SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
- SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
- SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
- SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
-
- /* Select and configure the SROMC bank */
- exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
- s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
- return smc911x_initialize(0, base_addr);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- printf("\nBoard: SMDK5250\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- int err, ret = 0, index, bus_width;
- u32 base;
-
- err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
- if (err)
- debug("SDMMC0 not configured\n");
- ret |= err;
-
- /*EMMC: dwmmc Channel-0 with 8 bit bus width */
- index = 0;
- base = samsung_get_base_mmc() + (0x10000 * index);
- bus_width = 8;
- err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
- if (err)
- debug("dwmmc Channel-0 init failed\n");
- ret |= err;
-
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
- if (err)
- debug("SDMMC2 not configured\n");
- ret |= err;
-
- /*SD: dwmmc Channel-2 with 4 bit bus width */
- index = 2;
- base = samsung_get_base_mmc() + (0x10000 * index);
- bus_width = 4;
- err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
- if (err)
- debug("dwmmc Channel-2 init failed\n");
- ret |= err;
-
- return ret;
-}
-#endif
-
-void board_i2c_init(const void *blob)
-{
- int i;
-
- for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
- exynos_pinmux_config((PERIPH_ID_I2C0 + i),
- PINMUX_FLAG_NONE);
- }
-}
-
-#if defined(CONFIG_POWER)
-#ifdef CONFIG_POWER_MAX77686
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
- u32 val;
- int ret = 0;
-
- ret = pmic_reg_read(p, reg, &val);
- if (ret) {
- debug("%s: PMIC %d register read failed\n", __func__, reg);
- return -1;
- }
- val |= regval;
- ret = pmic_reg_write(p, reg, val);
- if (ret) {
- debug("%s: PMIC %d register write failed\n", __func__, reg);
- return -1;
- }
- return 0;
-}
-
-static int max77686_init(void)
-{
- struct pmic *p;
-
- if (pmic_init(I2C_PMIC))
- return -1;
-
- p = pmic_get("MAX77686_PMIC");
- if (!p)
- return -ENODEV;
-
- if (pmic_probe(p))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
- MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
- return -1;
-
- /* VDD_MIF */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_BUCK1OUT_1V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK1OUT);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
- MAX77686_BUCK1CTRL_EN))
- return -1;
-
- /* VDD_ARM */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_BUCK2DVS1_1_3V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK2DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_BUCK2CTRL_ON))
- return -1;
-
- /* VDD_INT */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_BUCK3DVS1_1_0125V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK3DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_G3D */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
- MAX77686_BUCK4DVS1_1_2V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK4DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_LDO2 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_LD02CTRL1_1_5V | EN_LDO))
- return -1;
-
- /* VDD_LDO3 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_LD03CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO5 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_LD05CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO10 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_LD10CTRL1_1_8V | EN_LDO))
- return -1;
-
- return 0;
-}
-#endif /* CONFIG_POWER_MAX77686 */
-
-int exynos_power_init(void)
-{
- int ret = 0;
-
-#ifdef CONFIG_POWER_MAX77686
- ret = max77686_init();
-#endif
- return ret;
-}
-#endif /* CONFIG_POWER */
-
-#ifdef CONFIG_LCD
-void exynos_cfg_lcd_gpio(void)
-{
-
- /* For Backlight */
- gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5_GPIO_B20, 1);
-
- /* LCD power on */
- gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5_GPIO_X15, 1);
-
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
-}
-
-void exynos_set_dp_phy(unsigned int onoff)
-{
- set_dp_phy_ctrl(onoff);
-}
-
-vidinfo_t panel_info = {
- .vl_freq = 60,
- .vl_col = 2560,
- .vl_row = 1600,
- .vl_width = 2560,
- .vl_height = 1600,
- .vl_clkp = CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
-
- /* wDP panel timing infomation */
- .vl_hspw = 32,
- .vl_hbpd = 80,
- .vl_hfpd = 48,
-
- .vl_vspw = 6,
- .vl_vbpd = 37,
- .vl_vfpd = 3,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay = 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .dp_enabled = 1,
-};
-
-static struct edp_device_info edp_info = {
- .disp_info = {
- .h_res = 2560,
- .h_sync_width = 32,
- .h_back_porch = 80,
- .h_front_porch = 48,
- .v_res = 1600,
- .v_sync_width = 6,
- .v_back_porch = 37,
- .v_front_porch = 3,
- .v_sync_rate = 60,
- },
- .lt_info = {
- .lt_status = DP_LT_NONE,
- },
- .video_info = {
- .master_mode = 0,
- .bist_mode = DP_DISABLE,
- .bist_pattern = NO_PATTERN,
- .h_sync_polarity = 0,
- .v_sync_polarity = 0,
- .interlaced = 0,
- .color_space = COLOR_RGB,
- .dynamic_range = VESA,
- .ycbcr_coeff = COLOR_YCBCR601,
- .color_depth = COLOR_8,
- },
-};
-
-static struct exynos_dp_platform_data dp_platform_data = {
- .edp_dev_info = &edp_info,
-};
-
-void init_panel_info(vidinfo_t *vid)
-{
- vid->rgb_mode = MODE_RGB_P;
- exynos_set_dp_platform_data(&dp_platform_data);
-}
-#endif
#ifdef CONFIG_LCD
void cfg_lcd_gpio(void)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-
/* For Backlight */
gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := simpc8313.o sdram.o
+++ /dev/null
-Sheldon Instruments SIMPC8313 Board
------------------------------------------
-
-1. Board Switches and Jumpers
-
- S2 is used to set CFG_RESET_SOURCE.
-
- To boot the image in Large page NAND flash, use these DIP
- switch settings for S2:
-
- +----------+ ON
- | * * **** |
- | * * |
- +----------+
- 12345678
-
- To boot the image in Small page NAND flash, use these DIP
- switch settings for S2:
-
- +----------+ ON
- | *** **** |
- | * |
- +----------+
- 12345678
- (where the '*' indicates the position of the tab of the switch.)
-
-2. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x1fff_ffff DDR 512M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xe200_0000 0xe20f_ffff PCI IO 16M
- 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K
- or
- 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K
- 0xff00_0000 0xff00_7fff FPGA (CS1) 1M
-
-3. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make SIMPC8313_LP_config
- (or make SIMPC8313_SP_config, depending on the page size
- of your NAND flash)
- make
-
-4. Downloading and Flashing Images
-
-4.1 Reflash U-boot Image using U-boot
-
- =>run update_uboot
-
- You may want to try
- =>tftp $loadaddr $uboot
- first, to make sure that the TFTP load will succeed before it
- goes ahead and wipes out your current firmware. And of course,
- if the new u-boot doesn't boot, you can plug the board into
- your PCI slot and with the supplied driver and sample app
- you can reburn a working u-boot.
-
-4.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, fdtfile, and bootfile).
-
- =>tftp $loadaddr uImage
- =>nand write $loadaddr kernel $filesize
- =>tftp $loadaddr $fdtfile
- =>nand write $loadaddr 7e0000 1800
-
- =>boot
-
-5 Notes
-
- The console baudrate for SIMPC8313 is 115200bps.
+++ /dev/null
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * Author: Ron Madrid <info@sheldoninst.com>
- *
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/bitops.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static long fixed_sdram(void);
-
-#if defined(CONFIG_NAND_SPL)
-void si_wait_i2c(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-
- while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
- ;
-
- __raw_writeb(0x00, &im->i2c[0].sr);
-
- sync();
-
- return;
-}
-
-void si_read_i2c(u32 lbyte, int count, u8 *buffer)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 i;
- u8 chip = 0x50 << 1; /* boot sequencer I2C */
- u32 ubyte = (lbyte & 0xff00) >> 8;
-
- lbyte &= 0xff;
-
- /*
- * Set up controller
- */
- __raw_writeb(0x3f, &im->i2c[0].fdr);
- __raw_writeb(0x00, &im->i2c[0].adr);
- __raw_writeb(0x00, &im->i2c[0].sr);
- __raw_writeb(0x00, &im->i2c[0].dr);
-
- while (__raw_readb(&im->i2c[0].sr) & 0x20)
- ;
-
- /*
- * Writing address to device
- */
- __raw_writeb(0xb0, &im->i2c[0].cr);
- sync();
- __raw_writeb(chip, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(0xb0, &im->i2c[0].cr);
- sync();
- __raw_writeb(ubyte, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(lbyte, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(0xb4, &im->i2c[0].cr);
- sync();
- __raw_writeb(chip + 1, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(0xa0, &im->i2c[0].cr);
- sync();
-
- /*
- * Dummy read
- */
- __raw_readb(&im->i2c[0].dr);
-
- si_wait_i2c();
-
- /*
- * Read actual data
- */
- for (i = 0; i < count; i++)
- {
- if (i == (count - 2)) /* Reached next to last byte, No ACK */
- __raw_writeb(0xa8, &im->i2c[0].cr);
- if (i == (count - 1)) /* Reached last byte, STOP */
- __raw_writeb(0x88, &im->i2c[0].cr);
-
- /* Read byte of data */
- buffer[i] = __raw_readb(&im->i2c[0].dr);
-
- if (i == (count - 1))
- break;
- si_wait_i2c();
- }
-
- return;
-}
-#endif /* CONFIG_NAND_SPL */
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &im->im_lbc;
- u32 msize;
-
- if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
-
- msize = fixed_sdram();
-
- /* Local Bus setup lbcr and mrtpr */
- __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
- __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
- sync();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- * fixed sdram init -- reads values from boot sequencer I2C
- ************************************************************************/
-static long fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msizelog2, msize = 1;
-#if defined(CONFIG_NAND_SPL)
- u32 i;
- const u8 bytecount = 135;
- u8 buffer[bytecount];
- u32 addr, data;
-
- si_read_i2c(0, bytecount, buffer);
-
- for (i = 18; i < bytecount; i += 7){
- addr = (u32)buffer[i];
- addr <<= 8;
- addr |= (u32)buffer[i + 1];
- addr <<= 2;
- data = (u32)buffer[i + 2];
- data <<= 8;
- data |= (u32)buffer[i + 3];
- data <<= 8;
- data |= (u32)buffer[i + 4];
- data <<= 8;
- data |= (u32)buffer[i + 5];
-
- __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
- }
-
- sync();
-
- /* enable DDR controller */
- __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
-#endif /* (CONFIG_NAND_SPL) */
-
- msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
- msize <<= (msizelog2 - 20);
-
- return msize;
-}
+++ /dev/null
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * Author: Ron Madrid <info@sheldoninst.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <libfdt.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_NAND_SPL
-int checkboard(void)
-{
- puts("Board: Sheldon Instruments SIMPC8313\n");
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- */
-int misc_init_r(void)
-{
- int rc = 0;
- immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- fsl_lbc_t *lbus = &immap->im_lbc;
- u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
-
- /* UPM Table Configuration Code */
- static uint UPMATable[] = {
- /* Read Single-Beat (RSS) */
- 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Read Burst (RBS) */
- 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
- 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Write Single-Beat (WSS) */
- 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Write Burst (WBS) */
- 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
- 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
- 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Refresh Timer (RTS) */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Exception Condition (EXS) */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
- };
-
- upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
-
- /* Set LUPWAIT to be active low and enabled */
- out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
-
- return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-}
-#endif
-#else /* CONFIG_NAND_SPL */
-void board_init_f(ulong bootflag)
-{
- NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
- puts("NAND boot... ");
- init_timebase();
- initdram(0);
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (gd->flags & GD_FLG_SILENT)
- return;
-
- if (c == '\n')
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "board.h"
+#include <power/tps65218.h>
#include <miiphy.h>
#include <cpsw.h>
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define NUM_OPPS 6
const struct dpll_params *get_dpll_ddr_params(void)
{
- struct am43xx_board_id header;
-
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
if (board_is_eposevm())
return &epos_evm_dpll_ddr;
else if (board_is_gpevm())
static int get_opp_offset(int max_off, int min_off)
{
struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
- int opp = readl(&ctrl->dev_attr), offset, i;
+ int opp, offset, i;
+
+ /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
+ opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
for (i = max_off; i >= min_off; i--) {
offset = opp & (1 << i);
return &dpll_per[ind];
}
+void scale_vcores(void)
+{
+ const struct dpll_params *mpu_params;
+ int mpu_vdd;
+ struct am43xx_board_id header;
+
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ /* Get the frequency */
+ mpu_params = get_dpll_mpu_params();
+
+ if (i2c_probe(TPS65218_CHIP_PM))
+ return;
+
+ if (mpu_params->m == 1000) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+ } else if (mpu_params->m == 600) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+ } else {
+ puts("Unknown MPU clock, not scaling\n");
+ return;
+ }
+
+ /* Set DCDC1 (CORE) voltage to 1.1V */
+ if (tps65218_voltage_update(TPS65218_DCDC1,
+ TPS65218_DCDC_VOLT_SEL_1100MV)) {
+ puts("tps65218_voltage_update failure\n");
+ return;
+ }
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+ puts("tps65218_voltage_update failure\n");
+ return;
+ }
+}
+
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := zpc1900.o
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <miiphy.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-void *nvram_read(void *dest, long src, size_t count)
-{
- return memcpy(dest, (const void *)src, count);
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
- vu_char *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555);
- vu_char *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA);
- vu_char *d = (vu_char *)dest;
- const uchar *s = (const uchar *)src;
-
- /* Unprotect the EEPROM */
- *p1 = 0xAA;
- *p2 = 0x55;
- *p1 = 0x80;
- *p1 = 0xAA;
- *p2 = 0x55;
- *p1 = 0x20;
- udelay(10000);
-
- /* Write the data to the EEPROM */
- while (count--) {
- *d++ = *s++;
- while (*(d - 1) != *(s - 1))
- /* wait */;
- }
-
- /* Protect the EEPROM */
- *p1 = 0xAA;
- *p2 = 0x55;
- *p1 = 0xA0;
- udelay(10000);
-}
-#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */
-
-phys_size_t initdram(int board_type)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- vu_char *ramaddr;
- uchar c = 0xFF;
- long int msize = CONFIG_SYS_SDRAM_SIZE;
- int i;
-
- if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
- immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
- immap->im_siu_conf.sc_siumcr =
- (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
- | SIUMCR_LBPC01;
- }
-
-#ifndef CONFIG_SYS_RAMBOOT
- immap->im_siu_conf.sc_ppc_acr = 0x03;
- immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifdef CONFIG_SYS_LSDRAM_BASE
- /*
- Initialise local bus SDRAM only if the pins
- are configured as local bus pins and not as PCI.
- */
- if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
- memctl->memc_or4 = CONFIG_SYS_LSDRAM_OR;
- memctl->memc_br4 = CONFIG_SYS_LSDRAM_BR;
- ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN;
- }
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
- /* Initialise 60x bus SDRAM */
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or2 = CONFIG_SYS_PSDRAM_OR;
- memctl->memc_br2 = CONFIG_SYS_PSDRAM_BR;
- /*
- * The mode data for Mode Register Write command must appear on
- * the address lines during a mode-set cycle. It is driven by
- * the memory controller, in single PowerQUICC II mode,
- * according to PSDMR[CL] and PSDMR[BL] fields. In
- * 60x-compatible mode, software must drive the correct value on
- * the address lines. BL=0 because for 64-bit port size burst
- * length must be 4.
- */
- ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE |
- ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN; /* Refresh enable */
- *ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /* Return total 60x bus SDRAM size */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
- return 0;
-}
Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de>
Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de>
Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org>
-Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org>
Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com>
Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de>
Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de>
-Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de>
Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 am33xx ti am43xx am43xx_evm_qspiboot am43xx_evm:SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
Active arm armv7 am33xx ti ti816x ti816x_evm - -
Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
Active arm armv7 mx6 embest mx6boards marsboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH Eric Bénard <eric@eukrea.com>
Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric@eukrea.com>
Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
Active arm pxa - - - xaeniax - -
Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
-Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
-Active avr32 at32ap at32ap700x miromico - hammerhead -
Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
+Active avr32 at32ap at32ap700x miromico - hammerhead - Alex Raimondi <alex.raimondi@miromico.ch>
Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
+Active blackfin blackfin - - - bf561-acvilon - Valentin Yakovenkov <yakovenkov@niistt.ru>
Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
-Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>
Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - -
Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
Active powerpc mpc5xxx - - bc3450 BC3450 - -
-Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
-Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
Active powerpc mpc824x - - mvblue MVBLUE - -
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
Active powerpc mpc8260 - - - ep82xxm - -
Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
-Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu87 CPU87 - -
Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
-Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
-Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
Active powerpc mpc83xx - tqc tqm834x TQM834x - -
Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - socrates socrates - -
-Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
-Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
-Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
-Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT York Sun <yorksun@freescale.com>
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT -
Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
-Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
Active powerpc mpc85xx - xes - xpedite520x - -
Active powerpc mpc85xx - xes - xpedite537x - -
Active powerpc mpc85xx - xes - xpedite550x - -
Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
-Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc86xx - xes - xpedite517x - -
Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - - quantum - -
Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - - spc1920 - -
-Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
Active powerpc mpc8xx - - - v37 - -
Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
Active powerpc mpc8xx - - fads MPC86xADS - -
Active powerpc mpc8xx - - fads MPC885ADS - -
-Active powerpc mpc8xx - - flagadm FLAGADM - Kári DavÃðsson <kd@flaga.is>
-Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
-Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active powerpc mpc8xx - snmc qs850 QS823 - -
Active powerpc mpc8xx - snmc qs850 QS850 - -
Active powerpc mpc8xx - snmc qs860t QS860T - -
-Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx NSCU - -
Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de>
Active powerpc ppc4xx - - - sbc405 - -
Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
Active sparc leon3 - gaisler - gr_xc3s_1500 - -
Active sparc leon3 - gaisler - grsim - -
Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass <sjg@chromium.org>
+# The following were moved to "Orphan" in June, 2014
+Orphan arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
+Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
+Orphan arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
+Orphan avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+Orphan blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
+Orphan m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
+Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
+Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
+Orphan powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
+Orphan powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+Orphan powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
+Orphan powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
+Orphan powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
+Orphan powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
+Orphan powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
+Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
+Orphan powerpc mpc8xx - - flagadm FLAGADM - Kári DavÃðsson <kd@flaga.is>
+Orphan powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
+Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
+Orphan powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
+Orphan powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
# The following were moved to "Orphan" in April, 2014
Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
-Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
-Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
-Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <travis.sawyer@sandburst.com>
free_pipe_list(ctx.list_head,0);
}
b_free(&temp);
- } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP)); /* loop on syntax errors, return on EOF */
+ /* loop on syntax errors, return on EOF */
+ } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
+ (inp->peek != static_peek || b_peek(inp)));
#ifndef __U_BOOT__
return 0;
#else
++next;
}
if (rcode == 0 && *line)
- rcode = (cli_simple_run_command(line, 0) >= 0);
+ rcode = (cli_simple_run_command(line, 0) < 0);
return rcode;
}
/* get image parameters */
switch (genimg_get_format(os_hdr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
images.os.type = image_get_type(os_hdr);
images.os.comp = image_get_comp(os_hdr);
images.os.end = image_get_image_end(os_hdr);
images.os.load = image_get_load(os_hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
if (fit_image_get_type(images.fit_hdr_os,
return 0;
}
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
/**
* image_get_kernel - verify legacy format kernel image
* @img_addr: in RAM address of the legacy format image to be verified
}
return hdr;
}
+#endif
/**
* boot_get_kernel - find kernel image
char * const argv[], bootm_headers_t *images, ulong *os_data,
ulong *os_len)
{
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
image_header_t *hdr;
+#endif
ulong img_addr;
const void *buf;
#if defined(CONFIG_FIT)
*os_data = *os_len = 0;
buf = map_sysmem(img_addr, 0);
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
printf("## Booting kernel from Legacy Image at %08lx ...\n",
img_addr);
images->legacy_hdr_valid = 1;
bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
os_noffset = fit_image_load(images, FIT_KERNEL_PROP,
printf("\n## Checking Image at %08lx ...\n", addr);
switch (genimg_get_format(hdr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
puts(" Legacy image found\n");
if (!image_check_magic(hdr)) {
}
puts("OK\n");
return 0;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
puts(" FIT image found\n");
goto next_sector;
switch (genimg_get_format(hdr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
if (!image_check_hcrc(hdr))
goto next_sector;
puts("OK\n");
}
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
if (!fit_check_format(hdr))
}
switch (genimg_get_format(buffer)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
header = (const image_header_t *)buffer;
len = image_get_image_size(header);
nand_imls_legacyimage(nand, nand_dev, off, len);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
len = fit_get_size(buffer);
ulong addr = CONFIG_SYS_LOAD_ADDR;
ulong cnt;
disk_partition_t info;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
image_header_t *hdr;
+#endif
block_dev_desc_t *dev_desc;
#if defined(CONFIG_FIT)
bootstage_mark(BOOTSTAGE_ID_IDE_PART_READ);
switch (genimg_get_format((void *) addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *) addr;
cnt = image_get_image_size(hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = (const void *) addr;
#include <s_record.h>
#include <net.h>
#include <ata.h>
+#include <asm/io.h>
#include <part.h>
#include <fat.h>
#include <fs.h>
disk_partition_t info;
int dev = 0;
int part = 1;
+ void *buf;
if (argc < 5)
return cmd_usage(cmdtp);
addr = simple_strtoul(argv[3], NULL, 16);
count = simple_strtoul(argv[5], NULL, 16);
- size = file_fat_write(argv[4], (void *)addr, count);
+ buf = map_sysmem(addr, count);
+ size = file_fat_write(argv[4], buf, count);
+ unmap_sysmem(buf);
if (size == -1) {
printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
argv[4], argv[1], dev, part);
FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
FDC_COMMAND_STRUCT *pCMD = &cmd;
unsigned long addr,imsize;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
image_header_t *hdr; /* used for fdc boot */
+#endif
unsigned char boot_drive;
int i,nrofblk;
#if defined(CONFIG_FIT)
}
switch (genimg_get_format ((void *)addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *)addr;
image_print_contents (hdr);
imsize = image_get_image_size (hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = (const void *)addr;
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
switch (genimg_get_format(fpga_data)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
{
image_header_t *hdr =
BIT_FULL);
}
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
{
l = simple_strtoul(s, NULL, 16);
}
- return (l & ((1 << (w * 8)) - 1));
+ return l & ((1UL << (w * 8)) - 1);
}
static char * evalstr(char *s)
int r;
char *s;
size_t cnt;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
image_header_t *hdr;
+#endif
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
#endif
bootstage_mark(BOOTSTAGE_ID_NAND_HDR_READ);
switch (genimg_get_format ((void *)addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *)addr;
cnt = image_get_image_size (hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = (const void *)addr;
source (ulong addr, const char *fit_uname)
{
ulong len;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *hdr;
+#endif
ulong *data;
int verify;
void *buf;
buf = map_sysmem(addr, 0);
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = buf;
*/
while (*data++);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
if (fit_uname == NULL) {
{
ulong addr = load_addr;
ulong dest = 0;
- ulong data, len, count;
+ ulong data, len;
int verify;
int part = 0;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+ ulong count;
image_header_t *hdr = NULL;
+#endif
#if defined(CONFIG_FIT)
const char *uname = NULL;
const void* fit_hdr;
}
switch (genimg_get_format((void *)addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
printf("## Copying part %d from legacy image "
image_multi_getimg(hdr, part, &data, &len);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
if (uname == NULL) {
}
break;
#endif
-#if defined(CONFIG_BZIP2)
+#if defined(CONFIG_BZIP2) && defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IH_COMP_BZIP2:
{
int i;
#ifdef CONFIG_ENV_OFFSET_REDUND
int env_init(void)
{
+#ifdef ENV_IS_EMBEDDED
ulong len, crc[2], crc_tmp;
unsigned int off, off_env[2];
uchar buf[64], flags[2];
gd->env_addr = off_env[1] + offsetof(env_t, data);
else if (gd->env_valid == 1)
gd->env_addr = off_env[0] + offsetof(env_t, data);
-
+#else
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+#endif
return 0;
}
#else
int env_init(void)
{
+#ifdef ENV_IS_EMBEDDED
ulong crc, len, new;
unsigned off;
uchar buf[64];
gd->env_addr = 0;
gd->env_valid = 0;
}
-
+#else
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+#endif
return 0;
}
#endif
* a seperate section. Note that ENV_CRC is only defined when building
* U-Boot itself.
*/
-#if (defined(CONFIG_SYS_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \
+#if defined(CONFIG_SYS_USE_PPCENV) && \
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
/* XXX - This only works with GNU C */
# define __PPCENV__ __attribute__ ((section(".ppcenv")))
puts(" - must RESET the board to recover.\n");
}
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
static const image_header_t *image_get_fdt(ulong fdt_addr)
{
const image_header_t *fdt_hdr = map_sysmem(fdt_addr, 0);
}
return fdt_hdr;
}
+#endif
/**
* boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
{
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *fdt_hdr;
+ ulong load, load_end;
+ ulong image_start, image_data, image_end;
+#endif
ulong fdt_addr;
char *fdt_blob = NULL;
- ulong image_start, image_data, image_end;
- ulong load, load_end;
void *buf;
#if defined(CONFIG_FIT)
const char *fit_uname_config = images->fit_uname_cfg;
*/
buf = map_sysmem(fdt_addr, 0);
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
/* verify fdt_addr points to a valid image header */
printf("## Flattened Device Tree from Legacy Image at %08lx\n",
fdt_addr = load;
break;
+#endif
case IMAGE_FORMAT_FIT:
/*
* This case will catch both: new uImage format
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
int verify);
+#endif
#else
#include "mkimage.h"
#include <u-boot/md5.h>
#ifndef USE_HOSTCC
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
/**
* image_get_ramdisk - get and verify ramdisk image
* @rd_addr: ramdisk image start address
return rd_hdr;
}
+#endif
#endif /* !USE_HOSTCC */
/*****************************************************************************/
*/
int genimg_get_format(const void *img_addr)
{
- ulong format = IMAGE_FORMAT_INVALID;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *hdr;
hdr = (const image_header_t *)img_addr;
if (image_check_magic(hdr))
- format = IMAGE_FORMAT_LEGACY;
+ return IMAGE_FORMAT_LEGACY;
+#endif
#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
- else if (fdt_check_header(img_addr) == 0)
- format = IMAGE_FORMAT_FIT;
+ if (fdt_check_header(img_addr) == 0)
+ return IMAGE_FORMAT_FIT;
#endif
#ifdef CONFIG_ANDROID_BOOT_IMAGE
- else if (android_image_check_header(img_addr) == 0)
- format = IMAGE_FORMAT_ANDROID;
+ if (android_image_check_header(img_addr) == 0)
+ return IMAGE_FORMAT_ANDROID;
#endif
- return format;
+ return IMAGE_FORMAT_INVALID;
}
/**
/* get data size */
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
d_size = image_get_data_size(buf);
debug(" Legacy format image found at 0x%08lx, "
"size 0x%08lx\n",
ram_addr, d_size);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
d_size = fit_get_size(buf) - h_size;
{
ulong rd_addr, rd_load;
ulong rd_data, rd_len;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *rd_hdr;
+#endif
void *buf;
#ifdef CONFIG_SUPPORT_RAW_INITRD
char *end;
*/
buf = map_sysmem(rd_addr, 0);
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
printf("## Loading init Ramdisk from Legacy "
"Image at %08lx ...\n", rd_addr);
rd_len = image_get_data_size(rd_hdr);
rd_load = image_get_load(rd_hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
rd_noffset = fit_image_load(images, FIT_RAMDISK_PROP,
(part_num == which_part) &&
(is_extended(pt->sys_ind) == 0)) {
info->blksz = 512;
- info->start = ext_part_sector + le32_to_int (pt->start4);
- info->size = le32_to_int (pt->size4);
+ info->start = (lbaint_t)(ext_part_sector +
+ le32_to_int(pt->start4));
+ info->size = (lbaint_t)le32_to_int(pt->size4);
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_SATA:
*/
/*
- * Problems with CONFIG_SYS_64BIT_LBA:
- *
- * struct disk_partition.start in include/part.h is sized as ulong.
- * When CONFIG_SYS_64BIT_LBA is activated, lbaint_t changes from ulong to uint64_t.
- * For now, it is cast back to ulong at assignment.
- *
- * This limits the maximum size of addressable storage to < 2 Terra Bytes
+ * NOTE:
+ * when CONFIG_SYS_64BIT_LBA is not defined, lbaint_t is 32 bits; this
+ * limits the maximum size of addressable storage to < 2 Terra Bytes
*/
#include <asm/unaligned.h>
#include <common.h>
static int pmbr_part_valid(struct partition *part);
static int is_pmbr_valid(legacy_mbr * mbr);
-static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba,
- gpt_header * pgpt_head, gpt_entry ** pgpt_pte);
+static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
+ gpt_header *pgpt_head, gpt_entry **pgpt_pte);
static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc,
gpt_header * pgpt_head);
static int is_pte_valid(gpt_entry * pte);
return -1;
}
- /* The ulong casting limits the maximum disk size to 2 TB */
- info->start = (u64)le64_to_cpu(gpt_pte[part - 1].starting_lba);
+ /* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */
+ info->start = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].starting_lba);
/* The ending LBA is inclusive, to calculate size, add 1 to it */
- info->size = ((u64)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1)
+ info->size = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1
- info->start;
info->blksz = dev_desc->blksz;
UUID_STR_FORMAT_GUID);
#endif
- debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__,
+ debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__,
info->start, info->size, info->name);
/* Remember to free pte */
return 0;
}
+int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc,
+ const char *name, disk_partition_t *info)
+{
+ int ret;
+ int i;
+ for (i = 1; i < GPT_ENTRY_NUMBERS; i++) {
+ ret = get_partition_info_efi(dev_desc, i, info);
+ if (ret != 0) {
+ /* no more entries in table */
+ return -1;
+ }
+ if (strcmp(name, (const char *)info->name) == 0) {
+ /* matched */
+ return 0;
+ }
+ }
+ return -2;
+}
+
int test_part_efi(block_dev_desc_t * dev_desc)
{
ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
if (dev_desc->block_write(dev_desc->dev,
- le32_to_cpu(gpt_h->last_usable_lba + 1),
+ (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ + 1,
pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
if (dev_desc->block_write(dev_desc->dev,
- le32_to_cpu(gpt_h->my_lba), 1, gpt_h) != 1)
+ (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
+ gpt_h) != 1)
goto err;
debug("GPT successfully written to block device!\n");
int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
disk_partition_t *partitions, int parts)
{
- u32 offset = (u32)le32_to_cpu(gpt_h->first_usable_lba);
- ulong start;
+ lbaint_t offset = (lbaint_t)le64_to_cpu(gpt_h->first_usable_lba);
+ lbaint_t start;
+ lbaint_t last_usable_lba = (lbaint_t)
+ le64_to_cpu(gpt_h->last_usable_lba);
int i, k;
size_t efiname_len, dosname_len;
#ifdef CONFIG_PARTITION_UUIDS
gpt_e[i].starting_lba = cpu_to_le64(offset);
offset += partitions[i].size;
}
- if (offset >= gpt_h->last_usable_lba) {
+ if (offset >= last_usable_lba) {
printf("Partitions layout exceds disk size\n");
return -1;
}
gpt_e[i].partition_name[k] =
(efi_char16_t)(partitions[i].name[k]);
- debug("%s: name: %s offset[%d]: 0x%x size[%d]: 0x" LBAF "\n",
+ debug("%s: name: %s offset[%d]: 0x" LBAF
+ " size[%d]: 0x" LBAF "\n",
__func__, partitions[i].name, i,
offset, i, partitions[i].size);
}
* Description: returns 1 if valid, 0 on error.
* If valid, returns pointers to PTEs.
*/
-static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba,
- gpt_header * pgpt_head, gpt_entry ** pgpt_pte)
+static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
+ gpt_header *pgpt_head, gpt_entry **pgpt_pte)
{
u32 crc32_backup = 0;
u32 calc_crc32;
- unsigned long long lastlba;
+ u64 lastlba;
if (!dev_desc || !pgpt_head) {
printf("%s: Invalid Argument(s)\n", __func__);
}
/* Read GPT Header from device */
- if (dev_desc->block_read(dev_desc->dev, lba, 1, pgpt_head) != 1) {
+ if (dev_desc->block_read(dev_desc->dev, (lbaint_t)lba, 1, pgpt_head)
+ != 1) {
printf("*** ERROR: Can't read GPT header ***\n");
return 0;
}
}
/* Check the first_usable_lba and last_usable_lba are within the disk. */
- lastlba = (unsigned long long)dev_desc->lba;
+ lastlba = (u64)dev_desc->lba;
if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) {
printf("GPT: first_usable_lba incorrect: %llX > %llX\n",
le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
}
if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) {
printf("GPT: last_usable_lba incorrect: %llX > %llX\n",
- (u64) le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
return 0;
}
/* Read GPT Entries from device */
blk_cnt = BLOCK_CNT(count, dev_desc);
if (dev_desc->block_read (dev_desc->dev,
- le64_to_cpu(pgpt_head->partition_entry_lba),
+ (lbaint_t)le64_to_cpu(pgpt_head->partition_entry_lba),
(lbaint_t) (blk_cnt), pte)
!= blk_cnt) {
To use this feature you will need to get the device tree compiler here:
- git://jdl.com/software/dtc.git
+ git://git.kernel.org/pub/scm/utils/dtc/dtc.git
For example:
- $ git clone git://jdl.com/software/dtc.git
+ $ git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git
$ cd dtc
$ make
$ sudo make install
This is used by SoC platforms which do not have built-in ELM
hardware engine required for BCH ECC correction.
+ CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ Indicates that NAND device has 16-bit wide data-bus. In absence of this
+ config, bus-width of NAND device is assumed to be either 8-bit and later
+ determined by reading ONFI params.
+ Above config is useful when NAND device's bus-width information cannot
+ be determined from on-chip ONFI params, like in following scenarios:
+ - SPL boot does not support reading of ONFI parameters. This is done to
+ keep SPL code foot-print small.
+ - In current U-Boot flow using nand_init(), driver initialization
+ happens in board_nand_init() which is called before any device probe
+ (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
+ not available while configuring controller. So a static CONFIG_NAND_xx
+ is needed to know the device's bus-width in advance.
+ Some drivers using above config are:
+ drivers/mtd/nand/mxc_nand.c
+ drivers/mtd/nand/ndfc.c
+ drivers/mtd/nand/omap_gpmc.c
+
Platform specific options
=========================
8-bit BCH code with
- ecc calculation using GPMC hardware engine,
- error detection using ELM hardware engine.
+ OMAP_ECC_BCH16_CODE_HW
+ 16-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+
+ How to select ECC scheme on OMAP and AMxx platforms ?
+ -----------------------------------------------------
+ Though higher ECC schemes have more capability to detect and correct
+ bit-flips, but still selection of ECC scheme is dependent on following
+ - hardware engines present in SoC.
+ Some legacy OMAP SoC do not have ELM h/w engine thus such
+ SoC cannot support BCHx_HW ECC schemes.
+ - size of OOB/Spare region
+ With higher ECC schemes, more OOB/Spare area is required to
+ store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+ In general following expression can help:
+ NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+ where
+ NAND_OOBSIZE = number of bytes available in
+ OOB/spare area per NAND page.
+ NAND_PAGESIZE = bytes in main-area of NAND page.
+ ECC_BYTES = number of ECC bytes generated to
+ protect 512 bytes of data, which is:
+ 3 for HAM1_xx ecc schemes
+ 7 for BCH4_xx ecc schemes
+ 14 for BCH8_xx ecc schemes
+ 26 for BCH16_xx ecc schemes
+
+ example to check for BCH16 on 2K page NAND
+ NAND_PAGESIZE = 2048
+ NAND_OOBSIZE = 64
+ 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+ Thus BCH16 cannot be supported on 2K page NAND.
+
+ However, for 4K pagesize NAND
+ NAND_PAGESIZE = 4096
+ NAND_OOBSIZE = 64
+ ECC_BYTES = 26
+ 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+ Thus BCH16 can be supported on 4K page NAND.
+
NOTE:
=====
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-lubbock arm pxa - 2014-04-04 Kyle Harris <kharris@nexus-tech.net>
-MOUSSE powerpc mpc824x - 2014-04-04
-rsdproto powerpc mpc8260 - 2014-04-04
-RPXsuper powerpc mpc8260 - 2014-04-04
-RPXClassic powerpc mpc8xx - 2014-04-04
-RPXlite powerpc mpc8xx - 2014-04-04
-genietv powerpc mpc8xx - 2014-04-04
-mbx8xx powerpc mpc8xx - 2014-04-04
-nx823 powerpc mpc8xx - 2014-04-04
+simpc8313 powerpc mpc83xx - 2014-04-28 Ron Madrid <info@sheldoninst.com>
+hidden_dragon powerpc mpc824x 3fe1a854 2014-05-30 Yusdi Santoso <yusdi_santoso@adaptec.com>
+debris powerpc mpc824x 7edb1f7b 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
+kvme080 powerpc mpc824x 2868f862 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
+ep8248 powerpc mpc8260 49ad566d 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+ispan powerpc mpc8260 80bae39a 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+rattler powerpc mpc8260 d0664db4 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+zpc1900 powerpc mpc8260 6f80bb48 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+mpc8260ads powerpc mpc8260 facb6725 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+adder powerpc mpc8xx 373a9788 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+quad100hd powerpc ppc405ep 3569571d 2014-05-30 Gary Jennejohn <gljennjohn@googlemail.com>
+lubbock arm pxa 36bf57b 2014-04-18 Kyle Harris <kharris@nexus-tech.net>
+EVB64260 powerpc mpc824x bb3aef9 2014-04-18
+MOUSSE powerpc mpc824x 03f2ecc 2014-04-18
+rsdproto powerpc mpc8260 8b043e6 2014-04-18
+RPXsuper powerpc mpc8260 0ebf5f5 2014-04-18
+RPXClassic powerpc mpc8xx 4fb3925 2014-04-18
+RPXlite powerpc mpc8xx 4fb3925 2014-04-18
+FADS powerpc mpc8xx aa6e1e4 2014-04-18
+genietv powerpc mpc8xx b8a49bd 2014-04-18
+mbx8xx powerpc mpc8xx d6b11fd 2014-04-18
+nx823 powerpc mpc8xx a146e8b 2014-04-18
idmr m68k mcf52x2 ba650e9b 2014-01-28
M5271EVB m68k mcf52x2 ba650e9b 2014-01-28
dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen <michael@schwingen.org>
-* Exynos 5250 DWC_mobile_storage
+* Exynos DWC_mobile_storage
-The Exynos 5250 provides DWC_mobile_storage interface which supports
+The Exynos provides DWC_mobile_storage interface which supports
. Embedded Multimedia Cards (EMMC-version 4.5)
. Secure Digital memory (SD mem-version 2.0)
. Secure Digital I/O (SDIO-version 3.0)
. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
-The Exynos 5250 DWC_mobile_storage provides four channels.
+The Exynos DWC_mobile_storage provides four channels.
SOC specific and Board specific properties are channel specific.
Required SoC Specific Properties:
- compatible: should be
- - samsung,exynos5250-dwmmc: for exynos5250 platforms
+ - samsung,exynos-dwmmc: for exynos platforms
- reg: physical base address of the controller and length of memory mapped
region.
--- /dev/null
+TPS65090 Frontend PMU with Switchmode Charger
+
+Required Properties:
+-compatible: "ti,tps65090-charger"
+
+Optional Properties:
+-ti,enable-low-current-chrg: Enables charging when a low current is detected
+ while the default logic is to stop charging.
+
+This node is a subnode of the tps65090 PMIC.
+
+Example:
+
+ tps65090-charger {
+ compatible = "ti,tps65090-charger";
+ ti,enable-low-current-chrg;
+ };
--- /dev/null
+TPS65090 regulators
+
+Required properties:
+- compatible: "ti,tps65090"
+- reg: I2C slave address
+- interrupts: the interrupt outputs of the controller
+- regulators: A node that houses a sub-node for each regulator within the
+ device. Each sub-node is identified using the node's name, with valid
+ values listed below. The content of each sub-node is defined by the
+ standard binding for regulators; see regulator.txt.
+ dcdc[1-3], fet[1-7] and ldo[1-2] respectively.
+- vsys[1-3]-supply: The input supply for DCDC[1-3] respectively.
+- infet[1-7]-supply: The input supply for FET[1-7] respectively.
+- vsys-l[1-2]-supply: The input supply for LDO[1-2] respectively.
+
+Optional properties:
+- ti,enable-ext-control: This is applicable for DCDC1, DCDC2 and DCDC3.
+ If DCDCs are externally controlled then this property should be there.
+- "dcdc-ext-control-gpios: This is applicable for DCDC1, DCDC2 and DCDC3.
+ If DCDCs are externally controlled and if it is from GPIO then GPIO
+ number should be provided. If it is externally controlled and no GPIO
+ entry then driver will just configure this rails as external control
+ and will not provide any enable/disable APIs.
+
+Each regulator is defined using the standard binding for regulators.
+
+Example:
+
+ tps65090@48 {
+ compatible = "ti,tps65090";
+ reg = <0x48>;
+ interrupts = <0 88 0x4>;
+
+ vsys1-supply = <&some_reg>;
+ vsys2-supply = <&some_reg>;
+ vsys3-supply = <&some_reg>;
+ infet1-supply = <&some_reg>;
+ infet2-supply = <&some_reg>;
+ infet3-supply = <&some_reg>;
+ infet4-supply = <&some_reg>;
+ infet5-supply = <&some_reg>;
+ infet6-supply = <&some_reg>;
+ infet7-supply = <&some_reg>;
+ vsys_l1-supply = <&some_reg>;
+ vsys_l2-supply = <&some_reg>;
+
+ regulators {
+ dcdc1 {
+ regulator-name = "dcdc1";
+ regulator-boot-on;
+ regulator-always-on;
+ ti,enable-ext-control;
+ dcdc-ext-control-gpios = <&gpio 10 0>;
+ };
+
+ dcdc2 {
+ regulator-name = "dcdc2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3 {
+ regulator-name = "dcdc3";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fet1 {
+ regulator-name = "fet1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fet2 {
+ regulator-name = "fet2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fet3 {
+ regulator-name = "fet3";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fet4 {
+ regulator-name = "fet4";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fet5 {
+ regulator-name = "fet5";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fet6 {
+ regulator-name = "fet6";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fet7 {
+ regulator-name = "fet7";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1 {
+ regulator-name = "ldo1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "ldo2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
(mkimage) is invoked directly. dtc is called from within mkimage and operates
behind the scenes, but needs to be present in the $PATH nevertheless. It is
important that the dtc used has support for binary includes -- refer to
-www.jdl.com for its latest version. mkimage (together with dtc) takes as input
+
+ git://git.kernel.org/pub/scm/utils/dtc/dtc.git
+
+for its latest version. mkimage (together with dtc) takes as input
an image source file, which describes the contents of the image and defines
its various properties used during booting. By convention, image source file
has the ".its" extension, also, the details of its format are given in
CONFIG_FIT_SIGNATURE - enable signing and verfication in FITs
CONFIG_RSA - enable RSA algorithm for signing
+WARNING: When relying on signed FIT images with required signature check
+the legacy image format is default disabled by not defining
+CONFIG_IMAGE_FORMAT_LEGACY
Testing
-------
ddr->debug[2] = 0x00000400;
ddr->debug[4] = 0xff800000;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+ if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
+ ddr->debug[2] |= 0x00000200; /* set bit 22 */
+#endif
+
return check_fsl_memctl_config_regs(ddr);
}
printf("%-3d-%3d: ", 128, 255);
for (i = 128; i <= 255; i++)
- printf("%02x", spd->mod_section.uc[i - 60]);
+ printf("%02x", spd->mod_section.uc[i - 128]);
break;
}
static void dwmci_set_ios(struct mmc *mmc)
{
- struct dwmci_host *host = mmc->priv;
- u32 ctype;
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ u32 ctype, regs;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
dwmci_writel(host, DWMCI_CTYPE, ctype);
+ regs = dwmci_readl(host, DWMCI_UHS_REG);
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ regs |= DWMCI_DDR_MODE;
+ else
+ regs &= DWMCI_DDR_MODE;
+
+ dwmci_writel(host, DWMCI_UHS_REG, regs);
+
if (host->clksel)
host->clksel(host);
}
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include <asm-generic/errno.h>
#define DWMMC_MAX_CH_NUM 4
#define DWMMC_MAX_FREQ 52000000
& DWMCI_DIVRATIO_MASK) + 1;
sclk = get_mmc_clk(host->dev_index);
- return sclk / clk_div;
+ /*
+ * Assume to know divider value.
+ * When clock unit is broken, need to set "host->div"
+ */
+ return sclk / clk_div / (host->div + 1);
}
static void exynos_dwmci_board_init(struct dwmci_host *host)
}
}
-/*
- * This function adds the mmc channel to be registered with mmc core.
- * index - mmc channel number.
- * regbase - register base address of mmc channel specified in 'index'.
- * bus_width - operating bus width of mmc channel specified in 'index'.
- * clksel - value to be written into CLKSEL register in case of FDT.
- * NULL in case od non-FDT.
- */
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
+static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
{
- struct dwmci_host *host = NULL;
unsigned int div;
unsigned long freq, sclk;
- host = malloc(sizeof(struct dwmci_host));
- if (!host) {
- printf("dwmci_host malloc fail!\n");
- return 1;
- }
+
+ if (host->bus_hz)
+ freq = host->bus_hz;
+ else
+ freq = DWMMC_MAX_FREQ;
+
/* request mmc clock vlaue of 52MHz. */
- freq = 52000000;
sclk = get_mmc_clk(index);
div = DIV_ROUND_UP(sclk, freq);
/* set the clock divisor for mmc */
set_mmc_clk(index, div);
host->name = "EXYNOS DWMMC";
- host->ioaddr = (void *)regbase;
- host->buswidth = bus_width;
#ifdef CONFIG_EXYNOS5420
host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
host->board_init = exynos_dwmci_board_init;
- if (clksel) {
- host->clksel_val = clksel;
- } else {
- if (0 == index)
+ if (!host->clksel_val) {
+ if (index == 0)
host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
- if (2 == index)
+ else if (index == 2)
host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
}
+ host->caps = MMC_MODE_DDR_52MHz;
host->clksel = exynos_dwmci_clksel;
host->dev_index = index;
host->get_mmc_clk = exynos_dwmci_get_clk;
return 0;
}
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index - mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ * clksel - value to be written into CLKSEL register in case of FDT.
+ * NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
+{
+ struct dwmci_host *host = NULL;
+
+ host = malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ error("dwmci_host malloc fail!\n");
+ return -ENOMEM;
+ }
+
+ host->ioaddr = (void *)regbase;
+ host->buswidth = bus_width;
+
+ if (clksel)
+ host->clksel_val = clksel;
+
+ return exynos_dwmci_core_init(host, index);
+}
+
#ifdef CONFIG_OF_CONTROL
-int exynos_dwmmc_init(const void *blob)
+static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
+
+static int do_dwmci_init(struct dwmci_host *host)
{
- int index, bus_width;
- int node_list[DWMMC_MAX_CH_NUM];
- int err = 0, dev_id, flag, count, i;
- u32 clksel_val, base, timing[3];
+ int index, flag, err;
- count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
- DWMMC_MAX_CH_NUM);
+ index = host->dev_index;
- for (i = 0; i < count; i++) {
- int node = node_list[i];
+ flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+ err = exynos_pinmux_config(host->dev_id, flag);
+ if (err) {
+ debug("DWMMC not configure\n");
+ return err;
+ }
- if (node <= 0)
- continue;
+ return exynos_dwmci_core_init(host, index);
+}
- /* Extract device id for each mmc channel */
- dev_id = pinmux_decode_periph_id(blob, node);
+static int exynos_dwmci_get_config(const void *blob, int node,
+ struct dwmci_host *host)
+{
+ int err = 0;
+ u32 base, clksel_val, timing[3];
- /* Get the bus width from the device node */
- bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
- if (bus_width <= 0) {
- debug("DWMMC: Can't get bus-width\n");
- return -1;
- }
- if (8 == bus_width)
- flag = PINMUX_FLAG_8BIT_MODE;
- else
- flag = PINMUX_FLAG_NONE;
+ /* Extract device id for each mmc channel */
+ host->dev_id = pinmux_decode_periph_id(blob, node);
- /* config pinmux for each mmc channel */
- err = exynos_pinmux_config(dev_id, flag);
- if (err) {
- debug("DWMMC not configured\n");
- return err;
- }
+ /* Get the bus width from the device node */
+ host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+ if (host->buswidth <= 0) {
+ debug("DWMMC: Can't get bus-width\n");
+ return -EINVAL;
+ }
- index = dev_id - PERIPH_ID_SDMMC0;
+ host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
+ if (host->dev_index == host->dev_id)
+ host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
- /* Get the base address from the device node */
- base = fdtdec_get_addr(blob, node, "reg");
- if (!base) {
- debug("DWMMC: Can't get base address\n");
- return -1;
- }
- /* Extract the timing info from the node */
- err = fdtdec_get_int_array(blob, node, "samsung,timing",
- timing, 3);
+ /* Set the base address from the device node */
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (!base) {
+ debug("DWMMC: Can't get base address\n");
+ return -EINVAL;
+ }
+ host->ioaddr = (void *)base;
+
+ /* Extract the timing info from the node */
+ err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
+ if (err) {
+ debug("Can't get sdr-timings for devider\n");
+ return -EINVAL;
+ }
+
+ clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(timing[2]));
+ if (clksel_val)
+ host->clksel_val = clksel_val;
+
+ host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
+ host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
+ host->div = fdtdec_get_int(blob, node, "div", 0);
+
+ return 0;
+}
+
+static int exynos_dwmci_process_node(const void *blob,
+ int node_list[], int count)
+{
+ struct dwmci_host *host;
+ int i, node, err;
+
+ for (i = 0; i < count; i++) {
+ node = node_list[i];
+ if (node <= 0)
+ continue;
+ host = &dwmci_host[i];
+ err = exynos_dwmci_get_config(blob, node, host);
if (err) {
- debug("Can't get sdr-timings for divider\n");
- return -1;
+ debug("%s: failed to decode dev %d\n", __func__, i);
+ return err;
}
- clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
- DWMCI_SET_DRV_CLK(timing[1]) |
- DWMCI_SET_DIV_RATIO(timing[2]));
- /* Initialise each mmc channel */
- err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
- if (err)
- debug("dwmmc Channel-%d init failed\n", index);
+ do_dwmci_init(host);
}
return 0;
}
+
+int exynos_dwmmc_init(const void *blob)
+{
+ int compat_id;
+ int node_list[DWMMC_MAX_CH_NUM];
+ int err = 0, count;
+
+ compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
+
+ count = fdtdec_find_aliases_for_id(blob, "mmc",
+ compat_id, node_list, DWMMC_MAX_CH_NUM);
+ err = exynos_dwmci_process_node(blob, node_list, count);
+
+ return err;
+}
#endif
{
struct mmc_cmd cmd;
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ return 0;
+
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
- if (cardtype & MMC_HS_52MHZ)
+ if (cardtype & EXT_CSD_CARD_TYPE_52) {
+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
+ mmc->card_caps |= MMC_MODE_DDR_52MHz;
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- else
+ } else {
mmc->card_caps |= MMC_MODE_HS;
+ }
return 0;
}
/* An array of possible bus widths in order of preference */
static unsigned ext_csd_bits[] = {
+ EXT_CSD_DDR_BUS_WIDTH_8,
+ EXT_CSD_DDR_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_8,
EXT_CSD_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_1,
/* An array to map CSD bus widths to host cap bits */
static unsigned ext_to_hostcaps[] = {
+ [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
+ [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
};
/* An array to map chosen bus width to an integer */
static unsigned widths[] = {
- 8, 4, 1,
+ 8, 4, 8, 4, 1,
};
for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
}
-int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+static int s5p_sdhci_core_init(struct sdhci_host *host)
{
- struct sdhci_host *host = NULL;
- host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!host) {
- printf("sdhci__host malloc fail!\n");
- return 1;
- }
-
host->name = S5P_NAME;
- host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
- host->index = index;
host->host_caps = MMC_MODE_HC;
- if (bus_width == 8)
+ if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
return add_sdhci(host, 52000000, 400000);
}
+int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+{
+ struct sdhci_host *host = malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf("sdhci__host malloc fail!\n");
+ return 1;
+ }
+ host->ioaddr = (void *)regbase;
+ host->index = index;
+ host->bus_width = bus_width;
+
+ return s5p_sdhci_core_init(host);
+}
+
#ifdef CONFIG_OF_CONTROL
struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
}
}
- host->name = S5P_NAME;
-
- host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
- SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
- SDHCI_QUIRK_WAIT_SEND_CMD;
- host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
- host->set_control_reg = &s5p_sdhci_set_control_reg;
- host->set_clock = set_mmc_clk;
-
- host->host_caps = MMC_MODE_HC;
-
- return add_sdhci(host, 52000000, 400000);
+ return s5p_sdhci_core_init(host);
}
static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
}
/* Shift the offset from byte addressing to word addressing. */
- if (this->options & NAND_BUSWIDTH_16)
+ if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
/* Set ALE and clear CLE to start address cycle */
hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- if (this->options & NAND_BUSWIDTH_16)
+ if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
/* Serially input address */
if (column != -1) {
/* Adjust columns for 16 bit buswidth */
- if (chip->options & NAND_BUSWIDTH_16)
+ if ((chip->options & NAND_BUSWIDTH_16) &&
+ !nand_opcode_8bits(command))
column >>= 1;
chip->cmd_ctrl(mtd, column, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
/* Serially input address */
if (column != -1) {
/* Adjust columns for 16 bit buswidth */
- if (chip->options & NAND_BUSWIDTH_16)
+ if ((chip->options & NAND_BUSWIDTH_16) &&
+ !nand_opcode_8bits(command))
column >>= 1;
chip->cmd_ctrl(mtd, column, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
int *busw)
{
struct nand_onfi_params *p = &chip->onfi_params;
- int i;
+ int i, j;
int val;
/* Try ONFI for unknown chip or LP */
chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
for (i = 0; i < 3; i++) {
- chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
+ for (j = 0; j < sizeof(*p); j++)
+ ((uint8_t *)p)[j] = chip->read_byte(mtd);
if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
le16_to_cpu(p->crc)) {
pr_info("ONFI param page %d valid\n", i);
}
/* Shift the offset from byte addressing to word addressing. */
- if (this->options & NAND_BUSWIDTH_16)
+ if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
/* Begin command latch cycle */
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
-#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/omap_elm.h>
#include <asm/arch/hardware.h>
+#define DRIVER_NAME "omap-elm"
#define ELM_DEFAULT_POLY (0)
struct elm *elm_cfg;
/**
- * elm_load_syndromes - Load BCH syndromes based on nibble selection
+ * elm_load_syndromes - Load BCH syndromes based on bch_type selection
* @syndrome: BCH syndrome
- * @nibbles:
+ * @bch_type: BCH4/BCH8/BCH16
* @poly: Syndrome Polynomial set to use
- *
- * Load BCH syndromes based on nibble selection
*/
-static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
+static void elm_load_syndromes(u8 *syndrome, enum bch_level bch_type, u8 poly)
{
u32 *ptr;
u32 val;
(syndrome[7] << 24);
writel(val, ptr);
- /* BCH 8-bit with 26 nibbles (4*8=32) */
- if (nibbles > 13) {
+ if (bch_type == BCH_8_BIT || bch_type == BCH_16_BIT) {
/* reg 2 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
writel(val, ptr);
}
- /* BCH 16-bit with 52 nibbles (7*8=56) */
- if (nibbles > 26) {
+ if (bch_type == BCH_16_BIT) {
/* reg 4 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
val = syndrome[16] | (syndrome[17] << 8) |
/**
* elm_check_errors - Check for BCH errors and return error locations
* @syndrome: BCH syndrome
- * @nibbles:
+ * @bch_type: BCH4/BCH8/BCH16
* @error_count: Returns number of errrors in the syndrome
* @error_locations: Returns error locations (in decimal) in this array
*
* and locations in the array passed. Returns -1 if error is not correctable,
* else returns 0
*/
-int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
u32 *error_locations)
{
u8 poly = ELM_DEFAULT_POLY;
s8 i;
u32 location_status;
- elm_load_syndromes(syndrome, nibbles, poly);
+ elm_load_syndromes(syndrome, bch_type, poly);
/* start processing */
writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
/* check if correctable */
location_status = readl(&elm_cfg->error_location[poly].location_status);
- if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
- return -1;
+ if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) {
+ printf("%s: uncorrectable ECC errors\n", DRIVER_NAME);
+ return -EBADMSG;
+ }
/* get error count */
*error_count = readl(&elm_cfg->error_location[poly].location_status) &
}
/*
- * Generic BCH interface
+ * Driver configurations
*/
-struct nand_bch_priv {
- uint8_t mode;
- uint8_t type;
- uint8_t nibbles;
+struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
};
-/* bch types */
-#define ECC_BCH4 0
-#define ECC_BCH8 1
-#define ECC_BCH16 2
-
-/* BCH nibbles for diff bch levels */
-#define ECC_BCH4_NIBBLES 13
-#define ECC_BCH8_NIBBLES 26
-#define ECC_BCH16_NIBBLES 52
-
/*
* This can be a single instance cause all current users have only one NAND
* with nearly the same setup (BCH8, some with ELM and others with sw BCH
* library).
* When some users with other BCH strength will exists this have to change!
*/
-static __maybe_unused struct nand_bch_priv bch_priv = {
- .type = ECC_BCH8,
- .nibbles = ECC_BCH8_NIBBLES,
+static __maybe_unused struct omap_nand_info omap_nand_info = {
.control = NULL
};
static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
{
struct nand_chip *nand = mtd->priv;
- struct nand_bch_priv *bch = nand->priv;
+ struct omap_nand_info *info = nand->priv;
unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
unsigned int ecc_algo = 0;
unsigned int bch_type = 0;
u32 ecc_config_val = 0;
/* configure GPMC for specific ecc-scheme */
- switch (bch->ecc_scheme) {
+ switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_SW:
return;
case OMAP_ECC_HAM1_CODE_HW:
eccsize1 = 2; /* non-ECC bits in nibbles per sector */
}
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ ecc_algo = 0x1;
+ bch_type = 0x2;
+ if (mode == NAND_ECC_WRITE) {
+ bch_wrapmode = 0x01;
+ eccsize0 = 0; /* extra bits in nibbles per sector */
+ eccsize1 = 52; /* OOB bits in nibbles per sector */
+ } else {
+ bch_wrapmode = 0x01;
+ eccsize0 = 52; /* ECC bits in nibbles per sector */
+ eccsize1 = 0; /* non-ECC bits in nibbles per sector */
+ }
+ break;
default:
return;
}
uint8_t *ecc_code)
{
struct nand_chip *chip = mtd->priv;
- struct nand_bch_priv *bch = chip->priv;
+ struct omap_nand_info *info = chip->priv;
uint32_t *ptr, val = 0;
int8_t i = 0, j;
- switch (bch->ecc_scheme) {
+ switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:
val = readl(&gpmc_cfg->ecc1_result);
ecc_code[0] = val & 0xFF;
ptr--;
}
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
+ ecc_code[i++] = (val >> 8) & 0xFF;
+ ecc_code[i++] = (val >> 0) & 0xFF;
+ val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
+ ecc_code[i++] = (val >> 24) & 0xFF;
+ ecc_code[i++] = (val >> 16) & 0xFF;
+ ecc_code[i++] = (val >> 8) & 0xFF;
+ ecc_code[i++] = (val >> 0) & 0xFF;
+ val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
+ ecc_code[i++] = (val >> 24) & 0xFF;
+ ecc_code[i++] = (val >> 16) & 0xFF;
+ ecc_code[i++] = (val >> 8) & 0xFF;
+ ecc_code[i++] = (val >> 0) & 0xFF;
+ for (j = 3; j >= 0; j--) {
+ val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
+ );
+ ecc_code[i++] = (val >> 24) & 0xFF;
+ ecc_code[i++] = (val >> 16) & 0xFF;
+ ecc_code[i++] = (val >> 8) & 0xFF;
+ ecc_code[i++] = (val >> 0) & 0xFF;
+ }
+ break;
default:
return -EINVAL;
}
/* ECC scheme specific syndrome customizations */
- switch (bch->ecc_scheme) {
+ switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:
break;
#ifdef CONFIG_BCH
case OMAP_ECC_BCH8_CODE_HW:
ecc_code[chip->ecc.bytes - 1] = 0x00;
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ break;
default:
return -EINVAL;
}
uint8_t *read_ecc, uint8_t *calc_ecc)
{
struct nand_chip *chip = mtd->priv;
- struct nand_bch_priv *bch = chip->priv;
- uint32_t eccbytes = chip->ecc.bytes;
+ struct omap_nand_info *info = chip->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
uint32_t error_count = 0, error_max;
- uint32_t error_loc[8];
+ uint32_t error_loc[ELM_MAX_ERROR_COUNT];
+ enum bch_level bch_type;
uint32_t i, ecc_flag = 0;
uint8_t count, err = 0;
uint32_t byte_pos, bit_pos;
/* check calculated ecc */
- for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
+ for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
if (calc_ecc[i] != 0x00)
ecc_flag = 1;
}
/* check for whether its a erased-page */
ecc_flag = 0;
- for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
+ for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
if (read_ecc[i] != 0xff)
ecc_flag = 1;
}
* while reading ECC result we read it in big endian.
* Hence while loading to ELM we have rotate to get the right endian.
*/
- switch (bch->ecc_scheme) {
+ switch (info->ecc_scheme) {
case OMAP_ECC_BCH8_CODE_HW:
- omap_reverse_list(calc_ecc, eccbytes - 1);
+ bch_type = BCH_8_BIT;
+ omap_reverse_list(calc_ecc, ecc->bytes - 1);
+ break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ bch_type = BCH_16_BIT;
+ omap_reverse_list(calc_ecc, ecc->bytes);
break;
default:
return -EINVAL;
}
/* use elm module to check for errors */
- elm_config((enum bch_level)(bch->type));
- if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) {
- printf("nand: error: uncorrectable ECC errors\n");
- return -EINVAL;
- }
+ elm_config(bch_type);
+ err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
+ if (err)
+ return err;
+
/* correct bch error */
for (count = 0; count < error_count; count++) {
- switch (bch->type) {
- case ECC_BCH8:
+ switch (info->ecc_scheme) {
+ case OMAP_ECC_BCH8_CODE_HW:
/* 14th byte in ECC is reserved to match ROM layout */
- error_max = SECTOR_BYTES + (eccbytes - 1);
+ error_max = SECTOR_BYTES + (ecc->bytes - 1);
+ break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ error_max = SECTOR_BYTES + ecc->bytes;
break;
default:
return -EINVAL;
/* cannot correct more than 8 errors */
unsigned int errloc[8];
struct nand_chip *chip = mtd->priv;
- struct nand_bch_priv *chip_priv = chip->priv;
- struct bch_control *bch = chip_priv->control;
+ struct omap_nand_info *info = chip->priv;
- count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
+ count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
+ NULL, errloc);
if (count > 0) {
/* correct errors */
for (i = 0; i < count; i++) {
static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
- struct nand_bch_priv *chip_priv = chip->priv;
- struct bch_control *bch = NULL;
-
- if (chip_priv)
- bch = chip_priv->control;
+ struct omap_nand_info *info = chip->priv;
- if (bch) {
- free_bch(bch);
- chip_priv->control = NULL;
+ if (info->control) {
+ free_bch(info->control);
+ info->control = NULL;
}
}
#endif /* CONFIG_BCH */
*/
static int omap_select_ecc_scheme(struct nand_chip *nand,
enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
- struct nand_bch_priv *bch = nand->priv;
+ struct omap_nand_info *info = nand->priv;
struct nand_ecclayout *ecclayout = &omap_ecclayout;
int eccsteps = pagesize / SECTOR_BYTES;
int i;
debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
/* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
* initialized in nand_scan_tail(), so just set ecc.mode */
- bch_priv.control = NULL;
- bch_priv.type = 0;
+ info->control = NULL;
nand->ecc.mode = NAND_ECC_SOFT;
nand->ecc.layout = NULL;
nand->ecc.size = 0;
- bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW;
break;
case OMAP_ECC_HAM1_CODE_HW:
(3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
return -EINVAL;
}
- bch_priv.control = NULL;
- bch_priv.type = 0;
+ info->control = NULL;
/* populate ecc specific fields */
memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
nand->ecc.mode = NAND_ECC_HW;
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
BADBLOCK_MARKER_LENGTH;
- bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW;
break;
case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
return -EINVAL;
}
/* check if BCH S/W library can be used for error detection */
- bch_priv.control = init_bch(13, 8, 0x201b);
- if (!bch_priv.control) {
+ info->control = init_bch(13, 8, 0x201b);
+ if (!info->control) {
printf("nand: error: could not init_bch()\n");
return -ENODEV;
}
- bch_priv.type = ECC_BCH8;
/* populate ecc specific fields */
memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
nand->ecc.mode = NAND_ECC_HW;
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
BADBLOCK_MARKER_LENGTH;
- bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
break;
#else
printf("nand: error: CONFIG_BCH required for ECC\n");
}
/* intialize ELM for ECC error detection */
elm_init();
- bch_priv.type = ECC_BCH8;
+ info->control = NULL;
/* populate ecc specific fields */
memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
nand->ecc.mode = NAND_ECC_HW;
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
BADBLOCK_MARKER_LENGTH;
- bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW;
break;
#else
printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
return -EINVAL;
#endif
+ case OMAP_ECC_BCH16_CODE_HW:
+#ifdef CONFIG_NAND_OMAP_ELM
+ debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
+ /* check ecc-scheme requirements before updating ecc info */
+ if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
+ printf("nand: error: insufficient OOB: require=%d\n", (
+ (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
+ return -EINVAL;
+ }
+ /* intialize ELM for ECC error detection */
+ elm_init();
+ /* populate ecc specific fields */
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = SECTOR_BYTES;
+ nand->ecc.bytes = 26;
+ nand->ecc.strength = 16;
+ nand->ecc.hwctl = omap_enable_hwecc;
+ nand->ecc.correct = omap_correct_data_bch;
+ nand->ecc.calculate = omap_calculate_ecc;
+ nand->ecc.read_page = omap_read_page_bch;
+ /* define ecc-layout */
+ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
+ for (i = 0; i < ecclayout->eccbytes; i++)
+ ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
+ ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
+ ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
+ BADBLOCK_MARKER_LENGTH;
+ break;
+#else
+ printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
+ return -EINVAL;
+#endif
default:
debug("nand: error: ecc scheme not enabled or supported\n");
return -EINVAL;
if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
nand->ecc.layout = ecclayout;
+ info->ecc_scheme = ecc_scheme;
return 0;
}
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
- nand->priv = &bch_priv;
+ nand->priv = &omap_nand_info;
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
- /* If we are 16 bit dev, our gpmc config tells us that */
- if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
- nand->options |= NAND_BUSWIDTH_16;
-
nand->chip_delay = 100;
nand->ecc.layout = &omap_ecclayout;
+ /* configure driver and controller based on NAND device bus-width */
+ gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
+#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
+ nand->options |= NAND_BUSWIDTH_16;
+ writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
+#else
+ nand->options &= ~NAND_BUSWIDTH_16;
+ writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
+#endif
/* select ECC scheme */
#if defined(CONFIG_NAND_OMAP_ECCSCHEME)
err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
int r = get_phy_id(bus, addr, devad, &phy_id);
- if (r < 0)
- return ERR_PTR(r);
/* If the PHY ID is mostly f's, we didn't find anything */
- if ((phy_id & 0x1fffffff) != 0x1fffffff)
+ if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff)
return phy_device_create(bus, addr, phy_id, interface);
phy_mask &= ~(1 << addr);
}
/* packet must be a 4 byte boundary */
if ((int)packet & 3) {
- printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
+ printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n"
+ , __func__);
ret = -EFAULT;
goto err;
}
static int sh_eth_reset(struct sh_eth_dev *eth)
{
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
/* Perform a software reset and wait for it to complete */
sh_eth_write(eth, EDMR_SRST, EDMR);
- for (i = 0; i < TIMEOUT_CNT ; i++) {
+ for (i = 0; i < TIMEOUT_CNT; i++) {
if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
break;
udelay(1000);
/* Point the controller to the tx descriptor list. Must use physical
addresses */
sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
/* Point the controller to the rx descriptor list */
sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
sh_eth_write(eth, RDFFR_RDLF, RDFFR);
sh_eth_write(eth, 0, TFTR);
sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
sh_eth_write(eth, RMCR_RST, RMCR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, 0, RPADIR);
#endif
sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, 0, PIPR);
+#endif
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, APR_AP, APR);
sh_eth_write(eth, MPR_MP, MPR);
sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
int sh_eth_initialize(bd_t *bd)
{
- int ret = 0;
+ int ret = 0;
struct sh_eth_dev *eth = NULL;
- struct eth_device *dev = NULL;
+ struct eth_device *dev = NULL;
- eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
+ eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
- memset(dev, 0, sizeof(struct eth_device));
- memset(eth, 0, sizeof(struct sh_eth_dev));
+ memset(dev, 0, sizeof(struct eth_device));
+ memset(eth, 0, sizeof(struct sh_eth_dev));
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
- dev->priv = (void *)eth;
- dev->iobase = 0;
- dev->init = sh_eth_init;
- dev->halt = sh_eth_halt;
- dev->send = sh_eth_send;
- dev->recv = sh_eth_recv;
- eth->port_info[eth->port].dev = dev;
+ dev->priv = (void *)eth;
+ dev->iobase = 0;
+ dev->init = sh_eth_init;
+ dev->halt = sh_eth_halt;
+ dev->send = sh_eth_send;
+ dev->recv = sh_eth_recv;
+ eth->port_info[eth->port].dev = dev;
sprintf(dev->name, SHETHER_NAME);
- /* Register Device to EtherNet subsystem */
- eth_register(dev);
+ /* Register Device to EtherNet subsystem */
+ eth_register(dev);
bb_miiphy_buses[0].priv = eth;
miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
[RMII_MII] = 0x0790,
};
+#if defined(SH_ETH_TYPE_RZ)
+static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
+ [EDSR] = 0x0000,
+ [EDMR] = 0x0400,
+ [EDTRR] = 0x0408,
+ [EDRRR] = 0x0410,
+ [EESR] = 0x0428,
+ [EESIPR] = 0x0430,
+ [TDLAR] = 0x0010,
+ [TDFAR] = 0x0014,
+ [TDFXR] = 0x0018,
+ [TDFFR] = 0x001c,
+ [RDLAR] = 0x0030,
+ [RDFAR] = 0x0034,
+ [RDFXR] = 0x0038,
+ [RDFFR] = 0x003c,
+ [TRSCER] = 0x0438,
+ [RMFCR] = 0x0440,
+ [TFTR] = 0x0448,
+ [FDR] = 0x0450,
+ [RMCR] = 0x0458,
+ [RPADIR] = 0x0460,
+ [FCFTR] = 0x0468,
+ [CSMR] = 0x04E4,
+
+ [ECMR] = 0x0500,
+ [ECSR] = 0x0510,
+ [ECSIPR] = 0x0518,
+ [PSR] = 0x0528,
+ [PIPR] = 0x052c,
+ [RFLR] = 0x0508,
+ [APR] = 0x0554,
+ [MPR] = 0x0558,
+ [PFTCR] = 0x055c,
+ [PFRCR] = 0x0560,
+ [TPAUSER] = 0x0564,
+ [GECMR] = 0x05b0,
+ [BCULR] = 0x05b4,
+ [MAHR] = 0x05c0,
+ [MALR] = 0x05c8,
+ [TROCR] = 0x0700,
+ [CDCR] = 0x0708,
+ [LCCR] = 0x0710,
+ [CEFCR] = 0x0740,
+ [FRECR] = 0x0748,
+ [TSFRCR] = 0x0750,
+ [TLFRCR] = 0x0758,
+ [RFCR] = 0x0760,
+ [CERCR] = 0x0768,
+ [CEECR] = 0x0770,
+ [MAFCR] = 0x0778,
+ [RMII_MII] = 0x0790,
+};
+#endif
+
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100,
[RFLR] = 0x0108,
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
+#elif defined(CONFIG_R7S72100)
+#define SH_ETH_TYPE_RZ
+#define BASE_IO_ADDR 0xE8203000
#endif
/*
* Register's bits
* Copy from Linux driver source code
*/
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
/* EDSR */
enum EDSR_BIT {
EDSR_ENT = 0x01, EDSR_ENR = 0x02,
/* EDMR */
enum DMAC_M_BIT {
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDMR_SRST = 0x03, /* Receive/Send reset */
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
/* EDTRR */
enum DMAC_T_BIT {
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDTRR_TRNS = 0x03,
#else
EDTRR_TRNS = 0x01,
/* EESR */
enum EESR_BIT {
-
#if defined(SH_ETH_TYPE_ETHER)
EESR_TWB = 0x40000000,
#else
EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
- rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
+ EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
/* Transfer descriptor bit */
enum TD_STS_BIT {
-#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
+ defined(SH_ETH_TYPE_RZ)
TD_TACT = 0x80000000,
#else
TD_TACT = 0x7fffffff,
enum RECV_RST_BIT { RMCR_RST = 0x01, };
/* ECMR */
enum FELIC_MODE_BIT {
-#if defined(SH_ETH_TYPE_GETHER)
- ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
- ECMR_RZPF = 0x00100000,
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
+ ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
+ ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
#endif
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
};
-#if defined(SH_ETH_TYPE_GETHER)
-#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
- ECMR_TXF | ECMR_MCT)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
+#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
+ ECMR_RXF | ECMR_TXF | ECMR_MCT)
#elif defined(SH_ETH_TYPE_ETHER)
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
#else
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
ECSIPR_ICDIP = 0x01,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
#else
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
RPADIR_PADR = 0x0003f,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define RPADIR_INIT (0x00)
#else
# define RPADIR_INIT (RPADIR_PADS1)
const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4;
+#elif defined(SH_ETH_TYPE_RZ)
+ const u16 *reg_offset = sh_eth_offset_rz;
#else
#error
#endif
struct battery *battery = p_bat->bat;
int k;
- if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450))
+ if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450))
return -1;
for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) &&
}
}
exit:
- bat->chrg->chrg_state(p_bat->chrg, CHARGER_DISABLE, 0);
+ bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0);
return 0;
}
{
struct power_battery *p_bat = bat->pbat;
- if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450))
+ if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450))
return -1;
return 0;
val = MAX77693_CHG_UNLOCK;
pmic_reg_write(p, MAX77693_CHG_CNFG_06, val);
- if (state == CHARGER_DISABLE) {
+ if (state == PMIC_CHARGER_DISABLE) {
puts("Disable the charger.\n");
pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val);
val &= ~0x01;
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
+obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
if (pmic_probe(p))
return -1;
- if (state == CHARGER_DISABLE) {
+ if (state == PMIC_CHARGER_DISABLE) {
puts("Disable the charger.\n");
pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val);
val &= ~(MBCHOSTEN | VCHGR_FC);
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/tps65090_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TPS65090_NAME "TPS65090_PMIC"
+
+/* TPS65090 register addresses */
+enum {
+ REG_IRQ1 = 0,
+ REG_CG_CTRL0 = 4,
+ REG_CG_STATUS1 = 0xa,
+ REG_FET1_CTRL = 0x0f,
+ REG_FET2_CTRL,
+ REG_FET3_CTRL,
+ REG_FET4_CTRL,
+ REG_FET5_CTRL,
+ REG_FET6_CTRL,
+ REG_FET7_CTRL,
+ TPS65090_NUM_REGS,
+};
+
+enum {
+ IRQ1_VBATG = 1 << 3,
+ CG_CTRL0_ENC_MASK = 0x01,
+
+ MAX_FET_NUM = 7,
+ MAX_CTRL_READ_TRIES = 5,
+
+ /* TPS65090 FET_CTRL register values */
+ FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
+ FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
+ FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
+ FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */
+ FET_CTRL_ENFET = 1 << 0, /* Enable FET */
+};
+
+/**
+ * Checks for a valid FET number
+ *
+ * @param fet_id FET number to check
+ * @return 0 if ok, -EINVAL if FET value is out of range
+ */
+static int tps65090_check_fet(unsigned int fet_id)
+{
+ if (fet_id == 0 || fet_id > MAX_FET_NUM) {
+ debug("parameter fet_id is out of range, %u not in 1 ~ %u\n",
+ fet_id, MAX_FET_NUM);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Set the power state for a FET
+ *
+ * @param pmic pmic structure for the tps65090
+ * @param fet_id Fet number to set (1..MAX_FET_NUM)
+ * @param set 1 to power on FET, 0 to power off
+ * @return -EIO if we got a comms error, -EAGAIN if the FET failed to
+ * change state. If all is ok, returns 0.
+ */
+static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set)
+{
+ int retry;
+ u32 reg, value;
+
+ value = FET_CTRL_ADENFET | FET_CTRL_WAIT;
+ if (set)
+ value |= FET_CTRL_ENFET;
+
+ if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value))
+ return -EIO;
+
+ /* Try reading until we get a result */
+ for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {
+ if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®))
+ return -EIO;
+
+ /* Check that the fet went into the expected state */
+ if (!!(reg & FET_CTRL_PGFET) == set)
+ return 0;
+
+ /* If we got a timeout, there is no point in waiting longer */
+ if (reg & FET_CTRL_TOFET)
+ break;
+
+ mdelay(1);
+ }
+
+ debug("FET %d: Power good should have set to %d but reg=%#02x\n",
+ fet_id, set, reg);
+ return -EAGAIN;
+}
+
+int tps65090_fet_enable(unsigned int fet_id)
+{
+ struct pmic *pmic;
+ ulong start;
+ int loops;
+ int ret;
+
+ ret = tps65090_check_fet(fet_id);
+ if (ret)
+ return ret;
+
+ pmic = pmic_get(TPS65090_NAME);
+ if (!pmic)
+ return -EACCES;
+
+ start = get_timer(0);
+ for (loops = 0;; loops++) {
+ ret = tps65090_fet_set(pmic, fet_id, true);
+ if (!ret)
+ break;
+
+ if (get_timer(start) > 100)
+ break;
+
+ /* Turn it off and try again until we time out */
+ tps65090_fet_set(pmic, fet_id, false);
+ }
+
+ if (ret)
+ debug("%s: FET%d failed to power on: time=%lums, loops=%d\n",
+ __func__, fet_id, get_timer(start), loops);
+ else if (loops)
+ debug("%s: FET%d powered on after %lums, loops=%d\n",
+ __func__, fet_id, get_timer(start), loops);
+
+ /*
+ * Unfortunately, there are some conditions where the power
+ * good bit will be 0, but the fet still comes up. One such
+ * case occurs with the lcd backlight. We'll just return 0 here
+ * and assume that the fet will eventually come up.
+ */
+ if (ret == -EAGAIN)
+ ret = 0;
+
+ return ret;
+}
+
+int tps65090_fet_disable(unsigned int fet_id)
+{
+ struct pmic *pmic;
+ int ret;
+
+ ret = tps65090_check_fet(fet_id);
+ if (ret)
+ return ret;
+
+ pmic = pmic_get(TPS65090_NAME);
+ if (!pmic)
+ return -EACCES;
+ ret = tps65090_fet_set(pmic, fet_id, false);
+
+ return ret;
+}
+
+int tps65090_fet_is_enabled(unsigned int fet_id)
+{
+ struct pmic *pmic;
+ u32 reg;
+ int ret;
+
+ ret = tps65090_check_fet(fet_id);
+ if (ret)
+ return ret;
+
+ pmic = pmic_get(TPS65090_NAME);
+ if (!pmic)
+ return -ENODEV;
+ ret = pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®);
+ if (ret) {
+ debug("fail to read FET%u_CTRL register over I2C", fet_id);
+ return -EIO;
+ }
+
+ return reg & FET_CTRL_ENFET;
+}
+
+int tps65090_get_charging(void)
+{
+ struct pmic *pmic;
+ u32 val;
+ int ret;
+
+ pmic = pmic_get(TPS65090_NAME);
+ if (!pmic)
+ return -EACCES;
+
+ ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & CG_CTRL0_ENC_MASK);
+}
+
+static int tps65090_charger_state(struct pmic *pmic, int state,
+ int current)
+{
+ u32 val;
+ int ret;
+
+ ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val);
+ if (!ret) {
+ if (state == PMIC_CHARGER_ENABLE)
+ val |= CG_CTRL0_ENC_MASK;
+ else
+ val &= ~CG_CTRL0_ENC_MASK;
+ ret = pmic_reg_write(pmic, REG_CG_CTRL0, val);
+ }
+ if (ret) {
+ debug("%s: Failed to read/write register\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+int tps65090_get_status(void)
+{
+ struct pmic *pmic;
+ u32 val;
+ int ret;
+
+ pmic = pmic_get(TPS65090_NAME);
+ if (!pmic)
+ return -EACCES;
+
+ ret = pmic_reg_read(pmic, REG_CG_STATUS1, &val);
+ if (ret)
+ return ret;
+
+ return val;
+}
+
+static int tps65090_charger_bat_present(struct pmic *pmic)
+{
+ u32 val;
+ int ret;
+
+ ret = pmic_reg_read(pmic, REG_IRQ1, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & IRQ1_VBATG);
+}
+
+static struct power_chrg power_chrg_pmic_ops = {
+ .chrg_bat_present = tps65090_charger_bat_present,
+ .chrg_state = tps65090_charger_state,
+};
+
+int tps65090_init(void)
+{
+ struct pmic *p;
+ int bus;
+ int addr;
+ const void *blob = gd->fdt_blob;
+ int node, parent;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_TI_TPS65090);
+ if (node < 0) {
+ debug("PMIC: No node for PMIC Chip in device tree\n");
+ debug("node = %d\n", node);
+ return -ENODEV;
+ }
+
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0) {
+ debug("%s: Cannot find node parent\n", __func__);
+ return -EINVAL;
+ }
+
+ bus = i2c_get_bus_num_fdt(parent);
+ if (p->bus < 0) {
+ debug("%s: Cannot find I2C bus\n", __func__);
+ return -ENOENT;
+ }
+ addr = fdtdec_get_int(blob, node, "reg", TPS65090_I2C_ADDR);
+ p = pmic_alloc();
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = TPS65090_NAME;
+ p->bus = bus;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = TPS65090_NUM_REGS;
+ p->hw.i2c.addr = addr;
+ p->hw.i2c.tx_num = 1;
+ p->chrg = &power_chrg_pmic_ops;
+
+ puts("TPS65090 PMIC init\n");
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <power/tps65218.h>
+
+/**
+ * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC
+ * register or bit field regardless of protection
+ * level.
+ *
+ * @prot_level: Register password protection. Use
+ * TPS65218_PROT_LEVEL_NONE,
+ * TPS65218_PROT_LEVEL_1 or TPS65218_PROT_LEVEL_2
+ * @dest_reg: Register address to write.
+ * @dest_val: Value to write.
+ * @mask: Bit mask (8 bits) to be applied. Function will only
+ * change bits that are set in the bit mask.
+ *
+ * @return: 0 for success, not 0 on failure, as per the i2c API
+ */
+int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+ uchar mask)
+{
+ uchar read_val;
+ uchar xor_reg;
+ int ret;
+
+ /*
+ * If we are affecting only a bit field, read dest_reg and apply the
+ * mask
+ */
+ if (mask != TPS65218_MASK_ALL_BITS) {
+ ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1);
+ if (ret)
+ return ret;
+ read_val &= (~mask);
+ read_val |= (dest_val & mask);
+ dest_val = read_val;
+ }
+
+ if (prot_level > 0) {
+ xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK;
+ ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
+ &xor_reg, 1);
+ if (ret)
+ return ret;
+ }
+
+ ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1);
+ if (ret)
+ return ret;
+
+ if (prot_level == TPS65218_PROT_LEVEL_2) {
+ ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
+ &xor_reg, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * tps65218_voltage_update() - Function to change a voltage level, as this
+ * is a multi-step process.
+ * @dc_cntrl_reg: DC voltage control register to change.
+ * @volt_sel: New value for the voltage register
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
+{
+ if ((dc_cntrl_reg != TPS65218_DCDC1) &&
+ (dc_cntrl_reg != TPS65218_DCDC2))
+ return 1;
+
+ /* set voltage level */
+ if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
+ TPS65218_MASK_ALL_BITS))
+ return 1;
+
+ /* set GO bit to initiate voltage transition */
+ if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_SLEW,
+ TPS65218_DCDC_GO, TPS65218_DCDC_GO))
+ return 1;
+
+ return 0;
+}
#include <fsl_pmic.h>
#include <errno.h>
-#if defined(CONFIG_PMIC_FSL_MC13892)
+#if defined(CONFIG_POWER_FSL_MC13892)
#define FSL_PMIC_I2C_LENGTH 3
-#elif defined(CONFIG_PMIC_FSL_MC34704)
+#elif defined(CONFIG_POWER_FSL_MC34704)
#define FSL_PMIC_I2C_LENGTH 1
#endif
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
#else
-#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
+#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C"
#endif
return 0;
if (check_reg(p, reg))
return -1;
+ I2C_SET_BUS(p->bus);
+
switch (pmic_i2c_tx_num) {
case 3:
if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) {
if (check_reg(p, reg))
return -1;
+ I2C_SET_BUS(p->bus);
+
if (i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num))
return -1;
struct fsl_spi_slave {
struct spi_slave slave;
+ ccsr_espi_t *espi;
unsigned int div16;
unsigned int pm;
+ int tx_timeout;
unsigned int mode;
size_t cmd_len;
u8 cmd_buf[16];
};
#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
+#define US_PER_SECOND 1000000UL
#define ESPI_MAX_CS_NUM 4
+#define ESPI_FIFO_WIDTH_BIT 32
#define ESPI_EV_RNE (1 << 9)
#define ESPI_EV_TNF (1 << 8)
+#define ESPI_EV_DON (1 << 14)
+#define ESPI_EV_TXE (1 << 15)
+#define ESPI_EV_RFCNT_SHIFT 24
+#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT)
#define ESPI_MODE_EN (1 << 31) /* Enable interface */
#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */
struct fsl_spi_slave *fsl;
sys_info_t sysinfo;
unsigned long spibrg = 0;
+ unsigned long spi_freq = 0;
unsigned char pm = 0;
if (!spi_cs_is_valid(bus, cs))
if (!fsl)
return NULL;
+ fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
fsl->mode = mode;
fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
pm--;
fsl->pm = pm;
+ if (fsl->div16)
+ spi_freq = spibrg / ((pm + 1) * 2 * 16);
+ else
+ spi_freq = spibrg / ((pm + 1) * 2);
+
+ /* set tx_timeout to 10 times of one espi FIFO entry go out */
+ fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
+ * 10), spi_freq);
+
return &fsl->slave;
}
int spi_claim_bus(struct spi_slave *slave)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ ccsr_espi_t *espi = fsl->espi;
unsigned char pm = fsl->pm;
unsigned int cs = slave->cs;
unsigned int mode = fsl->mode;
}
+static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
+{
+ ccsr_espi_t *espi = fsl->espi;
+ unsigned int tmpdout, event;
+ int tmp_tx_timeout;
+
+ if (dout)
+ tmpdout = *(u32 *)dout;
+ else
+ tmpdout = 0;
+
+ out_be32(&espi->tx, tmpdout);
+ out_be32(&espi->event, ESPI_EV_TNF);
+ debug("***spi_xfer:...%08x written\n", tmpdout);
+
+ tmp_tx_timeout = fsl->tx_timeout;
+ /* Wait for eSPI transmit to go out */
+ while (tmp_tx_timeout--) {
+ event = in_be32(&espi->event);
+ if (event & ESPI_EV_DON || event & ESPI_EV_TXE) {
+ out_be32(&espi->event, ESPI_EV_TXE);
+ break;
+ }
+ udelay(1);
+ }
+
+ if (tmp_tx_timeout < 0)
+ debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
+}
+
+static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
+{
+ ccsr_espi_t *espi = fsl->espi;
+ unsigned int tmpdin, rx_times;
+ unsigned char *buf, *p_cursor;
+
+ if (bytes <= 0)
+ return 0;
+
+ rx_times = DIV_ROUND_UP(bytes, 4);
+ buf = (unsigned char *)malloc(4 * rx_times);
+ if (!buf) {
+ debug("SF: Failed to malloc memory.\n");
+ return -1;
+ }
+ p_cursor = buf;
+ while (rx_times--) {
+ tmpdin = in_be32(&espi->rx);
+ debug("***spi_xfer:...%08x readed\n", tmpdin);
+ *(u32 *)p_cursor = tmpdin;
+ p_cursor += 4;
+ }
+
+ if (din)
+ memcpy(din, buf, bytes);
+
+ free(buf);
+ out_be32(&espi->event, ESPI_EV_RNE);
+
+ return bytes;
+}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
void *data_in, unsigned long flags)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
- unsigned int tmpdout, tmpdin, event;
+ ccsr_espi_t *espi = fsl->espi;
+ unsigned int event, rx_bytes;
const void *dout = NULL;
void *din = NULL;
int len = 0;
int num_blks, num_chunks, max_tran_len, tran_len;
int num_bytes;
- unsigned char *ch;
unsigned char *buffer = NULL;
size_t buf_len;
u8 *cmd_buf = fsl->cmd_buf;
size_t cmd_len = fsl->cmd_len;
size_t data_len = bitlen / 8;
size_t rx_offset = 0;
+ int rf_cnt;
max_tran_len = fsl->max_transfer_length;
switch (flags) {
break;
}
- debug("spi_xfer: slave %u:%u dout %08X(%p) din %08X(%p) len %u\n",
- slave->bus, slave->cs, *(uint *) dout,
- dout, *(uint *) din, din, len);
+ debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n",
+ *(uint *)data_out, data_out, *(uint *)data_in, data_in, len);
num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
while (num_chunks--) {
/* Clear all eSPI events */
out_be32(&espi->event , 0xffffffff);
/* handle data in 32-bit chunks */
- while (num_blks--) {
-
+ while (num_blks) {
event = in_be32(&espi->event);
if (event & ESPI_EV_TNF) {
- tmpdout = *(u32 *)dout;
-
+ fsl_espi_tx(fsl, dout);
/* Set up the next iteration */
if (len > 4) {
len -= 4;
dout += 4;
}
-
- out_be32(&espi->tx, tmpdout);
- out_be32(&espi->event, ESPI_EV_TNF);
- debug("***spi_xfer:...%08x written\n", tmpdout);
}
- /* Wait for eSPI transmit to get out */
- udelay(80);
-
event = in_be32(&espi->event);
if (event & ESPI_EV_RNE) {
- tmpdin = in_be32(&espi->rx);
- if (num_blks == 0 && num_bytes != 0) {
- ch = (unsigned char *)&tmpdin;
- while (num_bytes--)
- *(unsigned char *)din++ = *ch++;
- } else {
- *(u32 *) din = tmpdin;
- din += 4;
+ rf_cnt = ((event & ESPI_EV_RFCNT_MASK)
+ >> ESPI_EV_RFCNT_SHIFT);
+ if (rf_cnt >= 4)
+ rx_bytes = 4;
+ else if (num_blks == 1 && rf_cnt == num_bytes)
+ rx_bytes = num_bytes;
+ else
+ continue;
+ if (fsl_espi_rx(fsl, din, rx_bytes)
+ == rx_bytes) {
+ num_blks--;
+ if (din)
+ din = (unsigned char *)din
+ + rx_bytes;
}
-
- out_be32(&espi->event, in_be32(&espi->event)
- | ESPI_EV_RNE);
- debug("***spi_xfer:...%08x readed\n", tmpdin);
}
}
if (data_in) {
void spi_cs_activate(struct spi_slave *slave)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ ccsr_espi_t *espi = fsl->espi;
unsigned int com = 0;
size_t data_len = fsl->data_len;
void spi_cs_deactivate(struct spi_slave *slave)
{
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+ ccsr_espi_t *espi = fsl->espi;
/* clear the RXCNT and TXCNT */
out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
slave->memory_map = (void *)MMAP_START_ADDR_DRA;
#else
slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
+ slave->op_mode_rx = 8;
#endif
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
DTB := arch/$(ARCH)/dts/$(DEVICE_TREE).dtb
-quiet_cmd_copy = COPY $@
- cmd_copy = cp $< $@
-
$(obj)/dt.dtb: $(DTB) FORCE
- $(call if_changed,copy)
+ $(call if_changed,shipped)
targets += dt.dtb
total_sector = bs.total_sect;
if (total_sector == 0)
- total_sector = cur_part_info.size;
+ total_sector = (int)cur_part_info.size; /* cast of lbaint_t */
if (mydata->fatsize == 32)
mydata->fatlength = bs.fat32_length;
#include <asm/immap_512x.h>
#elif defined(CONFIG_MPC8260)
#if defined(CONFIG_MPC8247) \
- || defined(CONFIG_MPC8248) \
- || defined(CONFIG_MPC8271) \
|| defined(CONFIG_MPC8272)
#define CONFIG_MPC8272_FAMILY 1
#endif
#define CONFIG_SYS_HZ 1000
#endif
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
+#ifdef CONFIG_DISABLE_IMAGE_LEGACY
+#undef CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
#endif /* __CONFIG_FALLBACKS_H */
+++ /dev/null
-/*
- * Copyright (C) 2004-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Adder boards family.
- * Tested on AdderII and Adder87x.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
-#define CONFIG_MPC875
-#endif
-
-#define CONFIG_ADDER /* Analogue&Micro Adder board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_ETHER_ON_FEC1
-#define CONFIG_ETHER_ON_FEC2
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII_INIT 1
-#define FEC_ENET
-#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
-
-#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
-#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
-#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
-#ifdef CONFIG_MPC852T
-#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000
-#else
-#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
-#endif /* CONFIG_MPC852T */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
-
-#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* #undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
-
-#define CONFIG_SYS_MAMR 0x00002114
-
-/*
- * 4096 Up to 4096 SDRAM rows
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR)
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x09900000
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-/*-----------------------------------------------------------------------
- * Flash organisation
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
-
-/* Environment is in flash */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_OR0_PRELIM 0xFF000774
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/*-----------------------------------------------------------------------
- * Internal Memory Map Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Configuration registers
- */
-#ifdef CONFIG_WATCHDOG
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
- SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
- SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
- SYPCR_SWF | SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
-
-/* TBSCR - Time Base Status and Control Register */
-#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE)
-
-/* PISCR - Periodic Interrupt Status and Control */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/* PLPRCR - PLL, Low-Power, and Reset Control Register */
-/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */
-
-/* SCCR - System Clock and reset Control Register */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR SCCR_RTSEL
-
-#define CONFIG_SYS_DER 0
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_HIDDEN_DRAGON 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#if 0
-#define USE_DINK32 1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_DRAM_SPEED 100 /* MHz */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-
-#define CONFIG_RTL8139
-
-/* Make sure the ethaddr can be overwritten
- TODO: Remove this on final product
-*/
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE 0x00090000
-#define CONFIG_SYS_RAMBOOT 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0xFFE00000
-#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_ISA_MEM 0xFD000000
-#define CONFIG_SYS_ISA_IO 0xFE000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
-#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly. Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
-#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
-#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
-#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/* TODO: Change this to VIA686A */
-
-/*
- * NS87308 Configuration
- */
-#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
-
-#define CONFIG_SYS_NS87308_BADDR_10 1
-
-#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
- CONFIG_SYS_NS87308_UART2 | \
- CONFIG_SYS_NS87308_POWRMAN | \
- CONFIG_SYS_NS87308_RTC_APC )
-
-#undef CONFIG_SYS_NS87308_PS2MOD
-
-#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
-#define CONFIG_SYS_NS87308_CS0_CONF 0x30
-#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
-#define CONFIG_SYS_NS87308_CS1_CONF 0x30
-#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
-#define CONFIG_SYS_NS87308_CS2_CONF 0x30
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#if (CONFIG_CONS_INDEX > 2)
-#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
-#else
-#define CONFIG_SYS_NS16550_CLK 1843200
-#endif
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
-
-#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#if 0
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
-#endif
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#undef NR_8259_INTS
-#define NR_8259_INTS 1
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Interphase iSPAN Communications Controllers
- * (453x and others). Tested on 4532.
- *
- * Derived from iSPAN 4539 port (iphase4539) by
- * Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
-
-/*-----------------------------------------------------------------------
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * If CONFIG_CONS_NONE is defined, then the serial console routines must be
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
-#undef CONFIG_CONS_NONE /* Define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
-
-/*-----------------------------------------------------------------------
- * Select Ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC).
- *
- * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
- * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
-#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
-#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
-#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#if CONFIG_ETHER_INDEX == 3
-
-#define CONFIG_SYS_PHY_ADDR 0
-#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
-#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-
-#endif /* CONFIG_ETHER_INDEX == 3 */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 3 /* Port D */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-
-#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
-#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
-
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#define CONFIG_8260_CLKIN 65536000 /* in Hz */
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-
-#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* #undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x09900000
-
-#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
-
-/* Environment is in flash, there is little space left in Serial EEPROM */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-/* 0x1686B245 */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
- HRCW_L2CPC10 | HRCW_ISB110 |\
- HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
- HRCW_CS10PC01 | HRCW_MODCK_H0101 \
- )
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0F00000
-#ifdef CONFIG_SYS_REV_B
-#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
-#endif /* CONFIG_SYS_REV_B */
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR 0xA01C0000
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined (CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*-----------------------------------------------------------------------
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSize Device
- * ---- --- ------- ----------------------------- ------
- * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
- * 1 60x SDRAM 64 bit SDRAM
- * 2 Local SDRAM 32 bit SDRAM
- */
-#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
- controller, rely on initialisation
- performed by the Interphase boot firmware.
- */
-
-#define CONFIG_SYS_OR0_PRELIM 0xFE000882
-#ifdef CONFIG_SYS_REV_B
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
-#else /* Rev. D */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
-#endif /* CONFIG_SYS_REV_B */
-
-#define CONFIG_SYS_MPTPR 0x7F00
-
-/* Please note that 60x SDRAM MUST start at 0 */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_60x_BR 0x00000041
-#define CONFIG_SYS_60x_OR 0xF0002CD0
-#define CONFIG_SYS_PSDMR 0x0049929A
-#define CONFIG_SYS_PSRT 0x07
-
-#define CONFIG_SYS_LSDRAM_BASE 0xF7000000
-#define CONFIG_SYS_LOC_BR 0x00001861
-#define CONFIG_SYS_LOC_OR 0xFF803280
-#define CONFIG_SYS_LSDMR 0x8285A552
-#define CONFIG_SYS_LSRT 0x07
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stuart Hughes <stuarth@lineo.com>
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the mpc8260ads manual.
- *
- * Note: my board is a PILOT rev.
- * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
- * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
- * Ported to MPC8272ADS board.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI bridge on MPC8272ADS
- *
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
-#endif
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/*
- * Figure out if we are booting low via flash HRCW or high via the BCSR.
- */
-#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/* ADS flavours */
-#define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
-#define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
-#define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
-#define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
-
-#ifndef CONFIG_ADSTYPE
-#define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
-#endif /* CONFIG_ADSTYPE */
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_MPC8272 1
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/*
- * Actually MPC8275, but the code is littered with ifdefs that
- * apply to both, or which use this ifdef to assume board-specific
- * details. :-(
- */
-#define CONFIG_MPC8272 1
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-
-#if CONFIG_ETHER_INDEX == 1
-
-# define CONFIG_SYS_PHY_ADDR 0
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-
-#elif CONFIG_ETHER_INDEX == 2
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
-# define CONFIG_SYS_PHY_ADDR 3
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
-#else /* RxCLK is CLK13, TxCLK is CLK14 */
-# define CONFIG_SYS_PHY_ADDR 0
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
-#define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
-#else
-#define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
-#define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
-#else
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
-#define CONFIG_SPD_ADDR 0x50
-#endif
-#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
-
-/*PCI*/
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_BOOTDELAY 0
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-#ifndef CONFIG_SDRAM_PBI
-#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
-#endif
-
-#ifndef CONFIG_8260_CLKIN
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#if defined(CONFIG_OF_LIBFDT)
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-
-#undef CONFIG_CMD_XIMG
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- #undef CONFIG_CMD_SDRAM
- #undef CONFIG_CMD_I2C
-
-#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
- #undef CONFIG_CMD_SDRAM
- #undef CONFIG_CMD_I2C
-
-#else
- #undef CONFIG_CMD_PCI
-
-#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xff800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-/*
- * JFFS2 partitions
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
-#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/* this is stuff came out of the Motorola docs */
-#ifndef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
-#endif
-
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_BCSR 0xF4500000
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_PCI_INT 0xF8200000
-#endif
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_LSDRAM_BASE 0xFD000000
-
-#define RS232EN_1 0x02000002
-#define RS232EN_2 0x01000001
-#define FETHIEN1 0x08000008
-#define FETH1_RST 0x04000004
-#define FETHIEN2 0x10000000
-#define FETH2_RST 0x08000000
-#define BCSR_PCI_MODE 0x01000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#ifdef CONFIG_SYS_LOWBOOT
-/* PQ2FADS flash HRCW = 0x0EB4B645 */
-#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
- ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
- ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
- ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
- )
-#else
-/* PQ2FADS BCSR HRCW = 0x0CB23645 */
-#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
- ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
- ( HRCW_BMS | HRCW_APPC10 ) |\
- ( HRCW_MODCK_H0101 ) \
- )
-#endif
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-#ifndef CONFIG_SYS_RAMBOOT
-# define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_SECT_SIZE 0x40000
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
-#else
-# define CONFIG_ENV_IS_IN_NVRAM 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-# define CONFIG_ENV_SIZE 0x200
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x100C0000
-#define CONFIG_SYS_SIUMCR 0x0A200000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
-#define CONFIG_SYS_OR0_PRELIM 0xFF800876
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
-#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
-
-/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
-#endif
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
-#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_OR2 0xFE002EC0
-#define CONFIG_SYS_PSDMR 0x824B36A3
-#define CONFIG_SYS_PSRT 0x13
-#define CONFIG_SYS_LSDMR 0x828737A3
-#define CONFIG_SYS_LSRT 0x13
-#define CONFIG_SYS_MPTPR 0x2800
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_OR2 0xFC002CC0
-#define CONFIG_SYS_PSDMR 0x834E24A3
-#define CONFIG_SYS_PSRT 0x13
-#define CONFIG_SYS_MPTPR 0x2800
-#else
-#define CONFIG_SYS_OR2 0xFF000CA0
-#define CONFIG_SYS_PSDMR 0x016EB452
-#define CONFIG_SYS_PSRT 0x21
-#define CONFIG_SYS_LSDMR 0x0086A522
-#define CONFIG_SYS_LSRT 0x21
-#define CONFIG_SYS_MPTPR 0x1900
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x04400000
-
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-
-/* PCI Memory map (if different from default map */
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
- PICMR_PREFETCH_EN)
-
-/*
- * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
- * these windows.
- */
-
-/*
- * Master window that allows the CPU to access PCI Memory (prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
-
-/*
- * Master window that allows the CPU to access PCI Memory (non-prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
-
-/*
- * Master window that allows the CPU to access PCI IO space.
- * This window will be setup with the first set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
-#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
-
-
-/* PCIBR0 - for PCI IO*/
-#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
-#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
-/* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
-
-#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
-
-#define CONFIG_HAS_ETH0
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_NETDEV eth0
-#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" __stringify(CONFIG_NETDEV) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=400000\0" \
- "console=ttyCPM0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#ifdef CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif /* CONFIG_NAND_SPL */
-#endif /* CONFIG_NAND_U_BOOT */
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#endif
*/
#define CONFIG_SYS_IMMR 0xE0000000
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
/*
* Arbiter Setup
*/
| OR_FCM_EHTR)
/* 0xFFFF8396 */
-#ifdef CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#endif
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* Environment
*/
-#if defined(CONFIG_NAND_U_BOOT)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_OFFSET (512 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_PHYS_64BIT 1
#endif
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
-#endif
-
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
- defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
#define CONFIG_SYS_BR4_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
*/
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif
-#endif
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
#undef CONFIG_SYS_RAMBOOT
-#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
-#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
* Environment
*/
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_PHYS_64BIT
#endif
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_RAMBOOT_NAND
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
-#endif
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
#undef CONFIG_SYS_RAMBOOT
-#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
*/
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024)\
- + CONFIG_SYS_NAND_BLOCK_SIZE)
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_RAMBOOT_NAND
-#endif
-
-#ifdef CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif /* CONFIG_NAND_SPL */
-#endif
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
-#ifndef CONFIG_NAND
#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#else
-#define CONFIG_SYS_NO_FLASH
-#endif
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_SYS_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-/* NAND Base Address */
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-/* chip select 1 - BCSR */
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
- | BR_MS_GPCM | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
- | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
/* chip select 1 - BCSR */
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
| OR_GPCM_EAD)
-#endif
/* Serial Port
* open - index 2
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_PHY_MARVELL
#endif
-#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000
-#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * U-Boot configuration for Analogue&Micro Rattler boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_MPC8248
-#define CPU_ID_STR "MPC8248"
-#else
-#define CPU_ID_STR "MPC8250"
-#endif /* CONFIG_MPC8248 */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
-
-#if (CONFIG_ETHER_INDEX == 1)
-
-/* - Rx clock is CLK11
- * - Tx clock is CLK10
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#elif (CONFIG_ETHER_INDEX == 2)
-
-/* - Rx clock is CLK15
- * - Tx clock is CLK14
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
- else iop->pdat &= ~0x00800000
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#if defined(CONFIG_CMD_JFFS2)
-#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00100000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=rattler-0"
-#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
-*/
-#endif /* CONFIG_CMD_JFFS2 */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-#define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
-
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 32
-#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
-#define CONFIG_SYS_SDRAM_OR 0xFE002EC0
-
-#define CONFIG_SYS_BCSR 0xFC000000
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x0E04C000
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x00000000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_PSDMR 0x8249A452
-#define CONFIG_SYS_PSRT 0x1F
-#define CONFIG_SYS_MPTPR 0x2000
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001)
-#define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
-#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
-
-#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * simpc8313 board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_NAND_U_BOOT
-
-#define CONFIG_E300 1
-#define CONFIG_MPC831x 1
-#define CONFIG_MPC8313 1
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
-#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_ELBC 1
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- *
- * TSEC1 is Marvell PHY 88E1118
- */
-
-#define CONFIG_SYS_33MHZ
-
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00001000
-#define CONFIG_SYS_MEMTEST_END 0x07f00000
-
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/*
- * Device configurations
- */
-#define CONFIG_TSEC1
-
-/*
- * DDR Setup
- */
- /* DDR is system memory*/
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED (512 << 20)
-
-#define CONFIG_SYS_DDRCDR (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
- /* 0x73000002 TODO ODR & DRN ? */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_NO_FLASH
-
-#if !defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF) /* 0x0004ff0f */
-
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-/* drivers/mtd/nand/nand.c */
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE2800000
-#endif
-#define CONFIG_SYS_FPGA_BASE 0xFF000000
-
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_NAND_FSL_ELBC 1
-
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit Port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-
-#ifdef CONFIG_NAND_SP
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
- /* NAND chip block size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
-#define NAND_CACHE_PAGES 32
-#elif defined(CONFIG_NAND_LP)
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
- | OR_FCM_PGS \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */
- /* NAND chip block size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
-#define NAND_CACHE_PAGES 64
-#else
-#error Page size of NAND not defined.
-#endif /* CONFIG_NAND_SP */
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
- | BR_PS_16 \
- | BR_MS_UPMA \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
- | OR_UPM_BCTLD)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB)
-
-/*
- * JFFS2 configuration
- */
-#define CONFIG_JFFS2_NAND
-#define CONFIG_JFFS2_DEV "nand0"
-
-/* mtdparts command line support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nand0=nand0"
-#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-
-#define CONFIG_GMII /* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Environment
- */
-#if defined(CONFIG_NAND_U_BOOT)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_OFFSET (768 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-
-/* Address and size of Redundant Environment Sector */
-#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_JFFS2
-
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) \
- + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
- | 0x20000000 /* reserved */ \
- | HRCWL_DDR_TO_SCB_CLK_2X1 \
- | HRCWL_CSB_TO_CLKIN_4X1 \
- | HRCWL_CORE_TO_CSB_2_5X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
- | HRCWH_PCI1_ARBITER_ENABLE \
- | HRCWH_CORE_ENABLE \
- | HRCWH_BOOTSEQ_DISABLE \
- | HRCWH_SW_WATCHDOG_DISABLE \
- | HRCWH_TSEC1M_IN_RGMII \
- | HRCWH_TSEC2M_IN_RGMII \
- | HRCWH_BIG_ENDIAN \
- | HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_LP
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
- | HRCWH_FROM_0XFFF00100 \
- | HRCWH_ROM_LOC_NAND_LP_8BIT \
- | HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
- | HRCWH_FROM_0XFFF00100 \
- | HRCWH_ROM_LOC_NAND_SP_8BIT \
- | HRCWH_RL_EXT_NAND)
-#endif
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
- | SICRH_ETSEC2_C \
- | SICRH_ETSEC2_D \
- | SICRH_ETSEC2_E \
- | SICRH_ETSEC2_F \
- | SICRH_ETSEC2_G \
- | SICRH_TSOBI1 \
- | SICRH_TSOBI2)
-#define CONFIG_SYS_SICRL (SICRL_LBC \
- | SICRL_USBDR_10 \
- | SICRL_ETSEC2_A)
-
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE \
- | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
- | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME simpc8313
-#define CONFIG_ROOTPATH "/tftpboot/"
-#define CONFIG_BOOTFILE "/tftpboot/uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot-nand.bin"
-#define CONFIG_FDTFILE "simpc8313.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 500000
-#define CONFIG_BOOTDELAY 5 /* 5 second delay */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=ae0000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "load_uboot=tftp 100000 u-boot-nand.bin\0" \
- "burn_uboot=nand erase u-boot 80000; " \
- "nand write 100000 u-boot $filesize\0" \
- "update_uboot=run load_uboot;run burn_uboot\0" \
- "mtdids=nand0=nand0\0" \
- "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
- "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
- "console=ttyS0,115200\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
+
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
+
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
+++ /dev/null
-/*
- * Copyright (C) 2003-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
- * This port was developed and tested on Revision C board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CPU_ID_STR "MPC8265"
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
-
-#if (CONFIG_ETHER_INDEX == 2)
-/*
- * - Rx clock is CLK13
- * - Tx clock is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Full duplex
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 64
-
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_LSDRAM_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_BCSR 0xFEA00000
-#define CONFIG_SYS_EEPROM 0xFEB00000
-#define CONFIG_SYS_FLSIMM_BASE 0xFF000000
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
-
-#define BCSR_PCI_MODE 0x01
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
- HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
- HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
- HRCW_MODCK_H0111 \
- ) /* 0x16848207 */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-# define CONFIG_ENV_SECT_SIZE 0x10000
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#else
-# define CONFIG_ENV_ADDR (CONFIG_SYS_EEPROM + 0x400)
-# define CONFIG_ENV_SIZE 0x1000
-# define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-#endif
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT (HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x42200000
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x90000000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_PSDMR /* 0x834DA43B */0x014DA43A
-#define CONFIG_SYS_PSRT 0x0F/* 0x0C */
-#define CONFIG_SYS_LSDMR 0x0085A562
-#define CONFIG_SYS_LSRT 0x0F
-#define CONFIG_SYS_MPTPR 0x4000
-
-#define CONFIG_SYS_PSDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
-#define CONFIG_SYS_PSDRAM_OR 0xFC0028C0
-#define CONFIG_SYS_LSDRAM_BR (CONFIG_SYS_LSDRAM_BASE | 0x00001861)
-#define CONFIG_SYS_LSDRAM_OR 0xFF803480
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00000801)
-#define CONFIG_SYS_OR0_PRELIM 0xFFE00856
-#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_EEPROM | 0x00000801)
-#define CONFIG_SYS_OR5_PRELIM 0xFFFF03F6
-#define CONFIG_SYS_BR6_PRELIM (CONFIG_SYS_FLSIMM_BASE | 0x00001801)
-#define CONFIG_SYS_OR6_PRELIM 0xFF000856
-#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR7_PRELIM 0xFFFF83F6
-
-#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
-
-#endif /* __CONFIG_H */
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/* NAND boot config */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
+/* Power */
+#define CONFIG_POWER_TPS65218
+
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
+#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
/* Enabling L2 Cache */
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
+/*
+ * When building U-Boot such that there is no previous loader
+ * we need to call board_early_init_f. This is taken care of in
+ * s_init when we have SPL used.
+ */
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
+
/* Now bring in the rest of the common code. */
#include <configs/ti_armv7_common.h>
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x30000000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
+#define CONFIG_ENV_OFFSET 0x110000
+#define CONFIG_ENV_OFFSET_REDUND 0x120000
+#ifdef MTDIDS_DEFAULT
+#undef MTDIDS_DEFAULT
+#endif
+#ifdef MTDPARTS_DEFAULT
+#undef MTDPARTS_DEFAULT
+#endif
+#define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \
+ "512k(QSPI.u-boot.backup)," \
+ "512k(QSPI.u-boot-spl-os)," \
+ "64k(QSPI.u-boot-env)," \
+ "64k(QSPI.u-boot-env.backup)," \
+ "8m(QSPI.kernel)," \
+ "-(QSPI.file-system)"
+#endif
+
/* SPI */
#undef CONFIG_OMAP3_SPI
#define CONFIG_TI_QSPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SPI_FLASH_BAR
#define CONFIG_QSPI_SEL_GPIO 48
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"setenv devnum ${mmcdev}; " \
+ "setenv devtype mmc; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${devnum};" \
"if run loadbootenv; then " \
/* PMIC */
#define CONFIG_PMIC
-#define CONFIG_PMIC_I2C
-#define CONFIG_PMIC_MAX77686
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX77686
#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
+#include "tegra-common-ums.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
-
+#define CONFIG_CMD_I2C
/* GPIO */
#define CONFIG_OMAP_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
#define CONFIG_CMD_NAND
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
"1m(u-boot),1m(u-boot-env)," \
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
/* Environment information */
#define CONFIG_BOOTDELAY 3
+++ /dev/null
-/*
- * (C) Copyright 2001, 2002
- * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-/* Environments */
-
-/* bootargs */
-#define CONFIG_BOOTARGS \
- "console=ttyS0,9600 init=/linuxrc " \
- "root=/dev/nfs rw nfsroot=192.168.0.1:" \
- "/tftpboot/target " \
- "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
- "255.255.255.0:debris:eth0:none " \
- "mtdparts=phys:12m(root),-(kernel)"
-
-/* bootcmd */
-#define CONFIG_BOOTCOMMAND \
- "tftp 800000 pImage; " \
- "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:eth0:none " \
- "mtdparts=phys:12m(root),-(kernel); " \
- "bootm 800000"
-
-/* bootdelay */
-#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
-
-/* baudrate */
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
-
-/* loads_echo */
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-
-/* ethaddr */
-#undef CONFIG_ETHADDR
-
-/* eth2addr */
-#undef CONFIG_ETH2ADDR
-
-/* eth3addr */
-#undef CONFIG_ETH3ADDR
-
-/* ipaddr */
-#define CONFIG_IPADDR 192.168.0.2
-
-/* serverip */
-#define CONFIG_SERVERIP 192.168.0.1
-
-/* autoload */
-#undef CONFIG_SYS_AUTOLOAD
-
-/* rootpath */
-#define CONFIG_ROOTPATH "/tftpboot/target"
-
-/* gatewayip */
-#define CONFIG_GATEWAYIP 192.168.0.1
-
-/* netmask */
-#define CONFIG_NETMASK 255.255.255.0
-
-/* hostname */
-#define CONFIG_HOSTNAME debris
-
-/* bootfile */
-#define CONFIG_BOOTFILE "pImage"
-
-/* loadaddr */
-#define CONFIG_LOADADDR 800000
-
-/* preboot */
-#undef CONFIG_PREBOOT
-
-/* clocks_in_mhz */
-#undef CONFIG_CLOCKS_IN_MHZ
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_DEBRIS 1
-
-#if 0
-#define USE_DINK32 1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_DRAM_SPEED 100 /* MHz */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE 0x00090000
-#define CONFIG_SYS_RAMBOOT 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0x7C000000
-#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
-#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
-#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=debris-0"
-#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
-*/
-
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
-#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
-#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
-#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
-
-/*
- * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
- * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
- */
-#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly. Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK 7372800
-
-#define CONFIG_SYS_NS16550_COM1 0xFF080000
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
-
-#define CONFIG_SYS_DLL_EXTEND 0x00
-#define CONFIG_SYS_PCI_HOLD_DEL 0x20
-
-#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
-
-#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
-
-#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#if 0
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
-#endif
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x04000000
-#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
-#define CONFIG_SYS_BANK1_ENABLE 1
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-#endif /* __CONFIG_H */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * U-Boot configuration for Embedded Planet EP8248 boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC8248
-#define CPU_ID_STR "MPC8248"
-
-#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-
-#define CONFIG_SYS_BCSR 0xFA000000
-
-/* Pass open firmware flat device tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
-
-/* Select ethernet configuration */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_ETHER_ON_FCC1 1
-/* - Rx clock is CLK10
- * - Tx clock is CLK11
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
-
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHER_ON_FCC2 1
-/* - Rx clock is CLK13
- * - Tx clock is CLK14
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 0 /* Not used - implemented in BCSR */
-
-#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
-#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
-#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
-
-#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
- else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
-
-#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
- else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
-
-#define MIIDELAY udelay(1)
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#if defined(CONFIG_CMD_JFFS2)
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
-#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-#define CONFIG_SYS_JFFS_CUSTOM_PART
-#endif
-
-#if defined(CONFIG_CMD_I2C)
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
-
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x01240200
-#define CONFIG_SYS_SYPCR 0xFFFF0683
-#define CONFIG_SYS_BCR 0x00000000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_MPTPR 0x1300
-#define CONFIG_SYS_PSDMR 0x82672522
-#define CONFIG_SYS_PSRT 0x4B
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
-#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
-#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
-
-#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
-
-#endif /* __CONFIG_H */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
/* Enable fdt support */
#define CONFIG_OF_CONTROL
#define CONFIG_S5P_SDHCI
#define CONFIG_SDHCI
#define CONFIG_MMC_SDMA
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MMC_DEFAULT_DEV 0
/* PWM */
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65090
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
/* PMIC */
-#define CONFIG_PMIC_MAX77686
+#define CONFIG_POWER_MAX77686
/* Sound */
#define CONFIG_CMD_SOUND
#define CONFIG_FIT
#define CONFIG_FIT_SIGNATURE
+#define CONFIG_IMAGE_FORMAT_LEGACY
#define CONFIG_CMD_FDT
#define CONFIG_CMD_HASH
#define CONFIG_RSA
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
+#include "tegra-common-ums.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 K2HK_UART0_BASE
+#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6)
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* NAND Configuration */
#define CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_NAND_ECCLAYOUT
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC8245 1
-#define CONFIG_KVME080 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_IPADDR 192.168.0.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.0.1
-
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 " \
- "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
- "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
- "kvme080:eth0:none " \
- "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
-
-#define CONFIG_BOOTCOMMAND \
- "tftp 800000 kvme080/uImage; " \
- "bootm 800000"
-
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_LOADS_ECHO 1
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#undef CONFIG_WATCHDOG
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_DS164x
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_NETCONSOLE
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000
-#define CONFIG_SYS_MEMTEST_END 0x07C00000
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x7C000000
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000
-#define CONFIG_SYS_NS16550_COM1 0xFF080000
-#define CONFIG_SYS_NS16550_COM2 0xFF080010
-#define CONFIG_SYS_NS16550_COM3 0xFF080020
-#define CONFIG_SYS_NS16550_COM4 0xFF080030
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
-#define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
-#define CONFIG_SYS_NVRAM_SIZE 0x7FFF8
-
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_PROTECT_CLEAR
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
-#define CONFIG_ENV_SIZE 0x400
-#define CONFIG_ENV_OFFSET 0
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 14745600
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-
-#define CONFIG_EEPRO100
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_SYS_CLK_FREQ 33333333
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5
-#endif
-
-#define CONFIG_SYS_DLL_EXTEND 0x00
-#define CONFIG_SYS_PCI_HOLD_DEL 0x20
-
-#define CONFIG_SYS_ROMNAL 15
-#define CONFIG_SYS_ROMFAL 31
-
-#define CONFIG_SYS_REFINT 430
-
-#define CONFIG_SYS_DBUS_SIZE2 1
-
-#define CONFIG_SYS_BSTOPRE 121
-#define CONFIG_SYS_REFREC 8
-#define CONFIG_SYS_RDLAT 4
-#define CONFIG_SYS_PRETOACT 3
-#define CONFIG_SYS_ACTTOPRE 5
-#define CONFIG_SYS_ACTORW 3
-#define CONFIG_SYS_SDMODE_CAS_LAT 3
-#define CONFIG_SYS_SDMODE_WRAP 0
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x04000000
-#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
-#define CONFIG_SYS_BANK1_ENABLE 1
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_BANK_ENABLE 0x03
-
-#define CONFIG_SYS_ODCR 0x75
-#define CONFIG_SYS_PGMAX 0x32
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#endif /* __CONFIG_H */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
-#define CONFIG_PMIC_FSL_MC34704
+#define CONFIG_POWER_FSL_MC34704
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
#define CONFIG_DOS_PARTITION
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
-#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
#define CONFIG_RTC_MC13XXX
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
-#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_POWER_FSL_MC13892
#define CONFIG_RTC_MC13XXX
/* MMC Configs */
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
-#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
#define CONFIG_SPL_OMAP3_ID_NAND
/* NAND boot config */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
/* Timeout values (in ticks) */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* NAND boot config */
#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_SYS_CACHELINE_SIZE 64
/* NAND boot config */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
/* Environment information */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
"128k(SPL.backup1)," \
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * quad100hd.h - configuration for Quad100hd board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
-#define CONFIG_405EP 1 /* Specifc 405EP support*/
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
-#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
-
-/* the environment is in the EEPROM by default */
-#define CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_HAS_ETH1 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0x01 /* PHY address */
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_PHY_RESET 1
-#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#undef CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * SDRAM
- *----------------------------------------------------------------------*/
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1
-
-/* FIX! SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*
- * JFFS2
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#ifdef CONFIG_SYS_KERNEL_IN_JFFS2
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
-#else /* kernel not in JFFS */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
-#endif
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_BASE_BAUD 691200
-#define CONFIG_BAUDRATE 115200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-/* the environment is located before u-boot */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET 0x00000000
-#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
-#endif
-
-/* partly from PPCBoot */
-/* NAND */
-#define CONFIG_NAND
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
-#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
-#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
-#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
-#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
-#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./arch/powerpc/cpu/ppc4xx/start.S */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- * Taken from PPCBoot board/icecube/icecube.h
- */
-
-/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
-#define CONFIG_SYS_EBC_PB0AP 0x04002480
-/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
-#define CONFIG_SYS_EBC_PB1AP 0x04005480
-#define CONFIG_SYS_EBC_PB1CR 0x60018000
-#define CONFIG_SYS_EBC_PB2AP 0x00000000
-#define CONFIG_SYS_EBC_PB2CR 0x00000000
-#define CONFIG_SYS_EBC_PB3AP 0x00000000
-#define CONFIG_SYS_EBC_PB3CR 0x00000000
-#define CONFIG_SYS_EBC_PB4AP 0x00000000
-#define CONFIG_SYS_EBC_PB4CR 0x00000000
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * Taken in part from PPCBoot board/icecube/icecube.h
- */
-/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
-#define CONFIG_SYS_GPIO0_OSRL 0x55555550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
-#define CONFIG_SYS_GPIO0_ODR 0x00000000
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/* ENVIRONMENT VARS */
-
-#define CONFIG_IPADDR 192.168.1.67
-#define CONFIG_SERVERIP 192.168.1.50
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 300000
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-
-#endif /* __CONFIG_H */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
+#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
-/*
- * Size of malloc() pool
- * 1MB = 0x100000, 0x100000 = 1024 * 1024
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+/* Size of malloc() pool.*/
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M)
+
/*
* select serial console configuration
*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
#define MTDIDS_DEFAULT "onenand0=samsung-onenand"
",7m(kernel)"\
",1m(log)"\
",12m(modem)"\
- ",60m(qboot)"\
- ",-(UBI)\0"
+ ",60m(qboot)\0"
-#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTCOMMAND "run ubifsboot"
+/* partitions definitions */
+#define PARTS_CSA "csa-mmc"
+#define PARTS_BOOTLOADER "u-boot"
+#define PARTS_BOOT "boot"
+#define PARTS_ROOT "platform"
+#define PARTS_DATA "data"
+#define PARTS_CSC "csc"
+#define PARTS_UMS "ums"
+
+#define CONFIG_DFU_ALT \
+ "u-boot raw 0x80 0x400;" \
+ "uImage ext4 0 2;" \
+ "exynos3-goni.dtb ext4 0 2;" \
+ ""PARTS_ROOT" part 0 5\0"
+
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+ "name="PARTS_BOOTLOADER",size=60MiB," \
+ "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
+ "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+ "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+ "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
+#define CONFIG_BOOTCOMMAND "run mmcboot"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
+#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \
" ${console} ${meminfo}"
#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \
- " rootfstype=cramfs " CONFIG_COMMON_BOOT
+#define CONFIG_BOOTARGS "root=/dev/mtdblock8 rootfstype=ext4 " \
+ CONFIG_COMMON_BOOT
#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \
" onenand write 0x32008000 0x0 0x100000\0"
-#define CONFIG_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6"
-
-#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc"
-
#define CONFIG_MISC_COMMON
#define CONFIG_MISC_INIT_R
"onenand erase 0x01560000 0x1eaa0000;" \
"onenand write 0x32000000 0x1260000 0x8C0000\0" \
"bootk=" \
- "onenand read 0x30007FC0 0xc00000 0x600000;" \
+ "run loaduimage;" \
"bootm 0x30007FC0\0" \
"flashboot=" \
"set bootargs root=/dev/mtdblock${bootblock} " \
- "rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \
+ "rootfstype=${rootfstype} ${opts} " \
"${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
"ubifsboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
- CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+ "${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"tftpboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
- CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
- CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \
- "bootm 0x30007FC0\0" \
+ "${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \
+ "; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \
"ramboot=" \
"set bootargs " CONFIG_RAMDISK_BOOT \
- " initrd=0x33000000,8M ramdisk=8192\0" \
+ "initrd=0x33000000,8M ramdisk=8192\0" \
"mmcboot=" \
- "set bootargs root=${mmcblk} rootfstype=${rootfstype}" \
- CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+ "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+ "rootfstype=${rootfstype} ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
"verify=n\0" \
- "rootfstype=cramfs\0" \
+ "rootfstype=ext4\0" \
"console=" CONFIG_DEFAULT_CONSOLE \
- "mtdparts=" MTDPARTS_DEFAULT \
"meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
- "mmcblk=/dev/mmcblk1p1\0" \
+ "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \
+ "mmcdev=0\0" \
+ "mmcbootpart=2\0" \
+ "mmcrootpart=5\0" \
+ "partitions=" PARTS_DEFAULT \
"bootblock=9\0" \
"ubiblock=8\0" \
"ubi=enabled\0" \
- "opts=always_resume=1"
+ "opts=always_resume=1\0" \
+ "dfu_alt_info=" CONFIG_DFU_ALT "\0"
-/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "Goni # "
#define CONFIG_DOS_PARTITION 1
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+/* write support for filesystems */
+#define CONFIG_FAT_WRITE
+#define CONFIG_EXT4_WRITE
+
+/* GPT */
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
#endif /* __CONFIG_H */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
/* Environment information */
#define CONFIG_BOOTDELAY 3
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA_COMMON_UMS_H_
+#define _TEGRA_COMMON_UMS_H
+
+#ifndef CONFIG_SPL_BUILD
+/* USB gadget, and mass storage protocol */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_CI_UDC
+#define CONFIG_CI_UDC_HAS_HOSTPC
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_G_DNL_VENDOR_NUM 0x0955
+#define CONFIG_G_DNL_PRODUCT_NUM 0x701A
+#define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+#endif
+
+#endif /* _TEGRA_COMMON_UMS_H */
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
+/*
+ * When building U-Boot such that there is no previous loader
+ * we need to call board_early_init_f. This is taken care of in
+ * s_init when we have SPL used.
+ */
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
+
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#endif
* under common/spl/. Given our generally common memory map, we set a
* number of related defaults and sizes here.
*/
-#ifndef CONFIG_NOR_BOOT
+#if !defined(CONFIG_NOR_BOOT) && \
+ !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_OS_BOOT
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
+#include "tegra-common-ums.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
-#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
#define CONFIG_RTC_MC13XXX
/* FIT support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
/* FDT support */
#define CONFIG_OF_CONTROL
#define DWMCI_BMOD_IDMAC_FB (1 << 1)
#define DWMCI_BMOD_IDMAC_EN (1 << 7)
+/* UHS register */
+#define DWMCI_DDR_MODE (1 << 16)
+
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
unsigned int version;
unsigned int clock;
unsigned int bus_hz;
+ unsigned int div;
int dev_index;
+ int dev_id;
int buswidth;
u32 clksel_val;
u32 fifoth_val;
#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */
#define PREFETCH_BLOCKS 2
-#define MAX_CLUSTSIZE 65536
+#ifndef CONFIG_FS_FAT_MAX_CLUSTSIZE
+#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
+#endif
+#define MAX_CLUSTSIZE CONFIG_FS_FAT_MAX_CLUSTSIZE
+
#define DIRENTSPERBLOCK (mydata->sect_size / sizeof(dir_entry))
#define DIRENTSPERCLUST ((mydata->clust_size * mydata->sect_size) / \
sizeof(dir_entry))
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
+ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */
COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
+ COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
+ COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
COMPAT_COUNT,
};
#ifndef _HASH_H
#define _HASH_H
+/*
+ * Maximum digest size for all algorithms we support. Having this value
+ * avoids a malloc() or C99 local declaration in common/cmd_hash.c.
+ */
+#define HASH_MAX_DIGEST_SIZE 32
+
+enum {
+ HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
+ HASH_FLAG_ENV = 1 << 1, /* Allow env vars */
+};
+
+#ifndef USE_HOSTCC
#if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY)
#define CONFIG_HASH_VERIFY
#endif
int size);
};
-/*
- * Maximum digest size for all algorithms we support. Having this value
- * avoids a malloc() or C99 local declaration in common/cmd_hash.c.
- */
-#define HASH_MAX_DIGEST_SIZE 32
-
-enum {
- HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
- HASH_FLAG_ENV = 1 << 1, /* Allow env vars */
-};
-
/**
* hash_command: Process a hash command for a particular algorithm
*
* @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
*/
int hash_lookup_algo(const char *algo_name, struct hash_algo **algop);
+#endif /* !USE_HOSTCC */
#endif
#endif /* USE_HOSTCC */
#if defined(CONFIG_FIT)
+#include <hash.h>
#include <libfdt.h>
#include <fdt_support.h>
# ifdef CONFIG_SPL_BUILD
#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
+#endif
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
#define FIT_FDT_PROP "fdt"
#define FIT_DEFAULT_PROP "default"
-#define FIT_MAX_HASH_LEN 20 /* max(crc32_len(4), sha1_len(20)) */
+#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
/* cmdline argument format parsing */
int fit_parse_conf(const char *spec, ulong addr_curr,
typedef int (*init_fnc_t)(void);
-int initcall_run_list(init_fnc_t init_sequence[]);
+int initcall_run_list(const init_fnc_t init_sequence[]);
}
#endif
+/**
+ * Check if the opcode's address should be sent only on the lower 8 bits
+ * @command: opcode to check
+ */
+static inline int nand_opcode_8bits(unsigned int command)
+{
+ switch (command) {
+ case NAND_CMD_READID:
+ case NAND_CMD_PARAM:
+ case NAND_CMD_GET_FEATURES:
+ case NAND_CMD_SET_FEATURES:
+ return 1;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
#endif /* __LINUX_MTD_NAND_H */
#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
+#define ELM_MAX_CHANNELS 8
+#define ELM_MAX_ERROR_COUNT 16
+
#ifndef __ASSEMBLY__
enum bch_level {
struct location {
u32 location_status; /* 0x800 */
u8 res1[124]; /* 0x804 */
- u32 error_location_x[16]; /* 0x880.... */
+ u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */
u8 res2[64]; /* 0x8c0 */
};
u8 res2[92]; /* 0x024 */
u32 page_ctrl; /* 0x080 */
u8 res3[892]; /* 0x084 */
- struct syndrome syndrome_fragments[8]; /* 0x400 */
+ struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */
u8 res4[512]; /* 0x600 */
- struct location error_location[8]; /* 0x800 */
+ struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */
};
-int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
u32 *error_locations);
int elm_config(enum bch_level level);
void elm_reset(void);
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
+#define GPMC_MAX_SECTORS 8
enum omap_ecc {
/* 1-bit ECC calculation by Software, Error detection by Software */
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH8_CODE_HW,
+ /* 16-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH16_CODE_HW,
};
struct gpmc_cs {
u32 bch_result_x[4];
};
+struct bch_res_4_6 {
+ u32 bch_result_x[3];
+};
+
struct gpmc {
u8 res1[0x10];
u32 sysconfig; /* 0x10 */
u8 res7[12]; /* 0x224 */
u32 testmomde_ctrl; /* 0x230 */
u8 res8[12]; /* 0x234 */
- struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
+ struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */
+ u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */
+ struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */
};
/* Used for board specific gpmc initialization */
#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
-#define MMC_MODE_HS 0x001
-#define MMC_MODE_HS_52MHz 0x010
-#define MMC_MODE_4BIT 0x100
-#define MMC_MODE_8BIT 0x200
-#define MMC_MODE_SPI 0x400
-#define MMC_MODE_HC 0x800
-
-#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
-#define MMC_MODE_WIDTH_BITS_SHIFT 8
+#define MMC_MODE_HS (1 << 0)
+#define MMC_MODE_HS_52MHz (1 << 1)
+#define MMC_MODE_4BIT (1 << 2)
+#define MMC_MODE_8BIT (1 << 3)
+#define MMC_MODE_SPI (1 << 4)
+#define MMC_MODE_HC (1 << 5)
+#define MMC_MODE_DDR_52MHz (1 << 6)
#define SD_DATA_4BIT 0x00040000
#define SD_HIGHSPEED_BUSY 0x00020000
#define SD_HIGHSPEED_SUPPORTED 0x00020000
-#define MMC_HS_TIMING 0x00000100
-#define MMC_HS_52MHZ 0x2
-
#define OCR_BUSY 0x80000000
#define OCR_HCS 0x40000000
#define OCR_VOLTAGE_MASK 0x007FFF80
#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
+#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
+#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
#if defined(CONFIG_MPC8272_FAMILY)
#ifdef CONFIG_MPC8247
#define CPU_ID_STR "MPC8247"
-#elif defined CONFIG_MPC8248
-#define CPU_ID_STR "MPC8248"
-#elif defined CONFIG_MPC8271
-#define CPU_ID_STR "MPC8271"
#else
#define CPU_ID_STR "MPC8272"
#endif
#include <part_efi.h>
/* disk/part_efi.c */
int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+/**
+ * get_partition_info_efi_by_name() - Find the specified GPT partition table entry
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_name - the specified table entry name
+ * @param info - returns the disk partition info
+ *
+ * @return - '0' on match, '-1' on no match, otherwise error
+ */
+int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc,
+ const char *name, disk_partition_t *info);
void print_part_efi (block_dev_desc_t *dev_desc);
int test_part_efi (block_dev_desc_t *dev_desc);
#include <power/power_chrg.h>
-enum {CHARGER_ENABLE, CHARGER_DISABLE};
-
#define CHARGER_MIN_CURRENT 200
#define CHARGER_MAX_CURRENT 2000
#define SAFEOUT_3_30V 0x03
/* Charger */
-enum {CHARGER_ENABLE, CHARGER_DISABLE};
#define DETBAT (1 << 2)
#define MBCICHFCSET (1 << 4)
#define MBCHOSTEN (1 << 6)
enum { PMIC_READ, PMIC_WRITE, };
enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, };
+enum {
+ PMIC_CHARGER_DISABLE,
+ PMIC_CHARGER_ENABLE,
+};
+
struct p_i2c {
unsigned char addr;
unsigned char *buf;
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TPS65090_PMIC_H_
+#define __TPS65090_PMIC_H_
+
+/* I2C device address for TPS65090 PMU */
+#define TPS65090_I2C_ADDR 0x48
+
+enum {
+ /* Status register fields */
+ TPS65090_ST1_OTC = 1 << 0,
+ TPS65090_ST1_OCC = 1 << 1,
+ TPS65090_ST1_STATE_SHIFT = 4,
+ TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT,
+};
+
+/**
+ * Enable FET
+ *
+ * @param fet_id FET ID, value between 1 and 7
+ * @return 0 on success, non-0 on failure
+ */
+int tps65090_fet_enable(unsigned int fet_id);
+
+/**
+ * Disable FET
+ *
+ * @param fet_id FET ID, value between 1 and 7
+ * @return 0 on success, non-0 on failure
+ */
+int tps65090_fet_disable(unsigned int fet_id);
+
+/**
+ * Is FET enabled?
+ *
+ * @param fet_id FET ID, value between 1 and 7
+ * @return 1 enabled, 0 disabled, negative value on failure
+ */
+int tps65090_fet_is_enabled(unsigned int fet_id);
+
+/**
+ * Enable / disable the battery charger
+ *
+ * @param enable 0 to disable charging, non-zero to enable
+ */
+int tps65090_set_charge_enable(int enable);
+
+/**
+ * Check whether we have enabled battery charging
+ *
+ * @return 1 if enabled, 0 if disabled
+ */
+int tps65090_get_charging(void);
+
+/**
+ * Return the value of the status register
+ *
+ * @return status register value, or -1 on error
+ */
+int tps65090_get_status(void);
+
+/**
+ * Initialize the TPS65090 PMU.
+ *
+ * @return 0 on success, non-0 on failure
+ */
+int tps65090_init(void);
+
+#endif /* __TPS65090_PMIC_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __POWER_TPS65218_H__
+#define __POWER_TPS65218_H__
+
+/* I2C chip address */
+#define TPS65218_CHIP_PM 0x24
+
+/* Registers */
+enum {
+ TPS65218_CHIPID = 0x00,
+ TPS65218_INT1,
+ TPS65218_INT2,
+ TPS65218_INT_MASK1,
+ TPS65218_INT_MASK2,
+ TPS65218_STATUS,
+ TPS65218_CONTROL,
+ TPS65218_FLAG,
+ TPS65218_PASSWORD = 0x10,
+ TPS65218_ENABLE1,
+ TPS65218_ENABLE2,
+ TPS65218_CONFIG1,
+ TPS65218_CONFIG2,
+ TPS65218_CONFIG3,
+ TPS65218_DCDC1,
+ TPS65218_DCDC2,
+ TPS65218_DCDC3,
+ TPS65218_DCDC4,
+ TPS65218_SLEW,
+ TPS65218_LDO1,
+ TPS65218_SEQ1 = 0x20,
+ TPS65218_SEQ2,
+ TPS65218_SEQ3,
+ TPS65218_SEQ4,
+ TPS65218_SEQ5,
+ TPS65218_SEQ6,
+ TPS65218_SEQ7,
+ TPS65218_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65218_PROT_LEVEL_NONE 0x00
+#define TPS65218_PROT_LEVEL_1 0x01
+#define TPS65218_PROT_LEVEL_2 0x02
+
+#define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00
+#define TPS65218_PASSWORD_UNLOCK 0x7D
+
+#define TPS65218_DCDC_GO 0x80
+
+#define TPS65218_MASK_ALL_BITS 0xFF
+
+#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19
+#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30
+
+int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+ uchar mask);
+int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+#endif /* __POWER_TPS65218_H__ */
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
- COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
+ COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
COMPAT(SANDBOX_HOST_EMULATION, "sandbox,host-emulation"),
COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"),
+ COMPAT(TI_TPS65090, "ti,tps65090"),
+ COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
#include <common.h>
#include <initcall.h>
-int initcall_run_list(init_fnc_t init_sequence[])
+DECLARE_GLOBAL_DATA_PTR;
+
+int initcall_run_list(const init_fnc_t init_sequence[])
{
- init_fnc_t *init_fnc_ptr;
+ const init_fnc_t *init_fnc_ptr;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- debug("initcall: %p\n", *init_fnc_ptr);
+ unsigned long reloc_ofs = 0;
+
+ if (gd->flags & GD_FLG_RELOC)
+ reloc_ofs = gd->reloc_off;
+ debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs);
if ((*init_fnc_ptr)()) {
- debug("initcall sequence %p failed at call %p\n",
- init_sequence, *init_fnc_ptr);
+ printf("initcall sequence %p failed at call %p\n",
+ init_sequence,
+ (char *)*init_fnc_ptr - reloc_ofs);
return -1;
}
}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-# (C) Copyright 2008 Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PAD_TO := 0xfff04000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o ticks.o
-COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
- time.o cache.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-$(obj)/start.S:
- ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/sdram.c:
- ln -sf $(srctree)/board/$(BOARDDIR)/sdram.c $@
-
-$(obj)/$(BOARD).c:
- ln -sf $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
-
-$(obj)/ns16550.c:
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/spl_minimal.c:
- ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
-
-$(obj)/cache.c:
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/time.c:
- ln -sf $(srctree)/arch/powerpc/lib/time.c $@
-
-$(obj)/ticks.S:
- ln -sf $(srctree)/arch/powerpc/lib/ticks.S $@
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- . = 0xfff00000;
- .text : {
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- . = ALIGN(8);
- .data : {
- *(.data*)
- *(.sdata*)
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-
- . = ALIGN(8);
- __bss_start = .;
- .bss (NOLOAD) : {
- *(.*bss)
- }
- __bss_end = .;
-}
-ENTRY(_start)
-ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-
-u32 sysclk_tbl[] = {
- 33333000, 39999600, 49999500, 66666000,
- 83332500, 99999000, 133332000, 166665000
-};
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, bus_clk, sys_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- /* for FPGA */
- set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
- set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-#else
-#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
-#endif
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
-#define SYSCLK_66 66666666
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- uint plat_ratio, bus_clk, sys_clk;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- sys_clk = SYSCLK_66;
-
- plat_ratio = gur->porpllsr & 0x0000003e;
- plat_ratio >>= 1;
- bus_clk = plat_ratio * sys_clk;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to DDR and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-
-u32 sysclk_tbl[] = {
- 33333000, 39999600, 49999500, 66666000,
- 83332500, 99999000, 133332000, 166665000
-};
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, bus_clk, sys_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- /* for FPGA */
- set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
- set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-#else
-#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
-#endif
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# Copyright 2010-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Author: Roy Zang <tie-fei.zang@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Fixed sdram init -- doesn't use serial presence detect. */
-void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
- set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
-
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
- __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
- __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
- __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
- /* Set, but do not enable the memory */
- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
- /* Initialize the DDR3 */
- sdram_init();
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-# (C) Copyright 2008 Freescale Semiconductor
-# (C) Copyright Sheldon Instruments, Inc. 2008
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(srctree)/$(src)/config.mk
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o ticks.o
-COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
- time.o cache.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -s $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/sdram.c:
- @rm -f $@
- ln -s $(srctree)/board/$(BOARDDIR)/sdram.c $@
-
-$(obj)/$(BOARD).c:
- @rm -f $@
- ln -s $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -s $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
-
-$(obj)/cache.c:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/time.c:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/lib/time.c $@
-
-$(obj)/ticks.S:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/lib/ticks.S $@
+++ /dev/null
-ifdef CONFIG_NAND_LP
-PAD_TO = 0xFFF20000
-else
-PAD_TO = 0xFFF04000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- . = 0xfff00000;
- .text : {
- *(.text*)
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- . = ALIGN(8);
- .data : {
- *(.data*)
- *(.sdata*)
- _GOT2_TABLE_ = .;
- *(.got2)
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-
- . = ALIGN(8);
- __bss_start = .;
- .bss (NOLOAD) : { *(.*bss) }
- __bss_end = .;
-}
-ENTRY(_start)
-ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
+++ /dev/null
-/*
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-
-#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
-
-
-#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
-/*
- * NAND command for small page NAND devices (512)
- */
-static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
-{
- struct nand_chip *this = mtd->priv;
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
-
- while (!this->dev_ready(mtd))
- ;
-
- /* Begin command latch cycle */
- this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- /* Set ALE and clear CLE to start address cycle */
- /* Column address */
- this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
- this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
- NAND_CTRL_ALE); /* A[24:17] */
-#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
- /* One more address cycle for devices > 32MiB */
- this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
- NAND_CTRL_ALE); /* A[28:25] */
-#endif
- /* Latch in address */
- this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-
- /*
- * Wait a while for the data to be ready
- */
- while (!this->dev_ready(mtd))
- ;
-
- return 0;
-}
-#else
-/*
- * NAND command for large page NAND devices (2k)
- */
-static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
-{
- struct nand_chip *this = mtd->priv;
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
- void (*hwctrl)(struct mtd_info *mtd, int cmd,
- unsigned int ctrl) = this->cmd_ctrl;
-
- while (!this->dev_ready(mtd))
- ;
-
- /* Emulate NAND_CMD_READOOB */
- if (cmd == NAND_CMD_READOOB) {
- offs += CONFIG_SYS_NAND_PAGE_SIZE;
- cmd = NAND_CMD_READ0;
- }
-
- /* Shift the offset from byte addressing to word addressing. */
- if (this->options & NAND_BUSWIDTH_16)
- offs >>= 1;
-
- /* Begin command latch cycle */
- hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- /* Set ALE and clear CLE to start address cycle */
- /* Column address */
- hwctrl(mtd, offs & 0xff,
- NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
- /* Row address */
- hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(mtd, ((page_addr >> 8) & 0xff),
- NAND_CTRL_ALE); /* A[27:20] */
-#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- /* One more address cycle for devices > 128MiB */
- hwctrl(mtd, (page_addr >> 16) & 0x0f,
- NAND_CTRL_ALE); /* A[31:28] */
-#endif
- /* Latch in address */
- hwctrl(mtd, NAND_CMD_READSTART,
- NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-
- /*
- * Wait a while for the data to be ready
- */
- while (!this->dev_ready(mtd))
- ;
-
- return 0;
-}
-#endif
-
-static int nand_is_bad_block(struct mtd_info *mtd, int block)
-{
- struct nand_chip *this = mtd->priv;
-
- nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
-
- /*
- * Read one byte (or two if it's a 16 bit chip).
- */
- if (this->options & NAND_BUSWIDTH_16) {
- if (readw(this->IO_ADDR_R) != 0xffff)
- return 1;
- } else {
- if (readb(this->IO_ADDR_R) != 0xff)
- return 1;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
-static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
-{
- struct nand_chip *this = mtd->priv;
- u_char ecc_calc[ECCTOTAL];
- u_char ecc_code[ECCTOTAL];
- u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
- int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
- int eccsteps = ECCSTEPS;
- uint8_t *p = dst;
-
- nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
- this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
- nand_command(mtd, block, page, 0, NAND_CMD_READ0);
-
- /* Pick the ECC bytes out of the oob data */
- for (i = 0; i < ECCTOTAL; i++)
- ecc_code[i] = oob_data[nand_ecc_pos[i]];
-
-
- for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(mtd, NAND_ECC_READ);
- this->read_buf(mtd, p, eccsize);
- this->ecc.calculate(mtd, p, &ecc_calc[i]);
- this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
- }
-
- return 0;
-}
-#else
-static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
-{
- struct nand_chip *this = mtd->priv;
- u_char ecc_calc[ECCTOTAL];
- u_char ecc_code[ECCTOTAL];
- u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
- int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
- int eccsteps = ECCSTEPS;
- uint8_t *p = dst;
-
- nand_command(mtd, block, page, 0, NAND_CMD_READ0);
-
- for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(mtd, NAND_ECC_READ);
- this->read_buf(mtd, p, eccsize);
- this->ecc.calculate(mtd, p, &ecc_calc[i]);
- }
- this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
-
- /* Pick the ECC bytes out of the oob data */
- for (i = 0; i < ECCTOTAL; i++)
- ecc_code[i] = oob_data[nand_ecc_pos[i]];
-
- eccsteps = ECCSTEPS;
- p = dst;
-
- for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- /* No chance to do something with the possible error message
- * from correct_data(). We just hope that all possible errors
- * are corrected by this routine.
- */
- this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
- }
-
- return 0;
-}
-#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */
-
-static int nand_load(struct mtd_info *mtd, unsigned int offs,
- unsigned int uboot_size, uchar *dst)
-{
- unsigned int block, lastblock;
- unsigned int page;
-
- /*
- * offs has to be aligned to a page address!
- */
- block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
- lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
- page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
-
- while (block <= lastblock) {
- if (!nand_is_bad_block(mtd, block)) {
- /*
- * Skip bad blocks
- */
- while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
- nand_read_page(mtd, block, page, dst);
- dst += CONFIG_SYS_NAND_PAGE_SIZE;
- page++;
- }
-
- page = 0;
- } else {
- lastblock++;
- }
-
- block++;
- }
-
- return 0;
-}
-
-/*
- * The main entry for NAND booting. It's necessary that SDRAM is already
- * configured and available since this code loads the main U-Boot image
- * from NAND into SDRAM and starts it from there.
- */
-void nand_boot(void)
-{
- struct nand_chip nand_chip;
- nand_info_t nand_info;
- __attribute__((noreturn)) void (*uboot)(void);
-
- /*
- * Init board specific nand support
- */
- nand_chip.select_chip = NULL;
- nand_info.priv = &nand_chip;
- nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand_chip.dev_ready = NULL; /* preset to NULL */
- nand_chip.options = 0;
- board_nand_init(&nand_chip);
-
- if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info, 0);
-
- /*
- * Load U-Boot image from NAND into RAM
- */
- nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
-
-#ifdef CONFIG_NAND_ENV_DST
- nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
-#endif
-#endif
-
- if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info, -1);
-
- /*
- * Jump to U-Boot image
- */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- (*uboot)();
-}
+++ /dev/null
-/*
- * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
- *
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (c) 2008 Freescale Semiconductor, Inc.
- * Author: Scott Wood <scottwood@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/fsl_lbc.h>
-#include <linux/mtd/nand.h>
-
-#define WINDOW_SIZE 8192
-
-static void nand_wait(void)
-{
- fsl_lbc_t *regs = LBC_BASE_ADDR;
-
- for (;;) {
- uint32_t status = in_be32(®s->ltesr);
-
- if (status == 1)
- return;
-
- if (status & 1) {
- puts("read failed (ltesr)\n");
- for (;;);
- }
- }
-}
-
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
-{
- fsl_lbc_t *regs = LBC_BASE_ADDR;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
- const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
- const int block_shift = large ? 17 : 14;
- const int block_size = 1 << block_shift;
- const int page_size = large ? 2048 : 512;
- const int bad_marker = large ? page_size + 0 : page_size + 5;
- int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
- int pos = 0;
-
- if (offs & (block_size - 1)) {
- puts("bad offset\n");
- for (;;);
- }
-
- if (large) {
- fmr |= FMR_ECCM;
- __raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
- (NAND_CMD_READSTART << FCR_CMD1_SHIFT),
- ®s->fcr);
- __raw_writel(
- (FIR_OP_CW0 << FIR_OP0_SHIFT) |
- (FIR_OP_CA << FIR_OP1_SHIFT) |
- (FIR_OP_PA << FIR_OP2_SHIFT) |
- (FIR_OP_CW1 << FIR_OP3_SHIFT) |
- (FIR_OP_RBW << FIR_OP4_SHIFT),
- ®s->fir);
- } else {
- __raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, ®s->fcr);
- __raw_writel(
- (FIR_OP_CW0 << FIR_OP0_SHIFT) |
- (FIR_OP_CA << FIR_OP1_SHIFT) |
- (FIR_OP_PA << FIR_OP2_SHIFT) |
- (FIR_OP_RBW << FIR_OP3_SHIFT),
- ®s->fir);
- }
-
- __raw_writel(0, ®s->fbcr);
-
- while (pos < uboot_size) {
- int i = 0;
- __raw_writel(offs >> block_shift, ®s->fbar);
-
- do {
- int j;
- unsigned int page_offs = (offs & (block_size - 1)) << 1;
-
- __raw_writel(~0, ®s->ltesr);
- __raw_writel(0, ®s->lteatr);
- __raw_writel(page_offs, ®s->fpar);
- __raw_writel(fmr, ®s->fmr);
- sync();
- __raw_writel(0, ®s->lsor);
- nand_wait();
-
- page_offs %= WINDOW_SIZE;
-
- /*
- * If either of the first two pages are marked bad,
- * continue to the next block.
- */
- if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
- puts("skipping\n");
- offs = (offs + block_size) & ~(block_size - 1);
- pos &= ~(block_size - 1);
- break;
- }
-
- for (j = 0; j < page_size; j++)
- dst[pos + j] = buf[page_offs + j];
-
- pos += page_size;
- offs += page_size;
- } while ((offs & (block_size - 1)) && (pos < uboot_size));
- }
-}
-
-/*
- * The main entry for NAND booting. It's necessary that SDRAM is already
- * configured and available since this code loads the main U-Boot image
- * from NAND into SDRAM and starts it from there.
- */
-void nand_boot(void)
-{
- __attribute__((noreturn)) void (*uboot)(void);
-
- /*
- * Load U-Boot image from NAND into RAM
- */
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
-
- /*
- * Jump to U-Boot image
- */
- puts("transfering control\n");
- /*
- * Clean d-cache and invalidate i-cache, to
- * make sure that no stale data is executed.
- */
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- uboot();
-}
cmd_xzmisc = (cat $(filter-out FORCE,$^) | \
xz --check=crc32 --lzma2=dict=1MiB) > $@ || \
(rm -f $@ ; false)
+
+# Additional commands for U-Boot
+#
+# mkimage
+# ---------------------------------------------------------------------------
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
"setenv list ${list}3", strlen("setenv list 1"), 0);
assert(!strcmp("1", getenv("list")));
+ assert(run_command("false", 0) == 1);
+ assert(run_command("echo", 0) == 0);
+ assert(run_command_list("false", -1, 0) == 1);
+ assert(run_command_list("echo", -1, 0) == 0);
+
#ifdef CONFIG_SYS_HUSH_PARSER
/* Test the 'test' command */
omapimage.o \
os_support.o \
pblimage.o \
+ pbl_crc32.o \
sha1.o \
sha256.o \
ublimage.o \
# TODO(sjg@chromium.org): Is this correct on Mac OS?
-# MXSImage needs LibSSL
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
-HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
endif
ifdef CONFIG_FIT_SIGNATURE
-HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto
-
# This affects include/image.h, but including the board config file
# is tricky, so manually define this options here.
HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE
endif
+# MXSImage needs LibSSL
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
+HOSTLOADLIBES_mkimage$(SFX) += -lssl -lcrypto
+endif
+
+HOSTLOADLIBES_dumpimage$(SFX) := $(HOSTLOADLIBES_mkimage$(SFX))
+HOSTLOADLIBES_fit_info$(SFX) := $(HOSTLOADLIBES_mkimage$(SFX))
+HOSTLOADLIBES_fit_check_sign$(SFX) := $(HOSTLOADLIBES_mkimage$(SFX))
+
hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl$(SFX)
hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl$(SFX)
HOSTCFLAGS_mkexynosspl$(SFX).o := -pedantic
void *fit_blob;
char *fdtfile = NULL;
char *keyfile = NULL;
- char cmdname[50];
+ char cmdname[256];
int ret;
void *key_blob;
int c;
- strcpy(cmdname, *argv);
+ strncpy(cmdname, *argv, sizeof(cmdname) - 1);
+ cmdname[sizeof(cmdname) - 1] = '\0';
while ((c = getopt(argc, argv, "f:k:")) != -1)
switch (c) {
case 'f':
#include "imagetool.h"
#include "mxsimage.h"
+#include "pbl_crc32.h"
#include <image.h>
return sb_aes_init(ictx, iv, enc);
}
-/*
- * CRC32
- */
-static uint32_t crc32(uint8_t *data, uint32_t len)
-{
- const uint32_t poly = 0x04c11db7;
- uint32_t crc32 = 0xffffffff;
- unsigned int byte, bit;
-
- for (byte = 0; byte < len; byte++) {
- crc32 ^= data[byte] << 24;
-
- for (bit = 8; bit > 0; bit--) {
- if (crc32 & (1UL << 31))
- crc32 = (crc32 << 1) ^ poly;
- else
- crc32 = (crc32 << 1);
- }
- }
-
- return crc32;
-}
-
/*
* Debug
*/
ccmd->load.address = dest;
ccmd->load.count = cctx->length;
- ccmd->load.crc32 = crc32(cctx->data, cctx->length);
+ ccmd->load.crc32 = pbl_crc32(0,
+ (const char *)cctx->data,
+ cctx->length);
cctx->size = sizeof(*ccmd) + cctx->length;
EVP_DigestUpdate(&ictx->md_ctx, cctx->data, asize);
sb_aes_crypt(ictx, cctx->data, cctx->data, asize);
- if (ccmd->load.crc32 != crc32(cctx->data, asize)) {
+ if (ccmd->load.crc32 != pbl_crc32(0,
+ (const char *)cctx->data,
+ asize)) {
fprintf(stderr,
"ERR: SB LOAD command payload CRC32 invalid!\n");
return -EINVAL;
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Cleaned up and refactored by Charles Manning.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include "pblimage.h"
+
+static uint32_t crc_table[256];
+static int crc_table_valid;
+
+static void make_crc_table(void)
+{
+ uint32_t mask;
+ int i, j;
+ uint32_t poly; /* polynomial exclusive-or pattern */
+
+ if (crc_table_valid)
+ return;
+
+ /*
+ * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10
+ * + x11 + x12 + x16 + x22 + x23 + x26 + x32.
+ */
+ poly = 0x04c11db7;
+
+ for (i = 0; i < 256; i++) {
+ mask = i << 24;
+ for (j = 0; j < 8; j++) {
+ if (mask & 0x80000000)
+ mask = (mask << 1) ^ poly;
+ else
+ mask <<= 1;
+ }
+ crc_table[i] = mask;
+ }
+
+ crc_table_valid = 1;
+}
+
+uint32_t pbl_crc32(uint32_t in_crc, const char *buf, uint32_t len)
+{
+ uint32_t crc32_val;
+ int i;
+
+ make_crc_table();
+
+ crc32_val = ~in_crc;
+
+ for (i = 0; i < len; i++)
+ crc32_val = (crc32_val << 8) ^
+ crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)];
+
+ return crc32_val;
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef PBLCRC32_H
+#define PBLCRC32_H
+
+#include <stdint.h>
+uint32_t pbl_crc32(uint32_t in_crc, const char *buf, uint32_t len);
+
+#endif
#include "imagetool.h"
#include <image.h>
#include "pblimage.h"
+#include "pbl_crc32.h"
/*
* Initialize to an invalid value.
fclose(fd);
}
-static uint32_t crc_table[256];
-
-static void make_crc_table(void)
-{
- uint32_t mask;
- int i, j;
- uint32_t poly; /* polynomial exclusive-or pattern */
-
- /*
- * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10
- * + x11 + x12 + x16 + x22 + x23 + x26 + x32.
- */
- poly = 0x04c11db7;
-
- for (i = 0; i < 256; i++) {
- mask = i << 24;
- for (j = 0; j < 8; j++) {
- if (mask & 0x80000000)
- mask = (mask << 1) ^ poly;
- else
- mask <<= 1;
- }
- crc_table[i] = mask;
- }
-}
-
-unsigned long pbl_crc32(unsigned long crc, const char *buf, uint32_t len)
-{
- uint32_t crc32_val = 0xffffffff;
- uint32_t xor = 0x0;
- int i;
-
- make_crc_table();
-
- for (i = 0; i < len; i++)
- crc32_val = (crc32_val << 8) ^
- crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)];
-
- crc32_val = crc32_val ^ xor;
- if (crc32_val < 0) {
- crc32_val += 0xffffffff;
- crc32_val += 1;
- }
- return crc32_val;
-}
-
static uint32_t reverse_byte(uint32_t val)
{
uint32_t temp;
projects / karo-tx-uboot.git / commitdiff