#ifndef __M28_INIT_H__
#define __M28_INIT_H__
-void early_delay(int delay);
-
void mxs_power_init(void);
#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
static bd_t bdata __section(".data");
#endif
-/*
- * This delay function is intended to be used only in early stage of boot, where
- * clock are not set up yet. The timer used here is reset on every boot and
- * takes a few seconds to roll. The boot doesn't take that long, so to keep the
- * code simple, it doesn't take rolling into consideration.
- */
-/*
- * There's nothing to be taken into consideration for the rollover.
- * Two's complement arithmetic used correctly does all that's needed
- * automagically.
- */
-void early_delay(int delay)
-{
- struct mxs_digctl_regs *digctl_regs =
- (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
- u32 start = readl(&digctl_regs->hw_digctl_microseconds);
-
- while (readl(&digctl_regs->hw_digctl_microseconds) - start < delay);
-}
-
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
static const iomux_cfg_t iomux_boot[] = {
#if defined(CONFIG_SOC_MX23)
debug("SPL: Setting mx23 VDDMEM\n");
/* We must wait before and after disabling the current limiter! */
- early_delay(10000);
+ udelay(10000);
clrbits_le32(&power_regs->hw_power_vddmemctrl,
POWER_VDDMEMCTRL_ENABLE_ILIMIT);
- early_delay(10000);
+ udelay(10000);
}
for (;;) {
if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
break;
- early_delay(1000);
+ udelay(1000);
}
/* Adjust EMI port priority. */
clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
- early_delay(20000);
+ udelay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
void mxs_mem_init(void)
{
- early_delay(11000);
+ udelay(11000);
mxs_mem_init_clock();
debug("SPL: Switching CPU core clock source to PLL\n");
+ writel(CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
/*
- * TODO: Are we really? It looks like we turn on PLL0, but we then
- * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
- * set by mxs_power_clock2xtal()). Clearing this bit here seems to
- * introduce some instability (causing the CPU core to hang). Maybe
- * we aren't giving PLL0 enough time to stabilise?
+ * The PLL is documented to lock within 10 µs from setting
+ * the POWER bit.
*/
- setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
- CLKCTRL_PLL0CTRL0_POWER);
- early_delay(100);
+ udelay(15);
/*
- * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
+ * TODO: Should the PLL0 FORCE_LOCK bit be set here followed by a
* wait on the PLL0 LOCK bit?
*/
- setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
- CLKCTRL_CLKSEQ_BYPASS_CPU);
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
}
static int mxs_power_wait_rtc_stat(u32 mask)
struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
- early_delay(1);
+ udelay(1);
if (timeout-- < 0)
break;
}
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
- early_delay(500000);
+ udelay(500000);
volt = mxs_get_batt_volt();
{
debug("SPL: Pre-Configuring power block\n");
- debug("SPL: Pre-Configuring power block\n");
-
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
if (!fixed_batt_supply) {
/* 5V to battery handoff ... FIXME */
- setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl_set);
+ udelay(30);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl_clr);
}
}
{
debug("SPL: Configuring common 4P2 regulator params\n");
- debug("SPL: Configuring common 4P2 regulator params\n");
-
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
POWER_CTRL_ENIRQ_VDD5V_DROOP;
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_clr);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
- clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, &power_regs->hw_power_ctrl_clr);
/*
* Recording orignal values that will be modified temporarlily
* Disable mechanisms that get erroneously tripped by when setting
* the DCDC4P2 EN_DCDC
*/
- clrbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_VBUSVALID_5VDETECT |
- POWER_5VCTRL_VBUSVALID_TRSH_MASK);
+ writel(POWER_5VCTRL_VBUSVALID_5VDETECT |
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK,
+ &power_regs->hw_power_5vctrl);
writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
if (xfer) {
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_DCDC_XFER);
- early_delay(20);
- clrbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_DCDC_XFER);
-
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_ENABLE_DCDC);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl);
+ udelay(20);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl_clr);
+
+ writel(POWER_5VCTRL_ENABLE_DCDC,
+ &power_regs->hw_power_5vctrl_set);
} else {
- setbits_le32(&power_regs->hw_power_dcdc4p2,
- POWER_DCDC4P2_ENABLE_DCDC);
+ writel(POWER_DCDC4P2_ENABLE_DCDC,
+ &power_regs->hw_power_dcdc4p2);
}
- early_delay(25);
+ udelay(25);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
if (!pwd_bo)
- clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
+ writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_clr);
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
writel(POWER_CTRL_VBUS_VALID_IRQ,
&power_regs->hw_power_ctrl_clr);
if (prev_5v_droop)
- clrbits_le32(&power_regs->hw_power_ctrl,
- POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
+ &power_regs->hw_power_ctrl_set);
else
- setbits_le32(&power_regs->hw_power_ctrl,
- POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
+ &power_regs->hw_power_ctrl_clr);
}
/**
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
- setbits_le32(&power_regs->hw_power_5vctrl,
- 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+ writel(0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET,
+ &power_regs->hw_power_5vctrl_set);
} else {
tmp = (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
POWER_STS_DCDC_4P2_BO)) {
tmp = readl(&power_regs->hw_power_5vctrl);
tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
- early_delay(100);
+ udelay(100);
writel(tmp, &power_regs->hw_power_5vctrl);
break;
} else {
tmp2 |= tmp <<
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
writel(tmp2, &power_regs->hw_power_5vctrl);
- early_delay(100);
+ udelay(100);
}
}
}
{
debug("SPL: Switching DC-DC converters to 4P2\n");
- debug("SPL: Switching DC-DC converters to 4P2\n");
-
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
debug("SPL: Already switched - aborting\n");
mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
- early_delay(20);
+ udelay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
- early_delay(20);
+ udelay(20);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
/*
{
debug("SPL: Booting from 5V supply\n");
- debug("SPL: Booting from 5V supply\n");
-
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
{
debug("SPL: Configuring power block to boot from battery\n");
- debug("SPL: Configuring power block to boot from battery\n");
-
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_clr);
+ writel(POWER_5VCTRL_ENABLE_DCDC,
+ &power_regs->hw_power_5vctrl_clr);
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
/* 5V to battery handoff. */
- setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_set);
+ udelay(30);
+ writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_clr);
writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
clrbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET);
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_ENABLE_DCDC);
+ writel(POWER_5VCTRL_ENABLE_DCDC, &power_regs->hw_power_5vctrl_set);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
{
debug("SPL: Configuring power block to boot from 5V input\n");
- debug("SPL: Configuring power block to boot from 5V input\n");
-
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
return;
}
- early_delay(1000);
+ udelay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
debug("SPL: 5V VDD good (after delay)\n");
mxs_boot_valid_5v();
{
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_ENABLE_DCDC |
+ writel(POWER_5VCTRL_ENABLE_DCDC |
POWER_5VCTRL_ILIMIT_EQ_ZERO |
POWER_5VCTRL_PWDN_5VBRNOUT |
- POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+ POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
*/
static void mxs_init_batt_bo(void)
{
- debug("SPL: Initialising battery brown-out level to 3.0V\n");
-
- debug("SPL: Initialising battery brown-out level to 3.0V\n");
+ debug("SPL: Initialising battery brown-out level to %u.%uV\n",
+ (BATT_BO_VAL * 40 + 2400) / 1000,
+ (BATT_BO_VAL * 40 + 2400) / 100 % 10);
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
{
debug("SPL: Switching VDDD to DC-DC converters\n");
- debug("SPL: Switching VDDD to DC-DC converters\n");
-
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
{
debug("SPL: Enabling output rail protection\n");
- debug("SPL: Enabling output rail protection\n");
-
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO)) {
- early_delay(500);
+ udelay(500);
} else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK)) {
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
- early_delay(10);
+ udelay(10);
}
/**
{
debug("SPL: Initialising Power Block\n");
- debug("SPL: Initialising Power Block\n");
-
mxs_ungate_power();
mxs_power_clock2xtal();
}
/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
-#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0
-
void __udelay(unsigned long usec)
{
- uint32_t start = readl(MXS_HW_DIGCTL_MICROSECONDS);
+ struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
+ u32 start = readl(&digctl_regs->hw_digctl_microseconds);
- while (readl(MXS_HW_DIGCTL_MICROSECONDS) - start <= usec)
+ while (readl(&digctl_regs->hw_digctl_microseconds) - start <= usec)
/* use '<=' to guarantee a delay of _at least_
* the given number of microseconds.
* No need for fancy rollover checks
inline void mxs_gpio_init(void) {}
#endif
+#define MXS_GPIO_NR(p, o) (((p) * 32) | ((o) & 0x1f))
+#define MXS_GPIO_TO_BANK(gpio) ((gpio) / 32)
+#define MXS_GPIO_TO_PIN(gpio) ((gpio) % 32)
+
#endif /* __MX28_GPIO_H__ */
* PAD_VOL_VALID: 14 (1)
* PAD_PULL: 15 (1)
* PAD_PULL_VALID: 16 (1)
- * RESERVED: 17..31 (15)
+ * RESERVED: 17..30 (14)
+ * sentinel to produce an invalid GPIO number when using an
+ * iomux_cfg_t value where a plain GPIO number is expected
+ * GPIO_SENTINEL: 31 (1)
*/
+#ifdef CONFIG_MXS_IOMUX_COMPILE_CHECK
+typedef u64 iomux_cfg_t;
+#define IOMUX_CFG_SHIFT 32
+#else
typedef u32 iomux_cfg_t;
+#define IOMUX_CFG_SHIFT 0
+#endif
-#define MXS_PAD_BANK_SHIFT 0
+#define MXS_PAD_BANK_SHIFT (IOMUX_CFG_SHIFT + 0)
#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
-#define MXS_PAD_PIN_SHIFT 3
+#define MXS_PAD_PIN_SHIFT (IOMUX_CFG_SHIFT + 3)
#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
-#define MXS_PAD_MUXSEL_SHIFT 8
+#define MXS_PAD_MUXSEL_SHIFT (IOMUX_CFG_SHIFT + 8)
#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
-#define MXS_PAD_MA_SHIFT 10
+#define MXS_PAD_MA_SHIFT (IOMUX_CFG_SHIFT + 10)
#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
-#define MXS_PAD_MA_VALID_SHIFT 12
+#define MXS_PAD_MA_VALID_SHIFT (IOMUX_CFG_SHIFT + 12)
#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
-#define MXS_PAD_VOL_SHIFT 13
+#define MXS_PAD_VOL_SHIFT (IOMUX_CFG_SHIFT + 13)
#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
-#define MXS_PAD_VOL_VALID_SHIFT 14
+#define MXS_PAD_VOL_VALID_SHIFT (IOMUX_CFG_SHIFT + 14)
#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
-#define MXS_PAD_PULL_SHIFT 15
+#define MXS_PAD_PULL_SHIFT (IOMUX_CFG_SHIFT + 15)
#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
-#define MXS_PAD_PULL_VALID_SHIFT 16
+#define MXS_PAD_PULL_VALID_SHIFT (IOMUX_CFG_SHIFT + 16)
#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
-#define PAD_MUXSEL_0 0
-#define PAD_MUXSEL_1 1
-#define PAD_MUXSEL_2 2
-#define PAD_MUXSEL_GPIO 3
+#define MXS_GPIO_SENTINEL_SHIFT (IOMUX_CFG_SHIFT + 31)
+#define MXS_GPIO_SENTINEL_MASK ((iomux_cfg_t)0x1 << MXS_GPIO_SENTINEL_SHIFT)
-#define PAD_4MA 0
-#define PAD_8MA 1
-#define PAD_12MA 2
-#define PAD_16MA 3
+#define PAD_MUXSEL_0 (iomux_cfg_t)0
+#define PAD_MUXSEL_1 (iomux_cfg_t)1
+#define PAD_MUXSEL_2 (iomux_cfg_t)2
+#define PAD_MUXSEL_GPIO (iomux_cfg_t)3
-#define PAD_1V8 0
+#define PAD_4MA (iomux_cfg_t)0
+#define PAD_8MA (iomux_cfg_t)1
+#define PAD_12MA (iomux_cfg_t)2
+#define PAD_16MA (iomux_cfg_t)3
+
+#define PAD_1V8 (iomux_cfg_t)0
#if defined(CONFIG_SOC_MX28)
-#define PAD_3V3 1
+#define PAD_3V3 (iomux_cfg_t)1
#else
-#define PAD_3V3 0
+#define PAD_3V3 (iomux_cfg_t)0
#endif
-#define PAD_NOPULL 0
-#define PAD_PULLUP 1
+#define PAD_NOPULL (iomux_cfg_t)0
+#define PAD_PULLUP (iomux_cfg_t)1
#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
MXS_PAD_MA_VALID_MASK)
((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \
((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \
((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \
- ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
+ ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT) | \
+ ((iomux_cfg_t)1 << 31))
+
+#define MXS_PAD_TO_GPIO(p) ((unsigned)(((((p) & MXS_PAD_BANK_MASK) >> \
+ MXS_PAD_BANK_SHIFT) << 5) | \
+ ((p) & MXS_PAD_PIN_MASK) >> \
+ MXS_PAD_PIN_SHIFT))
/*
* A pad becomes naked, when none of mA, vol or pull
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
- gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_AUART3_TX__GPIO_3_13), 0);
mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
- gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_AUART3_RX__GPIO_3_12), 0);
#endif
return 0;
return 1;
}
- return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
+ return gpio_get_value(MXS_PAD_TO_GPIO(MX28_PAD_AUART2_CTS__GPIO_3_10));
}
int board_mmc_init(bd_t *bis)
{
/* Configure WP as input. */
- gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+ gpio_direction_input(MXS_PAD_TO_GPIO(MX28_PAD_AUART2_CTS__GPIO_3_10));
/* Turn on the power to the card. */
- gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_PWM3__GPIO_3_28), 0);
return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
}
#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
/* Reset the new PHY */
- gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_AUART2_RTS__GPIO_3_11), 0);
udelay(10000);
- gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
+ gpio_set_value(MXS_PAD_TO_GPIO(MX28_PAD_AUART2_RTS__GPIO_3_11), 1);
udelay(10000);
#endif
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* Power on LCD */
- gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX23_PAD_LCD_RESET__GPIO_1_18), 1);
/* Set contrast to maximum */
- gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX23_PAD_PWM2__GPIO_1_28), 1);
return 0;
}
return 1;
}
- return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30);
+ return gpio_get_value(MXS_PAD_TO_GPIO(MX23_PAD_PWM4__GPIO_1_30));
}
int board_mmc_init(bd_t *bis)
{
/* Configure WP as input */
- gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30);
+ gpio_direction_input(MXS_PAD_TO_GPIO(MX23_PAD_PWM4__GPIO_1_30));
/* Configure MMC0 Power Enable */
- gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX23_PAD_PWM3__GPIO_1_29), 0);
return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL);
}
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
- gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_AUART2_RX__GPIO_3_8), 1);
#endif
/* Power on LCD */
- gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_LCD_RESET__GPIO_3_30), 1);
/* Set contrast to maximum */
- gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_PWM2__GPIO_3_18), 1);
return 0;
}
return 1;
}
- return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
+ return gpio_get_value(MXS_PAD_TO_GPIO(MX28_PAD_SSP1_SCK__GPIO_2_12));
}
int board_mmc_init(bd_t *bis)
{
/* Configure WP as input */
- gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
+ gpio_direction_input(MXS_PAD_TO_GPIO(MX28_PAD_SSP1_SCK__GPIO_2_12));
/* Configure MMC0 Power Enable */
- gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_PWM3__GPIO_3_28), 0);
return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
}
&clkctrl_regs->hw_clkctrl_enet);
/* Power-on FECs */
- gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_SSP1_DATA3__GPIO_2_15), 0);
/* Reset FEC PHYs */
- gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RX_CLK__GPIO_4_13), 0);
udelay(200);
- gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+ gpio_set_value(MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RX_CLK__GPIO_4_13), 1);
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
if (ret) {
/*
- * Copyright (C) 2011-2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright (C) 2011-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* See file CREDITS for list of people who contributed to this
* project.
nand_erase_options_t erase_opts = { 0, };
size_t actual;
size_t prg_length = max_len - skip * mtd->erasesize;
- int prg_start = (start_block + skip) * mtd->erasesize;
+ int prg_start = start_block * mtd->erasesize;
- erase_opts.offset = start_block * mtd->erasesize;
+ erase_opts.offset = (start_block - skip) * mtd->erasesize;
erase_opts.length = max_len;
erase_opts.quiet = 1;
printf("Programming redundant U-Boot image to block %lu @ %08llx\n",
fw2_start_block, (u64)fw2_start_block * mtd->erasesize);
- ret = tx28_prog_uboot(addr, fw2_start_block, fw2_skip, fw_num_blocks,
+ ret = tx28_prog_uboot(addr, fw2_start_block, fw2_skip, size,
max_len2);
out:
free(buf);
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
-#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_PULLUP)
+#define LED_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define TSC_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define SSP0_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define SSP2_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define GPMI_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define ENET_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define EMI_PAD_CTRL (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define GPIO_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define UART_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
static iomux_cfg_t tx28_stk5_pads[] = {
/* LED */
- MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
-
- /* framebuffer */
- MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
- MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+ MX28_PAD_ENET0_RXD3__GPIO_4_10 | LED_PAD_CTRL,
/* DUART pads */
- MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO,
- MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO,
- MX28_PAD_I2C0_SCL__GPIO_3_24 | MUX_CONFIG_GPIO,
- MX28_PAD_I2C0_SDA__GPIO_3_25 | MUX_CONFIG_GPIO,
-
- MX28_PAD_AUART0_RTS__DUART_TX,
- MX28_PAD_AUART0_CTS__DUART_RX,
- MX28_PAD_AUART0_TX__DUART_RTS,
- MX28_PAD_AUART0_RX__DUART_CTS,
+ MX28_PAD_PWM0__GPIO_3_16 | GPIO_PAD_CTRL, /* LCD backlight */
+ MX28_PAD_PWM1__GPIO_3_17 | GPIO_PAD_CTRL,
+ /* pads for selected console UART */
+#if CONFIG_CONS_INDEX == 0
+ MX28_PAD_AUART0_RX__DUART_CTS | UART_PAD_CTRL,
+ MX28_PAD_AUART0_TX__DUART_RTS | UART_PAD_CTRL,
+ MX28_PAD_AUART0_CTS__DUART_RX | UART_PAD_CTRL,
+ MX28_PAD_AUART0_RTS__DUART_TX | UART_PAD_CTRL,
+#elif CONFIG_CONS_INDEX == 1
+ MX28_PAD_AUART1_RX__AUART1_RX | UART_PAD_CTRL,
+ MX28_PAD_AUART1_TX__AUART1_TX | UART_PAD_CTRL,
+ MX28_PAD_AUART1_CTS__AUART1_CTS | UART_PAD_CTRL,
+ MX28_PAD_AUART1_RTS__AUART1_RTS | UART_PAD_CTRL,
+#elif CONFIG_CONS_INDEX == 2
+ MX28_PAD_AUART3_RX__AUART3_RX | UART_PAD_CTRL,
+ MX28_PAD_AUART3_TX__AUART3_TX | UART_PAD_CTRL,
+ MX28_PAD_AUART3_CTS__AUART3_CTS | UART_PAD_CTRL,
+ MX28_PAD_AUART3_RTS__AUART3_RTS | UART_PAD_CTRL,
+#endif
/* EMI */
- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D00__EMI_DATA0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D01__EMI_DATA1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D02__EMI_DATA2 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D03__EMI_DATA3 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D04__EMI_DATA4 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D05__EMI_DATA5 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D06__EMI_DATA6 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D07__EMI_DATA7 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D08__EMI_DATA8 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D09__EMI_DATA9 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D10__EMI_DATA10 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D11__EMI_DATA11 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D12__EMI_DATA12 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D13__EMI_DATA13 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D14__EMI_DATA14 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D15__EMI_DATA15 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CLK__EMI_CLK | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | EMI_PAD_CTRL,
- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A00__EMI_ADDR0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_BA0__EMI_BA0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_BA1__EMI_BA1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_BA2__EMI_BA2 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CASN__EMI_CASN | EMI_PAD_CTRL,
+ MX28_PAD_EMI_RASN__EMI_RASN | EMI_PAD_CTRL,
+ MX28_PAD_EMI_WEN__EMI_WEN | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CKE__EMI_CKE | EMI_PAD_CTRL,
/* FEC pads */
- MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_ENET, /* COL/CRS_DV/MODE2 */
- MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_ENET, /* RXD0/MODE0 */
- MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_ENET, /* RXD1/MODE1 */
- MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MUX_CONFIG_ENET, /* nINT/TX_ER/TXD4 */
- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+ MX28_PAD_PWM4__GPIO_3_29 | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_MDC__ENET0_MDC | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_RX_EN__GPIO_4_2 | ENET_PAD_CTRL, /* COL/CRS_DV/MODE2 */
+ MX28_PAD_ENET0_RXD0__GPIO_4_3 | ENET_PAD_CTRL, /* RXD0/MODE0 */
+ MX28_PAD_ENET0_RXD1__GPIO_4_4 | ENET_PAD_CTRL, /* RXD1/MODE1 */
+ MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | ENET_PAD_CTRL, /* nINT/TX_ER/TXD4 */
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | ENET_PAD_CTRL,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | ENET_PAD_CTRL,
/* MMC pads */
- MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_GPIO,
- MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | GPIO_PAD_CTRL,
+ MX28_PAD_SSP0_SCK__SSP0_SCK | SSP0_PAD_CTRL,
/* GPMI pads */
- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDN__GPMI_RDN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D00__GPMI_D0 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D01__GPMI_D1 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D02__GPMI_D2 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D03__GPMI_D3 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D04__GPMI_D4 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D05__GPMI_D5 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D06__GPMI_D6 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D07__GPMI_D7 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_RDN__GPMI_RDN | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_WRN__GPMI_WRN | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | GPMI_PAD_CTRL,
/* maybe used for EDT-FT5x06 */
- MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_GPIO,
- MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP0_DATA5__GPIO_2_5 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP0_DATA6__GPIO_2_6 | GPIO_PAD_CTRL,
+ MX28_PAD_ENET0_RXD2__GPIO_4_9 | GPIO_PAD_CTRL,
/* unused pads */
- MX28_PAD_GPMI_RDY1__GPIO_0_21 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_RDY2__GPIO_0_22 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_CE1N__GPIO_0_17 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_CE2N__GPIO_0_18 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_CE3N__GPIO_0_19 | MUX_CONFIG_GPIO,
+ MX28_PAD_GPMI_RDY1__GPIO_0_21 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_RDY2__GPIO_0_22 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_RDY3__GPIO_0_23 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_CE1N__GPIO_0_17 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_CE2N__GPIO_0_18 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_CE3N__GPIO_0_19 | GPIO_PAD_CTRL,
- MX28_PAD_SSP0_DATA4__GPIO_2_4 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP0_DATA7__GPIO_2_7 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP0_DATA4__GPIO_2_4 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP0_DATA7__GPIO_2_7 | GPIO_PAD_CTRL,
- MX28_PAD_SSP2_SS0__GPIO_2_19 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP2_SS2__GPIO_2_21 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP3_SS0__GPIO_2_27 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP2_SS0__GPIO_2_19 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP2_SS1__GPIO_2_20 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP2_SS2__GPIO_2_21 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP3_SS0__GPIO_2_27 | GPIO_PAD_CTRL,
- MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
- MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO,
- MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
+ MX28_PAD_ENET0_TXD2__GPIO_4_11 | GPIO_PAD_CTRL,
+ MX28_PAD_ENET0_TXD3__GPIO_4_12 | GPIO_PAD_CTRL,
+ MX28_PAD_ENET0_CRS__GPIO_4_15 | GPIO_PAD_CTRL,
};
-static void tx28_stk5_lcd_init(void)
-{
- gpio_direction_output(MX28_PAD_PWM0__GPIO_3_16, 1);
- gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 0);
- gpio_direction_output(MX28_PAD_LCD_ENABLE__GPIO_1_31, 0);
-}
-
-static void tx28_stk5_led_on(void)
-{
- gpio_direction_output(MX28_PAD_ENET0_RXD3__GPIO_4_10, 1);
-}
-
void board_init_ll(const uint32_t arg, const uint32_t *resptr)
{
mxs_common_spl_init(arg, resptr,
tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads));
- tx28_stk5_lcd_init();
- tx28_stk5_led_on();
}
static uint32_t tx28_dram_vals[] = {
#include <linux/fb.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <asm/arch/iomux.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
-#define MXS_GPIO_NR(p, o) (((p) << 5) | (o))
+#define TX28_LCD_PWR_GPIO MXS_PAD_TO_GPIO(MX28_PAD_LCD_ENABLE__GPIO_1_31)
+#define TX28_LCD_RST_GPIO MXS_PAD_TO_GPIO(MX28_PAD_LCD_RESET__GPIO_3_30)
+#define TX28_LCD_BACKLIGHT_GPIO MXS_PAD_TO_GPIO(MX28_PAD_PWM0__GPIO_3_16)
-#define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31
-#define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30
-#define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
+#define TX28_USBH_VBUSEN_GPIO MXS_PAD_TO_GPIO(MX28_PAD_SPDIF__GPIO_3_27)
+#define TX28_USBH_OC_GPIO MXS_PAD_TO_GPIO(MX28_PAD_JTAG_RTCK__GPIO_4_20)
+#define TX28_USBOTG_VBUSEN_GPIO MXS_PAD_TO_GPIO(MX28_PAD_GPMI_CE2N__GPIO_0_18)
+#define TX28_USBOTG_OC_GPIO MXS_PAD_TO_GPIO(MX28_PAD_GPMI_CE3N__GPIO_0_19)
+#define TX28_USBOTG_ID_GPIO MXS_PAD_TO_GPIO(MX28_PAD_PWM2__GPIO_3_18)
-#define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27
-#define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20
-#define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
-#define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19
-#define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18
+#define TX28_LED_GPIO MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RXD3__GPIO_4_10)
-#define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10
+#define STK5_CAN_XCVR_PAD MX28_PAD_LCD_D00__GPIO_1_0
+#define STK5_CAN_XCVR_GPIO MXS_PAD_TO_GPIO(STK5_CAN_XCVR_PAD)
-#define STK5_CAN_XCVR_GPIO MX28_PAD_LCD_D00__GPIO_1_0
+#define ENET_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define GPIO_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define I2C_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+
+#ifndef CONFIG_CONS_INDEX
+struct serial_device *default_serial_console(void)
+{
+ return NULL;
+}
+#endif
static const struct gpio tx28_gpios[] = {
{ TX28_USBH_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBH VBUSEN", },
};
static const iomux_cfg_t tx28_pads[] = {
- /* UART pads */
-#if CONFIG_CONS_INDEX == 0
- MX28_PAD_AUART0_RX__DUART_CTS,
- MX28_PAD_AUART0_TX__DUART_RTS,
- MX28_PAD_AUART0_CTS__DUART_RX,
- MX28_PAD_AUART0_RTS__DUART_TX,
-#elif CONFIG_CONS_INDEX == 1
- MX28_PAD_AUART1_RX__AUART1_RX,
- MX28_PAD_AUART1_TX__AUART1_TX,
- MX28_PAD_AUART1_CTS__AUART1_CTS,
- MX28_PAD_AUART1_RTS__AUART1_RTS,
-#elif CONFIG_CONS_INDEX == 2
- MX28_PAD_AUART3_RX__AUART3_RX,
- MX28_PAD_AUART3_TX__AUART3_TX,
- MX28_PAD_AUART3_CTS__AUART3_CTS,
- MX28_PAD_AUART3_RTS__AUART3_RTS,
-#endif
/* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
- MX28_PAD_I2C0_SCL__I2C0_SCL,
- MX28_PAD_I2C0_SDA__I2C0_SDA,
+ MX28_PAD_I2C0_SCL__I2C0_SCL | I2C_PAD_CTRL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA | I2C_PAD_CTRL,
/* USBH VBUSEN, OC */
MX28_PAD_SPDIF__GPIO_3_27,
#endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
static const iomux_cfg_t tx28_fec_pads[] = {
- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
- MX28_PAD_ENET0_RXD0__ENET0_RXD0,
- MX28_PAD_ENET0_RXD1__ENET0_RXD1,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | ENET_PAD_CTRL,
+};
+
+static struct gpio tx28_fec_strap_gpios[] = {
+ /* first entry must be RESET pin */
+ { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RX_CLK__GPIO_4_13),
+ GPIOFLAG_OUTPUT_INIT_LOW, "PHY Reset", },
+
+ { MXS_PAD_TO_GPIO(MX28_PAD_PWM4__GPIO_3_29),
+ GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Power", },
+
+ /* Pull strap pins to high */
+ { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RX_EN__GPIO_4_2),
+ GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Mode0", },
+ { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RXD0__GPIO_4_3),
+ GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Mode1", },
+ { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RXD1__GPIO_4_4),
+ GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Mode2", },
+
+ { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_TX_CLK__GPIO_4_5),
+ GPIOFLAG_INPUT, "PHY INT", },
};
int board_eth_init(bd_t *bis)
int ret;
/* Reset the external phy */
- gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
-
- /* Power on the external phy */
- gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
-
- /* Pull strap pins to high */
- gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
- gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
- gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
- gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
+ ret = gpio_request_array(tx28_fec_strap_gpios,
+ ARRAY_SIZE(tx28_fec_strap_gpios));
+ if (ret)
+ printf("Failed to request FEC GPIOs: %d\n", ret);
udelay(25000);
- gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+ gpio_set_value(tx28_fec_strap_gpios[0].gpio, 1);
udelay(100);
mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
LED_STATE_INIT = -1,
LED_STATE_OFF,
LED_STATE_ON,
+ LED_STATE_DISABLED,
};
+static int led_state = LED_STATE_DISABLED;
+
void show_activity(int arg)
{
- static int led_state = LED_STATE_INIT;
static ulong last;
+ int ret;
- if (led_state == LED_STATE_INIT) {
+ if (led_state == LED_STATE_DISABLED) {
+ return;
+ } else if (led_state == LED_STATE_INIT) {
last = get_timer(0);
- gpio_set_value(TX28_LED_GPIO, 1);
- led_state = LED_STATE_ON;
+ ret = gpio_request_one(TX28_LED_GPIO,
+ GPIOFLAG_OUTPUT_INIT_HIGH, "Activity");
+ if (ret == 0)
+ led_state = LED_STATE_ON;
+ else
+ led_state = LED_STATE_DISABLED;
} else {
if (get_timer(last) > CONFIG_SYS_HZ) {
last = get_timer(0);
if (led_state == LED_STATE_ON) {
gpio_set_value(TX28_LED_GPIO, 0);
+ led_state = LED_STATE_OFF;
} else {
gpio_set_value(TX28_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
}
- led_state = 1 - led_state;
}
}
}
static const iomux_cfg_t stk5_pads[] = {
/* SW controlled LED on STK5 baseboard */
- MX28_PAD_ENET0_RXD3__GPIO_4_10,
+ MX28_PAD_ENET0_RXD3__GPIO_4_10 | GPIO_PAD_CTRL,
};
static const struct gpio stk5_gpios[] = {
static void stk5v3_board_init(void)
{
+ led_state = LED_STATE_INIT;
stk5_board_init();
}
/* init flexcan transceiver enable GPIO */
gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH,
"Flexcan Transceiver");
- mxs_iomux_setup_pad(STK5_CAN_XCVR_GPIO);
+ mxs_iomux_setup_pad(STK5_CAN_XCVR_PAD);
}
int board_late_init(void)
+++ /dev/null
-sources {
- u_boot_spl="@@BUILD_DIR@@spl/u-boot-spl";
- u_boot="@@BUILD_DIR@@u-boot";
-}
-
-section (0) {
- load u_boot_spl;
- load ivt (entry = u_boot_spl:reset) > 0x8000;
- hab call 0x8000;
-
- load u_boot;
- load ivt (entry = u_boot:reset) > 0x8000;
- hab call 0x8000;
-}
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <asm/arch/iomux.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
int board_ehci_hcd_init(int port)
{
/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
- gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX23_PAD_GPMI_ALE__GPIO_0_17), 1);
udelay(100);
return 0;
}
int board_ehci_hcd_exit(int port)
{
/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
- gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0);
+ gpio_direction_output(MXS_PAD_TO_GPIO(MX23_PAD_GPMI_ALE__GPIO_0_17), 0);
return 0;
}
#endif
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,SYS_SDRAM_SIZE=SZ_128M"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,SYS_SDRAM_SIZE=SZ_128M"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,SYS_SDRAM_SIZE=SZ_256M"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,SYS_SDRAM_SIZE=SZ_256M"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
-CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,TX28_S,SYS_SDRAM_SIZE=SZ_64M"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
-CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=0,TX28_S,SYS_SDRAM_SIZE=SZ_64M"
CONFIG_ARM=y
CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
#error "Please select CONFIG_SOC_MX23 or CONFIG_SOC_MX28"
#endif
-#define GPIO_INT_FALL_EDGE 0x0
-#define GPIO_INT_LOW_LEV 0x1
-#define GPIO_INT_RISE_EDGE 0x2
-#define GPIO_INT_HIGH_LEV 0x3
-#define GPIO_INT_LEV_MASK (1 << 0)
-#define GPIO_INT_POL_MASK (1 << 1)
-
void mxs_gpio_init(void)
{
int i;
int gpio_get_value(unsigned gpio)
{
- uint32_t bank = PAD_BANK(gpio);
+ uint32_t bank = MXS_GPIO_TO_BANK(gpio);
uint32_t offset = PINCTRL_DIN(bank);
- struct mxs_register_32 *reg =
- (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg = (void *)(MXS_PINCTRL_BASE + offset);
+
+ if (bank >= PINCTRL_BANKS)
+ return -EINVAL;
- return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
+ return (readl(®->reg) >> MXS_GPIO_TO_PIN(gpio)) & 1;
}
int gpio_set_value(unsigned gpio, int value)
{
- uint32_t bank = PAD_BANK(gpio);
+ uint32_t bank = MXS_GPIO_TO_BANK(gpio);
uint32_t offset = PINCTRL_DOUT(bank);
- struct mxs_register_32 *reg =
- (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg = (void *)(MXS_PINCTRL_BASE + offset);
+
+ if (bank >= PINCTRL_BANKS)
+ return -EINVAL;
if (value)
- writel(1 << PAD_PIN(gpio), ®->reg_set);
+ writel(1 << MXS_GPIO_TO_PIN(gpio), ®->reg_set);
else
- writel(1 << PAD_PIN(gpio), ®->reg_clr);
+ writel(1 << MXS_GPIO_TO_PIN(gpio), ®->reg_clr);
return 0;
}
int gpio_direction_input(unsigned gpio)
{
- uint32_t bank = PAD_BANK(gpio);
+ uint32_t bank = MXS_GPIO_TO_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank);
- struct mxs_register_32 *reg =
- (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg = (void *)(MXS_PINCTRL_BASE + offset);
- writel(1 << PAD_PIN(gpio), ®->reg_clr);
+ if (bank >= PINCTRL_BANKS)
+ return -EINVAL;
+
+ writel(1 << MXS_GPIO_TO_PIN(gpio), ®->reg_clr);
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
- uint32_t bank = PAD_BANK(gpio);
+ uint32_t bank = MXS_GPIO_TO_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank);
- struct mxs_register_32 *reg =
- (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg = (void *)(MXS_PINCTRL_BASE + offset);
+
+ if (bank >= PINCTRL_BANKS)
+ return -EINVAL;
gpio_set_value(gpio, value);
- writel(1 << PAD_PIN(gpio), ®->reg_set);
+ writel(1 << MXS_GPIO_TO_PIN(gpio), ®->reg_set);
return 0;
}
int gpio_request(unsigned gpio, const char *label)
{
- if (PAD_BANK(gpio) >= PINCTRL_BANKS)
- return -1;
+ if (MXS_GPIO_TO_BANK(gpio) >= PINCTRL_BANKS) {
+ printf("%s(): Invalid GPIO%d (GPIO_%u_%u) requested; possibly intended: GPIO_%u_%u\n",
+ __func__, gpio, gpio / 32, gpio % 32,
+ PAD_BANK(gpio), PAD_PIN(gpio));
+ printf("Linear GPIO number required rather than iomux_cfg_t cookie!\n");
+ printf("Possibly missing MXS_PAD_TO_GPIO() in the GPIO specification.\n");
+ return -EINVAL;
+ }
return 0;
}
#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1
+#define STATUS_LED_BIT MXS_PAD_TO_GPIO(MX23_PAD_SSP1_DETECT__GPIO_2_1)
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_CMD_GPIO
/* LCD Logo and Splash screen support */
#ifdef CONFIG_LCD
/*
* Serial Driver
*/
+#ifdef CONFIG_CONS_INDEX
+/*
+ * select STK5 UART port 0: 1st UART (DUART) 1,2 2nd,3rd UART (Appl. UART)
+ */
+#if CONFIG_CONS_INDEX == 0
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { \
(void *)MXS_UARTDBG_BASE, \
}
-#define CONFIG_CONS_INDEX 0 /* do not change! */
+#else /* CONFIG_CONS_INDEX == 0 */
+#define CONFIG_MXS_AUART
+#if CONFIG_CONS_INDEX == 1
+#define CONFIG_MXS_AUART_BASE ((void *)MXS_UARTAPP1_BASE)
+#elif CONFIG_CONS_INDEX == 2
+#define CONFIG_MXS_AUART_BASE ((void *)MXS_UARTAPP3_BASE)
+#elif CONFIG_CONS_INDEX != -1
+#error Unsupported console UART selection
+#endif
+#endif /* CONFIG_CONS_INDEX == 0 */
+#endif /* ifdef CONFIG_CONS_INDEX */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
#define CONFIG_SYS_CONSOLE_INFO_QUIET
",512k@" xstr(CONFIG_SYS_NAND_BBT_OFFSET) "(bbt)ro"
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
+#endif
/* Defines for SPL */
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SYS_SPL_BATT_BO_LEVEL 2400
#define CONFIG_SYS_SPL_VDDA_BO_VAL 100
#define CONFIG_SYS_SPL_VDDMEM_VAL 0 /* VDDMEM is not utilized on TX28 */
+#define CONFIG_SPL_STACK 0x1fffc /* End of OCRAM */
#endif /* __CONFIG_H */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_CMD_GPIO
-#ifndef CONFIG_TX6_UBOOT_MFG
/* LCD Logo and Splash screen support */
#ifdef CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_32BPP
#define CONFIG_VIDEO_BMP_RLE8
#endif /* CONFIG_LCD */
-#endif /* CONFIG_TX6_UBOOT_MFG */
/*
* Memory configuration options
#endif
/*
- * Extra Environments
+ * Extra Environment Settings
*/
#ifdef CONFIG_TX6_UBOOT_NOENV
#define CONFIG_EXTRA_ENV_SETTINGS \
projects / karo-tx-uboot.git / commitdiff