imx: mx6ul: Update imx registers head file

1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
   "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
   because we can use runtime check

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 03cfac2d7d70d2710656f733da5c5f1b26f94463..cb68b44ff275d22d60c192522668f1c1bcea820b 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -11,28 +11,24 @@
 
 #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
+#define CONFIG_SYS_CACHELINE_SIZE      32
 
-#define ROMCP_ARB_BASE_ADDR            0x00000000
-#define ROMCP_ARB_END_ADDR             0x000FFFFF
+#define ROMCP_ARB_BASE_ADDR             0x00000000
+#define ROMCP_ARB_END_ADDR              0x000FFFFF
 
 #ifdef CONFIG_SOC_MX6SL
-#define GPU_2D_ARB_BASE_ADDR           0x02200000
-#define GPU_2D_ARB_END_ADDR            0x02203FFF
-#define OPENVG_ARB_BASE_ADDR           0x02204000
-#define OPENVG_ARB_END_ADDR            0x02207FFF
-#elif defined(CONFIG_SOC_MX6SX)
-#define CAAM_ARB_BASE_ADDR             0x00100000
-#define CAAM_ARB_END_ADDR              0x00107FFF
-#define GPU_ARB_BASE_ADDR              0x01800000
-#define GPU_ARB_END_ADDR               0x01803FFF
-#define APBH_DMA_ARB_BASE_ADDR         0x01804000
-#define APBH_DMA_ARB_END_ADDR          0x0180BFFF
-#define M4_BOOTROM_BASE_ADDR           0x007F8000
-
-#define MXS_APBH_BASE                  APBH_DMA_ARB_BASE_ADDR
-#define MXS_GPMI_BASE                  (APBH_DMA_ARB_BASE_ADDR + 0x02000)
-#define MXS_BCH_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+#define GPU_2D_ARB_BASE_ADDR            0x02200000
+#define GPU_2D_ARB_END_ADDR             0x02203FFF
+#define OPENVG_ARB_BASE_ADDR            0x02204000
+#define OPENVG_ARB_END_ADDR             0x02207FFF
+#elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#define CAAM_ARB_BASE_ADDR              0x00100000
+#define CAAM_ARB_END_ADDR               0x00107FFF
+#define GPU_ARB_BASE_ADDR               0x01800000
+#define GPU_ARB_END_ADDR                0x01803FFF
+#define APBH_DMA_ARB_BASE_ADDR          0x01804000
+#define APBH_DMA_ARB_END_ADDR           0x0180BFFF
+#define M4_BOOTROM_BASE_ADDR                   0x007F8000
 
 #else
 #define CAAM_ARB_BASE_ADDR             0x00100000
@@ -54,13 +50,13 @@
 #define MXS_BCH_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
-#define GPV2_BASE_ADDR                 0x00D00000
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#define GPV2_BASE_ADDR                  0x00D00000
 #else
 #define GPV2_BASE_ADDR                 0x00200000
 #endif
 
-#ifdef CONFIG_SOC_MX6SX
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
 #define GPV3_BASE_ADDR                 0x00E00000
 #define GPV4_BASE_ADDR                 0x00F00000
 #define GPV5_BASE_ADDR                 0x01000000
@@ -82,22 +78,28 @@
 #define PRIVATE_TIMERS_WD_BASE_ADDR    0x00A00600
 #define IC_DISTRIBUTOR_BASE_ADDR       0x00A01000
 #define L2_PL310_BASE                  0x00A02000
-#define GPV0_BASE_ADDR                 0x00B00000
-#define GPV1_BASE_ADDR                 0x00C00000
-
-#define AIPS1_ARB_BASE_ADDR            0x02000000
-#define AIPS1_ARB_END_ADDR             0x020FFFFF
-#define AIPS2_ARB_BASE_ADDR            0x02100000
-#define AIPS2_ARB_END_ADDR             0x021FFFFF
+#define GPV0_BASE_ADDR                  0x00B00000
+#define GPV1_BASE_ADDR                  0x00C00000
+
+#define AIPS1_ARB_BASE_ADDR             0x02000000
+#define AIPS1_ARB_END_ADDR              0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR             0x02100000
+#define AIPS2_ARB_END_ADDR              0x021FFFFF
+/* AIPS3 only on i.MX6SX */
+#define AIPS3_ARB_BASE_ADDR             0x02200000
+#define AIPS3_ARB_END_ADDR              0x022FFFFF
 #ifdef CONFIG_SOC_MX6SX
-#define AIPS3_ARB_BASE_ADDR            0x02200000
-#define AIPS3_ARB_END_ADDR             0x022FFFFF
-#define WEIM_ARB_BASE_ADDR             0x50000000
-#define WEIM_ARB_END_ADDR              0x57FFFFFF
-#define QSPI0_AMBA_BASE                        0x60000000
-#define QSPI0_AMBA_END                 0x6FFFFFFF
-#define QSPI1_AMBA_BASE                        0x70000000
-#define QSPI1_AMBA_END                 0x7FFFFFFF
+#define WEIM_ARB_BASE_ADDR              0x50000000
+#define WEIM_ARB_END_ADDR               0x57FFFFFF
+#define QSPI0_AMBA_BASE                0x60000000
+#define QSPI0_AMBA_END                 0x6FFFFFFF
+#define QSPI1_AMBA_BASE                0x70000000
+#define QSPI1_AMBA_END                 0x7FFFFFFF
+#elif defined(CONFIG_SOC_MX6UL)
+#define WEIM_ARB_BASE_ADDR              0x50000000
+#define WEIM_ARB_END_ADDR               0x57FFFFFF
+#define QSPI0_AMBA_BASE                 0x60000000
+#define QSPI0_AMBA_END                  0x6FFFFFFF
 #else
 #define SATA_ARB_BASE_ADDR             0x02200000
 #define SATA_ARB_END_ADDR              0x02203FFF
@@ -113,11 +115,11 @@
 #define WEIM_ARB_END_ADDR              0x0FFFFFFF
 #endif
 
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
-#define MMDC0_ARB_BASE_ADDR            0x80000000
-#define MMDC0_ARB_END_ADDR             0xFFFFFFFF
-#define MMDC1_ARB_BASE_ADDR            0xC0000000
-#define MMDC1_ARB_END_ADDR             0xFFFFFFFF
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#define MMDC0_ARB_BASE_ADDR             0x80000000
+#define MMDC0_ARB_END_ADDR              0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR             0xC0000000
+#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 #else
 #define MMDC0_ARB_BASE_ADDR            0x10000000
 #define MMDC0_ARB_END_ADDR             0x7FFFFFFF
@@ -231,22 +233,25 @@
 #define MLB_BASE_ADDR                  (AIPS2_OFF_BASE_ADDR + 0xC000)
 #endif
 
-#define USDHC1_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x10000)
-#define USDHC2_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x14000)
-#define USDHC3_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x18000)
-#define USDHC4_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x1C000)
-#define I2C1_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x20000)
-#define I2C2_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x24000)
-#define I2C3_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x28000)
-#define ROMCP_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x2C000)
-#define MMDC_P0_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x30000)
-#ifdef CONFIG_SOC_MX6SL
-#define RNGB_IPS_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
-#elif defined(CONFIG_SOC_MX6SX)
-#define ENET2_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
+/* i.MX6SL */
+#define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
+#ifdef CONFIG_SOC_MX6UL
+#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
-#define MMDC_P1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x34000)
+/* i.MX6SX */
+#define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
 #endif
+/* i.MX6DQ/SDL */
+#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
 
 #define WEIM_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x3C000)
@@ -258,64 +263,68 @@
 #else
 #define IP2APB_PERFMON3_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
-#define IP2APB_TZASC1_BASE_ADDR                (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_SOC_MX6SX
-#define SAI1_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x54000)
-#else
-#define IP2APB_TZASC2_BASE_ADDR                (AIPS2_OFF_BASE_ADDR + 0x54000)
-#endif
-#define AUDMUX_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x58000)
-#ifdef CONFIG_SOC_MX6SX
-#define SAI2_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI0_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define QSPI1_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
+#ifdef CONFIG_SOC_MX6UL
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#elif defined(CONFIG_SOC_MX6SX)
+#define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
-#define MIPI_CSI2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define MIPI_DSI_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define VDOA_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
 #endif
-#define UART2_BASE                     (AIPS2_OFF_BASE_ADDR + 0x68000)
-#define UART3_BASE                     (AIPS2_OFF_BASE_ADDR + 0x6C000)
-#define UART4_BASE                     (AIPS2_OFF_BASE_ADDR + 0x70000)
-#define UART5_BASE                     (AIPS2_OFF_BASE_ADDR + 0x74000)
-#define I2C4_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x78000)
-#define IP2APB_USBPHY1_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x78000)
-#define IP2APB_USBPHY2_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x7C000)
+#define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
+#define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
 #ifdef CONFIG_SOC_MX6SX
-#define GIS_BASE_ADDR                  (AIPS3_ARB_BASE_ADDR + 0x04000)
-#define DCIC1_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0x0C000)
-#define DCIC2_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0x10000)
-#define CSI1_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x14000)
-#define PXP_BASE_ADDR                  (AIPS3_ARB_BASE_ADDR + 0x18000)
-#define CSI2_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x1C000)
-#define LCDIF1_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x20000)
-#define LCDIF2_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x24000)
-#define VADC_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x28000)
-#define VDEC_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x2C000)
-#define SPBA_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x3C000)
-#define AIPS3_CONFIG_BASE_ADDR         (AIPS3_ARB_BASE_ADDR + 0x7C000)
-#define ADC1_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x80000)
-#define ADC2_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x84000)
-#define WDOG3_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0x88000)
-#define ECSPI5_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x8C000)
-#define HS_BASE_ADDR                   (AIPS3_ARB_BASE_ADDR + 0x90000)
-#define MU_MCU_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x94000)
-#define CANFD_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0x98000)
-#define MU_DSP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x9C000)
-#define UART6_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0xA0000)
-#define PWM5_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xA4000)
-#define PWM6_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xA8000)
-#define PWM7_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xAC000)
-#define PWM8_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
+#define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
+#define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
+#define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
+#define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
+#define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
+#define LCDIF1_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x20000)
+#define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
+#define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
+#define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
+#define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
+#define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
+#define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
+#define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
+#define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
+#define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
+#define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
+#define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
 #endif
-
-#define CHIP_REV_1_0                   0x10
-#define CHIP_REV_1_2                   0x12
-#define CHIP_REV_1_5                   0x15
-#define CHIP_REV_2_0                   0x20
-#ifndef CONFIG_SOC_MX6SX
-#define IRAM_SIZE                      0x00040000
+#define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
+
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?  \
+                        MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
+
+#define CHIP_REV_1_0                 0x10
+#define CHIP_REV_1_2                 0x12
+#define CHIP_REV_1_5                 0x15
+#define CHIP_REV_2_0                 0x20
+#if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#define IRAM_SIZE                    0x00040000
 #else
 #define IRAM_SIZE                      0x00020000
 #endif
@@ -451,8 +460,8 @@ struct src {
 
 
 struct iomuxc {
-#ifdef CONFIG_SOC_MX6SX
-       u32 reserved[0x1000];
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+       u8 reserved[0x4000];
 #endif
        u32 gpr[14];
 };
@@ -577,7 +586,7 @@ struct cspi_regs {
 #define MXC_CSPICON_POL                4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL      12 /* SS polarity */
 #define MXC_CSPICON_CTL                20 /* inactive state of SCLK */
-#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL)
+#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6UL)
 #define MXC_SPI_BASE_ADDRESSES \
        ECSPI1_BASE_ADDR, \
        ECSPI2_BASE_ADDR, \
@@ -638,7 +647,7 @@ struct fuse_bank1_regs {
        reg_32(ana2);
 };
 
-#ifdef CONFIG_SOC_MX6SX
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
 struct fuse_bank4_regs {
        reg_32(sjc_resp_low);
        reg_32(sjc_resp_high);