Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 19 Jun 2013 10:53:59 +0000 (12:53 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 19 Jun 2013 10:53:59 +0000 (12:53 +0200)
Conflicts:
spl/Makefile

479 files changed:
.gitignore
MAINTAINERS
MAKEALL
Makefile
README
api/api_platform-powerpc.c
arch/arm/config.mk
arch/arm/cpu/arm1136/start.S
arch/arm/cpu/arm1176/start.S
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm920t/start.S
arch/arm/cpu/arm925t/start.S
arch/arm/cpu/arm926ejs/davinci/Makefile
arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/mxs/mxs.c
arch/arm/cpu/arm926ejs/start.S
arch/arm/cpu/arm946es/start.S
arch/arm/cpu/arm_intcm/start.S
arch/arm/cpu/armv7/at91/Makefile [moved from arch/powerpc/cpu/mpc8220/Makefile with 71% similarity]
arch/arm/cpu/armv7/at91/clock.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/cpu.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/reset.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/sama5d3_devices.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/timer.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/abb.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/timer.c
arch/arm/cpu/armv7/omap-common/vc.c
arch/arm/cpu/armv7/omap3/clock.c
arch/arm/cpu/armv7/omap4/hw_data.c
arch/arm/cpu/armv7/omap4/prcm-regs.c
arch/arm/cpu/armv7/omap5/Makefile
arch/arm/cpu/armv7/omap5/abb.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/cpu/armv7/start.S
arch/arm/cpu/armv7/vf610/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/vf610/generic.c [new file with mode: 0644]
arch/arm/cpu/armv7/vf610/timer.c [new file with mode: 0644]
arch/arm/cpu/ixp/config.mk
arch/arm/cpu/ixp/start.S
arch/arm/cpu/pxa/pxa2xx.c
arch/arm/cpu/pxa/start.S
arch/arm/cpu/s3c44b0/start.S
arch/arm/cpu/sa1100/start.S
arch/arm/cpu/tegra-common/ap.c
arch/arm/cpu/tegra-common/clock.c
arch/arm/imx-common/Makefile
arch/arm/imx-common/iomux-v3.c
arch/arm/include/asm/arch-am33xx/omap.h
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-at91/at91_dbu.h
arch/arm/include/asm/arch-at91/at91_pmc.h
arch/arm/include/asm/arch-at91/clk.h
arch/arm/include/asm/arch-at91/hardware.h
arch/arm/include/asm/arch-at91/sama5d3.h [new file with mode: 0644]
arch/arm/include/asm/arch-at91/sama5d3_smc.h [new file with mode: 0644]
arch/arm/include/asm/arch-davinci/pinmux_defs.h
arch/arm/include/asm/arch-omap24xx/bits.h [deleted file]
arch/arm/include/asm/arch-omap24xx/clocks.h [deleted file]
arch/arm/include/asm/arch-omap24xx/i2c.h [deleted file]
arch/arm/include/asm/arch-omap24xx/mem.h [deleted file]
arch/arm/include/asm/arch-omap24xx/mux.h [deleted file]
arch/arm/include/asm/arch-omap24xx/omap2420.h [deleted file]
arch/arm/include/asm/arch-omap24xx/sys_info.h [deleted file]
arch/arm/include/asm/arch-omap24xx/sys_proto.h [deleted file]
arch/arm/include/asm/arch-omap3/clock.h [moved from arch/arm/include/asm/arch-omap3/clocks.h with 100% similarity]
arch/arm/include/asm/arch-omap3/omap3.h
arch/arm/include/asm/arch-omap4/clock.h [moved from arch/arm/include/asm/arch-omap4/clocks.h with 90% similarity]
arch/arm/include/asm/arch-omap4/cpu.h
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/clock.h [moved from arch/arm/include/asm/arch-omap5/clocks.h with 73% similarity]
arch/arm/include/asm/arch-omap5/cpu.h
arch/arm/include/asm/arch-omap5/mux_dra7xx.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/arch-omap5/sys_proto.h
arch/arm/include/asm/arch-tegra/tegra.h
arch/arm/include/asm/arch-vf610/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-vf610/crm_regs.h [new file with mode: 0644]
arch/arm/include/asm/arch-vf610/imx-regs.h [new file with mode: 0644]
arch/arm/include/asm/arch-vf610/iomux-vf610.h [new file with mode: 0644]
arch/arm/include/asm/bootm.h
arch/arm/include/asm/emif.h
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/omap_common.h
arch/arm/include/asm/u-boot-arm.h
arch/arm/lib/Makefile
arch/arm/lib/bootm-fdt.c [moved from board/sorcery/sorcery.c with 50% similarity]
arch/arm/lib/bootm.c
arch/arm/lib/cache.c
arch/arm/lib/crt0.S
arch/arm/lib/relocate.S [new file with mode: 0644]
arch/avr32/lib/board.c
arch/blackfin/cpu/Makefile
arch/blackfin/cpu/cpu.c
arch/blackfin/cpu/gpio.c
arch/blackfin/cpu/initcode.c
arch/blackfin/cpu/start.S
arch/blackfin/include/asm/clock.h [new file with mode: 0644]
arch/blackfin/include/asm/dma.h
arch/blackfin/include/asm/gpio.h
arch/blackfin/include/asm/mach-bf561/BF561_def.h
arch/blackfin/include/asm/mach-bf609/BF609_def.h
arch/blackfin/include/asm/portmux.h
arch/blackfin/include/asm/serial.h [moved from arch/blackfin/cpu/serial.h with 82% similarity]
arch/blackfin/include/asm/serial1.h [moved from arch/blackfin/cpu/serial1.h with 94% similarity]
arch/blackfin/include/asm/serial4.h [moved from arch/blackfin/cpu/serial4.h with 86% similarity]
arch/blackfin/include/asm/soft_switch.h [new file with mode: 0644]
arch/blackfin/lib/board.c
arch/blackfin/lib/clocks.c
arch/blackfin/lib/string.c
arch/m68k/lib/bootm.c
arch/microblaze/include/asm/gpio.h
arch/microblaze/lib/bootm.c
arch/nds32/include/asm/u-boot-nds32.h
arch/nds32/lib/board.c
arch/openrisc/config.mk
arch/openrisc/cpu/u-boot.lds [moved from board/openrisc/openrisc-generic/u-boot.lds with 98% similarity]
arch/powerpc/cpu/mpc8220/config.mk [deleted file]
arch/powerpc/cpu/mpc8220/cpu.c [deleted file]
arch/powerpc/cpu/mpc8220/cpu_init.c [deleted file]
arch/powerpc/cpu/mpc8220/dma.h [deleted file]
arch/powerpc/cpu/mpc8220/dramSetup.c [deleted file]
arch/powerpc/cpu/mpc8220/dramSetup.h [deleted file]
arch/powerpc/cpu/mpc8220/fec.c [deleted file]
arch/powerpc/cpu/mpc8220/fec.h [deleted file]
arch/powerpc/cpu/mpc8220/fec_dma_tasks.S [deleted file]
arch/powerpc/cpu/mpc8220/i2c.c [deleted file]
arch/powerpc/cpu/mpc8220/i2cCore.c [deleted file]
arch/powerpc/cpu/mpc8220/i2cCore.h [deleted file]
arch/powerpc/cpu/mpc8220/interrupts.c [deleted file]
arch/powerpc/cpu/mpc8220/io.S [deleted file]
arch/powerpc/cpu/mpc8220/loadtask.c [deleted file]
arch/powerpc/cpu/mpc8220/pci.c [deleted file]
arch/powerpc/cpu/mpc8220/speed.c [deleted file]
arch/powerpc/cpu/mpc8220/start.S [deleted file]
arch/powerpc/cpu/mpc8220/traps.c [deleted file]
arch/powerpc/cpu/mpc8220/u-boot.lds [deleted file]
arch/powerpc/cpu/mpc8220/uart.c [deleted file]
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
arch/powerpc/cpu/mpc85xx/mp.c
arch/powerpc/cpu/mpc85xx/portals.c
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t1040_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t1040_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_law.h
arch/powerpc/include/asm/fsl_secure_boot.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_8220.h [deleted file]
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/processor.h
arch/powerpc/include/asm/u-boot.h
arch/powerpc/lib/board.c
arch/powerpc/lib/bootm.c
arch/sparc/lib/bootm.c
arch/x86/cpu/Makefile
arch/x86/cpu/coreboot/coreboot.c
arch/x86/cpu/coreboot/timestamp.c
arch/x86/cpu/cpu.c
arch/x86/cpu/interrupts.c
arch/x86/cpu/timer.c [deleted file]
arch/x86/cpu/u-boot.lds
arch/x86/include/asm/arch-coreboot/timestamp.h
arch/x86/include/asm/init_helpers.h
arch/x86/include/asm/pci.h
arch/x86/include/asm/u-boot-x86.h
arch/x86/include/asm/u-boot.h
arch/x86/lib/Makefile
arch/x86/lib/bios.h [deleted file]
arch/x86/lib/board.c [deleted file]
arch/x86/lib/bootm.c
arch/x86/lib/cmd_boot.c
arch/x86/lib/init_helpers.c
arch/x86/lib/init_wrappers.c [deleted file]
arch/x86/lib/pcat_timer.c
arch/x86/lib/pci.c [deleted file]
arch/x86/lib/physmem.c
arch/x86/lib/relocate.c
arch/x86/lib/timer.c [deleted file]
arch/x86/lib/tsc_timer.c [new file with mode: 0644]
arch/x86/lib/zimage.c
board/LaCie/net2big_v2/kwbimage.cfg
board/LaCie/netspace_v2/kwbimage-is2.cfg
board/LaCie/netspace_v2/kwbimage-ns2l.cfg
board/LaCie/netspace_v2/kwbimage.cfg
board/LaCie/wireless_space/kwbimage.cfg
board/Marvell/dreamplug/kwbimage.cfg
board/Marvell/guruplug/kwbimage.cfg
board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
board/Marvell/openrd/kwbimage.cfg
board/Marvell/rd6281a/kwbimage.cfg
board/Seagate/dockstar/kwbimage.cfg
board/Seagate/goflexhome/Makefile [new file with mode: 0644]
board/Seagate/goflexhome/goflexhome.c [new file with mode: 0644]
board/Seagate/goflexhome/kwbimage.cfg [new file with mode: 0644]
board/alaska/README [deleted file]
board/alaska/alaska.c [deleted file]
board/alaska/flash.c [deleted file]
board/armltd/vexpress/Makefile
board/armltd/vexpress/vexpress_common.c [moved from board/armltd/vexpress/ca9x4_ct_vxp.c with 89% similarity]
board/atmel/sama5d3xek/Makefile [moved from board/ti/omap2420h4/Makefile with 77% similarity]
board/atmel/sama5d3xek/sama5d3xek.c [new file with mode: 0644]
board/bf609-ezkit/soft_switch.c [new file with mode: 0644]
board/bf609-ezkit/soft_switch.h [new file with mode: 0644]
board/boundary/nitrogen6x/nitrogen6dl.cfg
board/boundary/nitrogen6x/nitrogen6dl2g.cfg
board/boundary/nitrogen6x/nitrogen6q.cfg
board/boundary/nitrogen6x/nitrogen6q2g.cfg
board/boundary/nitrogen6x/nitrogen6s.cfg
board/boundary/nitrogen6x/nitrogen6s1g.cfg
board/boundary/nitrogen6x/nitrogen6x.c
board/buffalo/lsxl/kwbimage-lschl.cfg
board/buffalo/lsxl/kwbimage-lsxhl.cfg
board/cloudengines/pogo_e02/kwbimage.cfg
board/congatec/cgtqmx6eval/Makefile [new file with mode: 0644]
board/congatec/cgtqmx6eval/README [new file with mode: 0644]
board/congatec/cgtqmx6eval/cgtqmx6eval.c [new file with mode: 0644]
board/d-link/dns325/kwbimage.cfg
board/davinci/da8xxevm/da830evm.c
board/esg/ima3-mx53/imximage.cfg
board/freescale/b4860qds/b4860qds.c
board/freescale/b4860qds/b4860qds_crossbar_con.h
board/freescale/b4860qds/ddr.c
board/freescale/b4860qds/eth_b4860qds.c
board/freescale/b4860qds/law.c
board/freescale/b4860qds/tlb.c
board/freescale/common/qixis.h
board/freescale/corenet_ds/eth_superhydra.c
board/freescale/corenet_ds/pbi.cfg
board/freescale/corenet_ds/rcw_p5040ds.cfg [new file with mode: 0644]
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
board/freescale/mx23evk/mx23evk.c
board/freescale/mx23evk/spl_boot.c
board/freescale/mx25pdk/imximage.cfg
board/freescale/mx28evk/iomux.c
board/freescale/mx28evk/mx28evk.c
board/freescale/mx31pdk/mx31pdk.c
board/freescale/mx51evk/imximage.cfg
board/freescale/mx53ard/imximage_dd3.cfg
board/freescale/mx53evk/imximage.cfg
board/freescale/mx53loco/imximage.cfg
board/freescale/mx53smd/imximage.cfg
board/freescale/mx6qarm2/imximage.cfg
board/freescale/mx6qsabreauto/imximage.cfg
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/p2041rdb/p2041rdb.c
board/freescale/t4qds/ddr.c
board/freescale/t4qds/eth.c
board/freescale/t4qds/law.c
board/freescale/t4qds/t4240qds_qixis.h
board/freescale/t4qds/t4_pbi.cfg [new file with mode: 0644]
board/freescale/t4qds/t4_rcw.cfg [new file with mode: 0644]
board/freescale/t4qds/t4qds.c
board/freescale/t4qds/tlb.c
board/freescale/vf610twr/Makefile [moved from board/sorcery/Makefile with 81% similarity]
board/freescale/vf610twr/imximage.cfg [new file with mode: 0644]
board/freescale/vf610twr/vf610twr.c [new file with mode: 0644]
board/genesi/mx51_efikamx/imximage_mx.cfg
board/genesi/mx51_efikamx/imximage_sb.cfg
board/htkw/mcx/mcx.c
board/icpdas/lp8x4x/Makefile [moved from board/alaska/Makefile with 79% similarity]
board/icpdas/lp8x4x/lp8x4x.c [new file with mode: 0644]
board/iomega/iconnect/kwbimage.cfg
board/isee/igep0033/board.c
board/karo/tk71/kwbimage.cfg
board/karo/tx25/tx25.c
board/keymile/km_arm/km_arm.c
board/keymile/km_arm/kwbimage-memphis.cfg
board/keymile/km_arm/kwbimage.cfg
board/keymile/km_arm/kwbimage_128M16_1.cfg
board/keymile/km_arm/kwbimage_256M8_1.cfg
board/nvidia/beaver/Makefile [new file with mode: 0644]
board/phytec/pcm051/board.c
board/raidsonic/ib62x0/kwbimage.cfg
board/teejet/mt_ventoux/mt_ventoux.c
board/ti/am335x/board.c
board/ti/dra7xx/mux_data.h
board/ti/omap2420h4/config.mk [deleted file]
board/ti/omap2420h4/lowlevel_init.S [deleted file]
board/ti/omap2420h4/mem.c [deleted file]
board/ti/omap2420h4/omap2420h4.c [deleted file]
board/ti/omap2420h4/sys_info.c [deleted file]
board/ti/omap5_uevm/evm.c
board/ti/panda/panda.c
board/ti/sdp4430/sdp.c
board/ti/ti814x/evm.c
board/ttcontrol/vision2/imximage_hynix.cfg
board/wandboard/README
board/wandboard/wandboard.c
board/xilinx/microblaze-generic/microblaze-generic.c
boards.cfg
common/Makefile
common/board_f.c
common/board_r.c
common/bootstage.c
common/cmd_bdinfo.c
common/cmd_bootm.c
common/cmd_fpga.c
common/cmd_mem.c
common/cmd_nvedit.c
common/cmd_softswitch.c [new file with mode: 0644]
common/cmd_source.c
common/cmd_usb.c
common/cmd_ximg.c
common/fdt_support.c
common/hash.c
common/image-fdt.c [new file with mode: 0644]
common/image-fit.c [new file with mode: 0644]
common/image.c
common/spl/Makefile
common/spl/spl_mmc.c [moved from drivers/mmc/spl_mmc.c with 100% similarity]
common/update.c
common/usb.c
common/usb_hub.c
common/usb_kbd.c
common/usb_storage.c
config.mk
doc/README.at91
doc/README.b4860qds
doc/README.fdt-control
doc/README.mxc_ocotp
doc/README.scrapyard
doc/README.t4240qds
doc/README.ubi
doc/README.vf610 [new file with mode: 0644]
doc/README.watchdog
doc/SPL/README.am335x-network
doc/driver-model/UDM-pci.txt
drivers/gpio/Makefile
drivers/gpio/adi_gpio2.c [new file with mode: 0644]
drivers/gpio/xilinx_gpio.c [new file with mode: 0644]
drivers/i2c/omap24xx_i2c.c
drivers/mmc/Makefile
drivers/mmc/davinci_mmc.c
drivers/mmc/fsl_esdhc.c
drivers/mmc/ftsdc010_esdhc.c [deleted file]
drivers/mmc/ftsdc010_mci.c [new file with mode: 0644]
drivers/mmc/mmc.c
drivers/mmc/mv_sdhci.c
drivers/mmc/omap_hsmmc.c
drivers/mmc/s5p_sdhci.c
drivers/mmc/spear_sdhci.c [new file with mode: 0644]
drivers/mtd/cfi_flash.c
drivers/mtd/spi/spansion.c
drivers/net/bfin_mac.c
drivers/net/fec_mxc.c
drivers/net/fm/Makefile
drivers/net/fm/b4860.c
drivers/net/fm/eth.c
drivers/net/fm/fm.h
drivers/net/fm/init.c
drivers/net/fm/t4240.c
drivers/net/phy/teranetics.c
drivers/net/phy/vitesse.c
drivers/net/smc911x.h
drivers/power/palmas.c
drivers/serial/Makefile
drivers/serial/ns16550.c
drivers/serial/serial.c
drivers/serial/serial_bfin.c [moved from arch/blackfin/cpu/serial.c with 79% similarity]
drivers/serial/serial_lpuart.c [new file with mode: 0644]
drivers/serial/serial_ns16550.c
drivers/spi/bfin_spi.c
drivers/usb/eth/smsc95xx.c
drivers/usb/host/ehci-hcd.c
drivers/usb/host/ohci-at91.c
drivers/usb/musb/omap3.c
drivers/video/mxsfb.c
drivers/watchdog/Makefile
drivers/watchdog/bfin_wdt.c [moved from arch/blackfin/cpu/watchdog.c with 64% similarity]
fs/ext4/dev.c
fs/ext4/ext4_common.c
fs/ext4/ext4_common.h
fs/ext4/ext4_journal.c
fs/ext4/ext4_write.c
fs/ext4/ext4fs.c
include/asm-generic/u-boot.h
include/bootstage.h
include/common.h
include/configs/Alaska8220.h [deleted file]
include/configs/B4860QDS.h
include/configs/T4240QDS.h
include/configs/Yukon8220.h [deleted file]
include/configs/am335x_evm.h
include/configs/bf527-ezkit.h
include/configs/bf537-stamp.h
include/configs/bf548-ezkit.h
include/configs/bf561-ezkit.h
include/configs/bf609-ezkit.h
include/configs/bfin_adi_common.h
include/configs/cgtqmx6eval.h [new file with mode: 0644]
include/configs/coreboot.h
include/configs/corenet_ds.h
include/configs/da830evm.h
include/configs/dra7xx_evm.h
include/configs/goflexhome.h [new file with mode: 0644]
include/configs/igep0033.h
include/configs/lp8x4x.h [new file with mode: 0644]
include/configs/microblaze-generic.h
include/configs/mx23evk.h
include/configs/mx28evk.h
include/configs/mx53ard.h
include/configs/mx6qsabre_common.h
include/configs/mx6qsabreauto.h
include/configs/mx6qsabresd.h
include/configs/mx6slevk.h
include/configs/omap2420h4.h [deleted file]
include/configs/omap4_common.h
include/configs/omap5_common.h
include/configs/omap5_uevm.h
include/configs/pcm051.h
include/configs/sama5d3xek.h [new file with mode: 0644]
include/configs/sorcery.h [deleted file]
include/configs/t4qds.h
include/configs/tegra-common-post.h
include/configs/tegra114-common.h
include/configs/tegra20-common.h
include/configs/tegra30-common.h
include/configs/vexpress_ca15_tc2.h [moved from arch/x86/include/asm/init_wrappers.h with 56% similarity]
include/configs/vexpress_ca5x2.h [new file with mode: 0644]
include/configs/vexpress_ca9x4.h [new file with mode: 0644]
include/configs/vexpress_common.h [moved from include/configs/ca9x4_ct_vxp.h with 56% similarity]
include/configs/vf610twr.h [new file with mode: 0644]
include/configs/wandboard.h
include/ext4fs.h
include/ext_common.h
include/faraday/ftsdc010.h
include/fdt.h
include/fdt_support.h
include/fm_eth.h
include/hash.h
include/image.h
include/libfdt.h
include/libfdt_env.h
include/lmb.h
include/mmc.h
include/mpc8220.h [deleted file]
include/mtd/cfi_flash.h
include/netdev.h
include/palmas.h
include/phy.h
include/ppc_asm.tmpl
include/usb.h
include/usb_defs.h
include/watchdog.h
lib/hashtable.c
lib/libfdt/fdt.c
lib/libfdt/fdt_ro.c
spl/Makefile
tools/Makefile
tools/aisimage.c
tools/buildman/control.py
tools/fit_image.c
tools/image-host.c [new file with mode: 0644]
tools/logos/wandboard.bmp [new file with mode: 0644]
tools/mkimage.h
tools/patman/gitutil.py
tools/patman/patman.py
tools/patman/series.py

index c79d577..771b860 100644 (file)
@@ -80,5 +80,11 @@ cscope.*
 /ctags
 /etags
 
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
 # spl ais files
 /spl/*.ais
index efc2ecc..7820375 100644 (file)
@@ -850,6 +850,10 @@ Sricharan R <r.sricharan@ti.com>
        omap4_sdp4430   ARM ARMV7 (OMAP4xx SoC)
        omap5_evm       ARM ARMV7 (OMAP5xx Soc)
 
+Suriyan Ramasami <suriyan.r@gmail.com>
+
+       goflexhome      ARM926EJS (Kirkwood SoC)
+
 Thierry Reding <thierry.reding@avionic-design.de>
 
        plutux          Tegra20 (ARM7 & A9 Dual Core)
@@ -893,6 +897,10 @@ Steve Sakoman <sakoman@gmail.com>
 
        omap3_overo     ARM ARMV7 (OMAP3xx SoC)
 
+Leo Sartre <lsartre@adeneo-embedded.com>
+
+       cgtqmx6qeval            i.MX6Q
+
 Jens Scharsig <esw@bus-elektronik.de>
 
        eb_cpux9k2      ARM920T (AT91RM9200 SoC)
@@ -918,6 +926,7 @@ Matt Sealey <matt@genesi-usa.com>
 
 Bo Shen <voice.shen@atmel.com>
        at91sam9x5ek            ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+       sama5d3xek              ARMV7 (SAMA5D31, D33, D34, D35 SoC)
 
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 
@@ -964,9 +973,14 @@ Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
        SFFSDR          ARM926EJS
 
+Lokesh Vutla <lokeshvutla@ti.com>
+
+       dra7xx_evm      ARM ARMV7 (DRA7xx Soc)
+
 Matt Waddel <matt.waddel@linaro.org>
 
-       ca9x4_ct_vxp    ARM ARMV7 (Quad Core)
+       vexpress_ca9x4  ARM ARMV7 (Quad Core)
+       vexpress_ca5x2  ARM ARMV7 (Dual Core)
 
 Otavio Salvador <otavio@ossystems.com.br>
 
@@ -1019,10 +1033,6 @@ Matthias Weisser <weisserm@arcor.de>
        jadecpu         ARM926EJS (MB86R01 SoC)
        zmx25           ARM926EJS (imx25 SoC)
 
-Richard Woodruff <r-woodruff2@ti.com>
-
-       omap2420h4      ARM1136EJS
-
 Josh Wu <josh.wu@atmel.com>
        at91sam9n12ek   ARM926EJS (AT91SAM9N12 SoC)
 
@@ -1060,6 +1070,14 @@ Eric Nelson <eric.nelson@boundarydevices.com>
        nitrogen6s              i.MX6S          512MB
        nitrogen6s1g            i.MX6S          1GB
 
+Alison Wang <b18965@freescale.com>
+
+       vf610twr        VF610
+
+Sergey Yanovich <ynvich@gmail.com>
+
+       lp8x4x          xscale/pxa
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -1080,9 +1098,19 @@ Unknown / orphaned boards:
 #      Board           CPU                                             #
 #########################################################################
 
-Graeme Russ <graeme.russ@gmail.com>
+Simon Glass <sjg@chromium.org>
+
+       chromebook-x86  Coreboot runs first, then U-Boot
+                       Supports Intel Sandy Bridge / Ivy Bridge so far
 
-       eNET            AMD SC520
+                       Chromebooks for x86, including:
+                               Samsung Series 5 Chromebook
+                               Acer AC700 Chromebook
+                               Acer C7 Chromebook
+                               Samsung Chromebook 550
+                               HP Pavillion Chromebook
+                               Acer C710 Chromebook
+                               Chromebook Pixel
 
 #########################################################################
 # MIPS Systems:                                                                #
@@ -1347,6 +1375,17 @@ Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
        openrisc-generic        OpenRISC
 
+#########################################################################
+# Sandbox:                                                             #
+#                                                                      #
+# Maintainer Name, Email Address                                       #
+#      Board           CPU                                             #
+#########################################################################
+
+Simon Glass <sjg@chromium.org>
+
+       sandbox         sandbox
+
 #########################################################################
 # End of MAINTAINERS list                                              #
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 2737eab..2e16e0d 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -267,12 +267,6 @@ LIST_8xx="$(boards_by_cpu mpc8xx)"
 
 LIST_4xx="$(boards_by_cpu ppc4xx)"
 
-#########################################################################
-## MPC8220 Systems
-#########################################################################
-
-LIST_8220="$(boards_by_cpu mpc8220)"
-
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -324,7 +318,6 @@ LIST_powerpc="              \
        ${LIST_512x}    \
        ${LIST_5xxx}    \
        ${LIST_8xx}     \
-       ${LIST_8220}    \
        ${LIST_824x}    \
        ${LIST_8260}    \
        ${LIST_83xx}    \
index c52f0f1..af4c3c0 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
 LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
 endif
 
@@ -543,18 +543,15 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
                cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
 
 ifneq ($(CONFIG_TEGRA),)
-ifeq ($(CONFIG_OF_SEPARATE),y)
-nodtb=dtb
-dtbfile=$(obj)u-boot.dtb
-else
-nodtb=nodtb
-dtbfile=
-endif
-
-$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
                $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
+               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
                rm $(obj)spl/u-boot-spl-pad.bin
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
+               cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+endif
 endif
 
 $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
diff --git a/README b/README
index b72ab2f..b1b3e17 100644 (file)
--- a/README
+++ b/README
@@ -201,7 +201,6 @@ Directory Hierarchy:
       /mpc5xx          Files specific to Freescale MPC5xx CPUs
       /mpc5xxx         Files specific to Freescale MPC5xxx CPUs
       /mpc8xx          Files specific to Freescale MPC8xx CPUs
-      /mpc8220         Files specific to Freescale MPC8220 CPUs
       /mpc824x         Files specific to Freescale MPC824x CPUs
       /mpc8260         Files specific to Freescale MPC8260 CPUs
       /mpc85xx         Files specific to Freescale MPC85xx CPUs
@@ -899,6 +898,7 @@ The following options need to be configured:
                CONFIG_CMD_SF           * Read/write/erase SPI NOR flash
                CONFIG_CMD_SHA1SUM        print sha1 memory digest
                                          (requires CONFIG_CMD_MEMORY)
+               CONFIG_CMD_SOFTSWITCH   * Soft switch setting command for BF60x
                CONFIG_CMD_SOURCE         "source" command Support
                CONFIG_CMD_SPI          * SPI serial bus support
                CONFIG_CMD_TFTPSRV      * TFTP transfer in server mode
@@ -2997,6 +2997,12 @@ FIT uImage format:
                use an arch-specific makefile fragment instead, for
                example if more than one image needs to be produced.
 
+               CONFIG_FIT_SPL_PRINT
+               Printing information about a FIT image adds quite a bit of
+               code to SPL. So this is normally disabled in SPL. Use this
+               option to re-enable it. This will affect the output of the
+               bootm command when booting a FIT image.
+
 Modem Support:
 --------------
 
@@ -5062,7 +5068,7 @@ On some platforms, it's possible to boot Linux zImage. This is done
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.
 
-Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
+Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".
index a3d981f..ceb1271 100644 (file)
@@ -55,8 +55,6 @@ int platform_sys_info(struct sys_info *si)
 #define bi_bar bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar bi_immrbar
-#elif defined(CONFIG_MPC8220)
-#define bi_bar bi_mbar_base
 #endif
 
 #if defined(bi_bar)
index 461899e..dc64160 100644 (file)
@@ -31,6 +31,9 @@ CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif
 
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
 
index ccea2d5..a7e0c28 100644 (file)
@@ -104,10 +104,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -146,24 +142,6 @@ reset:
        orr     r0,r0,#0xd3
        msr     cpsr,r0
 
-#ifdef CONFIG_OMAP2420H4
-       /* Copy vectors to mask ROM indirect addr */
-       adr     r0, _start              /* r0 <- current position of code   */
-               add     r0, r0, #4                              /* skip reset vector                    */
-       mov     r2, #64                 /* r2 <- size to copy  */
-       add     r2, r0, r2              /* r2 <- source end address         */
-       mov     r1, #SRAM_OFFSET0         /* build vect addr */
-       mov     r3, #SRAM_OFFSET1
-       add     r1, r1, r3
-       mov     r3, #SRAM_OFFSET2
-       add     r1, r1, r3
-next:
-       ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
-       stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       bne     next                    /* loop until equal */
-       bl      cpy_clk_code            /* put dpll adjust code behind vectors */
-#endif
        /* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl  cpu_init_crit
@@ -173,83 +151,6 @@ next:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
-#endif
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index f20da8e..65292bc 100644 (file)
@@ -112,10 +112,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -225,79 +221,6 @@ skip_tcmdisable:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 9facc7e..a396ebc 100644 (file)
@@ -101,10 +101,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -155,79 +151,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
@@ -244,9 +167,9 @@ c_runtime_cpu_setup:
  *************************************************************************
  */
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 
-#if !defined(CONFIG_TEGRA)
        mov     ip, lr
        /*
         * before relocating, we have to setup RAM timing
@@ -255,9 +178,9 @@ cpu_init_crit:
         */
        bl      lowlevel_init
        mov     lr, ip
-#endif
 
        mov     pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 
 #ifndef CONFIG_SPL_BUILD
index 6250025..3232065 100644 (file)
@@ -89,10 +89,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -194,79 +190,6 @@ copyex:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 021e241..97eb276 100644 (file)
@@ -95,10 +95,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -184,79 +180,6 @@ poll1:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index dec7bfb..bba4671 100644 (file)
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_SOC_DM355)     += dm355.o
 COBJS-$(CONFIG_SOC_DM365)      += dm365.o
 COBJS-$(CONFIG_SOC_DM644X)     += dm644x.o
 COBJS-$(CONFIG_SOC_DM646X)     += dm646x.o
+COBJS-$(CONFIG_SOC_DA830)      += da830_pinmux.o
 COBJS-$(CONFIG_SOC_DA850)      += da850_pinmux.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
 
diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
new file mode 100644 (file)
index 0000000..d0c964a
--- /dev/null
@@ -0,0 +1,151 @@
+/*
+ * Pinmux configurations for the DA830 SoCs
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI0 pin muxer settings */
+const struct pinmux_config spi0_pins_base[] = {
+       { pinmux(7), 1, 3 },  /* SPI0_SOMI */
+       { pinmux(7), 1, 4 },  /* SPI0_SIMO */
+       { pinmux(7), 1, 6 }   /* SPI0_CLK */
+};
+
+const struct pinmux_config spi0_pins_scs0[] = {
+       { pinmux(7), 1, 7 }   /* SPI0_SCS[0] */
+};
+
+const struct pinmux_config spi0_pins_ena[] = {
+       { pinmux(7), 1, 5 }   /* SPI0_ENA */
+};
+
+/* NAND pin muxer settings */
+const struct pinmux_config emifa_pins_cs0[] = {
+       { pinmux(18), 1, 2 }   /* EMA_CS[0] */
+};
+
+const struct pinmux_config emifa_pins_cs2[] = {
+       { pinmux(18), 1, 3 }   /* EMA_CS[2] */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+       { pinmux(18), 1, 4 }   /* EMA_CS[3] */
+};
+
+#ifdef CONFIG_USE_NAND
+const struct pinmux_config emifa_pins[] = {
+       { pinmux(13), 1, 6 },  /* EMA_D[0] */
+       { pinmux(13), 1, 7 },  /* EMA_D[1] */
+       { pinmux(14), 1, 0 },  /* EMA_D[2] */
+       { pinmux(14), 1, 1 },  /* EMA_D[3] */
+       { pinmux(14), 1, 2 },  /* EMA_D[4] */
+       { pinmux(14), 1, 3 },  /* EMA_D[5] */
+       { pinmux(14), 1, 4 },  /* EMA_D[6] */
+       { pinmux(14), 1, 5 },  /* EMA_D[7] */
+       { pinmux(14), 1, 6 },  /* EMA_D[8] */
+       { pinmux(14), 1, 7 },  /* EMA_D[9] */
+       { pinmux(15), 1, 0 },  /* EMA_D[10] */
+       { pinmux(15), 1, 1 },  /* EMA_D[11] */
+       { pinmux(15), 1, 2 },  /* EMA_D[12] */
+       { pinmux(15), 1, 3 },  /* EMA_D[13] */
+       { pinmux(15), 1, 4 },  /* EMA_D[14] */
+       { pinmux(15), 1, 5 },  /* EMA_D[15] */
+       { pinmux(15), 1, 6 },  /* EMA_A[0] */
+       { pinmux(15), 1, 7 },  /* EMA_A[1] */
+       { pinmux(16), 1, 0 },  /* EMA_A[2] */
+       { pinmux(16), 1, 1 },  /* EMA_A[3] */
+       { pinmux(16), 1, 2 },  /* EMA_A[4] */
+       { pinmux(16), 1, 3 },  /* EMA_A[5] */
+       { pinmux(16), 1, 4 },  /* EMA_A[6] */
+       { pinmux(16), 1, 5 },  /* EMA_A[7] */
+       { pinmux(16), 1, 6 },  /* EMA_A[8] */
+       { pinmux(16), 1, 7 },  /* EMA_A[9] */
+       { pinmux(17), 1, 0 },  /* EMA_A[10] */
+       { pinmux(17), 1, 1 },  /* EMA_A[11] */
+       { pinmux(17), 1, 2 },  /* EMA_A[12] */
+       { pinmux(17), 1, 3 },  /* EMA_BA[1] */
+       { pinmux(17), 1, 4 },  /* EMA_BA[0] */
+       { pinmux(17), 1, 5 },  /* EMA_CLK */
+       { pinmux(17), 1, 6 },  /* EMA_SDCKE */
+       { pinmux(17), 1, 7 },  /* EMA_CAS */
+       { pinmux(18), 1, 0 },  /* EMA_CAS */
+       { pinmux(18), 1, 1 },  /* EMA_WE */
+       { pinmux(18), 1, 5 },  /* EMA_OE */
+       { pinmux(18), 1, 6 },  /* EMA_WE_DQM[1] */
+       { pinmux(18), 1, 7 },  /* EMA_WE_DQM[0] */
+       { pinmux(10), 1, 0 }   /* Tristate */
+};
+#endif
+
+/* EMAC PHY interface pins */
+const struct pinmux_config emac_pins_rmii[] = {
+       { pinmux(10), 2, 1 },  /* RMII_TXD[0] */
+       { pinmux(10), 2, 2 },  /* RMII_TXD[1] */
+       { pinmux(10), 2, 3 },  /* RMII_TXEN */
+       { pinmux(10), 2, 4 },  /* RMII_CRS_DV */
+       { pinmux(10), 2, 5 },  /* RMII_RXD[0] */
+       { pinmux(10), 2, 6 },  /* RMII_RXD[1] */
+       { pinmux(10), 2, 7 }   /* RMII_RXER */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+       { pinmux(11), 2, 0 },  /* MDIO_CLK */
+       { pinmux(11), 2, 1 }   /* MDIO_D */
+};
+
+const struct pinmux_config emac_pins_rmii_clk_source[] = {
+       { pinmux(9), 0, 5 }    /* ref.clk from external source */
+};
+
+/* UART2 pin muxer settings */
+const struct pinmux_config uart2_pins_txrx[] = {
+       { pinmux(8), 2, 7 },   /* UART2_RXD */
+       { pinmux(9), 2, 0 }    /* UART2_TXD */
+};
+
+/* I2C0 pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+       { pinmux(8), 2, 3 },   /* I2C0_SDA */
+       { pinmux(8), 2, 4 }    /* I2C0_SCL */
+};
+
+/* USB0_DRVVBUS pin muxer settings */
+const struct pinmux_config usb_pins[] = {
+       { pinmux(9), 1, 1 }    /* USB0_DRVVBUS */
+};
+
+#ifdef CONFIG_DAVINCI_MMC
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins_8bit[] = {
+       { pinmux(15), 2, 7 },  /* MMCSD0_CLK */
+       { pinmux(16), 2, 0 },  /* MMCSD0_CMD */
+       { pinmux(13), 2, 6 },  /* MMCSD0_DAT_0 */
+       { pinmux(13), 2, 7 },  /* MMCSD0_DAT_1 */
+       { pinmux(14), 2, 0 },  /* MMCSD0_DAT_2 */
+       { pinmux(14), 2, 1 },  /* MMCSD0_DAT_3 */
+       { pinmux(14), 2, 2 },  /* MMCSD0_DAT_4 */
+       { pinmux(14), 2, 3 },  /* MMCSD0_DAT_5 */
+       { pinmux(14), 2, 4 },  /* MMCSD0_DAT_6 */
+       { pinmux(14), 2, 5 }   /* MMCSD0_DAT_7 */
+       /* DA830 supports 8-bit mode */
+};
+#endif
index a5e388b..45667bd 100644 (file)
@@ -76,13 +76,32 @@ void enable_caches(void)
 #endif
 }
 
+/*
+ * This function will craft a jumptable at 0x0 which will redirect interrupt
+ * vectoring to proper location of U-Boot in RAM.
+ *
+ * The structure of the jumptable will be as follows:
+ *  ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
+ *  <destination address> ... for each previous ldr, thus also repeated 8 times
+ *
+ * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
+ * offset 0x18 from current value of PC register. Note that PC is already
+ * incremented by 4 when computing the offset, so the effective offset is
+ * actually 0x20, this the associated <destination address>. Loading the PC
+ * register with an address performs a jump to that address.
+ */
 void mx28_fixup_vt(uint32_t start_addr)
 {
-       uint32_t *vt = (uint32_t *)0x20;
+       /* ldr pc, [pc, #0x18] */
+       const uint32_t ldr_pc = 0xe59ff018;
+       /* Jumptable location is 0x0 */
+       uint32_t *vt = (uint32_t *)0x0;
        int i;
 
-       for (i = 0; i < 8; i++)
-               vt[i] = start_addr + (4 * i);
+       for (i = 0; i < 8; i++) {
+               vt[i] = ldr_pc;
+               vt[i + 8] = start_addr + (4 * i);
+       }
 }
 
 #ifdef CONFIG_ARCH_MISC_INIT
index 4c56711..5fc8e04 100644 (file)
@@ -136,10 +136,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -190,83 +186,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
-#endif
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 9c2b70d..e9d0c34 100644 (file)
@@ -105,10 +105,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -159,79 +155,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 5e8c528..8dfd919 100644 (file)
@@ -101,10 +101,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -155,79 +151,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
similarity index 71%
rename from arch/powerpc/cpu/mpc8220/Makefile
rename to arch/arm/cpu/armv7/at91/Makefile
index b8529ef..040c67d 100644 (file)
@@ -1,7 +1,10 @@
 #
-# (C) Copyright 2003-2006
+# (C) Copyright 2000-2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -12,7 +15,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 
 include $(TOPDIR)/config.mk
 
-LIB    = $(obj)lib$(CPU).o
+LIB    = $(obj)lib$(SOC).o
 
-START  = start.o
-SOBJS  = io.o fec_dma_tasks.o
-COBJS  = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
-         interrupts.o loadtask.o speed.o \
-         traps.o uart.o pci.o
+COBJS-$(CONFIG_SAMA5D3)        += sama5d3_devices.o
+COBJS-y += clock.o
+COBJS-y += cpu.o
+COBJS-y += reset.o
+COBJS-y += timer.o
 
-SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
-START  := $(addprefix $(obj),$(START))
+SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
-all:   $(obj).depend $(START) $(LIB)
+all:   $(obj).depend $(LIB)
 
 $(LIB):        $(OBJS)
        $(call cmd_link_o_target, $(OBJS))
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
new file mode 100644 (file)
index 0000000..624b52c
--- /dev/null
@@ -0,0 +1,125 @@
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+       switch (css) {
+       case AT91_PMC_MCKR_CSS_SLOW:
+               return CONFIG_SYS_AT91_SLOW_CLOCK;
+       case AT91_PMC_MCKR_CSS_MAIN:
+               return gd->arch.main_clk_rate_hz;
+       case AT91_PMC_MCKR_CSS_PLLA:
+               return gd->arch.plla_rate_hz;
+       }
+
+       return 0;
+}
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+       unsigned mul, div;
+
+       div = reg & 0xff;
+       mul = (reg >> 18) & 0x7f;
+       if (div && mul) {
+               freq /= div;
+               freq *= mul + 1;
+       } else {
+               freq = 0;
+       }
+
+       return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+       unsigned freq, mckr;
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+       unsigned tmp;
+       /*
+        * When the bootloader initialized the main oscillator correctly,
+        * there's no problem using the cycle counter.  But if it didn't,
+        * or when using oscillator bypass mode, we must be told the speed
+        * of the main clock.
+        */
+       if (!main_clock) {
+               do {
+                       tmp = readl(&pmc->mcfr);
+               } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+               tmp &= AT91_PMC_MCFR_MAINF_MASK;
+               main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+       }
+#endif
+       gd->arch.main_clk_rate_hz = main_clock;
+
+       /* report if PLLA is more than mildly overclocked */
+       gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+       /*
+        * MCK and CPU derive from one of those primary clocks.
+        * For now, assume this parentage won't change.
+        */
+       mckr = readl(&pmc->mckr);
+
+       /* plla divisor by 2 */
+       if (mckr & (1 << 12))
+               gd->arch.plla_rate_hz >>= 1;
+
+       gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+       freq = gd->arch.mck_rate_hz;
+
+       /* prescale */
+       freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
+
+       switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
+       case AT91_PMC_MCKR_MDIV_2:
+               gd->arch.mck_rate_hz = freq / 2;
+               break;
+       case AT91_PMC_MCKR_MDIV_3:
+               gd->arch.mck_rate_hz = freq / 3;
+               break;
+       case AT91_PMC_MCKR_MDIV_4:
+               gd->arch.mck_rate_hz = freq / 4;
+               break;
+       default:
+               break;
+       }
+
+       gd->arch.cpu_clk_rate_hz = freq;
+
+       return 0;
+}
+
+void at91_periph_clk_enable(int id)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       if (id > 31)
+               writel(1 << (id - 32), &pmc->pcer1);
+       else
+               writel(1 << id, &pmc->pcer);
+}
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
new file mode 100644 (file)
index 0000000..3df6143
--- /dev/null
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_dbu.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+       return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
+
+void arch_preboot_os(void)
+{
+       ulong cpiv;
+       at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+       cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+       /*
+        * Disable PITC
+        * Add 0x1000 to current counter to stop it faster
+        * without waiting for wrapping back to 0
+        */
+       writel(cpiv + 0x1000, &pit->mr);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+       char buf[32];
+
+       printf("CPU: %s\n", get_cpu_name());
+       printf("Crystal frequency: %8s MHz\n",
+              strmhz(buf, get_main_clk_rate()));
+       printf("CPU clock        : %8s MHz\n",
+              strmhz(buf, get_cpu_clk_rate()));
+       printf("Master clock     : %8s MHz\n",
+              strmhz(buf, get_mck_clk_rate()));
+
+       return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+}
+
+unsigned int get_chip_id(void)
+{
+       return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+       return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+}
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c
new file mode 100644 (file)
index 0000000..b9f83d9
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
+
+/* Reset the cpu by telling the reset controller to do so */
+void reset_cpu(ulong ignored)
+{
+       at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+       writel(AT91_RSTC_KEY
+               | AT91_RSTC_CR_PROCRST  /* Processor Reset */
+               | AT91_RSTC_CR_PERRST   /* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+               | AT91_RSTC_CR_EXTRST   /* External Reset (assert nRST pin) */
+#endif
+               , &rstc->cr);
+       /* never reached */
+       do { } while (1);
+}
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
new file mode 100644 (file)
index 0000000..acf8b43
--- /dev/null
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2012-2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sama5d3.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int has_emac()
+{
+       return cpu_is_sama5d31() || cpu_is_sama5d35();
+}
+
+unsigned int has_gmac()
+{
+       return !cpu_is_sama5d31();
+}
+
+unsigned int has_lcdc()
+{
+       return !cpu_is_sama5d35();
+}
+
+char *get_cpu_name()
+{
+       unsigned int extension_id = get_extension_chip_id();
+
+       if (cpu_is_sama5d3())
+               switch (extension_id) {
+               case ARCH_EXID_SAMA5D31:
+                       return "SAMA5D31";
+               case ARCH_EXID_SAMA5D33:
+                       return "SAMA5D33";
+               case ARCH_EXID_SAMA5D34:
+                       return "SAMA5D34";
+               case ARCH_EXID_SAMA5D35:
+                       return "SAMA5D35";
+               default:
+                       return "Unknown CPU type";
+               }
+       else
+               return "Unknown CPU type";
+}
+
+void at91_serial0_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTD, 18, 1);       /* TXD0 */
+       at91_set_a_periph(AT91_PIO_PORTD, 17, 0);       /* RXD0 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_USART0);
+}
+
+void at91_serial1_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTB, 29, 1);       /* TXD1 */
+       at91_set_a_periph(AT91_PIO_PORTB, 28, 0);       /* RXD1 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+void at91_serial2_hw_init(void)
+{
+       at91_set_b_periph(AT91_PIO_PORTE, 26, 1);       /* TXD2 */
+       at91_set_b_periph(AT91_PIO_PORTE, 25, 0);       /* RXD2 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_USART2);
+}
+
+void at91_seriald_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTB, 31, 1);       /* DTXD */
+       at91_set_a_periph(AT91_PIO_PORTB, 30, 0);       /* DRXD */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_SYS);
+}
+
+#if defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+       at91_set_a_periph(AT91_PIO_PORTD, 10, 0);       /* SPI0_MISO */
+       at91_set_a_periph(AT91_PIO_PORTD, 11, 0);       /* SPI0_MOSI */
+       at91_set_a_periph(AT91_PIO_PORTD, 12, 0);       /* SPI0_SPCK */
+
+       if (cs_mask & (1 << 0))
+               at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+       if (cs_mask & (1 << 1))
+               at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+       if (cs_mask & (1 << 2))
+               at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+       if (cs_mask & (1 << 3))
+               at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTD, 0, 0);        /* MCI0 CMD */
+       at91_set_a_periph(AT91_PIO_PORTD, 1, 0);        /* MCI0 DA0 */
+       at91_set_a_periph(AT91_PIO_PORTD, 2, 0);        /* MCI0 DA1 */
+       at91_set_a_periph(AT91_PIO_PORTD, 3, 0);        /* MCI0 DA2 */
+       at91_set_a_periph(AT91_PIO_PORTD, 4, 0);        /* MCI0 DA3 */
+#ifdef CONFIG_ATMEL_MCI_8BIT
+       at91_set_a_periph(AT91_PIO_PORTD, 5, 0);        /* MCI0 DA4 */
+       at91_set_a_periph(AT91_PIO_PORTD, 6, 0);        /* MCI0 DA5 */
+       at91_set_a_periph(AT91_PIO_PORTD, 7, 0);        /* MCI0 DA6 */
+       at91_set_a_periph(AT91_PIO_PORTD, 8, 0);        /* MCI0 DA7 */
+#endif
+       at91_set_a_periph(AT91_PIO_PORTD, 9, 0);        /* MCI0 CLK */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* ETXCK_EREFCK */
+       at91_set_a_periph(AT91_PIO_PORTC, 5, 0);        /* ERXDV */
+       at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* ERX0 */
+       at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* ERX1 */
+       at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* ERXER */
+       at91_set_a_periph(AT91_PIO_PORTC, 4, 0);        /* ETXEN */
+       at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* ETX0 */
+       at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* ETX1 */
+       at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* EMDIO */
+       at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* EMDC */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_EMAC);
+}
+#endif
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTA, 24, 0);       /* LCDPWM */
+       at91_set_a_periph(AT91_PIO_PORTA, 25, 0);       /* LCDDISP */
+       at91_set_a_periph(AT91_PIO_PORTA, 26, 0);       /* LCDVSYNC */
+       at91_set_a_periph(AT91_PIO_PORTA, 27, 0);       /* LCDHSYNC */
+       at91_set_a_periph(AT91_PIO_PORTA, 28, 0);       /* LCDDOTCK */
+       at91_set_a_periph(AT91_PIO_PORTA, 29, 0);       /* LCDDEN */
+
+       /* The lower 16-bit of LCD only available on Port A */
+       at91_set_a_periph(AT91_PIO_PORTA,  0, 0);       /* LCDD0 */
+       at91_set_a_periph(AT91_PIO_PORTA,  1, 0);       /* LCDD1 */
+       at91_set_a_periph(AT91_PIO_PORTA,  2, 0);       /* LCDD2 */
+       at91_set_a_periph(AT91_PIO_PORTA,  3, 0);       /* LCDD3 */
+       at91_set_a_periph(AT91_PIO_PORTA,  4, 0);       /* LCDD4 */
+       at91_set_a_periph(AT91_PIO_PORTA,  5, 0);       /* LCDD5 */
+       at91_set_a_periph(AT91_PIO_PORTA,  6, 0);       /* LCDD6 */
+       at91_set_a_periph(AT91_PIO_PORTA,  7, 0);       /* LCDD7 */
+       at91_set_a_periph(AT91_PIO_PORTA,  8, 0);       /* LCDD8 */
+       at91_set_a_periph(AT91_PIO_PORTA,  9, 0);       /* LCDD9 */
+       at91_set_a_periph(AT91_PIO_PORTA, 10, 0);       /* LCDD10 */
+       at91_set_a_periph(AT91_PIO_PORTA, 11, 0);       /* LCDD11 */
+       at91_set_a_periph(AT91_PIO_PORTA, 12, 0);       /* LCDD12 */
+       at91_set_a_periph(AT91_PIO_PORTA, 13, 0);       /* LCDD13 */
+       at91_set_a_periph(AT91_PIO_PORTA, 14, 0);       /* LCDD14 */
+       at91_set_a_periph(AT91_PIO_PORTA, 15, 0);       /* LCDD15 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
new file mode 100644 (file)
index 0000000..b3a450f
--- /dev/null
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <div64.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * We're using the SAMA5D3x PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
+ */
+
+#define TIMER_LOAD_VAL 0xfffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+       tick *= CONFIG_SYS_HZ;
+       do_div(tick, gd->arch.timer_rate_hz);
+
+       return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+       usec *= gd->arch.timer_rate_hz;
+       do_div(usec, 1000000);
+
+       return usec;
+}
+
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
+int timer_init(void)
+{
+       at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+       /* Enable PITC Clock */
+       at91_periph_clk_enable(ATMEL_ID_SYS);
+
+       /* Enable PITC */
+       writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
+
+       gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+       gd->arch.tbu = 0;
+       gd->arch.tbl = 0;
+
+       return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+       at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+       ulong now = readl(&pit->piir);
+
+       /* increment tbu if tbl has rolled over */
+       if (now < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl = now;
+       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+       unsigned long long start;
+       ulong tmo;
+
+       start = get_ticks();            /* get current timestamp */
+       tmo = usec_to_tick(usec);       /* convert usecs to ticks */
+       while ((get_ticks() - start) < tmo)
+               ;                       /* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+       return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return gd->arch.timer_rate_hz;
+}
index 55e82ba..c4b9809 100644 (file)
@@ -34,6 +34,7 @@ COBJS += hwinit-common.o
 COBJS  += clocks-common.o
 COBJS  += emif-common.o
 COBJS  += vc.o
+COBJS  += abb.o
 endif
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c
new file mode 100644 (file)
index 0000000..87d1fb8
--- /dev/null
@@ -0,0 +1,137 @@
+/*
+ *
+ * Adaptive Body Bias programming sequence for OMAP family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+       return -1;
+}
+
+static void abb_setup_timings(u32 setup)
+{
+       u32 sys_rate, sr2_cnt, clk_cycles;
+
+       /*
+        * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
+        * transition and must be programmed with the correct time at boot.
+        * The value programmed into the register is the number of SYS_CLK
+        * clock cycles that match a given wall time profiled for the ldo.
+        * This value depends on:
+        * settling time of ldo in micro-seconds (varies per OMAP family),
+        * of clock cycles per SYS_CLK period (varies per OMAP family),
+        * the SYS_CLK frequency in MHz (varies per board)
+        * The formula is:
+        *
+        *                     ldo settling time (in micro-seconds)
+        * SR2_WTCNT_VALUE = ------------------------------------------
+        *                  (# system clock cycles) * (sys_clk period)
+        *
+        * Put another way:
+        *
+        * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
+        *
+        * To avoid dividing by zero multiply both "# clock cycles" and
+        * "settling time" by 10 such that the final result is the one we want.
+        */
+
+       /* calculate SR2_WTCNT_VALUE */
+       sys_rate = DIV_ROUND(V_OSCK, 1000000);
+       clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
+       sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
+
+       setbits_le32(setup,
+                    sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
+}
+
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+              u32 txdone, u32 txdone_mask, u32 opp)
+{
+       u32 abb_type_mask, opp_sel_mask;
+
+       /* sanity check */
+       if (!setup || !control || !txdone)
+               return;
+
+       /* setup ABB only in case of Fast or Slow OPP */
+       switch (opp) {
+       case OMAP_ABB_FAST_OPP:
+               abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK;
+               opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK;
+               break;
+       case OMAP_ABB_SLOW_OPP:
+               abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK;
+               opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK;
+               break;
+       default:
+              return;
+       }
+
+       /*
+        * For some OMAP silicons additional setup for LDOVBB register is
+        * required. This is determined by data retrieved from corresponding
+        * OPP EFUSE register. Data, which is retrieved from EFUSE - is
+        * ABB enable/disable flag and VSET value, which must be copied
+        * to LDOVBB register. If function call fails - return quietly,
+        * it means no ABB is required for such silicon.
+        *
+        * For silicons, which don't require LDOVBB setup "fuse" and
+        * "ldovbb" offsets are not defined. ABB will be initialized in
+        * the common way for them.
+        */
+       if (fuse && ldovbb) {
+               if (abb_setup_ldovbb(fuse, ldovbb))
+                       return;
+       }
+
+       /* clear ABB registers */
+       writel(0, setup);
+       writel(0, control);
+
+       /* configure timings, based on oscillator value */
+       abb_setup_timings(setup);
+
+       /* clear pending interrupts before setup */
+       setbits_le32(txdone, txdone_mask);
+
+       /* select ABB type */
+       setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK);
+
+       /* initiate ABB ldo change */
+       setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
+
+       /* wait until transition complete */
+       if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY))
+               puts("Error: ABB txdone is not set\n");
+
+       /* clear ABB tranxdone */
+       setbits_le32(txdone, txdone_mask);
+}
index bff7e9c..76ae1b6 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void save_omap_boot_params(void)
+{
+       u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+       u8 boot_device;
+       u32 dev_desc, dev_data;
+
+       if ((rom_params <  NON_SECURE_SRAM_START) ||
+           (rom_params > NON_SECURE_SRAM_END))
+               return;
+
+       /*
+        * rom_params can be type casted to omap_boot_parameters and
+        * used. But it not correct to assume that romcode structure
+        * encoding would be same as u-boot. So use the defined offsets.
+        */
+       gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+                                  *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+       gd->arch.omap_boot_params.ch_flags =
+                               *((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+       if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+           (boot_device <= MMC_BOOT_DEVICES_END)) {
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX)
+               if ((omap_hw_init_context() ==
+                                     OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+                       gd->arch.omap_boot_params.omap_bootmode =
+                       *((u8 *)(rom_params + BOOT_MODE_OFFSET));
+               } else
+#endif
+               {
+                       dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+                       dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+                       gd->arch.omap_boot_params.omap_bootmode =
+                                       *((u32 *)(dev_data + BOOT_MODE_OFFSET));
+               }
+       }
+}
+
 #ifdef CONFIG_SPL_BUILD
 u32 spl_boot_device(void)
 {
index 99910cd..ef23127 100644 (file)
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <i2c.h>
 #include <asm/omap_common.h>
 #include <asm/gpio.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/utils.h>
 #include <asm/omap_gpio.h>
 
 const u32 sys_clk_array[8] = {
        12000000,              /* 12 MHz */
-       13000000,              /* 13 MHz */
+       20000000,               /* 20 MHz */
        16800000,              /* 16.8 MHz */
        19200000,              /* 19.2 MHz */
        26000000,              /* 26 MHz */
        27000000,              /* 27 MHz */
        38400000,              /* 38.4 MHz */
-       20000000,               /* 20 MHz */
 };
 
 static inline u32 __get_sys_clk_index(void)
@@ -74,13 +74,6 @@ static inline u32 __get_sys_clk_index(void)
                /* SYS_CLKSEL - 1 to match the dpll param array indices */
                ind = (readl((*prcm)->cm_sys_clksel) &
                        CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
-               /*
-                * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
-                * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
-                * NUM_SYS_CLK. So considering the last 3 bits as the index
-                * for the dpll param array.
-                */
-               ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
        }
        return ind;
 }
@@ -440,6 +433,12 @@ static void setup_non_essential_dplls(void)
        params = get_abe_dpll_params(*dplls_data);
 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
        abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+
+       if (omap_revision() == DRA752_ES1_0)
+               /* Select the sys clk for dpll_abe */
+               clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
+                               CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
+                               CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
 #else
        abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
        /*
@@ -487,6 +486,10 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
        u32 offset = volt_mv;
        int ret = 0;
 
+       if (!volt_mv)
+               return;
+
+       pmic->pmic_bus_init();
        /* See if we can first get the GPIO if needed */
        if (pmic->gpio_en)
                ret = gpio_request(pmic->gpio, "PMIC_GPIO");
@@ -509,14 +512,45 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
        debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
                offset_code);
 
-       if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
-                               vcore_reg, offset_code))
+       if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
                printf("Scaling voltage failed for 0x%x\n", vcore_reg);
 
        if (pmic->gpio_en)
                gpio_direction_output(pmic->gpio, 1);
 }
 
+static u32 optimize_vcore_voltage(struct volts const *v)
+{
+       u32 val;
+       if (!v->value)
+               return 0;
+       if (!v->efuse.reg)
+               return v->value;
+
+       switch (v->efuse.reg_bits) {
+       case 16:
+               val = readw(v->efuse.reg);
+               break;
+       case 32:
+               val = readl(v->efuse.reg);
+               break;
+       default:
+               printf("Error: efuse 0x%08x bits=%d unknown\n",
+                      v->efuse.reg, v->efuse.reg_bits);
+               return v->value;
+       }
+
+       if (!val) {
+               printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
+                      v->efuse.reg, v->efuse.reg_bits, v->value);
+               return v->value;
+       }
+
+       debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
+             __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
+       return val;
+}
+
 /*
  * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
  * We set the maximum voltages allowed here because Smart-Reflex is not
@@ -525,16 +559,34 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
  */
 void scale_vcores(struct vcores_data const *vcores)
 {
-       omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+       u32 val;
+
+       val = optimize_vcore_voltage(&vcores->core);
+       do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
+
+       val = optimize_vcore_voltage(&vcores->mpu);
+       do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
+
+       /* Configure MPU ABB LDO after scale */
+       abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+                 (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
+                 (*prcm)->prm_abbldo_mpu_setup,
+                 (*prcm)->prm_abbldo_mpu_ctrl,
+                 (*prcm)->prm_irqstatus_mpu_2,
+                 OMAP_ABB_MPU_TXDONE_MASK,
+                 OMAP_ABB_FAST_OPP);
 
-       do_scale_vcore(vcores->core.addr, vcores->core.value,
-                                         vcores->core.pmic);
+       val = optimize_vcore_voltage(&vcores->mm);
+       do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
 
-       do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
-                                         vcores->mpu.pmic);
+       val = optimize_vcore_voltage(&vcores->gpu);
+       do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
 
-       do_scale_vcore(vcores->mm.addr, vcores->mm.value,
-                                         vcores->mm.pmic);
+       val = optimize_vcore_voltage(&vcores->eve);
+       do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
+
+       val = optimize_vcore_voltage(&vcores->iva);
+       do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
 
         if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
                /* Configure LDO SRAM "magic" bits */
@@ -710,6 +762,7 @@ void prcm_init(void)
        case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
        case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
                enable_basic_clocks();
+               timer_init();
                scale_vcores(*omap_vcores);
                setup_dplls();
 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
@@ -725,3 +778,13 @@ void prcm_init(void)
        if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
                enable_basic_uboot_clocks();
 }
+
+void gpi2c_init(void)
+{
+       static int gpi2c = 1;
+
+       if (gpi2c) {
+               i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+               gpi2c = 0;
+       }
+}
index 11e830a..652e5a7 100644 (file)
@@ -27,7 +27,7 @@
 
 #include <common.h>
 #include <asm/emif.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/utils.h>
@@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
        writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-       if (omap_revision() >= OMAP5430_ES1_0) {
+       if ((omap_revision() >= OMAP5430_ES1_0) ||
+                               (omap_revision() == DRA752_ES1_0)) {
                writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
                        &emif->emif_l3_config);
        } else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
        __udelay(130);
 }
 
+static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+       config_data_eye_leveling_samples(base);
+
+       writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+       writel(regs->sdram_config, &emif->emif_sdram_config);
+}
+
 static void ddr3_init(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
         * defined, contents of mode Registers must be fully initialized.
         * H/W takes care of this initialization
         */
+       writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
        writel(regs->sdram_config_init, &emif->emif_sdram_config);
 
        writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
@@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
        /* enable leveling */
        writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 
-       ddr3_leveling(base, regs);
+       if (omap_revision() == DRA752_ES1_0)
+               ddr3_sw_leveling(base, regs);
+       else
+               ddr3_leveling(base, regs);
 }
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base)
        if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
                set_lpmode_selfrefresh(base);
                emif_reset_phy(base);
-               ddr3_leveling(base, regs);
+               if (omap_revision() == DRA752_ES1_0)
+                       ddr3_sw_leveling(base, regs);
+               else
+                       ddr3_leveling(base, regs);
        }
 
        /* Write to the shadow registers */
index 1645120..5df116e 100644 (file)
@@ -84,7 +84,7 @@ u32 cortex_rev(void)
        return rev;
 }
 
-void omap_rev_string(void)
+static void omap_rev_string(void)
 {
        u32 omap_rev = omap_revision();
        u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
@@ -111,42 +111,6 @@ void __weak srcomp_enable(void)
 {
 }
 
-static void save_omap_boot_params(void)
-{
-       u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
-       u8 boot_device;
-       u32 dev_desc, dev_data;
-
-       if ((rom_params <  NON_SECURE_SRAM_START) ||
-           (rom_params > NON_SECURE_SRAM_END))
-               return;
-
-       /*
-        * rom_params can be type casted to omap_boot_parameters and
-        * used. But it not correct to assume that romcode structure
-        * encoding would be same as u-boot. So use the defined offsets.
-        */
-       gd->arch.omap_boot_params.omap_bootdevice = boot_device =
-                                  *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
-
-       gd->arch.omap_boot_params.ch_flags =
-                               *((u8 *)(rom_params + CH_FLAGS_OFFSET));
-
-       if ((boot_device >= MMC_BOOT_DEVICES_START) &&
-           (boot_device <= MMC_BOOT_DEVICES_END)) {
-               if ((omap_hw_init_context() ==
-                                     OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
-                       gd->arch.omap_boot_params.omap_bootmode =
-                       *((u8 *)(rom_params + BOOT_MODE_OFFSET));
-               } else {
-                       dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
-                       dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
-                       gd->arch.omap_boot_params.omap_bootmode =
-                                       *((u32 *)(dev_data + BOOT_MODE_OFFSET));
-               }
-       }
-}
-
 #ifdef CONFIG_ARCH_CPU_INIT
 /*
  * SOC specific cpu init
@@ -202,8 +166,6 @@ void s_init(void)
 #endif
        prcm_init();
 #ifdef CONFIG_SPL_BUILD
-       timer_init();
-
        /* For regular u-boot sdram_init() is called from dram_init() */
        sdram_init();
 #endif
index 507f687..5926a5a 100644 (file)
@@ -35,6 +35,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
index e6e5f78..a68f1d1 100644 (file)
@@ -17,6 +17,7 @@
 #include <common.h>
 #include <asm/omap_common.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
 
 /*
  * Define Master code if there are multiple masters on the I2C_SR bus.
@@ -57,7 +58,7 @@
  * omap_vc_init() - Initialization for Voltage controller
  * @speed_khz: I2C buspeed in KHz
  */
-void omap_vc_init(u16 speed_khz)
+static void omap_vc_init(u16 speed_khz)
 {
        u32 val;
        u32 sys_clk_khz, cycles_hi, cycles_low;
@@ -137,3 +138,14 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
        /* All good.. */
        return 0;
 }
+
+void sri2c_init(void)
+{
+       static int sri2c = 1;
+
+       if (sri2c) {
+               omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+               sri2c = 0;
+       }
+       return;
+}
index 09c51f6..81cc859 100644 (file)
@@ -27,7 +27,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/clocks_omap3.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
index 06a2fc8..b97cad4 100644 (file)
@@ -29,7 +29,7 @@
 #include <asm/arch/omap.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/omap_gpio.h>
 #include <asm/io.h>
 
@@ -219,6 +219,9 @@ struct pmic_data twl6030_4430es1 = {
        .step = 12660, /* 12.66 mV represented in uV */
        /* The code starts at 1 not 0 */
        .start_code = 1,
+       .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+       .pmic_bus_init  = sri2c_init,
+       .pmic_write     = omap_vc_bypass_send_value,
 };
 
 struct pmic_data twl6030 = {
@@ -226,6 +229,9 @@ struct pmic_data twl6030 = {
        .step = 12660, /* 12.66 mV represented in uV */
        /* The code starts at 1 not 0 */
        .start_code = 1,
+       .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+       .pmic_bus_init  = sri2c_init,
+       .pmic_write     = omap_vc_bypass_send_value,
 };
 
 struct pmic_data tps62361 = {
@@ -233,7 +239,10 @@ struct pmic_data tps62361 = {
        .step = 10000, /* 10 mV represented in uV */
        .start_code = 0,
        .gpio = TPS62361_VSEL0_GPIO,
-       .gpio_en = 1
+       .gpio_en = 1,
+       .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+       .pmic_bus_init  = sri2c_init,
+       .pmic_write     = omap_vc_bypass_send_value,
 };
 
 struct vcores_data omap4430_volts_es1 = {
index 7225a30..7e71ca0 100644 (file)
@@ -301,6 +301,8 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
        .control_ldosram_iva_voltage_ctrl       = 0x4A002320,
        .control_ldosram_mpu_voltage_ctrl       = 0x4A002324,
        .control_ldosram_core_voltage_ctrl      = 0x4A002328,
+       .control_usbotghs_ctrl                  = 0x4A00233C,
+       .control_padconf_core_base              = 0x4A100000,
        .control_pbiaslite                      = 0x4A100600,
        .control_lpddr2io1_0                    = 0x4A100638,
        .control_lpddr2io1_1                    = 0x4A10063C,
@@ -312,4 +314,5 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
        .control_lpddr2io2_3                    = 0x4A100654,
        .control_efuse_1                        = 0x4A100700,
        .control_efuse_2                        = 0x4A100704,
+       .control_padconf_wkup_base              = 0x4A31E000,
 };
index ce00e2c..6ff8dbb 100644 (file)
@@ -30,6 +30,7 @@ COBJS += emif.o
 COBJS  += sdram.o
 COBJS  += prcm-regs.o
 COBJS  += hw_data.o
+COBJS  += abb.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c
new file mode 100644 (file)
index 0000000..92470be
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ *
+ * Adaptive Body Bias programming sequence for OMAP5 family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+
+/*
+ * Setup LDOVBB for OMAP5.
+ * On OMAP5+ some ABB settings are fused. They are handled
+ * in the following way:
+ *
+ * 1. corresponding EFUSE register contains ABB enable bit
+ *    and VSET value
+ * 2. If ABB enable bit is set to 1, than ABB should be
+ *    enabled, otherwise ABB should be disabled
+ * 3. If ABB is enabled, than VSET value should be copied
+ *    to corresponding MUX control register
+ */
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+       u32 vset;
+
+       /*
+        * ABB parameters must be properly fused
+        * otherwise ABB should be disabled
+        */
+       vset = readl(fuse);
+       if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK))
+               return -1;
+
+       /* prepare VSET value for LDOVBB mux register */
+       vset &= OMAP5_ABB_FUSE_VSET_MASK;
+       vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1;
+       vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
+       vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
+
+       /* setup LDOVBB using fused value */
+       clrsetbits_le32(ldovbb,  OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
+
+       return 0;
+}
index 604fa42..56cf1f8 100644 (file)
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <palmas.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/omap_gpio.h>
 #include <asm/io.h>
 #include <asm/emif.h>
@@ -99,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
-       {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
-       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-       {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
-       {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
-       {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
+       {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
+       {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
+       {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
+       {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
+       {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-       {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
-       {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 20 MHz   */
+       {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 38.4 MHz */
 };
 
 static const struct dpll_params
@@ -132,15 +132,14 @@ static const struct dpll_params
 };
 
 static const struct dpll_params
-               core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
-       {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 12 MHz   */
-       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-       {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 16.8 MHz */
-       {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 19.2 MHz */
-       {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 26 MHz   */
+               core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+       {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 12 MHz   */
+       {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 20 MHz   */
+       {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 16.8 MHz */
+       {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 19.2 MHz */
+       {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 26 MHz   */
        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-       {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 38.4 MHz */
-       {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}              /* 20 MHz   */
+       {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 38.4 MHz */
 };
 
 static const struct dpll_params
@@ -186,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
-       {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 12 MHz   */
-       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-       {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 16.8 MHz */
-       {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 19.2 MHz */
-       {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},          /* 26 MHz   */
+       {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
+       {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
+       {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
+       {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
+       {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */
        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-       {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 38.4 MHz */
-       {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}             /* 20 MHz   */
+       {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 38.4 MHz */
 };
 
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@@ -206,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
        {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}           /* 38.4 MHz */
 };
 
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
+       {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
+       {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz */
+       {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
+       {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
+       {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
+       {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 38.4 MHz */
+};
+
 /* ABE M & N values with sys_clk as source */
 static const struct dpll_params
                abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
@@ -223,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = {
        750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 };
 
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */
+static const struct dpll_params
+               abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
+       {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
+};
+
 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
        {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
-       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
+       {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 20 MHz   */
        {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
        {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
        {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
        {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
-       {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 20 MHz   */
 };
 
-static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
-       {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
-       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-       {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
-       {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
-       {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},           /* 26 MHz   */
+static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
+       {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
+       {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
+       {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
+       {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
+       {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-       {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
-       {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}          /* 20 MHz   */
+       {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 };
 
 struct dplls omap5_dplls_es1 = {
@@ -275,10 +293,12 @@ struct dplls omap5_dplls_es2 = {
 
 struct dplls dra7xx_dplls = {
        .mpu = mpu_dpll_params_1ghz,
-       .core = core_dpll_params_2128mhz_ddr532_dra7xx,
+       .core = core_dpll_params_2128mhz_dra7xx,
        .per = per_dpll_params_768mhz_dra7xx,
+       .abe = abe_dpll_params_sysclk2_361267khz,
+       .iva = iva_dpll_params_2330mhz_dra7xx,
        .usb = usb_dpll_params_1920mhz,
-       .ddr = ddr_dpll_params_1066mhz,
+       .ddr = ddr_dpll_params_2128mhz,
 };
 
 struct pmic_data palmas = {
@@ -289,6 +309,22 @@ struct pmic_data palmas = {
         * Offset code 0 switches OFF the SMPS
         */
        .start_code = 6,
+       .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+       .pmic_bus_init  = sri2c_init,
+       .pmic_write     = omap_vc_bypass_send_value,
+};
+
+struct pmic_data tps659038 = {
+       .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+       .step = 10000, /* 10 mV represented in uV */
+       /*
+        * Offset codes 1-6 all give the base voltage in Palmas
+        * Offset code 0 switches OFF the SMPS
+        */
+       .start_code = 6,
+       .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
+       .pmic_bus_init  = gpi2c_init,
+       .pmic_write     = palmas_i2c_write_u8,
 };
 
 struct vcores_data omap5430_volts = {
@@ -319,6 +355,38 @@ struct vcores_data omap5430_volts_es2 = {
        .mm.pmic = &palmas,
 };
 
+struct vcores_data dra752_volts = {
+       .mpu.value      = VDD_MPU_DRA752,
+       .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
+       .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .mpu.addr       = TPS659038_REG_ADDR_SMPS12_MPU,
+       .mpu.pmic       = &tps659038,
+
+       .eve.value      = VDD_EVE_DRA752,
+       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+       .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .eve.addr       = TPS659038_REG_ADDR_SMPS45_EVE,
+       .eve.pmic       = &tps659038,
+
+       .gpu.value      = VDD_GPU_DRA752,
+       .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
+       .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .gpu.addr       = TPS659038_REG_ADDR_SMPS6_GPU,
+       .gpu.pmic       = &tps659038,
+
+       .core.value     = VDD_CORE_DRA752,
+       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .core.addr      = TPS659038_REG_ADDR_SMPS7_CORE,
+       .core.pmic      = &tps659038,
+
+       .iva.value      = VDD_IVA_DRA752,
+       .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
+       .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .iva.addr       = TPS659038_REG_ADDR_SMPS8_IVA,
+       .iva.pmic       = &tps659038,
+};
+
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
@@ -383,12 +451,6 @@ void enable_basic_clocks(void)
                         clk_modules_explicit_en_essential,
                         1);
 
-       /* Select 384Mhz for GPU as its the POR for ES1.0 */
-       setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
-                       CLKSEL_GPU_HYD_GCLK_MASK);
-       setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
-                       CLKSEL_GPU_CORE_GCLK_MASK);
-
        /* Enable SCRM OPT clocks for PER and CORE dpll */
        setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
                        OPTFCLKEN_SCRM_PER_MASK);
@@ -540,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
        .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 };
 
+const struct ctrl_ioregs ioregs_dra7xx_es1 = {
+       .ctrl_ddrch = 0x40404040,
+       .ctrl_lpddr2ch = 0x40404040,
+       .ctrl_ddr3ch = 0x80808080,
+       .ctrl_ddrio_0 = 0xbae8c631,
+       .ctrl_ddrio_1 = 0xb46318d8,
+       .ctrl_ddrio_2 = 0x84210000,
+       .ctrl_emif_sdram_config_ext = 0xb2c00000,
+       .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
 void hw_data_init(void)
 {
        u32 omap_rev = omap_revision();
@@ -565,7 +638,7 @@ void hw_data_init(void)
        case DRA752_ES1_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra7xx_dplls;
-       *omap_vcores = &omap5430_volts_es2;
+       *omap_vcores = &dra752_volts;
        *ctrl = &dra7xx_ctrl;
        break;
 
@@ -582,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs)
        case OMAP5430_ES1_0:
        case OMAP5430_ES2_0:
                *regs = &ioregs_omap5430;
-       break;
+               break;
        case OMAP5432_ES1_0:
                *regs = &ioregs_omap5432_es1;
-       break;
+               break;
        case OMAP5432_ES2_0:
-       case DRA752_ES1_0:
                *regs = &ioregs_omap5432_es2;
-       break;
+               break;
+       case DRA752_ES1_0:
+               *regs = &ioregs_dra7xx_es1;
+               break;
 
        default:
                printf("\n INVALID OMAP REVISION ");
index e192fea..daf124e 100644 (file)
@@ -32,7 +32,7 @@
 #include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/sizes.h>
 #include <asm/utils.h>
 #include <asm/arch/gpio.h>
@@ -100,16 +100,21 @@ static void io_settings_ddr3(void)
        writel(ioregs->ctrl_emif_sdram_config_ext,
               (*ctrl)->control_emif2_sdram_config_ext);
 
-       /* Disable DLL select */
-       io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
+       if (is_omap54xx()) {
+               /* Disable DLL select */
+               io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
                                                        & 0xFFEFFFFF);
-       writel(io_settings,
-               (*ctrl)->control_port_emif1_sdram_config);
+               writel(io_settings,
+                       (*ctrl)->control_port_emif1_sdram_config);
 
-       io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
+               io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
                                                        & 0xFFEFFFFF);
-       writel(io_settings,
-               (*ctrl)->control_port_emif2_sdram_config);
+               writel(io_settings,
+                       (*ctrl)->control_port_emif2_sdram_config);
+       } else {
+               writel(ioregs->ctrl_ddr_ctrl_ext_0,
+                               (*ctrl)->control_ddr_control_ext_0);
+       }
 }
 
 /*
@@ -201,6 +206,9 @@ void srcomp_enable(void)
        u32 sysclk_ind  = get_sys_clk_index();
        u32 omap_rev    = omap_revision();
 
+       if (!is_omap54xx())
+               return;
+
        mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
        div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 
index e9f6a32..e839ff5 100644 (file)
@@ -298,6 +298,7 @@ struct prcm_regs const omap5_es1_prcm = {
        .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
        .prm_rstctrl = 0x4ae07b00,
        .prm_rstst = 0x4ae07b04,
+       .prm_rsttime = 0x4ae07b08,
        .prm_vc_val_bypass = 0x4ae07ba0,
        .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
        .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
@@ -307,10 +308,16 @@ struct prcm_regs const omap5_es1_prcm = {
        .prm_sldo_mpu_ctrl = 0x4ae07bd0,
        .prm_sldo_mm_setup = 0x4ae07bd4,
        .prm_sldo_mm_ctrl = 0x4ae07bd8,
+
+       /* SCRM stuff, used by some boards */
+       .scrm_auxclk0 = 0x4ae0a310,
+       .scrm_auxclk1 = 0x4ae0a314,
 };
 
 struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_status                         = 0x4A002134,
+       .control_std_fuse_opp_vdd_mpu_2         = 0x4A0021B4,
+       .control_padconf_core_base              = 0x4A002800,
        .control_paconf_global                  = 0x4A002DA0,
        .control_paconf_mode                    = 0x4A002DA4,
        .control_smart1io_padconf_0             = 0x4A002DA8,
@@ -358,6 +365,8 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_port_emif2_sdram_config        = 0x4AE0C118,
        .control_emif1_sdram_config_ext         = 0x4AE0C144,
        .control_emif2_sdram_config_ext         = 0x4AE0C148,
+       .control_wkup_ldovbb_mpu_voltage_ctrl   = 0x4AE0C318,
+       .control_padconf_wkup_base              = 0x4AE0C800,
        .control_smart1nopmio_padconf_0         = 0x4AE0CDA0,
        .control_smart1nopmio_padconf_1         = 0x4AE0CDA4,
        .control_padconf_mode                   = 0x4AE0CDA8,
@@ -434,6 +443,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_srcomp_east_side               = 0x4A002E7C,
        .control_srcomp_west_side               = 0x4A002E80,
        .control_srcomp_code_latch              = 0x4A002E84,
+       .control_ddr_control_ext_0              = 0x4A002E88,
        .control_padconf_core_base              = 0x4A003400,
        .control_port_emif1_sdram_config        = 0x4AE0C110,
        .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
@@ -709,6 +719,9 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
        .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
 
+       /* prm irqstatus regs */
+       .prm_irqstatus_mpu_2 = 0x4ae06014,
+
        /* l4 wkup regs */
        .cm_abe_pll_ref_clksel = 0x4ae0610c,
        .cm_sys_clksel = 0x4ae06110,
@@ -740,6 +753,12 @@ struct prcm_regs const omap5_es2_prcm = {
        .prm_sldo_mpu_ctrl = 0x4ae07cd0,
        .prm_sldo_mm_setup = 0x4ae07cd4,
        .prm_sldo_mm_ctrl = 0x4ae07cd8,
+       .prm_abbldo_mpu_setup = 0x4ae07cdc,
+       .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+
+       /* SCRM stuff, used by some boards */
+       .scrm_auxclk0 = 0x4ae0a310,
+       .scrm_auxclk1 = 0x4ae0a314,
 };
 
 struct prcm_regs const dra7xx_prcm = {
@@ -941,6 +960,7 @@ struct prcm_regs const dra7xx_prcm = {
        /* l4 wkup regs */
        .cm_abe_pll_ref_clksel                  = 0x4ae0610c,
        .cm_sys_clksel                          = 0x4ae06110,
+       .cm_abe_pll_sys_clksel                  = 0x4ae06118,
        .cm_wkup_clkstctrl                      = 0x4ae07800,
        .cm_wkup_l4wkup_clkctrl                 = 0x4ae07820,
        .cm_wkup_wdtimer1_clkctrl               = 0x4ae07828,
index 6b461e4..1b445a6 100644 (file)
@@ -108,6 +108,7 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
        .sdram_config_init              = 0x61851B32,
        .sdram_config                   = 0x61851B32,
+       .sdram_config2                  = 0x0,
        .ref_ctrl                       = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
@@ -131,6 +132,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
        .sdram_config_init              = 0x61851B32,
        .sdram_config                   = 0x61851B32,
+       .sdram_config2                  = 0x0,
        .ref_ctrl                       = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
@@ -151,6 +153,54 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
        .emif_rd_wr_exec_thresh         = 0x40000305
 };
 
+const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
+       .sdram_config_init              = 0x61851ab2,
+       .sdram_config                   = 0x61851ab2,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x00001035,
+       .sdram_tim1                     = 0xCCCF36B3,
+       .sdram_tim2                     = 0x308F7FDA,
+       .sdram_tim3                     = 0x027F88A8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x0007190B,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E20400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x009E009E,
+       .emif_ddr_ext_phy_ctrl_3        = 0x009E009E,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009E009E,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
+       .sdram_config_init              = 0x61851B32,
+       .sdram_config                   = 0x61851B32,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x00001035,
+       .sdram_tim1                     = 0xCCCF36B3,
+       .sdram_tim2                     = 0x308F7FDA,
+       .sdram_tim3                     = 0x027F88A8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x0007190B,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0020400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x009D009D,
+       .emif_ddr_ext_phy_ctrl_3        = 0x009D009D,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009D009D,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009D009D,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
+};
+
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
        .dmm_lisa_map_0 = 0x0,
        .dmm_lisa_map_1 = 0x0,
@@ -159,11 +209,39 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
        .is_ma_present  = 0x1
 };
 
-const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
+/*
+ * DRA752 EVM board has 1.5 GB of memory
+ * EMIF1 --> 2Gb * 2 =  512MB
+ * EMIF2 --> 2Gb * 4 =  1GB
+ * so mapping 1GB interleaved and 512MB non-interleaved
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
+       .dmm_lisa_map_0 = 0x0,
+       .dmm_lisa_map_1 = 0x80640300,
+       .dmm_lisa_map_2 = 0xC0500220,
+       .dmm_lisa_map_3 = 0xFF020100,
+       .is_ma_present  = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF1 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
        .dmm_lisa_map_0 = 0x0,
        .dmm_lisa_map_1 = 0x0,
-       .dmm_lisa_map_2 = 0x0,
-       .dmm_lisa_map_3 = 0x80500100,
+       .dmm_lisa_map_2 = 0x80500100,
+       .dmm_lisa_map_3 = 0xFF020100,
+       .is_ma_present  = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF2 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+       .dmm_lisa_map_0 = 0x0,
+       .dmm_lisa_map_1 = 0x0,
+       .dmm_lisa_map_2 = 0x80600200,
+       .dmm_lisa_map_3 = 0xFF020100,
        .is_ma_present  = 0x1
 };
 
@@ -180,9 +258,20 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                *regs = &emif_regs_532_mhz_2cs_es2;
                break;
        case OMAP5432_ES2_0:
+               *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+               break;
        case DRA752_ES1_0:
+               switch (emif_nr) {
+               case 1:
+                       *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
+                       break;
+               case 2:
+                       *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
+                       break;
+               }
+               break;
        default:
-               *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+               *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }
 }
 
@@ -201,7 +290,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
                break;
        case DRA752_ES1_0:
        default:
-               *dmm_lisa_regs = &lisa_map_512M_x_1;
+               *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
        }
 
 }
@@ -252,7 +341,8 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
        0x00000000,
        0x00000000,
        0x00000000,
-       0x00000077
+       0x00000077,
+       0x0
 };
 
 const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@@ -274,7 +364,8 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
        0x00000000,
        0x00000000,
        0x00000000,
-       0x00000057
+       0x00000057,
+       0x0
 };
 
 const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@@ -296,7 +387,56 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
        0x00000000,
        0x00000000,
        0x00000000,
-       0x00000057
+       0x00000057,
+       0x0
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+       0x009E009E,
+       0x002E002E,
+       0x002E002E,
+       0x002E002E,
+       0x002E002E,
+       0x002E002E,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x004D004D,
+       0x0,
+       0x600020,
+       0x40010080,
+       0x8102040
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+       0x009D009D,
+       0x002D002D,
+       0x002D002D,
+       0x002D002D,
+       0x002D002D,
+       0x002D002D,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x00570057,
+       0x0,
+       0x600020,
+       0x40010080,
+       0x8102040
 };
 
 const struct lpddr2_mr_regs mr_regs = {
@@ -307,7 +447,7 @@ const struct lpddr2_mr_regs mr_regs = {
        .mr16   = MR16_REF_FULL_ARRAY
 };
 
-static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
 {
        switch (omap_revision()) {
        case OMAP5430_ES1_0:
@@ -318,7 +458,14 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
                *regs = ddr3_ext_phy_ctrl_const_base_es1;
                break;
        case OMAP5432_ES2_0:
+               *regs = ddr3_ext_phy_ctrl_const_base_es2;
+               break;
        case DRA752_ES1_0:
+               if (emif_nr == 1)
+                       *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
+               else
+                       *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+               break;
        default:
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
 
@@ -334,9 +481,12 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 {
        u32 *ext_phy_ctrl_base = 0;
        u32 *emif_ext_phy_ctrl_base = 0;
+       u32 emif_nr;
        const u32 *ext_phy_ctrl_const_regs;
        u32 i = 0;
 
+       emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
        ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
@@ -353,7 +503,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
         * external phy 6-24 registers do not change with
         * ddr frequency
         */
-       emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
+       emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
        for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
                writel(ext_phy_ctrl_const_regs[i],
                       emif_ext_phy_ctrl_base++);
index e9e57e6..8e9cb19 100644 (file)
@@ -94,10 +94,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -167,80 +163,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-#ifndef CONFIG_SPL_BUILD
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-ENTRY(relocate_code)
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-
-relocate_done:
-
-       bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-ENDPROC(relocate_code)
-
-#endif
-
 ENTRY(c_runtime_cpu_setup)
 /*
  * If I-cache is enabled invalidate it
diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile
new file mode 100644 (file)
index 0000000..9232cd4
--- /dev/null
@@ -0,0 +1,42 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(SOC).o
+
+COBJS  += generic.o
+COBJS  += timer.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
new file mode 100644 (file)
index 0000000..87f2a86
--- /dev/null
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <netdev.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+       struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+       u32 reg;
+
+       reg = readl(&ccm->ccgr6);
+       if (enable)
+               reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
+       else
+               reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
+       writel(reg, &ccm->ccgr6);
+}
+#endif
+
+static u32 get_mcu_main_clk(void)
+{
+       struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+       u32 ccm_ccsr, ccm_cacrr, armclk_div;
+       u32 sysclk_sel, pll_pfd_sel = 0;
+       u32 freq = 0;
+
+       ccm_ccsr = readl(&ccm->ccsr);
+       sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
+       sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
+
+       ccm_cacrr = readl(&ccm->cacrr);
+       armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
+       armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
+       armclk_div += 1;
+
+       switch (sysclk_sel) {
+       case 0:
+               freq = FASE_CLK_FREQ;
+               break;
+       case 1:
+               freq = SLOW_CLK_FREQ;
+               break;
+       case 2:
+               pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
+               pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
+               if (pll_pfd_sel == 0)
+                       freq = PLL2_MAIN_FREQ;
+               else if (pll_pfd_sel == 1)
+                       freq = PLL2_PFD1_FREQ;
+               else if (pll_pfd_sel == 2)
+                       freq = PLL2_PFD2_FREQ;
+               else if (pll_pfd_sel == 3)
+                       freq = PLL2_PFD3_FREQ;
+               else if (pll_pfd_sel == 4)
+                       freq = PLL2_PFD4_FREQ;
+               break;
+       case 3:
+               freq = PLL2_MAIN_FREQ;
+               break;
+       case 4:
+               pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
+               pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
+               if (pll_pfd_sel == 0)
+                       freq = PLL1_MAIN_FREQ;
+               else if (pll_pfd_sel == 1)
+                       freq = PLL1_PFD1_FREQ;
+               else if (pll_pfd_sel == 2)
+                       freq = PLL1_PFD2_FREQ;
+               else if (pll_pfd_sel == 3)
+                       freq = PLL1_PFD3_FREQ;
+               else if (pll_pfd_sel == 4)
+                       freq = PLL1_PFD4_FREQ;
+               break;
+       case 5:
+               freq = PLL3_MAIN_FREQ;
+               break;
+       default:
+               printf("unsupported system clock select\n");
+       }
+
+       return freq / armclk_div;
+}
+
+static u32 get_bus_clk(void)
+{
+       struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+       u32 ccm_cacrr, busclk_div;
+
+       ccm_cacrr = readl(&ccm->cacrr);
+
+       busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
+       busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
+       busclk_div += 1;
+
+       return get_mcu_main_clk() / busclk_div;
+}
+
+static u32 get_ipg_clk(void)
+{
+       struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+       u32 ccm_cacrr, ipgclk_div;
+
+       ccm_cacrr = readl(&ccm->cacrr);
+
+       ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
+       ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
+       ipgclk_div += 1;
+
+       return get_bus_clk() / ipgclk_div;
+}
+
+static u32 get_uart_clk(void)
+{
+       return get_ipg_clk();
+}
+
+static u32 get_sdhc_clk(void)
+{
+       struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+       u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
+       u32 freq = 0;
+
+       ccm_cscmr1 = readl(&ccm->cscmr1);
+       sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
+       sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+
+       ccm_cscdr2 = readl(&ccm->cscdr2);
+       sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
+       sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
+       sdhc_clk_div += 1;
+
+       switch (sdhc_clk_sel) {
+       case 0:
+               freq = PLL3_MAIN_FREQ;
+               break;
+       case 1:
+               freq = PLL3_PFD3_FREQ;
+               break;
+       case 2:
+               freq = PLL1_PFD3_FREQ;
+               break;
+       case 3:
+               freq = get_bus_clk();
+               break;
+       }
+
+       return freq / sdhc_clk_div;
+}
+
+u32 get_fec_clk(void)
+{
+       struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+       u32 ccm_cscmr2, rmii_clk_sel;
+       u32 freq = 0;
+
+       ccm_cscmr2 = readl(&ccm->cscmr2);
+       rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
+       rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
+
+       switch (rmii_clk_sel) {
+       case 0:
+               freq = ENET_EXTERNAL_CLK;
+               break;
+       case 1:
+               freq = AUDIO_EXTERNAL_CLK;
+               break;
+       case 2:
+               freq = PLL5_MAIN_FREQ;
+               break;
+       case 3:
+               freq = PLL5_MAIN_FREQ / 2;
+               break;
+       }
+
+       return freq;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+       switch (clk) {
+       case MXC_ARM_CLK:
+               return get_mcu_main_clk();
+       case MXC_BUS_CLK:
+               return get_bus_clk();
+       case MXC_IPG_CLK:
+               return get_ipg_clk();
+       case MXC_UART_CLK:
+               return get_uart_clk();
+       case MXC_ESDHC_CLK:
+               return get_sdhc_clk();
+       case MXC_FEC_CLK:
+               return get_fec_clk();
+       default:
+               break;
+       }
+       return -1;
+}
+
+/* Dump some core clocks */
+int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+                        char * const argv[])
+{
+       printf("\n");
+       printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
+       printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
+
+       return 0;
+}
+
+U_BOOT_CMD(
+       clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
+       "display clocks",
+       ""
+);
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       struct fuse_bank *bank = &ocotp->bank[4];
+       struct fuse_bank4_regs *fuse =
+               (struct fuse_bank4_regs *)bank->fuse_regs;
+
+       u32 value = readl(&fuse->mac_addr0);
+       mac[0] = (value >> 8);
+       mac[1] = value;
+
+       value = readl(&fuse->mac_addr1);
+       mac[2] = value >> 24;
+       mac[3] = value >> 16;
+       mac[4] = value >> 8;
+       mac[5] = value;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+       u32 cause;
+       struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+       cause = readl(&src_regs->srsr);
+       writel(cause, &src_regs->srsr);
+       cause &= 0xff;
+
+       switch (cause) {
+       case 0x08:
+               return "WDOG";
+       case 0x20:
+               return "JTAG HIGH-Z";
+       case 0x80:
+               return "EXTERNAL RESET";
+       case 0xfd:
+               return "POR";
+       default:
+               return "unknown reset";
+       }
+}
+
+int print_cpuinfo(void)
+{
+       printf("CPU:   Freescale Vybrid VF610 at %d MHz\n",
+               mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("Reset cause: %s\n", get_reset_cause());
+
+       return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+       int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+       rc = fecmxc_initialize(bis);
+#endif
+
+       return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+       return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c
new file mode 100644 (file)
index 0000000..f8fbed7
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+static struct pit_reg *cur_pit = (struct pit_reg *)PIT_BASE_ADDR;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+       tick *= CONFIG_SYS_HZ;
+       do_div(tick, mxc_get_clock(MXC_IPG_CLK));
+
+       return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+       usec = usec * mxc_get_clock(MXC_IPG_CLK)  + 999999;
+       do_div(usec, 1000000);
+
+       return usec;
+}
+
+int timer_init(void)
+{
+       __raw_writel(0, &cur_pit->mcr);
+
+       __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1);
+       __raw_writel(0, &cur_pit->tctrl1);
+       __raw_writel(1, &cur_pit->tctrl1);
+
+       gd->arch.tbl = 0;
+       gd->arch.tbu = 0;
+
+       return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+       ulong now = TIMER_LOAD_VAL - __raw_readl(&cur_pit->cval1);
+
+       /* increment tbu if tbl has rolled over */
+       if (now < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl = now;
+
+       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+       return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+       return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+       unsigned long long start;
+       ulong tmo;
+
+       start = get_ticks();                    /* get current timestamp */
+       tmo = us_to_tick(usec);                 /* convert usecs to ticks */
+       while ((get_ticks() - start) < tmo)
+               ;                               /* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return mxc_get_clock(MXC_IPG_CLK);
+}
index b02e8af..fd3c29f 100644 (file)
@@ -31,10 +31,6 @@ PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
 PLATFORM_LDFLAGS += -EB
 USE_PRIVATE_LIBGCC = yes
 
-# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
-PLATFORM_RELFLAGS += -ffunction-sections
-LDFLAGS_u-boot += --gc-sections
-
 # =========================================================================
 #
 # Supply options according to compiler version
index 69ef8aa..46cba0c 100644 (file)
@@ -114,10 +114,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -257,79 +253,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 0c18610..f07dc67 100644 (file)
@@ -244,7 +244,7 @@ void pxa_clock_setup(void)
 {
        writel(CONFIG_SYS_CKEN, CKEN);
        writel(CONFIG_SYS_CCCR, CCCR);
-       asm volatile("mcr       p14, 0, %0, c6, c0, 0" : : "r"(2));
+       asm volatile("mcr       p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
 
        /* enable the 32Khz oscillator for RTC and PowerManager */
        writel(OSCC_OON, OSCC);
index ada91a6..2e3f65e 100644 (file)
@@ -118,10 +118,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -171,94 +167,24 @@ reset:
        bl      _main
 
 /*------------------------------------------------------------------------------*/
-#ifndef CONFIG_SPL_BUILD
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-/* Disable the Dcache RAM lock for stack now */
-#ifdef CONFIG_CPU_PXA25X
-       mov     r12, lr
-       bl      cpu_init_crit
-       mov     lr, r12
-#endif
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
 
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
 
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_CPU_PXA25X
        /*
-        * fix .rel.dyn relocations
+        * Unlock (actually, disable) the cache now that board_init_f
+        * is done. We could do this earlier but we would need to add
+        * a new C runtime hook, whereas c_runtime_cpu_setup already
+        * exists.
+        * As this routine is just a call to cpu_init_crit, let us
+        * tail-optimize and do a simple branch here.
         */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
+       b       cpu_init_crit
+#else
        bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
 #endif
 
-       .globl  c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-       bx      lr
-
 /*
  *************************************************************************
  *
index 7361aa2..78183fc 100644 (file)
@@ -80,10 +80,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -140,79 +136,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 8a2eafd..30d5a90 100644 (file)
@@ -90,10 +90,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -144,79 +140,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 9b77b2b..9e6d51d 100644 (file)
@@ -72,6 +72,7 @@ int tegra_get_chip_sku(void)
        switch (chip_id) {
        case CHIPID_TEGRA20:
                switch (sku_id) {
+               case SKU_ID_T20_7:
                case SKU_ID_T20:
                        return TEGRA_SOC_T20;
                case SKU_ID_T25SE:
@@ -92,6 +93,7 @@ int tegra_get_chip_sku(void)
        case CHIPID_TEGRA114:
                switch (sku_id) {
                case SKU_ID_T114_ENG:
+               case SKU_ID_T114_1:
                        return TEGRA_SOC_T114;
                }
                break;
@@ -107,6 +109,10 @@ static void enable_scu(void)
        struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
        u32 reg;
 
+       /* Only enable the SCU on T20/T25 */
+       if (tegra_get_chip() != CHIPID_TEGRA20)
+               return;
+
        /* If SCU already setup/enabled, return */
        if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
                return;
index 9156d00..268fb91 100644 (file)
@@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
        unsigned effective_rate;
        int mux_bits, divider_bits, source;
        int divider;
+       int xdiv = 0;
 
        /* work out the source clock and set it */
        source = get_periph_clock_source(periph_id, parent, &mux_bits,
                                         &divider_bits);
 
+       divider = find_best_divider(divider_bits, pll_rate[parent],
+                                   rate, &xdiv);
        if (extra_div)
-               divider = find_best_divider(divider_bits, pll_rate[parent],
-                                               rate, extra_div);
-       else
-               divider = clk_get_divider(divider_bits, pll_rate[parent],
-                                         rate);
+               *extra_div = xdiv;
+
        assert(divider >= 0);
        if (adjust_periph_pll(periph_id, source, mux_bits, divider))
                return -1U;
index 8bba8a5..9492326 100644 (file)
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB     = $(obj)libimx-common.o
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
 COBJS-y        = iomux-v3.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
index 7fe5ce7..35880c7 100644 (file)
@@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
        if (sel_input_ofs)
                __raw_writel(sel_input, base + sel_input_ofs);
 
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+       if (!(pad_ctrl & NO_PAD_CTRL))
+               __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
+                       base + pad_ctrl_ofs);
+#else
        if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
                __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#endif
 }
 
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
index 7e3bb9c..db15159 100644 (file)
@@ -29,8 +29,8 @@
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
 #ifdef CONFIG_AM33XX
-#define NON_SECURE_SRAM_START  0x40304000
-#define NON_SECURE_SRAM_END    0x4030E000
+#define NON_SECURE_SRAM_START  0x402F0400
+#define NON_SECURE_SRAM_END    0x40310000
 #elif defined(CONFIG_TI814X)
 #define NON_SECURE_SRAM_START  0x40300000
 #define NON_SECURE_SRAM_END    0x40320000
index c913b5f..fedc674 100644 (file)
@@ -30,6 +30,7 @@ int print_cpuinfo(void);
 
 extern struct ctrl_stat *cstat;
 u32 get_device_type(void);
+void save_omap_boot_params(void);
 void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);
 
index 3429293..9a640a5 100644 (file)
@@ -38,4 +38,8 @@ typedef struct at91_dbu {
 #define AT91_DBU_CID_ARCH_9xx          0x01900000
 #define AT91_DBU_CID_ARCH_9XExx        0x02900000
 
+#define AT91_DBU_CIDR_MASK             0x1f
+#define AT91_DBU_CIDR                  0x40
+#define AT91_DBU_EXID                  0x44
+
 #endif
index 086cb9b..66075b4 100644 (file)
@@ -55,7 +55,16 @@ typedef struct at91_pmc {
        u32     reserved5[21];
        u32     wpmr;           /* 0xE4 Write Protect Mode Register (CAP0) */
        u32     wpsr;           /* 0xE8 Write Protect Status Register (CAP0) */
+#ifdef CONFIG_SAMA5D3
+       u32     reserved6[8];
+       u32     pcer1;          /* 0x100 Periperial Clock Enable Register 1 */
+       u32     pcdr1;          /* 0x104 Periperial Clock Disable Register 1 */
+       u32     pcsr1;          /* 0x108 Periperial Clock Status Register 1 */
+       u32     pcr;            /* 0x10c Periperial Control Register */
+       u32     ocr;            /* 0x110 Oscillator Calibration Register */
+#else
        u32     reserved8[5];
+#endif
 } at91_pmc_t;
 
 #endif /* end not assembly */
@@ -82,6 +91,16 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_PLLB         0x00000003
 #define AT91_PMC_MCKR_CSS_MASK         0x00000003
 
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_PRES_1           0x00000000
+#define AT91_PMC_MCKR_PRES_2           0x00000010
+#define AT91_PMC_MCKR_PRES_4           0x00000020
+#define AT91_PMC_MCKR_PRES_8           0x00000030
+#define AT91_PMC_MCKR_PRES_16          0x00000040
+#define AT91_PMC_MCKR_PRES_32          0x00000050
+#define AT91_PMC_MCKR_PRES_64          0x00000060
+#define AT91_PMC_MCKR_PRES_MASK                0x00000070
+#else
 #define AT91_PMC_MCKR_PRES_1           0x00000000
 #define AT91_PMC_MCKR_PRES_2           0x00000004
 #define AT91_PMC_MCKR_PRES_4           0x00000008
@@ -90,6 +109,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_PRES_32          0x00000014
 #define AT91_PMC_MCKR_PRES_64          0x00000018
 #define AT91_PMC_MCKR_PRES_MASK                0x0000001C
+#endif
 
 #ifdef CONFIG_AT91RM9200
 #define AT91_PMC_MCKR_MDIV_1           0x00000000
@@ -100,6 +120,9 @@ typedef struct at91_pmc {
 #else
 #define AT91_PMC_MCKR_MDIV_1           0x00000000
 #define AT91_PMC_MCKR_MDIV_2           0x00000100
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_MDIV_3           0x00000300
+#endif
 #define AT91_PMC_MCKR_MDIV_4           0x00000200
 #define AT91_PMC_MCKR_MDIV_MASK                0x00000300
 #endif
index d4852a3..04b0f83 100644 (file)
@@ -95,4 +95,5 @@ static inline unsigned long get_mci_clk_rate(void)
 }
 
 int at91_clock_init(unsigned long main_clock);
+void at91_periph_clk_enable(int id);
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
index 8812b11..b04641e 100644 (file)
@@ -43,6 +43,8 @@
 # include <asm/arch/at91cap9.h>
 #elif defined(CONFIG_AT91X40)
 # include <asm/arch/at91x40.h>
+#elif defined(CONFIG_SAMA5D3)
+# include <asm/arch/sama5d3.h>
 #else
 # error "Unsupported AT91 processor"
 #endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
new file mode 100644 (file)
index 0000000..883b932
--- /dev/null
@@ -0,0 +1,212 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ * (C) 2012 - 2013 Atmel Corporation.
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * Definitions for the SoC:
+ * SAMA5D3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARMV7           /* ARM A5 Core */
+#define CONFIG_AT91FAMILY      /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ   0       /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS   1       /* System Controller Interrupt */
+#define ATMEL_ID_DBGU  2       /* Debug Unit Interrupt */
+#define ATMEL_ID_PIT   3       /* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT   4       /* Watchdog timer Interrupt */
+#define ATMEL_ID_SMC   5       /* Multi-bit ECC Interrupt */
+#define ATMEL_ID_PIOA  6       /* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB  7       /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC  8       /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD  9       /* Parallel I/O Controller D */
+#define ATMEL_ID_PIOE  10      /* Parallel I/O Controller E */
+#define ATMEL_ID_SMD   11      /* SMD Soft Modem */
+#define ATMEL_ID_USART0        12      /* USART 0 */
+#define ATMEL_ID_USART1        13      /* USART 1 */
+#define ATMEL_ID_USART2        14      /* USART 2 */
+#define ATMEL_ID_USART3        15      /* USART 3 */
+#define ATMEL_ID_UART0 16
+#define ATMEL_ID_UART1 17
+#define ATMEL_ID_TWI0  18      /* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1  19      /* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2  20      /* Two-Wire Interface 2 */
+#define ATMEL_ID_MCI0  21      /* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1  22      /*  */
+#define ATMEL_ID_MCI2  23      /*  */
+#define ATMEL_ID_SPI0  24      /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1  25      /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0   26      /* */
+#define ATMEL_ID_TC1   27      /* */
+#define ATMEL_ID_PWMC  28      /* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC   29      /* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA0  30      /* DMA Controller */
+#define ATMEL_ID_DMA1  31      /* DMA Controller */
+#define ATMEL_ID_UHPHS 32      /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 33      /* USB Device High Speed */
+#define ATMEL_ID_GMAC  34
+#define ATMEL_ID_EMAC  35      /* Ethernet MAC */
+#define ATMEL_ID_LCDC  36      /* LCD Controller */
+#define ATMEL_ID_ISI   37      /* Image Sensor Interface */
+#define ATMEL_ID_SSC0  38      /* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1  39      /* Synchronous Serial Controller 1 */
+#define ATMEL_ID_CAN0  40
+#define ATMEL_ID_CAN1  41
+#define ATMEL_ID_SHA   42
+#define ATMEL_ID_AES   43
+#define ATMEL_ID_TDES  44
+#define ATMEL_ID_TRNG  45
+#define ATMEL_ID_ARM   46
+#define ATMEL_ID_IRQ0  47      /* Advanced Interrupt Controller */
+#define ATMEL_ID_FUSE  48
+#define ATMEL_ID_MPDDRC        49
+
+/* sama5d3 series chip id definitions */
+#define ARCH_ID_SAMA5D3                0x8a5c07c0
+#define ARCH_EXID_SAMA5D31     0x00444300
+#define ARCH_EXID_SAMA5D33     0x00414300
+#define ARCH_EXID_SAMA5D34     0x00414301
+#define ARCH_EXID_SAMA5D35     0x00584300
+
+#define cpu_is_sama5d3()       (get_chip_id() == ARCH_ID_SAMA5D3)
+#define cpu_is_sama5d31()      (cpu_is_sama5d3() && \
+               (get_extension_chip_id() == ARCH_EXID_SAMA5D31))
+#define cpu_is_sama5d33()      (cpu_is_sama5d3() && \
+               (get_extension_chip_id() == ARCH_EXID_SAMA5D33))
+#define cpu_is_sama5d34()      (cpu_is_sama5d3() && \
+               (get_extension_chip_id() == ARCH_EXID_SAMA5D34))
+#define cpu_is_sama5d35()      (cpu_is_sama5d3() && \
+               (get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_MCI0                0xf0000000
+#define ATMEL_BASE_SPI0                0xf0004000
+#define ATMEL_BASE_SSC0                0xf000C000
+#define ATMEL_BASE_TC2         0xf0010000
+#define ATMEL_BASE_TWI0                0xf0014000
+#define ATMEL_BASE_TWI1                0xf0018000
+#define ATMEL_BASE_USART0      0xf001c000
+#define ATMEL_BASE_USART1      0xf0020000
+#define ATMEL_BASE_UART0       0xf0024000
+#define ATMEL_BASE_GMAC                0xf0028000
+#define ATMEL_BASE_PWMC                0xf002c000
+#define ATMEL_BASE_LCDC                0xf0030000
+#define ATMEL_BASE_ISI         0xf0034000
+#define ATMEL_BASE_SFR         0xf0038000
+/* Reserved: 0xf003c000 - 0xf8000000 */
+#define ATMEL_BASE_MCI1                0xf8000000
+#define ATMEL_BASE_MCI2                0xf8004000
+#define ATMEL_BASE_SPI1                0xf8008000
+#define ATMEL_BASE_SSC1                0xf800c000
+#define ATMEL_BASE_CAN1                0xf8010000
+#define ATMEL_BASE_TC3         0xf8014000
+#define ATMEL_BASE_TSADC       0xf8018000
+#define ATMEL_BASE_TWI2                0xf801c000
+#define ATMEL_BASE_USART2      0xf8020000
+#define ATMEL_BASE_USART3      0xf8024000
+#define ATMEL_BASE_UART1       0xf8028000
+#define ATMEL_BASE_EMAC                0xf802c000
+#define ATMEL_BASE_UDHPS       0xf8030000
+#define ATMEL_BASE_SHA         0xf8034000
+#define ATMEL_BASE_AES         0xf8038000
+#define ATMEL_BASE_TDES                0xf803c000
+#define ATMEL_BASE_TRNG                0xf8040000
+/* Reserved:   0xf804400 - 0xffffc00 */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS         0xffffc000
+#define ATMEL_BASE_SMC         0xffffc000
+#define ATMEL_BASE_PMECC       (ATMEL_BASE_SMC + 0x070)
+#define ATMEL_BASE_PMERRLOC    (ATMEL_BASE_SMC + 0x500)
+#define ATMEL_BASE_FUSE                0xffffe400
+#define ATMEL_BASE_DMAC0       0xffffe600
+#define ATMEL_BASE_DMAC1       0xffffe800
+#define ATMEL_BASE_MPDDRC      0xffffea00
+#define ATMEL_BASE_MATRIX      0xffffec00
+#define ATMEL_BASE_DBGU                0xffffee00
+#define ATMEL_BASE_AIC         0xfffff000
+#define ATMEL_BASE_PIOA                0xfffff200
+#define ATMEL_BASE_PIOB                0xfffff400
+#define ATMEL_BASE_PIOC                0xfffff600
+#define ATMEL_BASE_PIOD                0xfffff800
+#define ATMEL_BASE_PIOE                0xfffffa00
+#define ATMEL_BASE_PMC         0xfffffc00
+#define ATMEL_BASE_RSTC                0xfffffe00
+#define ATMEL_BASE_SHDWN       0xfffffe10
+#define ATMEL_BASE_PIT         0xfffffe30
+#define ATMEL_BASE_WDT         0xfffffe40
+#define ATMEL_BASE_SCKCR       0xfffffe50
+#define ATMEL_BASE_GPBR                0xfffffe60
+#define ATMEL_BASE_RTC         0xfffffeb0
+/* Reserved:   0xfffffee0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM         0x00100000      /* Internal ROM base address */
+#define ATMEL_BASE_SRAM                0x00200000      /* Internal ROM base address */
+#define ATMEL_BASE_SRAM0       0x00300000      /* Internal SRAM base address */
+#define ATMEL_BASE_SRAM1       0x00310000      /* Internal SRAM base address */
+#define ATMEL_BASE_SMD         0x00400000      /* Internal ROM base address */
+#define ATMEL_BASE_UDPHS_FIFO  0x00500000      /* USB Device HS controller */
+#define ATMEL_BASE_OHCI                0x00600000      /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI                0x00700000      /* USB Host controller (EHCI) */
+#define ATMEL_BASE_AXI         0x00800000      /* Video Decoder Controller */
+#define ATMEL_BASE_DAP         0x00900000      /* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0         0x10000000
+#define ATMEL_BASE_DDRCS       0x20000000
+#define ATMEL_BASE_CS1         0x40000000
+#define ATMEL_BASE_CS2         0x50000000
+#define ATMEL_BASE_CS3         0x60000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS                5
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV           0x3fff
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512   0x10000
+#define ATMEL_PMECC_INDEX_OFFSET_1024  0x18000
+#define ATMEL_PMECC_ALPHA_OFFSET_512   0x10000
+#define ATMEL_PMECC_ALPHA_OFFSET_1024  0x18000
+
+/*
+ * SAMA5D3 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac(void);
+unsigned int has_gmac(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
new file mode 100644 (file)
index 0000000..eb53eba
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on SAMA5D3 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_SMC_H
+#define SAMA5D3_SMC_H
+
+#ifdef __ASSEMBLY__
+#define AT91_ASM_SMC_SETUP0    (ATMEL_BASE_SMC + 0x600)
+#define AT91_ASM_SMC_PULSE0    (ATMEL_BASE_SMC + 0x604)
+#define AT91_ASM_SMC_CYCLE0    (ATMEL_BASE_SMC + 0x608)
+#define AT91_ASM_SMC_MODE0     (ATMEL_BASE_SMC + 0x60C)
+#else
+struct at91_cs {
+       u32     reserved[96];
+       u32     setup;          /* 0x600 SMC Setup Register */
+       u32     pulse;          /* 0x604 SMC Pulse Register */
+       u32     cycle;          /* 0x608 SMC Cycle Register */
+       u32     timings;        /* 0x60C SMC Cycle Register */
+       u32     mode;           /* 0x610 SMC Mode Register */
+};
+
+struct at91_smc {
+       struct at91_cs cs[4];
+};
+#endif /*  __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x)          (x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x)       ((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x)          ((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x)       ((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x)          (x & 0x3f)
+#define AT91_SMC_PULSE_NCS_WR(x)       ((x & 0x3f) << 8)
+#define AT91_SMC_PULSE_NRD(x)          ((x & 0x3f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x)       ((x & 0x3f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x)          (x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x)          ((x & 0x1ff) << 16)
+
+#define AT91_SMC_TIMINGS_TCLR(x)       (x & 0xf)
+#define AT91_SMC_TIMINGS_TADL(x)       ((x & 0xf) << 4)
+#define AT91_SMC_TIMINGS_TAR(x)                ((x & 0xf) << 8)
+#define AT91_SMC_TIMINGS_OCMS(x)       ((x & 0x1) << 12)
+#define AT91_SMC_TIMINGS_TRR(x)                ((x & 0xf) << 16)
+#define AT91_SMC_TIMINGS_TWB(x)                ((x & 0xf) << 24)
+#define AT91_SMC_TIMINGS_RBNSEL(x)     ((x & 0xf) << 28)
+#define AT91_SMC_TIMINGS_NFSEL(x)      ((x & 0x1) << 31)
+
+#define AT91_SMC_MODE_RM_NCS           0x00000000
+#define AT91_SMC_MODE_RM_NRD           0x00000001
+#define AT91_SMC_MODE_WM_NCS           0x00000000
+#define AT91_SMC_MODE_WM_NWE           0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE     0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN      0x00000020
+#define AT91_SMC_MODE_EXNW_READY       0x00000030
+
+#define AT91_SMC_MODE_BAT              0x00000100
+#define AT91_SMC_MODE_DBW_8            0x00000000
+#define AT91_SMC_MODE_DBW_16           0x00001000
+#define AT91_SMC_MODE_DBW_32           0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x)     ((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF              0x00100000
+#define AT91_SMC_MODE_PMEN             0x01000000
+#define AT91_SMC_MODE_PS_4             0x00000000
+#define AT91_SMC_MODE_PS_8             0x10000000
+#define AT91_SMC_MODE_PS_16            0x20000000
+#define AT91_SMC_MODE_PS_32            0x30000000
+
+#endif
index a851f1f..beaf0d6 100644 (file)
 #define __ASM_ARCH_PINMUX_DEFS_H
 
 #include <asm/arch/davinci_misc.h>
+#include <config.h>
 
-/* SPI pin muxer settings */
+/* SPI0 pin muxer settings */
+extern const struct pinmux_config spi0_pins_base[3];
+extern const struct pinmux_config spi0_pins_scs0[1];
+extern const struct pinmux_config spi0_pins_ena[1];
+
+/* SPI1 pin muxer settings */
 extern const struct pinmux_config spi1_pins_base[3];
 extern const struct pinmux_config spi1_pins_scs0[1];
 
@@ -35,6 +41,7 @@ extern const struct pinmux_config uart2_pins_rtscts[2];
 
 /* EMAC pin muxer settings*/
 extern const struct pinmux_config emac_pins_rmii[7];
+extern const struct pinmux_config emac_pins_rmii_clk_source[1];
 extern const struct pinmux_config emac_pins_mii[15];
 extern const struct pinmux_config emac_pins_mdio[2];
 
@@ -43,13 +50,19 @@ extern const struct pinmux_config i2c0_pins[2];
 extern const struct pinmux_config i2c1_pins[2];
 
 /* EMIFA pin muxer settings */
+extern const struct pinmux_config emifa_pins[40];
+extern const struct pinmux_config emifa_pins_cs0[1];
 extern const struct pinmux_config emifa_pins_cs2[1];
 extern const struct pinmux_config emifa_pins_cs3[1];
 extern const struct pinmux_config emifa_pins_cs4[1];
 extern const struct pinmux_config emifa_pins_nand[12];
 extern const struct pinmux_config emifa_pins_nor[43];
 
+/* USB pin mux setting */
+extern const struct pinmux_config usb_pins[1];
+
 /* MMC pin muxer settings */
+extern const struct pinmux_config mmc0_pins_8bit[10];
 extern const struct pinmux_config mmc0_pins[6];
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h
deleted file mode 100644 (file)
index 8522335..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software;  you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0  (1<<0)
-#define BIT1  (1<<1)
-#define BIT2  (1<<2)
-#define BIT3  (1<<3)
-#define BIT4  (1<<4)
-#define BIT5  (1<<5)
-#define BIT6  (1<<6)
-#define BIT7  (1<<7)
-#define BIT8  (1<<8)
-#define BIT9  (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/clocks.h b/arch/arm/include/asm/arch-omap24xx/clocks.h
deleted file mode 100644 (file)
index 2e92569..0000000
--- a/