Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'

Conflicts:
	arch/arm/include/asm/arch-zynq/hardware.h

The conflict above was trivial and solved during merge.

diff --combined arch/arm/include/asm/arch-zynq/hardware.h
index 081624e20160fc8ae088da5609aca7566f7a8faf,ca56d8a2dbe73c9fb79365b6e3c95474288090bc..cd69677729cbf81ad237e1ac64b8477fde37e1f3
--- 1/arch/arm/include/asm/arch-zynq/hardware.h
--- 2/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@@ -17,8 -17,7 +17,9 @@@
  #define ZYNQ_SDHCI_BASEADDR1          0xE0101000
  #define ZYNQ_I2C_BASEADDR0            0xE0004000
  #define ZYNQ_I2C_BASEADDR1            0xE0005000
 +#define ZYNQ_SPI_BASEADDR0            0xE0006000
 +#define ZYNQ_SPI_BASEADDR1            0xE0007000
+ #define ZYNQ_DDRC_BASEADDR            0xF8006000
  
  /* Reflect slcr offsets */
  struct slcr_regs {
@@@ -86,4 -85,11 +87,11 @@@ struct scu_regs 
  
  #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
  
+ struct ddrc_regs {
+       u32 ddrc_ctrl; /* 0x0 */
+       u32 reserved[60];
+       u32 ecc_scrub; /* 0xF4 */
+ };
+ #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+ 
  #endif /* _ASM_ARCH_HARDWARE_H */

diff --combined board/xilinx/zynq/board.c
index c173f0cc51f498b1c1c9cf7514f28b0ec1d8223d,decdce549ecceb431f177cf4d6600193af4a8565..f7f1c59ac5455fd44f53ccfb98de1344ce084ac3
--- 1/board/xilinx/zynq/board.c
--- 2/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@@ -20,7 -20,6 +20,7 @@@ Xilinx_desc fpga010 = XILINX_XC7Z010_DE
  Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
 +Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  #endif
  
  int board_init(void)
@@@ -43,9 -42,6 +43,9 @@@
        case XILINX_ZYNQ_7045:
                fpga = fpga045;
                break;
 +      case XILINX_ZYNQ_7100:
 +              fpga = fpga100;
 +              break;
        }
  #endif
  
@@@ -65,6 -61,23 +65,23 @@@ int board_eth_init(bd_t *bis
  {
        u32 ret = 0;
  
+ #ifdef CONFIG_XILINX_AXIEMAC
+       ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+                                               XILINX_AXIDMA_BASEADDR);
+ #endif
+ #ifdef CONFIG_XILINX_EMACLITE
+       u32 txpp = 0;
+       u32 rxpp = 0;
+ # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+       txpp = 1;
+ # endif
+ # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+       rxpp = 1;
+ # endif
+       ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+                       txpp, rxpp);
+ #endif
+ 
  #if defined(CONFIG_ZYNQ_GEM)
  # if defined(CONFIG_ZYNQ_GEM0)
        ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
@@@ -100,5 -113,7 +117,7 @@@ int dram_init(void
  {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  
+       zynq_ddrc_init();
+ 
        return 0;
  }