OMAP5: DPLL core lock for OMAP5432

No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 10d286a6d4d84435fe485c20e618b25e75519705..b1fd277d6d58cc17726b73cbcadc41a3b1d9a73e 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -299,8 +299,12 @@ static void setup_dplls(void)
         * Core DPLL will be locked after setting up EMIF
         * using the FREQ_UPDATE method(freq_update_core())
         */
-       do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
-                                                               "core");
+       if (omap_revision() != OMAP5432_ES1_0)
+               do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+                                                       DPLL_NO_LOCK, "core");
+       else
+               do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+                                                       DPLL_LOCK, "core");
        /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
        temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
            (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 846511d03bded902feee0414028da15f88cfd123..23cf6199eb7431a89d2da09f93f30e455fd383b0 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1232,6 +1232,7 @@ void dmm_init(u32 base)
 void sdram_init(void)
 {
        u32 in_sdram, size_prog, size_detect;
+       u32 omap_rev = omap_revision();
 
        debug(">>sdram_init()\n");
 
@@ -1241,9 +1242,12 @@ void sdram_init(void)
        in_sdram = running_from_sdram();
        debug("in_sdram = %d\n", in_sdram);
 
-       if (!in_sdram)
-               bypass_dpll(&prcm->cm_clkmode_dpll_core);
-
+       if (!in_sdram) {
+               if (omap_rev != OMAP5432_ES1_0)
+                       bypass_dpll(&prcm->cm_clkmode_dpll_core);
+               else
+                       writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+       }
 
        do_sdram_init(EMIF1_BASE);
        do_sdram_init(EMIF2_BASE);
@@ -1255,7 +1259,8 @@ void sdram_init(void)
        }
 
        /* for the shadow registers to take effect */
-       freq_update_core();
+       if (omap_rev != OMAP5432_ES1_0)
+               freq_update_core();
 
        /* Do some testing after the init */
        if (!in_sdram) {

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 617729c32b7675f1bdd4c7793618b0a6b1119a1b..be20fc0ce66a6abbf69393f5675ae98291c6bcd5 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -525,6 +525,11 @@ struct omap4_scrm_regs {
 
 #define DPLL_CLKOUT_DIV_MASK   0x1F /* post-divider mask */
 
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT     0
+#define CM_DLL_CTRL_OVERRIDE_MASK      (1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE                0
+
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT         11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK          (1 << 11)

diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index f32cf3eeef7beb8e79ef791b3945dc3155291087..409e0e3f8c11336e7f1ff889c6f74596e2df2faf 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -490,6 +490,11 @@ struct omap5_prcm_regs {
 
 #define DPLL_CLKOUT_DIV_MASK   0x1F /* post-divider mask */
 
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT             0
+#define CM_DLL_CTRL_OVERRIDE_MASK              (1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE                        0
+
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT         11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK          (1 << 11)