]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
Merge git://git.denx.de/u-boot-arc
authorTom Rini <trini@ti.com>
Tue, 20 Jan 2015 21:41:11 +0000 (16:41 -0500)
committerTom Rini <trini@ti.com>
Tue, 20 Jan 2015 21:41:11 +0000 (16:41 -0500)
20 files changed:
arch/arc/Kconfig
arch/arc/Makefile
arch/arc/config.mk
arch/arc/cpu/arc700/Makefile [deleted file]
arch/arc/cpu/arcv1/Makefile [new file with mode: 0644]
arch/arc/cpu/arcv1/config.mk [moved from arch/arc/cpu/arc700/config.mk with 100% similarity]
arch/arc/cpu/arcv1/start.S [moved from arch/arc/cpu/arc700/start.S with 87% similarity]
arch/arc/cpu/u-boot.lds [moved from arch/arc/cpu/arc700/u-boot.lds with 88% similarity]
arch/arc/include/asm/arcregs.h
arch/arc/include/asm/sections.h
arch/arc/lib/Makefile
arch/arc/lib/cache.c [moved from arch/arc/cpu/arc700/cache.c with 79% similarity]
arch/arc/lib/cpu.c [moved from arch/arc/cpu/arc700/cpu.c with 100% similarity]
arch/arc/lib/interrupts.c [moved from arch/arc/cpu/arc700/interrupts.c with 97% similarity]
arch/arc/lib/relocate.c
arch/arc/lib/reset.c [moved from arch/arc/cpu/arc700/reset.c with 100% similarity]
arch/arc/lib/sections.c
arch/arc/lib/timer.c [moved from arch/arc/cpu/arc700/timer.c with 100% similarity]
board/synopsys/Kconfig
board/synopsys/axs101/Kconfig

index d3ef58be043c20d43f4807c8aa74e8f1ff8d48dc..c6b1efeb8bf9acb06a8cb66a79a8733c1468ccf3 100644 (file)
@@ -4,6 +4,9 @@ menu "ARC architecture"
 config SYS_ARCH
        default "arc"
 
+config SYS_CPU
+       default "arcv1"
+
 choice
        prompt "Target select"
 
index 03ea6dbae0d73d8a61e327af0e9e132b70c7028c..a59231e70ebe7a9c092b4f25ab30cf91a38ca37e 100644 (file)
@@ -2,8 +2,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-head-y := arch/arc/cpu/$(CPU)/start.o
-
 libs-y += arch/arc/cpu/$(CPU)/
 libs-y += arch/arc/lib/
 
index e408800a919b36bc4bd64252c6b4b4602bf62118..5321987a566387ffcaeae4c0d51dfa8801f75351 100644 (file)
@@ -21,6 +21,10 @@ ifeq ($(CROSS_COMPILE),)
 CROSS_COMPILE := $(ARC_CROSS_COMPILE)
 endif
 
+ifdef CONFIG_ARC_MMU_VER
+CONFIG_MMU = 1
+endif
+
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
 
 # Needed for relocation
diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile
deleted file mode 100644 (file)
index cdc5002..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-extra-y        += start.o
-
-obj-y  += cache.o
-obj-y  += cpu.o
-obj-y  += interrupts.o
-obj-y  += reset.o
-obj-y  += timer.o
diff --git a/arch/arc/cpu/arcv1/Makefile b/arch/arc/cpu/arcv1/Makefile
new file mode 100644 (file)
index 0000000..3704ebe
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += start.o
similarity index 87%
rename from arch/arc/cpu/arc700/start.S
rename to arch/arc/cpu/arcv1/start.S
index 563513b6904ad01ce9fff550f46c5b3b635b0a92..01cfba493392eb40eda2c720ccf48f471a66c11f 100644 (file)
 .endm
 
 .macro SAVE_ALL_SYS
-
+       /* saving %r0 to reg->r0 in advance since we read %ecr into it */
+       st      %r0, [%sp, -8]
+       lr      %r0, [%ecr]     /* all stack addressing is manual so far */
        st      %r0, [%sp]
-       lr      %r0, [%ecr]
-       st      %r0, [%sp, 8]   /* ECR */
-       st      %sp, [%sp, 4]
+       st      %sp, [%sp, -4]
+       /* now move %sp to reg->r0 position so we can do "push" automatically */
+       sub     %sp, %sp, 8
 
        SAVE_R1_TO_R24
        PUSH    %r25
        PUSHAX  %erbta
 .endm
 
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+       /* If MMU exists exception faulting address is loaded in EFA reg */
+       lr      %r0, [%efa]
+#else
+       /* Otherwise in ERET (exception return) reg */
+       lr      %r0, [%eret]
+#endif
+.endm
+
+.section .ivt, "ax",@progbits
 .align 4
-.globl _start
-_start:
+_ivt:
        /* Critical system events */
-       j       reset                   /* 0 - 0x000 */
+       j       _start                  /* 0 - 0x000 */
        j       memory_error            /* 1 - 0x008 */
        j       instruction_error       /* 2 - 0x010 */
 
@@ -98,15 +110,37 @@ _start:
        j       EV_Trap                 /* 0x128, Trap exception       (0x25) */
        j       EV_Extension            /* 0x130, Extn Intruction Excp (0x26) */
 
+.text
+.globl _start
+_start:
+       /* Setup interrupt vector base that matches "__text_start" */
+       sr      __ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+       /* Setup stack pointer */
+       mov     %sp, CONFIG_SYS_INIT_SP_ADDR
+       mov     %fp, %sp
+
+       /* Clear bss */
+       mov     %r0, __bss_start
+       mov     %r1, __bss_end
+
+clear_bss:
+       st.ab   0, [%r0, 4]
+       brlt    %r0, %r1, clear_bss
+
+       /* Zero the one and only argument of "board_init_f" */
+       mov_s   %r0, 0
+       j       board_init_f
+
 memory_error:
        SAVE_ALL_SYS
-       lr      %r0, [%efa]
+       SAVE_EXCEPTION_SOURCE
        mov     %r1, %sp
        j       do_memory_error
 
 instruction_error:
        SAVE_ALL_SYS
-       lr      %r0, [%efa]
+       SAVE_EXCEPTION_SOURCE
        mov     %r1, %sp
        j       do_instruction_error
 
@@ -117,7 +151,7 @@ interrupt_handler:
 
 EV_MachineCheck:
        SAVE_ALL_SYS
-       lr      %r0, [%efa]
+       SAVE_EXCEPTION_SOURCE
        mov     %r1, %sp
        j       do_machine_check_fault
 
@@ -133,7 +167,7 @@ EV_TLBMissD:
 
 EV_TLBProtV:
        SAVE_ALL_SYS
-       lr      %r0, [%efa]
+       SAVE_EXCEPTION_SOURCE
        mov     %r1, %sp
        j       do_tlb_prot_violation
 
@@ -152,27 +186,6 @@ EV_Extension:
        mov     %r0, %sp
        j       do_extension
 
-
-reset:
-       /* Setup interrupt vector base that matches "__text_start" */
-       sr      __text_start, [ARC_AUX_INTR_VEC_BASE]
-
-       /* Setup stack pointer */
-       mov     %sp, CONFIG_SYS_INIT_SP_ADDR
-       mov     %fp, %sp
-
-       /* Clear bss */
-       mov     %r0, __bss_start
-       mov     %r1, __bss_end
-
-clear_bss:
-       st.ab   0, [%r0, 4]
-       brlt    %r0, %r1, clear_bss
-
-       /* Zero the one and only argument of "board_init_f" */
-       mov_s   %r0, 0
-       j       board_init_f
-
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
similarity index 88%
rename from arch/arc/cpu/arc700/u-boot.lds
rename to arch/arc/cpu/u-boot.lds
index 2d01b21b3670f33078f492c8256025dcd70461c8..ccddbf7dc9b754997b9ae7abc81d8d3b7351a5d6 100644 (file)
@@ -13,7 +13,6 @@ SECTIONS
        .text : {
                *(.__text_start)
                *(.__image_copy_start)
-               CPUDIR/start.o (.text*)
                *(.text*)
        }
 
@@ -23,6 +22,20 @@ SECTIONS
                *(.__text_end)
        }
 
+       . = ALIGN(1024);
+       .ivt_start : {
+               *(.__ivt_start)
+       }
+
+       .ivt :
+       {
+               *(.ivt)
+       }
+
+       .ivt_end : {
+               *(.__ivt_end)
+       }
+
        . = ALIGN(4);
        .rodata : {
                *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
index 5d48d11bab6b76e2878b69e2ecb7742dd90beca2..8ace87fa0f25953a910161c8c9eaf4e845822b9f 100644 (file)
@@ -24,6 +24,7 @@
 #if (CONFIG_ARC_MMU_VER > 2)
 #define ARC_AUX_IC_PTAG                0x1E
 #endif
+#define ARC_BCR_IC_BUILD       0x77
 
 /* Timer related auxiliary registers */
 #define ARC_AUX_TIMER0_CNT     0x21    /* Timer 0 count */
@@ -42,6 +43,7 @@
 #if (CONFIG_ARC_MMU_VER > 2)
 #define ARC_AUX_DC_PTAG                0x5C
 #endif
+#define ARC_BCR_DC_BUILD       0x72
 
 #ifndef __ASSEMBLY__
 /* Accessors for auxiliary registers */
index 18484a17f216e1bbce10c3b4b7ceae79e5e4595c..b8f2a859fd9a17aff0db8b97decaa39faf2e556f 100644 (file)
@@ -10,5 +10,8 @@
 #include <asm-generic/sections.h>
 
 extern ulong __text_end;
+extern ulong __ivt_start;
+extern ulong __ivt_end;
+extern ulong __image_copy_start;
 
 #endif /* __ASM_ARC_SECTIONS_H */
index 7675f855d5a964c56bd9c0c67f3d4a34c98659a7..bae44199a41b16c7662607d77bff0715def97b83 100644 (file)
@@ -4,6 +4,9 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+obj-y += cache.o
+obj-y += cpu.o
+obj-y += interrupts.o
 obj-y += sections.o
 obj-y += relocate.o
 obj-y += strchr-700.o
@@ -13,4 +16,7 @@ obj-y += strlen.o
 obj-y += memcmp.o
 obj-y += memcpy-700.o
 obj-y += memset.o
+obj-y += reset.o
+obj-y += timer.o
+
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
similarity index 79%
rename from arch/arc/cpu/arc700/cache.c
rename to arch/arc/lib/cache.c
index 39d522d22f24dfbf2d418b0e150a923cb014a12c..fa19a13b7e698f49384683423b157a55557ffb17 100644 (file)
 #define DC_CTRL_CACHE_DISABLE  (1 << 0)
 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
 #define DC_CTRL_FLUSH_STATUS   (1 << 8)
+#define CACHE_VER_NUM_MASK     0xF
 
 int icache_status(void)
 {
+       /* If no cache in CPU exit immediately */
+       if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+               return 0;
+
        return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
               IC_CTRL_CACHE_DISABLE;
 }
 
 void icache_enable(void)
 {
+       /* If no cache in CPU exit immediately */
+       if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+               return;
+
        write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
                      ~IC_CTRL_CACHE_DISABLE);
 }
 
 void icache_disable(void)
 {
+       /* If no cache in CPU exit immediately */
+       if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+               return;
+
        write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
                      IC_CTRL_CACHE_DISABLE);
 }
@@ -43,24 +56,40 @@ void invalidate_icache_all(void)
 
 int dcache_status(void)
 {
+       /* If no cache in CPU exit immediately */
+       if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+               return 0;
+
        return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
                DC_CTRL_CACHE_DISABLE;
 }
 
 void dcache_enable(void)
 {
+       /* If no cache in CPU exit immediately */
+       if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+               return;
+
        write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
                      ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
 }
 
 void dcache_disable(void)
 {
+       /* If no cache in CPU exit immediately */
+       if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+               return;
+
        write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
                      DC_CTRL_CACHE_DISABLE);
 }
 
 void flush_dcache_all(void)
 {
+       /* If no cache in CPU exit immediately */
+       if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+               return;
+
        /* Do flush of entire cache */
        write_aux_reg(ARC_AUX_DC_FLSH, 1);
 
similarity index 100%
rename from arch/arc/cpu/arc700/cpu.c
rename to arch/arc/lib/cpu.c
similarity index 97%
rename from arch/arc/cpu/arc700/interrupts.c
rename to arch/arc/lib/interrupts.c
index d93a6eb547bff99c02548a144d48b2d86d42ff68..d7cab3bb409d4727123eba4afb23b9ecb93fb0cf 100644 (file)
@@ -23,7 +23,7 @@ int interrupt_init(void)
 int disable_interrupts(void)
 {
        int status = read_aux_reg(ARC_AUX_STATUS32);
-       int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
+       int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0;
 
        status &= ~(E1_MASK | E2_MASK);
        /* STATUS32 register is updated indirectly with "FLAG" instruction */
@@ -61,6 +61,7 @@ static void print_reg_file(long *reg_rev, int start_num)
 
 void show_regs(struct pt_regs *regs)
 {
+       printf("ECR:\t0x%08lx\n", regs->ecr);
        printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
               regs->ret, regs->blink, regs->status32);
        printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
index 2482bcdffcc33103e913a5dc8ee33e0923278b18..7797782563bb7f6dc736440fa6fa7aa0818a9e5a 100644 (file)
@@ -26,7 +26,7 @@ int do_elf_reloc_fixups(void)
                offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
 
                /* Check that the location of the relocation is in .text */
-               if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+               if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
                    offset_ptr_rom > last_offset) {
                        unsigned int val;
                        /* Switch to the in-RAM version */
@@ -44,29 +44,22 @@ int do_elf_reloc_fixups(void)
 #ifdef __LITTLE_ENDIAN__
                        /* If location in ".text" section swap value */
                        if ((unsigned int)offset_ptr_rom <
-                           (unsigned int)&__text_end)
+                           (unsigned int)&__ivt_end)
                                val = (val << 16) | (val >> 16);
 #endif
 
-                       /* Check that the target points into .text */
-                       if (val >= CONFIG_SYS_TEXT_BASE && val <=
-                           (unsigned int)&__bss_end) {
+                       /* Check that the target points into executable */
+                       if (val >= (unsigned int)&__image_copy_start && val <=
+                           (unsigned int)&__image_copy_end) {
                                val += gd->reloc_off;
 #ifdef __LITTLE_ENDIAN__
                                /* If location in ".text" section swap value */
                                if ((unsigned int)offset_ptr_rom <
-                                   (unsigned int)&__text_end)
+                                   (unsigned int)&__ivt_end)
                                        val = (val << 16) | (val >> 16);
 #endif
                                memcpy(offset_ptr_ram, &val, sizeof(int));
-                       } else {
-                               debug("   %p: rom reloc %x, ram %p, value %x, limit %x\n",
-                                     re_src, re_src->r_offset, offset_ptr_ram,
-                                     val, (unsigned int)&__bss_end);
                        }
-               } else {
-                       debug("   %p: rom reloc %x, last %p\n", re_src,
-                             re_src->r_offset, last_offset);
                }
                last_offset = offset_ptr_rom;
 
index b0b46a4e9aeeffdc62c8afaabba74151f17f363a..a72c6946d53e5913b619b4178340e5401191b276 100644 (file)
@@ -19,3 +19,5 @@ char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
 char __text_start[0] __attribute__((section(".__text_start")));
 char __text_end[0] __attribute__((section(".__text_end")));
 char __init_end[0] __attribute__((section(".__init_end")));
+char __ivt_start[0] __attribute__((section(".__ivt_start")));
+char __ivt_end[0] __attribute__((section(".__ivt_end")));
index a54d3dfde367cdb154a8d04ec9fb6f770287a833..f614f88cc611444be2b05e24c9d454525605a68b 100644 (file)
@@ -1,8 +1,5 @@
 if TARGET_ARCANGEL4
 
-config SYS_CPU
-       default "arc700"
-
 config SYS_VENDOR
        default "synopsys"
 
@@ -13,9 +10,6 @@ endif
 
 if TARGET_ARCANGEL4_BE
 
-config SYS_CPU
-       default "arc700"
-
 config SYS_VENDOR
        default "synopsys"
 
index 8448265888076bc9cb9b521a1dc5f0e8e6b44ca4..79e5400ea86b14f3d6af0c598be8b7c54f07ef58 100644 (file)
@@ -1,8 +1,5 @@
 if TARGET_AXS101
 
-config SYS_CPU
-       default "arc700"
-
 config SYS_BOARD
        default "axs101"