$(obj)u-boot.ais
-$(obj)u-boot.sb: $(obj)u-boot $(obj)spl/u-boot-spl.bin elftosb
+$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb
$(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
#define MXC_SSPCLK_MAX MXC_SSPCLK3
#endif
-static uint32_t mxs_get_pclk(void)
+static struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
+
+static uint32_t get_frac_clk(uint32_t refclk, uint32_t div, uint32_t _mask)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ uint32_t mask = (_mask + 1) >> 1;
+ uint32_t acc = div;
+ int period = 0;
+ int mult = 0;
+
+ if (div & mask)
+ return 0;
+
+ do {
+ acc += div;
+ if (acc & mask) {
+ acc &= ~mask;
+ mult++;
+ }
+ period++;
+ } while (acc != div);
+ return refclk * mult / period;
+}
+
+static uint32_t mxs_get_pclk(void)
+{
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
- /* No support of fractional divider calculation */
+ div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
+ clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
+ frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
+ clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+
if (clkctrl &
(CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
- return 0;
+ uint32_t refclk, mask;
+
+ if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
+ refclk = XTAL_FREQ_MHZ;
+ mask = CLKCTRL_CPU_DIV_XTAL_MASK >>
+ CLKCTRL_CPU_DIV_XTAL_OFFSET;
+ div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
+ CLKCTRL_CPU_DIV_XTAL_OFFSET;
+ } else {
+ refclk = PLL_FREQ_MHZ * PLL_FREQ_COEF / frac;
+ mask = CLKCTRL_CPU_DIV_CPU_MASK;
+ }
+ return get_frac_clk(refclk, div, mask);
}
- clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
-
/* XTAL Path */
if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
}
/* REF Path */
- clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
- frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
- div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
static uint32_t mxs_get_hclk(void)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
uint32_t div;
uint32_t clkctrl;
+ uint32_t refclk = mxs_get_pclk();
clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
+ div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
- /* No support of fractional divider calculation */
if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
- return 0;
+ return get_frac_clk(refclk, div, CLKCTRL_HBUS_DIV_MASK);
- div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
- return mxs_get_pclk() / div;
+ return refclk / div;
}
static uint32_t mxs_get_emiclk(void)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
static uint32_t mxs_get_gpmiclk(void)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
#if defined(CONFIG_MX23)
uint8_t *reg =
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
*/
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
int io_reg;
*/
static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint8_t ret;
int io_reg;
- if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
+ if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) {
+ printf("%s: IO clock selector %u out of range %u..%u\n",
+ __func__, io, MXC_IOCLK0, MXC_IOCLK1);
return 0;
-
+ }
io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
*/
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
if (ssp > MXC_SSPCLK_MAX)
*/
static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
- uint32_t clkreg;
+ uint32_t *clkreg;
uint32_t clk, tmp;
if (ssp > MXC_SSPCLK_MAX)
if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
return XTAL_FREQ_KHZ;
- clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
- (ssp * sizeof(struct mxs_register_32));
+ clkreg = &clkctrl_regs->hw_clkctrl_ssp0 +
+ ssp * sizeof(struct mxs_register_32);
tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
-
if (tmp == 0)
return 0;
void mxs_set_lcdclk(uint32_t freq)
{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t fp, x, k_rest, k_best, x_best, tk;
int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
#endif
}
+static uint32_t mxs_get_xbus_clk(void)
+{
+ uint32_t div;
+ uint32_t clkctrl;
+ uint32_t refclk = mxs_get_pclk();
+
+ clkctrl = readl(&clkctrl_regs->hw_clkctrl_xbus);
+ div = clkctrl & CLKCTRL_XBUS_DIV_MASK;
+
+ if (clkctrl & CLKCTRL_XBUS_DIV_FRAC_EN)
+ return get_frac_clk(refclk, div, CLKCTRL_XBUS_DIV_MASK);
+
+ return refclk / div;
+}
+
uint32_t mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_SSP3_CLK:
return mxs_get_sspclk(MXC_SSPCLK3);
#endif
+ case MXC_XBUS_CLK:
+ return mxs_get_xbus_clk() * 1000000;
+ default:
+ printf("Invalid clock selector %u\n", clk);
}
return 0;
}
#endif
+#define pr_clk(n, c) { \
+ unsigned long clk = c; \
+ printf("%-5s %3lu.%03lu MHz\n", #n ":", clk / 1000000, \
+ clk / 1000 % 1000); \
+}
+
int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
- printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
- printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
- printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
+ pr_clk(CPU, mxc_get_clock(MXC_ARM_CLK));
+ pr_clk(APBH, mxc_get_clock(MXC_AHB_CLK));
+ pr_clk(APBX, mxc_get_clock(MXC_XBUS_CLK));
+ pr_clk(IO0, mxc_get_clock(MXC_IO0_CLK) * 1000);
+ pr_clk(IO1, mxc_get_clock(MXC_IO1_CLK) * 1000);
+ pr_clk(EMI, mxc_get_clock(MXC_EMI_CLK) * 1000000);
+ pr_clk(GPMI, mxc_get_clock(MXC_GPMI_CLK));
return 0;
}
TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
&timrot_regs->hw_timrot_timctrl0);
- /* Set fixed_count to maximal value */
+ /* Set fixed_count to maximum value */
#if defined(CONFIG_MX23)
writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
#elif defined(CONFIG_MX28)
writel(20 * MXS_INCREMENTER_HZ,
&timrot_regs->hw_timrot_fixed_count0);
gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ;
-#endif
-#ifdef DEBUG_TIMER_WRAP
+
/* Make the usec counter roll over 30 seconds after startup */
writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS);
#endif
#ifdef CONFIG_SPL_BUILD
u32 spl_boot_device(void)
{
- return (u32) (gd->arch.omap_boot_params.omap_bootdevice);
+ return gd->arch.omap_boot_params.omap_bootdevice;
}
u32 spl_boot_mode(void)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, MXC_CLK32);
-
return tick;
}
+static inline unsigned long time_to_tick(unsigned long time)
+{
+ unsigned long long ticks = (unsigned long long)time;
+
+ ticks *= MXC_CLK32;
+ do_div(ticks, CONFIG_SYS_HZ);
+ return ticks;
+}
+
static inline unsigned long long us_to_tick(unsigned long long usec)
{
usec = usec * MXC_CLK32 + 999999;
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
+ /*
+ * LW: get_ticks() returns a long long with the top 32 bits always ZERO!
+ * Thus the calculation above is not true.
+ * A 64bit timer value would only make sense if it was
+ * consistently used throughout the code. Thus also the parameter
+ * to get_timer() and its return value would need to be 64bit wide!
+ */
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
- return get_timer_masked() - base;
+ return tick_to_time(get_ticks() - time_to_tick(base));
}
/* delay x useconds AND preserve advance timstamp value */
void __udelay(unsigned long usec)
{
- unsigned long long tmp;
- ulong tmo;
+ unsigned long start = __raw_readl(&cur_gpt->counter);
+ unsigned long ticks;
+
+ if (usec == 0)
+ return;
- tmo = us_to_tick(usec);
- tmp = get_ticks() + tmo; /* get current timestamp */
+ ticks = us_to_tick(usec);
+ if (ticks == 0)
+ ticks++;
- while (get_ticks() < tmp) /* loop till event */
- /*NOP*/;
+ while (__raw_readl(&cur_gpt->counter) - start < ticks)
+ /* loop till event */;
}
/*
MXC_SSP2_CLK,
MXC_SSP3_CLK,
#endif
+ MXC_XBUS_CLK,
};
enum mxs_ioclock {
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
struct mxs_ssp_regs {
- mxs_reg_32(hw_ssp_ctrl0)
- mxs_reg_32(hw_ssp_cmd0)
- mxs_reg_32(hw_ssp_cmd1)
- mxs_reg_32(hw_ssp_compref)
- mxs_reg_32(hw_ssp_compmask)
- mxs_reg_32(hw_ssp_timing)
- mxs_reg_32(hw_ssp_ctrl1)
- mxs_reg_32(hw_ssp_data)
- mxs_reg_32(hw_ssp_sdresp0)
- mxs_reg_32(hw_ssp_sdresp1)
- mxs_reg_32(hw_ssp_sdresp2)
- mxs_reg_32(hw_ssp_sdresp3)
- mxs_reg_32(hw_ssp_status)
-
- uint32_t reserved1[12];
-
- mxs_reg_32(hw_ssp_debug)
- mxs_reg_32(hw_ssp_version)
+ mxs_reg_32(hw_ssp_ctrl0);
+ mxs_reg_32(hw_ssp_cmd0);
+ mxs_reg_32(hw_ssp_cmd1);
+ mxs_reg_32(hw_ssp_compref);
+ mxs_reg_32(hw_ssp_compmask);
+ mxs_reg_32(hw_ssp_timing);
+ mxs_reg_32(hw_ssp_ctrl1);
+ mxs_reg_32(hw_ssp_data);
+ mxs_reg_32(hw_ssp_sdresp0);
+ mxs_reg_32(hw_ssp_sdresp1);
+ mxs_reg_32(hw_ssp_sdresp2);
+ mxs_reg_32(hw_ssp_sdresp3);
+ mxs_reg_32(hw_ssp_status);
+ reg_32(reserved[3]);
+ mxs_reg_32(hw_ssp_debug);
+ mxs_reg_32(hw_ssp_version);
};
#elif defined(CONFIG_MX28)
struct mxs_ssp_regs {
gd->relocaddr = addr;
gd->start_addr_sp = addr_sp;
gd->reloc_off = addr - _TEXT_BASE;
+
debug("relocation Offset is: %08lx\n", gd->reloc_off);
if (new_fdt) {
memcpy(new_fdt, gd->fdt_blob, fdt_size);
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
/*
- * TODO: printing of the clock inforamtion of the board is now
+ * TODO: printing of the clock information of the board is now
* implemented as part of bdinfo command. Currently only support for
* davinci SOC's is added. Remove this check once all the board
* implement this.
int off;
int ret;
const uint32_t *ph;
+ int disable_otg = 0;
+ int disable_phy_pins = 1;
debug("OTG mode is '%s'\n", otg_mode ? otg_mode : "<UNSET>");
if (otg_mode && (strcmp(otg_mode, "device") == 0 ||
strcmp(otg_mode, "gadget") == 0)) {
+ debug("Setting dr_mode to 'peripheral'\n");
ret = fdt_setprop_string(blob, off, "dr_mode", "peripheral");
- phy = NULL;
} else if (otg_mode && strcmp(otg_mode, "host") == 0) {
+ debug("Setting dr_mode to 'host'\n");
ret = fdt_setprop_string(blob, off, "dr_mode", "host");
- phy = NULL;
+ disable_phy_pins = 0;
+ } else if (otg_mode && strcmp(otg_mode, "otg") == 0) {
+ debug("Setting dr_mode to 'host'\n");
+ ret = fdt_setprop_string(blob, off, "dr_mode", "otg");
} else {
if (otg_mode && strcmp(otg_mode, "none") != 0)
printf("Invalid 'otg_mode' setting '%s'; disabling usbotg port\n",
otg_mode);
- ret = fdt_setprop_string(blob, off, "status", "disabled");
+ disable_otg = 1;
+ ret = 0;
}
- if (ret)
- goto out;
- if (phy == NULL)
+ if ((!disable_phy_pins && !disable_otg) || ret)
goto out;
+ if (disable_otg) {
+ ret = fdt_setprop_string(blob, off, "status", "disabled");
+ if (ret)
+ goto out;
+ }
+
ph = fdt_getprop(blob, off, phy, NULL);
if (ph == NULL) {
printf("Failed to find '%s' phandle in node '%s'\n", phy,
phy, fdt32_to_cpu(*ph));
goto out;
}
- ret = fdt_setprop_string(blob, off, "status", "disabled");
+ if (disable_otg) {
+ debug("Disabling usbphy\n");
+ ret = fdt_setprop_string(blob, off, "status", "disabled");
+ } else {
+ debug("Removing host pins from usbphy\n");
+ ret = fdt_delprop(blob, off, "pinctrl-0");
+ }
out:
if (ret)
printf("Failed to update usbotg: %d\n", ret);
- printf("node '%s' updated\n", node);
+ else
+ debug("node '%s' updated\n", node);
karo_set_fdtsize(blob);
}
}
}
+#define RTC_PERSISTENT0_CLK32_MASK (RTC_PERSISTENT0_CLOCKSOURCE | \
+ RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
+static u32 boot_cause __attribute__((section("data")));
+
int board_early_init_f(void)
{
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
+ u32 rtc_stat;
+ int timeout = 5000;
+
random_init();
/* IO0 clock at 480MHz */
gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
+
+ while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
+ RTC_STAT_STALE_REGS_PERSISTENT0) {
+ if (timeout-- < 0)
+ return 0;
+ udelay(1);
+ }
+ boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
+ if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
+ RTC_PERSISTENT0_CLK32_MASK) {
+ if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
+ goto rtc_err;
+ writel(RTC_PERSISTENT0_CLK32_MASK,
+ &rtc_regs->hw_rtc_persistent0_set);
+ }
+ return 0;
+
+rtc_err:
+ serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
return 0;
}
return 0;
}
+#define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
+ RTC_PERSISTENT0_ALARM_WAKE | \
+ RTC_PERSISTENT0_THERMAL_RESET)
+
+static void thermal_init(void)
+{
+ struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
+
+ writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
+ POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
+ &power_regs->hw_power_thermal);
+
+ writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
+ CLKCTRL_RESET_THERMAL_RESET_ENABLE,
+ &clkctrl_regs->hw_clkctrl_reset);
+}
+
int checkboard(void)
{
- printf("Board: Ka-Ro TX28-4%sxx\n", TX28_MOD_SUFFIX);
+ struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+ u32 pwr_sts = readl(&power_regs->hw_power_sts);
+ u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
+ const char *dlm = "";
+
+ printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
+ CONFIG_SDRAM_SIZE / SZ_128M);
+
+ printf("POWERUP Source: ");
+ if (pwrup_src & (3 << 0)) {
+ printf("%sPSWITCH %s voltage", dlm,
+ pwrup_src & (1 << 1) ? "HIGH" : "MID");
+ dlm = " | ";
+ }
+ if (pwrup_src & (1 << 4)) {
+ printf("%sRTC", dlm);
+ dlm = " | ";
+ }
+ if (pwrup_src & (1 << 5)) {
+ printf("%s5V", dlm);
+ dlm = " | ";
+ }
+ printf("\n");
+
+ if (boot_cause & BOOT_CAUSE_MASK) {
+ dlm="";
+ printf("Last boot cause: ");
+ if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
+ printf("%sEXTERNAL", dlm);
+ dlm = " | ";
+ }
+ if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
+ printf("%sTHERMAL", dlm);
+ dlm = " | ";
+ }
+ if (*dlm != '\0')
+ printf(" RESET");
+ if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
+ printf("%sALARM WAKE", dlm);
+ dlm = " | ";
+ }
+ printf("\n");
+ }
+
+ while (pwr_sts & POWER_STS_THERMAL_WARNING) {
+ static int first = 1;
+
+ if (first) {
+ printf("CPU too hot to boot\n");
+ first = 0;
+ }
+ if (tstc())
+ break;
+ pwr_sts = readl(&power_regs->hw_power_sts);
+ }
+
+ if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
+ thermal_init();
+
return 0;
}
#include <jffs2/jffs2.h>
#include <mtd_node.h>
struct node_info tx28_nand_nodes[] = {
- { "gpmi-nand", MTD_DEV_TYPE_NAND, },
+ { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
};
#else
#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
#endif
-static void tx28_fixup_flexcan(void *blob)
+static int flexcan_enabled(void *blob)
{
- karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80032000, "transceiver-switch");
- karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80034000, "transceiver-switch");
+ const char *status;
+ int off = fdt_path_offset(blob, "can0");
+
+ if (off < 0) {
+ printf("node 'can0' not found\n");
+ } else {
+ status = fdt_getprop(blob, off, "status", NULL);
+ if (status && strcmp(status, "okay") == 0) {
+ printf("can0 is enabled\n");
+ return 1;
+ }
+ }
+ off = fdt_path_offset(blob, "can1");
+ if (off < 0) {
+ printf("node 'can1' not found\n");
+ return 0;
+ }
+ status = fdt_getprop(blob, off, "status", NULL);
+ if (status && strcmp(status, "okay") == 0) {
+ printf("can1 is enabled\n");
+ return 1;
+ }
+ printf("can driver disabled\n");
+ return 0;
+}
+
+static void tx28_set_lcd_pins(void *blob, const char *name)
+{
+ int off = fdt_path_offset(blob, name);
+ u32 ph;
+ const struct fdt_property *pc;
+ int len;
+
+ if (off < 0)
+ return;
+
+ ph = fdt32_to_cpu(fdt_create_phandle(blob, off));
+ if (!ph)
+ return;
+
+ off = fdt_path_offset(blob, "lcdif");
+ if (off < 0)
+ return;
+
+ pc = fdt_get_property(blob, off, "pinctrl-0", &len);
+ if (!pc || len < sizeof(ph))
+ return;
+
+ memcpy((void *)pc->data, &ph, sizeof(ph));
+ fdt_setprop(blob, off, "pinctrl-0", pc->data, len);
+}
+
+static void tx28_fixup_flexcan(void *blob, int stk5_v5)
+{
+ const char *can_xcvr = "disabled";
+
+ if (stk5_v5) {
+ if (flexcan_enabled(blob)) {
+ tx28_set_lcd_pins(blob, "lcdif_23bit_pins_a");
+ can_xcvr = "okay";
+ } else {
+ tx28_set_lcd_pins(blob, "lcdif_24bit_pins_a");
+ }
+ } else {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && (strcmp(otg_mode, "host") == 0))
+ karo_fdt_enable_node(blob, "can1", 0);
+ }
+ fdt_find_and_setprop(blob, "/regulators/can-xcvr", "status",
+ can_xcvr, strlen(can_xcvr) + 1, 1);
}
static void tx28_fixup_fec(void *blob)
void ft_board_setup(void *blob, bd_t *bd)
{
const char *baseboard = getenv("baseboard");
+ int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
#ifdef CONFIG_TX28_S
/* TX28-41xx (aka TX28S) has no external RTC
karo_fdt_remove_node(blob, "ds1339");
karo_fdt_remove_node(blob, "gpio5");
#endif
- if (baseboard != NULL && strcmp(baseboard, "stk5-v5") == 0) {
+ if (stk5_v5) {
karo_fdt_remove_node(blob, "stk5led");
} else {
- tx28_fixup_flexcan(blob);
tx28_fixup_fec(blob);
}
-
- if (baseboard != NULL && strcmp(baseboard, "stk5-v3") == 0) {
- const char *otg_mode = getenv("otg_mode");
-
- if (otg_mode && (strcmp(otg_mode, "device") == 0 ||
- strcmp(otg_mode, "gadget") == 0))
- karo_fdt_enable_node(blob, "can1", 0);
- }
+ tx28_fixup_flexcan(blob, stk5_v5);
fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
fdt_fixup_ethernet(blob);
#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
#endif
-#define REG_CCOSR 0x60
#define REG_CCGR0 0x68
#define REG_CCGR1 0x6c
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000)
-#if 1
- MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCOSR, (1 << 24) | (0xe << 16))
- MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x320, 0x4) /* GPIO_3 => CLKO2 */
-#endif
+
MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */
MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
-//#define DO_WL_CALIB
-
#ifndef CCM_CCR
#error asm-offsets not included
#endif
"fdt rsvmem delete <index> - Delete a mem reserves\n"
"fdt chosen [<start> <end>] - Add/update the /chosen branch in the tree\n"
" <start>/<end> - initrd start/end addr\n"
- "NOTE: Dereference aliases by omiting the leading '/', "
+ "NOTE: Dereference aliases by omitting the leading '/', "
"e.g. fdt print ethernet0.";
#endif
fb[2] = *bmap++; /* R */
fb += 4;
}
+ bmap += (padded_width - width) * 4;
fb -= lcd_line_length + width * (bpix / 8);
}
break;
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
return 0;
#endif
-
esdhc_write32(®s->irqstat, -1);
sync();
static int mmc_init_setup(struct mmc *mmc)
{
- struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv_data = mmc->priv;
+ struct hsmmc *mmc_base = priv_data->base_addr;
unsigned int reg_val;
unsigned int dsor;
ulong start;
- mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
mmc_board_init(mmc);
writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv_data = mmc->priv;
+ struct hsmmc *mmc_base = priv_data->base_addr;
unsigned int flags, mmc_stat;
ulong start;
- mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
start = get_timer(0);
while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
if (get_timer(start) > MAX_RETRY_MS) {
static void mmc_set_ios(struct mmc *mmc)
{
- struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv_data = mmc->priv;
+ struct hsmmc *mmc_base = priv_data->base_addr;
unsigned int dsor = 0;
ulong start;
- mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
/* configue bus width */
switch (mmc->bus_width) {
case 8:
#define NFC_VERSION "unknown"
#endif
-#ifndef CONFIG_MXC_NAND_IP_REGS_BASE
-#define CONFIG_MXC_NAND_IP_REGS_BASE 0
-#endif
-
/* Addresses for NFC registers */
#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
{
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
+
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
if (ret)
goto err;
__raw_writel(di_gen, DI_GENERAL(clk->id));
-debug("%s@%d:\n", __func__, __LINE__);
ipu_pixel_clk_recalc(clk);
clk->disable(clk->parent);
clk->parent = parent;
* SPDX-License-Identifier: GPL-2.0+
*/
+/* #define DEBUG */
#include <common.h>
#include <asm/errno.h>
#include <linux/string.h>
*
*/
-#ifndef __CONFIGS_TX48_H
-#define __CONFIGS_TX48_H
+#ifndef __CONFIG_H
+#define __CONFIG_H
#include <asm/sizes.h>
#define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
-#endif /* __CONFIGS_TX48_H */
+#endif /* __CONFIG_H */
* SPDX-License-Identifier: GPL-2.0
*
*/
-#ifndef __CONFIGS_TX51_H
-#define __CONFIGS_TX51_H
-#define CONFIG_MX51 /* must be set before including imx-regs.h */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX51 /* must be set before including imx-regs.h */
#include <asm/sizes.h>
#include <asm/arch/imx-regs.h>
* Ka-Ro TX51 board - SoC configuration
*/
#define CONFIG_SYS_MX5_IOMUX_V3
-#define CONFIG_MXC_GPIO /* GPIO control */
+#define CONFIG_MXC_GPIO /* GPIO control */
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
-#if 0
-#define CONFIG_CMD_IIM
-#endif
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI // 0xcfff0000
-#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR // 0x83fdb000
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_FSL_IIM
#endif
-#endif /* __CONFIGS_TX51_H */
+#endif /* __CONFIG_H */
*
*/
-#ifndef __CONFIGS_TX53_H
-#define __CONFIGS_TX53_H
+#ifndef __CONFIG_H
+#define __CONFIG_H
-#define CONFIG_MX53 /* must be set before including imx-regs.h */
+#define CONFIG_MX53 /* must be set before including imx-regs.h */
#include <asm/sizes.h>
#include <asm/arch/imx-regs.h>
/*
* Ka-Ro TX53 board - SoC configuration
*/
-#define CONFIG_TX53 /* TX53 SoM */
+#define CONFIG_TX53 /* TX53 SoM */
#define CONFIG_SYS_MX5_IOMUX_V3
-#define CONFIG_MXC_GPIO /* GPIO control */
+#define CONFIG_MXC_GPIO /* GPIO control */
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
-#if 0
-#define CONFIG_CMD_IIM
-#endif
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI // 0xf7ff0000
-#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR // 0x63fdb000
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
-#if 0
-#define CONFIG_SYS_FSL_ESDHC_USE_PIO
-#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
#define CONFIG_FSL_IIM
#endif
-#endif /* __CONFIGS_TX53_H */
+#endif /* __CONFIG_H */
*
*/
-#ifndef __TX6_H
-#define __TX6_H
+#ifndef __CONFIG_H
+#define __CONFIG_H
#include <asm/sizes.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
GENERATED_GBL_DATA_SIZE)
-#endif /* __CONFIGS_TX6_H */
+#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / commitdiff