update to 2015.04-rc1
authorLothar Waßmann <LW@KARO-electronics.de>
Mon, 9 Mar 2015 08:21:53 +0000 (09:21 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Mon, 9 Mar 2015 08:21:53 +0000 (09:21 +0100)
31 files changed:
1  2 
Kconfig
README
arch/arm/Kconfig
arch/arm/cpu/arm926ejs/cpu.c
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/cpu.c
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/emif.h
arch/arm/lib/cache.c
board/karo/tx53/u-boot.lds
common/Kconfig
common/Makefile
common/cmd_mmc.c
common/lcd.c
common/spl/spl.c
drivers/gpio/gpio-uclass.c
drivers/i2c/Kconfig
drivers/mmc/Kconfig
drivers/mmc/mmc.c
drivers/mmc/omap_hsmmc.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/omap_gpmc.c
drivers/net/phy/phy.c
include/asm-generic/gpio.h
include/configs/tx53.h
include/lcd.h
include/net.h
include/netdev.h
net/Makefile
tools/Makefile

diff --cc Kconfig
+++ b/Kconfig
@@@ -148,6 -156,6 +155,8 @@@ source "arch/Kconfig
  
  source "common/Kconfig"
  
++source "disk/Kconfig"
++
  source "dts/Kconfig"
  
  source "net/Kconfig"
diff --cc README
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
  
  /* Reg mapping structure */
  struct emif_reg_struct {
 -      u32 emif_mod_id_rev;
 -      u32 emif_status;
 -      u32 emif_sdram_config;
 -      u32 emif_lpddr2_nvm_config;
 -      u32 emif_sdram_ref_ctrl;
 -      u32 emif_sdram_ref_ctrl_shdw;
 -      u32 emif_sdram_tim_1;
 -      u32 emif_sdram_tim_1_shdw;
 -      u32 emif_sdram_tim_2;
 -      u32 emif_sdram_tim_2_shdw;
 -      u32 emif_sdram_tim_3;
 -      u32 emif_sdram_tim_3_shdw;
 -      u32 emif_lpddr2_nvm_tim;
 -      u32 emif_lpddr2_nvm_tim_shdw;
 -      u32 emif_pwr_mgmt_ctrl;
 -      u32 emif_pwr_mgmt_ctrl_shdw;
 -      u32 emif_lpddr2_mode_reg_data;
 -      u32 padding1[1];
 -      u32 emif_lpddr2_mode_reg_data_es2;
 -      u32 padding11[1];
 -      u32 emif_lpddr2_mode_reg_cfg;
 -      u32 emif_l3_config;
 -      u32 emif_l3_cfg_val_1;
 -      u32 emif_l3_cfg_val_2;
 -      u32 emif_iodft_tlgc;
 -      u32 padding2[7];
 -      u32 emif_perf_cnt_1;
 -      u32 emif_perf_cnt_2;
 -      u32 emif_perf_cnt_cfg;
 -      u32 emif_perf_cnt_sel;
 -      u32 emif_perf_cnt_tim;
 -      u32 padding3;
 -      u32 emif_read_idlectrl;
 -      u32 emif_read_idlectrl_shdw;
 -      u32 padding4;
 -      u32 emif_irqstatus_raw_sys;
 -      u32 emif_irqstatus_raw_ll;
 -      u32 emif_irqstatus_sys;
 -      u32 emif_irqstatus_ll;
 -      u32 emif_irqenable_set_sys;
 -      u32 emif_irqenable_set_ll;
 -      u32 emif_irqenable_clr_sys;
 -      u32 emif_irqenable_clr_ll;
 -      u32 padding5;
 -      u32 emif_zq_config;
 -      u32 emif_temp_alert_config;
 -      u32 emif_l3_err_log;
 -      u32 emif_rd_wr_lvl_rmp_win;
 -      u32 emif_rd_wr_lvl_rmp_ctl;
 -      u32 emif_rd_wr_lvl_ctl;
 -      u32 padding6[1];
 -      u32 emif_ddr_phy_ctrl_1;
 -      u32 emif_ddr_phy_ctrl_1_shdw;
 -      u32 emif_ddr_phy_ctrl_2;
 -      u32 padding7[4];
 -      u32 emif_prio_class_serv_map;
 -      u32 emif_connect_id_serv_1_map;
 -      u32 emif_connect_id_serv_2_map;
 -      u32 padding8[5];
 -      u32 emif_rd_wr_exec_thresh;
 -      u32 emif_cos_config;
 -      u32 padding9[6];
 -      u32 emif_ddr_phy_status[28];
 -      u32 padding10[20];
 -      u32 emif_ddr_ext_phy_ctrl_1;
 -      u32 emif_ddr_ext_phy_ctrl_1_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_2;
 -      u32 emif_ddr_ext_phy_ctrl_2_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_3;
 -      u32 emif_ddr_ext_phy_ctrl_3_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_4;
 -      u32 emif_ddr_ext_phy_ctrl_4_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_5;
 -      u32 emif_ddr_ext_phy_ctrl_5_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_6;
 -      u32 emif_ddr_ext_phy_ctrl_6_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_7;
 -      u32 emif_ddr_ext_phy_ctrl_7_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_8;
 -      u32 emif_ddr_ext_phy_ctrl_8_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_9;
 -      u32 emif_ddr_ext_phy_ctrl_9_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_10;
 -      u32 emif_ddr_ext_phy_ctrl_10_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_11;
 -      u32 emif_ddr_ext_phy_ctrl_11_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_12;
 -      u32 emif_ddr_ext_phy_ctrl_12_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_13;
 -      u32 emif_ddr_ext_phy_ctrl_13_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_14;
 -      u32 emif_ddr_ext_phy_ctrl_14_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_15;
 -      u32 emif_ddr_ext_phy_ctrl_15_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_16;
 -      u32 emif_ddr_ext_phy_ctrl_16_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_17;
 -      u32 emif_ddr_ext_phy_ctrl_17_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_18;
 -      u32 emif_ddr_ext_phy_ctrl_18_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_19;
 -      u32 emif_ddr_ext_phy_ctrl_19_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_20;
 -      u32 emif_ddr_ext_phy_ctrl_20_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_21;
 -      u32 emif_ddr_ext_phy_ctrl_21_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_22;
 -      u32 emif_ddr_ext_phy_ctrl_22_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_23;
 -      u32 emif_ddr_ext_phy_ctrl_23_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_24;
 -      u32 emif_ddr_ext_phy_ctrl_24_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_25;
 -      u32 emif_ddr_ext_phy_ctrl_25_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_26;
 -      u32 emif_ddr_ext_phy_ctrl_26_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_27;
 -      u32 emif_ddr_ext_phy_ctrl_27_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_28;
 -      u32 emif_ddr_ext_phy_ctrl_28_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_29;
 -      u32 emif_ddr_ext_phy_ctrl_29_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_30;
 -      u32 emif_ddr_ext_phy_ctrl_30_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_31;
 -      u32 emif_ddr_ext_phy_ctrl_31_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_32;
 -      u32 emif_ddr_ext_phy_ctrl_32_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_33;
 -      u32 emif_ddr_ext_phy_ctrl_33_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_34;
 -      u32 emif_ddr_ext_phy_ctrl_34_shdw;
 -      u32 emif_ddr_ext_phy_ctrl_35;
 -      u32 emif_ddr_ext_phy_ctrl_35_shdw;
 +      u32 emif_mod_id_rev;                    /* 0x000 */
 +      u32 emif_status;                        /* 0x004 */
 +      u32 emif_sdram_config;                  /* 0x008 */
 +      u32 emif_lpddr2_nvm_config;             /* 0x00c */
 +      u32 emif_sdram_ref_ctrl;                /* 0x010 */
 +      u32 emif_sdram_ref_ctrl_shdw;           /* 0x014 */
 +      u32 emif_sdram_tim_1;                   /* 0x018 */
 +      u32 emif_sdram_tim_1_shdw;              /* 0x01c */
 +      u32 emif_sdram_tim_2;                   /* 0x020 */
 +      u32 emif_sdram_tim_2_shdw;              /* 0x024 */
 +      u32 emif_sdram_tim_3;                   /* 0x028 */
 +      u32 emif_sdram_tim_3_shdw;              /* 0x02c */
 +      u32 emif_lpddr2_nvm_tim;                /* 0x030 */
 +      u32 emif_lpddr2_nvm_tim_shdw;           /* 0x034 */
 +      u32 emif_pwr_mgmt_ctrl;                 /* 0x038 */
 +      u32 emif_pwr_mgmt_ctrl_shdw;            /* 0x03c */
 +      u32 emif_lpddr2_mode_reg_data;          /* 0x040 */
 +      u32 padding1[1];                        /* 0x044 */
 +      u32 emif_lpddr2_mode_reg_data_es2;      /* 0x048 */
 +      u32 padding11[1];                       /* 0x04c */
 +      u32 emif_lpddr2_mode_reg_cfg;           /* 0x050 */
 +      u32 emif_l3_config;                     /* 0x054 */
 +      u32 emif_l3_cfg_val_1;                  /* 0x058 */
 +      u32 emif_l3_cfg_val_2;                  /* 0x05c */
 +      u32 emif_iodft_tlgc;                    /* 0x060 */
 +      u32 padding2[7];                        /* 0x064 */
 +      u32 emif_perf_cnt_1;                    /* 0x080 */
 +      u32 emif_perf_cnt_2;                    /* 0x084 */
 +      u32 emif_perf_cnt_cfg;                  /* 0x088 */
 +      u32 emif_perf_cnt_sel;                  /* 0x08c */
 +      u32 emif_perf_cnt_tim;                  /* 0x090 */
 +      u32 padding3;                           /* 0x094 */
 +      u32 emif_read_idlectrl;                 /* 0x098 */
 +      u32 emif_read_idlectrl_shdw;            /* 0x09c */
 +      u32 padding4;                           /* 0x0a0 */
 +      u32 emif_irqstatus_raw_sys;             /* 0x0a4 */
 +      u32 emif_irqstatus_raw_ll;              /* 0x0a8 */
 +      u32 emif_irqstatus_sys;                 /* 0x0ac */
 +      u32 emif_irqstatus_ll;                  /* 0x0b0 */
 +      u32 emif_irqenable_set_sys;             /* 0x0b4 */
 +      u32 emif_irqenable_set_ll;              /* 0x0b8 */
 +      u32 emif_irqenable_clr_sys;             /* 0x0bc */
 +      u32 emif_irqenable_clr_ll;              /* 0x0c0 */
 +      u32 padding5;                           /* 0x0c4 */
 +      u32 emif_zq_config;                     /* 0x0c8 */
 +      u32 emif_temp_alert_config;             /* 0x0cc */
 +      u32 emif_l3_err_log;                    /* 0x0d0 */
 +      u32 emif_rd_wr_lvl_rmp_win;             /* 0x0d4 */
 +      u32 emif_rd_wr_lvl_rmp_ctl;             /* 0x0d8 */
 +      u32 emif_rd_wr_lvl_ctl;                 /* 0x0dc */
 +      u32 padding6[1];                        /* 0x0e0 */
 +      u32 emif_ddr_phy_ctrl_1;                /* 0x0e4 */
 +      u32 emif_ddr_phy_ctrl_1_shdw;           /* 0x0e8 */
 +      u32 emif_ddr_phy_ctrl_2;                /* 0x0ec */
 +      u32 padding7[4];                        /* 0x0f0 */
 +      u32 emif_prio_class_serv_map;           /* 0x100 */
 +      u32 emif_connect_id_serv_1_map;         /* 0x104 */
 +      u32 emif_connect_id_serv_2_map;         /* 0x108 */
 +      u32 padding8[5];                        /* 0x10c */
 +      u32 emif_rd_wr_exec_thresh;             /* 0x120 */
-       u32 padding9[6];                        /* 0x124 */
-       u32 emif_ddr_phy_status[21];            /* 0x13c */
-       u32 padding10[27];                      /* 0x1fc */
++      u32 emif_cos_config;                    /* 0x124 */
++      u32 padding9[6];                        /* 0x128 */
++      u32 emif_ddr_phy_status[28];            /* 0x140 */
++      u32 padding10[20];                      /* 0x1b0 */
 +      u32 emif_ddr_ext_phy_ctrl_1;            /* 0x200 */
 +      u32 emif_ddr_ext_phy_ctrl_1_shdw;       /* 0x204 */
 +      u32 emif_ddr_ext_phy_ctrl_2;            /* 0x248 */
 +      u32 emif_ddr_ext_phy_ctrl_2_shdw;       /* 0x24c */
 +      u32 emif_ddr_ext_phy_ctrl_3;            /* 0x200 */
 +      u32 emif_ddr_ext_phy_ctrl_3_shdw;       /* 0x204 */
 +      u32 emif_ddr_ext_phy_ctrl_4;            /* 0x208 */
 +      u32 emif_ddr_ext_phy_ctrl_4_shdw;       /* 0x20c */
 +      u32 emif_ddr_ext_phy_ctrl_5;            /* 0x210 */
 +      u32 emif_ddr_ext_phy_ctrl_5_shdw;       /* 0x214 */
 +      u32 emif_ddr_ext_phy_ctrl_6;            /* 0x218 */
 +      u32 emif_ddr_ext_phy_ctrl_6_shdw;       /* 0x21c */
 +      u32 emif_ddr_ext_phy_ctrl_7;            /* 0x220 */
 +      u32 emif_ddr_ext_phy_ctrl_7_shdw;       /* 0x224 */
 +      u32 emif_ddr_ext_phy_ctrl_8;            /* 0x228 */
 +      u32 emif_ddr_ext_phy_ctrl_8_shdw;       /* 0x22c */
 +      u32 emif_ddr_ext_phy_ctrl_9;            /* 0x230 */
 +      u32 emif_ddr_ext_phy_ctrl_9_shdw;       /* 0x234 */
 +      u32 emif_ddr_ext_phy_ctrl_10;           /* 0x238 */
 +      u32 emif_ddr_ext_phy_ctrl_10_shdw;      /* 0x23c */
 +      u32 emif_ddr_ext_phy_ctrl_11;           /* 0x240 */
 +      u32 emif_ddr_ext_phy_ctrl_11_shdw;      /* 0x244 */
 +      u32 emif_ddr_ext_phy_ctrl_12;           /* 0x248 */
 +      u32 emif_ddr_ext_phy_ctrl_12_shdw;      /* 0x24c */
 +      u32 emif_ddr_ext_phy_ctrl_13;           /* 0x250 */
 +      u32 emif_ddr_ext_phy_ctrl_13_shdw;      /* 0x254 */
 +      u32 emif_ddr_ext_phy_ctrl_14;           /* 0x258 */
 +      u32 emif_ddr_ext_phy_ctrl_14_shdw;      /* 0x25c */
 +      u32 emif_ddr_ext_phy_ctrl_15;           /* 0x260 */
 +      u32 emif_ddr_ext_phy_ctrl_15_shdw;      /* 0x264 */
 +      u32 emif_ddr_ext_phy_ctrl_16;           /* 0x268 */
 +      u32 emif_ddr_ext_phy_ctrl_16_shdw;      /* 0x26c */
 +      u32 emif_ddr_ext_phy_ctrl_17;           /* 0x270 */
 +      u32 emif_ddr_ext_phy_ctrl_17_shdw;      /* 0x274 */
 +      u32 emif_ddr_ext_phy_ctrl_18;           /* 0x278 */
 +      u32 emif_ddr_ext_phy_ctrl_18_shdw;      /* 0x27c */
 +      u32 emif_ddr_ext_phy_ctrl_19;           /* 0x280 */
 +      u32 emif_ddr_ext_phy_ctrl_19_shdw;      /* 0x284 */
 +      u32 emif_ddr_ext_phy_ctrl_20;           /* 0x288 */
 +      u32 emif_ddr_ext_phy_ctrl_20_shdw;      /* 0x28c */
 +      u32 emif_ddr_ext_phy_ctrl_21;           /* 0x290 */
 +      u32 emif_ddr_ext_phy_ctrl_21_shdw;      /* 0x294 */
 +      u32 emif_ddr_ext_phy_ctrl_22;           /* 0x298 */
 +      u32 emif_ddr_ext_phy_ctrl_22_shdw;      /* 0x29c */
 +      u32 emif_ddr_ext_phy_ctrl_23;           /* 0x2a0 */
 +      u32 emif_ddr_ext_phy_ctrl_23_shdw;      /* 0x2a4 */
 +      u32 emif_ddr_ext_phy_ctrl_24;           /* 0x2a8 */
 +      u32 emif_ddr_ext_phy_ctrl_24_shdw;      /* 0x2ac */
-       u32 padding[22];                        /* 0x2b0 */
-       u32 emif_ddr_fifo_misaligned_clear_1;   /* 0x308 */
-       u32 emif_ddr_fifo_misaligned_clear_2;   /* 0x30c */
++      u32 emif_ddr_ext_phy_ctrl_25;           /* 0x2b0 */
++      u32 emif_ddr_ext_phy_ctrl_25_shdw;      /* 0x2b4 */
++      u32 emif_ddr_ext_phy_ctrl_26;           /* 0x2b8 */
++      u32 emif_ddr_ext_phy_ctrl_26_shdw;      /* 0x2bc */
++      u32 emif_ddr_ext_phy_ctrl_27;           /* 0x2c0 */
++      u32 emif_ddr_ext_phy_ctrl_27_shdw;      /* 0x2c4 */
++      u32 emif_ddr_ext_phy_ctrl_28;           /* 0x2c8 */
++      u32 emif_ddr_ext_phy_ctrl_28_shdw;      /* 0x2cc */
++      u32 emif_ddr_ext_phy_ctrl_29;           /* 0x2d0 */
++      u32 emif_ddr_ext_phy_ctrl_29_shdw;      /* 0x2d4 */
++      u32 emif_ddr_ext_phy_ctrl_30;           /* 0x2d8 */
++      u32 emif_ddr_ext_phy_ctrl_30_shdw;      /* 0x2dc */
++      u32 emif_ddr_ext_phy_ctrl_31;           /* 0x2e0 */
++      u32 emif_ddr_ext_phy_ctrl_31_shdw;      /* 0x2e4 */
++      u32 emif_ddr_ext_phy_ctrl_32;           /* 0x2e8 */
++      u32 emif_ddr_ext_phy_ctrl_32_shdw;      /* 0x2ec */
++      u32 emif_ddr_ext_phy_ctrl_33;           /* 0x2f0 */
++      u32 emif_ddr_ext_phy_ctrl_33_shdw;      /* 0x2f4 */
++      u32 emif_ddr_ext_phy_ctrl_34;           /* 0x2f8 */
++      u32 emif_ddr_ext_phy_ctrl_34_shdw;      /* 0x2fc */
++      u32 emif_ddr_ext_phy_ctrl_35;           /* 0x300 */
++      u32 emif_ddr_ext_phy_ctrl_35_shdw;      /* 0x304 */
+       union {
 -              u32 emif_ddr_ext_phy_ctrl_36;
++              u32 emif_ddr_ext_phy_ctrl_36;   /* 0x308 */
+               u32 emif_ddr_fifo_misaligned_clear_1;
+       };
+       union {
 -              u32 emif_ddr_ext_phy_ctrl_36_shdw;
++              u32 emif_ddr_ext_phy_ctrl_36_shdw; /* 0x30c */
+               u32 emif_ddr_fifo_misaligned_clear_2;
+       };
  };
  
  struct dmm_lisa_map_regs {
@@@ -24,14 -24,14 +24,16 @@@ __weak void flush_cache(unsigned long s
  
  #endif /* CONFIG_CPU_ARM1136 */
  
- #ifdef CONFIG_ARM926EJS
+ #ifdef CONFIG_CPU_ARM926EJS
+ #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 -      /* test and clean, page 2-23 of arm926ejs manual */
 -      asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
 -      /* disable write buffer as well (page 2-22) */
 -      asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 +      asm(
 +              /* test and clean, page 2-23 of arm926ejs manual */
 +              "0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n"
 +              /* flush write buffer as well (page 2-22) */
 +              "mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory"
 +              );
  #endif
+ #endif /* CONFIG_CPU_ARM926EJS */
        return;
  }
  
index 9276d3b,0000000..9de3dc5
mode 100644,000000..100644
--- /dev/null
@@@ -1,109 -1,0 +1,142 @@@
-               KEEP(board/karo/tx53/lowlevel_init.o (.text*))
 +/*
 + * (C) Copyright 2012  Lothar Waßmann <LW@KARO-electronics.de>
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 +OUTPUT_ARCH(arm)
 +ENTRY(_start)
 +SECTIONS
 +{
 +      . = 0x00000000;
 +      .text :
 +      {
-       _end = .;
 +              *(.__image_copy_start)
++              *(.vectors)
 +              CPUDIR/start.o (.text*)
++              . = 0x400;
++              KEEP(BOARDDIR/lowlevel_init.o (.text*))
 +              *(.text*)
 +      }
 +
++#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
++
++#ifndef CONFIG_ARMV7_SECURE_BASE
++#define CONFIG_ARMV7_SECURE_BASE
++#endif
++
++      .__secure_start : {
++              . = ALIGN(0x1000);
++              *(.__secure_start)
++      }
++
++      .secure_text CONFIG_ARMV7_SECURE_BASE :
++              AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
++      {
++              *(._secure.text)
++      }
++
++      . = LOADADDR(.__secure_start) +
++              SIZEOF(.__secure_start) +
++              SIZEOF(.secure_text);
++
++      __secure_end_lma = .;
++      .__secure_end : AT(__secure_end_lma) {
++              *(.__secure_end)
++              LONG(0x1d1071c);        /* Must output something to reset LMA */
++      }
++#endif
++
 +      . = ALIGN(4);
 +      .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 +
 +      . = ALIGN(4);
 +      .data : {
 +              *(.data*)
 +      }
 +
 +      . = ALIGN(4);
 +      .u_boot_list : {
 +              KEEP(*(SORT(.u_boot_list*)));
 +      }
 +
 +      . = ALIGN(4);
 +      .image_copy_end :
 +      {
 +              *(.__image_copy_end)
 +      }
 +
 +      .rel_dyn_start :
 +      {
 +              *(.__rel_dyn_start)
 +      }
 +
 +      .rel.dyn :
 +      {
 +              *(.rel*)
 +      }
 +
 +      .rel_dyn_end :
 +      {
 +              *(.__rel_dyn_end)
 +      }
 +
 +      /* Workaround for an apparent bug in i.MX53 ROM Code,
 +       * that skips loading the last block if it doesn't
 +       * end on a 4KiB boundary.
 +       */
++
 +      . = ALIGN(4096);
 +      .uboot_img_end :
 +      {
 +              *(.__uboot_img_end)
 +      }
 +
-  
-       /DISCARD/ : { *(.bss*) }
-       /DISCARD/ : { *(.dynstr*) }
-       /DISCARD/ : { *(.dynsym*) }
-       /DISCARD/ : { *(.dynamic*) }
-       /DISCARD/ : { *(.hash*) }
-       /DISCARD/ : { *(.plt*) }
-       /DISCARD/ : { *(.interp*) }
-       /DISCARD/ : { *(.gnu*) }
++      _image_binary_end = .;
 +
 +/*
 + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
 + * __bss_base and __bss_limit are for linker only (overlay ordering)
 + */
 +
 +      .bss_start __rel_dyn_start (OVERLAY) : {
 +              KEEP(*(.__bss_start));
 +              __bss_base = .;
 +      }
 +
 +      .bss __bss_base (OVERLAY) : {
 +              *(.bss*)
 +              . = ALIGN(4);
 +              __bss_limit = .;
 +      }
 +      .bss_end __bss_limit (OVERLAY) : {
 +              KEEP(*(.__bss_end));
 +      }
++
++      .dynsym _image_binary_end : { *(.dynsym) }
++      .dynbss : { *(.dynbss) }
++      .dynstr : { *(.dynstr*) }
++      .dynamic : { *(.dynamic*) }
++      .plt : { *(.plt*) }
++      .interp : { *(.interp*) }
++      .gnu.hash : { *(.gnu.hash) }
++      .gnu : { *(.gnu*) }
++      .ARM.exidx : { *(.ARM.exidx*) }
++      .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
 +}
diff --cc common/Kconfig
@@@ -226,19 -176,6 +226,20 @@@ config CMD_NAN
        help
          NAND support.
  
 +config CMD_NAND_TRIMFFS
 +      bool "Enable nand write.trimffs command"
 +      help
 +        Enable command to leave page sized runs of 0xff patterns in
 +        erased state rather than overwriting them. This is required
 +        for using NAND flash filesystems on NAND controllers with
 +        a non-0xff ECC code for all 0xff data.
 +
 +config CMD_MMC
 +      bool "mmc/sd"
++      select PARTITIONS
 +      help
 +        MMC/SD support.
 +
  config CMD_SPI
        bool "sspi"
        help
diff --cc common/Makefile
Simple merge
Simple merge
diff --cc common/lcd.c
@@@ -497,11 -260,16 +270,16 @@@ void lcd_clear(void
  #endif
  #endif
        /* Paint the logo and retrieve LCD base address */
 -      debug("[LCD] Drawing the logo...\n");
 +      debug("[LCD] Drawing the logo @ %p...\n", lcd_base);
-       lcd_console_address = lcd_logo();
-       console_col = 0;
-       console_row = 0;
+ #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+       console_rows = (panel_info.vl_row - BMP_LOGO_HEIGHT);
+       console_rows /= VIDEO_FONT_HEIGHT;
+ #else
+       console_rows = panel_info.vl_row / VIDEO_FONT_HEIGHT;
+ #endif
+       console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH;
+       lcd_init_console(lcd_base, console_rows, console_cols);
+       lcd_init_console(lcd_logo(), console_rows, console_cols);
        lcd_sync();
  }
  
@@@ -984,16 -733,13 +768,12 @@@ int lcd_display_bitmap(ulong bmp_image
  
                /* Set color map */
                for (i = 0; i < colors; ++i) {
 -                      bmp_color_table_entry_t cte = bmp->color_table[i];
  #if !defined(CONFIG_ATMEL_LCD)
                        ushort colreg =
 -                              ( ((cte.red)   << 8) & 0xf800) |
 -                              ( ((cte.green) << 3) & 0x07e0) |
 -                              ( ((cte.blue)  >> 3) & 0x001f) ;
 +                              ( ((cte[i].red)   << 8) & 0xf800) |
 +                              ( ((cte[i].green) << 3) & 0x07e0) |
 +                              ( ((cte[i].blue)  >> 3) & 0x001f) ;
- #ifdef CONFIG_SYS_INVERT_COLORS
-                       *cmap = 0xffff - colreg;
- #else
                        *cmap = colreg;
- #endif
  #if defined(CONFIG_MPC823)
                        cmap--;
  #else
Simple merge
@@@ -151,67 -190,11 +190,53 @@@ int gpio_requestf(unsigned gpio, const 
        return gpio_request(gpio, buf);
  }
  
- /**
-  * gpio_free() - [COMPAT] Relinquish GPIO
-  * gpio:      GPIO number
-  *
-  * This function implements the API that's compatible with current
-  * GPIO API used in U-Boot. The request is forwarded to particular
-  * GPIO driver. Returns 0 on success, negative value on error.
-  */
- int gpio_free(unsigned gpio)
 +int gpio_request_one(unsigned int gpio, enum gpio_flags flags,
 +              const char *label)
 +{
 +      int ret;
 +
 +      ret = gpio_request(gpio, label);
 +      if (ret)
 +              return ret;
 +
 +      if (flags == GPIOFLAG_INPUT)
 +              gpio_direction_input(gpio);
 +      else if (flags == GPIOFLAG_OUTPUT_INIT_LOW)
 +              gpio_direction_output(gpio, 0);
 +      else if (flags == GPIOFLAG_OUTPUT_INIT_HIGH)
 +              gpio_direction_output(gpio, 1);
 +
 +      return ret;
 +}
 +
 +int gpio_request_array(const struct gpio *gpios, int count)
 +{
 +      int ret;
 +      int i;
 +
 +      for (i = 0; i < count; i++) {
 +              ret = gpio_request_one(gpios[i].gpio, gpios[i].flags,
 +                              gpios[i].label);
 +              if (ret) {
 +                      printf("Failed to request GPIO%d (%u of %u): %d\n",
 +                              gpios[i].gpio, i, count, ret);
 +                      goto error;
 +              }
 +      }
 +      return 0;
 +
 +error:
 +      while (--i >= 0)
 +              gpio_free(gpios[i].gpio);
 +
 +      return ret;
 +}
 +
+ int _dm_gpio_free(struct udevice *dev, uint offset)
  {
        struct gpio_dev_priv *uc_priv;
-       unsigned int offset;
-       struct udevice *dev;
        int ret;
  
-       ret = gpio_to_device(gpio, &dev, &offset);
-       if (ret)
-               return ret;
        uc_priv = dev->uclass_priv;
        if (!uc_priv->name[offset])
                return -ENXIO;
        return 0;
  }
  
- static int check_reserved(struct udevice *dev, unsigned offset,
-                         const char *func)
 +int gpio_free_array(const struct gpio *gpios, int count)
 +{
 +      int ret = 0;
 +      int i;
 +
 +      for (i = 0; i < count; i++)
 +              ret |= gpio_free(gpios[i].gpio);
 +
 +      return ret;
 +}
 +
+ /**
+  * gpio_free() - [COMPAT] Relinquish GPIO
+  * gpio:      GPIO number
+  *
+  * This function implements the API that's compatible with current
+  * GPIO API used in U-Boot. The request is forwarded to particular
+  * GPIO driver. Returns 0 on success, negative value on error.
+  */
+ int gpio_free(unsigned gpio)
+ {
+       struct gpio_desc desc;
+       int ret;
+       ret = gpio_to_device(gpio, &desc);
+       if (ret)
+               return ret;
+       return _dm_gpio_free(desc.dev, desc.offset);
+ }
+ static int check_reserved(struct gpio_desc *desc, const char *func)
  {
-       struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+       struct gpio_dev_priv *uc_priv = desc->dev->uclass_priv;
  
-       if (!uc_priv->name[offset]) {
+       if (!uc_priv->name[desc->offset]) {
                printf("%s: %s: error: gpio %s%d not reserved\n",
-                      dev->name, func,
-                      uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+                      desc->dev->name, func,
+                      uc_priv->bank_name ? uc_priv->bank_name : "",
+                      desc->offset);
                return -EBUSY;
        }
  
@@@ -1,14 -1,22 +1,36 @@@
+ config DM_I2C
+       bool "Enable Driver Model for I2C drivers"
+       depends on DM
+       help
+         If you want to use driver model for I2C drivers, say Y.
+         To use legacy I2C drivers, say N.
+ config SYS_I2C_UNIPHIER
+       bool "UniPhier I2C driver"
+       depends on ARCH_UNIPHIER && DM_I2C
+       default y
+       help
+         Support for Panasonic UniPhier I2C controller driver.  This I2C
+         controller is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
+ config SYS_I2C_UNIPHIER_F
+       bool "UniPhier FIFO-builtin I2C driver"
+       depends on ARCH_UNIPHIER && DM_I2C
+       default y
+       help
+         Support for Panasonic UniPhier FIFO-builtin I2C controller driver.
+         This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
 +menuconfig SYS_I2C
 +      bool "I2C device support"
 +
 +if SYS_I2C
 +
 +config HARD_I2C
 +      bool
 +
 +config SYS_I2C_MXC
 +      bool "Freescale i.MX I2C controller"
 +      select HARD_I2C
 +      select I2C_QUIRK_REG if FSL_LSCH3 || LS102XA
 +
 +endif
@@@ -1,23 -1,9 +1,29 @@@
- menuconfig MMC
-       bool "MMC/SD device support"
-       select CMD_MMC
+ menu "MMC Host controller Support"
  
- if MMC
++config MMC
++      bool
 +
 +config GENERIC_MMC
 +      bool
++      select MMC
++
+ config SH_SDHI
+       bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
+       depends on RMOBILE
+       help
+         Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
  
- endif
 +config FSL_ESDHC
 +      bool "Freescale ESDHC controller"
 +      select GENERIC_MMC
 +
 +config FSL_USDHC
 +      bool "Support USDHC"
 +      depends on MX6Q
 +      depends on FSL_ESDHC
 +
 +config SUPPORT_EMMC_BOOT
 +      bool "Support boot from eMMC"
 +      depends on MMC
 +
+ endmenu
Simple merge
Simple merge
Simple merge
@@@ -1068,23 -988,9 +1177,24 @@@ int board_nand_init(struct nand_chip *n
  #endif
        if (err)
                return err;
 +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
 +      if (nand->ecc.layout) {
 +              bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
 +              bbt_main_descr.veroffs = bbt_main_descr.offs +
 +                      sizeof(bbt_pattern);
 +
 +              bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
 +              bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
 +                      sizeof(mirror_pattern);
 +      }
 +
 +      nand->bbt_options |= NAND_BBT_USE_FLASH;
 +      nand->bbt_td = &bbt_main_descr;
 +      nand->bbt_md = &bbt_mirror_descr;
 +#endif
  
- #ifdef CONFIG_SPL_BUILD
+ #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
+       /* TODO: Implement for 16-bit bus width */
        if (nand->options & NAND_BUSWIDTH_16)
                nand->read_buf = nand_read_buf16;
        else
Simple merge
   * an error value of -1.
   */
  
 +enum gpio_flags {
 +      GPIOFLAG_INPUT,
 +      GPIOFLAG_OUTPUT_INIT_LOW,
 +      GPIOFLAG_OUTPUT_INIT_HIGH,
 +};
 +
 +struct gpio {
 +      unsigned int gpio;
 +      enum gpio_flags flags;
 +      const char *label;
 +};
 +
  /**
+  * @deprecated        Please use driver model instead
   * Request a GPIO. This should be called before any of the other functions
   * are used on this GPIO.
   *
  int gpio_request(unsigned gpio, const char *label);
  
  /**
+  * @deprecated        Please use driver model instead
 + * Request a GPIO and configure it
 + * @param gpios       pointer to array of gpio defs
 + * @param count       number of GPIOs to set up
 + */
 +int gpio_request_one(unsigned gpio, enum gpio_flags flags, const char *label);
 +
 +/**
 + * Request a set of GPIOs and configure them
 + * @param gpios       pointer to array of gpio defs
 + * @param count       number of GPIOs to set up
 + */
 +int gpio_request_array(const struct gpio *gpios, int count);
 +
 +/**
++ * @deprecated        Please use driver model instead
   * Stop using the GPIO.  This function should not alter pin configuration.
   *
   * @param gpio        GPIO number
  int gpio_free(unsigned gpio);
  
  /**
+  * @deprecated        Please use driver model instead
 + * Release a set of GPIOs
 + * @param gpios       pointer to array of gpio defs
 + * @param count       number of GPIOs to set up
 + */
 +int gpio_free_array(const struct gpio *gpios, int count);
 +
 +/**
++ * @deprecated        Please use driver model instead
   * Make a GPIO an input.
   *
   * @param gpio        GPIO number
index 3f1cd67,0000000..96d82a2
mode 100644,000000..100644
--- /dev/null
@@@ -1,259 -1,0 +1,256 @@@
- #ifdef CONFIG_CMD_MMC
- #ifndef CONFIG_ENV_IS_IN_NAND
- #endif
 +/*
 + * Copyright (C) 2012-2014 <LW@KARO-electronics.de>
 + *
 + * SPDX-License-Identifier:      GPL-2.0
 + *
 + */
 +
 +#ifndef __CONFIG_H
 +#define __CONFIG_H
 +
 +#include <linux/sizes.h>
 +#include <asm/arch/imx-regs.h>
 +
 +/*
 + * Ka-Ro TX53 board - SoC configuration
 + */
 +#define CONFIG_SYS_MX5_IOMUX_V3
 +#define CONFIG_MXC_GPIO                       /* GPIO control */
 +#define CONFIG_SYS_MX5_HCLK           24000000
 +#define CONFIG_SYS_DDR_CLKSEL         0
 +#define CONFIG_SYS_HZ                 1000    /* Ticks per second */
 +#define CONFIG_SHOW_ACTIVITY
 +#define CONFIG_DISPLAY_BOARDINFO
 +#define CONFIG_BOARD_LATE_INIT
 +#define CONFIG_BOARD_EARLY_INIT_F
 +
 +/* LCD Logo and Splash screen support */
 +#define CONFIG_LCD
 +#ifdef CONFIG_LCD
 +#define CONFIG_SPLASH_SCREEN
 +#define CONFIG_SPLASH_SCREEN_ALIGN
 +#define CONFIG_VIDEO_IPUV3
 +#define CONFIG_IPUV3_CLK              200000000
 +#define CONFIG_LCD_LOGO
 +#define LCD_BPP                               LCD_COLOR32
 +#define CONFIG_CMD_BMP
 +#define CONFIG_VIDEO_BMP_RLE8
 +#endif /* CONFIG_LCD */
 +
 +/*
 + * Memory configuration options
 + */
 +#ifndef CONFIG_SYS_SDRAM_SIZE
 +#define CONFIG_SYS_SDRAM_SIZE         (SZ_512M * CONFIG_NR_DRAM_BANKS)
 +#endif
 +
 +#define PHYS_SDRAM_1                  0x70000000      /* Base address of bank 1 */
 +#define PHYS_SDRAM_1_SIZE             (CONFIG_SYS_SDRAM_SIZE / CONFIG_NR_DRAM_BANKS)
 +#if CONFIG_NR_DRAM_BANKS > 1
 +#define PHYS_SDRAM_2                  0xb0000000      /* Base address of bank 2 */
 +#define PHYS_SDRAM_2_SIZE             PHYS_SDRAM_1_SIZE
 +#endif
 +#define CONFIG_STACKSIZE              SZ_128K
 +#define CONFIG_SYS_MALLOC_LEN         SZ_8M
 +#define CONFIG_SYS_MEMTEST_START      PHYS_SDRAM_1    /* Memtest start address */
 +#define CONFIG_SYS_MEMTEST_END                (CONFIG_SYS_MEMTEST_START + SZ_4M)
 +#define CONFIG_SYS_SDRAM_CLK          400
 +
 +/*
 + * U-Boot general configurations
 + */
 +#define CONFIG_SYS_LONGHELP
 +#define CONFIG_SYS_PROMPT             "TX53 U-Boot > "
 +#define CONFIG_SYS_CBSIZE             2048    /* Console I/O buffer size */
 +#define CONFIG_SYS_PBSIZE \
 +      (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 +                                              /* Print buffer size */
 +#define CONFIG_SYS_MAXARGS            256     /* Max number of command args */
 +#define CONFIG_SYS_BARGSIZE           CONFIG_SYS_CBSIZE
 +                                              /* Boot argument buffer size */
 +#define CONFIG_VERSION_VARIABLE                       /* U-BOOT version */
 +#define CONFIG_AUTO_COMPLETE                  /* Command auto complete */
 +#define CONFIG_CMDLINE_EDITING                        /* Command history etc */
 +
 +#define CONFIG_SYS_64BIT_VSPRINTF
 +
 +/*
 + * Flattened Device Tree (FDT) support
 +*/
 +
 +/*
 + * Boot Linux
 + */
 +#define xstr(s)                               str(s)
 +#define str(s)                                #s
 +#define __pfx(x, s)                   (x##s)
 +#define _pfx(x, s)                    __pfx(x, s)
 +
 +#define CONFIG_CMDLINE_TAG
 +#define CONFIG_SETUP_MEMORY_TAGS
 +#define CONFIG_BOOTDELAY              3
 +#define CONFIG_ZERO_BOOTDELAY_CHECK
 +#define CONFIG_SYS_AUTOLOAD           "no"
 +#define CONFIG_BOOTFILE                       "uImage"
 +#define CONFIG_BOOTARGS                       "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
 +#define CONFIG_BOOTCOMMAND            "run bootcmd_${boot_mode} bootm_cmd"
 +#define CONFIG_LOADADDR                       78000000
 +#define CONFIG_FDTADDR                        71000000
 +#define CONFIG_SYS_LOAD_ADDR          _pfx(0x, CONFIG_LOADADDR)
 +#define CONFIG_SYS_FDT_ADDR           _pfx(0x, CONFIG_FDTADDR)
 +#define CONFIG_U_BOOT_IMG_SIZE                SZ_1M
 +#ifndef CONFIG_SYS_LVDS_IF
 +#define DEFAULT_VIDEO_MODE            "VGA"
 +#else
 +#define DEFAULT_VIDEO_MODE            "HSD100PXN1"
 +#endif
 +
 +/*
 + * Extra Environment Settings
 + */
 +#define CONFIG_EXTRA_ENV_SETTINGS                                     \
 +      "autostart=no\0"                                                \
 +      "baseboard=stk5-v3\0"                                           \
 +      "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}"  \
 +      " root=/dev/mtdblock3 rootfstype=jffs2\0"                       \
 +      "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}"    \
 +      " root=/dev/mmcblk0p2 rootwait\0"                               \
 +      "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}"    \
 +      " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock"        \
 +      " ip=dhcp\0"                                                    \
 +      "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}"  \
 +      " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0"           \
 +      "bootcmd_jffs2=set autostart no;run bootargs_jffs2"             \
 +      ";nboot linux\0"                                                \
 +      "bootcmd_mmc=set autostart no;run bootargs_mmc"                 \
 +      ";fatload mmc 0 ${loadaddr} uImage\0"                           \
 +      "bootcmd_nand=set autostart no;run bootargs_ubifs"              \
 +      ";nboot linux\0"                                                \
 +      "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs"   \
 +      ";dhcp\0"                                                       \
 +      "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0"                    \
 +      "boot_mode=nand\0"                                              \
 +      "cpu_clk=800\0"                                                 \
 +      "default_bootargs=set bootargs " CONFIG_BOOTARGS                \
 +      " ${append_bootargs}\0"                                         \
 +      "fdtaddr=" xstr(CONFIG_FDTADDR) "\0"                            \
 +      "fdtsave=fdt resize;nand erase.part dtb"                        \
 +      ";nand write ${fdtaddr} dtb ${fdtsize}\0"                       \
 +      "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 +      "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 +      "nfsroot=/tftpboot/rootfs\0"                                    \
 +      "otg_mode=device\0"                                             \
 +      "touchpanel=tsc2007\0"                                          \
 +      "video_mode=" DEFAULT_VIDEO_MODE "\0"
 +
 +#define MTD_NAME                      "mxc_nand"
 +#define MTDIDS_DEFAULT                        "nand0=" MTD_NAME
 +
 +/*
 + * U-Boot Commands
 + */
 +#include <config_cmd_default.h>
 +
 +/*
 + * Serial Driver
 + */
 +#define CONFIG_MXC_UART
 +#define CONFIG_MXC_UART_BASE          UART1_BASE
 +#define CONFIG_BAUDRATE                       115200          /* Default baud rate */
 +#define CONFIG_SYS_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, }
 +#define CONFIG_SYS_CONSOLE_INFO_QUIET
 +
 +/*
 + * GPIO driver
 + */
 +#define CONFIG_MXC_GPIO
 +
 +/*
 + * Ethernet Driver
 + */
 +#ifdef CONFIG_FEC_MXC
 +#define IMX_FEC_BASE                  FEC_BASE_ADDR
 +#define CONFIG_FEC_XCV_TYPE           MII100
 +#define CONFIG_CMD_MII
 +/* Add for working with "strict" DHCP server */
 +#define CONFIG_BOOTP_SUBNETMASK
 +#define CONFIG_BOOTP_GATEWAY
 +#define CONFIG_BOOTP_DNS
 +#endif
 +
 +/*
 + * I2C Configs
 + */
 +#ifdef CONFIG_CMD_I2C
 +#define CONFIG_I2C_MXC
 +#define CONFIG_SYS_I2C_BASE           I2C1_BASE_ADDR
 +#define CONFIG_SYS_I2C_MX6_PORT1
 +#define CONFIG_SYS_I2C_SPEED          400000
 +#define CONFIG_SYS_I2C_SLAVE          0x34
 +#endif
 +
 +/*
 + * NAND flash driver
 + */
 +#ifdef CONFIG_CMD_NAND
 +#define CONFIG_MXC_NAND_REGS_BASE     NFC_BASE_ADDR_AXI
 +#define CONFIG_MXC_NAND_IP_REGS_BASE  NFC_BASE_ADDR
 +#define CONFIG_MXC_NAND_HWECC
 +#define CONFIG_SYS_NAND_MAX_CHIPS     0x1
 +#define CONFIG_SYS_MAX_NAND_DEVICE    0x1
 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 +#ifdef CONFIG_ENV_IS_IN_NAND
 +#define CONFIG_ENV_OVERWRITE
 +#define CONFIG_ENV_OFFSET             CONFIG_U_BOOT_IMG_SIZE
 +#define CONFIG_ENV_SIZE                       0x20000 /* 128 KiB */
 +#define CONFIG_ENV_RANGE              0x60000
 +#endif
 +#define CONFIG_SYS_NAND_BASE          0x00000000
 +#endif /* CONFIG_CMD_NAND */
 +
 +/*
 + * MMC Driver
 + */
- #define CONFIG_DOS_PARTITION
++#ifdef CONFIG_FSL_ESDHC
 +#define CONFIG_SYS_FSL_ESDHC_ADDR     0
 +
 +#define CONFIG_CMD_FAT
 +#define CONFIG_FAT_WRITE
 +#define CONFIG_CMD_EXT2
 +
 +/*
 + * Environments on MMC
 + */
 +#ifdef CONFIG_ENV_IS_IN_MMC
 +#define CONFIG_SYS_MMC_ENV_DEV                0
 +#define CONFIG_ENV_OVERWRITE
 +/* Associated with the MMC layout defined in mmcops.c */
 +#define CONFIG_ENV_OFFSET             SZ_1K
 +#define CONFIG_ENV_SIZE                       (SZ_128K - CONFIG_ENV_OFFSET)
 +#define CONFIG_DYNAMIC_MMC_DEVNO
 +#endif /* CONFIG_ENV_IS_IN_MMC */
 +#endif /* CONFIG_CMD_MMC */
 +
 +#ifdef CONFIG_ENV_OFFSET_REDUND
 +#define MTDPARTS_DEFAULT              "mtdparts=" MTD_NAME ":"        \
 +      "1m(u-boot),"                                                   \
 +      xstr(CONFIG_ENV_RANGE)                                          \
 +      "(env),"                                                        \
 +      xstr(CONFIG_ENV_RANGE)                                          \
 +      "(env2),6m(linux),32m(rootfs),89344k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
 +#else
 +#define MTDPARTS_DEFAULT              "mtdparts=" MTD_NAME ":"        \
 +      "1m(u-boot),"                                                   \
 +      xstr(CONFIG_ENV_RANGE)                                          \
 +      "(env),6m(linux),32m(rootfs),89728k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
 +#endif
 +
 +#define CONFIG_SYS_SDRAM_BASE         PHYS_SDRAM_1
 +#define CONFIG_SYS_INIT_SP_ADDR               (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 +                                      GENERATED_GBL_DATA_SIZE)
 +
 +#ifdef CONFIG_CMD_IIM
 +#define CONFIG_FSL_IIM
 +#endif
 +
 +#endif /* __CONFIG_H */
diff --cc include/lcd.h
Simple merge
diff --cc include/net.h
Simple merge
Simple merge
diff --cc net/Makefile
@@@ -7,8 -7,8 +7,9 @@@
  
  #ccflags-y += -DDEBUG
  
+ obj-y += checksum.o
  obj-$(CONFIG_CMD_NET)  += arp.o
 +obj-$(CONFIG_CMD_BOOTCE) += bootme.o
  obj-$(CONFIG_CMD_NET)  += bootp.o
  obj-$(CONFIG_CMD_CDP)  += cdp.o
  obj-$(CONFIG_CMD_DNS)  += dns.o
diff --cc tools/Makefile
Simple merge