#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
- ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
+ is_cpu_type(MXC_CPU_MX6ULL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
- ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
+ is_cpu_type(MXC_CPU_MX6ULL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
- ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
+ is_cpu_type(MXC_CPU_MX6ULL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
#endif
-#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)
+#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL)
#define MXC_CCM_CCGR2_CSI_OFFSET 2
#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
#else
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
#endif
-#if !defined(CONFIG_SOC_MX6SX) && !defined(CONFIG_SOC_MX6UL)
+#if !defined(CONFIG_SOC_MX6SX) && !(defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL))
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
#endif
#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-#if defined(CONFIG_SOC_MX6SX) || (CONFIG_SOC_MX6UL)
+#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL)
#define MXC_CCM_CCGR2_LCD_OFFSET 28
#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
#define MXC_CCM_CCGR2_PXP_OFFSET 30
#define ARCH_MXC
-#ifdef CONFIG_SOC_MX6UL
+#if defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)
#define CONFIG_SYS_CACHELINE_SIZE 64
#else
#define CONFIG_SYS_CACHELINE_SIZE 32
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
-#elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL))
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00107FFF
#define GPU_ARB_BASE_ADDR 0x01800000
#define GPU_ARB_END_ADDR 0x01803FFF
#define APBH_DMA_ARB_BASE_ADDR 0x01804000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
-#define M4_BOOTROM_BASE_ADDR 0x007F8000
+#define M4_BOOTROM_BASE_ADDR 0x007F8000
#else
#define CAAM_ARB_BASE_ADDR 0x00100000
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || \
+ defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL))
#define GPV2_BASE_ADDR 0x00D00000
#else
#define GPV2_BASE_ADDR 0x00200000
#endif
-#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL))
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
-#elif defined(CONFIG_SOC_MX6UL)
+#elif defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || \
+ defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
/* i.MX6SL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
-#ifdef CONFIG_SOC_MX6UL
+#if defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#else
/* i.MX6SX */
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#endif
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_SOC_MX6UL
+#if defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#elif defined(CONFIG_SOC_MX6SX)
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
- MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
+#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) || \
+ is_cpu_type(MXC_CPU_MX6ULL)) ? \
+ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
-#if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL))
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
struct iomuxc {
-#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL))
u8 reserved[0x4000];
#endif
u32 gpr[14];
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6UL)
+#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL) || \
+ defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
reg_32(ana2);
};
-#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL))
struct fuse_bank4_regs {
reg_32(sjc_resp_low);
reg_32(sjc_resp_high);