arm: socfpga: Enable DWAPB GPIO driver
authorMarek Vasut <marex@denx.de>
Tue, 23 Jun 2015 14:01:28 +0000 (16:01 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 08:32:52 +0000 (10:32 +0200)
Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig
include/configs/socfpga_arria5.h
include/configs/socfpga_cyclone5.h

index dcd5cb3..eb3bf1b 100644 (file)
@@ -9,6 +9,8 @@ CONFIG_SPL=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_DM_SEQ_ALIAS=y
index 190cdae..954c936 100644 (file)
@@ -12,6 +12,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_DM_SEQ_ALIAS=y
index 16bfb7d..19eccc3 100644 (file)
@@ -12,6 +12,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_DM_SEQ_ALIAS=y
index e1cd9cc..3193684 100644 (file)
@@ -23,6 +23,7 @@
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
@@ -30,7 +31,6 @@
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 
index 192cda7..db38de7 100644 (file)
@@ -21,6 +21,7 @@
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
@@ -28,7 +29,6 @@
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */