MPC5200: enable snooping of DMA transactions on XLB even if no PCI

is configured; othrwise DMA accesses aren't cache coherent which
causes for example USB to fail.

diff --git a/CHANGELOG b/CHANGELOG
index becc55cd05abdfc70e08b3764ba88586f05896fb..cbc18d936959f7b75c1770eaa696b257d38f44cd 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,10 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
 Changes since U-Boot 1.1.4:
 ======================================================================
 

+* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
+  is configured; othrwise DMA accesses aren't cache coherent which
+  causes for example USB to fail.
+

 * Some code cleanup
 
 * Fix dbau1x00 boards broken by dbau1550 patch
 * Some code cleanup
 
 * Fix dbau1x00 boards broken by dbau1550 patch

diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index 4a370ffea94c568f66c8527fc8693b01f823ebb7..b7e00b3e244e4147be3811447fa312348419c078 100644 (file)
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -152,6 +152,10 @@ void cpu_init_f (void)
        /* enable timebase */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
 
        /* enable timebase */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
 

+       /* Enable snooping for RAM */
+       *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
+       *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+

 # if defined(CFG_IPBSPEED_133)
        /* Motorola reports IPB should better run at 133 MHz. */
        *(vu_long *)MPC5XXX_ADDECR |= 1;
 # if defined(CFG_IPBSPEED_133)
        /* Motorola reports IPB should better run at 133 MHz. */
        *(vu_long *)MPC5XXX_ADDECR |= 1;

diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 1d903459e0a746a39a9535cd3b13c830b61bf8a1..2f01d5ce996279e675a7e3398f4db5d8fac427f7 100644 (file)
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -135,10 +135,6 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
        *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
        *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 
        *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
        *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 

-       /* Enable snooping for RAM */
-       *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
-       *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
-

        /* Park XLB on PCI */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
        /* Park XLB on PCI */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);