-#if defined(CONFIG_SOC_MX6Q)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c
-#define I2C1_SEL_INPUT_VAL 0
-#endif
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c
-#define I2C1_SEL_INPUT_VAL 1
-#endif
+#if defined(TX6_I2C1_SCL_GPIO) && defined(TX6_I2C1_SDA_GPIO)
+#define SCL_BANK (TX6_I2C1_SCL_GPIO / 32)
+#define SDA_BANK (TX6_I2C1_SDA_GPIO / 32)
+#define SCL_BIT (1 << (TX6_I2C1_SCL_GPIO % 32))
+#define SDA_BIT (1 << (TX6_I2C1_SDA_GPIO % 32))