sunxi_nand_spl: Add proper cache flusing
authorHans de Goede <hdegoede@redhat.com>
Sat, 15 Aug 2015 10:32:24 +0000 (12:32 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 10:19:13 +0000 (12:19 +0200)
We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.

Things are working without this by mostly luck, but lets not rely on that.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
drivers/mtd/nand/sunxi_nand_spl.c

index 147d476..663c03e 100644 (file)
@@ -266,6 +266,10 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
                writel(oob_offset, SUNXI_NFC_BASE + NFC_SPARE_AREA);
        }
 
+       flush_dcache_range(dst,
+                          ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
+                                ARCH_DMA_MINALIGN));
+
        /* SUNXI_DMA */
        writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
        /* read from REG_IO_DATA */
@@ -311,6 +315,10 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
                return;
        }
 
+       invalidate_dcache_range(dst,
+                       ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
+                             ARCH_DMA_MINALIGN));
+
        if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
                (*ecc_errors)++;
 }