karo: merge with Ka-Ro specific tree for secure boot support
authorLothar Waßmann <LW@KARO-electronics.de>
Wed, 4 Mar 2015 12:41:53 +0000 (13:41 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Wed, 4 Mar 2015 12:41:53 +0000 (13:41 +0100)
210 files changed:
1  2 
.gitignore
Kconfig
README
arch/arm/Kconfig
arch/arm/config.mk
arch/arm/cpu/arm926ejs/mxs/mxs.c
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
arch/arm/cpu/arm926ejs/mxs/timer.c
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/cpu/armv7/am33xx/sys_info.c
arch/arm/cpu/armv7/cache_v7.c
arch/arm/cpu/armv7/lowlevel_init.S
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/cpu/armv7/mx5/soc.c
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/imx-common/iomux-v3.c
arch/arm/imx-common/timer.c
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/ddr_defs.h
arch/arm/include/asm/arch-am33xx/gpio.h
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
arch/arm/include/asm/arch-exynos/system.h
arch/arm/include/asm/arch-mx5/clock.h
arch/arm/include/asm/arch-mx5/crm_regs.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx5/sys_proto.h
arch/arm/include/asm/arch-mx6/clock.h
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/sys_proto.h
arch/arm/include/asm/arch-mxs/sys_proto.h
arch/arm/include/asm/emif.h
arch/arm/include/asm/global_data.h
arch/arm/include/asm/imx-common/dma.h
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/system.h
arch/arm/lib/asm-offsets.c
arch/arm/lib/board.c
arch/arm/lib/cache-cp15.c
arch/arm/lib/cache.c
arch/arm/lib/crt0.S
arch/arm/lib/interrupts.c
arch/arm/lib/reset.c
arch/arm/lib/vectors.S
board/boundary/nitrogen6x/nitrogen6x.c
board/congatec/cgtqmx6eval/cgtqmx6eval.c
board/denx/m28evk/spl_boot.c
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/mx6sabresd/mx6sabresd.c
board/karo/common/Makefile
board/karo/common/karo.h
board/karo/common/mmc.c
board/karo/common/nand.c
board/karo/tx28/Kconfig
board/karo/tx28/Makefile
board/karo/tx28/flash.c
board/karo/tx28/tx28.c
board/karo/tx48/Kconfig
board/karo/tx48/Makefile
board/karo/tx48/spl.c
board/karo/tx48/tx48.c
board/karo/tx51/Kconfig
board/karo/tx51/Makefile
board/karo/tx51/tx51.c
board/karo/tx53/Kconfig
board/karo/tx53/Makefile
board/karo/tx53/flash.c
board/karo/tx53/tx53.c
board/karo/tx6/Kconfig
board/karo/tx6/Makefile
board/karo/tx6/config.mk
board/karo/tx6/flash.c
board/karo/tx6/ltc3676.c
board/karo/tx6/pmic.c
board/karo/tx6/pmic.h
board/karo/tx6/rn5t567.c
board/karo/tx6/rn5t618.c
board/karo/tx6/tx6qdl.c
board/karo/tx6/u-boot.lds
board/wandboard/wandboard.c
common/Kconfig
common/Makefile
common/cmd_bootce.c
common/cmd_gpt.c
common/cmd_mmc.c
common/cmd_mtdparts.c
common/cmd_nand.c
common/env_nand.c
common/fdt_support.c
common/lcd.c
common/spl/spl.c
common/spl/spl_nand.c
common/xyzModem.c
configs/tx28-40x1_defconfig
configs/tx28-40x1_noenv_defconfig
configs/tx28-40x2_defconfig
configs/tx28-40x2_noenv_defconfig
configs/tx28-40x3_defconfig
configs/tx28-40x3_noenv_defconfig
configs/tx28-41x0_defconfig
configs/tx28-41x0_noenv_defconfig
configs/tx48_defconfig
configs/tx51-8xx0_defconfig
configs/tx51-8xx1_2_defconfig
configs/tx53-1232_defconfig
configs/tx53-x030_defconfig
configs/tx53-x130_defconfig
configs/tx53-x131_defconfig
configs/tx6q-1020_defconfig
configs/tx6q-1020_mfg_defconfig
configs/tx6q-1020_noenv_defconfig
configs/tx6q-10x0_defconfig
configs/tx6q-10x0_mfg_defconfig
configs/tx6q-10x0_noenv_defconfig
configs/tx6q-11x0_defconfig
configs/tx6q-11x0_mfg_defconfig
configs/tx6q-11x0_noenv_defconfig
configs/tx6s-8034_defconfig
configs/tx6s-8034_mfg_defconfig
configs/tx6s-8034_noenv_defconfig
configs/tx6s-8035_defconfig
configs/tx6s-8035_mfg_defconfig
configs/tx6s-8035_noenv_defconfig
configs/tx6u-8011_defconfig
configs/tx6u-8011_mfg_defconfig
configs/tx6u-8011_noenv_defconfig
configs/tx6u-8012_defconfig
configs/tx6u-8012_mfg_defconfig
configs/tx6u-8012_noenv_defconfig
configs/tx6u-8033_defconfig
configs/tx6u-8033_mfg_defconfig
configs/tx6u-8033_noenv_defconfig
configs/tx6u-80x0_defconfig
configs/tx6u-80x0_mfg_defconfig
configs/tx6u-80x0_noenv_defconfig
configs/tx6u-8111_defconfig
configs/tx6u-8111_mfg_defconfig
configs/tx6u-8111_noenv_defconfig
configs/tx6u-81x0_defconfig
configs/tx6u-81x0_mfg_defconfig
configs/tx6u-81x0_noenv_defconfig
disk/part.c
drivers/dma/Kconfig
drivers/dma/apbh_dma.c
drivers/gpio/Makefile
drivers/gpio/am33xx_gpio.c
drivers/gpio/gpio-uclass.c
drivers/gpio/gpiolib.c
drivers/gpio/mxc_gpio.c
drivers/i2c/Kconfig
drivers/misc/fsl_iim.c
drivers/mmc/Kconfig
drivers/mmc/fsl_esdhc.c
drivers/mmc/mmc.c
drivers/mmc/mxsmmc.c
drivers/mmc/omap_hsmmc.c
drivers/mtd/Kconfig
drivers/mtd/nand/Kconfig
drivers/mtd/nand/mxs_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_spl_simple.c
drivers/mtd/nand/omap_gpmc.c
drivers/net/Kconfig
drivers/net/cpsw.c
drivers/net/fec_mxc.c
drivers/net/fec_mxc.h
drivers/net/phy/Kconfig
drivers/net/phy/phy.c
drivers/net/phy/smsc.c
drivers/serial/serial_mxc.c
drivers/usb/host/ehci-mx6.c
drivers/video/ipu_common.c
drivers/video/ipu_disp.c
drivers/video/ipu_regs.h
drivers/video/mxc_ipuv3_fb.c
drivers/video/mxsfb.c
drivers/watchdog/Kconfig
drivers/watchdog/Makefile
drivers/watchdog/imx_watchdog.c
dts/Kconfig
include/ahci.h
include/asm-generic/gpio.h
include/configs/tx25.h
include/configs/tx28.h
include/configs/tx48.h
include/configs/tx51.h
include/configs/tx53.h
include/configs/tx6.h
include/fsl_esdhc.h
include/ipu.h
include/lcd.h
include/nand.h
include/net.h
include/netdev.h
include/spl.h
net/Makefile
net/bootp.c
net/bootp.h
net/net.c
tools/Makefile

diff --cc .gitignore
Simple merge
diff --cc Kconfig
index 60cf1dd,0000000..3e74c89
mode 100644,000000..100644
--- /dev/null
+++ b/Kconfig
@@@ -1,160 -1,0 +1,159 @@@
-       depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
-       default y
 +#
 +# For a description of the syntax of this configuration file,
 +# see Documentation/kbuild/kconfig-language.txt.
 +#
 +mainmenu "U-Boot $UBOOTVERSION Configuration"
 +
 +config UBOOTVERSION
 +      string
 +      option env="UBOOTVERSION"
 +
 +config KCONFIG_OBJDIR
 +      string
 +      option env="KCONFIG_OBJDIR"
 +
 +menu "General setup"
 +
 +config LOCALVERSION
 +      string "Local version - append to U-Boot release"
 +      depends on !SPL_BUILD
 +      help
 +        Append an extra string to the end of your U-Boot version.
 +        This will show up on your boot log, for example.
 +        The string you set here will be appended after the contents of
 +        any files with a filename matching localversion* in your
 +        object and source tree, in that order.  Your total string can
 +        be a maximum of 64 characters.
 +
 +config LOCALVERSION_AUTO
 +      bool "Automatically append version information to the version string"
 +      depends on !SPL_BUILD
 +      default y
 +      help
 +        This will try to automatically determine if the current tree is a
 +        release tree by looking for git tags that belong to the current
 +        top of tree revision.
 +
 +        A string of the format -gxxxxxxxx will be added to the localversion
 +        if a git-based tree is found.  The string generated by this will be
 +        appended after any matching localversion* files, and after the value
 +        set in CONFIG_LOCALVERSION.
 +
 +        (The actual string used here is the first eight characters produced
 +        by running the command:
 +
 +          $ git rev-parse --verify HEAD
 +
 +        which is done within the script "scripts/setlocalversion".)
 +
 +config CC_OPTIMIZE_FOR_SIZE
 +      bool "Optimize for size"
 +      depends on !SPL_BUILD
 +      default y
 +      help
 +        Enabling this option will pass "-Os" instead of "-O2" to gcc
 +        resulting in a smaller U-Boot image.
 +
 +        This option is enabled by default for U-Boot.
 +
 +menuconfig EXPERT
 +        bool "Configure standard U-Boot features (expert users)"
 +        help
 +          This option allows certain base U-Boot options and settings
 +          to be disabled or tweaked. This is for specialized
 +          environments which can tolerate a "non-standard" U-Boot.
 +          Only use this if you really know what you are doing.
 +
 +endmenu               # General setup
 +
 +menu "Boot images"
 +
 +config SPL_BUILD
 +      bool
++      default y if $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
 +
 +config TPL_BUILD
 +      bool
 +      depends on $KCONFIG_OBJDIR="tpl"
 +      default y
 +
 +config SUPPORT_SPL
 +      bool
 +
 +config SUPPORT_TPL
 +      bool
 +
 +config SPL
 +      bool
 +      depends on SUPPORT_SPL
 +      prompt "Enable SPL" if !SPL_BUILD
 +      default y if SPL_BUILD
 +      help
 +        If you want to build SPL as well as the normal image, say Y.
 +
 +config TPL
 +      bool
 +      depends on SPL && SUPPORT_TPL
 +      prompt "Enable TPL" if !SPL_BUILD
 +      default y if TPL_BUILD
 +      default n
 +      help
 +        If you want to build TPL as well as the normal image and SPL, say Y.
 +
 +config FIT
 +      bool "Support Flattened Image Tree"
 +      depends on !SPL_BUILD
 +      help
 +        This option allows to boot the new uImage structrure,
 +        Flattened Image Tree.  FIT is formally a FDT, which can include
 +        images of various types (kernel, FDT blob, ramdisk, etc.)
 +        in a single blob.  To boot this new uImage structure,
 +        pass the the address of the blob to the "bootm" command.
 +
 +config FIT_VERBOSE
 +      bool "Display verbose messages on FIT boot"
 +      depends on FIT
 +
 +config FIT_SIGNATURE
 +      bool "Enabel signature verification of FIT uImages"
 +      depends on FIT
 +      help
 +        This option enables signature verification of FIT uImages,
 +        using a hash signed and verified using RSA.
 +        See doc/uImage.FIT/signature.txt for more details.
 +
 +config SYS_EXTRA_OPTIONS
 +      string "Extra Options (DEPRECATED)"
 +      depends on !SPL_BUILD
 +      help
 +        The old configuration infrastructure (= mkconfig + boards.cfg)
 +        provided the extra options field. If you have something like
 +        "HAS_BAR,BAZ=64", the optional options
 +          #define CONFIG_HAS
 +          #define CONFIG_BAZ  64
 +        will be defined in include/config.h.
 +        This option was prepared for the smooth migration from the old
 +        configuration to Kconfig. Since this option will be removed sometime,
 +        new boards should not use this option.
 +
 +config SYS_TEXT_BASE
 +      depends on SPARC
 +      hex "Text Base"
 +      help
 +        TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
 +
 +endmenu               # Boot images
 +
 +source "arch/Kconfig"
 +
 +source "common/Kconfig"
 +
 +source "dts/Kconfig"
 +
 +source "net/Kconfig"
 +
 +source "drivers/Kconfig"
 +
 +source "fs/Kconfig"
 +
 +source "lib/Kconfig"
diff --cc README
--- 1/README
--- 2/README
+++ b/README
@@@ -2190,24 -1804,17 +2190,35 @@@ CBFS (Coreboot Filesystem) suppor
                4th and following
                BOOTP requests:         delay 0 ... 8 sec
  
 +              CONFIG_BOOTP_ID_CACHE_SIZE
 +
 +              BOOTP packets are uniquely identified using a 32-bit ID. The
 +              server will copy the ID from client requests to responses and
 +              U-Boot will use this to determine if it is the destination of
 +              an incoming response. Some servers will check that addresses
 +              aren't in use before handing them out (usually using an ARP
 +              ping) and therefore take up to a few hundred milliseconds to
 +              respond. Network congestion may also influence the time it
 +              takes for a response to make it back to the client. If that
 +              time is too long, U-Boot will retransmit requests. In order
 +              to allow earlier responses to still be accepted after these
 +              retransmissions, U-Boot's BOOTP client keeps a small cache of
 +              IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
 +              cache. The default is to keep IDs for up to four outstanding
 +              requests. Increasing this will allow U-Boot to accept offers
 +              from a BOOTP client in networks with unusually high latency.
 +
+ - BOOTP Random transaction ID:
+               CONFIG_BOOTP_RANDOM_ID
+               The standard algorithm to generate a DHCP/BOOTP transaction ID
+               by using the MAC address and the current time stamp may not
+               quite unlikely produce duplicate transaction IDs from different
+               clients in the same network. This option creates a transaction
+               ID using the rand() function. Provided that the RNG has been
+               seeded well, this should guarantee unique transaction IDs
+               always.
  - DHCP Advanced Options:
                You can fine tune the DHCP functionality by defining
                CONFIG_BOOTP_* symbols:
index 5eb1d03,0000000..682f882
mode 100644,000000..100644
--- /dev/null
@@@ -1,989 -1,0 +1,1016 @@@
 +menu "ARM architecture"
 +      depends on ARM
 +
 +config SYS_ARCH
 +      default "arm"
 +
 +config ARM64
 +      bool
 +
 +config HAS_VBAR
 +        bool
 +
 +config CPU_ARM720T
 +        bool
 +
 +config CPU_ARM920T
 +        bool
 +
 +config CPU_ARM926EJS
 +        bool
 +
 +config CPU_ARM946ES
 +        bool
 +
 +config CPU_ARM1136
 +        bool
 +
 +config CPU_ARM1176
 +        bool
 +        select HAS_VBAR
 +
 +config CPU_V7
 +        bool
 +        select HAS_VBAR
 +
 +config CPU_PXA
 +        bool
 +
 +config CPU_SA1100
 +        bool
 +
 +config SYS_CPU
 +        default "arm720t" if CPU_ARM720T
 +        default "arm920t" if CPU_ARM920T
 +        default "arm926ejs" if CPU_ARM926EJS
 +        default "arm946es" if CPU_ARM946ES
 +        default "arm1136" if CPU_ARM1136
 +        default "arm1176" if CPU_ARM1176
 +        default "armv7" if CPU_V7
 +        default "pxa" if CPU_PXA
 +        default "sa1100" if CPU_SA1100
 +      default "armv8" if ARM64
 +
 +choice
 +      prompt "Target select"
 +
 +config TARGET_INTEGRATORAP_CM720T
 +      bool "Support integratorap_cm720t"
 +      select CPU_ARM720T
 +
 +config TARGET_INTEGRATORAP_CM920T
 +      bool "Support integratorap_cm920t"
 +      select CPU_ARM920T
 +
 +config TARGET_INTEGRATORCP_CM920T
 +      bool "Support integratorcp_cm920t"
 +      select CPU_ARM920T
 +
 +config TARGET_A320EVB
 +      bool "Support a320evb"
 +      select CPU_ARM920T
 +
 +config TARGET_AT91RM9200EK
 +      bool "Support at91rm9200ek"
 +      select CPU_ARM920T
 +
 +config TARGET_EB_CPUX9K2
 +      bool "Support eb_cpux9k2"
 +      select CPU_ARM920T
 +
 +config TARGET_CPUAT91
 +      bool "Support cpuat91"
 +      select CPU_ARM920T
 +
 +config TARGET_EDB93XX
 +      bool "Support edb93xx"
 +      select CPU_ARM920T
 +
 +config TARGET_SCB9328
 +      bool "Support scb9328"
 +      select CPU_ARM920T
 +
 +config TARGET_CM4008
 +      bool "Support cm4008"
 +      select CPU_ARM920T
 +
 +config TARGET_CM41XX
 +      bool "Support cm41xx"
 +      select CPU_ARM920T
 +
 +config TARGET_VCMA9
 +      bool "Support VCMA9"
 +      select CPU_ARM920T
 +
 +config TARGET_SMDK2410
 +      bool "Support smdk2410"
 +      select CPU_ARM920T
 +
 +config TARGET_INTEGRATORAP_CM926EJS
 +      bool "Support integratorap_cm926ejs"
 +      select CPU_ARM926EJS
 +
 +config TARGET_INTEGRATORCP_CM926EJS
 +      bool "Support integratorcp_cm926ejs"
 +      select CPU_ARM926EJS
 +
 +config TARGET_ASPENITE
 +      bool "Support aspenite"
 +      select CPU_ARM926EJS
 +
 +config TARGET_GPLUGD
 +      bool "Support gplugd"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AFEB9260
 +      bool "Support afeb9260"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AT91SAM9260EK
 +      bool "Support at91sam9260ek"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AT91SAM9261EK
 +      bool "Support at91sam9261ek"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AT91SAM9263EK
 +      bool "Support at91sam9263ek"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AT91SAM9M10G45EK
 +      bool "Support at91sam9m10g45ek"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AT91SAM9N12EK
 +      bool "Support at91sam9n12ek"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AT91SAM9RLEK
 +      bool "Support at91sam9rlek"
 +      select CPU_ARM926EJS
 +
 +config TARGET_AT91SAM9X5EK
 +      bool "Support at91sam9x5ek"
 +      select CPU_ARM926EJS
 +
 +config TARGET_SNAPPER9260
 +      bool "Support snapper9260"
 +      select CPU_ARM926EJS
 +
 +config TARGET_VL_MA2SC
 +      bool "Support vl_ma2sc"
 +      select CPU_ARM926EJS
 +
 +config TARGET_SBC35_A9G20
 +      bool "Support sbc35_a9g20"
 +      select CPU_ARM926EJS
 +
 +config TARGET_TNY_A9260
 +      bool "Support tny_a9260"
 +      select CPU_ARM926EJS
 +
 +config TARGET_USB_A9263
 +      bool "Support usb_a9263"
 +      select CPU_ARM926EJS
 +
 +config TARGET_ETHERNUT5
 +      bool "Support ethernut5"
 +      select CPU_ARM926EJS
 +
 +config TARGET_MEESC
 +      bool "Support meesc"
 +      select CPU_ARM926EJS
 +
 +config TARGET_OTC570
 +      bool "Support otc570"
 +      select CPU_ARM926EJS
 +
 +config TARGET_CPU9260
 +      bool "Support cpu9260"
 +      select CPU_ARM926EJS
 +
 +config TARGET_PM9261
 +      bool "Support pm9261"
 +      select CPU_ARM926EJS
 +
 +config TARGET_PM9263
 +      bool "Support pm9263"
 +      select CPU_ARM926EJS
 +
 +config TARGET_PM9G45
 +      bool "Support pm9g45"
 +      select CPU_ARM926EJS
 +
 +config TARGET_CORVUS
 +      select SUPPORT_SPL
 +      bool "Support corvus"
 +      select CPU_ARM926EJS
 +
 +config TARGET_TAURUS
 +      select SUPPORT_SPL
 +      bool "Support taurus"
 +      select CPU_ARM926EJS
 +
 +config TARGET_STAMP9G20
 +      bool "Support stamp9g20"
 +      select CPU_ARM926EJS
 +
 +config ARCH_DAVINCI
 +      bool "TI DaVinci"
 +      select CPU_ARM926EJS
 +      help
 +        Support for TI's DaVinci platform.
 +
 +config KIRKWOOD
 +      bool "Marvell Kirkwood"
 +      select CPU_ARM926EJS
 +
 +config TARGET_DB_MV784MP_GP
 +      bool "Support db-mv784mp-gp"
 +      select CPU_V7
 +
 +config TARGET_MAXBCM
 +      bool "Support maxbcm"
 +      select CPU_V7
 +
 +config TARGET_DEVKIT3250
 +      bool "Support devkit3250"
 +      select CPU_ARM926EJS
 +
 +config TARGET_JADECPU
 +      bool "Support jadecpu"
 +      select CPU_ARM926EJS
 +
 +config TARGET_MX25PDK
 +      bool "Support mx25pdk"
 +      select CPU_ARM926EJS
 +
 +config TARGET_TX25
 +      bool "Support tx25"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
++config TARGET_TX28
++      bool "Support tx28"
++      select CPU_ARM926EJS
++      select SUPPORT_SPL
++
++config TARGET_TX48
++      bool "Support tx48"
++      select CPU_V7
++      select SUPPORT_SPL
++
++config TARGET_TX51
++      bool "Support tx51"
++      select CPU_V7
++
++config TARGET_TX53
++      bool "Support tx53"
++      select CPU_V7
++
++config TARGET_TX6
++      bool "Support tx6"
++      select CPU_V7
++
 +config TARGET_ZMX25
 +      bool "Support zmx25"
 +      select CPU_ARM926EJS
 +
 +config TARGET_APF27
 +      bool "Support apf27"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_IMX27LITE
 +      bool "Support imx27lite"
 +      select CPU_ARM926EJS
 +
 +config TARGET_MAGNESIUM
 +      bool "Support magnesium"
 +      select CPU_ARM926EJS
 +
 +config TARGET_APX4DEVKIT
 +      bool "Support apx4devkit"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_XFI3
 +      bool "Support xfi3"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_M28EVK
 +      bool "Support m28evk"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_MX23EVK
 +      bool "Support mx23evk"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_MX28EVK
 +      bool "Support mx28evk"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_MX23_OLINUXINO
 +      bool "Support mx23_olinuxino"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_BG0900
 +      bool "Support bg0900"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_SANSA_FUZE_PLUS
 +      bool "Support sansa_fuze_plus"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config TARGET_SC_SPS_1
 +      bool "Support sc_sps_1"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config ARCH_NOMADIK
 +      bool "ST-Ericsson Nomadik"
 +      select CPU_ARM926EJS
 +
 +config ORION5X
 +      bool "Marvell Orion"
 +      select CPU_ARM926EJS
 +
 +config TARGET_DKB
 +      bool "Support dkb"
 +      select CPU_ARM926EJS
 +
 +config TARGET_SPEAR300
 +      bool "Support spear300"
 +      select CPU_ARM926EJS
 +
 +config TARGET_SPEAR310
 +      bool "Support spear310"
 +      select CPU_ARM926EJS
 +
 +config TARGET_SPEAR320
 +      bool "Support spear320"
 +      select CPU_ARM926EJS
 +
 +config TARGET_SPEAR600
 +      bool "Support spear600"
 +      select CPU_ARM926EJS
 +
 +config TARGET_STV0991
 +      bool "Support stv0991"
 +      select CPU_V7
 +
 +config TARGET_X600
 +      bool "Support x600"
 +      select CPU_ARM926EJS
 +      select SUPPORT_SPL
 +
 +config ARCH_VERSATILE
 +      bool "ARM Ltd. Versatile family"
 +      select CPU_ARM926EJS
 +
 +config TARGET_INTEGRATORCP_CM1136
 +      bool "Support integratorcp_cm1136"
 +      select CPU_ARM1136
 +
 +config TARGET_IMX31_PHYCORE
 +      bool "Support imx31_phycore"
 +      select CPU_ARM1136
 +
 +config TARGET_QONG
 +      bool "Support qong"
 +      select CPU_ARM1136
 +
 +config TARGET_MX31ADS
 +      bool "Support mx31ads"
 +      select CPU_ARM1136
 +
 +config TARGET_MX31PDK
 +      bool "Support mx31pdk"
 +      select CPU_ARM1136
 +      select SUPPORT_SPL
 +
 +config TARGET_TT01
 +      bool "Support tt01"
 +      select CPU_ARM1136
 +
 +config TARGET_IMX31_LITEKIT
 +      bool "Support imx31_litekit"
 +      select CPU_ARM1136
 +
 +config TARGET_WOODBURN
 +      bool "Support woodburn"
 +      select CPU_ARM1136
 +
 +config TARGET_WOODBURN_SD
 +      bool "Support woodburn_sd"
 +      select CPU_ARM1136
 +      select SUPPORT_SPL
 +
 +config TARGET_FLEA3
 +      bool "Support flea3"
 +      select CPU_ARM1136
 +
 +config TARGET_MX35PDK
 +      bool "Support mx35pdk"
 +      select CPU_ARM1136
 +
 +config TARGET_RPI
 +      bool "Support rpi"
 +      select CPU_ARM1176
 +
 +config TARGET_TNETV107X_EVM
 +      bool "Support tnetv107x_evm"
 +      select CPU_ARM1176
 +
 +config TARGET_INTEGRATORAP_CM946ES
 +      bool "Support integratorap_cm946es"
 +      select CPU_ARM946ES
 +
 +config TARGET_INTEGRATORCP_CM946ES
 +      bool "Support integratorcp_cm946es"
 +      select CPU_ARM946ES
 +
 +config TARGET_VEXPRESS_CA15_TC2
 +      bool "Support vexpress_ca15_tc2"
 +      select CPU_V7
 +      select CPU_V7_HAS_NONSEC
 +      select CPU_V7_HAS_VIRT
 +
 +config TARGET_VEXPRESS_CA5X2
 +      bool "Support vexpress_ca5x2"
 +      select CPU_V7
 +
 +config TARGET_VEXPRESS_CA9X4
 +      bool "Support vexpress_ca9x4"
 +      select CPU_V7
 +
 +config TARGET_KWB
 +      bool "Support kwb"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_TSERIES
 +      bool "Support tseries"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_CM_T335
 +      bool "Support cm_t335"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_PEPPER
 +      bool "Support pepper"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_AM335X_IGEP0033
 +      bool "Support am335x_igep0033"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_PCM051
 +      bool "Support pcm051"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_DRACO
 +      bool "Support draco"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_DXR2
 +      bool "Support dxr2"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_PXM2
 +      bool "Support pxm2"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_RUT
 +      bool "Support rut"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_PENGWYN
 +      bool "Support pengwyn"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_AM335X_EVM
 +      bool "Support am335x_evm"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_AM43XX_EVM
 +      bool "Support am43xx_evm"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_TI814X_EVM
 +      bool "Support ti814x_evm"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_TI816X_EVM
 +      bool "Support ti816x_evm"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_SAMA5D3_XPLAINED
 +      bool "Support sama5d3_xplained"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_SAMA5D3XEK
 +      bool "Support sama5d3xek"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_SAMA5D4_XPLAINED
 +      bool "Support sama5d4_xplained"
 +      select CPU_V7
 +
 +config TARGET_SAMA5D4EK
 +      bool "Support sama5d4ek"
 +      select CPU_V7
 +
 +config TARGET_BCM28155_AP
 +      bool "Support bcm28155_ap"
 +      select CPU_V7
 +
 +config TARGET_BCMCYGNUS
 +      bool "Support bcmcygnus"
 +      select CPU_V7
 +
 +config TARGET_BCMNSP
 +      bool "Support bcmnsp"
 +      select CPU_V7
 +
 +config ARCH_EXYNOS
 +      bool "Samsung EXYNOS"
 +      select CPU_V7
 +
 +config ARCH_S5PC1XX
 +      bool "Samsung S5PC1XX"
 +      select CPU_V7
 +
 +config ARCH_HIGHBANK
 +      bool "Calxeda Highbank"
 +      select CPU_V7
 +
 +config ARCH_KEYSTONE
 +      bool "TI Keystone"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_M53EVK
 +      bool "Support m53evk"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_IMA3_MX53
 +      bool "Support ima3-mx53"
 +      select CPU_V7
 +
 +config TARGET_MX51EVK
 +      bool "Support mx51evk"
 +      select CPU_V7
 +
 +config TARGET_MX53ARD
 +      bool "Support mx53ard"
 +      select CPU_V7
 +
 +config TARGET_MX53EVK
 +      bool "Support mx53evk"
 +      select CPU_V7
 +
 +config TARGET_MX53LOCO
 +      bool "Support mx53loco"
 +      select CPU_V7
 +
 +config TARGET_MX53SMD
 +      bool "Support mx53smd"
 +      select CPU_V7
 +
 +config TARGET_MX51_EFIKAMX
 +      bool "Support mx51_efikamx"
 +      select CPU_V7
 +
 +config TARGET_VISION2
 +      bool "Support vision2"
 +      select CPU_V7
 +
 +config TARGET_UDOO
 +      bool "Support udoo"
 +      select CPU_V7
 +
 +config TARGET_WANDBOARD
 +      bool "Support wandboard"
 +      select CPU_V7
 +
 +config TARGET_TITANIUM
 +      bool "Support titanium"
 +      select CPU_V7
 +
 +config TARGET_NITROGEN6X
 +      bool "Support nitrogen6x"
 +      select CPU_V7
 +
 +config TARGET_CGTQMX6EVAL
 +      bool "Support cgtqmx6eval"
 +      select CPU_V7
 +
 +config TARGET_EMBESTMX6BOARDS
 +      bool "Support embestmx6boards"
 +      select CPU_V7
 +
 +config TARGET_ARISTAINETOS
 +      bool "Support aristainetos"
 +      select CPU_V7
 +
 +config TARGET_MX6QARM2
 +      bool "Support mx6qarm2"
 +      select CPU_V7
 +
 +config TARGET_MX6QSABREAUTO
 +      bool "Support mx6qsabreauto"
 +      select CPU_V7
 +
 +config TARGET_MX6SABRESD
 +      bool "Support mx6sabresd"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_MX6SLEVK
 +      bool "Support mx6slevk"
 +      select CPU_V7
 +
 +config TARGET_MX6SXSABRESD
 +      bool "Support mx6sxsabresd"
 +      select CPU_V7
 +
 +config TARGET_GW_VENTANA
 +      bool "Support gw_ventana"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_HUMMINGBOARD
 +      bool "Support hummingboard"
 +      select CPU_V7
 +
 +config TARGET_KOSAGI_NOVENA
 +      bool "Support Kosagi Novena"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_TBS2910
 +      bool "Support tbs2910"
 +      select CPU_V7
 +
 +config TARGET_TQMA6
 +      bool "TQ Systems TQMa6 board"
 +      select CPU_V7
 +
 +config TARGET_OT1200
 +      bool "Bachmann OT1200"
 +      select CPU_V7
 +
 +config OMAP34XX
 +      bool "OMAP34XX SoC"
 +      select CPU_V7
 +
 +config OMAP44XX
 +      bool "OMAP44XX SoC"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config OMAP54XX
 +      bool "OMAP54XX SoC"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config RMOBILE
 +      bool "Renesas ARM SoCs"
 +      select CPU_V7
 +
 +config TARGET_CM_FX6
 +      bool "Support cm_fx6"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_SOCFPGA_CYCLONE5
 +      bool "Support socfpga_cyclone5"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config ARCH_SUNXI
 +      bool "Support sunxi (Allwinner) SoCs"
 +
 +config TARGET_SNOWBALL
 +      bool "Support snowball"
 +      select CPU_V7
 +
 +config TARGET_U8500_HREF
 +      bool "Support u8500_href"
 +      select CPU_V7
 +
 +config TARGET_VF610TWR
 +      bool "Support vf610twr"
 +      select CPU_V7
 +
 +config ZYNQ
 +      bool "Xilinx Zynq Platform"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TEGRA
 +      bool "NVIDIA Tegra"
 +      select SUPPORT_SPL
 +      select SPL
 +      select OF_CONTROL if !SPL_BUILD
 +      select CPU_ARM720T if SPL_BUILD
 +      select CPU_V7 if !SPL_BUILD
 +
 +config TARGET_VEXPRESS_AEMV8A
 +      bool "Support vexpress_aemv8a"
 +      select ARM64
 +
 +config TARGET_LS2085A_EMU
 +      bool "Support ls2085a_emu"
 +      select ARM64
 +
 +config TARGET_LS2085A_SIMU
 +      bool "Support ls2085a_simu"
 +      select ARM64
 +
 +config TARGET_LS1021AQDS
 +      bool "Support ls1021aqds"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_LS1021ATWR
 +      bool "Support ls1021atwr"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +
 +config TARGET_BALLOON3
 +      bool "Support balloon3"
 +      select CPU_PXA
 +
 +config TARGET_H2200
 +      bool "Support h2200"
 +      select CPU_PXA
 +
 +config TARGET_PALMLD
 +      bool "Support palmld"
 +      select CPU_PXA
 +
 +config TARGET_PALMTC
 +      bool "Support palmtc"
 +      select CPU_PXA
 +
 +config TARGET_PALMTREO680
 +      bool "Support palmtreo680"
 +      select CPU_PXA
 +      select SUPPORT_SPL
 +
 +config TARGET_PXA255_IDP
 +      bool "Support pxa255_idp"
 +      select CPU_PXA
 +
 +config TARGET_TRIZEPSIV
 +      bool "Support trizepsiv"
 +      select CPU_PXA
 +
 +config TARGET_VPAC270
 +      bool "Support vpac270"
 +      select CPU_PXA
 +      select SUPPORT_SPL
 +
 +config TARGET_XAENIAX
 +      bool "Support xaeniax"
 +      select CPU_PXA
 +
 +config TARGET_ZIPITZ2
 +      bool "Support zipitz2"
 +      select CPU_PXA
 +
 +config TARGET_LP8X4X
 +      bool "Support lp8x4x"
 +      select CPU_PXA
 +
 +config TARGET_COLIBRI_PXA270
 +      bool "Support colibri_pxa270"
 +      select CPU_PXA
 +
 +config TARGET_JORNADA
 +      bool "Support jornada"
 +      select CPU_SA1100
 +
 +config ARCH_UNIPHIER
 +      bool "Panasonic UniPhier platform"
 +      select CPU_V7
 +      select SUPPORT_SPL
 +      select SPL
 +      select OF_CONTROL if !SPL_BUILD
 +
 +endchoice
 +
 +source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
 +
 +source "arch/arm/cpu/armv7/exynos/Kconfig"
 +
 +source "arch/arm/cpu/armv7/highbank/Kconfig"
 +
 +source "arch/arm/cpu/armv7/keystone/Kconfig"
 +
 +source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
 +
 +source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
 +
 +source "arch/arm/cpu/armv7/omap3/Kconfig"
 +
 +source "arch/arm/cpu/armv7/omap4/Kconfig"
 +
 +source "arch/arm/cpu/armv7/omap5/Kconfig"
 +
 +source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
 +
 +source "arch/arm/cpu/armv7/rmobile/Kconfig"
 +
 +source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
 +
 +source "arch/arm/cpu/armv7/tegra-common/Kconfig"
 +
 +source "arch/arm/cpu/armv7/uniphier/Kconfig"
 +
 +source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
 +
 +source "arch/arm/cpu/armv7/zynq/Kconfig"
 +
 +source "arch/arm/cpu/armv7/Kconfig"
 +
 +source "board/aristainetos/Kconfig"
 +source "board/BuR/kwb/Kconfig"
 +source "board/BuR/tseries/Kconfig"
 +source "board/BuS/eb_cpux9k2/Kconfig"
 +source "board/BuS/vl_ma2sc/Kconfig"
 +source "board/CarMediaLab/flea3/Kconfig"
 +source "board/Marvell/aspenite/Kconfig"
 +source "board/Marvell/db-mv784mp-gp/Kconfig"
 +source "board/Marvell/dkb/Kconfig"
 +source "board/Marvell/gplugd/Kconfig"
 +source "board/afeb9260/Kconfig"
 +source "board/altera/socfpga/Kconfig"
 +source "board/armadeus/apf27/Kconfig"
 +source "board/armltd/integrator/Kconfig"
 +source "board/armltd/vexpress/Kconfig"
 +source "board/armltd/vexpress64/Kconfig"
 +source "board/atmel/at91rm9200ek/Kconfig"
 +source "board/atmel/at91sam9260ek/Kconfig"
 +source "board/atmel/at91sam9261ek/Kconfig"
 +source "board/atmel/at91sam9263ek/Kconfig"
 +source "board/atmel/at91sam9m10g45ek/Kconfig"
 +source "board/atmel/at91sam9n12ek/Kconfig"
 +source "board/atmel/at91sam9rlek/Kconfig"
 +source "board/atmel/at91sam9x5ek/Kconfig"
 +source "board/atmel/sama5d3_xplained/Kconfig"
 +source "board/atmel/sama5d3xek/Kconfig"
 +source "board/atmel/sama5d4_xplained/Kconfig"
 +source "board/atmel/sama5d4ek/Kconfig"
 +source "board/bachmann/ot1200/Kconfig"
 +source "board/balloon3/Kconfig"
 +source "board/barco/titanium/Kconfig"
 +source "board/bluegiga/apx4devkit/Kconfig"
 +source "board/bluewater/snapper9260/Kconfig"
 +source "board/boundary/nitrogen6x/Kconfig"
 +source "board/broadcom/bcm28155_ap/Kconfig"
 +source "board/broadcom/bcmcygnus/Kconfig"
 +source "board/broadcom/bcmnsp/Kconfig"
 +source "board/calao/sbc35_a9g20/Kconfig"
 +source "board/calao/tny_a9260/Kconfig"
 +source "board/calao/usb_a9263/Kconfig"
 +source "board/cirrus/edb93xx/Kconfig"
 +source "board/cm4008/Kconfig"
 +source "board/cm41xx/Kconfig"
 +source "board/compulab/cm_t335/Kconfig"
 +source "board/compulab/cm_fx6/Kconfig"
 +source "board/congatec/cgtqmx6eval/Kconfig"
 +source "board/creative/xfi3/Kconfig"
 +source "board/davedenx/qong/Kconfig"
 +source "board/denx/m28evk/Kconfig"
 +source "board/denx/m53evk/Kconfig"
 +source "board/egnite/ethernut5/Kconfig"
 +source "board/embest/mx6boards/Kconfig"
 +source "board/esd/meesc/Kconfig"
 +source "board/esd/otc570/Kconfig"
 +source "board/esg/ima3-mx53/Kconfig"
 +source "board/eukrea/cpu9260/Kconfig"
 +source "board/eukrea/cpuat91/Kconfig"
 +source "board/faraday/a320evb/Kconfig"
 +source "board/freescale/ls2085a/Kconfig"
 +source "board/freescale/ls1021aqds/Kconfig"
 +source "board/freescale/ls1021atwr/Kconfig"
 +source "board/freescale/mx23evk/Kconfig"
 +source "board/freescale/mx25pdk/Kconfig"
 +source "board/freescale/mx28evk/Kconfig"
 +source "board/freescale/mx31ads/Kconfig"
 +source "board/freescale/mx31pdk/Kconfig"
 +source "board/freescale/mx35pdk/Kconfig"
 +source "board/freescale/mx51evk/Kconfig"
 +source "board/freescale/mx53ard/Kconfig"
 +source "board/freescale/mx53evk/Kconfig"
 +source "board/freescale/mx53loco/Kconfig"
 +source "board/freescale/mx53smd/Kconfig"
 +source "board/freescale/mx6qarm2/Kconfig"
 +source "board/freescale/mx6qsabreauto/Kconfig"
 +source "board/freescale/mx6sabresd/Kconfig"
 +source "board/freescale/mx6slevk/Kconfig"
 +source "board/freescale/mx6sxsabresd/Kconfig"
 +source "board/freescale/vf610twr/Kconfig"
 +source "board/gateworks/gw_ventana/Kconfig"
 +source "board/genesi/mx51_efikamx/Kconfig"
 +source "board/gumstix/pepper/Kconfig"
 +source "board/h2200/Kconfig"
 +source "board/hale/tt01/Kconfig"
 +source "board/icpdas/lp8x4x/Kconfig"
 +source "board/imx31_phycore/Kconfig"
 +source "board/isee/igep0033/Kconfig"
 +source "board/jornada/Kconfig"
 +source "board/karo/tx25/Kconfig"
++source "board/karo/tx28/Kconfig"
++source "board/karo/tx48/Kconfig"
++source "board/karo/tx51/Kconfig"
++source "board/karo/tx53/Kconfig"
++source "board/karo/tx6/Kconfig"
 +source "board/kosagi/novena/Kconfig"
 +source "board/logicpd/imx27lite/Kconfig"
 +source "board/logicpd/imx31_litekit/Kconfig"
 +source "board/maxbcm/Kconfig"
 +source "board/mpl/vcma9/Kconfig"
 +source "board/olimex/mx23_olinuxino/Kconfig"
 +source "board/palmld/Kconfig"
 +source "board/palmtc/Kconfig"
 +source "board/palmtreo680/Kconfig"
 +source "board/phytec/pcm051/Kconfig"
 +source "board/ppcag/bg0900/Kconfig"
 +source "board/pxa255_idp/Kconfig"
 +source "board/raspberrypi/rpi/Kconfig"
 +source "board/ronetix/pm9261/Kconfig"
 +source "board/ronetix/pm9263/Kconfig"
 +source "board/ronetix/pm9g45/Kconfig"
 +source "board/samsung/smdk2410/Kconfig"
 +source "board/sandisk/sansa_fuze_plus/Kconfig"
 +source "board/scb9328/Kconfig"
 +source "board/schulercontrol/sc_sps_1/Kconfig"
 +source "board/siemens/corvus/Kconfig"
 +source "board/siemens/draco/Kconfig"
 +source "board/siemens/pxm2/Kconfig"
 +source "board/siemens/rut/Kconfig"
 +source "board/siemens/taurus/Kconfig"
 +source "board/silica/pengwyn/Kconfig"
 +source "board/solidrun/hummingboard/Kconfig"
 +source "board/spear/spear300/Kconfig"
 +source "board/spear/spear310/Kconfig"
 +source "board/spear/spear320/Kconfig"
 +source "board/spear/spear600/Kconfig"
 +source "board/spear/x600/Kconfig"
 +source "board/st-ericsson/snowball/Kconfig"
 +source "board/st-ericsson/u8500/Kconfig"
 +source "board/st/stv0991/Kconfig"
 +source "board/sunxi/Kconfig"
 +source "board/syteco/jadecpu/Kconfig"
 +source "board/syteco/zmx25/Kconfig"
 +source "board/taskit/stamp9g20/Kconfig"
 +source "board/tbs/tbs2910/Kconfig"
 +source "board/ti/am335x/Kconfig"
 +source "board/ti/am43xx/Kconfig"
 +source "board/ti/ti814x/Kconfig"
 +source "board/ti/ti816x/Kconfig"
 +source "board/ti/tnetv107xevm/Kconfig"
 +source "board/timll/devkit3250/Kconfig"
 +source "board/toradex/colibri_pxa270/Kconfig"
 +source "board/tqc/tqma6/Kconfig"
 +source "board/trizepsiv/Kconfig"
 +source "board/ttcontrol/vision2/Kconfig"
 +source "board/udoo/Kconfig"
 +source "board/vpac270/Kconfig"
 +source "board/wandboard/Kconfig"
 +source "board/woodburn/Kconfig"
 +source "board/xaeniax/Kconfig"
 +source "board/zipitz2/Kconfig"
 +
 +source "arch/arm/Kconfig.debug"
 +
 +endmenu
@@@ -39,20 -36,10 +39,20 @@@ endi
  
  # Only test once
  ifneq ($(CONFIG_SPL_BUILD),y)
 -ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb
 +ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
 +archprepare: checkthumb
 +
 +checkthumb:
 +      @if test "$(call cc-version)" -lt "0404"; then \
 +              echo -n '*** Your GCC does not produce working '; \
 +              echo 'binaries in THUMB mode.'; \
 +              echo '*** Your board is configured for THUMB mode.'; \
 +              false; \
 +      fi
 +endif
  endif
  
- # Try if EABI is supported, else fall back to old API,
+ # Try if EABI is supported, else fall back to old ABI,
  # i. e. for example:
  # - with ELDK 4.2 (EABI supported), use:
  #     -mabi=aapcs-linux
@@@ -77,17 -109,12 +109,21 @@@ void enable_caches(void
  void mx28_fixup_vt(uint32_t start_addr)
  {
        /* ldr pc, [pc, #0x18] */
-       const uint32_t ldr_pc = 0xe59ff018;
        /* Jumptable location is 0x0 */
-       uint32_t *vt = (uint32_t *)0x0;
-       int i;
+       uint32_t *vt = (uint32_t *)0x20;
+       uint32_t cr = get_cr();
  
++<<<<<<< HEAD
 +      for (i = 0; i < 8; i++) {
 +              /* cppcheck-suppress nullPointer */
 +              vt[i] = ldr_pc;
 +              /* cppcheck-suppress nullPointer */
 +              vt[i + 8] = start_addr + (4 * i);
 +      }
++=======
+       memcpy(vt, (void *)start_addr + 0x20, 32);
+       set_cr(cr & ~CR_V);
++>>>>>>> karo-tx-uboot
  }
  
  #ifdef        CONFIG_ARCH_MISC_INIT
Simple merge
  
  #include "mxs_init.h"
  
+ #ifdef CONFIG_SYS_SPL_VDDD_VAL
+ #define VDDD_VAL      CONFIG_SYS_SPL_VDDD_VAL
+ #else
+ #define VDDD_VAL      1350
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDIO_VAL
+ #define VDDIO_VAL     CONFIG_SYS_SPL_VDDIO_VAL
+ #else
+ #define VDDIO_VAL     3300
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDA_VAL
+ #define VDDA_VAL      CONFIG_SYS_SPL_VDDA_VAL
+ #else
+ #define VDDA_VAL      1800
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
+ #define VDDMEM_VAL    CONFIG_SYS_SPL_VDDMEM_VAL
+ #else
+ #define VDDMEM_VAL    1700
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
+ #define VDDD_BO_VAL   CONFIG_SYS_SPL_VDDD_BO_VAL
+ #else
+ #define VDDD_BO_VAL   150
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
+ #define VDDIO_BO_VAL  CONFIG_SYS_SPL_VDDIO_BO_VAL
+ #else
+ #define VDDIO_BO_VAL  150
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
+ #define VDDA_BO_VAL   CONFIG_SYS_SPL_VDDA_BO_VAL
+ #else
+ #define VDDA_BO_VAL   175
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
+ #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
+ #else
+ #define VDDMEM_BO_VAL 25
+ #endif
+ #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
+ #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
+ #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
+ #endif
+ #define BATT_BO_VAL   (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
+ #else
+ /* Brownout default at 3V */
+ #define BATT_BO_VAL   ((3000 - 2400) / 40)
+ #endif
+ #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
+ static const int fixed_batt_supply = 1;
+ #else
+ static const int fixed_batt_supply;
+ #endif
+ static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 +/**
 + * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
 + *
 + * This function switches the CPU core clock from PLL to 24MHz XTAL
 + * oscilator. This is necessary if the PLL is being reconfigured to
 + * prevent crash of the CPU core.
 + */
  static void mxs_power_clock2xtal(void)
  {
        struct mxs_clkctrl_regs *clkctrl_regs =
@@@ -50,56 -96,49 +110,63 @@@ static void mxs_power_clock2pll(void
                        CLKCTRL_CLKSEQ_BYPASS_CPU);
  }
  
- static void mxs_power_set_auto_restart(void)
+ static int mxs_power_wait_rtc_stat(u32 mask)
+ {
+       int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
+       u32 val;
+       struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
+       while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
+               early_delay(1);
+               if (timeout-- < 0)
+                       break;
+       }
+       return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
+ }
 +/**
 + * mxs_power_set_auto_restart() - Set the auto-restart bit
 + *
 + * This function ungates the RTC block and sets the AUTO_RESTART
 + * bit to work around a design bug on MX28EVK Rev. A .
 + */
+ static int mxs_power_set_auto_restart(int on)
  {
-       struct mxs_rtc_regs *rtc_regs =
-               (struct mxs_rtc_regs *)MXS_RTC_BASE;
-       writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
-       while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
-               ;
+       struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
  
-       writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
-       while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
-               ;
 -      /*
 -       * Due to the hardware design bug of mx28 EVK-A
 -       * we need to set the AUTO_RESTART bit.
 -       */
+       if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
+               return 1;
  
-               return;
 +      /* Do nothing if flag already set */
 +      if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
-       while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
-               ;
++              return 0;
 +
+       if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
+                               RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
+               return 0;
  
-       setbits_le32(&rtc_regs->hw_rtc_persistent0,
-                       RTC_PERSISTENT0_AUTO_RESTART);
-       writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
-       writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
-       while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
-               ;
-       while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
-               ;
+       if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+               return 1;
+       clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
+                       !on * RTC_PERSISTENT0_AUTO_RESTART,
+                       !!on * RTC_PERSISTENT0_AUTO_RESTART);
+       if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+               return 1;
+       return 0;
  }
  
 +/**
 + * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
 + *
 + * This function configures the VDDIO, VDDA and VDDD linear regulators output
 + * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
 + * converter. This is the recommended setting for the case where we use both
 + * linear regulators and DC-DC converter to power the VDDIO rail.
 + */
  static void mxs_power_set_linreg(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        /* Set linear regulator 25mV below switching converter */
        clrsetbits_le32(&power_regs->hw_power_vdddctrl,
                        POWER_VDDDCTRL_LINREG_OFFSET_MASK,
                        POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
  }
  
 +/**
 + * mxs_get_batt_volt() - Measure battery input voltage
 + *
 + * This function retrieves the battery input voltage and returns it.
 + */
  static int mxs_get_batt_volt(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t volt = readl(&power_regs->hw_power_battmonitor);
        volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
        volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
        volt *= 8;
@@@ -141,17 -168,8 +207,15 @@@ static int mxs_is_batt_ready(void
        return (mxs_get_batt_volt() >= 3600);
  }
  
 +/**
 + * mxs_is_batt_good() - Test if battery is operational at all
 + *
 + * This function starts recharging the battery and tests if the input current
 + * provided by the 5V input recharging the battery is also sufficient to power
 + * the DC-DC converter.
 + */
  static int mxs_is_batt_good(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t volt = mxs_get_batt_volt();
  
        if ((volt >= 2400) && (volt <= 4300))
        return 0;
  }
  
 +/**
 + * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
 + *
 + * This function enables the 5V detection comparator and sets the 5V valid
 + * threshold to 4.4V . We use 4.4V threshold here to make sure that even
 + * under high load, the voltage drop on the 5V input won't be so critical
 + * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
 + * converter and thus making the system crash.
 + */
  static void mxs_power_setup_5v_detect(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        /* Start 5V detection */
        clrsetbits_le32(&power_regs->hw_power_5vctrl,
                        POWER_5VCTRL_VBUSVALID_TRSH_MASK,
                        POWER_5VCTRL_PWRUP_VBUS_CMPS);
  }
  
 +/**
 + * mxs_src_power_init() - Preconfigure the power block
 + *
 + * This function configures reasonable values for the DC-DC control loop
 + * and battery monitor.
 + */
  static void mxs_src_power_init(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        /* Improve efficieny and reduce transient ripple */
        writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
                POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
        clrsetbits_le32(&power_regs->hw_power_minpwr,
                        POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
  
-       /* 5V to battery handoff ... FIXME */
-       setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
-       early_delay(30);
-       clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+       if (!fixed_batt_supply) {
+               /* 5V to battery handoff ... FIXME */
+               setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+               early_delay(30);
+               clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+       }
  }
  
 +/**
 + * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
 + *
 + * This function configures the necessary parameters for the 4P2 linear
 + * regulator to supply the DC-DC converter from 5V input.
 + */
  static void mxs_power_init_4p2_params(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        /* Setup 4P2 parameters */
        clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
                POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
                0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  }
  
 +/**
 + * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
 + * @xfer:     Select if the input shall be enabled or disabled
 + *
 + * This function enables or disables the 4P2 input into the DC-DC converter.
 + */
  static void mxs_enable_4p2_dcdc_input(int xfer)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
        uint32_t prev_5v_brnout, prev_5v_droop;
  
                                POWER_CTRL_ENIRQ_VDD5V_DROOP);
  }
  
 +/**
 + * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
 + *
 + * This function enables the 4P2 regulator and switches the DC-DC converter
 + * to use the 4P2 input.
 + */
  static void mxs_power_init_4p2_regulator(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp, tmp2;
  
        setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
        writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  }
  
 +/**
 + * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
 + *
 + * This function configures the DC-DC converter to be supplied from the 4P2
 + * linear regulator.
 + */
  static void mxs_power_init_dcdc_4p2_source(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        if (!(readl(&power_regs->hw_power_dcdc4p2) &
                POWER_DCDC4P2_ENABLE_DCDC)) {
                hang();
        }
  }
  
 +/**
 + * mxs_power_enable_4p2() - Power up the 4P2 regulator
 + *
 + * This function drives the process of powering up the 4P2 linear regulator
 + * and switching the DC-DC converter input over to the 4P2 linear regulator.
 + */
  static void mxs_power_enable_4p2(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t vdddctrl, vddactrl, vddioctrl;
        uint32_t tmp;
  
                        &power_regs->hw_power_charge_clr);
  }
  
 +/**
 + * mxs_boot_valid_5v() - Boot from 5V supply
 + *
 + * This function configures the power block to boot from valid 5V input.
 + * This is called only if the 5V is reliable and can properly supply the
 + * CPU. This function proceeds to configure the 4P2 converter to be supplied
 + * from the 5V input.
 + */
  static void mxs_boot_valid_5v(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        /*
         * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
         * disconnect event. FIXME
        mxs_power_enable_4p2();
  }
  
 +/**
 + * mxs_powerdown() - Shut down the system
 + *
 + * This function powers down the CPU completely.
 + */
  static void mxs_powerdown(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
        writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
                &power_regs->hw_power_reset);
  }
  
 +/**
 + * mxs_batt_boot() - Configure the power block to boot from battery input
 + *
 + * This function configures the power block to boot from the battery voltage
 + * supply.
 + */
  static void mxs_batt_boot(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
        clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
  
        clrsetbits_le32(&power_regs->hw_power_5vctrl,
                POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
                0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 +
 +      mxs_power_enable_4p2();
  }
  
 +/**
 + * mxs_handle_5v_conflict() - Test if the 5V input is reliable
 + *
 + * This function tests if the 5V input can reliably supply the system. If it
 + * can, then proceed to configuring the system to boot from 5V source, otherwise
 + * try booting from battery supply. If we can not boot from battery supply
 + * either, shut down the system.
 + */
  static void mxs_handle_5v_conflict(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp;
  
        setbits_le32(&power_regs->hw_power_vddioctrl,
        }
  }
  
 +/**
 + * mxs_5v_boot() - Configure the power block to boot from 5V input
 + *
 + * This function handles configuration of the power block when supplied by
 + * a 5V input.
 + */
  static void mxs_5v_boot(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        /*
         * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
         * but their implementation always returns 1 so we omit it here.
        mxs_handle_5v_conflict();
  }
  
 -static void mxs_fixed_batt_boot(void)
 +/**
 + * mxs_init_batt_bo() - Configure battery brownout threshold
 + *
 + * This function configures the battery input brownout threshold. The value
 + * at which the battery brownout happens is configured to 3.0V in the code.
 + */
 +static void mxs_init_batt_bo(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
+       writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+       setbits_le32(&power_regs->hw_power_5vctrl,
+               POWER_5VCTRL_PWDN_5VBRNOUT |
+               POWER_5VCTRL_ENABLE_DCDC |
+               POWER_5VCTRL_ILIMIT_EQ_ZERO |
+               POWER_5VCTRL_PWDN_5VBRNOUT |
+               POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+       writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+       clrbits_le32(&power_regs->hw_power_vdddctrl,
+               POWER_VDDDCTRL_DISABLE_FET |
+               POWER_VDDDCTRL_ENABLE_LINREG |
+               POWER_VDDDCTRL_DISABLE_STEPPING);
+       clrbits_le32(&power_regs->hw_power_vddactrl,
+               POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+               POWER_VDDACTRL_DISABLE_STEPPING);
+       clrbits_le32(&power_regs->hw_power_vddioctrl,
+               POWER_VDDIOCTRL_DISABLE_FET |
+               POWER_VDDIOCTRL_DISABLE_STEPPING);
  
-       /* Brownout at 3V */
+       /* Stop 5V detection */
+       writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
+               &power_regs->hw_power_5vctrl_clr);
+ }
+ static void mxs_init_batt_bo(void)
+ {
        clrsetbits_le32(&power_regs->hw_power_battmonitor,
                POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
-               15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+               BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
  
        writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
        writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
  }
  
 +/**
 + * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
 + *
 + * This function turns off the VDDD linear regulator and therefore makes
 + * the VDDD rail be supplied only by the DC-DC converter.
 + */
  static void mxs_switch_vddd_to_dcdc_source(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        clrsetbits_le32(&power_regs->hw_power_vdddctrl,
                POWER_VDDDCTRL_LINREG_OFFSET_MASK,
                POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
                POWER_VDDDCTRL_DISABLE_STEPPING);
  }
  
 +/**
 + * mxs_power_configure_power_source() - Configure power block source
 + *
 + * This function is the core of the power configuration logic. The function
 + * selects the power block input source and configures the whole power block
 + * accordingly. After the configuration is complete and the system is stable
 + * again, the function switches the CPU clock source back to PLL. Finally,
 + * the function switches the voltage rails to DC-DC converter.
 + */
  static void mxs_power_configure_power_source(void)
  {
-       int batt_ready, batt_good;
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        struct mxs_lradc_regs *lradc_regs =
                (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  
  #endif
  }
  
 +/**
 + * mxs_enable_output_rail_protection() - Enable power rail protection
 + *
 + * This function enables overload protection on the power rails. This is
 + * triggered if the power rails' voltage drops rapidly due to overload and
 + * in such case, the supply to the powerrail is cut-off, protecting the
 + * CPU from damage. Note that under such condition, the system will likely
 + * crash or misbehave.
 + */
  static void mxs_enable_output_rail_protection(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
                POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  
                        POWER_VDDIOCTRL_PWDN_BRNOUT);
  }
  
 +/**
 + * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
 + *
 + * This function tests if the VDDIO rail is supplied by linear regulator
 + * or by the DC-DC converter. Returns 1 if powered by linear regulator,
 + * returns 0 if powered by the DC-DC converter.
 + */
  static int mxs_get_vddio_power_source_off(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp;
  
-       if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+       if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
+               !(readl(&power_regs->hw_power_5vctrl) &
+                       POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
                tmp = readl(&power_regs->hw_power_vddioctrl);
                if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
                        if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
        }
  
        return 0;
  }
  
 +/**
 + * mxs_get_vddd_power_source_off() - Get VDDD rail power source
 + *
 + * This function tests if the VDDD rail is supplied by linear regulator
 + * or by the DC-DC converter. Returns 1 if powered by linear regulator,
 + * returns 0 if powered by the DC-DC converter.
 + */
  static int mxs_get_vddd_power_source_off(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp;
  
        tmp = readl(&power_regs->hw_power_vdddctrl);
@@@ -996,14 -918,16 +1100,17 @@@ static const struct mxs_vddx_cfg mxs_vd
  static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
                                uint32_t new_target, uint32_t new_brownout)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t cur_target, diff, bo_int = 0;
-       uint32_t powered_by_linreg = 0;
-       int adjust_up, tmp;
+       int powered_by_linreg = 0;
+       int adjust_up;
+       if (new_target < cfg->lowest_mV)
+               new_target = cfg->lowest_mV;
+       if (new_target > cfg->highest_mV)
+               new_target = cfg->highest_mV;
  
 -      new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
 +      new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
 +                                       cfg->step_mV);
  
        cur_target = readl(cfg->reg);
        cur_target &= cfg->trg_mask;
@@@ -1100,17 -1004,14 +1203,20 @@@ static void mxs_ungate_power(void
  #endif
  }
  
+ #ifdef CONFIG_CONFIG_MACH_MX28EVK
+ #define auto_restart 1
+ #else
+ #define auto_restart 0
+ #endif
 +/**
 + * mxs_power_init() - The power block init main function
 + *
 + * This function calls all the power block initialization functions in
 + * proper sequence to start the power block.
 + */
  void mxs_power_init(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        mxs_ungate_power();
  
        mxs_power_clock2xtal();
  }
  
  #ifdef        CONFIG_SPL_MXS_PSWITCH_WAIT
 +/**
 + * mxs_power_wait_pswitch() - Wait for power switch to be pressed
 + *
 + * This function waits until the power-switch was pressed to start booting
 + * the board.
 + */
  void mxs_power_wait_pswitch(void)
  {
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
        while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
                ;
  }
@@@ -68,13 -74,34 +74,39 @@@ int timer_init(void
                TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
                &timrot_regs->hw_timrot_timctrl0);
  
-       /* Set fixed_count to maximal value */
++#ifndef DEBUG_TIMER_WRAP
+       /* Set fixed_count to maximum value */
  #if defined(CONFIG_MX23)
        writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
  #elif defined(CONFIG_MX28)
        writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
  #endif
--
 -#ifndef DEBUG_TIMER_WRAP
 -      /* Set fixed_count to maximum value */
 -      writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
 -#else
++#else /* DEBUG_TIMER_WRAP */
+       /* Set fixed_count so that the counter will wrap after 20 seconds */
++#if defined(CONFIG_MX23)
++      writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
++#elif defined(CONFIG_MX28)
+       writel(20 * MXS_INCREMENTER_HZ,
+               &timrot_regs->hw_timrot_fixed_count0);
++#endif
+       gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ;
+       /* Make the usec counter roll over 30 seconds after startup */
+       writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS);
 -#endif
++#endif /* DEBUG_TIMER_WRAP */
+       writel(TIMROT_TIMCTRLn_UPDATE,
+               &timrot_regs->hw_timrot_timctrl0_clr);
+ #ifdef DEBUG_TIMER_WRAP
 -      /* Set fixed_count to maximal value for subsequent loads */
++      /* Set fixed_count to maximum value for subsequent loads */
++#if defined(CONFIG_MX23)
++      writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
++#elif defined(CONFIG_MX28)
+       writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
+ #endif
++#endif /* DEBUG_TIMER_WRAP */
+       gd->arch.timer_rate_hz = MXS_INCREMENTER_HZ;
+       gd->arch.tbl = TIMER_START;
+       gd->arch.tbu = 0;
        return 0;
  }
  
@@@ -89,26 -120,20 +125,22 @@@ unsigned long long get_ticks(void
        /* Upper bits are the valid ones. */
        now = readl(&timrot_regs->hw_timrot_timcount0) >>
                TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
 -#else
 +#elif defined(CONFIG_MX28)
-       now = readl(&timrot_regs->hw_timrot_running_count0);
+       /* The timer is counting down, so subtract the register value from
+        * the counter period length (implicitly 2^32) to get an incrementing
+        * timestamp
+        */
+       now = -readl(&timrot_regs->hw_timrot_running_count0);
 +#else
 +#error "Don't know how to read timrot_regs"
  #endif
+       ulong inc = now - gd->arch.lastinc;
  
-       if (lastdec >= now) {
-               /*
-                * normal mode (non roll)
-                * move stamp forward with absolut diff ticks
-                */
-               timestamp += (lastdec - now);
-       } else {
-               /* we have rollover of decrementer */
-               timestamp += (TIMER_LOAD_VAL - now) + lastdec;
-       }
-       lastdec = now;
-       return timestamp;
+       if (gd->arch.tbl + inc < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl += inc;
+       gd->arch.lastinc = now;
+       return ((unsigned long long)gd->arch.tbu << 32) | gd->arch.tbl;
  }
  
  ulong get_timer_masked(void)
@@@ -121,8 -108,16 +121,10 @@@ int __cpu_mmc_init(bd_t *bis
  
        return omap_mmc_init(1, 0, 0, -1, -1);
  }
+ /* let platform code be able to override this! */
+ int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__cpu_mmc_init")));
  #endif
  
 -void setup_clocks_for_console(void)
 -{
 -      /* Not yet implemented */
 -      return;
 -}
 -
  /* AM33XX has two MUSB controllers which can be host or gadget */
  #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
        (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
  #include <asm/arch/hardware.h>
  #include <asm/io.h>
  
 -
+ #define PRCM_MOD_EN           0x2
+ #define PRCM_FORCE_WAKEUP     0x2
+ #define PRCM_FUNCTL           0x0
+ #define PRCM_EMIF_CLK_ACTIVITY        BIT(2)
+ #define PRCM_L3_GCLK_ACTIVITY BIT(4)
+ #define PLL_BYPASS_MODE               0x4
+ #define ST_MN_BYPASS          0x00000100
+ #define ST_DPLL_CLK           0x00000001
+ #define CLK_SEL_MASK          0x7ffff
+ #define CLK_DIV_MASK          0x1f
+ #define CLK_DIV2_MASK         0x7f
+ #define CLK_SEL_SHIFT         0x8
+ #define CLK_MODE_MASK         0x7
+ #define CLK_MODE_SEL          0x7
+ #define DPLL_CLKDCOLDO_GATE_CTRL 0x300
  #define OSC   (V_OSCK/1000000)
  
 -#define MPUPLL_N      (OSC-1)
+ #define MPUPLL_M      CONFIG_SYS_MPUCLK
 -#define COREPLL_N     (OSC-1)
++#define MPUPLL_N      (OSC - 1)
+ #define MPUPLL_M2     1
+ /* Core PLL Fdll = 1 GHZ, */
+ #define COREPLL_M     1000
 -#define PERPLL_N      (OSC-1)
++#define COREPLL_N     (OSC - 1)
+ #define COREPLL_M4    10      /* CORE_CLKOUTM4 = 200 MHZ */
+ #define COREPLL_M5    8       /* CORE_CLKOUTM5 = 250 MHZ */
+ #define COREPLL_M6    4       /* CORE_CLKOUTM6 = 500 MHZ */
+ /*
+  * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+  * frequency needs to be set to 960 MHZ. Hence,
+  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+  */
+ #define PERPLL_M      960
 -#define DDRPLL_N      (OSC-1)
++#define PERPLL_N      (OSC - 1)
+ #define PERPLL_M2     5
+ /* DDR Freq is 266 MHZ for now */
+ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+ #define DDRPLL_M      266
 -const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 -const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 -const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 -const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
 -
 -#ifdef CONFIG_SPL_BUILD
 -#define enable_clk(reg, val) __enable_clk(#reg, &reg, val)
++#define DDRPLL_N      (OSC - 1)
+ #define DDRPLL_M2     1
 +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
 +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
 +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 +struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 +
 +const struct dpll_regs dpll_mpu_regs = {
 +      .cm_clkmode_dpll        = CM_WKUP + 0x88,
 +      .cm_idlest_dpll         = CM_WKUP + 0x20,
 +      .cm_clksel_dpll         = CM_WKUP + 0x2C,
 +      .cm_div_m2_dpll         = CM_WKUP + 0xA8,
 +};
 +
 +const struct dpll_regs dpll_core_regs = {
 +      .cm_clkmode_dpll        = CM_WKUP + 0x90,
 +      .cm_idlest_dpll         = CM_WKUP + 0x5C,
 +      .cm_clksel_dpll         = CM_WKUP + 0x68,
 +      .cm_div_m4_dpll         = CM_WKUP + 0x80,
 +      .cm_div_m5_dpll         = CM_WKUP + 0x84,
 +      .cm_div_m6_dpll         = CM_WKUP + 0xD8,
 +};
 +
 +const struct dpll_regs dpll_per_regs = {
 +      .cm_clkmode_dpll        = CM_WKUP + 0x8C,
 +      .cm_idlest_dpll         = CM_WKUP + 0x70,
 +      .cm_clksel_dpll         = CM_WKUP + 0x9C,
 +      .cm_div_m2_dpll         = CM_WKUP + 0xAC,
 +};
 +
 +const struct dpll_regs dpll_ddr_regs = {
 +      .cm_clkmode_dpll        = CM_WKUP + 0x94,
 +      .cm_idlest_dpll         = CM_WKUP + 0x34,
 +      .cm_clksel_dpll         = CM_WKUP + 0x40,
 +      .cm_div_m2_dpll         = CM_WKUP + 0xA0,
 +};
 +
 +struct dpll_params dpll_mpu_opp100 = {
 +              CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
 +const struct dpll_params dpll_core_opp100 = {
 +              1000, OSC-1, -1, -1, 10, 8, 4};
 +const struct dpll_params dpll_mpu = {
 +              MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
 +const struct dpll_params dpll_core = {
 +              50, OSC-1, -1, -1, 1, 1, 1};
 +const struct dpll_params dpll_per = {
 +              960, OSC-1, 5, -1, -1, -1, -1};
 +
 +const struct dpll_params *get_dpll_mpu_params(void)
 +{
 +      return &dpll_mpu;
 +}
  
 -static void __enable_clk(const char *name, const void *reg, u32 mask)
 +const struct dpll_params *get_dpll_core_params(void)
  {
 -      unsigned long timeout = 10000000;
 -
 -      writel(mask, reg);
 -      while (readl(reg) != mask)
 -              /* poor man's timeout, since timers not initialized */
 -              if (timeout-- == 0)
 -                      /* no error message, since console not yet available */
 -                      break;
 +      return &dpll_core;
  }
  
 -static void enable_interface_clocks(void)
 +const struct dpll_params *get_dpll_per_params(void)
  {
 -      /* Enable all the Interconnect Modules */
 -      enable_clk(cmper->l3clkctrl, PRCM_MOD_EN);
 -      enable_clk(cmper->l4lsclkctrl, PRCM_MOD_EN);
 -      enable_clk(cmper->l4fwclkctrl, PRCM_MOD_EN);
 -      enable_clk(cmwkup->wkl4wkclkctrl, PRCM_MOD_EN);
 -      enable_clk(cmper->l3instrclkctrl, PRCM_MOD_EN);
 -      enable_clk(cmper->l4hsclkctrl, PRCM_MOD_EN);
 -#ifdef CONFIG_HW_WATCHDOG
 -      enable_clk(cmwkup->wdtimer1ctrl, PRCM_MOD_EN);
 -#endif
 -      /* GPIO0 */
 -      enable_clk(cmwkup->wkgpio0clkctrl, PRCM_MOD_EN);
 +      return &dpll_per;
  }
  
 -/*
 - * Force power domain wake up transition
 - * Ensure that the corresponding interface clock is active before
 - * using the peripheral
 - */
 -static void power_domain_wkup_transition(void)
 +void setup_clocks_for_console(void)
  {
 -      writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
 -      writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
 -      writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
 -      writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
 -      writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
 +      clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 +                      CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 +                      CD_CLKCTRL_CLKTRCTRL_SHIFT);
 +
 +      clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 +                      CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 +                      CD_CLKCTRL_CLKTRCTRL_SHIFT);
 +
 +      clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
 +                      MODULE_CLKCTRL_MODULEMODE_MASK,
 +                      MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 +                      MODULE_CLKCTRL_MODULEMODE_SHIFT);
 +      clrsetbits_le32(&cmper->uart1clkctrl,
 +                      MODULE_CLKCTRL_MODULEMODE_MASK,
 +                      MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 +                      MODULE_CLKCTRL_MODULEMODE_SHIFT);
 +      clrsetbits_le32(&cmper->uart2clkctrl,
 +                      MODULE_CLKCTRL_MODULEMODE_MASK,
 +                      MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 +                      MODULE_CLKCTRL_MODULEMODE_SHIFT);
 +      clrsetbits_le32(&cmper->uart3clkctrl,
 +                      MODULE_CLKCTRL_MODULEMODE_MASK,
 +                      MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 +                      MODULE_CLKCTRL_MODULEMODE_SHIFT);
 +      clrsetbits_le32(&cmper->uart4clkctrl,
 +                      MODULE_CLKCTRL_MODULEMODE_MASK,
 +                      MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 +                      MODULE_CLKCTRL_MODULEMODE_SHIFT);
 +      clrsetbits_le32(&cmper->uart5clkctrl,
 +                      MODULE_CLKCTRL_MODULEMODE_MASK,
 +                      MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 +                      MODULE_CLKCTRL_MODULEMODE_SHIFT);
  }
  
 -/*
 - * Enable the peripheral clock for required peripherals
 - */
 -static void enable_per_clocks(void)
 +void enable_basic_clocks(void)
  {
 -      /* Enable the control module though RBL would have done it*/
 -      enable_clk(cmwkup->wkctrlclkctrl, PRCM_MOD_EN);
 -      /* Enable the timer2 clock */
 -      enable_clk(cmper->timer2clkctrl, PRCM_MOD_EN);
 +      u32 *const clk_domains[] = {
 +              &cmper->l3clkstctrl,
 +              &cmper->l4fwclkstctrl,
 +              &cmper->l3sclkstctrl,
 +              &cmper->l4lsclkstctrl,
 +              &cmwkup->wkclkstctrl,
 +              &cmper->emiffwclkctrl,
 +              &cmrtc->clkstctrl,
 +              0
 +      };
 +
 +      u32 *const clk_modules_explicit_en[] = {
 +              &cmper->l3clkctrl,
 +              &cmper->l4lsclkctrl,
 +              &cmper->l4fwclkctrl,
 +              &cmwkup->wkl4wkclkctrl,
 +              &cmper->l3instrclkctrl,
 +              &cmper->l4hsclkctrl,
 +              &cmwkup->wkgpio0clkctrl,
 +              &cmwkup->wkctrlclkctrl,
 +              &cmper->timer2clkctrl,
 +              &cmper->gpmcclkctrl,
 +              &cmper->elmclkctrl,
 +              &cmper->mmc0clkctrl,
 +              &cmper->mmc1clkctrl,
 +              &cmwkup->wkup_i2c0ctrl,
 +              &cmper->gpio1clkctrl,
 +              &cmper->gpio2clkctrl,
 +              &cmper->gpio3clkctrl,
 +              &cmper->i2c1clkctrl,
 +              &cmper->cpgmac0clkctrl,
 +              &cmper->spi0clkctrl,
 +              &cmrtc->rtcclkctrl,
 +              &cmper->usb0clkctrl,
 +              &cmper->emiffwclkctrl,
 +              &cmper->emifclkctrl,
 +              0
 +      };
 +
 +      do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 +
        /* Select the Master osc 24 MHZ as Timer2 clock source */
        writel(0x1, &cmdpll->clktimer2clk);
 -
 -#ifdef CONFIG_SYS_NS16550_COM1
 -      /* UART0 */
 -      enable_clk(cmwkup->wkup_uart0ctrl, PRCM_MOD_EN);
 -#endif
 -#ifdef CONFIG_SYS_NS16550_COM2
 -      enable_clk(cmper->uart1clkctrl, PRCM_MOD_EN);
 -#endif
 -#ifdef CONFIG_SYS_NS16550_COM3
 -      enable_clk(cmper->uart2clkctrl, PRCM_MOD_EN);
 -#endif
 -#ifdef CONFIG_SYS_NS16550_COM4
 -      enable_clk(cmper->uart3clkctrl, PRCM_MOD_EN);
 -#endif
 -#ifdef CONFIG_SYS_NS16550_COM5
 -      enable_clk(cmper->uart4clkctrl, PRCM_MOD_EN);
 -#endif
 -#ifdef CONFIG_SYS_NS16550_COM6
 -      enable_clk(cmper->uart5clkctrl, PRCM_MOD_EN);
 -#endif
 -      /* GPMC */
 -      enable_clk(cmper->gpmcclkctrl, PRCM_MOD_EN);
 -
 -      /* ELM */
 -      enable_clk(cmper->elmclkctrl, PRCM_MOD_EN);
 -
 -      /* Ethernet */
 -      enable_clk(cmper->cpswclkstctrl, PRCM_MOD_EN);
 -      enable_clk(cmper->cpgmac0clkctrl, PRCM_MOD_EN);
 -
 -      /* MMC */
 -#ifdef CONFIG_OMAP_MMC_DEV_0
 -      enable_clk(cmper->mmc0clkctrl, PRCM_MOD_EN);
 -#endif
 -#ifdef CONFIG_OMAP_MMC_DEV_1
 -      enable_clk(cmper->mmc1clkctrl, PRCM_MOD_EN);
 -#endif
 -      /* LCD */
 -      enable_clk(cmper->lcdclkctrl, PRCM_MOD_EN);
 -
 -      /* MMC1 */
 -      writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
 -      while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
 -              ;
 -
 -      /* i2c0 */
 -      enable_clk(cmwkup->wkup_i2c0ctrl, PRCM_MOD_EN);
 -
 -      /* GPIO1-3 */
 -      enable_clk(cmper->gpio1clkctrl, PRCM_MOD_EN);
 -      enable_clk(cmper->gpio2clkctrl, PRCM_MOD_EN);
 -      enable_clk(cmper->gpio3clkctrl, PRCM_MOD_EN);
 -
 -      /* i2c1 */
 -      enable_clk(cmper->i2c1clkctrl, PRCM_MOD_EN);
 -
 -      /* spi0 */
 -      enable_clk(cmper->spi0clkctrl, PRCM_MOD_EN);
 -
 -      /* rtc */
 -      enable_clk(cmrtc->rtcclkctrl, PRCM_MOD_EN);
 -
 -      /* usb0 */
 -      enable_clk(cmper->usb0clkctrl, PRCM_MOD_EN);
  }
 -#endif /* CONFIG_SPL_BUILD */
 -
+ void mpu_pll_config_val(int mpull_m)
+ {
+       u32 clkmode, clksel, div_m2;
+       clkmode = readl(&cmwkup->clkmoddpllmpu);
+       clksel = readl(&cmwkup->clkseldpllmpu);
+       div_m2 = readl(&cmwkup->divm2dpllmpu);
+       /* Set the PLL to bypass Mode */
+       writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
+       while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
+               ;
+       clksel &= ~CLK_SEL_MASK;
+       clksel |= (mpull_m << CLK_SEL_SHIFT) | MPUPLL_N;
+       writel(clksel, &cmwkup->clkseldpllmpu);
+       div_m2 &= ~CLK_DIV_MASK;
+       div_m2 |= MPUPLL_M2;
+       writel(div_m2, &cmwkup->divm2dpllmpu);
+       clkmode &= ~CLK_MODE_MASK;
+       clkmode |= CLK_MODE_SEL;
+       writel(clkmode, &cmwkup->clkmoddpllmpu);
+       while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
+               ;
+ }
+ void mpu_pll_config(void)
+ {
+       mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+ }
+ static void core_pll_config_val(int m)
+ {
+       u32 clkmode, clksel, div_m4, div_m5, div_m6;
+       clkmode = readl(&cmwkup->clkmoddpllcore);
+       clksel = readl(&cmwkup->clkseldpllcore);
+       div_m4 = readl(&cmwkup->divm4dpllcore);
+       div_m5 = readl(&cmwkup->divm5dpllcore);
+       div_m6 = readl(&cmwkup->divm6dpllcore);
+       /* Set the PLL to bypass Mode */
+       writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
+       while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
+               ;
+       clksel &= ~CLK_SEL_MASK;
+       clksel |= ((m << CLK_SEL_SHIFT) | COREPLL_N);
+       writel(clksel, &cmwkup->clkseldpllcore);
+       div_m4 &= ~CLK_DIV_MASK;
+       div_m4 |= COREPLL_M4;
+       writel(div_m4, &cmwkup->divm4dpllcore);
+       div_m5 &= ~CLK_DIV_MASK;
+       div_m5 |= COREPLL_M5;
+       writel(div_m5, &cmwkup->divm5dpllcore);
+       div_m6 &= ~CLK_DIV_MASK;
+       div_m6 |= COREPLL_M6;
+       writel(div_m6, &cmwkup->divm6dpllcore);
+       clkmode &= ~CLK_MODE_MASK;
+       clkmode |= CLK_MODE_SEL;
+       writel(clkmode, &cmwkup->clkmoddpllcore);
+       while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+               ;
+ }
+ static inline void core_pll_config(void)
+ {
+       core_pll_config_val(COREPLL_M);
+ }
+ static void per_pll_config_val(int m)
+ {
+       u32 clkmode, clksel, div_m2;
+       clkmode = readl(&cmwkup->clkmoddpllper);
+       clksel = readl(&cmwkup->clkseldpllper);
+       div_m2 = readl(&cmwkup->divm2dpllper);
+       /* Set the PLL to bypass Mode */
+       writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
+       while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
+               ;
+       clksel &= ~CLK_SEL_MASK;
+       clksel |= (m << CLK_SEL_SHIFT) | PERPLL_N;
+       writel(clksel, &cmwkup->clkseldpllper);
+       div_m2 &= ~CLK_DIV2_MASK;
+       div_m2 |= PERPLL_M2;
+       writel(div_m2, &cmwkup->divm2dpllper);
+       clkmode &= ~CLK_MODE_MASK;
+       clkmode |= CLK_MODE_SEL;
+       writel(clkmode, &cmwkup->clkmoddpllper);
+       while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
+               ;
+       writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
+ }
+ static inline void per_pll_config(void)
+ {
+       per_pll_config_val(PERPLL_M);
+ }
+ static void disp_pll_config_val(int m)
+ {
+       u32 clkmode, clksel, div_m2;
+       clkmode = readl(&cmwkup->clkmoddplldisp);
+       clksel = readl(&cmwkup->clkseldplldisp);
+       div_m2 = readl(&cmwkup->divm2dplldisp);
+       /* Set the PLL to bypass Mode */
+       writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp);
+       while (!(readl(&cmwkup->idlestdplldisp) & ST_MN_BYPASS))
+               ;
+       clksel &= ~CLK_SEL_MASK;
+       clksel |= (m << CLK_SEL_SHIFT) | DISPPLL_N;
+       writel(clksel, &cmwkup->clkseldplldisp);
+       div_m2 &= ~CLK_DIV2_MASK;
+       div_m2 |= DISPPLL_M2;
+       writel(div_m2, &cmwkup->divm2dplldisp);
+       clkmode &= ~CLK_MODE_MASK;
+       clkmode |= CLK_MODE_SEL;
+       writel(clkmode, &cmwkup->clkmoddplldisp);
+       while (!(readl(&cmwkup->idlestdplldisp) & ST_DPLL_CLK))
+               ;
+ }
+ static inline void disp_pll_config(void)
+ {
+       disp_pll_config_val(DISPPLL_M);
+ }
+ void ddr_pll_config(unsigned int ddrpll_m)
+ {
+       u32 clkmode, clksel, div_m2;
+       clkmode = readl(&cmwkup->clkmoddpllddr);
+       clksel = readl(&cmwkup->clkseldpllddr);
+       div_m2 = readl(&cmwkup->divm2dpllddr);
+       /* Set the PLL to bypass Mode */
+       clkmode &= ~CLK_MODE_MASK;
+       clkmode |= PLL_BYPASS_MODE;
+       writel(clkmode, &cmwkup->clkmoddpllddr);
+       /* Wait till bypass mode is enabled */
+       while (!(readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS))
+               ;
+       clksel &= ~CLK_SEL_MASK;
+       clksel |= (ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N;
+       writel(clksel, &cmwkup->clkseldpllddr);
+       div_m2 &= ~CLK_DIV_MASK;
+       div_m2 |= DDRPLL_M2;
+       writel(div_m2, &cmwkup->divm2dpllddr);
+       clkmode &= ~CLK_MODE_MASK;
+       clkmode |= CLK_MODE_SEL;
+       writel(clkmode, &cmwkup->clkmoddpllddr);
+       /* Wait till dpll is locked */
+       while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
+               ;
+ }
 -#ifdef CONFIG_SPL_BUILD
 -void enable_emif_clocks(void)
 -{
 -      /* Enable the  EMIF_FW Functional clock */
 -      writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 -      /* Enable EMIF0 Clock */
 -      writel(PRCM_MOD_EN, &cmper->emifclkctrl);
 -      /* Poll if module is functional */
 -      while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 -              ;
 -}
 -
 -/*
 - * Configure the PLL/PRCM for necessary peripherals
 - */
 -void pll_init()
 -{
 -      mpu_pll_config();
 -      core_pll_config();
 -      per_pll_config();
 -      disp_pll_config();
 -
 -      /* Enable the required interconnect clocks */
 -      enable_interface_clocks();
 -
 -      /* Power domain wake up transition */
 -      power_domain_wkup_transition();
 -
 -      /* Enable the required peripherals */
 -      enable_per_clocks();
 -}
 -#endif
 -
+ #define M(mn) (((mn) & CLK_SEL_MASK) >> CLK_SEL_SHIFT)
+ #define N(mn) ((mn) & CLK_DIV2_MASK)
+ unsigned long __clk_get_rate(u32 m_n, u32 div_m2)
+ {
+       unsigned long rate;
+       div_m2 &= CLK_DIV_MASK;
+       debug("M=%u N=%u M2=%u\n", M(m_n), N(m_n), div_m2);
+       rate = V_OSCK / 1000 * M(m_n) / (N(m_n) + 1) / div_m2;
+       debug("CLK = %lu.%03luMHz\n", rate / 1000, rate % 1000);
+       return rate * 1000;
+ }
+ unsigned long lcdc_clk_rate(void)
+ {
+       return clk_get_rate(cmwkup, disp);
+ }
+ unsigned long mpu_clk_rate(void)
+ {
+       return clk_get_rate(cmwkup, mpu);
+ }
+ enum {
+       CLK_MPU_PLL,
+       CLK_CORE_PLL,
+       CLK_PER_PLL,
+       CLK_DISP_PLL,
+       CLK_GPMC,
+ };
+ static struct clk_lookup {
+       const char *name;
+       unsigned int index;
+ } am33xx_clk_lookup[] = {
+       { "mpu", CLK_MPU_PLL, },
+       { "core", CLK_CORE_PLL, },
+       { "per", CLK_PER_PLL, },
+       { "lcdc", CLK_DISP_PLL, },
+       { "gpmc", CLK_GPMC, },
+ };
+ #define print_pll(dom, pll) {                         \
+       u32 __pll = clk_get_rate(dom, pll);             \
+       printf("%-12s %4d.%03d MHz\n", #pll,            \
+               __pll / 1000000, __pll / 1000 % 1000);  \
+       }
+ #define print_pll2(dom, n, pll) {                     \
+       u32 __m_n = readl(&(dom)->clkseldpll##pll);     \
+       u32 __div = readl(&(dom)->divm##n##dpll##pll);  \
+       u32 __pll = __clk_get_rate(__m_n, __div);       \
+       printf("%-12s %4d.%03d MHz\n", #pll "_m" #n,    \
+               __pll / 1000000, __pll / 1000 % 1000);  \
+       }
+ static void do_showclocks(void)
+ {
+       print_pll(cmwkup, mpu);
+       print_pll2(cmwkup, 4, core);
+       print_pll2(cmwkup, 5, core);
+       print_pll2(cmwkup, 6, core);
+       print_pll(cmwkup, ddr);
+       print_pll(cmwkup, per);
+       print_pll(cmwkup, disp);
+ }
+ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc,
+       char *const argv[])
+ {
+       int i;
+       unsigned long freq;
+       unsigned long __attribute__((unused)) ref = ~0UL;
+       if (argc < 2) {
+               do_showclocks();
+               return CMD_RET_SUCCESS;
+       } else if (argc == 2 || argc > 4) {
+               return CMD_RET_USAGE;
+       }
+       freq = simple_strtoul(argv[2], NULL, 0);
+       if (freq < 1000) {
+               printf("Invalid clock frequency %lu\n", freq);
+               return CMD_RET_FAILURE;
+       }
+       if (argc > 3) {
+               ref = simple_strtoul(argv[3], NULL, 0);
+       }
+       for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) {
+               if (strcasecmp(argv[1], am33xx_clk_lookup[i].name) == 0) {
+                       switch (am33xx_clk_lookup[i].index) {
+                       case CLK_MPU_PLL:
+                               mpu_pll_config_val(freq / 1000000);
+                               break;
+                       case CLK_CORE_PLL:
+                               core_pll_config_val(freq / 1000000);
+                               break;
+                       case CLK_PER_PLL:
+                               per_pll_config_val(freq / 1000000);
+                               break;
+                       case CLK_DISP_PLL:
+                               disp_pll_config_val(freq / 1000000);
+                               break;
+                       default:
+                               printf("Cannot change %s clock\n",
+                                       am33xx_clk_lookup[i].name);
+                               return CMD_RET_FAILURE;
+                       }
+                       printf("%s clock set to %lu.%03lu MHz\n",
+                               am33xx_clk_lookup[i].name,
+                               freq / 1000000, freq / 1000 % 1000);
+                       return CMD_RET_SUCCESS;
+               }
+       }
+       if (i == ARRAY_SIZE(am33xx_clk_lookup)) {
+               printf("clock %s not found; supported clocks are:\n", argv[1]);
+               for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) {
+                       printf("\t%s\n", am33xx_clk_lookup[i].name);
+               }
+       } else {
+               printf("Failed to set clock %s to %s MHz\n",
+                       argv[1], argv[2]);
+       }
+       return CMD_RET_FAILURE;
+ }
+ U_BOOT_CMD(
+       clocks, 4, 0, do_clocks,
+       "display/set clocks",
+       "                    - display clock settings\n"
+       "clocks <clkname> <freq>    - set clock <clkname> to <freq> Hz"
+ );
@@@ -33,111 -36,30 +36,140 @@@ static struct ddr_data_regs *ddr_data_r
  /**
   * Base address for ddr io control instances
   */
- static struct ddr_cmdtctrl *ioctrl_reg = {
-                       (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+ static struct ddr_cmdtctrl *ioctrl_reg =
+                               (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR;
  
-  * Configure EMIF4D5 registers and MR registers
 +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
 +{
 +      u32 mr;
 +
 +      mr_addr |= cs << EMIF_REG_CS_SHIFT;
 +      writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
 +
 +      mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
 +      debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
 +      if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
 +          ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
 +          ((mr & 0xff000000) >> 24) == (mr & 0xff))
 +              return mr & 0xff;
 +      else
 +              return mr;
 +}
 +
 +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
 +{
 +      mr_addr |= cs << EMIF_REG_CS_SHIFT;
 +      writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
 +      writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
 +}
 +
 +static void configure_mr(int nr, u32 cs)
 +{
 +      u32 mr_addr;
 +
 +      while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 +              ;
 +      set_mr(nr, cs, LPDDR2_MR10, 0x56);
 +
 +      set_mr(nr, cs, LPDDR2_MR1, 0x43);
 +      set_mr(nr, cs, LPDDR2_MR2, 0x2);
 +
 +      mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 +      set_mr(nr, cs, mr_addr, 0x2);
 +}
 +
 +/*
-       writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
++ * Configure EMIF4D5 registers and MR registers For details about these magic
++ * values please see the EMIF registers section of the TRM.
 + */
 +void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 +{
 +      writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
 +      writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
-       writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-       writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 +      writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 +
 +      writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
 +      writel(regs->emif_rd_wr_lvl_rmp_win,
 +             &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
 +      writel(regs->emif_rd_wr_lvl_rmp_ctl,
 +             &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 +      writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 +      writel(regs->emif_rd_wr_exec_thresh,
 +             &emif_reg[nr]->emif_rd_wr_exec_thresh);
 +
 +      /*
 +       * for most SOCs these registers won't need to be changed so only
 +       * write to these registers if someone explicitly has set the
 +       * register's value.
 +       */
 +      if(regs->emif_cos_config) {
 +              writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
 +              writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
 +              writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
 +              writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
 +      }
 +
++      /*
++       * Sequence to ensure that the PHY is in a known state prior to
++       * startting hardware leveling.  Also acts as to latch some state from
++       * the EMIF into the PHY.
++       */
++      writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
++      writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
++      writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
++
++      clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
++                      EMIF_REG_INITREF_DIS_MASK);
++
 +      writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 +      writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
++      writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
++      writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
++
++      /* Perform hardware leveling. */
++      udelay(1000);
++      writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
++             0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
++      writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
++             0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
++
++      writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
++
++      /* Enable read leveling */
++      writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
++
++      /*
++       * Enable full read and write leveling.  Wait for read and write
++       * leveling bit to clear RDWRLVLFULL_START bit 31
++       */
++      while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
++              ;
++
++      /* Check the timeout register to see if leveling is complete */
++      if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
++              puts("DDR3 H/W leveling incomplete with errors\n");
 +
 +      if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
 +              configure_mr(nr, 0);
 +              configure_mr(nr, 1);
 +      }
 +}
 +
  /**
   * Configure SDRAM
   */
  void config_sdram(const struct emif_regs *regs, int nr)
  {
        if (regs->zq_config) {
--              /*
--               * A value of 0x2800 for the REF CTRL will give us
--               * about 570us for a delay, which will be long enough
--               * to configure things.
--               */
--              writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
                writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 -              writel(regs->sdram_config, &cstat->emif_sdram_config);
 +              writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
                writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
                writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
                writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
        }
++      writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
--      writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  }
  
  /**
@@@ -153,60 -75,11 +185,75 @@@ void set_sdram_timings(const struct emi
        writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
  }
  
- void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
- {
- }
 +/*
-  * Configure EXT PHY registers
++ * Configure EXT PHY registers for hardware leveling
 + */
 +static void ext_phy_settings(const struct emif_regs *regs, int nr)
 +{
-       u32 *ext_phy_ctrl_base = 0;
-       u32 *emif_ext_phy_ctrl_base = 0;
-       const u32 *ext_phy_ctrl_const_regs;
-       u32 i = 0;
-       u32 size;
-       ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
-       emif_ext_phy_ctrl_base =
-                       (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
-       /* Configure external phy control timing registers */
-       for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-               writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-               /* Update shadow registers */
-               writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-       }
 +      /*
-        * external phy 6-24 registers do not change with
-        * ddr frequency
++       * Enable hardware leveling on the EMIF.  For details about these
++       * magic values please see the EMIF registers section of the TRM.
 +       */
-       emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
-       if (!size)
-               return;
++      writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
++      writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
++      writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
++      writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
++      writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
++      writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
++      writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
++      writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
++      writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
++      writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
++      writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
++      writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 +
-       for (i = 0; i < size; i++) {
-               writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
-               /* Update shadow registers */
-               writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
-       }
++      /*
++       * Sequence to ensure that the PHY is again in a known state after
++       * hardware leveling.
++       */
++      writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
++      writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
++      writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 +}
 +
  /**
   * Configure DDR PHY
   */
  void config_ddr_phy(const struct emif_regs *regs, int nr)
  {
-        * disable initialization and refreshes for now until we
 +      /*
++       * Disable initialization and refreshes for now until we
 +       * finish programming EMIF regs.
++       * Also set time between rising edge of DDR_RESET to rising
++       * edge of DDR_CKE to > 500us per memory spec.
 +       */
++#ifndef CONFIG_AM43XX
 +      setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 +                   EMIF_REG_INITREF_DIS_MASK);
++#endif
++      if (regs->zq_config)
++              writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
 +
        writel(regs->emif_ddr_phy_ctlr_1,
                &emif_reg[nr]->emif_ddr_phy_ctrl_1);
        writel(regs->emif_ddr_phy_ctlr_1,
Simple merge
Simple merge
@@@ -19,14 -19,18 +19,18 @@@ ENTRY(lowlevel_init
        /*
         * Setup a temporary stack
         */
+ #ifndef CONFIG_SPL_BUILD
        ldr     sp, =CONFIG_SYS_INIT_SP_ADDR
+ #else
+       ldr     sp, =CONFIG_SPL_STACK
+ #endif
        bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
  #ifdef CONFIG_SPL_BUILD
 -      ldr     r8, =gdata
 +      ldr     r9, =gdata
  #else
 -      sub     sp, #GD_SIZE
 +      sub     sp, sp, #GD_SIZE
        bic     sp, sp, #7
 -      mov     r8, sp
 +      mov     r9, sp
  #endif
        /*
         * Save the old lr(passed in ip) and the current lr to stack
@@@ -94,7 -183,101 +183,101 @@@ void enable_usboh3_clk(bool enable
                        MXC_CCM_CCGR2_USBOH3_60M(cg));
  }
  
 -#ifdef CONFIG_I2C_MXC
+ void ipu_clk_enable(void)
+ {
+       /* IPU root clock derived from AXI B */
+       clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK,
+                       MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1));
+       setbits_le32(&mxc_ccm->CCGR5,
+               MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+       /* Handshake with IPU when certain clock rates are changed. */
+       clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+       /* Handshake with IPU when LPM is entered as its enabled. */
+       clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+ }
+ void ipu_clk_disable(void)
+ {
+       clrbits_le32(&mxc_ccm->CCGR5,
+               MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+       /* Handshake with IPU when certain clock rates are changed. */
+       setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+       /* Handshake with IPU when LPM is entered as its enabled. */
+       setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+ }
+ void ipu_di_clk_enable(int di)
+ {
+       switch (di) {
+       case 0:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid DI index %d\n", __func__, di);
+       }
+ }
+ void ipu_di_clk_disable(int di)
+ {
+       switch (di) {
+       case 0:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid DI index %d\n", __func__, di);
+       }
+ }
+ #ifdef CONFIG_MX53
+ void ldb_clk_enable(int ldb)
+ {
+       switch (ldb) {
+       case 0:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid LDB index %d\n", __func__, ldb);
+       }
+ }
+ void ldb_clk_disable(int ldb)
+ {
+       switch (ldb) {
+       case 0:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid LDB index %d\n", __func__, ldb);
+       }
+ }
+ #endif
 +#ifdef CONFIG_SYS_I2C_MXC
  /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
  int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  {
@@@ -294,25 -289,29 +295,30 @@@ setup_pll_func
        mov r1, #0x4
        str r1, [r0, #CLKCTL_CCSR]
  
+ #if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
        setup_pll PLL1_BASE_ADDR, 800
+ #elif CONFIG_SYS_CPU_CLK == 600
+       setup_pll PLL1_BASE_ADDR, 600
+ #else
+ #error Unsupported CONFIG_SYS_CPU_CLK value
+ #endif
  
 -        setup_pll PLL3_BASE_ADDR, 400
 +      setup_pll PLL3_BASE_ADDR, 400
+ #ifndef CONFIG_TX53
 -        /* Switch peripheral to PLL3 */
 -        ldr r1, =0x00015154
 -        str r1, [r0, #CLKCTL_CBCMR]
 -        ldr r1, =0x02898945
 -        str r1, [r0, #CLKCTL_CBCDR]
 -        /* make sure change is effective */
 +      /* Switch peripheral to PLL3 */
 +      ldr r0, =CCM_BASE_ADDR
 +      ldr r1, =0x00015154
 +      str r1, [r0, #CLKCTL_CBCMR]
 +      ldr r1, =0x02898945
 +      str r1, [r0, #CLKCTL_CBCDR]
 +      /* make sure change is effective */
  1:      ldr r1, [r0, #CLKCTL_CDHIPR]
-       cmp r1, #0x0
+       tst r1, #0x7f
 -        bne 1b
 +      bne 1b
  
 -        setup_pll PLL2_BASE_ADDR, 400
 +      setup_pll PLL2_BASE_ADDR, 400
  
        /* Switch peripheral to PLL2 */
-       ldr r0, =CCM_BASE_ADDR
        ldr r1, =0x00888945
        str r1, [r0, #CLKCTL_CBCDR]
  
  
        /* make sure change is effective */
  1:      ldr r1, [r0, #CLKCTL_CDHIPR]
-       cmp r1, #0x0
+       tst r1, #0x7f
        bne 1b
  
 +      setup_pll PLL3_BASE_ADDR, 216
 +
        setup_pll PLL4_BASE_ADDR, 455
  
+ #else /* CONFIG_TX53 */
+       /* Switch peripheral to PLL 3 */
+       ldr r1, [r0, #CLKCTL_CBCMR]
+       bic r1, #(0x3 << 12)
+       orr r1, r1, #(1 << 12)
+       str r1, [r0, #CLKCTL_CBCMR]
+       ldr r1, [r0, #CLKCTL_CBCDR]
+       orr r1, r1, #(1 << 25)
+       str r1, [r0, #CLKCTL_CBCDR]
+ 1:
+       /* make sure change is effective */
+       ldr r1, [r0, #CLKCTL_CDHIPR]
+       tst r1, #0x7f
+       bne 1b
+ #if CONFIG_SYS_SDRAM_CLK == 533
+       setup_pll PLL2_BASE_ADDR, 533
+ #elif CONFIG_SYS_SDRAM_CLK == 400
+       setup_pll PLL2_BASE_ADDR, 400
+ #elif CONFIG_SYS_SDRAM_CLK == 333
+       setup_pll PLL2_BASE_ADDR, 333
+ #else
+ #error Unsupported CONFIG_SYS_SDRAM_CLK
+ #endif
+       /* Switch peripheral to PLL2 */
+       ldr r1, [r0, #CLKCTL_CBCDR]
+       bic r1, #(1 << 25)
+       str r1, [r0, #CLKCTL_CBCDR]
+       ldr r1, [r0, #CLKCTL_CBCMR]
+       bic r1, #(3 << 12)
+       orr r1, #(2 << 12)
+       str r1, [r0, #CLKCTL_CBCMR]
+ #endif
+         setup_pll PLL3_BASE_ADDR, 216
        /* Set the platform clock dividers */
        ldr r0, =ARM_BASE_ADDR
        ldr r1, =0x00000124
@@@ -83,8 -100,54 +100,12 @@@ static void __imx_get_mac_from_fuse(in
        for (i = 0; i < 6; i++)
                mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  }
+ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+       __attribute__((weak, alias("__imx_get_mac_from_fuse")));
  #endif
  
 -void set_chipselect_size(int const cs_size)
 -{
 -      unsigned int reg;
 -      struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 -      reg = readl(&iomuxc_regs->gpr1);
 -
 -      switch (cs_size) {
 -      case CS0_128:
 -              reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
 -              reg |= 0x5;
 -              break;
 -      case CS0_64M_CS1_64M:
 -              reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
 -              reg |= 0x1B;
 -              break;
 -      case CS0_64M_CS1_32M_CS2_32M:
 -              reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
 -              reg |= 0x4B;
 -              break;
 -      case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
 -              reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
 -              reg |= 0x249;
 -              break;
 -      default:
 -              printf("Unknown chip select size: %d\n", cs_size);
 -              break;
 -      }
 -
 -      writel(reg, &iomuxc_regs->gpr1);
 -}
 -
 -void cpu_cache_initialization(void)
 -{
 -      printf("Enabling L2 cache\n");
 -      asm volatile(
 -              "mrc 15, 0, r0, c1, c0, 1\n"
 -              "orr r0, r0, #0x2\n"
 -              "mcr 15, 0, r0, c1, c0, 1\n"
 -              : : : "r0", "memory"
 -              );
 -}
 -
  #ifdef CONFIG_MX53
  void boot_mode_apply(unsigned cfg_val)
  {
  #include <asm/arch/sys_proto.h>
  
  enum pll_clocks {
-       PLL_SYS,        /* System PLL */
-       PLL_BUS,        /* System Bus PLL*/
-       PLL_USBOTG,     /* OTG USB PLL */
-       PLL_ENET,       /* ENET PLL */
+       PLL_ARM,        /* PLL1: ARM PLL */
 -      PLL_BUS,        /* PLL2: System Bus PLL*/
++      PLL_528,        /* PLL2: System Bus PLL*/
+       PLL_USBOTG,     /* PLL3: OTG USB PLL */
+       PLL_AUDIO,      /* PLL4: Audio PLL */
+       PLL_VIDEO,      /* PLL5: Video PLL */
+       PLL_ENET,       /* PLL6: ENET PLL */
+       PLL_USB2,       /* PLL7: USB2 PLL */
+       PLL_MLB,        /* PLL8: MLB PLL */
  };
  
- struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
+ struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
+ int clk_enable(struct clk *clk)
+ {
+       int ret = 0;
+       if (!clk)
+               return 0;
+       if (clk->usecount == 0) {
 -debug("%s: Enabling %s clock\n", __func__, clk->name);
++              debug("%s: Enabling %s clock\n", __func__, clk->name);
+               ret = clk->enable(clk);
+               if (ret)
+                       return ret;
+               clk->usecount++;
+       }
+       assert(clk->usecount > 0);
+       return ret;
+ }
+ void clk_disable(struct clk *clk)
+ {
+       if (!clk)
+               return;
+       assert(clk->usecount > 0);
+       if (!(--clk->usecount)) {
+               if (clk->disable) {
 -debug("%s: Disabling %s clock\n", __func__, clk->name);
++                      debug("%s: Disabling %s clock\n", __func__, clk->name);
+                       clk->disable(clk);
+               }
+       }
+ }
+ int clk_get_usecount(struct clk *clk)
+ {
+       if (clk == NULL)
+               return 0;
+       return clk->usecount;
+ }
+ u32 clk_get_rate(struct clk *clk)
+ {
+       if (!clk)
+               return 0;
+       return clk->rate;
+ }
+ struct clk *clk_get_parent(struct clk *clk)
+ {
+       if (!clk)
+               return 0;
+       return clk->parent;
+ }
+ int clk_set_rate(struct clk *clk, unsigned long rate)
+ {
+       if (clk && clk->set_rate)
+               clk->set_rate(clk, rate);
+       return clk->rate;
+ }
+ long clk_round_rate(struct clk *clk, unsigned long rate)
+ {
+       if (clk == NULL || !clk->round_rate)
+               return 0;
+       return clk->round_rate(clk, rate);
+ }
+ int clk_set_parent(struct clk *clk, struct clk *parent)
+ {
+       debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
+               clk ? clk->parent : NULL);
+       if (!clk || clk == parent)
+               return 0;
+       if (clk->set_parent) {
+               int ret;
+               ret = clk->set_parent(clk, parent);
+               if (ret)
+                       return ret;
+       }
+       clk->parent = parent;
+       return 0;
+ }
  
  #ifdef CONFIG_MXC_OCOTP
  void enable_ocotp_clk(unsigned char enable)
@@@ -184,57 -169,65 +278,92 @@@ static u32 decode_pll(enum pll_clocks p
        u32 div;
  
        switch (pll) {
-       case PLL_SYS:
-               div = __raw_readl(&imx_ccm->analog_pll_sys);
-               div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
-               return (infreq * div) >> 1;
-       case PLL_BUS:
-               div = __raw_readl(&imx_ccm->analog_pll_528);
+       case PLL_ARM:
+               div = __raw_readl(&anatop->pll_arm);
+               if (div & BM_ANADIG_PLL_ARM_BYPASS)
+                       /* Assume the bypass clock is always derived from OSC */
+                       return infreq;
+               div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
+               return infreq * div / 2;
 -      case PLL_BUS:
++      case PLL_528:
+               div = __raw_readl(&anatop->pll_528);
 -              if (div & BM_ANADIG_PLL_SYS_BYPASS)
++              if (div & BM_ANADIG_PLL_528_BYPASS)
+                       return infreq;
 -              div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 +              div &= BM_ANADIG_PLL_528_DIV_SELECT;
  
-               return infreq * (20 + (div << 1));
+               return infreq * (20 + div * 2);
        case PLL_USBOTG:
-               div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
-               div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
-               return infreq * (20 + (div << 1));
+               div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 -              if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
++              if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+                       return infreq;
 -              div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
++              div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+               return infreq * (20 + div * 2);
+       case PLL_AUDIO:
+               div = __raw_readl(&anatop->pll_audio);
+               if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
+                       return infreq;
+               div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
+               return infreq * div;
+       case PLL_VIDEO:
+               div = __raw_readl(&anatop->pll_video);
+               if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
+                       return infreq;
+               div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+               return infreq * div;
        case PLL_ENET:
-               div = __raw_readl(&imx_ccm->analog_pll_enet);
+               div = __raw_readl(&anatop->pll_enet);
+               if (div & BM_ANADIG_PLL_ENET_BYPASS)
+                       return infreq;
                div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
  
 -              return (div == 3 ? 125000000 : 25000000 * div * 2);
 +              return 25000000 * (div + (div >> 1) + 1);
-       default:
+       case PLL_USB2:
+               div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 -              if (div & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS)
++              if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+                       return infreq;
 -              div &= BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT;
++              div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+               return infreq * (20 + div * 2);
+       case PLL_MLB:
+               div = __raw_readl(&anatop->pll_mlb);
+               if (div & BM_ANADIG_PLL_MLB_BYPASS)
+                       return infreq;
+               /* unknown external clock provided on MLB_CLK pin */
                return 0;
        }
-       /* NOTREACHED */
+       return 0;
  }
-       case PLL_BUS:
 +static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 +{
 +      u32 div;
 +      u64 freq;
++      struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 +
 +      switch (pll) {
-                       /* No PFD3 on PPL2 */
++      case PLL_528:
 +              if (pfd_num == 3) {
-               div = __raw_readl(&imx_ccm->analog_pfd_528);
-               freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
++                      /* No PFD3 on PLL2 */
 +                      return 0;
 +              }
-               div = __raw_readl(&imx_ccm->analog_pfd_480);
++              div = __raw_readl(&anatop->pfd_528);
++              freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 +              break;
 +      case PLL_USBOTG:
-               /* No PFD on other PLL                                       */
++              div = __raw_readl(&anatop->pfd_480);
 +              freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 +              break;
 +      default:
++              /* No PFD on other PLL */
 +              return 0;
 +      }
 +
 +      return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 +                            ANATOP_PFD_FRAC_SHIFT(pfd_num));
 +}
  
  static u32 get_mcu_main_clk(void)
  {
@@@ -276,19 -267,16 +403,17 @@@ u32 get_periph_clk(void
  
                switch (reg) {
                case 0:
--                      freq = decode_pll(PLL_BUS, MXC_HCLK);
++                      freq = decode_pll(PLL_528, MXC_HCLK);
                        break;
                case 1:
-                       freq = mxc_get_pll_pfd(PLL_BUS, 2);
 -                      freq = PLL2_PFD2_FREQ;
++                      freq = mxc_get_pll_pfd(PLL_528, 2);
                        break;
                case 2:
-                       freq = mxc_get_pll_pfd(PLL_BUS, 0);
 -                      freq = PLL2_PFD0_FREQ;
++                      freq = mxc_get_pll_pfd(PLL_528, 0);
                        break;
                case 3:
 -                      freq = PLL2_PFD2_DIV_FREQ;
 +                      /* static / 2 divider */
-                       freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
-                       break;
-               default:
++                      freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
                        break;
                }
        }
@@@ -357,9 -341,9 +482,9 @@@ static u32 get_axi_clk(void
  
        if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
                if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
-                       root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 -                      root_freq = PLL2_PFD2_FREQ;
++                      root_freq = mxc_get_pll_pfd(PLL_528, 2);
                else
 -                      root_freq = PLL3_PFD1_FREQ;
 +                      root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
        } else
                root_freq = get_periph_clk();
  
@@@ -384,17 -368,115 +509,115 @@@ static u32 get_emi_slow_clk(void
                root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
                break;
        case 2:
-               root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 -              root_freq = PLL2_PFD2_FREQ;
++              root_freq =  mxc_get_pll_pfd(PLL_528, 2);
                break;
        case 3:
-               root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 -              root_freq = PLL2_PFD0_FREQ;
++              root_freq =  mxc_get_pll_pfd(PLL_528, 0);
                break;
        }
  
 -      return root_freq / (emi_slow_pof + 1);
 +      return root_freq / (emi_slow_podf + 1);
  }
  
 -              root_freq = PLL2_PFD0_FREQ;
+ static u32 get_nfc_clk(void)
+ {
+       u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
+       u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
+       u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
+       int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
+               MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
+       u32 root_freq;
+       switch (nfc_clk_sel) {
+       case 0:
 -              root_freq = decode_pll(PLL_BUS, MXC_HCLK);
++              root_freq = mxc_get_pll_pfd(PLL_528, 0);
+               break;
+       case 1:
 -              root_freq = PLL2_PFD2_FREQ;
++              root_freq = decode_pll(PLL_528, MXC_HCLK);
+               break;
+       case 2:
+               root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+               break;
+       case 3:
 -                      root_freq = PLL2_PFD0_FREQ;
++              root_freq = mxc_get_pll_pfd(PLL_528, 2);
+               break;
+       }
+       return root_freq / (pred + 1) / (podf + 1);
+ }
+ #define CS2CDR_ENFC_MASK      (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
+                               MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
+                               MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
+ static int set_nfc_clk(u32 ref, u32 freq_khz)
+ {
+       u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
+       u32 podf;
+       u32 pred;
+       int nfc_clk_sel;
+       u32 root_freq;
+       u32 min_err = ~0;
+       u32 nfc_val = ~0;
+       u32 freq = freq_khz * 1000;
+       for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
+               u32 act_freq;
+               u32 err;
+               if (ref < 4 && ref != nfc_clk_sel)
+                       continue;
+               switch (nfc_clk_sel) {
+               case 0:
 -                      root_freq = decode_pll(PLL_BUS, MXC_HCLK);
++                      root_freq = mxc_get_pll_pfd(PLL_528, 0);
+                       break;
+               case 1:
 -                      root_freq = PLL2_PFD2_FREQ;
++                      root_freq = decode_pll(PLL_528, MXC_HCLK);
+                       break;
+               case 2:
+                       root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+                       break;
+               case 3:
 -              podf = min(DIV_ROUND_UP(root_freq, freq), 1 << 6);
 -              pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8);
++                      root_freq = mxc_get_pll_pfd(PLL_528, 2);
+                       break;
+               }
+               if (root_freq < freq)
+                       continue;
 -#ifdef CONFIG_MX6SL
++              podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
++              pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
+               act_freq = root_freq / pred / podf;
+               err = (freq - act_freq) * 100 / freq;
+               debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
+                       nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
+               if (act_freq > freq)
+                       continue;
+               if (err < min_err) {
+                       nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
+                       nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
+                       nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
+                       min_err = err;
+                       if (err == 0)
+                               break;
+               }
+       }
+       if (nfc_val == ~0 || min_err > 10)
+               return -EINVAL;
+       if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
+               debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
+                       (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
+               __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
+                       &imx_ccm->cs2cdr);
+       } else {
+               debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
+       }
+       return 0;
+ }
 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
  static u32 get_mmdc_ch0_clk(void)
  {
        u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
        switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
                MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
        case 0:
--              freq = decode_pll(PLL_BUS, MXC_HCLK);
++              freq = decode_pll(PLL_528, MXC_HCLK);
                break;
        case 1:
-               freq = mxc_get_pll_pfd(PLL_BUS, 2);
 -              freq = PLL2_PFD2_FREQ;
++              freq = mxc_get_pll_pfd(PLL_528, 2);
                break;
        case 2:
-               freq = mxc_get_pll_pfd(PLL_BUS, 0);
 -              freq = PLL2_PFD0_FREQ;
++              freq = mxc_get_pll_pfd(PLL_528, 0);
                break;
        case 3:
 -              freq = PLL2_PFD2_DIV_FREQ;
 +              /* static / 2 divider */
-               freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
++              freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
        }
  
        return freq / (podf + 1);
@@@ -578,9 -551,9 +801,9 @@@ static u32 get_usdhc_clk(u32 port
        }
  
        if (clk_sel)
-               root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 -              root_freq = PLL2_PFD0_FREQ;
++              root_freq = mxc_get_pll_pfd(PLL_528, 0);
        else
-               root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 -              root_freq = PLL2_PFD2_FREQ;
++              root_freq = mxc_get_pll_pfd(PLL_528, 2);
  
        return root_freq / (usdhc_podf + 1);
  }
@@@ -592,175 -565,130 +815,265 @@@ u32 imx_get_uartclk(void
  
  u32 imx_get_fecclk(void)
  {
 -      return decode_pll(PLL_ENET, MXC_HCLK);
 +      return mxc_get_clock(MXC_IPG_CLK);
  }
  
 -int enable_sata_clock(void)
 +static int enable_enet_pll(uint32_t en)
  {
-       struct mxc_ccm_reg *const imx_ccm
-               = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
+       u32 reg;
        s32 timeout = 100000;
-       u32 reg = 0;
  
 -      /* Enable sata clock */
 -      reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
 -      reg |= MXC_CCM_CCGR5_SATA_MASK;
 -      writel(reg, &imx_ccm->CCGR5);
 -
        /* Enable PLLs */
-       reg = readl(&imx_ccm->analog_pll_enet);
-       reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
-       writel(reg, &imx_ccm->analog_pll_enet);
-       reg |= BM_ANADIG_PLL_SYS_ENABLE;
+       reg = readl(&anatop->pll_enet);
+       reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+       writel(reg, &anatop->pll_enet);
+       reg |= BM_ANADIG_PLL_ENET_ENABLE;
        while (timeout--) {
-               if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+               if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
                        break;
        }
        if (timeout <= 0)
                return -EIO;
-       reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
-       writel(reg, &imx_ccm->analog_pll_enet);
+       reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+       writel(reg, &anatop->pll_enet);
 -      reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
 +      reg |= en;
-       writel(reg, &imx_ccm->analog_pll_enet);
+       writel(reg, &anatop->pll_enet);
 +      return 0;
 +}
 +
 +#ifndef CONFIG_MX6SX
 +static void ungate_sata_clock(void)
 +{
 +      struct mxc_ccm_reg *const imx_ccm =
 +              (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  
 -      return 0 ;
 +      /* Enable SATA clock. */
 +      setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 +}
 +#endif
 +
 +static void ungate_pcie_clock(void)
 +{
 +      struct mxc_ccm_reg *const imx_ccm =
 +              (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 +
 +      /* Enable PCIe clock. */
 +      setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 +}
 +
 +#ifndef CONFIG_MX6SX
 +int enable_sata_clock(void)
 +{
 +      ungate_sata_clock();
 +      return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 +}
 +
 +void disable_sata_clock(void)
 +{
 +      struct mxc_ccm_reg *const imx_ccm =
 +              (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 +
 +      clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 +}
 +#endif
 +
 +int enable_pcie_clock(void)
 +{
 +      struct anatop_regs *anatop_regs =
 +              (struct anatop_regs *)ANATOP_BASE_ADDR;
 +      struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 +      u32 lvds1_clk_sel;
 +
 +      /*
 +       * Here be dragons!
 +       *
 +       * The register ANATOP_MISC1 is not documented in the Freescale
 +       * MX6RM. The register that is mapped in the ANATOP space and
 +       * marked as ANATOP_MISC1 is actually documented in the PMU section
 +       * of the datasheet as PMU_MISC1.
 +       *
 +       * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 +       * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 +       * for PCI express link that is clocked from the i.MX6.
 +       */
 +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN                (1 << 12)
 +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN                (1 << 10)
 +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK   0x0000001F
 +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF       0xa
 +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF       0xb
 +
 +      if (is_cpu_type(MXC_CPU_MX6SX))
 +              lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 +      else
 +              lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 +
 +      clrsetbits_le32(&anatop_regs->ana_misc1,
 +                      ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 +                      ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 +                      ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 +
 +      /* PCIe reference clock sourced from AXI. */
 +      clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 +
 +      /* Party time! Ungate the clock to the PCIe. */
 +#ifndef CONFIG_MX6SX
 +      ungate_sata_clock();
 +#endif
 +      ungate_pcie_clock();
 +
 +      return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 +                             BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 +}
 +
 +#ifdef CONFIG_SECURE_BOOT
 +void hab_caam_clock_enable(unsigned char enable)
 +{
 +      u32 reg;
 +
 +      /* CG4 ~ CG6, CAAM clocks */
 +      reg = __raw_readl(&imx_ccm->CCGR0);
 +      if (enable)
 +              reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 +                      MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 +                      MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 +      else
 +              reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 +                      MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 +                      MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 +      __raw_writel(reg, &imx_ccm->CCGR0);
 +
 +      /* EMI slow clk */
 +      reg = __raw_readl(&imx_ccm->CCGR6);
 +      if (enable)
 +              reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
 +      else
 +              reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
 +      __raw_writel(reg, &imx_ccm->CCGR6);
 +}
 +#endif
 +
 +static void enable_pll3(void)
 +{
 +      struct anatop_regs __iomem *anatop =
 +              (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 +
 +      /* make sure pll3 is enabled */
 +      if ((readl(&anatop->usb1_pll_480_ctrl) &
-                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
++                      BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
 +              /* enable pll's power */
-               writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
++              writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
 +                     &anatop->usb1_pll_480_ctrl_set);
 +              writel(0x80, &anatop->ana_misc2_clr);
 +              /* wait for pll lock */
 +              while ((readl(&anatop->usb1_pll_480_ctrl) &
-                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
++                      BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
 +                      ;
 +              /* disable bypass */
-               writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
++              writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
 +                     &anatop->usb1_pll_480_ctrl_clr);
 +              /* enable pll output */
-               writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
++              writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
 +                     &anatop->usb1_pll_480_ctrl_set);
 +      }
 +}
 +
 +void enable_thermal_clk(void)
 +{
 +      enable_pll3();
  }
  
+ void ipu_clk_enable(void)
+ {
+       u32 reg = readl(&imx_ccm->CCGR3);
+       reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
+       writel(reg, &imx_ccm->CCGR3);
+ }
+ void ipu_clk_disable(void)
+ {
+       u32 reg = readl(&imx_ccm->CCGR3);
+       reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
+       writel(reg, &imx_ccm->CCGR3);
+ }
+ void ipu_di_clk_enable(int di)
+ {
+       switch (di) {
+       case 0:
+               setbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
+               break;
+       case 1:
+               setbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
+               break;
+       default:
+               printf("%s: Invalid DI index %d\n", __func__, di);
+       }
+ }
+ void ipu_di_clk_disable(int di)
+ {
+       switch (di) {
+       case 0:
+               clrbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
+               break;
+       case 1:
+               clrbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
+               break;
+       default:
+               printf("%s: Invalid DI index %d\n", __func__, di);
+       }
+ }
+ void ldb_clk_enable(int ldb)
+ {
+       switch (ldb) {
+       case 0:
+               setbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_LDB_DI0_MASK);
+               break;
+       case 1:
+               setbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_LDB_DI1_MASK);
+               break;
+       default:
+               printf("%s: Invalid LDB index %d\n", __func__, ldb);
+       }
+ }
+ void ldb_clk_disable(int ldb)
+ {
+       switch (ldb) {
+       case 0:
+               clrbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_LDB_DI0_MASK);
+               break;
+       case 1:
+               clrbits_le32(&imx_ccm->CCGR3,
+                       MXC_CCM_CCGR3_LDB_DI1_MASK);
+               break;
+       default:
+               printf("%s: Invalid LDB index %d\n", __func__, ldb);
+       }
+ }
+ void ocotp_clk_enable(void)
+ {
+       u32 reg = readl(&imx_ccm->CCGR2);
+       reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+       writel(reg, &imx_ccm->CCGR2);
+ }
+ void ocotp_clk_disable(void)
+ {
+       u32 reg = readl(&imx_ccm->CCGR2);
+       reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+       writel(reg, &imx_ccm->CCGR2);
+ }
  unsigned int mxc_get_clock(enum mxc_clock clk)
  {
        switch (clk) {
                return get_usdhc_clk(3);
        case MXC_SATA_CLK:
                return get_ahb_clk();
-               break;
+       case MXC_NFC_CLK:
+               return get_nfc_clk();
 +      default:
 +              printf("Unsupported MXC CLK: %d\n", clk);
        }
  
 -      return -1;
 +      return 0;
  }
  
+ static inline int gcd(int m, int n)
+ {
+       int t;
+       while (m > 0) {
+               if (n > m) {
+                       t = m;
+                       m = n;
+                       n = t;
+               } /* swap */
+               m -= n;
+       }
+       return n;
+ }
+ /* Config CPU clock */
+ static int set_arm_clk(u32 ref, u32 freq_khz)
+ {
+       int d;
+       int div = 0;
+       int mul = 0;
+       u32 min_err = ~0;
+       u32 reg;
+       if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
+               printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
+                       freq_khz / 1000, freq_khz % 1000,
+                       54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
+                       108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
+               return -EINVAL;
+       }
+       for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
+               int m = freq_khz * 2 * d / (ref / 1000);
+               u32 f;
+               u32 err;
+               if (m > 108) {
+                       debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
+                               d, m);
+                       break;
+               }
+               f = ref * m / d / 2;
+               if (f > freq_khz * 1000) {
+                       debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
+                               d, m, f, freq_khz);
+                       if (--m < 54)
+                               return -EINVAL;
+                       f = ref * m / d / 2;
+               }
+               err = freq_khz * 1000 - f;
+               debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
+                       d, m, f, freq_khz, err);
+               if (err < min_err) {
+                       mul = m;
+                       div = d;
+                       min_err = err;
+                       if (err == 0)
+                               break;
+               }
+       }
+       if (min_err == ~0)
+               return -EINVAL;
+       debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
+               mul, div, freq_khz / 1000, freq_khz % 1000,
+               ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
+       reg = readl(&anatop->pll_arm);
+       debug("anadig_pll_arm=%08x -> %08x\n",
+               reg, (reg & ~0x7f) | mul);
+       reg |= 1 << 16;
+       writel(reg, &anatop->pll_arm); /* bypass PLL */
+       reg = (reg & ~0x7f) | mul;
+       writel(reg, &anatop->pll_arm);
+       writel(div - 1, &imx_ccm->cacrr);
+       reg &= ~(1 << 16);
+       writel(reg, &anatop->pll_arm); /* disable PLL bypass */
+       return 0;
+ }
  /*
-  * Dump some core clockes.
+  * This function assumes the expected core clock has to be changed by
+  * modifying the PLL. This is NOT true always but for most of the times,
+  * it is. So it assumes the PLL output freq is the same as the expected
+  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+  * In the latter case, it will try to increase the presc value until
+  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+  * on the targeted PLL and reference input clock to the PLL. Lastly,
+  * it sets the register based on these values along with the dividers.
+  * Note 1) There is no value checking for the passed-in divider values
+  *         so the caller has to make sure those values are sensible.
+  *      2) Also adjust the NFC divider such that the NFC clock doesn't
+  *         exceed NFC_CLK_MAX.
+  *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
+  *         177MHz for higher voltage, this function fixes the max to 133MHz.
+  *      4) This function should not have allowed diag_printf() calls since
+  *         the serial driver has been stoped. But leave then here to allow
+  *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
   */
- int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
- {
-       u32 freq;
-       freq = decode_pll(PLL_SYS, MXC_HCLK);
-       printf("PLL_SYS    %8d MHz\n", freq / 1000000);
-       freq = decode_pll(PLL_BUS, MXC_HCLK);
-       printf("PLL_BUS    %8d MHz\n", freq / 1000000);
-       freq = decode_pll(PLL_USBOTG, MXC_HCLK);
-       printf("PLL_OTG    %8d MHz\n", freq / 1000000);
-       freq = decode_pll(PLL_ENET, MXC_HCLK);
-       printf("PLL_NET    %8d MHz\n", freq / 1000000);
+ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+ {
+       int ret;
+       freq *= 1000;
+       switch (clk) {
+       case MXC_ARM_CLK:
+               ret = set_arm_clk(ref, freq);
+               break;
+       case MXC_NFC_CLK:
+               ret = set_nfc_clk(ref, freq);
+               break;
+       default:
+               printf("Warning: Unsupported or invalid clock type: %d\n",
+                       clk);
+               return -EINVAL;
+       }
+       return ret;
+ }
+ /*
+  * Dump some core clocks.
+  */
+ #define print_pll(pll)        {                               \
+       u32 __pll = decode_pll(pll, MXC_HCLK);          \
+       printf("%-12s %4d.%03d MHz\n", #pll,            \
+               __pll / 1000000, __pll / 1000 % 1000);  \
+       }
+ #define MXC_IPG_PER_CLK       MXC_IPG_PERCLK
  
 -      print_pll(PLL_BUS);
+ #define print_clk(clk)        {                               \
+       u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
+       printf("%-12s %4d.%03d MHz\n", #clk,            \
+               __clk / 1000000, __clk / 1000 % 1000);  \
+       }
+ #define print_pfd(pll, pfd)   {                                       \
+       u32 __pfd = readl(&anatop->pfd_##pll);                          \
+       if (__pfd & (0x80 << 8 * pfd)) {                                \
+               printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
+       } else {                                                        \
+               __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
+               printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
+                       pll * 18 / __pfd,                               \
+                       pll * 18 * 1000 / __pfd % 1000);                \
+       }                                                               \
+ }
+ static void do_mx6_showclocks(void)
+ {
+       print_pll(PLL_ARM);
++      print_pll(PLL_528);
+       print_pll(PLL_USBOTG);
+       print_pll(PLL_AUDIO);
+       print_pll(PLL_VIDEO);
+       print_pll(PLL_ENET);
+       print_pll(PLL_USB2);
        printf("\n");
-       printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
-       printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
- #ifdef CONFIG_MXC_SPI
-       printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
- #endif
-       printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
-       printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
-       printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-       printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
-       printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
-       printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
-       printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
-       printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
-       printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
  
-       return 0;
+       print_pfd(480, 0);
+       print_pfd(480, 1);
+       print_pfd(480, 2);
+       print_pfd(480, 3);
+       print_pfd(528, 0);
+       print_pfd(528, 1);
+       print_pfd(528, 2);
+       printf("\n");
+       print_clk(IPG);
+       print_clk(UART);
+       print_clk(CSPI);
+       print_clk(AHB);
+       print_clk(AXI);
+       print_clk(DDR);
+       print_clk(ESDHC);
+       print_clk(ESDHC2);
+       print_clk(ESDHC3);
+       print_clk(ESDHC4);
+       print_clk(EMI_SLOW);
+       print_clk(NFC);
+       print_clk(IPG_PER);
+       print_clk(ARM);
+ }
+ static struct clk_lookup {
+       const char *name;
+       unsigned int index;
+ } mx6_clk_lookup[] = {
+       { "arm", MXC_ARM_CLK, },
+       { "nfc", MXC_NFC_CLK, },
+ };
+ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+       int i;
+       unsigned long freq;
+       unsigned long ref = ~0UL;
+       if (argc < 2) {
+               do_mx6_showclocks();
+               return CMD_RET_SUCCESS;
+       } else if (argc == 2 || argc > 4) {
+               return CMD_RET_USAGE;
+       }
+       freq = simple_strtoul(argv[2], NULL, 0);
+       if (freq == 0) {
+               printf("Invalid clock frequency %lu\n", freq);
+               return CMD_RET_FAILURE;
+       }
+       if (argc > 3) {
+               ref = simple_strtoul(argv[3], NULL, 0);
+       }
+       for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
+               if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
+                       switch (mx6_clk_lookup[i].index) {
+                       case MXC_ARM_CLK:
+                               if (argc > 3)
+                                       return CMD_RET_USAGE;
 -                              ref = CONFIG_SYS_MX6_HCLK;
++                              ref = MXC_HCLK;
+                               break;
+                       case MXC_NFC_CLK:
+                               if (argc > 3 && ref > 3) {
+                                       printf("Invalid clock selector value: %lu\n", ref);
+                                       return CMD_RET_FAILURE;
+                               }
+                               break;
+                       }
+                       printf("Setting %s clock to %lu MHz\n",
+                               mx6_clk_lookup[i].name, freq);
+                       if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
+                               break;
+                       freq = mxc_get_clock(mx6_clk_lookup[i].index);
+                       printf("%s clock set to %lu.%03lu MHz\n",
+                               mx6_clk_lookup[i].name,
+                               freq / 1000000, freq / 1000 % 1000);
+                       return CMD_RET_SUCCESS;
+               }
+       }
+       if (i == ARRAY_SIZE(mx6_clk_lookup)) {
+               printf("clock %s not found; supported clocks are:\n", argv[1]);
+               for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
+                       printf("\t%s\n", mx6_clk_lookup[i].name);
+               }
+       } else {
+               printf("Failed to set clock %s to %s MHz\n",
+                       argv[1], argv[2]);
+       }
+       return CMD_RET_FAILURE;
  }
  
 +#ifndef CONFIG_MX6SX
 +void enable_ipu_clock(void)
 +{
 +      struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 +      int reg;
 +      reg = readl(&mxc_ccm->CCGR3);
 +      reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 +      writel(reg, &mxc_ccm->CCGR3);
 +}
 +#endif
  /***************************************************/
  
  U_BOOT_CMD(
  #include <asm/imx-common/boot_mode.h>
  #include <asm/imx-common/dma.h>
  #include <stdbool.h>
 -#ifdef CONFIG_VIDEO_IPUV3
 +#include <asm/arch/mxc_hdmi.h>
 +#include <asm/arch/crm_regs.h>
 +#include <asm/bootm.h>
 +#include <dm.h>
 +#include <imx_thermal.h>
++#include <div64.h>
+ #include <ipu.h>
 -#endif
+ DECLARE_GLOBAL_DATA_PTR;
++#define __data __attribute__((section(".data")))
++
+ #ifdef CONFIG_MX6_TEMPERATURE_MIN
+ #define TEMPERATURE_MIN                       CONFIG_MX6_TEMPERATURE_MIN
+ #else
+ #define TEMPERATURE_MIN                       (-40)
+ #endif
+ #ifdef CONFIG_MX6_TEMPERATURE_HOT
+ #define TEMPERATURE_HOT                       CONFIG_MX6_TEMPERATURE_HOT
+ #else
+ #define TEMPERATURE_HOT                       80
+ #endif
+ #ifdef CONFIG_MX6_TEMPERATURE_MAX
+ #define TEMPERATURE_MAX                       CONFIG_MX6_TEMPERATURE_MAX
+ #else
+ #define TEMPERATURE_MAX                       125
+ #endif
+ #define TEMP_AVG_COUNT                        5
+ #define TEMP_WARN_THRESHOLD           5
  
 -#define __data        __attribute__((section(".data")))
 +enum ldo_reg {
 +      LDO_ARM,
 +      LDO_SOC,
 +      LDO_PU,
 +};
  
  struct scu_regs {
        u32     ctrl;
@@@ -192,39 -161,185 +218,210 @@@ static int set_ldo_voltage(enum ldo_re
        else
                val = (mv - 700) / 25;
  
 +      clear_ldo_ramp();
 +
 +      switch (ldo) {
 +      case LDO_SOC:
 +              shift = 18;
 +              break;
 +      case LDO_PU:
 +              shift = 9;
 +              break;
 +      case LDO_ARM:
 +              shift = 0;
 +              break;
 +      default:
 +              return -EINVAL;
 +      }
 +
 +      old = (reg & (0x1F << shift)) >> shift;
 +      step = abs(val - old);
 +      if (step == 0)
 +              return 0;
 +
 +      reg = (reg & ~(0x1F << shift)) | (val << shift);
 +      writel(reg, &anatop->reg_core);
 +
        /*
 -       * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
 -       * and set them to the calculated value (0.7V + val * 0.25V)
 +       * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
 +       * step
         */
 -      reg = (reg & ~(0x1F << 18)) | (val << 18);
 -      writel(reg, &anatop->reg_core);
 +      udelay(3 * step);
 +
 +      return 0;
  }
  
+ static u32 __data thermal_calib;
+ #define FACTOR0                               10000000
+ #define FACTOR1                               15976
+ #define FACTOR2                               4297157
+ int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
+               unsigned int hot_temp)
+ {
+       int temperature;
+       if (raw_hot != 0 && hot_temp != 0) {
+               unsigned int raw_n40c, ratio;
+               ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
+               raw_n40c = raw_25c + (13 * ratio) / 20;
+               if (raw <= raw_n40c)
+                       temperature = (raw_n40c - raw) * 100 / ratio - 40;
+               else
+                       temperature = TEMPERATURE_MIN;
+       } else {
+               u64 temp64 = FACTOR0;
+               unsigned int c1, c2;
+               /*
+                * Derived from linear interpolation:
+                * slope = 0.4297157 - (0.0015976 * 25C fuse)
+                * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
+                * (Nmeas - n1) / (Tmeas - t1) = slope
+                * We want to reduce this down to the minimum computation necessary
+                * for each temperature read.  Also, we want Tmeas in millicelsius
+                * and we don't want to lose precision from integer division. So...
+                * Tmeas = (Nmeas - n1) / slope + t1
+                * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
+                * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
+                * Let constant c1 = (-1000 / slope)
+                * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
+                * Let constant c2 = n1 *c1 + 1000 * t1
+                * milli_Tmeas = c2 - Nmeas * c1
+                */
+               temp64 *= 1000;
+               do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
+               c1 = temp64;
+               c2 = raw_25c * c1 + 1000 * 25;
+               temperature = (c2 - raw * c1) / 1000;
+       }
+       return temperature;
+ }
+ int read_cpu_temperature(void)
+ {
+       unsigned int reg, tmp, i;
+       unsigned int raw_25c, raw_hot, hot_temp;
+       int temperature;
+       struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
+       struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
+       if (!thermal_calib) {
+               ocotp_clk_enable();
+               writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
+               thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
+               writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
+               ocotp_clk_disable();
+       }
+       if (thermal_calib == 0 || thermal_calib == 0xffffffff)
+               return TEMPERATURE_MIN;
+       /* Fuse data layout:
+        * [31:20] sensor value @ 25C
+        * [19:8] sensor value of hot
+        * [7:0] hot temperature value */
+       raw_25c = thermal_calib >> 20;
+       raw_hot = (thermal_calib & 0xfff00) >> 8;
+       hot_temp = thermal_calib & 0xff;
+       /* now we only using single measure, every time we measure
+        * the temperature, we will power on/off the anadig module
+        */
+       writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
+       writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+       /* write measure freq */
+       writel(327, &anatop->tempsense1);
+       writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
+       writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
+       writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
+       /* average the temperature value over multiple readings */
+       for (i = 0; i < TEMP_AVG_COUNT; i++) {
+               static int failed;
+               int limit = 100;
+               while ((readl(&anatop->tempsense0) &
+                               BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
+                       udelay(10000);
+                       if (--limit < 0)
+                               break;
+               }
+               if ((readl(&anatop->tempsense0) &
+                               BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
+                       if (!failed) {
+                               printf("Failed to read temp sensor\n");
+                               failed = 1;
+                       }
+                       return 0;
+               }
+               failed = 0;
+               reg = (readl(&anatop->tempsense0) &
+                       BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
+                       BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
+               if (i == 0)
+                       tmp = reg;
+               else
+                       tmp = (tmp * i + reg) / (i + 1);
+               writel(BM_ANADIG_TEMPSENSE0_FINISHED,
+                       &anatop->tempsense0_clr);
+       }
+       temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
+       /* power down anatop thermal sensor */
+       writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
+       writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
+       return temperature;
+ }
+ int check_cpu_temperature(int boot)
+ {
+       static int __data max_temp;
+       int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
+       int tmp = read_cpu_temperature();
+       bool first = true;
+       if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
+               printf("Temperature:   can't get valid data!\n");
+               return tmp;
+       }
+       if (!boot) {
+               if (tmp > boot_limit) {
+                       printf("CPU is %d C, too hot, resetting...\n", tmp);
+                       udelay(100000);
+                       reset_cpu(0);
+               }
+               if (tmp > max_temp) {
+                       if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
+                               printf("WARNING: CPU temperature %d C\n", tmp);
+                       max_temp = tmp;
+               }
+       } else {
+               printf("Temperature:   %d C, calibration data 0x%x\n",
+                       tmp, thermal_calib);
+               while (tmp >= boot_limit) {
+                       if (first) {
+                               printf("CPU is %d C, too hot to boot, waiting...\n",
+                                       tmp);
+                               first = false;
+                       }
+                       if (ctrlc())
+                               break;
+                       udelay(50000);
+                       tmp = read_cpu_temperature();
+                       if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
+                               printf("WARNING: CPU temperature %d C\n", tmp);
+                       max_temp = tmp;
+               }
+       }
+       return tmp;
+ }
  static void imx_set_wdog_powerdown(bool enable)
  {
        struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
@@@ -289,20 -359,17 +486,24 @@@ int arch_cpu_init(void
  
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
  
- #ifdef CONFIG_APBH_DMA
-       /* Start APBH DMA */
+ #ifdef CONFIG_VIDEO_IPUV3
+       gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
+ #endif
+ #ifdef  CONFIG_APBH_DMA
+       /* Timer is required for Initializing APBH DMA */
+       timer_init();
        mxs_dma_init();
  #endif
 +
 +      return 0;
 +}
 +
 +int board_postclk_init(void)
 +{
 +      set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 +
        return 0;
  }
 -#endif
  
  #ifndef CONFIG_SYS_DCACHE_OFF
  void enable_caches(void)
@@@ -33,14 -30,6 +33,19 @@@ void imx_iomux_v3_setup_pad(iomux_v3_cf
                (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
  
 +#if defined CONFIG_MX6SL
 +      /* Check whether LVE bit needs to be set */
 +      if (pad_ctrl & PAD_CTL_LVE) {
 +              pad_ctrl &= ~PAD_CTL_LVE;
 +              pad_ctrl |= PAD_CTL_LVE_BIT;
 +      }
 +#endif
++#ifdef DEBUG
++      printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
++              i, pad, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
++              pad & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
++#endif
 +
        if (mux_ctrl_ofs)
                __raw_writel(mux_mode, base + mux_ctrl_ofs);
  
@@@ -62,33 -50,24 +67,28 @@@ void imx_iomux_v3_setup_multiple_pads(i
                                      unsigned count)
  {
        iomux_v3_cfg_t const *p = pad_list;
 +      int stride;
        int i;
  
 -      for (i = 0; i < count; i++) {
 -#ifdef DEBUG
 -              u32 mux_ctrl_ofs = (*p & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
 -              u32 mux_mode = (*p & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
 -              u32 sel_input_ofs =
 -                      (*p & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
 -              u32 sel_input =
 -                      (*p & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
 -              u32 pad_ctrl_ofs =
 -                      (*p & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
 -              u32 pad_ctrl = (*p & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 -
 -              printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
 -                      i, *p, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
 -                      *p & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
 +#if defined(CONFIG_MX6QDL)
 +      stride = 2;
 +      if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
 +              p += 1;
 +#else
 +      stride = 1;
  #endif
 -              imx_iomux_v3_setup_pad(*p++);
 +      for (i = 0; i < count; i++) {
 +              imx_iomux_v3_setup_pad(*p);
 +              p += stride;
        }
  }
-                                       int num_bits, int value)
 +
 +void imx_iomux_set_gpr_register(int group, int start_bit,
-       int i = 0;
-       u32 reg;
-       reg = readl(base + group * 4);
-       while (num_bits) {
-               reg &= ~(1<<(start_bit + i));
-               i++;
-               num_bits--;
-       }
-       reg |= (value << start_bit);
++                              int num_bits, int value)
 +{
++      u32 reg = readl(base + group * 4);
++
++      reg &= ~(((1 << num_bits) - 1) << start_bit);
++      reg |= value << start_bit;
 +      writel(reg, base + group * 4);
 +}
@@@ -75,11 -39,18 +75,20 @@@ static inline unsigned long long tick_t
        return tick;
  }
  
+ static inline unsigned long time_to_tick(unsigned long time)
+ {
+       unsigned long long ticks = (unsigned long long)time;
+       ticks *= MXC_CLK32;
+       do_div(ticks, CONFIG_SYS_HZ);
+       return ticks;
+ }
  static inline unsigned long long us_to_tick(unsigned long long usec)
  {
 -      usec = usec * MXC_CLK32 + 999999;
 +      ulong gpt_clk = gpt_get_clk();
 +
 +      usec = usec * gpt_clk + 999999;
        do_div(usec, 1000000);
  
        return usec;
  #ifndef _CLOCKS_AM33XX_H_
  #define _CLOCKS_AM33XX_H_
  
 +/* MAIN PLL Fdll supported frequencies */
 +#define MPUPLL_M_1000 1000
 +#define MPUPLL_M_800  800
 +#define MPUPLL_M_720  720
 +#define MPUPLL_M_600  600
 +#define MPUPLL_M_550  550
 +#define MPUPLL_M_300  300
 +
  /* MAIN PLL Fdll = 550 MHz, by default */
  #ifndef CONFIG_SYS_MPUCLK
 -#define CONFIG_SYS_MPUCLK     550
 +#define CONFIG_SYS_MPUCLK     MPUPLL_M_550
  #endif
  
 -extern void pll_init(void);
 -extern void enable_emif_clocks(void);
+ #define DISPPLL_M     200
+ #define DISPPLL_N     (OSC - 1)
+ #define DISPPLL_M2    1
 +#define UART_RESET            (0x1 << 1)
 +#define UART_CLK_RUNNING_MASK 0x1
 +#define UART_SMART_IDLE_EN    (0x1 << 0x3)
 +
 +#define CM_DLL_CTRL_NO_OVERRIDE       0x0
 +#define CM_DLL_READYST                0x4
 +
  extern void enable_dmm_clocks(void);
 +extern const struct dpll_params dpll_core_opp100;
 +extern struct dpll_params dpll_mpu_opp100;
  
  #endif        /* endif _CLOCKS_AM33XX_H_ */
  #define TCLR_ST                               BIT(0)  /* Start=1 Stop=0 */
  #define TCLR_AR                               BIT(1)  /* Auto reload */
  #define TCLR_PRE                      BIT(5)  /* Pre-scaler enable */
- #define TCLR_PTV_SHIFT                        (2)     /* Pre-scaler shift value */
+ #define TCLR_PTV_SHIFT                        2       /* Pre-scaler shift value */
  #define TCLR_PRE_DISABLE              CL_BIT(5) /* Pre-scalar disable */
 +#define TCLR_CE                               BIT(6)  /* compare mode enable */
 +#define TCLR_SCPWM                    BIT(7)  /* pwm outpin behaviour */
 +#define TCLR_TCM                      BIT(8)  /* edge detection of input pin*/
 +#define TCLR_TRG_SHIFT                        (10)    /* trigmode on pwm outpin */
 +#define TCLR_PT                               BIT(12) /* pulse/toggle mode of outpin*/
 +#define TCLR_CAPTMODE                 BIT(13) /* capture mode */
 +#define TCLR_GPOCFG                   BIT(14) /* 0=output,1=input */
  
 +#define TCFG_RESET                    BIT(0)  /* software reset */
 +#define TCFG_EMUFREE                  BIT(1)  /* behaviour of tmr on debug */
 +#define TCFG_IDLEMOD_SHIFT            (2)     /* power management */
  /* device type */
  #define DEVICE_MASK                   (BIT(8) | BIT(9) | BIT(10))
  #define TST_DEVICE                    0x0
  #define AM335X                                0xB944
  #define TI81XX                                0xB81E
  #define DEVICE_ID                     (CTRL_BASE + 0x0600)
 +#define DEVICE_ID_MASK                        0x1FFF
 +
 +/* MPU max frequencies */
 +#define AM335X_ZCZ_300                        0x1FEF
 +#define AM335X_ZCZ_600                        0x1FAF
 +#define AM335X_ZCZ_720                        0x1F2F
 +#define AM335X_ZCZ_800                        0x1E2F
 +#define AM335X_ZCZ_1000                       0x1C2F
 +#define AM335X_ZCE_300                        0x1FDF
 +#define AM335X_ZCE_600                        0x1F9F
  
  /* This gives the status of the boot mode pins on the evm */
- #define SYSBOOT_MASK                  (BIT(0) | BIT(1) | BIT(2)\
-                                       | BIT(3) | BIT(4))
+ #define SYSBOOT_MASK                  (BIT(0) | BIT(1) | BIT(2) | \
+                                               BIT(3) | BIT(4))
  
 -/* Reset control */
 -#ifdef CONFIG_AM33XX
 -#define PRM_RSTCTRL                   (PRCM_BASE + 0x0F00)
 -#elif defined(CONFIG_TI814X)
 -#define PRM_RSTCTRL                   (PRCM_BASE + 0x00A0)
 -#endif
 -#define PRM_RSTST                     (PRM_RSTCTRL + 8)
  #define PRM_RSTCTRL_RESET             0x01
  #define PRM_RSTST_WARM_RESET_MASK     0x232
  
@@@ -464,9 -303,7 +466,9 @@@ struct ctrl_stat 
        unsigned int resv1[16];
        unsigned int statusreg;         /* ofset 0x40 */
        unsigned int resv2[51];
-       unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
+       unsigned int emif_sdram_config; /* offset 0x0110 */
 +      unsigned int resv3[319];
 +      unsigned int dev_attr;
  };
  
  /* AM33XX GPIO registers */
@@@ -508,72 -339,19 +510,80 @@@ struct ctrl_dev 
        unsigned int macid1h;           /* offset 0x3c */
        unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
 +      unsigned int resv5[7];
 +      unsigned int mreqprio_0;        /* offset 0x70 */
 +      unsigned int mreqprio_1;        /* offset 0x74 */
 +      unsigned int resv6[97];
 +      unsigned int efuse_sma;         /* offset 0x1FC */
 +};
 +
 +/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
 +#define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
 +#define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
 +#define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
 +
 +struct l3f_cfg_bwlimiter {
 +      u32 padding0[2];
 +      u32 modena_init0_bw_fractional;
 +      u32 modena_init0_bw_integer;
 +      u32 modena_init0_watermark_0;
 +};
 +
 +/* gmii_sel register defines */
 +#define GMII1_SEL_MII         0x0
 +#define GMII1_SEL_RMII                0x1
 +#define GMII1_SEL_RGMII               0x2
 +#define GMII2_SEL_MII         0x0
 +#define GMII2_SEL_RMII                0x4
 +#define GMII2_SEL_RGMII               0x8
 +#define RGMII1_IDMODE         BIT(4)
 +#define RGMII2_IDMODE         BIT(5)
 +#define RMII1_IO_CLK_EN               BIT(6)
 +#define RMII2_IO_CLK_EN               BIT(7)
 +
 +#define MII_MODE_ENABLE               (GMII1_SEL_MII | GMII2_SEL_MII)
 +#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
 +#define RGMII_MODE_ENABLE     (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
 +#define RGMII_INT_DELAY               (RGMII1_IDMODE | RGMII2_IDMODE)
 +#define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 +
 +/* PWMSS */
 +struct pwmss_regs {
 +      unsigned int idver;
 +      unsigned int sysconfig;
 +      unsigned int clkconfig;
 +      unsigned int clkstatus;
 +};
 +#define ECAP_CLK_EN           BIT(0)
 +#define ECAP_CLK_STOP_REQ     BIT(1)
 +
 +struct pwmss_ecap_regs {
 +      unsigned int tsctr;
 +      unsigned int ctrphs;
 +      unsigned int cap1;
 +      unsigned int cap2;
 +      unsigned int cap3;
 +      unsigned int cap4;
 +      unsigned int resv1[4];
 +      unsigned short ecctl1;
 +      unsigned short ecctl2;
  };
  
 -void init_timer(void);
 +/* Capture Control register 2 */
 +#define ECTRL2_SYNCOSEL_MASK  (0x03 << 6)
 +#define ECTRL2_MDSL_ECAP      BIT(9)
 +#define ECTRL2_CTRSTP_FREERUN BIT(4)
 +#define ECTRL2_PLSL_LOW               BIT(10)
 +#define ECTRL2_SYNC_EN                BIT(5)
  
 -unsigned long lcdc_clk_rate(void);
+ #define clk_get_rate(c,p)                                     \
+       __clk_get_rate(readl(&(c)->clkseldpll##p),              \
+               readl(&(c)->divm2dpll##p))
+ unsigned long __clk_get_rate(u32 m_n, u32 div_m2);
+ unsigned long mpu_clk_rate(void);
  #endif /* __ASSEMBLY__ */
  #endif /* __KERNEL_STRICT_NAMES */
  
  /* AM335X EMIF Register values */
  #define VTP_CTRL_READY                (0x1 << 5)
  #define VTP_CTRL_ENABLE               (0x1 << 6)
- #define VTP_CTRL_START_EN     (0x1)
+ #define VTP_CTRL_FILTER_SHIFT 1
+ #define VTP_CTRL_FILTER_MASK  (0x7 << VTP_CTRL_FILTER_SHIFT)
+ #define VTP_CTRL_FILTER(n)    (((n) << VTP_CTRL_FILTER_SHIFT) & VTP_CTRL_FILTER_MASK)
+ #define VTP_CTRL_START_EN     (0x1 << 0)
+ #define PHY_DLL_LOCK_DIFF     0x0
 +#ifdef CONFIG_AM43XX
 +#define DDR_CKE_CTRL_NORMAL   0x3
 +#else
  #define DDR_CKE_CTRL_NORMAL   0x1
 +#endif
  #define PHY_EN_DYN_PWRDN      (0x1 << 20)
  
  /* Micron MT47H128M16RT-25E */
  #define AM33XX_GPIO1_BASE       0x4804C000
  #define AM33XX_GPIO2_BASE       0x481AC000
  #define AM33XX_GPIO3_BASE       0x481AE000
 +#define AM33XX_GPIO4_BASE     0x48320000
 +#define AM33XX_GPIO5_BASE     0x48322000
  
+ #define AM33XX_GPIO_NR(bank, pin)     (((bank) << 5) | (pin))
 +/* GPIO CTRL register */
 +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
 +#define GPIO_CTRL_DISABLEMODULE_MASK  (1 << 0)
 +#define GPIO_CTRL_ENABLEMODULE                GPIO_CTRL_DISABLEMODULE_MASK
 +
 +/* GPIO OUTPUT ENABLE register */
 +#define GPIO_OE_ENABLE(x)             (1 << x)
 +
 +/* GPIO SETDATAOUT register */
 +#define GPIO_SETDATAOUT(x)            (1 << x)
  #endif /* _GPIO_AM33xx_H */
@@@ -44,15 -94,30 +94,31 @@@ struct clk 
  u32 imx_get_uartclk(void);
  u32 imx_get_fecclk(void);
  unsigned int mxc_get_clock(enum mxc_clock clk);
- int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
+ int adjust_core_voltage(u32 freq);
  void set_usb_phy_clk(void);
 -void enable_usb_phy1_clk(unsigned char enable);
 -void enable_usb_phy2_clk(unsigned char enable);
 +void enable_usb_phy1_clk(bool enable);
 +void enable_usb_phy2_clk(bool enable);
  void set_usboh3_clk(void);
 -void enable_usboh3_clk(unsigned char enable);
 +void enable_usboh3_clk(bool enable);
  void mxc_set_sata_internal_clock(void);
  int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  void enable_nfc_clk(unsigned char enable);
 +void enable_efuse_prog_supply(bool enable);
+ void ipu_clk_enable(void);
+ void ipu_clk_disable(void);
+ void ipu_di_clk_enable(int di);
+ void ipu_di_clk_disable(int di);
+ #ifdef CONFIG_MX53
+ void ldb_clk_enable(int ldb);
+ void ldb_clk_disable(int ldb);
+ #else
+ static inline void ldb_clk_enable(int ldb)
+ {
+ }
+ static inline void ldb_clk_disable(int ldb)
+ {
+ }
+ #endif /* CONFIG_MX53 */
  
  #endif /* __ASM_ARCH_CLOCK_H */
@@@ -303,11 -303,8 +303,11 @@@ struct mxc_ccm_reg 
  #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)            ((r) & 0x7)
  
  /* Define the bits in register CCDR */
- #define MXC_CCM_CCDR_IPU_HS_MASK                      (0x1 << 17)
+ #define MXC_CCM_CCDR_IPU_HS_MASK                      (0x1 << 21)
  
 +/* Define the bits in register CGPR */
 +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE           (1 << 4)
 +
  /* Define the bits in register CCGRx */
  #define MXC_CCM_CCGR_CG_MASK                          0x3
  #define MXC_CCM_CCGR_CG_OFF                           0x0
@@@ -42,31 -42,68 +42,86 @@@ enum mxc_clock 
        MXC_I2C_CLK,
  };
  
 +enum enet_freq {
 +      ENET_25MHZ,
 +      ENET_50MHZ,
 +      ENET_100MHZ,
 +      ENET_125MHZ,
 +};
  
+ struct clk {
+       const char *name;
+       int id;
+       /* Source clock this clk depends on */
+       struct clk *parent;
+       /* Secondary clock to enable/disable with this clock */
+       struct clk *secondary;
+       /* Current clock rate */
+       unsigned long rate;
+       /* Reference count of clock enable/disable */
+       __s8 usecount;
+       /* Register bit position for clock's enable/disable control. */
+       u8 enable_shift;
+       /* Register address for clock's enable/disable control. */
+       void *enable_reg;
+       u32 flags;
+       /*
+        * Function ptr to recalculate the clock's rate based on parent
+        * clock's rate
+        */
+       void (*recalc) (struct clk *);
+       /*
+        * Function ptr to set the clock to a new rate. The rate must match a
+        * supported rate returned from round_rate. Leave blank if clock is not
+       * programmable
+        */
+       int (*set_rate) (struct clk *, unsigned long);
+       /*
+        * Function ptr to round the requested clock rate to the nearest
+        * supported rate that is less than or equal to the requested rate.
+        */
+       unsigned long (*round_rate) (struct clk *, unsigned long);
+       /*
+        * Function ptr to enable the clock. Leave blank if clock can not
+        * be gated.
+        */
+       int (*enable) (struct clk *);
+       /*
+        * Function ptr to disable the clock. Leave blank if clock can not
+        * be gated.
+        */
+       void (*disable) (struct clk *);
+       /* Function ptr to set the parent clock of the clock. */
+       int (*set_parent) (struct clk *, struct clk *);
+ };
  u32 imx_get_uartclk(void);
  u32 imx_get_fecclk(void);
  unsigned int mxc_get_clock(enum mxc_clock clk);
+ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
 +void setup_gpmi_io_clk(u32 cfg);
 +void hab_caam_clock_enable(unsigned char enable);
  void enable_ocotp_clk(unsigned char enable);
  void enable_usboh3_clk(unsigned char enable);
 +void enable_uart_clk(unsigned char enable);
 +int enable_cspi_clock(unsigned char enable, unsigned spi_num);
 +int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
  int enable_sata_clock(void);
 +void disable_sata_clock(void);
 +int enable_pcie_clock(void);
  int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 -
 +int enable_spi_clk(unsigned char enable, unsigned spi_num);
 +void enable_ipu_clock(void);
 +int enable_fec_anatop_clock(enum enet_freq freq);
 +void enable_enet_clk(unsigned char enable);
 +void enable_qspi_clk(int qspi_num);
 +void enable_thermal_clk(void);
+ void ipu_clk_enable(void);
+ void ipu_clk_disable(void);
+ void ipu_di_clk_enable(int di);
+ void ipu_di_clk_disable(int di);
+ void ldb_clk_enable(int ldb);
+ void ldb_clk_disable(int ldb);
+ void ocotp_clk_enable(void);
+ void ocotp_clk_disable(void);
  #endif /* __ASM_ARCH_CLOCK_H */
@@@ -55,69 -55,61 +55,21 @@@ struct mxc_ccm_reg 
        u32 CCGR6;      /* 0x0080 */
        u32 CCGR7;
        u32 cmeor;
-       u32 resv[0xfdd];
-       u32 analog_pll_sys;                     /* 0x4000 */
-       u32 analog_pll_sys_set;
-       u32 analog_pll_sys_clr;
-       u32 analog_pll_sys_tog;
-       u32 analog_usb1_pll_480_ctrl;           /* 0x4010 */
-       u32 analog_usb1_pll_480_ctrl_set;
-       u32 analog_usb1_pll_480_ctrl_clr;
-       u32 analog_usb1_pll_480_ctrl_tog;
-       u32 analog_reserved0[4];
-       u32 analog_pll_528;                     /* 0x4030 */
-       u32 analog_pll_528_set;
-       u32 analog_pll_528_clr;
-       u32 analog_pll_528_tog;
-       u32 analog_pll_528_ss;                  /* 0x4040 */
-       u32 analog_reserved1[3];
-       u32 analog_pll_528_num;                 /* 0x4050 */
-       u32 analog_reserved2[3];
-       u32 analog_pll_528_denom;               /* 0x4060 */
-       u32 analog_reserved3[3];
-       u32 analog_pll_audio;                   /* 0x4070 */
-       u32 analog_pll_audio_set;
-       u32 analog_pll_audio_clr;
-       u32 analog_pll_audio_tog;
-       u32 analog_pll_audio_num;               /* 0x4080*/
-       u32 analog_reserved4[3];
-       u32 analog_pll_audio_denom;             /* 0x4090 */
-       u32 analog_reserved5[3];
-       u32 analog_pll_video;                   /* 0x40a0 */
-       u32 analog_pll_video_set;
-       u32 analog_pll_video_clr;
-       u32 analog_pll_video_tog;
-       u32 analog_pll_video_num;               /* 0x40b0 */
-       u32 analog_reserved6[3];
-       u32 analog_pll_video_denom;             /* 0x40c0 */
-       u32 analog_reserved7[7];
-       u32 analog_pll_enet;                    /* 0x40e0 */
-       u32 analog_pll_enet_set;
-       u32 analog_pll_enet_clr;
-       u32 analog_pll_enet_tog;
-       u32 analog_pfd_480;                     /* 0x40f0 */
-       u32 analog_pfd_480_set;
-       u32 analog_pfd_480_clr;
-       u32 analog_pfd_480_tog;
-       u32 analog_pfd_528;                     /* 0x4100 */
-       u32 analog_pfd_528_set;
-       u32 analog_pfd_528_clr;
-       u32 analog_pfd_528_tog;
  };
 -
 -struct anatop_regs {
 -      mxs_reg_32(pll_arm);            /* 0x000 */
 -      mxs_reg_32(usb1_pll_480_ctrl);  /* 0x010 */
 -      mxs_reg_32(usb2_pll_480_ctrl);  /* 0x020 */
 -      mxs_reg_32(pll_528);            /* 0x030 */
 -      reg_32(pll_528_ss);             /* 0x040 */
 -      reg_32(pll_528_num);            /* 0x050 */
 -      reg_32(pll_528_denom);          /* 0x060 */
 -      mxs_reg_32(pll_audio);          /* 0x070 */
 -      reg_32(pll_audio_num);          /* 0x080 */
 -      reg_32(pll_audio_denom);        /* 0x090 */
 -      mxs_reg_32(pll_video);          /* 0x0a0 */
 -      reg_32(pll_video_num);          /* 0x0b0 */
 -      reg_32(pll_video_denom);        /* 0x0c0 */
 -      mxs_reg_32(pll_mlb);            /* 0x0d0 */
 -      mxs_reg_32(pll_enet);           /* 0x0e0 */
 -      mxs_reg_32(pfd_480);            /* 0x0f0 */
 -      mxs_reg_32(pfd_528);            /* 0x100 */
 -      mxs_reg_32(reg_1p1);            /* 0x110 */
 -      mxs_reg_32(reg_3p0);            /* 0x120 */
 -      mxs_reg_32(reg_2p5);            /* 0x130 */
 -      mxs_reg_32(reg_core);           /* 0x140 */
 -      mxs_reg_32(ana_misc0);          /* 0x150 */
 -      mxs_reg_32(ana_misc1);          /* 0x160 */
 -      mxs_reg_32(ana_misc2);          /* 0x170 */
 -      mxs_reg_32(tempsense0);         /* 0x180 */
 -      mxs_reg_32(tempsense1);         /* 0x190 */
 -      mxs_reg_32(usb1_vbus_detect);   /* 0x1a0 */
 -      mxs_reg_32(usb1_chrg_detect);   /* 0x1b0 */
 -      mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
 -      mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
 -      mxs_reg_32(usb1_loopback);      /* 0x1e0 */
 -      mxs_reg_32(usb1_misc);          /* 0x1f0 */
 -      mxs_reg_32(usb2_vbus_detect);   /* 0x200 */
 -      mxs_reg_32(usb2_chrg_detect);   /* 0x210 */
 -      mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */
 -      mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */
 -      mxs_reg_32(usb2_loopback);      /* 0x240 */
 -      mxs_reg_32(usb2_misc);          /* 0x250 */
 -      reg_32(digprog);                /* 0x260 */
 -      reg_32(rsrvd);                  /* 0x270 */
 -      reg_32(digprog_sololite);       /* 0x280 */
 -};
  #endif
  
  /* Define the bits in register CCR */
  #define MXC_CCM_CCR_RBC_EN                            (1 << 27)
- #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                       (0x3F << 21)
+ #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                       (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
  #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET             21
- #define MXC_CCM_CCR_WB_COUNT_MASK                     0x7
+ #define MXC_CCM_CCR_WB_COUNT_MASK                     (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
  #define MXC_CCM_CCR_WB_COUNT_OFFSET                   (1 << 16)
  #define MXC_CCM_CCR_COSC_EN                           (1 << 12)
 -#define MXC_CCM_CCR_OSCNT_MASK                                (0xFF << MXC_CCM_CCR_OSCNT_OFFSET)
 +#ifdef CONFIG_MX6SX
 +#define MXC_CCM_CCR_OSCNT_MASK                                0x7F
 +#else
 +#define MXC_CCM_CCR_OSCNT_MASK                                0xFF
 +#endif
  #define MXC_CCM_CCR_OSCNT_OFFSET                      0
  
  /* Define the bits in register CCDR */
  #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET         27
  #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                        (1 << 26)
  #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                  (1 << 25)
- #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK              (0x7 << 19)
 +#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK              (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
  #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET            19
- #define MXC_CCM_CBCDR_AXI_PODF_MASK                   (0x7 << 16)
 +#endif
+ #define MXC_CCM_CBCDR_AXI_PODF_MASK                   (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
  #define MXC_CCM_CBCDR_AXI_PODF_OFFSET                 16
- #define MXC_CCM_CBCDR_AHB_PODF_MASK                   (0x7 << 10)
+ #define MXC_CCM_CBCDR_AHB_PODF_MASK                   (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
  #define MXC_CCM_CBCDR_AHB_PODF_OFFSET                 10
- #define MXC_CCM_CBCDR_IPG_PODF_MASK                   (0x3 << 8)
+ #define MXC_CCM_CBCDR_IPG_PODF_MASK                   (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
  #define MXC_CCM_CBCDR_IPG_PODF_OFFSET                 8
  #define MXC_CCM_CBCDR_AXI_ALT_SEL                     (1 << 7)
  #define MXC_CCM_CBCDR_AXI_SEL                         (1 << 6)
  #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET                0
  
  /* Define the bits in register CBCMR */
- #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK          (0x7 << 29)
+ #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK          (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
  #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET                29
- #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK            (0x7 << 26)
+ #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK            (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
  #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET          26
- #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK            (0x7 << 23)
+ #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK            (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
  #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET          23
- #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK                (0x3 << 21)
+ #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK                (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
  #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET      21
  #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL            (1 << 20)
- #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK         (0x3 << 18)
+ #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK         (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
  #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET               18
- #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK              (0x3 << 16)
 +#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK              (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
  #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET            16
- #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK            (0x3 << 14)
+ #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK            (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
  #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET          14
- #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK            (0x3 << 12)
 +#endif
+ #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK            (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
  #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET          12
 +#ifndef CONFIG_MX6SX
  #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                  (1 << 11)
 +#endif
  #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                        (1 << 10)
- #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK               (0x3 << 8)
+ #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK               (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
  #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET     8
- #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK         (0x3 << 4)
+ #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK         (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
  #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET               4
 +#ifndef CONFIG_MX6SX
  #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                       (1 << 1)
  #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                       (1 << 0)
 +#endif
  
  /* Define the bits in register CSCMR1 */
- #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK             (0x3 << 29)
+ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK             (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
  #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET           29
- #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                        (0x7 << 26)
 +#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR1_ACLK_EMI_MASK                  (0x3 << 27)
++#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                        (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
 +#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET              26
 +#else
+ #define MXC_CCM_CSCMR1_ACLK_EMI_MASK                  (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
  #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET                        27
- #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK                (0x7 << 23)
 +#endif
+ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK                (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
  #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET      23
- #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK             (0x7 << 20)
 +/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
+ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK             (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
  #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET           20
  #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL                 (1 << 19)
  #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL                 (1 << 18)
  #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL                 (1 << 17)
  #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL                 (1 << 16)
- #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK              (0x3 << 14)
+ #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK              (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
  #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET            14
- #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK              (0x3 << 12)
+ #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK              (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
  #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET            12
- #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK              (0x3 << 10)
+ #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK              (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
  #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET            10
- #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK             (0x7 << 7)
 +#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                       (1 << 6)
++#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK             (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET           7
 +#endif
 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                       0x3F
++#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                       (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
 +#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET             6
 +#endif
+ #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET             0
+ #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                       (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
  
  /* Define the bits in register CSCMR2 */
- #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                       (0x7 << 21)
 +#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK              (0x3 << 19)
++#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                       (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
 +#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET             21
 +#endif
+ #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK              (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
  #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET            19
  #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                        (1 << 11)
  #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                        (1 << 10)
- #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                       (0x3 << 8)
 +#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK              (0x3F << 2)
++#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                       (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
 +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET             8
- #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                       (0x3F << 2)
++#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
 +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET            2
 +#else
+ #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                       (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
  #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET             2
 +#endif
  
  /* Define the bits in register CSCDR1 */
- #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK              (0x7 << 25)
 +#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK              (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
  #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET            25
- #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                       (0x7 << 22)
 +#endif
+ #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                       (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
  #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET             22
- #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                       (0x7 << 19)
+ #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                       (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
  #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET             19
- #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK                       (0x7 << 16)
+ #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK                       (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
  #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET             16
- #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                       (0x7 << 11)
+ #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                       (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
  #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET             11
 +#ifndef CONFIG_MX6SX
  #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET         8
- #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK           (0x7 << 8)
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK           (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
  #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET         6
- #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK           (0x3 << 6)
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK           (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 +#endif
  #ifdef CONFIG_MX6SL
- #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK             0x1F
- #define MXC_CCM_CSCDR1_UART_CLK_SEL                   (1 << 6)
+ #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK             (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
+ #define MXC_CCM_CSCDR1_UART_CLK_SEL                   (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
  #else
- #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK             0x3F
+ #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK             (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 +#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCDR1_UART_CLK_SEL                   (1 << 6)
++#define MXC_CCM_CSCDR1_UART_CLK_SEL                   (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 +#endif
  #endif
+ #define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET            6
  #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET           0
  
  /* Define the bits in register CS1CDR */
- #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK             (0x3F << 25)
+ #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK             (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
  #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET           25
- #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK             (0x7 << 22)
++#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK             (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
 +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET           22
- #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK             (0x3F << 16)
+ #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK             (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
  #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET           16
- #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK             (0x3 << 9)
+ #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK             (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
  #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET           9
- #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK             (0x7 << 6)
+ #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK             (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
  #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET           6
- #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK             0x3F
+ #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK             (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
  #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET           0
  
  /* Define the bits in register CS2CDR */
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << 21)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                       (((v) & 0x3f) << 21)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK             (0x7 << 18)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET           18
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)                       (((v) & 0x7) << 18)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK              (0x7 << 15)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET            15
- #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                        (((v) & 0x7) << 15)
 +#ifdef CONFIG_MX6SX
- #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK             (0x3F << 21)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK            (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET          21
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)              (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK            (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET          18
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)              (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK             (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET           15
++#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                       (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
 +#else
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK             (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
  #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET           21
- #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                       (((v) & 0x3f) << 21)
- #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK             (0x7 << 18)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                       (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK             (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
  #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET           18
- #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                       (((v) & 0x7) << 18)
- #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK              (0x3 << 16)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                       (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK              (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
  #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET            16
- #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)                        (((v) & 0x3) << 16)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)                        (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
 +#endif
- #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK           (0x7 << 12)
+ #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK           (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET         12
- #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK           (0x7 << 9)
+ #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK           (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET         9
- #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK             (0x7 << 6)
+ #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK             (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
  #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET           6
- #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK             0x3F
+ #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK             (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
  #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET           0
  
  /* Define the bits in register CDCDR */
- #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                        (0x7 << 29)
 +#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                        (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
  #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET              29
--#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL                  (1 << 28)
++#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK             (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
++#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET           28
 +#endif
- #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK            (0x7 << 25)
+ #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK            (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
  #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET          25
- #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK            (0x7 << 22)
+ #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK            (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
 -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET          19
 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET          22
- #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK             (0x3 << 20)
+ #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK             (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
  #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET           20
- #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK            (0x7 << 12)
+ #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK            (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
  #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET          12
- #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK            (0x7 << 9)
+ #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK            (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
  #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET          9
- #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK             (0x3 << 7)
+ #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK             (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
  #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET           7
  
  /* Define the bits in register CHSCCDR */
- #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK         (0x7 << 15)
 +#ifdef CONFIG_MX6SX
- #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                        (0x7 << 12)
++#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK         (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
 +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET               15
- #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK             (0x7 << 9)
++#define MXC_CCM_CHSCCDR_ENET_PODF_MASK                        (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
 +#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET              12
- #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK           (0x7 << 6)
++#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK             (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
 +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET           9
- #define MXC_CCM_CHSCCDR_M4_PODF_MASK                  (0x7 << 3)
++#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK           (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
 +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET         6
- #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK                       (0x7)
++#define MXC_CCM_CHSCCDR_M4_PODF_MASK                  (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
 +#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET                        3
- #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK     (0x7 << 15)
++#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK                       (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
 +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET             0
 +#else
+ #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK     (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
  #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET   15
- #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK            (0x7 << 12)
+ #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK            (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
  #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET          12
- #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK         (0x7 << 9)
+ #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK         (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
  #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET               9
- #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK     (0x7 << 6)
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK     (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
  #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET   6
- #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK            (0x7 << 3)
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK            (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
  #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET          3
- #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK         (0x7)
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK         (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
  #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET               0
 +#endif
  
- #define CHSCCDR_CLK_SEL_LDB_DI0                               3
- #define CHSCCDR_PODF_DIVIDE_BY_3                      2
- #define CHSCCDR_IPU_PRE_CLK_540M_PFD                  5
  /* Define the bits in register CSCDR2 */
- #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK            (0x3F << 19)
+ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK            (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
  #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET          19
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK     (0x7 << 15)
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET   15
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK            (0x7 << 12)
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET          12
- #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK         (0x7 << 9)
- #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET               9
 +/* All IPU2_DI1 are LCDIF1 on MX6SX */
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK     (0x7 << 6)
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET   6
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK            (0x7 << 3)
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET          3
- #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK         0x7
- #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET               0
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK      (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET    15
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK             (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET           12
+ #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK          (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET                9
 +/* All IPU2_DI0 are LCDIF2 on MX6SX */
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK      (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET    6
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK             (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET           3
+ #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK          (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET                0
  
  /* Define the bits in register CSCDR3 */
- #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK             (0x7 << 16)
+ #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK             (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
  #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET           16
- #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK          (0x3 << 14)
+ #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK          (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
  #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET                14
- #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK             (0x7 << 11)
+ #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK             (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
  #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET           11
- #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK          (0x3 << 9)
+ #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK          (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
  #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET                9
  
  /* Define the bits in register CDHIPR */
  #define MXC_CCM_CLPCR_MASK_CORE3_WFI                  (1 << 25)
  #define MXC_CCM_CLPCR_MASK_CORE2_WFI                  (1 << 24)
  #define MXC_CCM_CLPCR_MASK_CORE1_WFI                  (1 << 23)
 +#endif
  #define MXC_CCM_CLPCR_MASK_CORE0_WFI                  (1 << 22)
  #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS             (1 << 21)
 +#ifndef CONFIG_MX6SX
  #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS             (1 << 19)
  #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                  (1 << 17)
 -#define MXC_CCM_CLPCR_WB_PER_AT_LPM                   (1 << 17)
 +#endif
 +#define MXC_CCM_CLPCR_WB_PER_AT_LPM                   (1 << 16)
  #define MXC_CCM_CLPCR_COSC_PWRDOWN                    (1 << 11)
- #define MXC_CCM_CLPCR_STBY_COUNT_MASK                 (0x3 << 9)
+ #define MXC_CCM_CLPCR_STBY_COUNT_MASK                 (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
  #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                       9
  #define MXC_CCM_CLPCR_VSTBY                           (1 << 8)
  #define MXC_CCM_CLPCR_DIS_REF_OSC                     (1 << 7)
  #define MXC_CCM_CLPCR_SBYOS                           (1 << 6)
  #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM              (1 << 5)
- #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                       (0x3 << 3)
 +#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                       (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
  #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET             3
  #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY         (1 << 2)
- #define MXC_CCM_CLPCR_LPM_MASK                                0x3
 +#endif
+ #define MXC_CCM_CLPCR_LPM_MASK                                (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
  #define MXC_CCM_CLPCR_LPM_OFFSET                      0
  
  /* Define the bits in register CISR */
  #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED               (1 << 22)
  #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED                (1 << 21)
  #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED             (1 << 20)
 -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED      (1 << 22)
 +#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED      (1 << 19)
  #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED             (1 << 17)
  #define MXC_CCM_CIMR_MASK_COSC_READY                  (1 << 6)
- #define MXC_CCM_CIMR_MASK_LRF_PLL                     1
+ #define MXC_CCM_CIMR_MASK_LRF_PLL                     (1 << 0)
  
  /* Define the bits in register CCOSR */
  #define MXC_CCM_CCOSR_CKO2_EN_OFFSET                  (1 << 24)
- #define MXC_CCM_CCOSR_CKO2_DIV_MASK                   (0x7 << 21)
+ #define MXC_CCM_CCOSR_CKO2_DIV_MASK                   (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
  #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                 21
  #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                 16
- #define MXC_CCM_CCOSR_CKO2_SEL_MASK                   (0x1F << 16)
+ #define MXC_CCM_CCOSR_CKO2_SEL_MASK                   (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
 +#define MXC_CCM_CCOSR_CLK_OUT_SEL                     (0x1 << 8)
  #define MXC_CCM_CCOSR_CKOL_EN                         (0x1 << 7)
- #define MXC_CCM_CCOSR_CKOL_DIV_MASK                   (0x7 << 4)
+ #define MXC_CCM_CCOSR_CKOL_DIV_MASK                   (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
  #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                 4
- #define MXC_CCM_CCOSR_CKOL_SEL_MASK                   0xF
+ #define MXC_CCM_CCOSR_CKOL_SEL_MASK                   (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
  #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                 0
  
  /* Define the bits in registers CGPR */
 +#define MXC_CCM_CGPR_FAST_PLL_EN                      (1 << 16)
  #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE           (1 << 4)
  #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS                 (1 << 2)
- #define MXC_CCM_CGPR_PMIC_DELAY_SCALER                        1
+ #define MXC_CCM_CGPR_PMIC_DELAY_SCALER                        (1 << 0)
  
  /* Define the bits in registers CCGRx */
  #define MXC_CCM_CCGR_CG_MASK                          3
  #define MXC_CCM_CCGR5_UART_MASK                               (3 << MXC_CCM_CCGR5_UART_OFFSET)
  #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET              26
  #define MXC_CCM_CCGR5_UART_SERIAL_MASK                        (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
 +#ifdef CONFIG_MX6SX
 +#define MXC_CCM_CCGR5_SAI1_OFFSET                     20
 +#define MXC_CCM_CCGR5_SAI1_MASK                               (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
 +#define MXC_CCM_CCGR5_SAI2_OFFSET                     30
 +#define MXC_CCM_CCGR5_SAI2_MASK                               (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
 +#endif
  
- #define MXC_CCM_CCGR6_USBOH3_OFFSET           0
- #define MXC_CCM_CCGR6_USBOH3_MASK             (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
- #define MXC_CCM_CCGR6_USDHC1_OFFSET           2
- #define MXC_CCM_CCGR6_USDHC1_MASK             (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
- #define MXC_CCM_CCGR6_USDHC2_OFFSET           4
- #define MXC_CCM_CCGR6_USDHC2_MASK             (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
- #define MXC_CCM_CCGR6_USDHC3_OFFSET           6
- #define MXC_CCM_CCGR6_USDHC3_MASK             (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
- #define MXC_CCM_CCGR6_USDHC4_OFFSET           8
- #define MXC_CCM_CCGR6_USDHC4_MASK             (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
- #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET         10
- #define MXC_CCM_CCGR6_EMI_SLOW_MASK           (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+ #define MXC_CCM_CCGR6_USBOH3_OFFSET                   0
+ #define MXC_CCM_CCGR6_USBOH3_MASK                     (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC1_OFFSET                   2
+ #define MXC_CCM_CCGR6_USDHC1_MASK                     (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC2_OFFSET                   4
+ #define MXC_CCM_CCGR6_USDHC2_MASK                     (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC3_OFFSET                   6
+ #define MXC_CCM_CCGR6_USDHC3_MASK                     (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC4_OFFSET                   8
+ #define MXC_CCM_CCGR6_USDHC4_MASK                     (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+ #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                 10
+ #define MXC_CCM_CCGR6_EMI_SLOW_MASK                   (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+ #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET                        12
+ #define MXC_CCM_CCGR6_VDOAXICLK_MASK                  (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+ #define ANATOP_PFD_480_PFD0_FRAC_SHIFT                        0
+ #define ANATOP_PFD_480_PFD0_FRAC_MASK                 (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD0_STABLE_SHIFT              6
+ #define ANATOP_PFD_480_PFD0_STABLE_MASK                       (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT             7
+ #define ANATOP_PFD_480_PFD0_CLKGATE_MASK              (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
+ #define ANATOP_PFD_480_PFD1_FRAC_SHIFT                        8
+ #define ANATOP_PFD_480_PFD1_FRAC_MASK                 (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD1_STABLE_SHIFT              14
+ #define ANATOP_PFD_480_PFD1_STABLE_MASK                       (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT             15
+ #define ANATOP_PFD_480_PFD1_CLKGATE_MASK              (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
+ #define ANATOP_PFD_480_PFD2_FRAC_SHIFT                        16
+ #define ANATOP_PFD_480_PFD2_FRAC_MASK                 (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD2_STABLE_SHIFT              22
+ #define ANATOP_PFD_480_PFD2_STABLE_MASK                       (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT             23
+ #define ANATOP_PFD_480_PFD2_CLKGATE_MASK              (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
+ #define ANATOP_PFD_480_PFD3_FRAC_SHIFT                        24
+ #define ANATOP_PFD_480_PFD3_FRAC_MASK                 (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD3_STABLE_SHIFT              30
+ #define ANATOP_PFD_480_PFD3_STABLE_MASK                       (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT             31
+ #define BM_ANADIG_PLL_ARM_LOCK                                (1 << 31)
+ #define BM_ANADIG_PLL_ARM_PLL_SEL                     (1 << 19)
+ #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL              (1 << 18)
+ #define BM_ANADIG_PLL_ARM_LVDS_SEL                    (1 << 17)
+ #define BM_ANADIG_PLL_ARM_BYPASS                      (1 << 16)
+ #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC              14
+ #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC              (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
 -#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v)                           \
 -      (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
 -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M     BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0)
 -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1    BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1)
 -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2    BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2)
 -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR         BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3)
++#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v)        \
++      (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
++              BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M     0x0
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1    0x1
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2    0x2
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR         0x3
+ #define BM_ANADIG_PLL_ARM_ENABLE                      (1 << 13)
+ #define BM_ANADIG_PLL_ARM_POWERDOWN                   (1 << 12)
+ #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF                       (1 << 11)
+ #define BM_ANADIG_PLL_ARM_DOUBLE_CP                   (1 << 10)
+ #define BM_ANADIG_PLL_ARM_HALF_CP                     (1 << 9)
+ #define BM_ANADIG_PLL_ARM_DOUBLE_LF                   (1 << 8)
+ #define BM_ANADIG_PLL_ARM_HALF_LF                     (1 << 7)
+ #define BP_ANADIG_PLL_ARM_DIV_SELECT                  0
+ #define BM_ANADIG_PLL_ARM_DIV_SELECT                  (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
 -#define BF_ANADIG_PLL_ARM_DIV_SELECT(v)                       \
 -      (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) &        \
++#define BF_ANADIG_PLL_ARM_DIV_SELECT(v)                \
++      (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
+               BM_ANADIG_PLL_ARM_DIV_SELECT)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK              (1 << 31)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS            (1 << 16)
 -#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC    14
 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC    (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
 -#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)                 \
 -      (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) &          \
 -              BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M   BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(0)
 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1  BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1)
 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2  BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2)
 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR               BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE            (1 << 13)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_POWER             (1 << 12)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF     (1 << 11)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP         (1 << 10)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP           (1 << 9)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF         (1 << 8)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF           (1 << 7)
 -#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS               (1 << 6)
 -#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0          2
 -#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0          (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
 -#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)                       \
 -      (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) &        \
 -              BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
 -#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT                0
 -#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT                (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
 -#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)             \
 -      (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) &      \
 -              BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
 -
 -#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK              (1 << 31)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS            (1 << 16)
 -#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC    14
 -#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC    (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
 -#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v)         \
 -      (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) &  \
 -              BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
 -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M   BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0)
 -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1  BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1)
 -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2  BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2)
 -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR               BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE            (1 << 13)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_POWER             (1 << 12)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF     (1 << 11)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP         (1 << 10)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP           (1 << 9)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF         (1 << 8)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF           (1 << 7)
 -#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS               (1 << 6)
 -#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0          2
 -#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0          (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
 -#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v)                       \
 -      (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) &        \
 -              BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
 -#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT                0
 -#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT                (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
 -#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v)             \
 -      (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) &      \
 -              BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
 -
 -#define BM_ANADIG_PLL_SYS_LOCK                                (1 << 31)
 -#define BM_ANADIG_PLL_SYS_PLL_SEL                     (1 << 19)
 -#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL              (1 << 18)
 -#define BM_ANADIG_PLL_SYS_LVDS_SEL                    (1 << 17)
 -#define BM_ANADIG_PLL_SYS_BYPASS                      (1 << 16)
 -#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC              14
 -#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC              (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
 -#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)                           \
 -      (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M     0x0
 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1    0x1
 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2    0x2
 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR         0x3
 -#define BM_ANADIG_PLL_SYS_ENABLE                      (1 << 13)
 -#define BM_ANADIG_PLL_SYS_POWERDOWN                   (1 << 12)
 -#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF                       (1 << 11)
 -#define BM_ANADIG_PLL_SYS_DOUBLE_CP                   (1 << 10)
 -#define BM_ANADIG_PLL_SYS_HALF_CP                     (1 << 9)
 -#define BM_ANADIG_PLL_SYS_DOUBLE_LF                   (1 << 8)
 -#define BM_ANADIG_PLL_SYS_HALF_LF                     (1 << 7)
 -#define BP_ANADIG_PLL_SYS_DIV_SELECT                  0
 -#define BM_ANADIG_PLL_SYS_DIV_SELECT                  (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
 -#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)                                       \
 -      (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT)
++#define BM_ANADIG_PLL_528_CTRL_LOCK                   (1 << 31)
++#define BM_ANADIG_PLL_528_PFD_OFFSET_EN                       (1 << 18)
++#define BM_ANADIG_PLL_528_DITHER_ENABLE                       (1 << 17)
++#define BM_ANADIG_PLL_528_CTRL_BYPASS                 (1 << 16)
++#define BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC         14
++#define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC         (0x3 << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC(v)        \
++      (((v) << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) & \
++              BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M        0x0
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1       0x1
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_2       0x2
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__XOR    0x3
++#define BM_ANADIG_PLL_528_CTRL_ENABLE                 (1 << 13)
++#define BM_ANADIG_PLL_528_CTRL_POWER                  (1 << 12)
++#define BM_ANADIG_PLL_528_CTRL_HOLD_RING_OFF          (1 << 11)
++#define BM_ANADIG_PLL_528_CTRL_DOUBLE_CP              (1 << 10)
++#define BM_ANADIG_PLL_528_CTRL_HALF_CP                        (1 << 9)
++#define BM_ANADIG_PLL_528_CTRL_DOUBLE_LF              (1 << 8)
++#define BM_ANADIG_PLL_528_CTRL_HALF_LF                        (1 << 7)
++#define BM_ANADIG_PLL_528_CTRL_EN_USB_CLKS            (1 << 6)
++#define BP_ANADIG_PLL_528_CTRL_CONTROL0                       2
++#define BM_ANADIG_PLL_528_CTRL_CONTROL0                       (0x7 << BP_ANADIG_PLL_528_CTRL_CONTROL0)
++#define BF_ANADIG_PLL_528_CTRL_CONTROL0(v)            \
++      (((v) << BP_ANADIG_PLL_528_CTRL_CONTROL0) &     \
++              BM_ANADIG_PLL_528_CTRL_CONTROL0)
++#define BP_ANADIG_PLL_528_CTRL_DIV_SELECT             0
++#define BM_ANADIG_PLL_528_CTRL_DIV_SELECT             (0x3 << BP_ANADIG_PLL_528_CTRL_DIV_SELECT)
++#define BF_ANADIG_PLL_528_CTRL_DIV_SELECT(v)          \
++      (((v) << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) &   \
++              BM_ANADIG_PLL_528_CTRL_DIV_SELECT)
+ #define BM_ANADIG_PLL_AUDIO_LOCK                      (1 << 31)
+ #define BM_ANADIG_PLL_AUDIO_SSC_EN                    (1 << 21)
+ #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT           19
+ #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT           (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+ #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)                                \
+       (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+ #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN             (1 << 18)
+ #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE             (1 << 17)
+ #define BM_ANADIG_PLL_AUDIO_BYPASS                    (1 << 16)
+ #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC            14
+ #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC            (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
 -#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)         \
++#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)                         \
+       (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M   0x0
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1  0x1
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2  0x2
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR               0x3
+ #define BM_ANADIG_PLL_AUDIO_ENABLE                    (1 << 13)
+ #define BM_ANADIG_PLL_AUDIO_POWERDOWN                 (1 << 12)
+ #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF             (1 << 11)
+ #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP                 (1 << 10)
+ #define BM_ANADIG_PLL_AUDIO_HALF_CP                   (1 << 9)
+ #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF                 (1 << 8)
+ #define BM_ANADIG_PLL_AUDIO_HALF_LF                   (1 << 7)
+ #define BP_ANADIG_PLL_AUDIO_DIV_SELECT                        0
+ #define BM_ANADIG_PLL_AUDIO_DIV_SELECT                        (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
 -#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)                             \
 -      (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
++#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)        \
++      (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
++              BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+ #define BP_ANADIG_PLL_AUDIO_NUM_A                     0
 -#define BM_ANADIG_PLL_AUDIO_NUM_A                     0x3FFFFFFF
 -#define BF_ANADIG_PLL_AUDIO_NUM_A(v)                                  \
 -      (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A)
++#define BM_ANADIG_PLL_AUDIO_NUM_A                     (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
++#define BF_ANADIG_PLL_AUDIO_NUM_A(v)        \
++      (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
++              BM_ANADIG_PLL_AUDIO_NUM_A)
+ #define BP_ANADIG_PLL_AUDIO_DENOM_B                   0
 -#define BM_ANADIG_PLL_AUDIO_DENOM_B                   0x3FFFFFFF
 -#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)                                        \
 -      (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B)
++#define BM_ANADIG_PLL_AUDIO_DENOM_B                   (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
++#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)                \
++      (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
++              BM_ANADIG_PLL_AUDIO_DENOM_B)
+ #define BM_ANADIG_PLL_VIDEO_LOCK                      (1 << 31)
+ #define BM_ANADIG_PLL_VIDEO_SSC_EN                    (1 << 21)
+ #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT           19
+ #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT           (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
 -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)                                \
 -      (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
++#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)                \
++      (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & \
++              BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+ #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN             (1 << 18)
+ #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE             (1 << 17)
+ #define BM_ANADIG_PLL_VIDEO_BYPASS                    (1 << 16)
+ #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC            14
+ #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC            (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
 -#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)                         \
 -      (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)        \
++      (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
++              BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M   0x0
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1  0x1
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2  0x2
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR               0x3
+ #define BM_ANADIG_PLL_VIDEO_ENABLE                    (1 << 13)
+ #define BM_ANADIG_PLL_VIDEO_POWERDOWN                 (1 << 12)
+ #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF             (1 << 11)
+ #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP                 (1 << 10)
+ #define BM_ANADIG_PLL_VIDEO_HALF_CP                   (1 << 9)
+ #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF                 (1 << 8)
+ #define BM_ANADIG_PLL_VIDEO_HALF_LF                   (1 << 7)
+ #define BP_ANADIG_PLL_VIDEO_DIV_SELECT                        0
+ #define BM_ANADIG_PLL_VIDEO_DIV_SELECT                        (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
 -#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)                             \
 -      (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
++#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)        \
++      (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
++              BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+ #define BP_ANADIG_PLL_VIDEO_NUM_A                     0
+ #define BM_ANADIG_PLL_VIDEO_NUM_A                     (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
 -#define BF_ANADIG_PLL_VIDEO_NUM_A(v)                                  \
 -      (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A)
++#define BF_ANADIG_PLL_VIDEO_NUM_A(v)        \
++      (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
++              BM_ANADIG_PLL_VIDEO_NUM_A)
+ #define BP_ANADIG_PLL_VIDEO_DENOM_B                   0
+ #define BM_ANADIG_PLL_VIDEO_DENOM_B                   (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
 -#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)                                        \
 -      (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B)
++#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)                \
++      (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
++              BM_ANADIG_PLL_VIDEO_DENOM_B)
+ #define BM_ANADIG_PLL_MLB_LOCK                                (1 << 31)
+ #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG         26
+ #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG         (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
 -#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v)                      \
 -      (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v)        \
++      (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
++              BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+ #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG              23
+ #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG              (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
 -#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v)                           \
 -      (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v)        \
++      (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
++              BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+ #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG                        20
+ #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG                        (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
 -#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v)                             \
 -      (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v)        \
++      (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
++              BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+ #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG                        17
+ #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG                        (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
 -#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v)                             \
 -      (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v)        \
++      (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
++              BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+ #define BM_ANADIG_PLL_MLB_BYPASS                      (1 << 16)
+ #define BP_ANADIG_PLL_MLB_PHASE_SEL                   12
+ #define BM_ANADIG_PLL_MLB_PHASE_SEL                   (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
 -#define BF_ANADIG_PLL_MLB_PHASE_SEL(v)                                \
 -      (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL)
++#define BF_ANADIG_PLL_MLB_PHASE_SEL(v)                \
++      (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
++              BM_ANADIG_PLL_MLB_PHASE_SEL)
+ #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF                       (1 << 11)
+ #define BM_ANADIG_PLL_ENET_LOCK                               (1 << 31)
+ #define BM_ANADIG_PLL_ENET_ENABLE_SATA                        (1 << 20)
+ #define BM_ANADIG_PLL_ENET_ENABLE_PCIE                        (1 << 19)
+ #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN              (1 << 18)
+ #define BM_ANADIG_PLL_ENET_DITHER_ENABLE              (1 << 17)
+ #define BM_ANADIG_PLL_ENET_BYPASS                     (1 << 16)
+ #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC             14
+ #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC             (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
 -#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)                          \
 -      (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)        \
++      (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
++              BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M    0x0
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1   0x1
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2   0x2
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR                0x3
+ #define BM_ANADIG_PLL_ENET_ENABLE                     (1 << 13)
+ #define BM_ANADIG_PLL_ENET_POWERDOWN                  (1 << 12)
+ #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF              (1 << 11)
+ #define BM_ANADIG_PLL_ENET_DOUBLE_CP                  (1 << 10)
+ #define BM_ANADIG_PLL_ENET_HALF_CP                    (1 << 9)
+ #define BM_ANADIG_PLL_ENET_DOUBLE_LF                  (1 << 8)
+ #define BM_ANADIG_PLL_ENET_HALF_LF                    (1 << 7)
+ #define BP_ANADIG_PLL_ENET_DIV_SELECT                 0
+ #define BM_ANADIG_PLL_ENET_DIV_SELECT                 (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
 -#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)                              \
 -      (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT)
++#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)        \
++      (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
++              BM_ANADIG_PLL_ENET_DIV_SELECT)
+ #define BM_ANADIG_PFD_480_PFD3_CLKGATE                        (1 << 31)
+ #define BM_ANADIG_PFD_480_PFD3_STABLE                 (1 << 30)
+ #define BP_ANADIG_PFD_480_PFD3_FRAC                   24
+ #define BM_ANADIG_PFD_480_PFD3_FRAC                   (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
+ #define BF_ANADIG_PFD_480_PFD3_FRAC(v)                \
 -      (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC)
++      (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
++              BM_ANADIG_PFD_480_PFD3_FRAC)
+ #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY             26
+ #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY             (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
 -#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)                  \
 -      (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
++#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)        \
++      (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
++              BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+ #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL              (1 << 25)
+ #define BP_ANADIG_ANA_MISC0_ANAMUX                    21
+ #define BM_ANADIG_ANA_MISC0_ANAMUX                    (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
 -#define BF_ANADIG_ANA_MISC0_ANAMUX(v)         \
 -      (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & BM_ANADIG_ANA_MISC0_ANAMUX)
++#define BF_ANADIG_ANA_MISC0_ANAMUX(v)        \
++      (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
++              BM_ANADIG_ANA_MISC0_ANAMUX)
+ #define BM_ANADIG_ANA_MISC0_ANAMUX_EN                 (1 << 20)
+ #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH           18
+ #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH           (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+ #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v)                \
 -      (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
++      (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
++              BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+ #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN             (1 << 17)
 -#define BM_ANADIG_ANA_MISC0_OSC_XTALOK                (1 << 16)
 -#define BP_ANADIG_ANA_MISC0_OSC_I             14
 -#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
 -#define BF_ANADIG_ANA_MISC0_OSC_I(v)          \
 -      (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & BM_ANADIG_ANA_MISC0_OSC_I)
++#define BM_ANADIG_ANA_MISC0_OSC_XTALOK                        (1 << 16)
++#define BP_ANADIG_ANA_MISC0_OSC_I                     14
++#define BM_ANADIG_ANA_MISC0_OSC_I                     (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
++#define BF_ANADIG_ANA_MISC0_OSC_I(v)        \
++      (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
++              BM_ANADIG_ANA_MISC0_OSC_I)
+ #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN            (1 << 13)
 -#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG                  (1 << 12)
++#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG          (1 << 12)
+ #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST           8
 -#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
++#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST           (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+ #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v)                \
 -      (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
 -#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP                      (1 << 7)
++      (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
++              BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
++#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP              (1 << 7)
+ #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ             4
+ #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ             (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
 -#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v)          \
 -      (((v) << BM_ANADIG_ANA_MISC0_REFTOP_VBGUP) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
 -#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF                 (1 << 3)
 -#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER         &nbs