--- /dev/null
- depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
- default y
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+mainmenu "U-Boot $UBOOTVERSION Configuration"
+
+config UBOOTVERSION
+ string
+ option env="UBOOTVERSION"
+
+config KCONFIG_OBJDIR
+ string
+ option env="KCONFIG_OBJDIR"
+
+menu "General setup"
+
+config LOCALVERSION
+ string "Local version - append to U-Boot release"
+ depends on !SPL_BUILD
+ help
+ Append an extra string to the end of your U-Boot version.
+ This will show up on your boot log, for example.
+ The string you set here will be appended after the contents of
+ any files with a filename matching localversion* in your
+ object and source tree, in that order. Your total string can
+ be a maximum of 64 characters.
+
+config LOCALVERSION_AUTO
+ bool "Automatically append version information to the version string"
+ depends on !SPL_BUILD
+ default y
+ help
+ This will try to automatically determine if the current tree is a
+ release tree by looking for git tags that belong to the current
+ top of tree revision.
+
+ A string of the format -gxxxxxxxx will be added to the localversion
+ if a git-based tree is found. The string generated by this will be
+ appended after any matching localversion* files, and after the value
+ set in CONFIG_LOCALVERSION.
+
+ (The actual string used here is the first eight characters produced
+ by running the command:
+
+ $ git rev-parse --verify HEAD
+
+ which is done within the script "scripts/setlocalversion".)
+
+config CC_OPTIMIZE_FOR_SIZE
+ bool "Optimize for size"
+ depends on !SPL_BUILD
+ default y
+ help
+ Enabling this option will pass "-Os" instead of "-O2" to gcc
+ resulting in a smaller U-Boot image.
+
+ This option is enabled by default for U-Boot.
+
+menuconfig EXPERT
+ bool "Configure standard U-Boot features (expert users)"
+ help
+ This option allows certain base U-Boot options and settings
+ to be disabled or tweaked. This is for specialized
+ environments which can tolerate a "non-standard" U-Boot.
+ Only use this if you really know what you are doing.
+
+endmenu # General setup
+
+menu "Boot images"
+
+config SPL_BUILD
+ bool
++ default y if $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
+
+config TPL_BUILD
+ bool
+ depends on $KCONFIG_OBJDIR="tpl"
+ default y
+
+config SUPPORT_SPL
+ bool
+
+config SUPPORT_TPL
+ bool
+
+config SPL
+ bool
+ depends on SUPPORT_SPL
+ prompt "Enable SPL" if !SPL_BUILD
+ default y if SPL_BUILD
+ help
+ If you want to build SPL as well as the normal image, say Y.
+
+config TPL
+ bool
+ depends on SPL && SUPPORT_TPL
+ prompt "Enable TPL" if !SPL_BUILD
+ default y if TPL_BUILD
+ default n
+ help
+ If you want to build TPL as well as the normal image and SPL, say Y.
+
+config FIT
+ bool "Support Flattened Image Tree"
+ depends on !SPL_BUILD
+ help
+ This option allows to boot the new uImage structrure,
+ Flattened Image Tree. FIT is formally a FDT, which can include
+ images of various types (kernel, FDT blob, ramdisk, etc.)
+ in a single blob. To boot this new uImage structure,
+ pass the the address of the blob to the "bootm" command.
+
+config FIT_VERBOSE
+ bool "Display verbose messages on FIT boot"
+ depends on FIT
+
+config FIT_SIGNATURE
+ bool "Enabel signature verification of FIT uImages"
+ depends on FIT
+ help
+ This option enables signature verification of FIT uImages,
+ using a hash signed and verified using RSA.
+ See doc/uImage.FIT/signature.txt for more details.
+
+config SYS_EXTRA_OPTIONS
+ string "Extra Options (DEPRECATED)"
+ depends on !SPL_BUILD
+ help
+ The old configuration infrastructure (= mkconfig + boards.cfg)
+ provided the extra options field. If you have something like
+ "HAS_BAR,BAZ=64", the optional options
+ #define CONFIG_HAS
+ #define CONFIG_BAZ 64
+ will be defined in include/config.h.
+ This option was prepared for the smooth migration from the old
+ configuration to Kconfig. Since this option will be removed sometime,
+ new boards should not use this option.
+
+config SYS_TEXT_BASE
+ depends on SPARC
+ hex "Text Base"
+ help
+ TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
+
+endmenu # Boot images
+
+source "arch/Kconfig"
+
+source "common/Kconfig"
+
+source "dts/Kconfig"
+
+source "net/Kconfig"
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+source "lib/Kconfig"
4th and following
BOOTP requests: delay 0 ... 8 sec
+ CONFIG_BOOTP_ID_CACHE_SIZE
+
+ BOOTP packets are uniquely identified using a 32-bit ID. The
+ server will copy the ID from client requests to responses and
+ U-Boot will use this to determine if it is the destination of
+ an incoming response. Some servers will check that addresses
+ aren't in use before handing them out (usually using an ARP
+ ping) and therefore take up to a few hundred milliseconds to
+ respond. Network congestion may also influence the time it
+ takes for a response to make it back to the client. If that
+ time is too long, U-Boot will retransmit requests. In order
+ to allow earlier responses to still be accepted after these
+ retransmissions, U-Boot's BOOTP client keeps a small cache of
+ IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
+ cache. The default is to keep IDs for up to four outstanding
+ requests. Increasing this will allow U-Boot to accept offers
+ from a BOOTP client in networks with unusually high latency.
+
+ - BOOTP Random transaction ID:
+ CONFIG_BOOTP_RANDOM_ID
+
+ The standard algorithm to generate a DHCP/BOOTP transaction ID
+ by using the MAC address and the current time stamp may not
+ quite unlikely produce duplicate transaction IDs from different
+ clients in the same network. This option creates a transaction
+ ID using the rand() function. Provided that the RNG has been
+ seeded well, this should guarantee unique transaction IDs
+ always.
+
- DHCP Advanced Options:
You can fine tune the DHCP functionality by defining
CONFIG_BOOTP_* symbols:
--- /dev/null
+menu "ARM architecture"
+ depends on ARM
+
+config SYS_ARCH
+ default "arm"
+
+config ARM64
+ bool
+
+config HAS_VBAR
+ bool
+
+config CPU_ARM720T
+ bool
+
+config CPU_ARM920T
+ bool
+
+config CPU_ARM926EJS
+ bool
+
+config CPU_ARM946ES
+ bool
+
+config CPU_ARM1136
+ bool
+
+config CPU_ARM1176
+ bool
+ select HAS_VBAR
+
+config CPU_V7
+ bool
+ select HAS_VBAR
+
+config CPU_PXA
+ bool
+
+config CPU_SA1100
+ bool
+
+config SYS_CPU
+ default "arm720t" if CPU_ARM720T
+ default "arm920t" if CPU_ARM920T
+ default "arm926ejs" if CPU_ARM926EJS
+ default "arm946es" if CPU_ARM946ES
+ default "arm1136" if CPU_ARM1136
+ default "arm1176" if CPU_ARM1176
+ default "armv7" if CPU_V7
+ default "pxa" if CPU_PXA
+ default "sa1100" if CPU_SA1100
+ default "armv8" if ARM64
+
+choice
+ prompt "Target select"
+
+config TARGET_INTEGRATORAP_CM720T
+ bool "Support integratorap_cm720t"
+ select CPU_ARM720T
+
+config TARGET_INTEGRATORAP_CM920T
+ bool "Support integratorap_cm920t"
+ select CPU_ARM920T
+
+config TARGET_INTEGRATORCP_CM920T
+ bool "Support integratorcp_cm920t"
+ select CPU_ARM920T
+
+config TARGET_A320EVB
+ bool "Support a320evb"
+ select CPU_ARM920T
+
+config TARGET_AT91RM9200EK
+ bool "Support at91rm9200ek"
+ select CPU_ARM920T
+
+config TARGET_EB_CPUX9K2
+ bool "Support eb_cpux9k2"
+ select CPU_ARM920T
+
+config TARGET_CPUAT91
+ bool "Support cpuat91"
+ select CPU_ARM920T
+
+config TARGET_EDB93XX
+ bool "Support edb93xx"
+ select CPU_ARM920T
+
+config TARGET_SCB9328
+ bool "Support scb9328"
+ select CPU_ARM920T
+
+config TARGET_CM4008
+ bool "Support cm4008"
+ select CPU_ARM920T
+
+config TARGET_CM41XX
+ bool "Support cm41xx"
+ select CPU_ARM920T
+
+config TARGET_VCMA9
+ bool "Support VCMA9"
+ select CPU_ARM920T
+
+config TARGET_SMDK2410
+ bool "Support smdk2410"
+ select CPU_ARM920T
+
+config TARGET_INTEGRATORAP_CM926EJS
+ bool "Support integratorap_cm926ejs"
+ select CPU_ARM926EJS
+
+config TARGET_INTEGRATORCP_CM926EJS
+ bool "Support integratorcp_cm926ejs"
+ select CPU_ARM926EJS
+
+config TARGET_ASPENITE
+ bool "Support aspenite"
+ select CPU_ARM926EJS
+
+config TARGET_GPLUGD
+ bool "Support gplugd"
+ select CPU_ARM926EJS
+
+config TARGET_AFEB9260
+ bool "Support afeb9260"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9260EK
+ bool "Support at91sam9260ek"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9261EK
+ bool "Support at91sam9261ek"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9263EK
+ bool "Support at91sam9263ek"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9M10G45EK
+ bool "Support at91sam9m10g45ek"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9N12EK
+ bool "Support at91sam9n12ek"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9RLEK
+ bool "Support at91sam9rlek"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9X5EK
+ bool "Support at91sam9x5ek"
+ select CPU_ARM926EJS
+
+config TARGET_SNAPPER9260
+ bool "Support snapper9260"
+ select CPU_ARM926EJS
+
+config TARGET_VL_MA2SC
+ bool "Support vl_ma2sc"
+ select CPU_ARM926EJS
+
+config TARGET_SBC35_A9G20
+ bool "Support sbc35_a9g20"
+ select CPU_ARM926EJS
+
+config TARGET_TNY_A9260
+ bool "Support tny_a9260"
+ select CPU_ARM926EJS
+
+config TARGET_USB_A9263
+ bool "Support usb_a9263"
+ select CPU_ARM926EJS
+
+config TARGET_ETHERNUT5
+ bool "Support ethernut5"
+ select CPU_ARM926EJS
+
+config TARGET_MEESC
+ bool "Support meesc"
+ select CPU_ARM926EJS
+
+config TARGET_OTC570
+ bool "Support otc570"
+ select CPU_ARM926EJS
+
+config TARGET_CPU9260
+ bool "Support cpu9260"
+ select CPU_ARM926EJS
+
+config TARGET_PM9261
+ bool "Support pm9261"
+ select CPU_ARM926EJS
+
+config TARGET_PM9263
+ bool "Support pm9263"
+ select CPU_ARM926EJS
+
+config TARGET_PM9G45
+ bool "Support pm9g45"
+ select CPU_ARM926EJS
+
+config TARGET_CORVUS
+ select SUPPORT_SPL
+ bool "Support corvus"
+ select CPU_ARM926EJS
+
+config TARGET_TAURUS
+ select SUPPORT_SPL
+ bool "Support taurus"
+ select CPU_ARM926EJS
+
+config TARGET_STAMP9G20
+ bool "Support stamp9g20"
+ select CPU_ARM926EJS
+
+config ARCH_DAVINCI
+ bool "TI DaVinci"
+ select CPU_ARM926EJS
+ help
+ Support for TI's DaVinci platform.
+
+config KIRKWOOD
+ bool "Marvell Kirkwood"
+ select CPU_ARM926EJS
+
+config TARGET_DB_MV784MP_GP
+ bool "Support db-mv784mp-gp"
+ select CPU_V7
+
+config TARGET_MAXBCM
+ bool "Support maxbcm"
+ select CPU_V7
+
+config TARGET_DEVKIT3250
+ bool "Support devkit3250"
+ select CPU_ARM926EJS
+
+config TARGET_JADECPU
+ bool "Support jadecpu"
+ select CPU_ARM926EJS
+
+config TARGET_MX25PDK
+ bool "Support mx25pdk"
+ select CPU_ARM926EJS
+
+config TARGET_TX25
+ bool "Support tx25"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
++config TARGET_TX28
++ bool "Support tx28"
++ select CPU_ARM926EJS
++ select SUPPORT_SPL
++
++config TARGET_TX48
++ bool "Support tx48"
++ select CPU_V7
++ select SUPPORT_SPL
++
++config TARGET_TX51
++ bool "Support tx51"
++ select CPU_V7
++
++config TARGET_TX53
++ bool "Support tx53"
++ select CPU_V7
++
++config TARGET_TX6
++ bool "Support tx6"
++ select CPU_V7
++
+config TARGET_ZMX25
+ bool "Support zmx25"
+ select CPU_ARM926EJS
+
+config TARGET_APF27
+ bool "Support apf27"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_IMX27LITE
+ bool "Support imx27lite"
+ select CPU_ARM926EJS
+
+config TARGET_MAGNESIUM
+ bool "Support magnesium"
+ select CPU_ARM926EJS
+
+config TARGET_APX4DEVKIT
+ bool "Support apx4devkit"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_XFI3
+ bool "Support xfi3"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_M28EVK
+ bool "Support m28evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_MX23EVK
+ bool "Support mx23evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_MX28EVK
+ bool "Support mx28evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_MX23_OLINUXINO
+ bool "Support mx23_olinuxino"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_BG0900
+ bool "Support bg0900"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_SANSA_FUZE_PLUS
+ bool "Support sansa_fuze_plus"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_SC_SPS_1
+ bool "Support sc_sps_1"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config ARCH_NOMADIK
+ bool "ST-Ericsson Nomadik"
+ select CPU_ARM926EJS
+
+config ORION5X
+ bool "Marvell Orion"
+ select CPU_ARM926EJS
+
+config TARGET_DKB
+ bool "Support dkb"
+ select CPU_ARM926EJS
+
+config TARGET_SPEAR300
+ bool "Support spear300"
+ select CPU_ARM926EJS
+
+config TARGET_SPEAR310
+ bool "Support spear310"
+ select CPU_ARM926EJS
+
+config TARGET_SPEAR320
+ bool "Support spear320"
+ select CPU_ARM926EJS
+
+config TARGET_SPEAR600
+ bool "Support spear600"
+ select CPU_ARM926EJS
+
+config TARGET_STV0991
+ bool "Support stv0991"
+ select CPU_V7
+
+config TARGET_X600
+ bool "Support x600"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config ARCH_VERSATILE
+ bool "ARM Ltd. Versatile family"
+ select CPU_ARM926EJS
+
+config TARGET_INTEGRATORCP_CM1136
+ bool "Support integratorcp_cm1136"
+ select CPU_ARM1136
+
+config TARGET_IMX31_PHYCORE
+ bool "Support imx31_phycore"
+ select CPU_ARM1136
+
+config TARGET_QONG
+ bool "Support qong"
+ select CPU_ARM1136
+
+config TARGET_MX31ADS
+ bool "Support mx31ads"
+ select CPU_ARM1136
+
+config TARGET_MX31PDK
+ bool "Support mx31pdk"
+ select CPU_ARM1136
+ select SUPPORT_SPL
+
+config TARGET_TT01
+ bool "Support tt01"
+ select CPU_ARM1136
+
+config TARGET_IMX31_LITEKIT
+ bool "Support imx31_litekit"
+ select CPU_ARM1136
+
+config TARGET_WOODBURN
+ bool "Support woodburn"
+ select CPU_ARM1136
+
+config TARGET_WOODBURN_SD
+ bool "Support woodburn_sd"
+ select CPU_ARM1136
+ select SUPPORT_SPL
+
+config TARGET_FLEA3
+ bool "Support flea3"
+ select CPU_ARM1136
+
+config TARGET_MX35PDK
+ bool "Support mx35pdk"
+ select CPU_ARM1136
+
+config TARGET_RPI
+ bool "Support rpi"
+ select CPU_ARM1176
+
+config TARGET_TNETV107X_EVM
+ bool "Support tnetv107x_evm"
+ select CPU_ARM1176
+
+config TARGET_INTEGRATORAP_CM946ES
+ bool "Support integratorap_cm946es"
+ select CPU_ARM946ES
+
+config TARGET_INTEGRATORCP_CM946ES
+ bool "Support integratorcp_cm946es"
+ select CPU_ARM946ES
+
+config TARGET_VEXPRESS_CA15_TC2
+ bool "Support vexpress_ca15_tc2"
+ select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+
+config TARGET_VEXPRESS_CA5X2
+ bool "Support vexpress_ca5x2"
+ select CPU_V7
+
+config TARGET_VEXPRESS_CA9X4
+ bool "Support vexpress_ca9x4"
+ select CPU_V7
+
+config TARGET_KWB
+ bool "Support kwb"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_TSERIES
+ bool "Support tseries"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_CM_T335
+ bool "Support cm_t335"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PEPPER
+ bool "Support pepper"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_AM335X_IGEP0033
+ bool "Support am335x_igep0033"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PCM051
+ bool "Support pcm051"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_DRACO
+ bool "Support draco"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_DXR2
+ bool "Support dxr2"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PXM2
+ bool "Support pxm2"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_RUT
+ bool "Support rut"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PENGWYN
+ bool "Support pengwyn"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_AM335X_EVM
+ bool "Support am335x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_AM43XX_EVM
+ bool "Support am43xx_evm"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_TI814X_EVM
+ bool "Support ti814x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_TI816X_EVM
+ bool "Support ti816x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_SAMA5D3_XPLAINED
+ bool "Support sama5d3_xplained"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_SAMA5D3XEK
+ bool "Support sama5d3xek"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_SAMA5D4_XPLAINED
+ bool "Support sama5d4_xplained"
+ select CPU_V7
+
+config TARGET_SAMA5D4EK
+ bool "Support sama5d4ek"
+ select CPU_V7
+
+config TARGET_BCM28155_AP
+ bool "Support bcm28155_ap"
+ select CPU_V7
+
+config TARGET_BCMCYGNUS
+ bool "Support bcmcygnus"
+ select CPU_V7
+
+config TARGET_BCMNSP
+ bool "Support bcmnsp"
+ select CPU_V7
+
+config ARCH_EXYNOS
+ bool "Samsung EXYNOS"
+ select CPU_V7
+
+config ARCH_S5PC1XX
+ bool "Samsung S5PC1XX"
+ select CPU_V7
+
+config ARCH_HIGHBANK
+ bool "Calxeda Highbank"
+ select CPU_V7
+
+config ARCH_KEYSTONE
+ bool "TI Keystone"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_M53EVK
+ bool "Support m53evk"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_IMA3_MX53
+ bool "Support ima3-mx53"
+ select CPU_V7
+
+config TARGET_MX51EVK
+ bool "Support mx51evk"
+ select CPU_V7
+
+config TARGET_MX53ARD
+ bool "Support mx53ard"
+ select CPU_V7
+
+config TARGET_MX53EVK
+ bool "Support mx53evk"
+ select CPU_V7
+
+config TARGET_MX53LOCO
+ bool "Support mx53loco"
+ select CPU_V7
+
+config TARGET_MX53SMD
+ bool "Support mx53smd"
+ select CPU_V7
+
+config TARGET_MX51_EFIKAMX
+ bool "Support mx51_efikamx"
+ select CPU_V7
+
+config TARGET_VISION2
+ bool "Support vision2"
+ select CPU_V7
+
+config TARGET_UDOO
+ bool "Support udoo"
+ select CPU_V7
+
+config TARGET_WANDBOARD
+ bool "Support wandboard"
+ select CPU_V7
+
+config TARGET_TITANIUM
+ bool "Support titanium"
+ select CPU_V7
+
+config TARGET_NITROGEN6X
+ bool "Support nitrogen6x"
+ select CPU_V7
+
+config TARGET_CGTQMX6EVAL
+ bool "Support cgtqmx6eval"
+ select CPU_V7
+
+config TARGET_EMBESTMX6BOARDS
+ bool "Support embestmx6boards"
+ select CPU_V7
+
+config TARGET_ARISTAINETOS
+ bool "Support aristainetos"
+ select CPU_V7
+
+config TARGET_MX6QARM2
+ bool "Support mx6qarm2"
+ select CPU_V7
+
+config TARGET_MX6QSABREAUTO
+ bool "Support mx6qsabreauto"
+ select CPU_V7
+
+config TARGET_MX6SABRESD
+ bool "Support mx6sabresd"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_MX6SLEVK
+ bool "Support mx6slevk"
+ select CPU_V7
+
+config TARGET_MX6SXSABRESD
+ bool "Support mx6sxsabresd"
+ select CPU_V7
+
+config TARGET_GW_VENTANA
+ bool "Support gw_ventana"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_HUMMINGBOARD
+ bool "Support hummingboard"
+ select CPU_V7
+
+config TARGET_KOSAGI_NOVENA
+ bool "Support Kosagi Novena"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_TBS2910
+ bool "Support tbs2910"
+ select CPU_V7
+
+config TARGET_TQMA6
+ bool "TQ Systems TQMa6 board"
+ select CPU_V7
+
+config TARGET_OT1200
+ bool "Bachmann OT1200"
+ select CPU_V7
+
+config OMAP34XX
+ bool "OMAP34XX SoC"
+ select CPU_V7
+
+config OMAP44XX
+ bool "OMAP44XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config OMAP54XX
+ bool "OMAP54XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config RMOBILE
+ bool "Renesas ARM SoCs"
+ select CPU_V7
+
+config TARGET_CM_FX6
+ bool "Support cm_fx6"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_SOCFPGA_CYCLONE5
+ bool "Support socfpga_cyclone5"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config ARCH_SUNXI
+ bool "Support sunxi (Allwinner) SoCs"
+
+config TARGET_SNOWBALL
+ bool "Support snowball"
+ select CPU_V7
+
+config TARGET_U8500_HREF
+ bool "Support u8500_href"
+ select CPU_V7
+
+config TARGET_VF610TWR
+ bool "Support vf610twr"
+ select CPU_V7
+
+config ZYNQ
+ bool "Xilinx Zynq Platform"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TEGRA
+ bool "NVIDIA Tegra"
+ select SUPPORT_SPL
+ select SPL
+ select OF_CONTROL if !SPL_BUILD
+ select CPU_ARM720T if SPL_BUILD
+ select CPU_V7 if !SPL_BUILD
+
+config TARGET_VEXPRESS_AEMV8A
+ bool "Support vexpress_aemv8a"
+ select ARM64
+
+config TARGET_LS2085A_EMU
+ bool "Support ls2085a_emu"
+ select ARM64
+
+config TARGET_LS2085A_SIMU
+ bool "Support ls2085a_simu"
+ select ARM64
+
+config TARGET_LS1021AQDS
+ bool "Support ls1021aqds"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_LS1021ATWR
+ bool "Support ls1021atwr"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_BALLOON3
+ bool "Support balloon3"
+ select CPU_PXA
+
+config TARGET_H2200
+ bool "Support h2200"
+ select CPU_PXA
+
+config TARGET_PALMLD
+ bool "Support palmld"
+ select CPU_PXA
+
+config TARGET_PALMTC
+ bool "Support palmtc"
+ select CPU_PXA
+
+config TARGET_PALMTREO680
+ bool "Support palmtreo680"
+ select CPU_PXA
+ select SUPPORT_SPL
+
+config TARGET_PXA255_IDP
+ bool "Support pxa255_idp"
+ select CPU_PXA
+
+config TARGET_TRIZEPSIV
+ bool "Support trizepsiv"
+ select CPU_PXA
+
+config TARGET_VPAC270
+ bool "Support vpac270"
+ select CPU_PXA
+ select SUPPORT_SPL
+
+config TARGET_XAENIAX
+ bool "Support xaeniax"
+ select CPU_PXA
+
+config TARGET_ZIPITZ2
+ bool "Support zipitz2"
+ select CPU_PXA
+
+config TARGET_LP8X4X
+ bool "Support lp8x4x"
+ select CPU_PXA
+
+config TARGET_COLIBRI_PXA270
+ bool "Support colibri_pxa270"
+ select CPU_PXA
+
+config TARGET_JORNADA
+ bool "Support jornada"
+ select CPU_SA1100
+
+config ARCH_UNIPHIER
+ bool "Panasonic UniPhier platform"
+ select CPU_V7
+ select SUPPORT_SPL
+ select SPL
+ select OF_CONTROL if !SPL_BUILD
+
+endchoice
+
+source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
+
+source "arch/arm/cpu/armv7/exynos/Kconfig"
+
+source "arch/arm/cpu/armv7/highbank/Kconfig"
+
+source "arch/arm/cpu/armv7/keystone/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
+
+source "arch/arm/cpu/armv7/omap3/Kconfig"
+
+source "arch/arm/cpu/armv7/omap4/Kconfig"
+
+source "arch/arm/cpu/armv7/omap5/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
+
+source "arch/arm/cpu/armv7/rmobile/Kconfig"
+
+source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
+
+source "arch/arm/cpu/armv7/tegra-common/Kconfig"
+
+source "arch/arm/cpu/armv7/uniphier/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
+
+source "arch/arm/cpu/armv7/zynq/Kconfig"
+
+source "arch/arm/cpu/armv7/Kconfig"
+
+source "board/aristainetos/Kconfig"
+source "board/BuR/kwb/Kconfig"
+source "board/BuR/tseries/Kconfig"
+source "board/BuS/eb_cpux9k2/Kconfig"
+source "board/BuS/vl_ma2sc/Kconfig"
+source "board/CarMediaLab/flea3/Kconfig"
+source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/db-mv784mp-gp/Kconfig"
+source "board/Marvell/dkb/Kconfig"
+source "board/Marvell/gplugd/Kconfig"
+source "board/afeb9260/Kconfig"
+source "board/altera/socfpga/Kconfig"
+source "board/armadeus/apf27/Kconfig"
+source "board/armltd/integrator/Kconfig"
+source "board/armltd/vexpress/Kconfig"
+source "board/armltd/vexpress64/Kconfig"
+source "board/atmel/at91rm9200ek/Kconfig"
+source "board/atmel/at91sam9260ek/Kconfig"
+source "board/atmel/at91sam9261ek/Kconfig"
+source "board/atmel/at91sam9263ek/Kconfig"
+source "board/atmel/at91sam9m10g45ek/Kconfig"
+source "board/atmel/at91sam9n12ek/Kconfig"
+source "board/atmel/at91sam9rlek/Kconfig"
+source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d3_xplained/Kconfig"
+source "board/atmel/sama5d3xek/Kconfig"
+source "board/atmel/sama5d4_xplained/Kconfig"
+source "board/atmel/sama5d4ek/Kconfig"
+source "board/bachmann/ot1200/Kconfig"
+source "board/balloon3/Kconfig"
+source "board/barco/titanium/Kconfig"
+source "board/bluegiga/apx4devkit/Kconfig"
+source "board/bluewater/snapper9260/Kconfig"
+source "board/boundary/nitrogen6x/Kconfig"
+source "board/broadcom/bcm28155_ap/Kconfig"
+source "board/broadcom/bcmcygnus/Kconfig"
+source "board/broadcom/bcmnsp/Kconfig"
+source "board/calao/sbc35_a9g20/Kconfig"
+source "board/calao/tny_a9260/Kconfig"
+source "board/calao/usb_a9263/Kconfig"
+source "board/cirrus/edb93xx/Kconfig"
+source "board/cm4008/Kconfig"
+source "board/cm41xx/Kconfig"
+source "board/compulab/cm_t335/Kconfig"
+source "board/compulab/cm_fx6/Kconfig"
+source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/creative/xfi3/Kconfig"
+source "board/davedenx/qong/Kconfig"
+source "board/denx/m28evk/Kconfig"
+source "board/denx/m53evk/Kconfig"
+source "board/egnite/ethernut5/Kconfig"
+source "board/embest/mx6boards/Kconfig"
+source "board/esd/meesc/Kconfig"
+source "board/esd/otc570/Kconfig"
+source "board/esg/ima3-mx53/Kconfig"
+source "board/eukrea/cpu9260/Kconfig"
+source "board/eukrea/cpuat91/Kconfig"
+source "board/faraday/a320evb/Kconfig"
+source "board/freescale/ls2085a/Kconfig"
+source "board/freescale/ls1021aqds/Kconfig"
+source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/mx23evk/Kconfig"
+source "board/freescale/mx25pdk/Kconfig"
+source "board/freescale/mx28evk/Kconfig"
+source "board/freescale/mx31ads/Kconfig"
+source "board/freescale/mx31pdk/Kconfig"
+source "board/freescale/mx35pdk/Kconfig"
+source "board/freescale/mx51evk/Kconfig"
+source "board/freescale/mx53ard/Kconfig"
+source "board/freescale/mx53evk/Kconfig"
+source "board/freescale/mx53loco/Kconfig"
+source "board/freescale/mx53smd/Kconfig"
+source "board/freescale/mx6qarm2/Kconfig"
+source "board/freescale/mx6qsabreauto/Kconfig"
+source "board/freescale/mx6sabresd/Kconfig"
+source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/vf610twr/Kconfig"
+source "board/gateworks/gw_ventana/Kconfig"
+source "board/genesi/mx51_efikamx/Kconfig"
+source "board/gumstix/pepper/Kconfig"
+source "board/h2200/Kconfig"
+source "board/hale/tt01/Kconfig"
+source "board/icpdas/lp8x4x/Kconfig"
+source "board/imx31_phycore/Kconfig"
+source "board/isee/igep0033/Kconfig"
+source "board/jornada/Kconfig"
+source "board/karo/tx25/Kconfig"
++source "board/karo/tx28/Kconfig"
++source "board/karo/tx48/Kconfig"
++source "board/karo/tx51/Kconfig"
++source "board/karo/tx53/Kconfig"
++source "board/karo/tx6/Kconfig"
+source "board/kosagi/novena/Kconfig"
+source "board/logicpd/imx27lite/Kconfig"
+source "board/logicpd/imx31_litekit/Kconfig"
+source "board/maxbcm/Kconfig"
+source "board/mpl/vcma9/Kconfig"
+source "board/olimex/mx23_olinuxino/Kconfig"
+source "board/palmld/Kconfig"
+source "board/palmtc/Kconfig"
+source "board/palmtreo680/Kconfig"
+source "board/phytec/pcm051/Kconfig"
+source "board/ppcag/bg0900/Kconfig"
+source "board/pxa255_idp/Kconfig"
+source "board/raspberrypi/rpi/Kconfig"
+source "board/ronetix/pm9261/Kconfig"
+source "board/ronetix/pm9263/Kconfig"
+source "board/ronetix/pm9g45/Kconfig"
+source "board/samsung/smdk2410/Kconfig"
+source "board/sandisk/sansa_fuze_plus/Kconfig"
+source "board/scb9328/Kconfig"
+source "board/schulercontrol/sc_sps_1/Kconfig"
+source "board/siemens/corvus/Kconfig"
+source "board/siemens/draco/Kconfig"
+source "board/siemens/pxm2/Kconfig"
+source "board/siemens/rut/Kconfig"
+source "board/siemens/taurus/Kconfig"
+source "board/silica/pengwyn/Kconfig"
+source "board/solidrun/hummingboard/Kconfig"
+source "board/spear/spear300/Kconfig"
+source "board/spear/spear310/Kconfig"
+source "board/spear/spear320/Kconfig"
+source "board/spear/spear600/Kconfig"
+source "board/spear/x600/Kconfig"
+source "board/st-ericsson/snowball/Kconfig"
+source "board/st-ericsson/u8500/Kconfig"
+source "board/st/stv0991/Kconfig"
+source "board/sunxi/Kconfig"
+source "board/syteco/jadecpu/Kconfig"
+source "board/syteco/zmx25/Kconfig"
+source "board/taskit/stamp9g20/Kconfig"
+source "board/tbs/tbs2910/Kconfig"
+source "board/ti/am335x/Kconfig"
+source "board/ti/am43xx/Kconfig"
+source "board/ti/ti814x/Kconfig"
+source "board/ti/ti816x/Kconfig"
+source "board/ti/tnetv107xevm/Kconfig"
+source "board/timll/devkit3250/Kconfig"
+source "board/toradex/colibri_pxa270/Kconfig"
+source "board/tqc/tqma6/Kconfig"
+source "board/trizepsiv/Kconfig"
+source "board/ttcontrol/vision2/Kconfig"
+source "board/udoo/Kconfig"
+source "board/vpac270/Kconfig"
+source "board/wandboard/Kconfig"
+source "board/woodburn/Kconfig"
+source "board/xaeniax/Kconfig"
+source "board/zipitz2/Kconfig"
+
+source "arch/arm/Kconfig.debug"
+
+endmenu
# Only test once
ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb
+
+checkthumb:
+ @if test "$(call cc-version)" -lt "0404"; then \
+ echo -n '*** Your GCC does not produce working '; \
+ echo 'binaries in THUMB mode.'; \
+ echo '*** Your board is configured for THUMB mode.'; \
+ false; \
+ fi
+endif
endif
- # Try if EABI is supported, else fall back to old API,
+ # Try if EABI is supported, else fall back to old ABI,
# i. e. for example:
# - with ELDK 4.2 (EABI supported), use:
# -mabi=aapcs-linux
void mx28_fixup_vt(uint32_t start_addr)
{
/* ldr pc, [pc, #0x18] */
- const uint32_t ldr_pc = 0xe59ff018;
/* Jumptable location is 0x0 */
- uint32_t *vt = (uint32_t *)0x0;
- int i;
+ uint32_t *vt = (uint32_t *)0x20;
+ uint32_t cr = get_cr();
++<<<<<<< HEAD
+ for (i = 0; i < 8; i++) {
+ /* cppcheck-suppress nullPointer */
+ vt[i] = ldr_pc;
+ /* cppcheck-suppress nullPointer */
+ vt[i + 8] = start_addr + (4 * i);
+ }
++=======
+ memcpy(vt, (void *)start_addr + 0x20, 32);
+ set_cr(cr & ~CR_V);
++>>>>>>> karo-tx-uboot
}
#ifdef CONFIG_ARCH_MISC_INIT
#include "mxs_init.h"
+ #ifdef CONFIG_SYS_SPL_VDDD_VAL
+ #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
+ #else
+ #define VDDD_VAL 1350
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDIO_VAL
+ #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
+ #else
+ #define VDDIO_VAL 3300
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDA_VAL
+ #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
+ #else
+ #define VDDA_VAL 1800
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
+ #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
+ #else
+ #define VDDMEM_VAL 1700
+ #endif
+
+ #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
+ #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
+ #else
+ #define VDDD_BO_VAL 150
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
+ #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
+ #else
+ #define VDDIO_BO_VAL 150
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
+ #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
+ #else
+ #define VDDA_BO_VAL 175
+ #endif
+ #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
+ #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
+ #else
+ #define VDDMEM_BO_VAL 25
+ #endif
+
+ #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
+ #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
+ #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
+ #endif
+ #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
+ #else
+ /* Brownout default at 3V */
+ #define BATT_BO_VAL ((3000 - 2400) / 40)
+ #endif
+
+ #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
+ static const int fixed_batt_supply = 1;
+ #else
+ static const int fixed_batt_supply;
+ #endif
+
+ static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+
+/**
+ * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
+ *
+ * This function switches the CPU core clock from PLL to 24MHz XTAL
+ * oscilator. This is necessary if the PLL is being reconfigured to
+ * prevent crash of the CPU core.
+ */
static void mxs_power_clock2xtal(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-
- static void mxs_power_set_auto_restart(void)
+ static int mxs_power_wait_rtc_stat(u32 mask)
+ {
+ int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
+ u32 val;
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
+
+ while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
+ early_delay(1);
+ if (timeout-- < 0)
+ break;
+ }
+ return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
+ }
+
+/**
+ * mxs_power_set_auto_restart() - Set the auto-restart bit
+ *
+ * This function ungates the RTC block and sets the AUTO_RESTART
+ * bit to work around a design bug on MX28EVK Rev. A .
+ */
+ static int mxs_power_set_auto_restart(int on)
{
- struct mxs_rtc_regs *rtc_regs =
- (struct mxs_rtc_regs *)MXS_RTC_BASE;
-
- writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
- ;
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
- writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
- ;
- /*
- * Due to the hardware design bug of mx28 EVK-A
- * we need to set the AUTO_RESTART bit.
- */
+ if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
+ return 1;
- return;
+ /* Do nothing if flag already set */
+ if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
- ;
++ return 0;
+
+ if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
+ RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
+ return 0;
- setbits_le32(&rtc_regs->hw_rtc_persistent0,
- RTC_PERSISTENT0_AUTO_RESTART);
- writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
- writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
- ;
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
- ;
+ if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+ return 1;
+
+ clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
+ !on * RTC_PERSISTENT0_AUTO_RESTART,
+ !!on * RTC_PERSISTENT0_AUTO_RESTART);
+ if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+ return 1;
+
+ return 0;
}
+/**
+ * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
+ *
+ * This function configures the VDDIO, VDDA and VDDD linear regulators output
+ * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
+ * converter. This is the recommended setting for the case where we use both
+ * linear regulators and DC-DC converter to power the VDDIO rail.
+ */
static void mxs_power_set_linreg(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Set linear regulator 25mV below switching converter */
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
+/**
+ * mxs_get_batt_volt() - Measure battery input voltage
+ *
+ * This function retrieves the battery input voltage and returns it.
+ */
static int mxs_get_batt_volt(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
return (mxs_get_batt_volt() >= 3600);
}
+/**
+ * mxs_is_batt_good() - Test if battery is operational at all
+ *
+ * This function starts recharging the battery and tests if the input current
+ * provided by the 5V input recharging the battery is also sufficient to power
+ * the DC-DC converter.
+ */
static int mxs_is_batt_good(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = mxs_get_batt_volt();
if ((volt >= 2400) && (volt <= 4300))
return 0;
}
+/**
+ * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
+ *
+ * This function enables the 5V detection comparator and sets the 5V valid
+ * threshold to 4.4V . We use 4.4V threshold here to make sure that even
+ * under high load, the voltage drop on the 5V input won't be so critical
+ * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
+ * converter and thus making the system crash.
+ */
static void mxs_power_setup_5v_detect(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Start 5V detection */
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
+/**
+ * mxs_src_power_init() - Preconfigure the power block
+ *
+ * This function configures reasonable values for the DC-DC control loop
+ * and battery monitor.
+ */
static void mxs_src_power_init(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
- /* 5V to battery handoff ... FIXME */
- setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ if (!fixed_batt_supply) {
+ /* 5V to battery handoff ... FIXME */
+ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ early_delay(30);
+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ }
}
+/**
+ * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
+ *
+ * This function configures the necessary parameters for the 4P2 linear
+ * regulator to supply the DC-DC converter from 5V input.
+ */
static void mxs_power_init_4p2_params(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
+/**
+ * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
+ * @xfer: Select if the input shall be enabled or disabled
+ *
+ * This function enables or disables the 4P2 input into the DC-DC converter.
+ */
static void mxs_enable_4p2_dcdc_input(int xfer)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
+/**
+ * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
+ *
+ * This function enables the 4P2 regulator and switches the DC-DC converter
+ * to use the 4P2 input.
+ */
static void mxs_power_init_4p2_regulator(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
+/**
+ * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
+ *
+ * This function configures the DC-DC converter to be supplied from the 4P2
+ * linear regulator.
+ */
static void mxs_power_init_dcdc_4p2_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
hang();
}
}
+/**
+ * mxs_power_enable_4p2() - Power up the 4P2 regulator
+ *
+ * This function drives the process of powering up the 4P2 linear regulator
+ * and switching the DC-DC converter input over to the 4P2 linear regulator.
+ */
static void mxs_power_enable_4p2(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
&power_regs->hw_power_charge_clr);
}
+/**
+ * mxs_boot_valid_5v() - Boot from 5V supply
+ *
+ * This function configures the power block to boot from valid 5V input.
+ * This is called only if the 5V is reliable and can properly supply the
+ * CPU. This function proceeds to configure the 4P2 converter to be supplied
+ * from the 5V input.
+ */
static void mxs_boot_valid_5v(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
mxs_power_enable_4p2();
}
+/**
+ * mxs_powerdown() - Shut down the system
+ *
+ * This function powers down the CPU completely.
+ */
static void mxs_powerdown(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
}
+/**
+ * mxs_batt_boot() - Configure the power block to boot from battery input
+ *
+ * This function configures the power block to boot from the battery voltage
+ * supply.
+ */
static void mxs_batt_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+
+ mxs_power_enable_4p2();
}
+/**
+ * mxs_handle_5v_conflict() - Test if the 5V input is reliable
+ *
+ * This function tests if the 5V input can reliably supply the system. If it
+ * can, then proceed to configuring the system to boot from 5V source, otherwise
+ * try booting from battery supply. If we can not boot from battery supply
+ * either, shut down the system.
+ */
static void mxs_handle_5v_conflict(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
}
}
+/**
+ * mxs_5v_boot() - Configure the power block to boot from 5V input
+ *
+ * This function handles configuration of the power block when supplied by
+ * a 5V input.
+ */
static void mxs_5v_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
mxs_handle_5v_conflict();
}
-static void mxs_fixed_batt_boot(void)
+/**
+ * mxs_init_batt_bo() - Configure battery brownout threshold
+ *
+ * This function configures the battery input brownout threshold. The value
+ * at which the battery brownout happens is configured to 3.0V in the code.
+ */
+static void mxs_init_batt_bo(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_PWDN_5VBRNOUT |
+ POWER_5VCTRL_ENABLE_DCDC |
+ POWER_5VCTRL_ILIMIT_EQ_ZERO |
+ POWER_5VCTRL_PWDN_5VBRNOUT |
+ POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET |
+ POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+ POWER_VDDACTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_DISABLE_FET |
+ POWER_VDDIOCTRL_DISABLE_STEPPING);
- /* Brownout at 3V */
+ /* Stop 5V detection */
+ writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
+ &power_regs->hw_power_5vctrl_clr);
+ }
+
+ static void mxs_init_batt_bo(void)
+ {
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
- 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+ BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
+/**
+ * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
+ *
+ * This function turns off the VDDD linear regulator and therefore makes
+ * the VDDD rail be supplied only by the DC-DC converter.
+ */
static void mxs_switch_vddd_to_dcdc_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
POWER_VDDDCTRL_DISABLE_STEPPING);
}
+/**
+ * mxs_power_configure_power_source() - Configure power block source
+ *
+ * This function is the core of the power configuration logic. The function
+ * selects the power block input source and configures the whole power block
+ * accordingly. After the configuration is complete and the system is stable
+ * again, the function switches the CPU clock source back to PLL. Finally,
+ * the function switches the voltage rails to DC-DC converter.
+ */
static void mxs_power_configure_power_source(void)
{
- int batt_ready, batt_good;
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
#endif
}
+/**
+ * mxs_enable_output_rail_protection() - Enable power rail protection
+ *
+ * This function enables overload protection on the power rails. This is
+ * triggered if the power rails' voltage drops rapidly due to overload and
+ * in such case, the supply to the powerrail is cut-off, protecting the
+ * CPU from damage. Note that under such condition, the system will likely
+ * crash or misbehave.
+ */
static void mxs_enable_output_rail_protection(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
+/**
+ * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
+ *
+ * This function tests if the VDDIO rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
static int mxs_get_vddio_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
- if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
+ !(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
+
tmp = readl(&power_regs->hw_power_vddioctrl);
if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
}
return 0;
-
}
+/**
+ * mxs_get_vddd_power_source_off() - Get VDDD rail power source
+ *
+ * This function tests if the VDDD rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
static int mxs_get_vddd_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
tmp = readl(&power_regs->hw_power_vdddctrl);
static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
uint32_t new_target, uint32_t new_brownout)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
- uint32_t powered_by_linreg = 0;
- int adjust_up, tmp;
+ int powered_by_linreg = 0;
+ int adjust_up;
+
+ if (new_target < cfg->lowest_mV)
+ new_target = cfg->lowest_mV;
+ if (new_target > cfg->highest_mV)
+ new_target = cfg->highest_mV;
- new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
+ new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
+ cfg->step_mV);
cur_target = readl(cfg->reg);
cur_target &= cfg->trg_mask;
#endif
}
+ #ifdef CONFIG_CONFIG_MACH_MX28EVK
+ #define auto_restart 1
+ #else
+ #define auto_restart 0
+ #endif
+
+/**
+ * mxs_power_init() - The power block init main function
+ *
+ * This function calls all the power block initialization functions in
+ * proper sequence to start the power block.
+ */
void mxs_power_init(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
mxs_ungate_power();
mxs_power_clock2xtal();
}
#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
+/**
+ * mxs_power_wait_pswitch() - Wait for power switch to be pressed
+ *
+ * This function waits until the power-switch was pressed to start booting
+ * the board.
+ */
void mxs_power_wait_pswitch(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}
TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
&timrot_regs->hw_timrot_timctrl0);
- /* Set fixed_count to maximal value */
++#ifndef DEBUG_TIMER_WRAP
+ /* Set fixed_count to maximum value */
#if defined(CONFIG_MX23)
writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
#elif defined(CONFIG_MX28)
writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
#endif
--
-#ifndef DEBUG_TIMER_WRAP
- /* Set fixed_count to maximum value */
- writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
-#else
++#else /* DEBUG_TIMER_WRAP */
+ /* Set fixed_count so that the counter will wrap after 20 seconds */
++#if defined(CONFIG_MX23)
++ writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
++#elif defined(CONFIG_MX28)
+ writel(20 * MXS_INCREMENTER_HZ,
+ &timrot_regs->hw_timrot_fixed_count0);
++#endif
+ gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ;
+
+ /* Make the usec counter roll over 30 seconds after startup */
+ writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS);
-#endif
++#endif /* DEBUG_TIMER_WRAP */
+ writel(TIMROT_TIMCTRLn_UPDATE,
+ &timrot_regs->hw_timrot_timctrl0_clr);
+ #ifdef DEBUG_TIMER_WRAP
- /* Set fixed_count to maximal value for subsequent loads */
++ /* Set fixed_count to maximum value for subsequent loads */
++#if defined(CONFIG_MX23)
++ writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
++#elif defined(CONFIG_MX28)
+ writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
+ #endif
++#endif /* DEBUG_TIMER_WRAP */
+ gd->arch.timer_rate_hz = MXS_INCREMENTER_HZ;
+ gd->arch.tbl = TIMER_START;
+ gd->arch.tbu = 0;
return 0;
}
/* Upper bits are the valid ones. */
now = readl(&timrot_regs->hw_timrot_timcount0) >>
TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
-#else
+#elif defined(CONFIG_MX28)
- now = readl(&timrot_regs->hw_timrot_running_count0);
+ /* The timer is counting down, so subtract the register value from
+ * the counter period length (implicitly 2^32) to get an incrementing
+ * timestamp
+ */
+ now = -readl(&timrot_regs->hw_timrot_running_count0);
+#else
+#error "Don't know how to read timrot_regs"
#endif
+ ulong inc = now - gd->arch.lastinc;
- if (lastdec >= now) {
- /*
- * normal mode (non roll)
- * move stamp forward with absolut diff ticks
- */
- timestamp += (lastdec - now);
- } else {
- /* we have rollover of decrementer */
- timestamp += (TIMER_LOAD_VAL - now) + lastdec;
-
- }
- lastdec = now;
-
- return timestamp;
+ if (gd->arch.tbl + inc < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl += inc;
+ gd->arch.lastinc = now;
+ return ((unsigned long long)gd->arch.tbu << 32) | gd->arch.tbl;
}
ulong get_timer_masked(void)
return omap_mmc_init(1, 0, 0, -1, -1);
}
+ /* let platform code be able to override this! */
+ int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__cpu_mmc_init")));
#endif
-void setup_clocks_for_console(void)
-{
- /* Not yet implemented */
- return;
-}
-
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
#include <asm/arch/hardware.h>
#include <asm/io.h>
-
+ #define PRCM_MOD_EN 0x2
+ #define PRCM_FORCE_WAKEUP 0x2
+ #define PRCM_FUNCTL 0x0
+
+ #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
+ #define PRCM_L3_GCLK_ACTIVITY BIT(4)
+
+ #define PLL_BYPASS_MODE 0x4
+ #define ST_MN_BYPASS 0x00000100
+ #define ST_DPLL_CLK 0x00000001
+ #define CLK_SEL_MASK 0x7ffff
+ #define CLK_DIV_MASK 0x1f
+ #define CLK_DIV2_MASK 0x7f
+ #define CLK_SEL_SHIFT 0x8
+ #define CLK_MODE_MASK 0x7
+ #define CLK_MODE_SEL 0x7
+ #define DPLL_CLKDCOLDO_GATE_CTRL 0x300
+
#define OSC (V_OSCK/1000000)
-#define MPUPLL_N (OSC-1)
+ #define MPUPLL_M CONFIG_SYS_MPUCLK
-#define COREPLL_N (OSC-1)
++#define MPUPLL_N (OSC - 1)
+ #define MPUPLL_M2 1
+
+ /* Core PLL Fdll = 1 GHZ, */
+ #define COREPLL_M 1000
-#define PERPLL_N (OSC-1)
++#define COREPLL_N (OSC - 1)
+
+ #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
+ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
+ #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+
+ /*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+ #define PERPLL_M 960
-#define DDRPLL_N (OSC-1)
++#define PERPLL_N (OSC - 1)
+ #define PERPLL_M2 5
+
+ /* DDR Freq is 266 MHZ for now */
+ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+ #define DDRPLL_M 266
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
-
-#ifdef CONFIG_SPL_BUILD
-#define enable_clk(reg, val) __enable_clk(#reg, ®, val)
++#define DDRPLL_N (OSC - 1)
+ #define DDRPLL_M2 1
+
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
+
+const struct dpll_regs dpll_mpu_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x88,
+ .cm_idlest_dpll = CM_WKUP + 0x20,
+ .cm_clksel_dpll = CM_WKUP + 0x2C,
+ .cm_div_m2_dpll = CM_WKUP + 0xA8,
+};
+
+const struct dpll_regs dpll_core_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x90,
+ .cm_idlest_dpll = CM_WKUP + 0x5C,
+ .cm_clksel_dpll = CM_WKUP + 0x68,
+ .cm_div_m4_dpll = CM_WKUP + 0x80,
+ .cm_div_m5_dpll = CM_WKUP + 0x84,
+ .cm_div_m6_dpll = CM_WKUP + 0xD8,
+};
+
+const struct dpll_regs dpll_per_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x8C,
+ .cm_idlest_dpll = CM_WKUP + 0x70,
+ .cm_clksel_dpll = CM_WKUP + 0x9C,
+ .cm_div_m2_dpll = CM_WKUP + 0xAC,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x94,
+ .cm_idlest_dpll = CM_WKUP + 0x34,
+ .cm_clksel_dpll = CM_WKUP + 0x40,
+ .cm_div_m2_dpll = CM_WKUP + 0xA0,
+};
+
+struct dpll_params dpll_mpu_opp100 = {
+ CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core_opp100 = {
+ 1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+ MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+ 50, OSC-1, -1, -1, 1, 1, 1};
+const struct dpll_params dpll_per = {
+ 960, OSC-1, 5, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+ return &dpll_mpu;
+}
-static void __enable_clk(const char *name, const void *reg, u32 mask)
+const struct dpll_params *get_dpll_core_params(void)
{
- unsigned long timeout = 10000000;
-
- writel(mask, reg);
- while (readl(reg) != mask)
- /* poor man's timeout, since timers not initialized */
- if (timeout-- == 0)
- /* no error message, since console not yet available */
- break;
+ return &dpll_core;
}
-static void enable_interface_clocks(void)
+const struct dpll_params *get_dpll_per_params(void)
{
- /* Enable all the Interconnect Modules */
- enable_clk(cmper->l3clkctrl, PRCM_MOD_EN);
- enable_clk(cmper->l4lsclkctrl, PRCM_MOD_EN);
- enable_clk(cmper->l4fwclkctrl, PRCM_MOD_EN);
- enable_clk(cmwkup->wkl4wkclkctrl, PRCM_MOD_EN);
- enable_clk(cmper->l3instrclkctrl, PRCM_MOD_EN);
- enable_clk(cmper->l4hsclkctrl, PRCM_MOD_EN);
-#ifdef CONFIG_HW_WATCHDOG
- enable_clk(cmwkup->wdtimer1ctrl, PRCM_MOD_EN);
-#endif
- /* GPIO0 */
- enable_clk(cmwkup->wkgpio0clkctrl, PRCM_MOD_EN);
+ return &dpll_per;
}
-/*
- * Force power domain wake up transition
- * Ensure that the corresponding interface clock is active before
- * using the peripheral
- */
-static void power_domain_wkup_transition(void)
+void setup_clocks_for_console(void)
{
- writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
+ clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+ clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+ clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ clrsetbits_le32(&cmper->uart1clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ clrsetbits_le32(&cmper->uart2clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ clrsetbits_le32(&cmper->uart3clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ clrsetbits_le32(&cmper->uart4clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ clrsetbits_le32(&cmper->uart5clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
+void enable_basic_clocks(void)
{
- /* Enable the control module though RBL would have done it*/
- enable_clk(cmwkup->wkctrlclkctrl, PRCM_MOD_EN);
- /* Enable the timer2 clock */
- enable_clk(cmper->timer2clkctrl, PRCM_MOD_EN);
+ u32 *const clk_domains[] = {
+ &cmper->l3clkstctrl,
+ &cmper->l4fwclkstctrl,
+ &cmper->l3sclkstctrl,
+ &cmper->l4lsclkstctrl,
+ &cmwkup->wkclkstctrl,
+ &cmper->emiffwclkctrl,
+ &cmrtc->clkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en[] = {
+ &cmper->l3clkctrl,
+ &cmper->l4lsclkctrl,
+ &cmper->l4fwclkctrl,
+ &cmwkup->wkl4wkclkctrl,
+ &cmper->l3instrclkctrl,
+ &cmper->l4hsclkctrl,
+ &cmwkup->wkgpio0clkctrl,
+ &cmwkup->wkctrlclkctrl,
+ &cmper->timer2clkctrl,
+ &cmper->gpmcclkctrl,
+ &cmper->elmclkctrl,
+ &cmper->mmc0clkctrl,
+ &cmper->mmc1clkctrl,
+ &cmwkup->wkup_i2c0ctrl,
+ &cmper->gpio1clkctrl,
+ &cmper->gpio2clkctrl,
+ &cmper->gpio3clkctrl,
+ &cmper->i2c1clkctrl,
+ &cmper->cpgmac0clkctrl,
+ &cmper->spi0clkctrl,
+ &cmrtc->rtcclkctrl,
+ &cmper->usb0clkctrl,
+ &cmper->emiffwclkctrl,
+ &cmper->emifclkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
/* Select the Master osc 24 MHZ as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
-
-#ifdef CONFIG_SYS_NS16550_COM1
- /* UART0 */
- enable_clk(cmwkup->wkup_uart0ctrl, PRCM_MOD_EN);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM2
- enable_clk(cmper->uart1clkctrl, PRCM_MOD_EN);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM3
- enable_clk(cmper->uart2clkctrl, PRCM_MOD_EN);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM4
- enable_clk(cmper->uart3clkctrl, PRCM_MOD_EN);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM5
- enable_clk(cmper->uart4clkctrl, PRCM_MOD_EN);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM6
- enable_clk(cmper->uart5clkctrl, PRCM_MOD_EN);
-#endif
- /* GPMC */
- enable_clk(cmper->gpmcclkctrl, PRCM_MOD_EN);
-
- /* ELM */
- enable_clk(cmper->elmclkctrl, PRCM_MOD_EN);
-
- /* Ethernet */
- enable_clk(cmper->cpswclkstctrl, PRCM_MOD_EN);
- enable_clk(cmper->cpgmac0clkctrl, PRCM_MOD_EN);
-
- /* MMC */
-#ifdef CONFIG_OMAP_MMC_DEV_0
- enable_clk(cmper->mmc0clkctrl, PRCM_MOD_EN);
-#endif
-#ifdef CONFIG_OMAP_MMC_DEV_1
- enable_clk(cmper->mmc1clkctrl, PRCM_MOD_EN);
-#endif
- /* LCD */
- enable_clk(cmper->lcdclkctrl, PRCM_MOD_EN);
-
- /* MMC1 */
- writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
- while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* i2c0 */
- enable_clk(cmwkup->wkup_i2c0ctrl, PRCM_MOD_EN);
-
- /* GPIO1-3 */
- enable_clk(cmper->gpio1clkctrl, PRCM_MOD_EN);
- enable_clk(cmper->gpio2clkctrl, PRCM_MOD_EN);
- enable_clk(cmper->gpio3clkctrl, PRCM_MOD_EN);
-
- /* i2c1 */
- enable_clk(cmper->i2c1clkctrl, PRCM_MOD_EN);
-
- /* spi0 */
- enable_clk(cmper->spi0clkctrl, PRCM_MOD_EN);
-
- /* rtc */
- enable_clk(cmrtc->rtcclkctrl, PRCM_MOD_EN);
-
- /* usb0 */
- enable_clk(cmper->usb0clkctrl, PRCM_MOD_EN);
}
-#endif /* CONFIG_SPL_BUILD */
-
+ void mpu_pll_config_val(int mpull_m)
+ {
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddpllmpu);
+ clksel = readl(&cmwkup->clkseldpllmpu);
+ div_m2 = readl(&cmwkup->divm2dpllmpu);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
+ while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
+ ;
+
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (mpull_m << CLK_SEL_SHIFT) | MPUPLL_N;
+ writel(clksel, &cmwkup->clkseldpllmpu);
+
+ div_m2 &= ~CLK_DIV_MASK;
+ div_m2 |= MPUPLL_M2;
+ writel(div_m2, &cmwkup->divm2dpllmpu);
+
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllmpu);
+
+ while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
+ ;
+ }
+
+ void mpu_pll_config(void)
+ {
+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+ }
+
+ static void core_pll_config_val(int m)
+ {
+ u32 clkmode, clksel, div_m4, div_m5, div_m6;
+
+ clkmode = readl(&cmwkup->clkmoddpllcore);
+ clksel = readl(&cmwkup->clkseldpllcore);
+ div_m4 = readl(&cmwkup->divm4dpllcore);
+ div_m5 = readl(&cmwkup->divm5dpllcore);
+ div_m6 = readl(&cmwkup->divm6dpllcore);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
+
+ while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
+ ;
+
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= ((m << CLK_SEL_SHIFT) | COREPLL_N);
+ writel(clksel, &cmwkup->clkseldpllcore);
+
+ div_m4 &= ~CLK_DIV_MASK;
+ div_m4 |= COREPLL_M4;
+ writel(div_m4, &cmwkup->divm4dpllcore);
+
+ div_m5 &= ~CLK_DIV_MASK;
+ div_m5 |= COREPLL_M5;
+ writel(div_m5, &cmwkup->divm5dpllcore);
+
+ div_m6 &= ~CLK_DIV_MASK;
+ div_m6 |= COREPLL_M6;
+ writel(div_m6, &cmwkup->divm6dpllcore);
+
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllcore);
+
+ while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+ ;
+ }
+
+ static inline void core_pll_config(void)
+ {
+ core_pll_config_val(COREPLL_M);
+ }
+
+ static void per_pll_config_val(int m)
+ {
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddpllper);
+ clksel = readl(&cmwkup->clkseldpllper);
+ div_m2 = readl(&cmwkup->divm2dpllper);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
+
+ while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
+ ;
+
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (m << CLK_SEL_SHIFT) | PERPLL_N;
+ writel(clksel, &cmwkup->clkseldpllper);
+
+ div_m2 &= ~CLK_DIV2_MASK;
+ div_m2 |= PERPLL_M2;
+ writel(div_m2, &cmwkup->divm2dpllper);
+
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllper);
+
+ while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
+ ;
+
+ writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
+ }
+
+ static inline void per_pll_config(void)
+ {
+ per_pll_config_val(PERPLL_M);
+ }
+
+ static void disp_pll_config_val(int m)
+ {
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddplldisp);
+ clksel = readl(&cmwkup->clkseldplldisp);
+ div_m2 = readl(&cmwkup->divm2dplldisp);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp);
+
+ while (!(readl(&cmwkup->idlestdplldisp) & ST_MN_BYPASS))
+ ;
+
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (m << CLK_SEL_SHIFT) | DISPPLL_N;
+ writel(clksel, &cmwkup->clkseldplldisp);
+
+ div_m2 &= ~CLK_DIV2_MASK;
+ div_m2 |= DISPPLL_M2;
+ writel(div_m2, &cmwkup->divm2dplldisp);
+
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddplldisp);
+
+ while (!(readl(&cmwkup->idlestdplldisp) & ST_DPLL_CLK))
+ ;
+ }
+
+ static inline void disp_pll_config(void)
+ {
+ disp_pll_config_val(DISPPLL_M);
+ }
+
+ void ddr_pll_config(unsigned int ddrpll_m)
+ {
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddpllddr);
+ clksel = readl(&cmwkup->clkseldpllddr);
+ div_m2 = readl(&cmwkup->divm2dpllddr);
+
+ /* Set the PLL to bypass Mode */
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= PLL_BYPASS_MODE;
+ writel(clkmode, &cmwkup->clkmoddpllddr);
+
+ /* Wait till bypass mode is enabled */
+ while (!(readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS))
+ ;
+
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N;
+ writel(clksel, &cmwkup->clkseldpllddr);
+
+ div_m2 &= ~CLK_DIV_MASK;
+ div_m2 |= DDRPLL_M2;
+ writel(div_m2, &cmwkup->divm2dpllddr);
+
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllddr);
+
+ /* Wait till dpll is locked */
+ while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
+ ;
+ }
+
-#ifdef CONFIG_SPL_BUILD
-void enable_emif_clocks(void)
-{
- /* Enable the EMIF_FW Functional clock */
- writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
- /* Enable EMIF0 Clock */
- writel(PRCM_MOD_EN, &cmper->emifclkctrl);
- /* Poll if module is functional */
- while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
- ;
-}
-
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void pll_init()
-{
- mpu_pll_config();
- core_pll_config();
- per_pll_config();
- disp_pll_config();
-
- /* Enable the required interconnect clocks */
- enable_interface_clocks();
-
- /* Power domain wake up transition */
- power_domain_wkup_transition();
-
- /* Enable the required peripherals */
- enable_per_clocks();
-}
-#endif
-
+ #define M(mn) (((mn) & CLK_SEL_MASK) >> CLK_SEL_SHIFT)
+ #define N(mn) ((mn) & CLK_DIV2_MASK)
+
+ unsigned long __clk_get_rate(u32 m_n, u32 div_m2)
+ {
+ unsigned long rate;
+
+ div_m2 &= CLK_DIV_MASK;
+ debug("M=%u N=%u M2=%u\n", M(m_n), N(m_n), div_m2);
+ rate = V_OSCK / 1000 * M(m_n) / (N(m_n) + 1) / div_m2;
+ debug("CLK = %lu.%03luMHz\n", rate / 1000, rate % 1000);
+ return rate * 1000;
+ }
+
+ unsigned long lcdc_clk_rate(void)
+ {
+ return clk_get_rate(cmwkup, disp);
+ }
+
+ unsigned long mpu_clk_rate(void)
+ {
+ return clk_get_rate(cmwkup, mpu);
+ }
+
+ enum {
+ CLK_MPU_PLL,
+ CLK_CORE_PLL,
+ CLK_PER_PLL,
+ CLK_DISP_PLL,
+ CLK_GPMC,
+ };
+
+ static struct clk_lookup {
+ const char *name;
+ unsigned int index;
+ } am33xx_clk_lookup[] = {
+ { "mpu", CLK_MPU_PLL, },
+ { "core", CLK_CORE_PLL, },
+ { "per", CLK_PER_PLL, },
+ { "lcdc", CLK_DISP_PLL, },
+ { "gpmc", CLK_GPMC, },
+ };
+
+ #define print_pll(dom, pll) { \
+ u32 __pll = clk_get_rate(dom, pll); \
+ printf("%-12s %4d.%03d MHz\n", #pll, \
+ __pll / 1000000, __pll / 1000 % 1000); \
+ }
+
+ #define print_pll2(dom, n, pll) { \
+ u32 __m_n = readl(&(dom)->clkseldpll##pll); \
+ u32 __div = readl(&(dom)->divm##n##dpll##pll); \
+ u32 __pll = __clk_get_rate(__m_n, __div); \
+ printf("%-12s %4d.%03d MHz\n", #pll "_m" #n, \
+ __pll / 1000000, __pll / 1000 % 1000); \
+ }
+
+ static void do_showclocks(void)
+ {
+ print_pll(cmwkup, mpu);
+ print_pll2(cmwkup, 4, core);
+ print_pll2(cmwkup, 5, core);
+ print_pll2(cmwkup, 6, core);
+ print_pll(cmwkup, ddr);
+ print_pll(cmwkup, per);
+ print_pll(cmwkup, disp);
+ }
+
+ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+ {
+ int i;
+ unsigned long freq;
+ unsigned long __attribute__((unused)) ref = ~0UL;
+
+ if (argc < 2) {
+ do_showclocks();
+ return CMD_RET_SUCCESS;
+ } else if (argc == 2 || argc > 4) {
+ return CMD_RET_USAGE;
+ }
+
+ freq = simple_strtoul(argv[2], NULL, 0);
+ if (freq < 1000) {
+ printf("Invalid clock frequency %lu\n", freq);
+ return CMD_RET_FAILURE;
+ }
+ if (argc > 3) {
+ ref = simple_strtoul(argv[3], NULL, 0);
+ }
+ for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) {
+ if (strcasecmp(argv[1], am33xx_clk_lookup[i].name) == 0) {
+ switch (am33xx_clk_lookup[i].index) {
+ case CLK_MPU_PLL:
+ mpu_pll_config_val(freq / 1000000);
+ break;
+ case CLK_CORE_PLL:
+ core_pll_config_val(freq / 1000000);
+ break;
+ case CLK_PER_PLL:
+ per_pll_config_val(freq / 1000000);
+ break;
+ case CLK_DISP_PLL:
+ disp_pll_config_val(freq / 1000000);
+ break;
+ default:
+ printf("Cannot change %s clock\n",
+ am33xx_clk_lookup[i].name);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("%s clock set to %lu.%03lu MHz\n",
+ am33xx_clk_lookup[i].name,
+ freq / 1000000, freq / 1000 % 1000);
+ return CMD_RET_SUCCESS;
+ }
+ }
+ if (i == ARRAY_SIZE(am33xx_clk_lookup)) {
+ printf("clock %s not found; supported clocks are:\n", argv[1]);
+ for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) {
+ printf("\t%s\n", am33xx_clk_lookup[i].name);
+ }
+ } else {
+ printf("Failed to set clock %s to %s MHz\n",
+ argv[1], argv[2]);
+ }
+ return CMD_RET_FAILURE;
+ }
+
+ U_BOOT_CMD(
+ clocks, 4, 0, do_clocks,
+ "display/set clocks",
+ " - display clock settings\n"
+ "clocks <clkname> <freq> - set clock <clkname> to <freq> Hz"
+ );
/**
* Base address for ddr io control instances
*/
- static struct ddr_cmdtctrl *ioctrl_reg = {
- (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+ static struct ddr_cmdtctrl *ioctrl_reg =
+ (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR;
- * Configure EMIF4D5 registers and MR registers
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+ u32 mr;
+
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+ mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+ debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+ if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
+ ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+ ((mr & 0xff000000) >> 24) == (mr & 0xff))
+ return mr & 0xff;
+ else
+ return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+ writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+ u32 mr_addr;
+
+ while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+ ;
+ set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+ set_mr(nr, cs, LPDDR2_MR1, 0x43);
+ set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+ set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
- writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
++ * Configure EMIF4D5 registers and MR registers For details about these magic
++ * values please see the EMIF registers section of the TRM.
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+ writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+ writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+ writel(regs->emif_rd_wr_lvl_rmp_win,
+ &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+ writel(regs->emif_rd_wr_lvl_rmp_ctl,
+ &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+ writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+ writel(regs->emif_rd_wr_exec_thresh,
+ &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+ /*
+ * for most SOCs these registers won't need to be changed so only
+ * write to these registers if someone explicitly has set the
+ * register's value.
+ */
+ if(regs->emif_cos_config) {
+ writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+ writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+ writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+ writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+ }
+
++ /*
++ * Sequence to ensure that the PHY is in a known state prior to
++ * startting hardware leveling. Also acts as to latch some state from
++ * the EMIF into the PHY.
++ */
++ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
++ writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
++ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
++
++ clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
++ EMIF_REG_INITREF_DIS_MASK);
++
+ writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+ writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
++ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
++ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
++
++ /* Perform hardware leveling. */
++ udelay(1000);
++ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
++ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
++ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
++ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
++
++ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
++
++ /* Enable read leveling */
++ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
++
++ /*
++ * Enable full read and write leveling. Wait for read and write
++ * leveling bit to clear RDWRLVLFULL_START bit 31
++ */
++ while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
++ ;
++
++ /* Check the timeout register to see if leveling is complete */
++ if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
++ puts("DDR3 H/W leveling incomplete with errors\n");
+
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+ configure_mr(nr, 0);
+ configure_mr(nr, 1);
+ }
+}
+
/**
* Configure SDRAM
*/
void config_sdram(const struct emif_regs *regs, int nr)
{
if (regs->zq_config) {
-- /*
-- * A value of 0x2800 for the REF CTRL will give us
-- * about 570us for a delay, which will be long enough
-- * to configure things.
-- */
-- writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
- writel(regs->sdram_config, &cstat->emif_sdram_config);
+ writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
}
++ writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
-- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}
/**
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}
- void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
- {
- }
-
+/*
- * Configure EXT PHY registers
++ * Configure EXT PHY registers for hardware leveling
+ */
+static void ext_phy_settings(const struct emif_regs *regs, int nr)
+{
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- const u32 *ext_phy_ctrl_const_regs;
- u32 i = 0;
- u32 size;
-
- ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base =
- (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
+ /*
- * external phy 6-24 registers do not change with
- * ddr frequency
++ * Enable hardware leveling on the EMIF. For details about these
++ * magic values please see the EMIF registers section of the TRM.
+ */
- emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
-
- if (!size)
- return;
++ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
++ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
++ writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
++ writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
++ writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
++ writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
++ writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
++ writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
++ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
++ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
++ writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
++ writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
- for (i = 0; i < size; i++) {
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- }
++ /*
++ * Sequence to ensure that the PHY is again in a known state after
++ * hardware leveling.
++ */
++ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
++ writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
++ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+}
+
/**
* Configure DDR PHY
*/
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
- * disable initialization and refreshes for now until we
+ /*
++ * Disable initialization and refreshes for now until we
+ * finish programming EMIF regs.
++ * Also set time between rising edge of DDR_RESET to rising
++ * edge of DDR_CKE to > 500us per memory spec.
+ */
++#ifndef CONFIG_AM43XX
+ setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+ EMIF_REG_INITREF_DIS_MASK);
++#endif
++ if (regs->zq_config)
++ writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1,
/*
* Setup a temporary stack
*/
+ #ifndef CONFIG_SPL_BUILD
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
+ #else
+ ldr sp, =CONFIG_SPL_STACK
+ #endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_SPL_BUILD
- ldr r8, =gdata
+ ldr r9, =gdata
#else
- sub sp, #GD_SIZE
+ sub sp, sp, #GD_SIZE
bic sp, sp, #7
- mov r8, sp
+ mov r9, sp
#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
MXC_CCM_CCGR2_USBOH3_60M(cg));
}
-#ifdef CONFIG_I2C_MXC
+ void ipu_clk_enable(void)
+ {
+ /* IPU root clock derived from AXI B */
+ clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK,
+ MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1));
+
+ setbits_le32(&mxc_ccm->CCGR5,
+ MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+
+ /* Handshake with IPU when certain clock rates are changed. */
+ clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+
+ /* Handshake with IPU when LPM is entered as its enabled. */
+ clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+ }
+
+ void ipu_clk_disable(void)
+ {
+ clrbits_le32(&mxc_ccm->CCGR5,
+ MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+
+ /* Handshake with IPU when certain clock rates are changed. */
+ setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+
+ /* Handshake with IPU when LPM is entered as its enabled. */
+ setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+ }
+
+ void ipu_di_clk_enable(int di)
+ {
+ switch (di) {
+ case 0:
+ setbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
+ break;
+ case 1:
+ setbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
+ break;
+ default:
+ printf("%s: Invalid DI index %d\n", __func__, di);
+ }
+ }
+
+ void ipu_di_clk_disable(int di)
+ {
+ switch (di) {
+ case 0:
+ clrbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
+ break;
+ case 1:
+ clrbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
+ break;
+ default:
+ printf("%s: Invalid DI index %d\n", __func__, di);
+ }
+ }
+
+ #ifdef CONFIG_MX53
+ void ldb_clk_enable(int ldb)
+ {
+ switch (ldb) {
+ case 0:
+ setbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
+ break;
+ case 1:
+ setbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
+ break;
+ default:
+ printf("%s: Invalid LDB index %d\n", __func__, ldb);
+ }
+ }
+
+ void ldb_clk_disable(int ldb)
+ {
+ switch (ldb) {
+ case 0:
+ clrbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
+ break;
+ case 1:
+ clrbits_le32(&mxc_ccm->CCGR6,
+ MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
+ break;
+ default:
+ printf("%s: Invalid LDB index %d\n", __func__, ldb);
+ }
+ }
+ #endif
+
+#ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
+ #if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
setup_pll PLL1_BASE_ADDR, 800
+ #elif CONFIG_SYS_CPU_CLK == 600
+ setup_pll PLL1_BASE_ADDR, 600
+ #else
+ #error Unsupported CONFIG_SYS_CPU_CLK value
+ #endif
- setup_pll PLL3_BASE_ADDR, 400
+ setup_pll PLL3_BASE_ADDR, 400
-
+ #ifndef CONFIG_TX53
- /* Switch peripheral to PLL3 */
- ldr r1, =0x00015154
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x02898945
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure change is effective */
+ /* Switch peripheral to PLL3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x02898945
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
+ tst r1, #0x7f
- bne 1b
+ bne 1b
- setup_pll PLL2_BASE_ADDR, 400
+ setup_pll PLL2_BASE_ADDR, 400
/* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00888945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
+ tst r1, #0x7f
bne 1b
+ setup_pll PLL3_BASE_ADDR, 216
+
setup_pll PLL4_BASE_ADDR, 455
+ #else /* CONFIG_TX53 */
+ /* Switch peripheral to PLL 3 */
+ ldr r1, [r0, #CLKCTL_CBCMR]
+ bic r1, #(0x3 << 12)
+ orr r1, r1, #(1 << 12)
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ ldr r1, [r0, #CLKCTL_CBCDR]
+ orr r1, r1, #(1 << 25)
+ str r1, [r0, #CLKCTL_CBCDR]
+ 1:
+ /* make sure change is effective */
+ ldr r1, [r0, #CLKCTL_CDHIPR]
+ tst r1, #0x7f
+ bne 1b
+
+ #if CONFIG_SYS_SDRAM_CLK == 533
+ setup_pll PLL2_BASE_ADDR, 533
+ #elif CONFIG_SYS_SDRAM_CLK == 400
+ setup_pll PLL2_BASE_ADDR, 400
+ #elif CONFIG_SYS_SDRAM_CLK == 333
+ setup_pll PLL2_BASE_ADDR, 333
+ #else
+ #error Unsupported CONFIG_SYS_SDRAM_CLK
+ #endif
+
+ /* Switch peripheral to PLL2 */
+ ldr r1, [r0, #CLKCTL_CBCDR]
+ bic r1, #(1 << 25)
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, [r0, #CLKCTL_CBCMR]
+ bic r1, #(3 << 12)
+ orr r1, #(2 << 12)
+ str r1, [r0, #CLKCTL_CBCMR]
+ #endif
+ setup_pll PLL3_BASE_ADDR, 216
+
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
ldr r1, =0x00000124
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
+
+ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+ __attribute__((weak, alias("__imx_get_mac_from_fuse")));
+
#endif
-void set_chipselect_size(int const cs_size)
-{
- unsigned int reg;
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- reg = readl(&iomuxc_regs->gpr1);
-
- switch (cs_size) {
- case CS0_128:
- reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
- reg |= 0x5;
- break;
- case CS0_64M_CS1_64M:
- reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
- reg |= 0x1B;
- break;
- case CS0_64M_CS1_32M_CS2_32M:
- reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
- reg |= 0x4B;
- break;
- case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
- reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
- reg |= 0x249;
- break;
- default:
- printf("Unknown chip select size: %d\n", cs_size);
- break;
- }
-
- writel(reg, &iomuxc_regs->gpr1);
-}
-
-void cpu_cache_initialization(void)
-{
- printf("Enabling L2 cache\n");
- asm volatile(
- "mrc 15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #0x2\n"
- "mcr 15, 0, r0, c1, c0, 1\n"
- : : : "r0", "memory"
- );
-}
-
#ifdef CONFIG_MX53
void boot_mode_apply(unsigned cfg_val)
{
#include <asm/arch/sys_proto.h>
enum pll_clocks {
- PLL_SYS, /* System PLL */
- PLL_BUS, /* System Bus PLL*/
- PLL_USBOTG, /* OTG USB PLL */
- PLL_ENET, /* ENET PLL */
+ PLL_ARM, /* PLL1: ARM PLL */
- PLL_BUS, /* PLL2: System Bus PLL*/
++ PLL_528, /* PLL2: System Bus PLL*/
+ PLL_USBOTG, /* PLL3: OTG USB PLL */
+ PLL_AUDIO, /* PLL4: Audio PLL */
+ PLL_VIDEO, /* PLL5: Video PLL */
+ PLL_ENET, /* PLL6: ENET PLL */
+ PLL_USB2, /* PLL7: USB2 PLL */
+ PLL_MLB, /* PLL8: MLB PLL */
};
- struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
+ struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
+
+ int clk_enable(struct clk *clk)
+ {
+ int ret = 0;
+
+ if (!clk)
+ return 0;
+ if (clk->usecount == 0) {
-debug("%s: Enabling %s clock\n", __func__, clk->name);
++ debug("%s: Enabling %s clock\n", __func__, clk->name);
+ ret = clk->enable(clk);
+ if (ret)
+ return ret;
+ clk->usecount++;
+ }
+ assert(clk->usecount > 0);
+ return ret;
+ }
+
+ void clk_disable(struct clk *clk)
+ {
+ if (!clk)
+ return;
+
+ assert(clk->usecount > 0);
+ if (!(--clk->usecount)) {
+ if (clk->disable) {
-debug("%s: Disabling %s clock\n", __func__, clk->name);
++ debug("%s: Disabling %s clock\n", __func__, clk->name);
+ clk->disable(clk);
+ }
+ }
+ }
+
+ int clk_get_usecount(struct clk *clk)
+ {
+ if (clk == NULL)
+ return 0;
+
+ return clk->usecount;
+ }
+
+ u32 clk_get_rate(struct clk *clk)
+ {
+ if (!clk)
+ return 0;
+
+ return clk->rate;
+ }
+
+ struct clk *clk_get_parent(struct clk *clk)
+ {
+ if (!clk)
+ return 0;
+
+ return clk->parent;
+ }
+
+ int clk_set_rate(struct clk *clk, unsigned long rate)
+ {
+ if (clk && clk->set_rate)
+ clk->set_rate(clk, rate);
+ return clk->rate;
+ }
+
+ long clk_round_rate(struct clk *clk, unsigned long rate)
+ {
+ if (clk == NULL || !clk->round_rate)
+ return 0;
+
+ return clk->round_rate(clk, rate);
+ }
+
+ int clk_set_parent(struct clk *clk, struct clk *parent)
+ {
+ debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
+ clk ? clk->parent : NULL);
+
+ if (!clk || clk == parent)
+ return 0;
+
+ if (clk->set_parent) {
+ int ret;
+
+ ret = clk->set_parent(clk, parent);
+ if (ret)
+ return ret;
+ }
+ clk->parent = parent;
+ return 0;
+ }
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
u32 div;
switch (pll) {
- case PLL_SYS:
- div = __raw_readl(&imx_ccm->analog_pll_sys);
- div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
-
- return (infreq * div) >> 1;
- case PLL_BUS:
- div = __raw_readl(&imx_ccm->analog_pll_528);
+ case PLL_ARM:
+ div = __raw_readl(&anatop->pll_arm);
+ if (div & BM_ANADIG_PLL_ARM_BYPASS)
+ /* Assume the bypass clock is always derived from OSC */
+ return infreq;
+ div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
+
+ return infreq * div / 2;
- case PLL_BUS:
++ case PLL_528:
+ div = __raw_readl(&anatop->pll_528);
- if (div & BM_ANADIG_PLL_SYS_BYPASS)
++ if (div & BM_ANADIG_PLL_528_BYPASS)
+ return infreq;
- div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
+ div &= BM_ANADIG_PLL_528_DIV_SELECT;
- return infreq * (20 + (div << 1));
+ return infreq * (20 + div * 2);
case PLL_USBOTG:
- div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
- div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
-
- return infreq * (20 + (div << 1));
+ div = __raw_readl(&anatop->usb1_pll_480_ctrl);
- if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
++ if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+ return infreq;
- div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
++ div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+
+ return infreq * (20 + div * 2);
+ case PLL_AUDIO:
+ div = __raw_readl(&anatop->pll_audio);
+ if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
+ return infreq;
+ div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
+
+ return infreq * div;
+ case PLL_VIDEO:
+ div = __raw_readl(&anatop->pll_video);
+ if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
+ return infreq;
+ div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+
+ return infreq * div;
case PLL_ENET:
- div = __raw_readl(&imx_ccm->analog_pll_enet);
+ div = __raw_readl(&anatop->pll_enet);
+ if (div & BM_ANADIG_PLL_ENET_BYPASS)
+ return infreq;
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
- return (div == 3 ? 125000000 : 25000000 * div * 2);
+ return 25000000 * (div + (div >> 1) + 1);
- default:
+ case PLL_USB2:
+ div = __raw_readl(&anatop->usb2_pll_480_ctrl);
- if (div & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS)
++ if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+ return infreq;
- div &= BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT;
++ div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+
+ return infreq * (20 + div * 2);
+ case PLL_MLB:
+ div = __raw_readl(&anatop->pll_mlb);
+ if (div & BM_ANADIG_PLL_MLB_BYPASS)
+ return infreq;
+ /* unknown external clock provided on MLB_CLK pin */
return 0;
}
- /* NOTREACHED */
+ return 0;
}
- case PLL_BUS:
+static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
+{
+ u32 div;
+ u64 freq;
++ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+
+ switch (pll) {
- /* No PFD3 on PPL2 */
++ case PLL_528:
+ if (pfd_num == 3) {
- div = __raw_readl(&imx_ccm->analog_pfd_528);
- freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
++ /* No PFD3 on PLL2 */
+ return 0;
+ }
- div = __raw_readl(&imx_ccm->analog_pfd_480);
++ div = __raw_readl(&anatop->pfd_528);
++ freq = (u64)decode_pll(PLL_528, MXC_HCLK);
+ break;
+ case PLL_USBOTG:
- /* No PFD on other PLL */
++ div = __raw_readl(&anatop->pfd_480);
+ freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ default:
++ /* No PFD on other PLL */
+ return 0;
+ }
+
+ return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+ ANATOP_PFD_FRAC_SHIFT(pfd_num));
+}
static u32 get_mcu_main_clk(void)
{
switch (reg) {
case 0:
-- freq = decode_pll(PLL_BUS, MXC_HCLK);
++ freq = decode_pll(PLL_528, MXC_HCLK);
break;
case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
- freq = PLL2_PFD2_FREQ;
++ freq = mxc_get_pll_pfd(PLL_528, 2);
break;
case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
- freq = PLL2_PFD0_FREQ;
++ freq = mxc_get_pll_pfd(PLL_528, 0);
break;
case 3:
- freq = PLL2_PFD2_DIV_FREQ;
+ /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
- break;
- default:
++ freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
break;
}
}
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- root_freq = PLL2_PFD2_FREQ;
++ root_freq = mxc_get_pll_pfd(PLL_528, 2);
else
- root_freq = PLL3_PFD1_FREQ;
+ root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
} else
root_freq = get_periph_clk();
root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 2:
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- root_freq = PLL2_PFD2_FREQ;
++ root_freq = mxc_get_pll_pfd(PLL_528, 2);
break;
case 3:
- root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
- root_freq = PLL2_PFD0_FREQ;
++ root_freq = mxc_get_pll_pfd(PLL_528, 0);
break;
}
- return root_freq / (emi_slow_pof + 1);
+ return root_freq / (emi_slow_podf + 1);
}
- root_freq = PLL2_PFD0_FREQ;
+ static u32 get_nfc_clk(void)
+ {
+ u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
+ u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
+ u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
+ int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
+ u32 root_freq;
+
+ switch (nfc_clk_sel) {
+ case 0:
- root_freq = decode_pll(PLL_BUS, MXC_HCLK);
++ root_freq = mxc_get_pll_pfd(PLL_528, 0);
+ break;
+ case 1:
- root_freq = PLL2_PFD2_FREQ;
++ root_freq = decode_pll(PLL_528, MXC_HCLK);
+ break;
+ case 2:
+ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ case 3:
- root_freq = PLL2_PFD0_FREQ;
++ root_freq = mxc_get_pll_pfd(PLL_528, 2);
+ break;
+ }
+
+ return root_freq / (pred + 1) / (podf + 1);
+ }
+
+ #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
+
+ static int set_nfc_clk(u32 ref, u32 freq_khz)
+ {
+ u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
+ u32 podf;
+ u32 pred;
+ int nfc_clk_sel;
+ u32 root_freq;
+ u32 min_err = ~0;
+ u32 nfc_val = ~0;
+ u32 freq = freq_khz * 1000;
+
+ for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
+ u32 act_freq;
+ u32 err;
+
+ if (ref < 4 && ref != nfc_clk_sel)
+ continue;
+
+ switch (nfc_clk_sel) {
+ case 0:
- root_freq = decode_pll(PLL_BUS, MXC_HCLK);
++ root_freq = mxc_get_pll_pfd(PLL_528, 0);
+ break;
+ case 1:
- root_freq = PLL2_PFD2_FREQ;
++ root_freq = decode_pll(PLL_528, MXC_HCLK);
+ break;
+ case 2:
+ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ case 3:
- podf = min(DIV_ROUND_UP(root_freq, freq), 1 << 6);
- pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8);
++ root_freq = mxc_get_pll_pfd(PLL_528, 2);
+ break;
+ }
+ if (root_freq < freq)
+ continue;
+
-#ifdef CONFIG_MX6SL
++ podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
++ pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
+ act_freq = root_freq / pred / podf;
+ err = (freq - act_freq) * 100 / freq;
+ debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
+ nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
+ if (act_freq > freq)
+ continue;
+ if (err < min_err) {
+ nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
+ nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
+ nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
+ min_err = err;
+ if (err == 0)
+ break;
+ }
+ }
+
+ if (nfc_val == ~0 || min_err > 10)
+ return -EINVAL;
+
+ if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
+ debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
+ (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
+ __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
+ &imx_ccm->cs2cdr);
+ } else {
+ debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
+ }
+ return 0;
+ }
+
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
case 0:
-- freq = decode_pll(PLL_BUS, MXC_HCLK);
++ freq = decode_pll(PLL_528, MXC_HCLK);
break;
case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
- freq = PLL2_PFD2_FREQ;
++ freq = mxc_get_pll_pfd(PLL_528, 2);
break;
case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
- freq = PLL2_PFD0_FREQ;
++ freq = mxc_get_pll_pfd(PLL_528, 0);
break;
case 3:
- freq = PLL2_PFD2_DIV_FREQ;
+ /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
++ freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
}
return freq / (podf + 1);
}
if (clk_sel)
- root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
- root_freq = PLL2_PFD0_FREQ;
++ root_freq = mxc_get_pll_pfd(PLL_528, 0);
else
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- root_freq = PLL2_PFD2_FREQ;
++ root_freq = mxc_get_pll_pfd(PLL_528, 2);
return root_freq / (usdhc_podf + 1);
}
u32 imx_get_fecclk(void)
{
- return decode_pll(PLL_ENET, MXC_HCLK);
+ return mxc_get_clock(MXC_IPG_CLK);
}
-int enable_sata_clock(void)
+static int enable_enet_pll(uint32_t en)
{
- struct mxc_ccm_reg *const imx_ccm
- = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
+ u32 reg;
s32 timeout = 100000;
- u32 reg = 0;
- /* Enable sata clock */
- reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
- reg |= MXC_CCM_CCGR5_SATA_MASK;
- writel(reg, &imx_ccm->CCGR5);
-
/* Enable PLLs */
- reg = readl(&imx_ccm->analog_pll_enet);
- reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
- writel(reg, &imx_ccm->analog_pll_enet);
- reg |= BM_ANADIG_PLL_SYS_ENABLE;
+ reg = readl(&anatop->pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+ writel(reg, &anatop->pll_enet);
+ reg |= BM_ANADIG_PLL_ENET_ENABLE;
while (timeout--) {
- if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+ if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
break;
}
if (timeout <= 0)
return -EIO;
- reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
- writel(reg, &imx_ccm->analog_pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+ writel(reg, &anatop->pll_enet);
- reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
+ reg |= en;
- writel(reg, &imx_ccm->analog_pll_enet);
+ writel(reg, &anatop->pll_enet);
+ return 0;
+}
+
+#ifndef CONFIG_MX6SX
+static void ungate_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- return 0 ;
+ /* Enable SATA clock. */
+ setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
+#endif
+
+static void ungate_pcie_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* Enable PCIe clock. */
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
+#ifndef CONFIG_MX6SX
+int enable_sata_clock(void)
+{
+ ungate_sata_clock();
+ return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
+}
+
+void disable_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
+#endif
+
+int enable_pcie_clock(void)
+{
+ struct anatop_regs *anatop_regs =
+ (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 lvds1_clk_sel;
+
+ /*
+ * Here be dragons!
+ *
+ * The register ANATOP_MISC1 is not documented in the Freescale
+ * MX6RM. The register that is mapped in the ANATOP space and
+ * marked as ANATOP_MISC1 is actually documented in the PMU section
+ * of the datasheet as PMU_MISC1.
+ *
+ * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
+ * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
+ * for PCI express link that is clocked from the i.MX6.
+ */
+#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
+#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
+
+ if (is_cpu_type(MXC_CPU_MX6SX))
+ lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
+ else
+ lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
+
+ clrsetbits_le32(&anatop_regs->ana_misc1,
+ ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+ ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+ ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
+
+ /* PCIe reference clock sourced from AXI. */
+ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
+
+ /* Party time! Ungate the clock to the PCIe. */
+#ifndef CONFIG_MX6SX
+ ungate_sata_clock();
+#endif
+ ungate_pcie_clock();
+
+ return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
+ BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+}
+
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+ u32 reg;
+
+ /* CG4 ~ CG6, CAAM clocks */
+ reg = __raw_readl(&imx_ccm->CCGR0);
+ if (enable)
+ reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ else
+ reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ __raw_writel(reg, &imx_ccm->CCGR0);
+
+ /* EMI slow clk */
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
+static void enable_pll3(void)
+{
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+ /* make sure pll3 is enabled */
+ if ((readl(&anatop->usb1_pll_480_ctrl) &
- BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
++ BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
+ /* enable pll's power */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
++ writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
+ &anatop->usb1_pll_480_ctrl_set);
+ writel(0x80, &anatop->ana_misc2_clr);
+ /* wait for pll lock */
+ while ((readl(&anatop->usb1_pll_480_ctrl) &
- BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
++ BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
+ ;
+ /* disable bypass */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
++ writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
+ &anatop->usb1_pll_480_ctrl_clr);
+ /* enable pll output */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
++ writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
+ &anatop->usb1_pll_480_ctrl_set);
+ }
+}
+
+void enable_thermal_clk(void)
+{
+ enable_pll3();
}
+ void ipu_clk_enable(void)
+ {
+ u32 reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+ }
+
+ void ipu_clk_disable(void)
+ {
+ u32 reg = readl(&imx_ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+ }
+
+ void ipu_di_clk_enable(int di)
+ {
+ switch (di) {
+ case 0:
+ setbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
+ break;
+ case 1:
+ setbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
+ break;
+ default:
+ printf("%s: Invalid DI index %d\n", __func__, di);
+ }
+ }
+
+ void ipu_di_clk_disable(int di)
+ {
+ switch (di) {
+ case 0:
+ clrbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
+ break;
+ case 1:
+ clrbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
+ break;
+ default:
+ printf("%s: Invalid DI index %d\n", __func__, di);
+ }
+ }
+
+ void ldb_clk_enable(int ldb)
+ {
+ switch (ldb) {
+ case 0:
+ setbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_LDB_DI0_MASK);
+ break;
+ case 1:
+ setbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_LDB_DI1_MASK);
+ break;
+ default:
+ printf("%s: Invalid LDB index %d\n", __func__, ldb);
+ }
+ }
+
+ void ldb_clk_disable(int ldb)
+ {
+ switch (ldb) {
+ case 0:
+ clrbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_LDB_DI0_MASK);
+ break;
+ case 1:
+ clrbits_le32(&imx_ccm->CCGR3,
+ MXC_CCM_CCGR3_LDB_DI1_MASK);
+ break;
+ default:
+ printf("%s: Invalid LDB index %d\n", __func__, ldb);
+ }
+ }
+
+ void ocotp_clk_enable(void)
+ {
+ u32 reg = readl(&imx_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+ }
+
+ void ocotp_clk_disable(void)
+ {
+ u32 reg = readl(&imx_ccm->CCGR2);
+ reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+ }
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
return get_usdhc_clk(3);
case MXC_SATA_CLK:
return get_ahb_clk();
- break;
+ case MXC_NFC_CLK:
+ return get_nfc_clk();
+ default:
+ printf("Unsupported MXC CLK: %d\n", clk);
}
- return -1;
+ return 0;
}
+ static inline int gcd(int m, int n)
+ {
+ int t;
+ while (m > 0) {
+ if (n > m) {
+ t = m;
+ m = n;
+ n = t;
+ } /* swap */
+ m -= n;
+ }
+ return n;
+ }
+
+ /* Config CPU clock */
+ static int set_arm_clk(u32 ref, u32 freq_khz)
+ {
+ int d;
+ int div = 0;
+ int mul = 0;
+ u32 min_err = ~0;
+ u32 reg;
+
+ if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
+ printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
+ freq_khz / 1000, freq_khz % 1000,
+ 54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
+ 108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
+ return -EINVAL;
+ }
+
+ for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
+ int m = freq_khz * 2 * d / (ref / 1000);
+ u32 f;
+ u32 err;
+
+ if (m > 108) {
+ debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
+ d, m);
+ break;
+ }
+
+ f = ref * m / d / 2;
+ if (f > freq_khz * 1000) {
+ debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
+ d, m, f, freq_khz);
+ if (--m < 54)
+ return -EINVAL;
+ f = ref * m / d / 2;
+ }
+ err = freq_khz * 1000 - f;
+ debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
+ d, m, f, freq_khz, err);
+ if (err < min_err) {
+ mul = m;
+ div = d;
+ min_err = err;
+ if (err == 0)
+ break;
+ }
+ }
+ if (min_err == ~0)
+ return -EINVAL;
+ debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
+ mul, div, freq_khz / 1000, freq_khz % 1000,
+ ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
+
+ reg = readl(&anatop->pll_arm);
+ debug("anadig_pll_arm=%08x -> %08x\n",
+ reg, (reg & ~0x7f) | mul);
+
+ reg |= 1 << 16;
+ writel(reg, &anatop->pll_arm); /* bypass PLL */
+
+ reg = (reg & ~0x7f) | mul;
+ writel(reg, &anatop->pll_arm);
+
+ writel(div - 1, &imx_ccm->cacrr);
+
+ reg &= ~(1 << 16);
+ writel(reg, &anatop->pll_arm); /* disable PLL bypass */
+
+ return 0;
+ }
+
/*
- * Dump some core clockes.
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ * so the caller has to make sure those values are sensible.
+ * 2) Also adjust the NFC divider such that the NFC clock doesn't
+ * exceed NFC_CLK_MAX.
+ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ * 177MHz for higher voltage, this function fixes the max to 133MHz.
+ * 4) This function should not have allowed diag_printf() calls since
+ * the serial driver has been stoped. But leave then here to allow
+ * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
*/
- int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
- {
- u32 freq;
- freq = decode_pll(PLL_SYS, MXC_HCLK);
- printf("PLL_SYS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- printf("PLL_BUS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- printf("PLL_OTG %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_ENET, MXC_HCLK);
- printf("PLL_NET %8d MHz\n", freq / 1000000);
+ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+ {
+ int ret;
+
+ freq *= 1000;
+
+ switch (clk) {
+ case MXC_ARM_CLK:
+ ret = set_arm_clk(ref, freq);
+ break;
+
+ case MXC_NFC_CLK:
+ ret = set_nfc_clk(ref, freq);
+ break;
+
+ default:
+ printf("Warning: Unsupported or invalid clock type: %d\n",
+ clk);
+ return -EINVAL;
+ }
+
+ return ret;
+ }
+
+ /*
+ * Dump some core clocks.
+ */
+ #define print_pll(pll) { \
+ u32 __pll = decode_pll(pll, MXC_HCLK); \
+ printf("%-12s %4d.%03d MHz\n", #pll, \
+ __pll / 1000000, __pll / 1000 % 1000); \
+ }
+
+ #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
- print_pll(PLL_BUS);
+ #define print_clk(clk) { \
+ u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
+ printf("%-12s %4d.%03d MHz\n", #clk, \
+ __clk / 1000000, __clk / 1000 % 1000); \
+ }
+
+ #define print_pfd(pll, pfd) { \
+ u32 __pfd = readl(&anatop->pfd_##pll); \
+ if (__pfd & (0x80 << 8 * pfd)) { \
+ printf("PFD_%s[%d] OFF\n", #pll, pfd); \
+ } else { \
+ __pfd = (__pfd >> 8 * pfd) & 0x3f; \
+ printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
+ pll * 18 / __pfd, \
+ pll * 18 * 1000 / __pfd % 1000); \
+ } \
+ }
+
+ static void do_mx6_showclocks(void)
+ {
+ print_pll(PLL_ARM);
++ print_pll(PLL_528);
+ print_pll(PLL_USBOTG);
+ print_pll(PLL_AUDIO);
+ print_pll(PLL_VIDEO);
+ print_pll(PLL_ENET);
+ print_pll(PLL_USB2);
printf("\n");
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
- #ifdef CONFIG_MXC_SPI
- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
- #endif
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
- printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
- printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
- printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
- printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
- printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
- printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
- return 0;
+ print_pfd(480, 0);
+ print_pfd(480, 1);
+ print_pfd(480, 2);
+ print_pfd(480, 3);
+ print_pfd(528, 0);
+ print_pfd(528, 1);
+ print_pfd(528, 2);
+ printf("\n");
+
+ print_clk(IPG);
+ print_clk(UART);
+ print_clk(CSPI);
+ print_clk(AHB);
+ print_clk(AXI);
+ print_clk(DDR);
+ print_clk(ESDHC);
+ print_clk(ESDHC2);
+ print_clk(ESDHC3);
+ print_clk(ESDHC4);
+ print_clk(EMI_SLOW);
+ print_clk(NFC);
+ print_clk(IPG_PER);
+ print_clk(ARM);
+ }
+
+ static struct clk_lookup {
+ const char *name;
+ unsigned int index;
+ } mx6_clk_lookup[] = {
+ { "arm", MXC_ARM_CLK, },
+ { "nfc", MXC_NFC_CLK, },
+ };
+
+ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int i;
+ unsigned long freq;
+ unsigned long ref = ~0UL;
+
+ if (argc < 2) {
+ do_mx6_showclocks();
+ return CMD_RET_SUCCESS;
+ } else if (argc == 2 || argc > 4) {
+ return CMD_RET_USAGE;
+ }
+
+ freq = simple_strtoul(argv[2], NULL, 0);
+ if (freq == 0) {
+ printf("Invalid clock frequency %lu\n", freq);
+ return CMD_RET_FAILURE;
+ }
+ if (argc > 3) {
+ ref = simple_strtoul(argv[3], NULL, 0);
+ }
+ for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
+ if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
+ switch (mx6_clk_lookup[i].index) {
+ case MXC_ARM_CLK:
+ if (argc > 3)
+ return CMD_RET_USAGE;
- ref = CONFIG_SYS_MX6_HCLK;
++ ref = MXC_HCLK;
+ break;
+
+ case MXC_NFC_CLK:
+ if (argc > 3 && ref > 3) {
+ printf("Invalid clock selector value: %lu\n", ref);
+ return CMD_RET_FAILURE;
+ }
+ break;
+ }
+ printf("Setting %s clock to %lu MHz\n",
+ mx6_clk_lookup[i].name, freq);
+ if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
+ break;
+ freq = mxc_get_clock(mx6_clk_lookup[i].index);
+ printf("%s clock set to %lu.%03lu MHz\n",
+ mx6_clk_lookup[i].name,
+ freq / 1000000, freq / 1000 % 1000);
+ return CMD_RET_SUCCESS;
+ }
+ }
+ if (i == ARRAY_SIZE(mx6_clk_lookup)) {
+ printf("clock %s not found; supported clocks are:\n", argv[1]);
+ for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
+ printf("\t%s\n", mx6_clk_lookup[i].name);
+ }
+ } else {
+ printf("Failed to set clock %s to %s MHz\n",
+ argv[1], argv[2]);
+ }
+ return CMD_RET_FAILURE;
}
+#ifndef CONFIG_MX6SX
+void enable_ipu_clock(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+}
+#endif
/***************************************************/
U_BOOT_CMD(
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
-#ifdef CONFIG_VIDEO_IPUV3
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/bootm.h>
+#include <dm.h>
+#include <imx_thermal.h>
++#include <div64.h>
+ #include <ipu.h>
-#endif
+
+ DECLARE_GLOBAL_DATA_PTR;
+
++#define __data __attribute__((section(".data")))
++
+ #ifdef CONFIG_MX6_TEMPERATURE_MIN
+ #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
+ #else
+ #define TEMPERATURE_MIN (-40)
+ #endif
+ #ifdef CONFIG_MX6_TEMPERATURE_HOT
+ #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
+ #else
+ #define TEMPERATURE_HOT 80
+ #endif
+ #ifdef CONFIG_MX6_TEMPERATURE_MAX
+ #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
+ #else
+ #define TEMPERATURE_MAX 125
+ #endif
+ #define TEMP_AVG_COUNT 5
+ #define TEMP_WARN_THRESHOLD 5
-#define __data __attribute__((section(".data")))
+enum ldo_reg {
+ LDO_ARM,
+ LDO_SOC,
+ LDO_PU,
+};
struct scu_regs {
u32 ctrl;
else
val = (mv - 700) / 25;
+ clear_ldo_ramp();
+
+ switch (ldo) {
+ case LDO_SOC:
+ shift = 18;
+ break;
+ case LDO_PU:
+ shift = 9;
+ break;
+ case LDO_ARM:
+ shift = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ old = (reg & (0x1F << shift)) >> shift;
+ step = abs(val - old);
+ if (step == 0)
+ return 0;
+
+ reg = (reg & ~(0x1F << shift)) | (val << shift);
+ writel(reg, &anatop->reg_core);
+
/*
- * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
- * and set them to the calculated value (0.7V + val * 0.25V)
+ * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+ * step
*/
- reg = (reg & ~(0x1F << 18)) | (val << 18);
- writel(reg, &anatop->reg_core);
+ udelay(3 * step);
+
+ return 0;
}
+ static u32 __data thermal_calib;
+
+ #define FACTOR0 10000000
+ #define FACTOR1 15976
+ #define FACTOR2 4297157
+
+ int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
+ unsigned int hot_temp)
+ {
+ int temperature;
+
+ if (raw_hot != 0 && hot_temp != 0) {
+ unsigned int raw_n40c, ratio;
+
+ ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
+ raw_n40c = raw_25c + (13 * ratio) / 20;
+ if (raw <= raw_n40c)
+ temperature = (raw_n40c - raw) * 100 / ratio - 40;
+ else
+ temperature = TEMPERATURE_MIN;
+ } else {
+ u64 temp64 = FACTOR0;
+ unsigned int c1, c2;
+ /*
+ * Derived from linear interpolation:
+ * slope = 0.4297157 - (0.0015976 * 25C fuse)
+ * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
+ * (Nmeas - n1) / (Tmeas - t1) = slope
+ * We want to reduce this down to the minimum computation necessary
+ * for each temperature read. Also, we want Tmeas in millicelsius
+ * and we don't want to lose precision from integer division. So...
+ * Tmeas = (Nmeas - n1) / slope + t1
+ * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
+ * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
+ * Let constant c1 = (-1000 / slope)
+ * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
+ * Let constant c2 = n1 *c1 + 1000 * t1
+ * milli_Tmeas = c2 - Nmeas * c1
+ */
+ temp64 *= 1000;
+ do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
+ c1 = temp64;
+ c2 = raw_25c * c1 + 1000 * 25;
+ temperature = (c2 - raw * c1) / 1000;
+ }
+ return temperature;
+ }
+
+ int read_cpu_temperature(void)
+ {
+ unsigned int reg, tmp, i;
+ unsigned int raw_25c, raw_hot, hot_temp;
+ int temperature;
+ struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
+ struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
+
+ if (!thermal_calib) {
+ ocotp_clk_enable();
+ writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
+ thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
+ writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
+ ocotp_clk_disable();
+ }
+
+ if (thermal_calib == 0 || thermal_calib == 0xffffffff)
+ return TEMPERATURE_MIN;
+
+ /* Fuse data layout:
+ * [31:20] sensor value @ 25C
+ * [19:8] sensor value of hot
+ * [7:0] hot temperature value */
+ raw_25c = thermal_calib >> 20;
+ raw_hot = (thermal_calib & 0xfff00) >> 8;
+ hot_temp = thermal_calib & 0xff;
+
+ /* now we only using single measure, every time we measure
+ * the temperature, we will power on/off the anadig module
+ */
+ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+
+ /* write measure freq */
+ writel(327, &anatop->tempsense1);
+ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
+
+ /* average the temperature value over multiple readings */
+ for (i = 0; i < TEMP_AVG_COUNT; i++) {
+ static int failed;
+ int limit = 100;
+
+ while ((readl(&anatop->tempsense0) &
+ BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
+ udelay(10000);
+ if (--limit < 0)
+ break;
+ }
+ if ((readl(&anatop->tempsense0) &
+ BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
+ if (!failed) {
+ printf("Failed to read temp sensor\n");
+ failed = 1;
+ }
+ return 0;
+ }
+ failed = 0;
+ reg = (readl(&anatop->tempsense0) &
+ BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
+ BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
+ if (i == 0)
+ tmp = reg;
+ else
+ tmp = (tmp * i + reg) / (i + 1);
+ writel(BM_ANADIG_TEMPSENSE0_FINISHED,
+ &anatop->tempsense0_clr);
+ }
+
+ temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
+
+ /* power down anatop thermal sensor */
+ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
+
+ return temperature;
+ }
+
+ int check_cpu_temperature(int boot)
+ {
+ static int __data max_temp;
+ int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
+ int tmp = read_cpu_temperature();
+ bool first = true;
+
+ if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
+ printf("Temperature: can't get valid data!\n");
+ return tmp;
+ }
+
+ if (!boot) {
+ if (tmp > boot_limit) {
+ printf("CPU is %d C, too hot, resetting...\n", tmp);
+ udelay(100000);
+ reset_cpu(0);
+ }
+ if (tmp > max_temp) {
+ if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
+ printf("WARNING: CPU temperature %d C\n", tmp);
+ max_temp = tmp;
+ }
+ } else {
+ printf("Temperature: %d C, calibration data 0x%x\n",
+ tmp, thermal_calib);
+ while (tmp >= boot_limit) {
+ if (first) {
+ printf("CPU is %d C, too hot to boot, waiting...\n",
+ tmp);
+ first = false;
+ }
+ if (ctrlc())
+ break;
+ udelay(50000);
+ tmp = read_cpu_temperature();
+ if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
+ printf("WARNING: CPU temperature %d C\n", tmp);
+ max_temp = tmp;
+ }
+ }
+ return tmp;
+ }
+
static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
- #ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
+ #ifdef CONFIG_VIDEO_IPUV3
+ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
+ #endif
+ #ifdef CONFIG_APBH_DMA
+ /* Timer is required for Initializing APBH DMA */
+ timer_init();
mxs_dma_init();
#endif
+
+ return 0;
+}
+
+int board_postclk_init(void)
+{
+ set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
+
return 0;
}
-#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+#if defined CONFIG_MX6SL
+ /* Check whether LVE bit needs to be set */
+ if (pad_ctrl & PAD_CTL_LVE) {
+ pad_ctrl &= ~PAD_CTL_LVE;
+ pad_ctrl |= PAD_CTL_LVE_BIT;
+ }
+#endif
++#ifdef DEBUG
++ printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
++ i, pad, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
++ pad & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
++#endif
+
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
unsigned count)
{
iomux_v3_cfg_t const *p = pad_list;
+ int stride;
int i;
- for (i = 0; i < count; i++) {
-#ifdef DEBUG
- u32 mux_ctrl_ofs = (*p & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
- u32 mux_mode = (*p & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
- u32 sel_input_ofs =
- (*p & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
- u32 sel_input =
- (*p & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
- u32 pad_ctrl_ofs =
- (*p & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
- u32 pad_ctrl = (*p & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-
- printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
- i, *p, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
- *p & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
+#if defined(CONFIG_MX6QDL)
+ stride = 2;
+ if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ p += 1;
+#else
+ stride = 1;
#endif
- imx_iomux_v3_setup_pad(*p++);
+ for (i = 0; i < count; i++) {
+ imx_iomux_v3_setup_pad(*p);
+ p += stride;
}
}
- int num_bits, int value)
+
+void imx_iomux_set_gpr_register(int group, int start_bit,
- int i = 0;
- u32 reg;
- reg = readl(base + group * 4);
- while (num_bits) {
- reg &= ~(1<<(start_bit + i));
- i++;
- num_bits--;
- }
- reg |= (value << start_bit);
++ int num_bits, int value)
+{
++ u32 reg = readl(base + group * 4);
++
++ reg &= ~(((1 << num_bits) - 1) << start_bit);
++ reg |= value << start_bit;
+ writel(reg, base + group * 4);
+}
return tick;
}
+ static inline unsigned long time_to_tick(unsigned long time)
+ {
+ unsigned long long ticks = (unsigned long long)time;
+
+ ticks *= MXC_CLK32;
+ do_div(ticks, CONFIG_SYS_HZ);
+ return ticks;
+ }
+
static inline unsigned long long us_to_tick(unsigned long long usec)
{
- usec = usec * MXC_CLK32 + 999999;
+ ulong gpt_clk = gpt_get_clk();
+
+ usec = usec * gpt_clk + 999999;
do_div(usec, 1000000);
return usec;
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000 1000
+#define MPUPLL_M_800 800
+#define MPUPLL_M_720 720
+#define MPUPLL_M_600 600
+#define MPUPLL_M_550 550
+#define MPUPLL_M_300 300
+
/* MAIN PLL Fdll = 550 MHz, by default */
#ifndef CONFIG_SYS_MPUCLK
-#define CONFIG_SYS_MPUCLK 550
+#define CONFIG_SYS_MPUCLK MPUPLL_M_550
#endif
-extern void pll_init(void);
-extern void enable_emif_clocks(void);
+ #define DISPPLL_M 200
+ #define DISPPLL_N (OSC - 1)
+ #define DISPPLL_M2 1
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+#define CM_DLL_CTRL_NO_OVERRIDE 0x0
+#define CM_DLL_READYST 0x4
+
extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
#endif /* endif _CLOCKS_AM33XX_H_ */
#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
#define TCLR_AR BIT(1) /* Auto reload */
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
- #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
+ #define TCLR_PTV_SHIFT 2 /* Pre-scaler shift value */
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
+#define TCLR_CE BIT(6) /* compare mode enable */
+#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
+#define TCLR_TCM BIT(8) /* edge detection of input pin*/
+#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
+#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
+#define TCLR_CAPTMODE BIT(13) /* capture mode */
+#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
+#define TCFG_RESET BIT(0) /* software reset */
+#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
+#define TCFG_IDLEMOD_SHIFT (2) /* power management */
/* device type */
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
#define AM335X 0xB944
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK 0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300 0x1FEF
+#define AM335X_ZCZ_600 0x1FAF
+#define AM335X_ZCZ_720 0x1F2F
+#define AM335X_ZCZ_800 0x1E2F
+#define AM335X_ZCZ_1000 0x1C2F
+#define AM335X_ZCE_300 0x1FDF
+#define AM335X_ZCE_600 0x1F9F
/* This gives the status of the boot mode pins on the evm */
- #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
- | BIT(3) | BIT(4))
+ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2) | \
+ BIT(3) | BIT(4))
-/* Reset control */
-#ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
-#elif defined(CONFIG_TI814X)
-#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
-#endif
-#define PRM_RSTST (PRM_RSTCTRL + 8)
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
unsigned int resv1[16];
unsigned int statusreg; /* ofset 0x40 */
unsigned int resv2[51];
- unsigned int secure_emif_sdram_config; /* offset 0x0110 */
+ unsigned int emif_sdram_config; /* offset 0x0110 */
+ unsigned int resv3[319];
+ unsigned int dev_attr;
};
/* AM33XX GPIO registers */
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
+ unsigned int resv5[7];
+ unsigned int mreqprio_0; /* offset 0x70 */
+ unsigned int mreqprio_1; /* offset 0x74 */
+ unsigned int resv6[97];
+ unsigned int efuse_sma; /* offset 0x1FC */
+};
+
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+ u32 padding0[2];
+ u32 modena_init0_bw_fractional;
+ u32 modena_init0_bw_integer;
+ u32 modena_init0_watermark_0;
+};
+
+/* gmii_sel register defines */
+#define GMII1_SEL_MII 0x0
+#define GMII1_SEL_RMII 0x1
+#define GMII1_SEL_RGMII 0x2
+#define GMII2_SEL_MII 0x0
+#define GMII2_SEL_RMII 0x4
+#define GMII2_SEL_RGMII 0x8
+#define RGMII1_IDMODE BIT(4)
+#define RGMII2_IDMODE BIT(5)
+#define RMII1_IO_CLK_EN BIT(6)
+#define RMII2_IO_CLK_EN BIT(7)
+
+#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
+#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
+
+/* PWMSS */
+struct pwmss_regs {
+ unsigned int idver;
+ unsigned int sysconfig;
+ unsigned int clkconfig;
+ unsigned int clkstatus;
+};
+#define ECAP_CLK_EN BIT(0)
+#define ECAP_CLK_STOP_REQ BIT(1)
+
+struct pwmss_ecap_regs {
+ unsigned int tsctr;
+ unsigned int ctrphs;
+ unsigned int cap1;
+ unsigned int cap2;
+ unsigned int cap3;
+ unsigned int cap4;
+ unsigned int resv1[4];
+ unsigned short ecctl1;
+ unsigned short ecctl2;
};
-void init_timer(void);
+/* Capture Control register 2 */
+#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
+#define ECTRL2_MDSL_ECAP BIT(9)
+#define ECTRL2_CTRSTP_FREERUN BIT(4)
+#define ECTRL2_PLSL_LOW BIT(10)
+#define ECTRL2_SYNC_EN BIT(5)
-unsigned long lcdc_clk_rate(void);
+ #define clk_get_rate(c,p) \
+ __clk_get_rate(readl(&(c)->clkseldpll##p), \
+ readl(&(c)->divm2dpll##p))
+
+ unsigned long __clk_get_rate(u32 m_n, u32 div_m2);
+
+ unsigned long mpu_clk_rate(void);
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
- #define VTP_CTRL_START_EN (0x1)
+ #define VTP_CTRL_FILTER_SHIFT 1
+ #define VTP_CTRL_FILTER_MASK (0x7 << VTP_CTRL_FILTER_SHIFT)
+ #define VTP_CTRL_FILTER(n) (((n) << VTP_CTRL_FILTER_SHIFT) & VTP_CTRL_FILTER_MASK)
+ #define VTP_CTRL_START_EN (0x1 << 0)
+ #define PHY_DLL_LOCK_DIFF 0x0
+#ifdef CONFIG_AM43XX
+#define DDR_CKE_CTRL_NORMAL 0x3
+#else
#define DDR_CKE_CTRL_NORMAL 0x1
+#endif
#define PHY_EN_DYN_PWRDN (0x1 << 20)
/* Micron MT47H128M16RT-25E */
#define AM33XX_GPIO1_BASE 0x4804C000
#define AM33XX_GPIO2_BASE 0x481AC000
#define AM33XX_GPIO3_BASE 0x481AE000
+#define AM33XX_GPIO4_BASE 0x48320000
+#define AM33XX_GPIO5_BASE 0x48322000
+ #define AM33XX_GPIO_NR(bank, pin) (((bank) << 5) | (pin))
+
+/* GPIO CTRL register */
+#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
+#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
+#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
+
+/* GPIO OUTPUT ENABLE register */
+#define GPIO_OE_ENABLE(x) (1 << x)
+
+/* GPIO SETDATAOUT register */
+#define GPIO_SETDATAOUT(x) (1 << x)
#endif /* _GPIO_AM33xx_H */
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
- int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
+ int adjust_core_voltage(u32 freq);
void set_usb_phy_clk(void);
-void enable_usb_phy1_clk(unsigned char enable);
-void enable_usb_phy2_clk(unsigned char enable);
+void enable_usb_phy1_clk(bool enable);
+void enable_usb_phy2_clk(bool enable);
void set_usboh3_clk(void);
-void enable_usboh3_clk(unsigned char enable);
+void enable_usboh3_clk(bool enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_nfc_clk(unsigned char enable);
+void enable_efuse_prog_supply(bool enable);
+ void ipu_clk_enable(void);
+ void ipu_clk_disable(void);
+ void ipu_di_clk_enable(int di);
+ void ipu_di_clk_disable(int di);
+ #ifdef CONFIG_MX53
+ void ldb_clk_enable(int ldb);
+ void ldb_clk_disable(int ldb);
+ #else
+ static inline void ldb_clk_enable(int ldb)
+ {
+ }
+ static inline void ldb_clk_disable(int ldb)
+ {
+ }
+ #endif /* CONFIG_MX53 */
#endif /* __ASM_ARCH_CLOCK_H */
#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CCDR */
- #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+ #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21)
+/* Define the bits in register CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
+
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#define MXC_CCM_CCGR_CG_OFF 0x0
MXC_I2C_CLK,
};
+enum enet_freq {
+ ENET_25MHZ,
+ ENET_50MHZ,
+ ENET_100MHZ,
+ ENET_125MHZ,
+};
+ struct clk {
+ const char *name;
+ int id;
+ /* Source clock this clk depends on */
+ struct clk *parent;
+ /* Secondary clock to enable/disable with this clock */
+ struct clk *secondary;
+ /* Current clock rate */
+ unsigned long rate;
+ /* Reference count of clock enable/disable */
+ __s8 usecount;
+ /* Register bit position for clock's enable/disable control. */
+ u8 enable_shift;
+ /* Register address for clock's enable/disable control. */
+ void *enable_reg;
+ u32 flags;
+ /*
+ * Function ptr to recalculate the clock's rate based on parent
+ * clock's rate
+ */
+ void (*recalc) (struct clk *);
+ /*
+ * Function ptr to set the clock to a new rate. The rate must match a
+ * supported rate returned from round_rate. Leave blank if clock is not
+ * programmable
+ */
+ int (*set_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to round the requested clock rate to the nearest
+ * supported rate that is less than or equal to the requested rate.
+ */
+ unsigned long (*round_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to enable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ int (*enable) (struct clk *);
+ /*
+ * Function ptr to disable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ void (*disable) (struct clk *);
+ /* Function ptr to set the parent clock of the clock. */
+ int (*set_parent) (struct clk *, struct clk *);
+ };
+
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
+ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
+void setup_gpmi_io_clk(u32 cfg);
+void hab_caam_clock_enable(unsigned char enable);
void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
+void enable_uart_clk(unsigned char enable);
+int enable_cspi_clock(unsigned char enable, unsigned spi_num);
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
int enable_sata_clock(void);
+void disable_sata_clock(void);
+int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
-
+int enable_spi_clk(unsigned char enable, unsigned spi_num);
+void enable_ipu_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
+void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
+void enable_thermal_clk(void);
+ void ipu_clk_enable(void);
+ void ipu_clk_disable(void);
+ void ipu_di_clk_enable(int di);
+ void ipu_di_clk_disable(int di);
+ void ldb_clk_enable(int ldb);
+ void ldb_clk_disable(int ldb);
+ void ocotp_clk_enable(void);
+ void ocotp_clk_disable(void);
#endif /* __ASM_ARCH_CLOCK_H */
u32 CCGR6; /* 0x0080 */
u32 CCGR7;
u32 cmeor;
- u32 resv[0xfdd];
- u32 analog_pll_sys; /* 0x4000 */
- u32 analog_pll_sys_set;
- u32 analog_pll_sys_clr;
- u32 analog_pll_sys_tog;
- u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
- u32 analog_usb1_pll_480_ctrl_set;
- u32 analog_usb1_pll_480_ctrl_clr;
- u32 analog_usb1_pll_480_ctrl_tog;
- u32 analog_reserved0[4];
- u32 analog_pll_528; /* 0x4030 */
- u32 analog_pll_528_set;
- u32 analog_pll_528_clr;
- u32 analog_pll_528_tog;
- u32 analog_pll_528_ss; /* 0x4040 */
- u32 analog_reserved1[3];
- u32 analog_pll_528_num; /* 0x4050 */
- u32 analog_reserved2[3];
- u32 analog_pll_528_denom; /* 0x4060 */
- u32 analog_reserved3[3];
- u32 analog_pll_audio; /* 0x4070 */
- u32 analog_pll_audio_set;
- u32 analog_pll_audio_clr;
- u32 analog_pll_audio_tog;
- u32 analog_pll_audio_num; /* 0x4080*/
- u32 analog_reserved4[3];
- u32 analog_pll_audio_denom; /* 0x4090 */
- u32 analog_reserved5[3];
- u32 analog_pll_video; /* 0x40a0 */
- u32 analog_pll_video_set;
- u32 analog_pll_video_clr;
- u32 analog_pll_video_tog;
- u32 analog_pll_video_num; /* 0x40b0 */
- u32 analog_reserved6[3];
- u32 analog_pll_video_denom; /* 0x40c0 */
- u32 analog_reserved7[7];
- u32 analog_pll_enet; /* 0x40e0 */
- u32 analog_pll_enet_set;
- u32 analog_pll_enet_clr;
- u32 analog_pll_enet_tog;
- u32 analog_pfd_480; /* 0x40f0 */
- u32 analog_pfd_480_set;
- u32 analog_pfd_480_clr;
- u32 analog_pfd_480_tog;
- u32 analog_pfd_528; /* 0x4100 */
- u32 analog_pfd_528_set;
- u32 analog_pfd_528_clr;
- u32 analog_pfd_528_tog;
};
-
-struct anatop_regs {
- mxs_reg_32(pll_arm); /* 0x000 */
- mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */
- mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */
- mxs_reg_32(pll_528); /* 0x030 */
- reg_32(pll_528_ss); /* 0x040 */
- reg_32(pll_528_num); /* 0x050 */
- reg_32(pll_528_denom); /* 0x060 */
- mxs_reg_32(pll_audio); /* 0x070 */
- reg_32(pll_audio_num); /* 0x080 */
- reg_32(pll_audio_denom); /* 0x090 */
- mxs_reg_32(pll_video); /* 0x0a0 */
- reg_32(pll_video_num); /* 0x0b0 */
- reg_32(pll_video_denom); /* 0x0c0 */
- mxs_reg_32(pll_mlb); /* 0x0d0 */
- mxs_reg_32(pll_enet); /* 0x0e0 */
- mxs_reg_32(pfd_480); /* 0x0f0 */
- mxs_reg_32(pfd_528); /* 0x100 */
- mxs_reg_32(reg_1p1); /* 0x110 */
- mxs_reg_32(reg_3p0); /* 0x120 */
- mxs_reg_32(reg_2p5); /* 0x130 */
- mxs_reg_32(reg_core); /* 0x140 */
- mxs_reg_32(ana_misc0); /* 0x150 */
- mxs_reg_32(ana_misc1); /* 0x160 */
- mxs_reg_32(ana_misc2); /* 0x170 */
- mxs_reg_32(tempsense0); /* 0x180 */
- mxs_reg_32(tempsense1); /* 0x190 */
- mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */
- mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */
- mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
- mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
- mxs_reg_32(usb1_loopback); /* 0x1e0 */
- mxs_reg_32(usb1_misc); /* 0x1f0 */
- mxs_reg_32(usb2_vbus_detect); /* 0x200 */
- mxs_reg_32(usb2_chrg_detect); /* 0x210 */
- mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */
- mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */
- mxs_reg_32(usb2_loopback); /* 0x240 */
- mxs_reg_32(usb2_misc); /* 0x250 */
- reg_32(digprog); /* 0x260 */
- reg_32(rsrvd); /* 0x270 */
- reg_32(digprog_sololite); /* 0x280 */
-};
#endif
/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN (1 << 27)
- #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
+ #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
- #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
+ #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
#define MXC_CCM_CCR_COSC_EN (1 << 12)
-#define MXC_CCM_CCR_OSCNT_MASK (0xFF << MXC_CCM_CCR_OSCNT_OFFSET)
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CCR_OSCNT_MASK 0x7F
+#else
+#define MXC_CCM_CCR_OSCNT_MASK 0xFF
+#endif
#define MXC_CCM_CCR_OSCNT_OFFSET 0
/* Define the bits in register CCDR */
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
- #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
+#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
- #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
+#endif
+ #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
- #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+ #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
- #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+ #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
/* Define the bits in register CBCMR */
- #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
+ #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
- #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
+ #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
- #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
+ #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
- #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
+ #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
- #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
+ #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
- #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
+#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
- #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+ #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
- #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
+#endif
+ #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
+#ifndef CONFIG_MX6SX
#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
+#endif
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
- #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
+ #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
- #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
+ #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
+#ifndef CONFIG_MX6SX
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
+#endif
/* Define the bits in register CSCMR1 */
- #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
+ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
- #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
++#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
+#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
+#else
+ #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
- #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
+#endif
+ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
- #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
+/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
+ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
- #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
+ #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
- #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+ #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
- #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
+ #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
- #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
++#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
+#endif
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
++#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
+#endif
+ #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
+ #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
/* Define the bits in register CSCMR2 */
- #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
++#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
+#endif
+ #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
- #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
++#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
- #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
++#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
+#else
+ #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
+#endif
/* Define the bits in register CSCDR1 */
- #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
+#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
- #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
+#endif
+ #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
- #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
+ #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
- #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
+ #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
- #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
+ #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
+#ifndef CONFIG_MX6SX
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
- #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
- #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
+#endif
#ifdef CONFIG_MX6SL
- #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
- #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
+ #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
+ #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
#else
- #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
+ #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
++#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
+#endif
#endif
+ #define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */
- #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
+ #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
- #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
++#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
- #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
+ #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
- #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
+ #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
- #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+ #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
- #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
+ #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
/* Define the bits in register CS2CDR */
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
- #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
- #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
- #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
++#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
++#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
++#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
+#else
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
- #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
- #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
- #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
- #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
- #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
+ #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
+#endif
- #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
+ #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
- #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
+ #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
- #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+ #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
- #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
+ #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
/* Define the bits in register CDCDR */
- #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
+#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
--#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
++#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
++#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28
+#endif
- #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+ #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
- #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
+ #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
- #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
+ #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
- #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
+ #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
- #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
+ #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
- #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
+ #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
/* Define the bits in register CHSCCDR */
- #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
++#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
- #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
++#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
+#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
- #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
++#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
- #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
++#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
- #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
++#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
+#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
- #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
++#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
+#else
+ #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
- #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
+ #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
- #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
+ #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
- #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
- #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
- #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
+#endif
- #define CHSCCDR_CLK_SEL_LDB_DI0 3
- #define CHSCCDR_PODF_DIVIDE_BY_3 2
- #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
-
/* Define the bits in register CSCDR2 */
- #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
+ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
- #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
- #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
- #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
+/* All IPU2_DI1 are LCDIF1 on MX6SX */
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
- #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
- #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
- #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
+ #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
+/* All IPU2_DI0 are LCDIF2 on MX6SX */
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
+ #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
+ #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
/* Define the bits in register CSCDR3 */
- #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
+ #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
- #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
+ #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
- #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
+ #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
- #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
+ #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
/* Define the bits in register CDHIPR */
#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
+#endif
#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
+#ifndef CONFIG_MX6SX
#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
-#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
+#endif
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
- #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+ #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
#define MXC_CCM_CLPCR_VSTBY (1 << 8)
#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
#define MXC_CCM_CLPCR_SBYOS (1 << 6)
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
- #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#ifndef CONFIG_MX6SX
+ #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
- #define MXC_CCM_CLPCR_LPM_MASK 0x3
+#endif
+ #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
#define MXC_CCM_CLPCR_LPM_OFFSET 0
/* Define the bits in register CISR */
#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
-#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
- #define MXC_CCM_CIMR_MASK_LRF_PLL 1
+ #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
/* Define the bits in register CCOSR */
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
- #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+ #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
- #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+ #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
+#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
- #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+ #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
- #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
+ #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
- #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
+ #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK 3
#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CCGR5_SAI1_OFFSET 20
+#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
+#define MXC_CCM_CCGR5_SAI2_OFFSET 30
+#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
+#endif
- #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
- #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
- #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
- #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
- #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
- #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
- #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
- #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
- #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
- #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
- #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
- #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+ #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+ #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+ #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+ #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+ #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+ #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+ #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+ #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+ #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+ #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+ #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
+ #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
+ #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
+ #define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
+ #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
+ #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
+ #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
+ #define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
+ #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
+ #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
+ #define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
+ #define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
+ #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
+ #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
+ #define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
+ #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
+ #define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
+ #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
+
+ #define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
+ #define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
+ #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
+ #define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
+ #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
+ #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
+ #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3)
++#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2
++#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3
+ #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
+ #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
+ #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
+ #define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
+ #define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
+ #define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
+ #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
+ #define BP_ANADIG_PLL_ARM_DIV_SELECT 0
+ #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
-#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
++#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
+ BM_ANADIG_PLL_ARM_DIV_SELECT)
+
-#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
-#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
- BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(0)
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1)
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2)
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3)
-#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
-#define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
-#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
-#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
-#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
-#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
- (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
- BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
-#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
- (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
- BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
-
-#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31)
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16)
-#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \
- BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3)
-#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13)
-#define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9)
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7)
-#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
-#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
-#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \
- (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \
- BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
-#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \
- (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \
- BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
-
-#define BM_ANADIG_PLL_SYS_LOCK (1 << 31)
-#define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19)
-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18)
-#define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17)
-#define BM_ANADIG_PLL_SYS_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_SYS_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
-#define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
-#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT)
++#define BM_ANADIG_PLL_528_CTRL_LOCK (1 << 31)
++#define BM_ANADIG_PLL_528_PFD_OFFSET_EN (1 << 18)
++#define BM_ANADIG_PLL_528_DITHER_ENABLE (1 << 17)
++#define BM_ANADIG_PLL_528_CTRL_BYPASS (1 << 16)
++#define BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC 14
++#define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
++#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__XOR 0x3
++#define BM_ANADIG_PLL_528_CTRL_ENABLE (1 << 13)
++#define BM_ANADIG_PLL_528_CTRL_POWER (1 << 12)
++#define BM_ANADIG_PLL_528_CTRL_HOLD_RING_OFF (1 << 11)
++#define BM_ANADIG_PLL_528_CTRL_DOUBLE_CP (1 << 10)
++#define BM_ANADIG_PLL_528_CTRL_HALF_CP (1 << 9)
++#define BM_ANADIG_PLL_528_CTRL_DOUBLE_LF (1 << 8)
++#define BM_ANADIG_PLL_528_CTRL_HALF_LF (1 << 7)
++#define BM_ANADIG_PLL_528_CTRL_EN_USB_CLKS (1 << 6)
++#define BP_ANADIG_PLL_528_CTRL_CONTROL0 2
++#define BM_ANADIG_PLL_528_CTRL_CONTROL0 (0x7 << BP_ANADIG_PLL_528_CTRL_CONTROL0)
++#define BF_ANADIG_PLL_528_CTRL_CONTROL0(v) \
++ (((v) << BP_ANADIG_PLL_528_CTRL_CONTROL0) & \
++ BM_ANADIG_PLL_528_CTRL_CONTROL0)
++#define BP_ANADIG_PLL_528_CTRL_DIV_SELECT 0
++#define BM_ANADIG_PLL_528_CTRL_DIV_SELECT (0x3 << BP_ANADIG_PLL_528_CTRL_DIV_SELECT)
++#define BF_ANADIG_PLL_528_CTRL_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) & \
++ BM_ANADIG_PLL_528_CTRL_DIV_SELECT)
+
+ #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
+ #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
+ #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
+ #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+ #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+ #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
+ #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
+ #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
+ #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+ #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
++#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+ #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+ #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
+ #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
+ #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
+ #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
+ #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
+ #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
+ #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
+ #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+ #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
++#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
++ BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+ #define BP_ANADIG_PLL_AUDIO_NUM_A 0
-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A)
++#define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
++#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
++ BM_ANADIG_PLL_AUDIO_NUM_A)
+
+ #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B)
++#define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
++#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
++ BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+ #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
+ #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
+ #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
+ #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
++#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & \
++ BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+ #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
+ #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
+ #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
+ #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+ #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+ #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+ #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
+ #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
+ #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
+ #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
+ #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
+ #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
+ #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
+ #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+ #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
++#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
++ BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+ #define BP_ANADIG_PLL_VIDEO_NUM_A 0
+ #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
-#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A)
++#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
++ BM_ANADIG_PLL_VIDEO_NUM_A)
+
+ #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+ #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
- (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B)
++#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
++ BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+ #define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
+ #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
+ #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
++ (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
++ BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+ #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
+ #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
++ (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
++ BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+ #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
+ #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
++ (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
++ BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+ #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
+ #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
- (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
++#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
++ (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
++ BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+ #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
+ #define BP_ANADIG_PLL_MLB_PHASE_SEL 12
+ #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
-#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
- (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL)
++#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
++ (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
++ BM_ANADIG_PLL_MLB_PHASE_SEL)
+ #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
+
+ #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
+ #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
+ #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
+ #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
+ #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
+ #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
+ #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+ #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+ #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+ #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
+ #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
+ #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
+ #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
+ #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
+ #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
+ #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
+ #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+ #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT)
++#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
++ BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+ #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
+ #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
+ #define BP_ANADIG_PFD_480_PFD3_FRAC 24
+ #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
+ #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
- (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC)
++ (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
++ BM_ANADIG_PFD_480_PFD3_FRAC)
+
+ #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
+ #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
-#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
- (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
++#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
++ (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
++ BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+ #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
+ #define BP_ANADIG_ANA_MISC0_ANAMUX 21
+ #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
-#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
- (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & BM_ANADIG_ANA_MISC0_ANAMUX)
++#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
++ (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
++ BM_ANADIG_ANA_MISC0_ANAMUX)
+ #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
+ #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
+ #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+ #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
- (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
++ (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
++ BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+ #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
-#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
-#define BP_ANADIG_ANA_MISC0_OSC_I 14
-#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
-#define BF_ANADIG_ANA_MISC0_OSC_I(v) \
- (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & BM_ANADIG_ANA_MISC0_OSC_I)
++#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
++#define BP_ANADIG_ANA_MISC0_OSC_I 14
++#define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
++#define BF_ANADIG_ANA_MISC0_OSC_I(v) \
++ (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
++ BM_ANADIG_ANA_MISC0_OSC_I)
+ #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
-#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
++#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
+ #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
-#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
++#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+ #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
- (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
-#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
++ (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
++ BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
++#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
+ #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
+ #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
-#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
- (((v) << BM_ANADIG_ANA_MISC0_REFTOP_VBGUP) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
-#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
-#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
-#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
++#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
++ (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
++ BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
++#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
++#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
++#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
+ #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
+
-#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
-#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
-#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
++#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
++#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
++#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29)
+ #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
-#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
-#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
-#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
++#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
++#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
++#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
+ #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
-#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
-#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
- (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
++#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
++#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
++ (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
++ BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+ #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
-#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
-#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
- (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
-
-#define BP_ANADIG_ANA_MISC2_CONTROL3 30
-#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
-#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
- (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & BM_ANADIG_ANA_MISC2_CONTROL3)
++#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
++#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
++ (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
++ BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
++
++#define BP_ANADIG_ANA_MISC2_CONTROL3 30
++#define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
++#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
++ (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
++ BM_ANADIG_ANA_MISC2_CONTROL3)
+ #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
-#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
-#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
- (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
++#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
++#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
++ (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
++ BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+ #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
-#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
-#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
- (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
++#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
++#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
++ (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
++ BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+ #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
-#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
-#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
- (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
-#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
-#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
-#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
++#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
++#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
++ (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
++ BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
++#define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23)
++#define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22)
++#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
+ #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
+ #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
-#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
-#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
- (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
-#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
-#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
++#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
++#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
++ (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
++ BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
++#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
++#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
+ #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
-#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
++#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
+ #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
-#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
-#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
- (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
++#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
++#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
++ (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
++ BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
+ #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
+ #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
+ #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
+ #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
+ #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
+ #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
-#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
- (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
-
-#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
-#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
-#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
- (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
-#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
-#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
-#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
- (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
-#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
-#define BP_ANADIG_TEMPSENSE0_VBGADJ 3
-#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
++#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
++ (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
++ BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
++
++#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
++#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
++#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
++ (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
++ BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
++#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
++#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
++#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
++ (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
++ BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
++#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
++#define BP_ANADIG_TEMPSENSE0_VBGADJ 3
++#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
+ #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
- (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & BM_ANADIG_TEMPSENSE0_VBGADJ)
-#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
-#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
-#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
-
-#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
-#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
-#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
- (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
-
-#ifdef CONFIG_MX6Q
-#define PLL2_PFD0_FREQ 352000000
-#define PLL2_PFD1_FREQ 594000000
++ (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
++ BM_ANADIG_TEMPSENSE0_VBGADJ)
++#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
++#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
++#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
++
++#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
++#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
++#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
++ (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
++ BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
++
++#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
++#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
++#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
++#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
++#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
++#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
++#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
++#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
++#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
++#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
++#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
++#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#ifdef CONFIG_MX6SX
- #define MXC_CCM_CCGR6_PWM8_OFFSET 16
- #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
- #define MXC_CCM_CCGR6_VADC_OFFSET 20
- #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
- #define MXC_CCM_CCGR6_GIS_OFFSET 22
- #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
- #define MXC_CCM_CCGR6_I2C4_OFFSET 24
- #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
- #define MXC_CCM_CCGR6_PWM5_OFFSET 26
- #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
- #define MXC_CCM_CCGR6_PWM6_OFFSET 28
- #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
- #define MXC_CCM_CCGR6_PWM7_OFFSET 30
- #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
++#define MXC_CCM_CCGR6_PWM8_OFFSET 16
++#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
++#define MXC_CCM_CCGR6_VADC_OFFSET 20
++#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
++#define MXC_CCM_CCGR6_GIS_OFFSET 22
++#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
++#define MXC_CCM_CCGR6_I2C4_OFFSET 24
++#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
++#define MXC_CCM_CCGR6_PWM5_OFFSET 26
++#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
++#define MXC_CCM_CCGR6_PWM6_OFFSET 28
++#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
++#define MXC_CCM_CCGR6_PWM7_OFFSET 30
++#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
#else
- #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
- #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
-#define PLL2_PFD0_FREQ 306580000
-#define PLL2_PFD1_FREQ 528000000
-#endif
-#define PLL2_PFD2_FREQ 396000000
-#define PLL2_PFD2_DIV_FREQ (PLL2_PFD2_FREQ / 2)
-#define PLL3_PFD0_FREQ 720000000
-#define PLL3_PFD1_FREQ 540000000
-#define PLL3_PFD2_FREQ 508200000
-#define PLL3_PFD3_FREQ 454700000
-#define PLL3_80M 80000000
-#define PLL3_60M 60000000
++#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
++#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#endif
+
- #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
- #define BP_ANADIG_PLL_SYS_RSVD0 20
- #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
- #define BF_ANADIG_PLL_SYS_RSVD0(v) \
- (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
- #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
- #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
- #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
- #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
- #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
- #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
- #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
- #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
- #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
- #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
- #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
- #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
- #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
- #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
- #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
- #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
- #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
- #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
- #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
- #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
- #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
-
- #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
- #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
- #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
- #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
- (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
- #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
- #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
- #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
- #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
- #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
- #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
- #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
- #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
- #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
- #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
- #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
- #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
- #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
- #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
- #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
- #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
- #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
- #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
- #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
- #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
- (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
- #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
- #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
- #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
-
- #define BM_ANADIG_PLL_528_LOCK 0x80000000
- #define BP_ANADIG_PLL_528_RSVD1 19
- #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
- #define BF_ANADIG_PLL_528_RSVD1(v) \
- (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
- #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
- #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
- #define BM_ANADIG_PLL_528_BYPASS 0x00010000
- #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
- #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
- #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
- #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
- #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
- #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
- #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
- #define BM_ANADIG_PLL_528_ENABLE 0x00002000
- #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
- #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
- #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
- #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
- #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
- #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
- #define BP_ANADIG_PLL_528_RSVD0 1
- #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
- #define BF_ANADIG_PLL_528_RSVD0(v) \
- (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
- #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
-
- #define BP_ANADIG_PLL_528_SS_STOP 16
- #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
- #define BF_ANADIG_PLL_528_SS_STOP(v) \
- (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
- #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
- #define BP_ANADIG_PLL_528_SS_STEP 0
- #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
- #define BF_ANADIG_PLL_528_SS_STEP(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
-
- #define BP_ANADIG_PLL_528_NUM_RSVD0 30
- #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
- #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
- #define BP_ANADIG_PLL_528_NUM_A 0
- #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
- #define BF_ANADIG_PLL_528_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
-
- #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
- #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
- #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
- #define BP_ANADIG_PLL_528_DENOM_B 0
- #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
- #define BF_ANADIG_PLL_528_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
-
- #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
- #define BP_ANADIG_PLL_AUDIO_RSVD0 22
- #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
- #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
- (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
- #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
- #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
- #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
- #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
- #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
- #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
- #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
- #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
- #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
- #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
- #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
- #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
- #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
- #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
- #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
- #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
- #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
- #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
- #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
- #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
- #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
- #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
- #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
- #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
-
- #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
- #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
- #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
- #define BP_ANADIG_PLL_AUDIO_NUM_A 0
- #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
- #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
-
- #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
- #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
- #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
- #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
- #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
- #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
-
- #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
- #define BP_ANADIG_PLL_VIDEO_RSVD0 22
- #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
- #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
- (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
- #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
- #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
- #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
- #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
- #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
- #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
- #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
- #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
- #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
- #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
- #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
- #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
- #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
- #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
- #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
- #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
- #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
- #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
- #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
- #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
- #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
- #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
- #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
- #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
-
- #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
- #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
- #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
- #define BP_ANADIG_PLL_VIDEO_NUM_A 0
- #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
- #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
-
- #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
- #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
- #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
- #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
- #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
- #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
-
- #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
- #define BP_ANADIG_PLL_ENET_RSVD1 21
- #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
- #define BF_ANADIG_PLL_ENET_RSVD1(v) \
- (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
- #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
- #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
- #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
- #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
- #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
- #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
- #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
- #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
- #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
- #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
- #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
- #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
- #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
- #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
- #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
- #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
- #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
- #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
- #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
- #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
- #define BP_ANADIG_PLL_ENET_RSVD0 2
- #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
- #define BF_ANADIG_PLL_ENET_RSVD0(v) \
- (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
- #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
- #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
- #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
-
- #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
- #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
- #define BP_ANADIG_PFD_480_PFD3_FRAC 24
- #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
- #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
- (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
- #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
- #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
- #define BP_ANADIG_PFD_480_PFD2_FRAC 16
- #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
- #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
- (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
- #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
- #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
- #define BP_ANADIG_PFD_480_PFD1_FRAC 8
- #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
- #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
- (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
- #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
- #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
- #define BP_ANADIG_PFD_480_PFD0_FRAC 0
- #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
- #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
- (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
-
- #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
- #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
- #define BP_ANADIG_PFD_528_PFD3_FRAC 24
- #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
- #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
- (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
- #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
- #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
- #define BP_ANADIG_PFD_528_PFD2_FRAC 16
- #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
- #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
- (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
- #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
- #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
- #define BP_ANADIG_PFD_528_PFD1_FRAC 8
- #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
- #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
- (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
- #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
- #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
- #define BP_ANADIG_PFD_528_PFD0_FRAC 0
- #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
- #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
- (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
++#define BM_ANADIG_USB_PLL_480_CTRL_LOCK (1 << 31)
++#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS (1 << 16)
++#define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC 14
++#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
++#define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \
++ BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
++#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
++#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
++#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
++#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
++#define BM_ANADIG_USB_PLL_480_CTRL_ENABLE (1 << 13)
++#define BM_ANADIG_USB_PLL_480_CTRL_POWER (1 << 12)
++#define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
++#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP (1 << 10)
++#define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP (1 << 9)
++#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF (1 << 8)
++#define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF (1 << 7)
++#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
++#define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0 2
++#define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
++#define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v) \
++ (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
++ BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
++#define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT 0
++#define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
++#define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
++ BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
++
++#define BM_ANADIG_PLL_528_LOCK (1 << 31)
++#define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
++#define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
++#define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
++#define BM_ANADIG_PLL_528_BYPASS (1 << 16)
++#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
++#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
++#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
++#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
++#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
++#define BM_ANADIG_PLL_528_ENABLE (1 << 13)
++#define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
++#define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
++#define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
++#define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
++#define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
++#define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
++#define BP_ANADIG_PLL_528_DIV_SELECT 0
++#define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
++#define BF_ANADIG_PLL_528_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
++ BM_ANADIG_PLL_528_DIV_SELECT)
++
++#define BP_ANADIG_PLL_528_SS_STOP 16
++#define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
++#define BF_ANADIG_PLL_528_SS_STOP(v) \
++ (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
++ BM_ANADIG_PLL_528_SS_STOP)
++#define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
++#define BP_ANADIG_PLL_528_SS_STEP 0
++#define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
++#define BF_ANADIG_PLL_528_SS_STEP(v) \
++ (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
++ BM_ANADIG_PLL_528_SS_STEP)
++
++#define BP_ANADIG_PLL_528_NUM_A 0
++#define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
++#define BF_ANADIG_PLL_528_NUM_A(v) \
++ (((v) << BP_ANADIG_PLL_528_NUM_A) & \
++ BM_ANADIG_PLL_528_NUM_A)
++
++#define BP_ANADIG_PLL_528_DENOM_B 0
++#define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
++#define BF_ANADIG_PLL_528_DENOM_B(v) \
++ (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
++ BM_ANADIG_PLL_528_DENOM_B)
++
++#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
++#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
++#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
++#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
++#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
++ BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
++#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
++#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
++#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
++#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
++#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
++#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
++#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
++#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
++#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
++#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
++#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
++#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
++#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
++#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
++#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
++#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
++#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
++#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
++ BM_ANADIG_PLL_AUDIO_DIV_SELECT)
++
++#define BP_ANADIG_PLL_AUDIO_NUM_A 0
++#define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
++#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
++ BM_ANADIG_PLL_AUDIO_NUM_A)
++
++#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
++#define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
++#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
++ (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
++ BM_ANADIG_PLL_AUDIO_DENOM_B)
++
++#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
++#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
++#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
++#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
++#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
++ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
++#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
++#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
++#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
++#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
++#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
++#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
++#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
++#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
++#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
++#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
++#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
++#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
++#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
++#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
++#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
++#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
++#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
++#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
++ BM_ANADIG_PLL_VIDEO_DIV_SELECT)
++
++#define BP_ANADIG_PLL_VIDEO_NUM_A 0
++#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
++#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
++ BM_ANADIG_PLL_VIDEO_NUM_A)
++
++#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
++#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
++#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
++ (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
++ BM_ANADIG_PLL_VIDEO_DENOM_B)
++
++#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
++#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
++#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
++#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
++#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
++#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
++#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
++#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
++#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
++#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
++ (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
++ BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
++#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
++#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
++#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
++#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
++#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
++#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
++#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
++#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
++#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
++#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
++#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
++#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
++#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
++#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
++ (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
++ BM_ANADIG_PLL_ENET_DIV_SELECT)
++
++#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
++#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
++#define BP_ANADIG_PFD_480_PFD3_FRAC 24
++#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
++#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
++ BM_ANADIG_PFD_480_PFD3_FRAC)
++#define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23)
++#define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22)
++#define BP_ANADIG_PFD_480_PFD2_FRAC 16
++#define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
++#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
++ BM_ANADIG_PFD_480_PFD2_FRAC)
++#define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
++#define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
++#define BP_ANADIG_PFD_480_PFD1_FRAC 8
++#define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
++#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
++ BM_ANADIG_PFD_480_PFD1_FRAC)
++#define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
++#define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
++#define BP_ANADIG_PFD_480_PFD0_FRAC 0
++#define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
++#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
++ BM_ANADIG_PFD_480_PFD0_FRAC)
++
++#define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
++#define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30)
++#define BP_ANADIG_PFD_528_PFD3_FRAC 24
++#define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
++#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
++ BM_ANADIG_PFD_528_PFD3_FRAC)
++#define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23)
++#define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22)
++#define BP_ANADIG_PFD_528_PFD2_FRAC 16
++#define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
++#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
++ BM_ANADIG_PFD_528_PFD2_FRAC)
++#define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
++#define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
++#define BP_ANADIG_PFD_528_PFD1_FRAC 8
++#define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
++#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
++ BM_ANADIG_PFD_528_PFD1_FRAC)
++#define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
++#define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
++#define BP_ANADIG_PFD_528_PFD0_FRAC 0
++#define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
++#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
++ (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
++ BM_ANADIG_PFD_528_PFD0_FRAC)
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
#define __ASM_ARCH_MX6_IMX_REGS_H__
+ #include <asm/imx-common/regs-common.h>
+
#define ARCH_MXC
- #define CONFIG_SYS_CACHELINE_SIZE 32
++#define CONFIG_SYS_CACHELINE_SIZE 64
+
- #define ROMCP_ARB_BASE_ADDR 0x00000000
- #define ROMCP_ARB_END_ADDR 0x000FFFFF
+ #define ROMCP_ARB_BASE_ADDR 0x00000000
+ #define ROMCP_ARB_END_ADDR 0x000FFFFF
#ifdef CONFIG_MX6SL
- #define GPU_2D_ARB_BASE_ADDR 0x02200000
- #define GPU_2D_ARB_END_ADDR 0x02203FFF
- #define OPENVG_ARB_BASE_ADDR 0x02204000
- #define OPENVG_ARB_END_ADDR 0x02207FFF
- #elif CONFIG_MX6SX
- #define CAAM_ARB_BASE_ADDR 0x00100000
- #define CAAM_ARB_END_ADDR 0x00107FFF
- #define GPU_ARB_BASE_ADDR 0x01800000
- #define GPU_ARB_END_ADDR 0x01803FFF
- #define APBH_DMA_ARB_BASE_ADDR 0x01804000
- #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
- #define M4_BOOTROM_BASE_ADDR 0x007F8000
+ #define GPU_2D_ARB_BASE_ADDR 0x02200000
+ #define GPU_2D_ARB_END_ADDR 0x02203FFF
+ #define OPENVG_ARB_BASE_ADDR 0x02204000
+ #define OPENVG_ARB_END_ADDR 0x02207FFF
++#elif defined(CONFIG_MX6SX)
++#define CAAM_ARB_BASE_ADDR 0x00100000
++#define CAAM_ARB_END_ADDR 0x00107FFF
++#define GPU_ARB_BASE_ADDR 0x01800000
++#define GPU_ARB_END_ADDR 0x01803FFF
++#define APBH_DMA_ARB_BASE_ADDR 0x01804000
++#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
++#define M4_BOOTROM_BASE_ADDR 0x007F8000
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
#else
- #define CAAM_ARB_BASE_ADDR 0x00100000
- #define CAAM_ARB_END_ADDR 0x00103FFF
- #define APBH_DMA_ARB_BASE_ADDR 0x00110000
- #define APBH_DMA_ARB_END_ADDR 0x00117FFF
- #define HDMI_ARB_BASE_ADDR 0x00120000
- #define HDMI_ARB_END_ADDR 0x00128FFF
- #define GPU_3D_ARB_BASE_ADDR 0x00130000
- #define GPU_3D_ARB_END_ADDR 0x00133FFF
- #define GPU_2D_ARB_BASE_ADDR 0x00134000
- #define GPU_2D_ARB_END_ADDR 0x00137FFF
- #define DTCP_ARB_BASE_ADDR 0x00138000
- #define DTCP_ARB_END_ADDR 0x0013BFFF
+ #define CAAM_ARB_BASE_ADDR 0x00100000
+ #define CAAM_ARB_END_ADDR 0x00103FFF
+ #define APBH_DMA_ARB_BASE_ADDR 0x00110000
+ #define APBH_DMA_ARB_END_ADDR 0x00117FFF
+ #define HDMI_ARB_BASE_ADDR 0x00120000
+ #define HDMI_ARB_END_ADDR 0x00128FFF
+ #define GPU_3D_ARB_BASE_ADDR 0x00130000
+ #define GPU_3D_ARB_END_ADDR 0x00133FFF
+ #define GPU_2D_ARB_BASE_ADDR 0x00134000
+ #define GPU_2D_ARB_END_ADDR 0x00137FFF
+ #define DTCP_ARB_BASE_ADDR 0x00138000
+ #define DTCP_ARB_END_ADDR 0x0013BFFF
#endif /* CONFIG_MX6SL */
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
-#ifdef CONFIG_MX6SL
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- #define GPV2_BASE_ADDR 0x00D00000
+ #define GPV2_BASE_ADDR 0x00D00000
#else
#define GPV2_BASE_ADDR 0x00200000
#endif
- #define PCIE_ARB_BASE_ADDR 0x08000000
- #define PCIE_ARB_END_ADDR 0x08FFFFFF
+#ifdef CONFIG_MX6SX
+#define GPV3_BASE_ADDR 0x00E00000
+#define GPV4_BASE_ADDR 0x00F00000
+#define GPV5_BASE_ADDR 0x01000000
+#define GPV6_BASE_ADDR 0x01100000
++#define PCIE_ARB_BASE_ADDR 0x08000000
++#define PCIE_ARB_END_ADDR 0x08FFFFFF
+
+#else
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
- #define PCIE_ARB_BASE_ADDR 0x01000000
- #define PCIE_ARB_END_ADDR 0x01FFFFFF
++#define PCIE_ARB_BASE_ADDR 0x01000000
++#define PCIE_ARB_END_ADDR 0x01FFFFFF
+#endif
+
#define IRAM_BASE_ADDR 0x00900000
- #define SCU_BASE_ADDR 0x00A00000
- #define IC_INTERFACES_BASE_ADDR 0x00A00100
- #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
- #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
- #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+ #define SCU_BASE_ADDR 0x00A00000
+ #define IC_INTERFACES_BASE_ADDR 0x00A00100
+ #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
+ #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
+ #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+#define L2_PL310_BASE 0x00A02000
- #define GPV0_BASE_ADDR 0x00B00000
- #define GPV1_BASE_ADDR 0x00C00000
+ #define GPV0_BASE_ADDR 0x00B00000
+ #define GPV1_BASE_ADDR 0x00C00000
-#define PCIE_ARB_BASE_ADDR 0x01000000
-#define PCIE_ARB_END_ADDR 0x01FFFFFF
- #define AIPS1_ARB_BASE_ADDR 0x02000000
- #define AIPS1_ARB_END_ADDR 0x020FFFFF
- #define AIPS2_ARB_BASE_ADDR 0x02100000
- #define AIPS2_ARB_END_ADDR 0x021FFFFF
+ #define AIPS1_ARB_BASE_ADDR 0x02000000
+ #define AIPS1_ARB_END_ADDR 0x020FFFFF
+ #define AIPS2_ARB_BASE_ADDR 0x02100000
+ #define AIPS2_ARB_END_ADDR 0x021FFFFF
+#ifdef CONFIG_MX6SX
+#define AIPS3_BASE_ADDR 0x02200000
+#define AIPS3_END_ADDR 0x022FFFFF
- #define WEIM_ARB_BASE_ADDR 0x50000000
- #define WEIM_ARB_END_ADDR 0x57FFFFFF
- #define QSPI0_AMBA_BASE 0x60000000
- #define QSPI0_AMBA_END 0x6FFFFFFF
- #define QSPI1_AMBA_BASE 0x70000000
- #define QSPI1_AMBA_END 0x7FFFFFFF
++#define WEIM_ARB_BASE_ADDR 0x50000000
++#define WEIM_ARB_END_ADDR 0x57FFFFFF
++#define QSPI0_AMBA_BASE 0x60000000
++#define QSPI0_AMBA_END 0x6FFFFFFF
++#define QSPI1_AMBA_BASE 0x70000000
++#define QSPI1_AMBA_END 0x7FFFFFFF
+#else
- #define SATA_ARB_BASE_ADDR 0x02200000
- #define SATA_ARB_END_ADDR 0x02203FFF
- #define OPENVG_ARB_BASE_ADDR 0x02204000
- #define OPENVG_ARB_END_ADDR 0x02207FFF
- #define HSI_ARB_BASE_ADDR 0x02208000
- #define HSI_ARB_END_ADDR 0x0220BFFF
- #define IPU1_ARB_BASE_ADDR 0x02400000
- #define IPU1_ARB_END_ADDR 0x027FFFFF
- #define IPU2_ARB_BASE_ADDR 0x02800000
- #define IPU2_ARB_END_ADDR 0x02BFFFFF
- #define WEIM_ARB_BASE_ADDR 0x08000000
- #define WEIM_ARB_END_ADDR 0x0FFFFFFF
+ #define SATA_ARB_BASE_ADDR 0x02200000
+ #define SATA_ARB_END_ADDR 0x02203FFF
+ #define OPENVG_ARB_BASE_ADDR 0x02204000
+ #define OPENVG_ARB_END_ADDR 0x02207FFF
+ #define HSI_ARB_BASE_ADDR 0x02208000
+ #define HSI_ARB_END_ADDR 0x0220BFFF
+ #define IPU1_ARB_BASE_ADDR 0x02400000
+ #define IPU1_ARB_END_ADDR 0x027FFFFF
+ #define IPU2_ARB_BASE_ADDR 0x02800000
+ #define IPU2_ARB_END_ADDR 0x02BFFFFF
+ #define WEIM_ARB_BASE_ADDR 0x08000000
+ #define WEIM_ARB_END_ADDR 0x0FFFFFFF
+#endif
-#ifdef CONFIG_MX6SL
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- #define MMDC0_ARB_BASE_ADDR 0x80000000
- #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
- #define MMDC1_ARB_BASE_ADDR 0xC0000000
- #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+ #define MMDC0_ARB_BASE_ADDR 0x80000000
+ #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
+ #define MMDC1_ARB_BASE_ADDR 0xC0000000
+ #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
#else
- #define MMDC0_ARB_BASE_ADDR 0x10000000
- #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
- #define MMDC1_ARB_BASE_ADDR 0x80000000
- #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+ #define MMDC0_ARB_BASE_ADDR 0x10000000
+ #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
+ #define MMDC1_ARB_BASE_ADDR 0x80000000
+ #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
#endif
+#ifndef CONFIG_MX6SX
#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
#define IPU_SOC_OFFSET 0x00200000
+#endif
/* Defines for Blocks connected via AIPS (SkyBlue) */
- #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
- #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
- #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
- #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
-
- #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
- #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
- #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
- #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
- #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
+ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
+ #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+ #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
+ #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+
+ #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
+ #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
+ #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
+ #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
+ #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
#ifdef CONFIG_MX6SL
- #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
- #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
- #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
- #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
- #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
- #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
- #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
- #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+ #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+ #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
+ #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+ #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+ #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+ #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+ #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+ #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
#else
- #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#ifndef CONFIG_MX6SX
- #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
- #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
- #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
- #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
- #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
- #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+ #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#endif
+ #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
+ #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+ #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+ #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+ #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+ #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#endif
- #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
- #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
+#ifndef CONFIG_MX6SX
- #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
-
- #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
- #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
- #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
- #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
- #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
- #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
- #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
- #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
- #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
- #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
- #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
- #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
- #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
- #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
- #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
- #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
- #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
- #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
- #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
- #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
- #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
- #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
- #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
- #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
- #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
- #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
- #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
- #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
+ #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
+ #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
+#endif
+ #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
+
+ #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
+ #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
+ #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
+ #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
+ #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
+ #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
+ #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
+ #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
+ #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
+ #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
+ #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
+ #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
+ #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
+ #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
+ #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
+ #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
+ #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
+ #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
+ #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
+ #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
+ #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
+ #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
+ #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
+ #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
+ #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
+ #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
+ #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
+ #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
#ifdef CONFIG_MX6SL
- #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
- #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+ #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+ #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
- #elif CONFIG_MX6SX
++#elif defined(CONFIG_MX6SX)
+#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
#else
- #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
- #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+ #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+ #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#endif
- #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
- #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
- #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
+ #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
+ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+ #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
- #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
- #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
-#ifdef CONFIG_MX6SL
-#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
-#else
-#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
-#endif
++#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
++#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
- #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
+ #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
#ifdef CONFIG_MX6SL
- #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+ #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
#else
- #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+ #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
#endif
- #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
- #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
- #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
- #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
- #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
- #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
- #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
- #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
- #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
+ #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
+ #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
+ #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
+ #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
+ #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
+ #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
+ #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
+ #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
+ #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
#ifdef CONFIG_MX6SL
- #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
- #elif CONFIG_MX6SX
- #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+ #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
++#elif defined(CONFIG_MX6SX)
++#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#else
- #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+ #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#endif
- #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
- #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
- #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
+ #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
+ #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
+ #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#ifdef CONFIG_MX6SX
+#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#else
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
- #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
+#endif
- #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+ #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
+#ifdef CONFIG_MX6SX
- #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
++#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+#else
- #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
- #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
+ #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+#endif
- #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
- #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
- #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+ #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
+#ifdef CONFIG_MX6SX
- #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
- #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
- #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
++#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
++#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
++#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#else
- #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
- #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
- #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
- #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
+ #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
+ #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+ #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#endif
+ #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
+ #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
+ #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
+ #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
- #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
- #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
- #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
- #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
- #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
- #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
- #define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
- #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
- #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
- #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
- #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
- #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
- #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
- #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
- #define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
- #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
- #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
- #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
- #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
- #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
- #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
- #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
- #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
- #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
- #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#ifdef CONFIG_MX6SX
- #define CHIP_REV_1_0 0x10
- #define CHIP_REV_1_2 0x12
- #define CHIP_REV_1_5 0x15
++#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
++#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
++#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
++#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
++#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
++#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
++#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
++#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
++#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
++#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
++#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
++#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
++#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
++#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
++#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
++#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
++#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
++#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
++#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
++#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
++#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
++#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
++#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
++#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
++#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#endif
+
- #define IRAM_SIZE 0x00040000
+ #define CHIP_REV_1_0 0x10
++#define CHIP_REV_1_2 0x12
++#define CHIP_REV_1_5 0x15
+#ifndef CONFIG_MX6SX
- #define IRAM_SIZE 0x00020000
+ #define IRAM_SIZE 0x00040000
+#else
++#define IRAM_SIZE 0x00020000
+#endif
+ #define IMX_IIM_BASE OCOTP_BASE_ADDR
#define FEC_QUIRK_ENET_MAC
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
- extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
- #define SRC_SCR_CORE_1_RESET_OFFSET 14
- #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
- #define SRC_SCR_CORE_2_RESET_OFFSET 15
- #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
- #define SRC_SCR_CORE_3_RESET_OFFSET 16
- #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
- #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
- #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
- #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
- #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
- #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
- #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
++#define SRC_SCR_CORE_1_RESET_OFFSET 14
++#define SRC_SCR_CORE_1_RESET_MASK (1 << SRC_SCR_CORE_1_RESET_OFFSET)
++#define SRC_SCR_CORE_2_RESET_OFFSET 15
++#define SRC_SCR_CORE_2_RESET_MASK (1 << SRC_SCR_CORE_2_RESET_OFFSET)
++#define SRC_SCR_CORE_3_RESET_OFFSET 16
++#define SRC_SCR_CORE_3_RESET_MASK (1 << SRC_SCR_CORE_3_RESET_OFFSET)
++#define SRC_SCR_CORE_1_ENABLE_OFFSET 22
++#define SRC_SCR_CORE_1_ENABLE_MASK (1 << SRC_SCR_CORE_1_ENABLE_OFFSET)
++#define SRC_SCR_CORE_2_ENABLE_OFFSET 23
++#define SRC_SCR_CORE_2_ENABLE_MASK (1 << SRC_SCR_CORE_2_ENABLE_OFFSET)
++#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
++#define SRC_SCR_CORE_3_ENABLE_MASK (1 << SRC_SCR_CORE_3_ENABLE_OFFSET)
+
+/* WEIM registers */
+struct weim {
+ u32 cs0gcr1;
+ u32 cs0gcr2;
+ u32 cs0rcr1;
+ u32 cs0rcr2;
+ u32 cs0wcr1;
+ u32 cs0wcr2;
+
+ u32 cs1gcr1;
+ u32 cs1gcr2;
+ u32 cs1rcr1;
+ u32 cs1rcr2;
+ u32 cs1wcr1;
+ u32 cs1wcr2;
+
+ u32 cs2gcr1;
+ u32 cs2gcr2;
+ u32 cs2rcr1;
+ u32 cs2rcr2;
+ u32 cs2wcr1;
+ u32 cs2wcr2;
+
+ u32 cs3gcr1;
+ u32 cs3gcr2;
+ u32 cs3rcr1;
+ u32 cs3rcr2;
+ u32 cs3wcr1;
+ u32 cs3wcr2;
+
+ u32 unused[12];
+
+ u32 wcr;
+ u32 wiar;
+ u32 ear;
+};
+
/* System Reset Controller (SRC) */
struct src {
u32 scr;
u32 reserved1[2];
u32 sisr;
u32 simr;
- u32 sbmr2;
- u32 gpr1;
- u32 gpr2;
- u32 gpr3;
- u32 gpr4;
- u32 gpr5;
- u32 gpr6;
- u32 gpr7;
- u32 gpr8;
- u32 gpr9;
- u32 gpr10;
+ u32 sbmr2;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 gpr5;
+ u32 gpr6;
+ u32 gpr7;
+ u32 gpr8;
+ u32 gpr9;
+ u32 gpr10;
};
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
+#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
struct iomuxc {
- u8 reserved[0x4000];
+#ifdef CONFIG_MX6SX
++ u32 reserved[0x1000];
+#endif
u32 gpr[14];
- u32 omux[5];
- /* mux and pad registers */
+};
+
+struct gpc {
+ u32 cntr;
+ u32 pgr;
+ u32 imr1;
+ u32 imr2;
+ u32 imr3;
+ u32 imr4;
+ u32 isr1;
+ u32 isr2;
+ u32 isr3;
+ u32 isr4;
};
#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
};
struct fuse_bank0_regs {
- u32 lock;
- u32 rsvd0[3];
- u32 uid_low;
- u32 rsvd1[3];
- u32 uid_high;
- u32 rsvd2[3];
- u32 rsvd3[4];
- u32 rsvd4[4];
- u32 rsvd5[4];
- u32 cfg5;
- u32 rsvd6[3];
- u32 rsvd7[4];
+ reg_32(misc_conf_lock);
- reg_32(cfg0);
- reg_32(cfg1);
++ union {
++ reg_32(cfg0);
++ reg_32(uid_low);
++ };
++ union {
++ reg_32(cfg1);
++ reg_32(uid_high);
++ };
+ reg_32(cfg2);
+ reg_32(cfg3);
+ reg_32(cfg4);
+ reg_32(cfg5);
+ reg_32(cfg6);
};
+#ifdef CONFIG_MX6SX
+struct fuse_bank4_regs {
+ u32 sjc_resp_low;
+ u32 rsvd0[3];
+ u32 sjc_resp_high;
+ u32 rsvd1[3];
+ u32 mac_addr_low;
+ u32 rsvd2[3];
+ u32 mac_addr_high;
+ u32 rsvd3[3];
+ u32 mac_addr2;
+ u32 rsvd4[7];
+ u32 gp1;
+ u32 rsvd5[7];
+};
+#else
struct fuse_bank4_regs {
- u32 sjc_resp_low;
- u32 rsvd0[3];
- u32 sjc_resp_high;
- u32 rsvd1[3];
- u32 mac_addr_low;
- u32 rsvd2[3];
- u32 mac_addr_high;
- u32 rsvd3[0xb];
- u32 gp1;
- u32 rsvd4[3];
- u32 gp2;
- u32 rsvd5[3];
+ reg_32(sjc_resp_low);
+ reg_32(sjc_resp_high);
+ reg_32(mac_addr_low);
+ reg_32(mac_addr_high);
+ reg_32(rsvd[2]);
+ reg_32(gp1);
+ reg_32(gp2);
+ };
+
+ struct fuse_bank5_regs {
+ reg_32(rsvd[5]);
+ reg_32(pad_settings);
+ reg_32(field_return);
};
+#endif
struct aipstz_regs {
u32 mprot0;
u32 opacr4;
};
-struct iomuxc_base_regs {
- u32 gpr[14]; /* 0x000 */
- u32 obsrv[5]; /* 0x038 */
- u32 swmux_ctl[197]; /* 0x04c */
- u32 swpad_ctl[250]; /* 0x360 */
- u32 swgrp[26]; /* 0x748 */
- u32 daisy[104]; /* 0x7b0..94c */
+struct anatop_regs {
- u32 pll_sys; /* 0x000 */
- u32 pll_sys_set; /* 0x004 */
- u32 pll_sys_clr; /* 0x008 */
- u32 pll_sys_tog; /* 0x00c */
- u32 usb1_pll_480_ctrl; /* 0x010 */
- u32 usb1_pll_480_ctrl_set; /* 0x014 */
- u32 usb1_pll_480_ctrl_clr; /* 0x018 */
- u32 usb1_pll_480_ctrl_tog; /* 0x01c */
- u32 usb2_pll_480_ctrl; /* 0x020 */
- u32 usb2_pll_480_ctrl_set; /* 0x024 */
- u32 usb2_pll_480_ctrl_clr; /* 0x028 */
- u32 usb2_pll_480_ctrl_tog; /* 0x02c */
- u32 pll_528; /* 0x030 */
- u32 pll_528_set; /* 0x034 */
- u32 pll_528_clr; /* 0x038 */
- u32 pll_528_tog; /* 0x03c */
- u32 pll_528_ss; /* 0x040 */
- u32 rsvd0[3];
- u32 pll_528_num; /* 0x050 */
- u32 rsvd1[3];
- u32 pll_528_denom; /* 0x060 */
- u32 rsvd2[3];
- u32 pll_audio; /* 0x070 */
- u32 pll_audio_set; /* 0x074 */
- u32 pll_audio_clr; /* 0x078 */
- u32 pll_audio_tog; /* 0x07c */
- u32 pll_audio_num; /* 0x080 */
- u32 rsvd3[3];
- u32 pll_audio_denom; /* 0x090 */
- u32 rsvd4[3];
- u32 pll_video; /* 0x0a0 */
- u32 pll_video_set; /* 0x0a4 */
- u32 pll_video_clr; /* 0x0a8 */
- u32 pll_video_tog; /* 0x0ac */
- u32 pll_video_num; /* 0x0b0 */
- u32 rsvd5[3];
- u32 pll_video_denom; /* 0x0c0 */
- u32 rsvd6[3];
- u32 pll_mlb; /* 0x0d0 */
- u32 pll_mlb_set; /* 0x0d4 */
- u32 pll_mlb_clr; /* 0x0d8 */
- u32 pll_mlb_tog; /* 0x0dc */
- u32 pll_enet; /* 0x0e0 */
- u32 pll_enet_set; /* 0x0e4 */
- u32 pll_enet_clr; /* 0x0e8 */
- u32 pll_enet_tog; /* 0x0ec */
- u32 pfd_480; /* 0x0f0 */
- u32 pfd_480_set; /* 0x0f4 */
- u32 pfd_480_clr; /* 0x0f8 */
- u32 pfd_480_tog; /* 0x0fc */
- u32 pfd_528; /* 0x100 */
- u32 pfd_528_set; /* 0x104 */
- u32 pfd_528_clr; /* 0x108 */
- u32 pfd_528_tog; /* 0x10c */
- u32 reg_1p1; /* 0x110 */
- u32 reg_1p1_set; /* 0x114 */
- u32 reg_1p1_clr; /* 0x118 */
- u32 reg_1p1_tog; /* 0x11c */
- u32 reg_3p0; /* 0x120 */
- u32 reg_3p0_set; /* 0x124 */
- u32 reg_3p0_clr; /* 0x128 */
- u32 reg_3p0_tog; /* 0x12c */
- u32 reg_2p5; /* 0x130 */
- u32 reg_2p5_set; /* 0x134 */
- u32 reg_2p5_clr; /* 0x138 */
- u32 reg_2p5_tog; /* 0x13c */
- u32 reg_core; /* 0x140 */
- u32 reg_core_set; /* 0x144 */
- u32 reg_core_clr; /* 0x148 */
- u32 reg_core_tog; /* 0x14c */
- u32 ana_misc0; /* 0x150 */
- u32 ana_misc0_set; /* 0x154 */
- u32 ana_misc0_clr; /* 0x158 */
- u32 ana_misc0_tog; /* 0x15c */
- u32 ana_misc1; /* 0x160 */
- u32 ana_misc1_set; /* 0x164 */
- u32 ana_misc1_clr; /* 0x168 */
- u32 ana_misc1_tog; /* 0x16c */
- u32 ana_misc2; /* 0x170 */
- u32 ana_misc2_set; /* 0x174 */
- u32 ana_misc2_clr; /* 0x178 */
- u32 ana_misc2_tog; /* 0x17c */
- u32 tempsense0; /* 0x180 */
- u32 tempsense0_set; /* 0x184 */
- u32 tempsense0_clr; /* 0x188 */
- u32 tempsense0_tog; /* 0x18c */
- u32 tempsense1; /* 0x190 */
- u32 tempsense1_set; /* 0x194 */
- u32 tempsense1_clr; /* 0x198 */
- u32 tempsense1_tog; /* 0x19c */
- u32 usb1_vbus_detect; /* 0x1a0 */
- u32 usb1_vbus_detect_set; /* 0x1a4 */
- u32 usb1_vbus_detect_clr; /* 0x1a8 */
- u32 usb1_vbus_detect_tog; /* 0x1ac */
- u32 usb1_chrg_detect; /* 0x1b0 */
- u32 usb1_chrg_detect_set; /* 0x1b4 */
- u32 usb1_chrg_detect_clr; /* 0x1b8 */
- u32 usb1_chrg_detect_tog; /* 0x1bc */
- u32 usb1_vbus_det_stat; /* 0x1c0 */
- u32 usb1_vbus_det_stat_set; /* 0x1c4 */
- u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
- u32 usb1_vbus_det_stat_tog; /* 0x1cc */
- u32 usb1_chrg_det_stat; /* 0x1d0 */
- u32 usb1_chrg_det_stat_set; /* 0x1d4 */
- u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
- u32 usb1_chrg_det_stat_tog; /* 0x1dc */
- u32 usb1_loopback; /* 0x1e0 */
- u32 usb1_loopback_set; /* 0x1e4 */
- u32 usb1_loopback_clr; /* 0x1e8 */
- u32 usb1_loopback_tog; /* 0x1ec */
- u32 usb1_misc; /* 0x1f0 */
- u32 usb1_misc_set; /* 0x1f4 */
- u32 usb1_misc_clr; /* 0x1f8 */
- u32 usb1_misc_tog; /* 0x1fc */
- u32 usb2_vbus_detect; /* 0x200 */
- u32 usb2_vbus_detect_set; /* 0x204 */
- u32 usb2_vbus_detect_clr; /* 0x208 */
- u32 usb2_vbus_detect_tog; /* 0x20c */
- u32 usb2_chrg_detect; /* 0x210 */
- u32 usb2_chrg_detect_set; /* 0x214 */
- u32 usb2_chrg_detect_clr; /* 0x218 */
- u32 usb2_chrg_detect_tog; /* 0x21c */
- u32 usb2_vbus_det_stat; /* 0x220 */
- u32 usb2_vbus_det_stat_set; /* 0x224 */
- u32 usb2_vbus_det_stat_clr; /* 0x228 */
- u32 usb2_vbus_det_stat_tog; /* 0x22c */
- u32 usb2_chrg_det_stat; /* 0x230 */
- u32 usb2_chrg_det_stat_set; /* 0x234 */
- u32 usb2_chrg_det_stat_clr; /* 0x238 */
- u32 usb2_chrg_det_stat_tog; /* 0x23c */
- u32 usb2_loopback; /* 0x240 */
- u32 usb2_loopback_set; /* 0x244 */
- u32 usb2_loopback_clr; /* 0x248 */
- u32 usb2_loopback_tog; /* 0x24c */
- u32 usb2_misc; /* 0x250 */
- u32 usb2_misc_set; /* 0x254 */
- u32 usb2_misc_clr; /* 0x258 */
- u32 usb2_misc_tog; /* 0x25c */
- u32 digprog; /* 0x260 */
- u32 reserved1[7];
- u32 digprog_sololite; /* 0x280 */
++ mxs_reg_32(pll_arm); /* 0x000 */
++ mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */
++ mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */
++ mxs_reg_32(pll_528); /* 0x030 */
++ reg_32(pll_528_ss); /* 0x040 */
++ reg_32(pll_528_num); /* 0x050 */
++ reg_32(pll_528_denom); /* 0x060 */
++ mxs_reg_32(pll_audio); /* 0x070 */
++ reg_32(pll_audio_num); /* 0x080 */
++ reg_32(pll_audio_denom); /* 0x090 */
++ mxs_reg_32(pll_video); /* 0x0a0 */
++ reg_32(pll_video_num); /* 0x0b0 */
++ reg_32(pll_video_denom); /* 0x0c0 */
++ mxs_reg_32(pll_mlb); /* 0x0d0 */
++ mxs_reg_32(pll_enet); /* 0x0e0 */
++ mxs_reg_32(pfd_480); /* 0x0f0 */
++ mxs_reg_32(pfd_528); /* 0x100 */
++ mxs_reg_32(reg_1p1); /* 0x110 */
++ mxs_reg_32(reg_3p0); /* 0x120 */
++ mxs_reg_32(reg_2p5); /* 0x130 */
++ mxs_reg_32(reg_core); /* 0x140 */
++ mxs_reg_32(ana_misc0); /* 0x150 */
++ mxs_reg_32(ana_misc1); /* 0x160 */
++ mxs_reg_32(ana_misc2); /* 0x170 */
++ mxs_reg_32(tempsense0); /* 0x180 */
++ mxs_reg_32(tempsense1); /* 0x190 */
++ mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */
++ mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */
++ mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
++ mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
++ mxs_reg_32(usb1_loopback); /* 0x1e0 */
++ mxs_reg_32(usb1_misc); /* 0x1f0 */
++ mxs_reg_32(usb2_vbus_detect); /* 0x200 */
++ mxs_reg_32(usb2_chrg_detect); /* 0x210 */
++ mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */
++ mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */
++ mxs_reg_32(usb2_loopback); /* 0x240 */
++ mxs_reg_32(usb2_misc); /* 0x250 */
++ reg_32(digprog); /* 0x260 */
++ reg_32(rsrvd); /* 0x270 */
++ reg_32(digprog_sololite); /* 0x280 */
};
- #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
- #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
- #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
- #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
- #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
- #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
++#define ANATOP_PFD_FRAC_SHIFT(n) ((n) * 8)
++#define ANATOP_PFD_FRAC_MASK(n) (0x3f << ANATOP_PFD_FRAC_SHIFT(n))
++#define ANATOP_PFD_STABLE_SHIFT(n) (6 + ((n) * 8))
++#define ANATOP_PFD_STABLE_MASK(n) (1 << ANATOP_PFD_STABLE_SHIFT(n))
++#define ANATOP_PFD_CLKGATE_SHIFT(n) (7 + ((n) * 8))
++#define ANATOP_PFD_CLKGATE_MASK(n) (1 << ANATOP_PFD_CLKGATE_SHIFT(n))
+
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */
u16 wmcr; /* Miscellaneous Control */
};
- #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
++#define PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
#endif /* __ASSEMBLER__*/
-
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
#define _SYS_PROTO_H_
#include <asm/imx-common/regs-common.h>
+#include "../arch-imx/cpu.h"
-#define MXC_CPU_MX51 0x51
-#define MXC_CPU_MX53 0x53
-#define MXC_CPU_MX6SL 0x60
-#define MXC_CPU_MX6DL 0x61
-#define MXC_CPU_MX6SOLO 0x62
-#define MXC_CPU_MX6Q 0x63
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev) (soc_rev() - rev)
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
+
+/* returns MXC_CPU_ value */
+#define cpu_type(rev) (((rev) >> 12)&0xff)
+
+/* both macros return/take MXC_CPU_ constants */
+#define get_cpu_type() (cpu_type(get_cpu_rev()))
+#define is_cpu_type(cpu) (get_cpu_type() == cpu)
+
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
+void set_chipselect_size(int const);
+
+ struct mxs_register_32;
+
+ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
/* Reg mapping structure */
struct emif_reg_struct {
- u32 emif_mod_id_rev;
- u32 emif_status;
- u32 emif_sdram_config;
- u32 emif_lpddr2_nvm_config;
- u32 emif_sdram_ref_ctrl;
- u32 emif_sdram_ref_ctrl_shdw;
- u32 emif_sdram_tim_1;
- u32 emif_sdram_tim_1_shdw;
- u32 emif_sdram_tim_2;
- u32 emif_sdram_tim_2_shdw;
- u32 emif_sdram_tim_3;
- u32 emif_sdram_tim_3_shdw;
- u32 emif_lpddr2_nvm_tim;
- u32 emif_lpddr2_nvm_tim_shdw;
- u32 emif_pwr_mgmt_ctrl;
- u32 emif_pwr_mgmt_ctrl_shdw;
- u32 emif_lpddr2_mode_reg_data;
- u32 padding1[1];
- u32 emif_lpddr2_mode_reg_data_es2;
- u32 padding11[1];
- u32 emif_lpddr2_mode_reg_cfg;
- u32 emif_l3_config;
- u32 emif_l3_cfg_val_1;
- u32 emif_l3_cfg_val_2;
- u32 emif_iodft_tlgc;
- u32 padding2[7];
- u32 emif_perf_cnt_1;
- u32 emif_perf_cnt_2;
- u32 emif_perf_cnt_cfg;
- u32 emif_perf_cnt_sel;
- u32 emif_perf_cnt_tim;
- u32 padding3;
- u32 emif_read_idlectrl;
- u32 emif_read_idlectrl_shdw;
- u32 padding4;
- u32 emif_irqstatus_raw_sys;
- u32 emif_irqstatus_raw_ll;
- u32 emif_irqstatus_sys;
- u32 emif_irqstatus_ll;
- u32 emif_irqenable_set_sys;
- u32 emif_irqenable_set_ll;
- u32 emif_irqenable_clr_sys;
- u32 emif_irqenable_clr_ll;
- u32 padding5;
- u32 emif_zq_config;
- u32 emif_temp_alert_config;
- u32 emif_l3_err_log;
- u32 emif_rd_wr_lvl_rmp_win;
- u32 emif_rd_wr_lvl_rmp_ctl;
- u32 emif_rd_wr_lvl_ctl;
- u32 padding6[1];
- u32 emif_ddr_phy_ctrl_1;
- u32 emif_ddr_phy_ctrl_1_shdw;
- u32 emif_ddr_phy_ctrl_2;
- u32 padding7[4];
- u32 emif_prio_class_serv_map;
- u32 emif_connect_id_serv_1_map;
- u32 emif_connect_id_serv_2_map;
- u32 padding8[5];
- u32 emif_rd_wr_exec_thresh;
- u32 emif_cos_config;
- u32 padding9[6];
- u32 emif_ddr_phy_status[21];
- u32 padding10[27];
- u32 emif_ddr_ext_phy_ctrl_1;
- u32 emif_ddr_ext_phy_ctrl_1_shdw;
- u32 emif_ddr_ext_phy_ctrl_2;
- u32 emif_ddr_ext_phy_ctrl_2_shdw;
- u32 emif_ddr_ext_phy_ctrl_3;
- u32 emif_ddr_ext_phy_ctrl_3_shdw;
- u32 emif_ddr_ext_phy_ctrl_4;
- u32 emif_ddr_ext_phy_ctrl_4_shdw;
- u32 emif_ddr_ext_phy_ctrl_5;
- u32 emif_ddr_ext_phy_ctrl_5_shdw;
- u32 emif_ddr_ext_phy_ctrl_6;
- u32 emif_ddr_ext_phy_ctrl_6_shdw;
- u32 emif_ddr_ext_phy_ctrl_7;
- u32 emif_ddr_ext_phy_ctrl_7_shdw;
- u32 emif_ddr_ext_phy_ctrl_8;
- u32 emif_ddr_ext_phy_ctrl_8_shdw;
- u32 emif_ddr_ext_phy_ctrl_9;
- u32 emif_ddr_ext_phy_ctrl_9_shdw;
- u32 emif_ddr_ext_phy_ctrl_10;
- u32 emif_ddr_ext_phy_ctrl_10_shdw;
- u32 emif_ddr_ext_phy_ctrl_11;
- u32 emif_ddr_ext_phy_ctrl_11_shdw;
- u32 emif_ddr_ext_phy_ctrl_12;
- u32 emif_ddr_ext_phy_ctrl_12_shdw;
- u32 emif_ddr_ext_phy_ctrl_13;
- u32 emif_ddr_ext_phy_ctrl_13_shdw;
- u32 emif_ddr_ext_phy_ctrl_14;
- u32 emif_ddr_ext_phy_ctrl_14_shdw;
- u32 emif_ddr_ext_phy_ctrl_15;
- u32 emif_ddr_ext_phy_ctrl_15_shdw;
- u32 emif_ddr_ext_phy_ctrl_16;
- u32 emif_ddr_ext_phy_ctrl_16_shdw;
- u32 emif_ddr_ext_phy_ctrl_17;
- u32 emif_ddr_ext_phy_ctrl_17_shdw;
- u32 emif_ddr_ext_phy_ctrl_18;
- u32 emif_ddr_ext_phy_ctrl_18_shdw;
- u32 emif_ddr_ext_phy_ctrl_19;
- u32 emif_ddr_ext_phy_ctrl_19_shdw;
- u32 emif_ddr_ext_phy_ctrl_20;
- u32 emif_ddr_ext_phy_ctrl_20_shdw;
- u32 emif_ddr_ext_phy_ctrl_21;
- u32 emif_ddr_ext_phy_ctrl_21_shdw;
- u32 emif_ddr_ext_phy_ctrl_22;
- u32 emif_ddr_ext_phy_ctrl_22_shdw;
- u32 emif_ddr_ext_phy_ctrl_23;
- u32 emif_ddr_ext_phy_ctrl_23_shdw;
- u32 emif_ddr_ext_phy_ctrl_24;
- u32 emif_ddr_ext_phy_ctrl_24_shdw;
- u32 padding[22];
- u32 emif_ddr_fifo_misaligned_clear_1;
- u32 emif_ddr_fifo_misaligned_clear_2;
+ u32 emif_mod_id_rev; /* 0x000 */
+ u32 emif_status; /* 0x004 */
+ u32 emif_sdram_config; /* 0x008 */
+ u32 emif_lpddr2_nvm_config; /* 0x00c */
+ u32 emif_sdram_ref_ctrl; /* 0x010 */
+ u32 emif_sdram_ref_ctrl_shdw; /* 0x014 */
+ u32 emif_sdram_tim_1; /* 0x018 */
+ u32 emif_sdram_tim_1_shdw; /* 0x01c */
+ u32 emif_sdram_tim_2; /* 0x020 */
+ u32 emif_sdram_tim_2_shdw; /* 0x024 */
+ u32 emif_sdram_tim_3; /* 0x028 */
+ u32 emif_sdram_tim_3_shdw; /* 0x02c */
+ u32 emif_lpddr2_nvm_tim; /* 0x030 */
+ u32 emif_lpddr2_nvm_tim_shdw; /* 0x034 */
+ u32 emif_pwr_mgmt_ctrl; /* 0x038 */
+ u32 emif_pwr_mgmt_ctrl_shdw; /* 0x03c */
+ u32 emif_lpddr2_mode_reg_data; /* 0x040 */
+ u32 padding1[1]; /* 0x044 */
+ u32 emif_lpddr2_mode_reg_data_es2; /* 0x048 */
+ u32 padding11[1]; /* 0x04c */
+ u32 emif_lpddr2_mode_reg_cfg; /* 0x050 */
+ u32 emif_l3_config; /* 0x054 */
+ u32 emif_l3_cfg_val_1; /* 0x058 */
+ u32 emif_l3_cfg_val_2; /* 0x05c */
+ u32 emif_iodft_tlgc; /* 0x060 */
+ u32 padding2[7]; /* 0x064 */
+ u32 emif_perf_cnt_1; /* 0x080 */
+ u32 emif_perf_cnt_2; /* 0x084 */
+ u32 emif_perf_cnt_cfg; /* 0x088 */
+ u32 emif_perf_cnt_sel; /* 0x08c */
+ u32 emif_perf_cnt_tim; /* 0x090 */
+ u32 padding3; /* 0x094 */
+ u32 emif_read_idlectrl; /* 0x098 */
+ u32 emif_read_idlectrl_shdw; /* 0x09c */
+ u32 padding4; /* 0x0a0 */
+ u32 emif_irqstatus_raw_sys; /* 0x0a4 */
+ u32 emif_irqstatus_raw_ll; /* 0x0a8 */
+ u32 emif_irqstatus_sys; /* 0x0ac */
+ u32 emif_irqstatus_ll; /* 0x0b0 */
+ u32 emif_irqenable_set_sys; /* 0x0b4 */
+ u32 emif_irqenable_set_ll; /* 0x0b8 */
+ u32 emif_irqenable_clr_sys; /* 0x0bc */
+ u32 emif_irqenable_clr_ll; /* 0x0c0 */
+ u32 padding5; /* 0x0c4 */
+ u32 emif_zq_config; /* 0x0c8 */
+ u32 emif_temp_alert_config; /* 0x0cc */
+ u32 emif_l3_err_log; /* 0x0d0 */
+ u32 emif_rd_wr_lvl_rmp_win; /* 0x0d4 */
+ u32 emif_rd_wr_lvl_rmp_ctl; /* 0x0d8 */
+ u32 emif_rd_wr_lvl_ctl; /* 0x0dc */
+ u32 padding6[1]; /* 0x0e0 */
+ u32 emif_ddr_phy_ctrl_1; /* 0x0e4 */
+ u32 emif_ddr_phy_ctrl_1_shdw; /* 0x0e8 */
+ u32 emif_ddr_phy_ctrl_2; /* 0x0ec */
- u32 padding7[12]; /* 0x0f0 */
++ u32 padding7[4]; /* 0x0f0 */
++ u32 emif_prio_class_serv_map; /* 0x100 */
++ u32 emif_connect_id_serv_1_map; /* 0x104 */
++ u32 emif_connect_id_serv_2_map; /* 0x108 */
++ u32 padding8[5]; /* 0x10c */
+ u32 emif_rd_wr_exec_thresh; /* 0x120 */
- u32 padding8[55]; /* 0x124 */
++ u32 padding9[6]; /* 0x124 */
++ u32 emif_ddr_phy_status[21]; /* 0x13c */
++ u32 padding10[27]; /* 0x1fc */
+ u32 emif_ddr_ext_phy_ctrl_1; /* 0x200 */
+ u32 emif_ddr_ext_phy_ctrl_1_shdw; /* 0x204 */
+ u32 emif_ddr_ext_phy_ctrl_2; /* 0x248 */
+ u32 emif_ddr_ext_phy_ctrl_2_shdw; /* 0x24c */
+ u32 emif_ddr_ext_phy_ctrl_3; /* 0x200 */
+ u32 emif_ddr_ext_phy_ctrl_3_shdw; /* 0x204 */
+ u32 emif_ddr_ext_phy_ctrl_4; /* 0x208 */
+ u32 emif_ddr_ext_phy_ctrl_4_shdw; /* 0x20c */
+ u32 emif_ddr_ext_phy_ctrl_5; /* 0x210 */
+ u32 emif_ddr_ext_phy_ctrl_5_shdw; /* 0x214 */
+ u32 emif_ddr_ext_phy_ctrl_6; /* 0x218 */
+ u32 emif_ddr_ext_phy_ctrl_6_shdw; /* 0x21c */
+ u32 emif_ddr_ext_phy_ctrl_7; /* 0x220 */
+ u32 emif_ddr_ext_phy_ctrl_7_shdw; /* 0x224 */
+ u32 emif_ddr_ext_phy_ctrl_8; /* 0x228 */
+ u32 emif_ddr_ext_phy_ctrl_8_shdw; /* 0x22c */
+ u32 emif_ddr_ext_phy_ctrl_9; /* 0x230 */
+ u32 emif_ddr_ext_phy_ctrl_9_shdw; /* 0x234 */
+ u32 emif_ddr_ext_phy_ctrl_10; /* 0x238 */
+ u32 emif_ddr_ext_phy_ctrl_10_shdw; /* 0x23c */
+ u32 emif_ddr_ext_phy_ctrl_11; /* 0x240 */
+ u32 emif_ddr_ext_phy_ctrl_11_shdw; /* 0x244 */
+ u32 emif_ddr_ext_phy_ctrl_12; /* 0x248 */
+ u32 emif_ddr_ext_phy_ctrl_12_shdw; /* 0x24c */
+ u32 emif_ddr_ext_phy_ctrl_13; /* 0x250 */
+ u32 emif_ddr_ext_phy_ctrl_13_shdw; /* 0x254 */
+ u32 emif_ddr_ext_phy_ctrl_14; /* 0x258 */
+ u32 emif_ddr_ext_phy_ctrl_14_shdw; /* 0x25c */
+ u32 emif_ddr_ext_phy_ctrl_15; /* 0x260 */
+ u32 emif_ddr_ext_phy_ctrl_15_shdw; /* 0x264 */
+ u32 emif_ddr_ext_phy_ctrl_16; /* 0x268 */
+ u32 emif_ddr_ext_phy_ctrl_16_shdw; /* 0x26c */
+ u32 emif_ddr_ext_phy_ctrl_17; /* 0x270 */
+ u32 emif_ddr_ext_phy_ctrl_17_shdw; /* 0x274 */
+ u32 emif_ddr_ext_phy_ctrl_18; /* 0x278 */
+ u32 emif_ddr_ext_phy_ctrl_18_shdw; /* 0x27c */
+ u32 emif_ddr_ext_phy_ctrl_19; /* 0x280 */
+ u32 emif_ddr_ext_phy_ctrl_19_shdw; /* 0x284 */
+ u32 emif_ddr_ext_phy_ctrl_20; /* 0x288 */
+ u32 emif_ddr_ext_phy_ctrl_20_shdw; /* 0x28c */
+ u32 emif_ddr_ext_phy_ctrl_21; /* 0x290 */
+ u32 emif_ddr_ext_phy_ctrl_21_shdw; /* 0x294 */
+ u32 emif_ddr_ext_phy_ctrl_22; /* 0x298 */
+ u32 emif_ddr_ext_phy_ctrl_22_shdw; /* 0x29c */
+ u32 emif_ddr_ext_phy_ctrl_23; /* 0x2a0 */
+ u32 emif_ddr_ext_phy_ctrl_23_shdw; /* 0x2a4 */
+ u32 emif_ddr_ext_phy_ctrl_24; /* 0x2a8 */
+ u32 emif_ddr_ext_phy_ctrl_24_shdw; /* 0x2ac */
++ u32 padding[22]; /* 0x2b0 */
++ u32 emif_ddr_fifo_misaligned_clear_1; /* 0x308 */
++ u32 emif_ddr_fifo_misaligned_clear_2; /* 0x30c */
};
struct dmm_lisa_map_regs {
s8 mr16;
};
+struct read_write_regs {
+ u32 read_reg;
+ u32 write_reg;
+};
+
+static inline u32 get_emif_rev(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
+ >> EMIF_REG_MAJOR_REVISION_SHIFT;
+}
+
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ return (readl(&emif->emif_sdram_config) &
+ EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
/* assert macros */
#if defined(DEBUG)
- #define emif_assert(c) ({ if (!(c)) for (;;); })
+ #define emif_assert(c) ({ if (!(c)) hang(); })
#else
- #define emif_assert(c) ({ if (0) hang(); })
+ #define emif_assert(c) (c)
#endif
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+
+#if defined(CONFIG_U_QE)
+ u32 qe_clk;
+ u32 brg_clk;
+ uint mp_alloc_base;
+ uint mp_alloc_top;
+#endif /* CONFIG_U_QE */
+
+ #ifdef CONFIG_VIDEO_IPUV3
+ unsigned int ipu_hw_rev;
+ #endif
++
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
- #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
+ MUX_MODE_SHIFT)
+ #define __MUX_PAD_CTRL(x) ((x) | __PAD_CTRL_VALID)
+ #define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)__MUX_PAD_CTRL(x) << \
+ MUX_PAD_CTRL_SHIFT))
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
sel_input, pad_ctrl) \
#ifdef CONFIG_MX6
- #define PAD_CTL_HYS (1 << 16)
+ #define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16)
- #define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
- #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
- #define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
- #define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
- #define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
- #define PAD_CTL_PKE (1 << 12)
+ #define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 14 | PAD_CTL_PUE)
+ #define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 14 | PAD_CTL_PUE)
+ #define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 14 | PAD_CTL_PUE)
+ #define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 14 | PAD_CTL_PUE)
+ #define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 13 | PAD_CTL_PKE)
+ #define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 12)
- #define PAD_CTL_ODE (1 << 11)
+ #define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 11)
- #define PAD_CTL_SPEED_LOW (1 << 6)
- #define PAD_CTL_SPEED_MED (2 << 6)
- #define PAD_CTL_SPEED_HIGH (3 << 6)
+ #define PAD_CTL_SPEED_LOW __MUX_PAD_CTRL(1 << 6)
+ #define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(2 << 6)
+ #define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 6)
- #define PAD_CTL_DSE_DISABLE (0 << 3)
- #define PAD_CTL_DSE_240ohm (1 << 3)
- #define PAD_CTL_DSE_120ohm (2 << 3)
- #define PAD_CTL_DSE_80ohm (3 << 3)
- #define PAD_CTL_DSE_60ohm (4 << 3)
- #define PAD_CTL_DSE_48ohm (5 << 3)
- #define PAD_CTL_DSE_40ohm (6 << 3)
- #define PAD_CTL_DSE_34ohm (7 << 3)
+ #define PAD_CTL_DSE_DISABLE __MUX_PAD_CTRL(0 << 3)
+ #define PAD_CTL_DSE_240ohm __MUX_PAD_CTRL(1 << 3)
+ #define PAD_CTL_DSE_120ohm __MUX_PAD_CTRL(2 << 3)
+ #define PAD_CTL_DSE_80ohm __MUX_PAD_CTRL(3 << 3)
+ #define PAD_CTL_DSE_60ohm __MUX_PAD_CTRL(4 << 3)
+ #define PAD_CTL_DSE_48ohm __MUX_PAD_CTRL(5 << 3)
+ #define PAD_CTL_DSE_40ohm __MUX_PAD_CTRL(6 << 3)
+ #define PAD_CTL_DSE_34ohm __MUX_PAD_CTRL(7 << 3)
- #define PAD_CTL_LVE (1 << 1)
- #define PAD_CTL_LVE_BIT (1 << 22)
+#if defined CONFIG_MX6SL
++#define PAD_CTL_LVE __MUX_PAD_CTRL(1 << 1)
++#define PAD_CTL_LVE_BIT __MUX_PAD_CTRL(1 << 22)
+#endif
+
#elif defined(CONFIG_VF610)
#define PAD_MUX_MODE_SHIFT 20
- #define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
++#define PAD_CTL_INPUT_DIFFERENTIAL __MUX_PAD_CTRL(1 << 16)
+
- #define PAD_CTL_SPEED_MED (1 << 12)
- #define PAD_CTL_SPEED_HIGH (3 << 12)
+ #define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(1 << 12)
+ #define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 12)
- #define PAD_CTL_SRE (1 << 11)
++#define PAD_CTL_SRE __MUX_PAD_CTRL(1 << 11)
+
- #define PAD_CTL_DSE_150ohm (1 << 6)
- #define PAD_CTL_DSE_50ohm (3 << 6)
- #define PAD_CTL_DSE_25ohm (6 << 6)
- #define PAD_CTL_DSE_20ohm (7 << 6)
++#define PAD_CTL_DSE_150ohm __MUX_PAD_CTRL(1 << 6)
+ #define PAD_CTL_DSE_50ohm __MUX_PAD_CTRL(3 << 6)
+ #define PAD_CTL_DSE_25ohm __MUX_PAD_CTRL(6 << 6)
+ #define PAD_CTL_DSE_20ohm __MUX_PAD_CTRL(7 << 6)
- #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
- #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
- #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
- #define PAD_CTL_PKE (1 << 3)
- #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
+ #define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE)
+ #define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE)
++#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE)
+ #define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 3)
+ #define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 2 | PAD_CTL_PKE)
- #define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
- #define PAD_CTL_OBE_ENABLE (1 << 1)
- #define PAD_CTL_IBE_ENABLE (1 << 0)
+ #define PAD_CTL_OBE_IBE_ENABLE __MUX_PAD_CTRL(3 << 0)
++#define PAD_CTL_OBE_ENABLE __MUX_PAD_CTRL(1 << 1)
++#define PAD_CTL_IBE_ENABLE __MUX_PAD_CTRL(1 << 0)
#else
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
--void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
++void imx_iomux_v3_setup_pad(const iomux_v3_cfg_t const pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value);
+
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def); \
+}
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
- #endif /* __MACH_IOMUX_V3_H__*/
+ #endif /* __ASM_ARCH_IOMUX_V3_H__*/
--- /dev/null
- || defined(CONFIG_MX51) || defined(CONFIG_MX53)
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/kbuild.h>
+
+#if defined(CONFIG_MB86R0x)
+#include <asm/arch/mb86r0x.h>
+#endif
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
++ || defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#include <asm/arch/imx-regs.h>
+#endif
++#if defined(CONFIG_MX6)
++#include <asm/arch/crm_regs.h>
++#endif
+
+int main(void)
+{
+ /*
+ * TODO : Check if each entry in this file is really necessary.
+ * - struct mb86r0x_ddr2
+ * - struct mb86r0x_memc
+ * - struct esdramc_regs
+ * - struct max_regs
+ * - struct aips_regs
+ * - struct aipi_regs
+ * - struct clkctl
+ * - struct dpll
+ * are used only for generating asm-offsets.h.
+ * It means their offset addresses are referenced only from assembly
+ * code. Is it better to define the macros directly in headers?
+ */
+
+#if defined(CONFIG_MB86R0x)
+ /* ddr2 controller */
+ DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
+ DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
+ DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
+ DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
+ DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
+ DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
+ DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
+ DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
+ DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
+ DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
+ DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
+ DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
+ DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
+ DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
+ DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
+
+ /* clock reset generator */
+ DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
+ DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
+ DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
+ DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
+ DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
+ DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
+
+ /* chip control module */
+ DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
+
+ /* external bus interface */
+ DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
+ DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
+ DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
+ DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
+ DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
+ DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
+ DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
+ DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
+ DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
+#endif
+
+#if defined(CONFIG_MX25)
+ /* Clock Control Module */
+ DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+ DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+ DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+ DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+ DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+ DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+ /* Enhanced SDRAM Controller */
+ DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+ DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+ DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+ /* Multi-Layer AHB Crossbar Switch */
+ DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+ DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+ DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+ DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+ DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+ DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+ DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+ DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+ DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+ DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+ DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+ DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+ DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+ DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+ DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+ /* AHB <-> IP-Bus Interface */
+ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+ DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+#endif
+
+#if defined(CONFIG_MX27)
+ DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
+ DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
+ DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
+ DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
+
+ DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
+ DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
+ DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
+ DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
+ DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+ DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+ DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+
+ DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+ DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+ DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
+ DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
+ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, gpcr));
+ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, fmcr));
+#endif
+
+#if defined(CONFIG_MX35)
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
+ DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
+ DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
+ DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
+ DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
+ DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
+ DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
+ DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
+ DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
+ DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
+ DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
+ DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
+ DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
+ DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
+ DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
+
+ /* Multi-Layer AHB Crossbar Switch */
+ DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+ DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+ DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+ DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+ DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+ DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+ DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+ DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+ DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+ DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+ DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+ DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+ DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+ DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+ DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+ DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
+
+ /* AHB <-> IP-Bus Interface */
+ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+ DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+ DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
+ DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
+ DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
+ DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
+ DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
+ DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
+ DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
+ DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
+ DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
+ DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
+ DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+ DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+ DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+ DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
+ DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
+ DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+ DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+ DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+ DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
+ DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
+ DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
+ DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
+ DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+ DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+ DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+ DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
+ DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
+ DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
+ DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+ DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+ DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+ DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+ DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+ DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+ DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+ DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+ DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+ DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+ DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+ DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+ DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+ DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
+#if defined(CONFIG_MX53)
+ DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+#endif
+
+ /* DPLL */
+ DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
+ DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
+ DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
+ DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
+ DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
+ DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
+ DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
+ DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
+#endif
++#if defined(CONFIG_MX6)
++ DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
++ DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
++ DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));
++ DEFINE(CCM_CCSR, offsetof(struct mxc_ccm_reg, ccsr));
++ DEFINE(CCM_CACRR, offsetof(struct mxc_ccm_reg, cacrr));
++ DEFINE(CCM_CBCDR, offsetof(struct mxc_ccm_reg, cbcdr));
++ DEFINE(CCM_CBCMR, offsetof(struct mxc_ccm_reg, cbcmr));
++ DEFINE(CCM_CSCMR1, offsetof(struct mxc_ccm_reg, cscmr1));
++ DEFINE(CCM_CSCMR2, offsetof(struct mxc_ccm_reg, cscmr2));
++ DEFINE(CCM_CSCDR1, offsetof(struct mxc_ccm_reg, cscdr1));
++ DEFINE(CCM_CS1CDR, offsetof(struct mxc_ccm_reg, cs1cdr));
++ DEFINE(CCM_CS2CDR, offsetof(struct mxc_ccm_reg, cs2cdr));
++ DEFINE(CCM_CDCDR, offsetof(struct mxc_ccm_reg, cdcdr));
++ DEFINE(CCM_CHSCCDR, offsetof(struct mxc_ccm_reg, chsccdr));
++ DEFINE(CCM_CSCDR2, offsetof(struct mxc_ccm_reg, cscdr2));
++ DEFINE(CCM_CSCDR3, offsetof(struct mxc_ccm_reg, cscdr3));
++ DEFINE(CCM_CSCDR4, offsetof(struct mxc_ccm_reg, cscdr4));
++ DEFINE(CCM_CDHIPR, offsetof(struct mxc_ccm_reg, cdhipr));
++ DEFINE(CCM_CDCR, offsetof(struct mxc_ccm_reg, cdcr));
++ DEFINE(CCM_CTOR, offsetof(struct mxc_ccm_reg, ctor));
++ DEFINE(CCM_CLPCR, offsetof(struct mxc_ccm_reg, clpcr));
++ DEFINE(CCM_CISR, offsetof(struct mxc_ccm_reg, cisr));
++ DEFINE(CCM_CIMR, offsetof(struct mxc_ccm_reg, cimr));
++ DEFINE(CCM_CCOSR, offsetof(struct mxc_ccm_reg, ccosr));
++ DEFINE(CCM_CGPR, offsetof(struct mxc_ccm_reg, cgpr));
++ DEFINE(CCM_CCGR0, offsetof(struct mxc_ccm_reg, CCGR0));
++ DEFINE(CCM_CCGR1, offsetof(struct mxc_ccm_reg, CCGR1));
++ DEFINE(CCM_CCGR2, offsetof(struct mxc_ccm_reg, CCGR2));
++ DEFINE(CCM_CCGR3, offsetof(struct mxc_ccm_reg, CCGR3));
++ DEFINE(CCM_CCGR4, offsetof(struct mxc_ccm_reg, CCGR4));
++ DEFINE(CCM_CCGR5, offsetof(struct mxc_ccm_reg, CCGR5));
++ DEFINE(CCM_CCGR6, offsetof(struct mxc_ccm_reg, CCGR6));
++ DEFINE(CCM_CCGR7, offsetof(struct mxc_ccm_reg, CCGR7));
++ DEFINE(CCM_CMEOR, offsetof(struct mxc_ccm_reg, cmeor));
+
++ DEFINE(ANATOP_PLL_ENET, offsetof(struct anatop_regs, pll_enet));
++#endif
+ return 0;
+}
/* for now: just dummy functions to satisfy the linker */
#include <common.h>
+#include <malloc.h>
-void __flush_cache(unsigned long start, unsigned long size)
+__weak void flush_cache(unsigned long start, unsigned long size)
{
-#if defined(CONFIG_ARM1136)
- void arm1136_cache_flush(void);
+#if defined(CONFIG_CPU_ARM1136)
- arm1136_cache_flush();
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+ asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
#endif
- #ifdef CONFIG_CPU_ARM926EJS
- /* test and clean, page 2-23 of arm926ejs manual */
- asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- /* disable write buffer as well (page 2-22) */
- asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
- #endif /* CONFIG_CPU_ARM926EJS */
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
+#endif
+
+#endif /* CONFIG_CPU_ARM1136 */
+
+ #ifdef CONFIG_ARM926EJS
+ asm(
+ /* test and clean, page 2-23 of arm926ejs manual */
+ "0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n"
+ /* flush write buffer as well (page 2-22) */
+ "mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory"
+ );
+ #endif
return;
}
-void flush_cache(unsigned long start, unsigned long size)
- __attribute__((weak, alias("__flush_cache")));
/*
* Default implementation:
*/
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
- ldr sp, =(CONFIG_SPL_STACK)
+ ldr sp, =CONFIG_SPL_STACK
#else
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ ldr sp, =CONFIG_SYS_INIT_SP_ADDR
#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- sub sp, #GD_SIZE /* allocate one GD above SP */
+ mov r2, sp
+ sub sp, sp, #GD_SIZE /* allocate one GD above SP */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- mov r8, sp /* GD is above SP */
+ mov r9, sp /* GD is above SP */
+ mov r1, sp
mov r0, #0
+clr_gd:
+ cmp r1, r2 /* while not at end of GD */
+ strlo r0, [r1] /* clear 32-bit GD word */
+ addlo r1, r1, #4 /* move to next */
+ blo clr_gd
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ sub sp, sp, #CONFIG_SYS_MALLOC_F_LEN
+ str sp, [r9, #GD_MALLOC_BASE]
+#endif
+ /* mov r0, #0 not needed due to above code */
bl board_init_f
#if ! defined(CONFIG_SPL_BUILD)
void do_data_abort (struct pt_regs *pt_regs)
{
- unsigned long fsr;
-
- /* Read Fault Status Register */
- asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r"(fsr));
-
- printf ("data abort\n\n");
- if (fsr & 1)
- printf ("MAYBE you should read doc/README.arm-unaligned-accesses\n\n");
+ printf ("data abort\n");
+ fixup_pc(pt_regs, -8);
show_regs (pt_regs);
bad_mode ();
}
udelay (50000); /* wait 50 ms */
disable_interrupts();
+
+ reset_misc();
reset_cpu(0);
-
- /*NOTREACHED*/
- return 0;
+ hang();
}
--- /dev/null
+/*
+ * vectors - Generic ARM exception table code
+ *
+ * Copyright (c) 1998 Dan Malek <dmalek@jlc.net>
+ * Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (c) 2000 Wolfgang Denk <wd@denx.de>
+ * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/*
+ *************************************************************************
+ *
+ * Symbol _start is referenced elsewhere, so make it global
+ *
+ *************************************************************************
+ */
+
+.globl _start
+
+/*
+ *************************************************************************
+ *
+ * Vectors have their own section so linker script can map them easily
+ *
+ *************************************************************************
+ */
+
+ .section ".vectors", "ax"
+
+/*
+ *************************************************************************
+ *
+ * Exception vectors as described in ARM reference manuals
+ *
+ * Uses indirect branch to allow reaching handlers anywhere in memory.
+ *
+ *************************************************************************
+ */
+
+_start:
+
+#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
+ .word CONFIG_SYS_DV_NOR_BOOT_CFG
+#endif
+
+ b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+/*
+ *************************************************************************
+ *
+ * Indirect vectors table
+ *
+ * Symbols referenced here must be defined somewhere else
+ *
+ *************************************************************************
+ */
+
+ .globl _undefined_instruction
+ .globl _software_interrupt
+ .globl _prefetch_abort
+ .globl _data_abort
+ .globl _not_used
+ .globl _irq
+ .globl _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort: .word data_abort
+_not_used: .word not_used
+_irq: .word irq
+_fiq: .word fiq
+
+ .balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+/* SPL interrupt handling: just hang */
+
+#ifdef CONFIG_SPL_BUILD
+
+ .align 5
+undefined_instruction:
+software_interrupt:
+prefetch_abort:
+data_abort:
+not_used:
+irq:
+fiq:
+
+1:
+ bl 1b /* hang and never return */
+
+#else /* !CONFIG_SPL_BUILD */
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
++#ifndef IRAM_BASE_ADDR
+ .word 0x0badc0de
++#else
++ .word IRAM_BASE_ADDR + 0x20
++#endif
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+
+#endif /* CONFIG_USE_IRQ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ @ carve out a frame on current user stack
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
+ ldr r2, IRQ_STACK_START_IN
+ @ get values for "aborted" pc and cpsr (into parm regs)
+ ldmia r2, {r2 - r3}
+ add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp @ save current stack into r0 (param register)
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, IRQ_STACK_START_IN @ setup our mode stack
+
+ str lr, [r13] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r13, #4] @ save spsr in position 1 of saved stack
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13 @ switch modes, make sure moves will execute
+ mov lr, pc @ capture return pc
+ movs pc, lr @ jump to next instruction & switch modes.
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif /* CONFIG_USE_IRQ */
+
+#endif /* CONFIG_SPL_BUILD */
}
};
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO_7_0, /* CD */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++ MX6_PAD_SD3_DAT5__GPIO7_IO00, /* CD */
};
-iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++ MX6_PAD_NANDF_D6__GPIO2_IO06, /* CD */
};
-iomux_v3_cfg_t const enet_pads1[] = {
+static iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
- MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_RXC__GPIO_6_30,
++ MX6_PAD_RGMII_RXC__GPIO6_IO30,
/* pin 32 - 1 - (MODE0) all */
- MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_RD0__GPIO_6_25,
++ MX6_PAD_RGMII_RD0__GPIO6_IO25,
/* pin 31 - 1 - (MODE1) all */
- MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_RD1__GPIO_6_27,
++ MX6_PAD_RGMII_RD1__GPIO6_IO27,
/* pin 28 - 1 - (MODE2) all */
- MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_RD2__GPIO_6_28,
++ MX6_PAD_RGMII_RD2__GPIO6_IO28,
/* pin 27 - 1 - (MODE3) all */
- MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_RD3__GPIO_6_29,
++ MX6_PAD_RGMII_RD3__GPIO6_IO29,
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__GPIO_6_24,
++ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24,
/* pin 42 PHY nRST */
- MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D23__GPIO_3_23,
- MX6_PAD_ENET_RXD0__GPIO_1_27,
++ MX6_PAD_EIM_D23__GPIO3_IO23,
++ MX6_PAD_ENET_RXD0__GPIO1_IO27,
};
-iomux_v3_cfg_t const enet_pads2[] = {
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+static iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ udelay(100); /* Wait 100 us before using mii interface */
}
-iomux_v3_cfg_t const usb_pads[] = {
- MX6_PAD_GPIO_17__GPIO_7_12,
+static iomux_v3_cfg_t const usb_pads[] = {
- MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_GPIO_17__GPIO7_IO12,
};
static void setup_iomux_uart(void)
#endif
#ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t const ecspi1_pads[] = {
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
++ MX6_PAD_EIM_D19__GPIO3_IO19,
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight on RGB connector: J15 */
- MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD1_DAT3__GPIO_1_21,
++ MX6_PAD_SD1_DAT3__GPIO1_IO21,
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
/* Backlight on LVDS connector: J6 */
- MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD1_CMD__GPIO_1_18,
++ MX6_PAD_SD1_CMD__GPIO1_IO18,
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
};
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++ MX6_PAD_NANDF_D6__GPIO2_IO06, /* CD */
};
static void setup_iomux_uart(void)
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
};
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
{
- mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
}
+
+ static uint32_t dram_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
+ 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
+ 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+ 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
+ 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
+ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
+ 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
+ 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
+ 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
+ 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
+ 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
+ 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+ };
+
+ void mx28_ddr2_setup(void)
+ {
+ int i;
+
+ serial_puts("\n");
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ }
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS0__GPIO_6_11, /* CD */
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++ MX6_PAD_NANDF_CS0__GPIO6_IO11, /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
return 0;
}
- MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
++ MX6_PAD_EIM_D22__USB_OTG_PWR,
++ MX6_PAD_GPIO_1__USB_OTG_ID,
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 1);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 0)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
int board_early_init_f(void)
{
setup_iomux_uart();
.gp = IMX_GPIO_NR(3, 18)
}
};
- MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#endif
+
+static iomux_v3_cfg_t const i2c3_pads[] = {
++ MX6_PAD_EIM_A24__GPIO5_IO04,
+};
-iomux_v3_cfg_t const i2c3_pads[] = {
- MX6_PAD_EIM_A24__GPIO_5_4,
+static iomux_v3_cfg_t const port_exp[] = {
- MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_SD2_DAT0__GPIO1_IO15,
};
-iomux_v3_cfg_t const port_exp[] = {
- MX6_PAD_SD2_DAT0__GPIO_1_15,
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
+ MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_EIM_OE__EIM_OE_B,
++ MX6_PAD_EIM_RW__EIM_RW,
++ MX6_PAD_EIM_CS0__EIM_CS0_B,
};
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(0x00020181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0a020000, &weim_regs->cs0rcr1);
+ writel(0x0000c000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000120, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void setup_iomux_eimnor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
+
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+ eimnor_cs_setup();
+}
+
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS2__GPIO_6_15,
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_NANDF_CS2__GPIO6_IO15,
};
static void setup_iomux_uart(void)
return 0;
}
- MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
+#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
++ MX6_PAD_ENET_RX_ER__USB_OTG_ID,
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * Set daisy chain for otg_pin_id on 6q.
+ * For 6dl, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+ break;
+ case 1:
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ if (on)
+ port_exp_direction_output(USB_OTG_PWR, 1);
+ else
+ port_exp_direction_output(USB_OTG_PWR, 0);
+ break;
+ case 1:
+ if (on)
+ port_exp_direction_output(USB_HOST1_PWR, 1);
+ else
+ port_exp_direction_output(USB_HOST1_PWR, 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
--- /dev/null
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+ /*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ #include <common.h>
+ #include <asm/io.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/iomux.h>
+ #include <asm/arch/mx6q_pins.h>
+ #include <asm/errno.h>
+ #include <asm/gpio.h>
+ #include <asm/imx-common/iomux-v3.h>
+ #include <asm/imx-common/mxc_i2c.h>
+ #include <asm/imx-common/boot_mode.h>
+ #include <mmc.h>
+ #include <fsl_esdhc.h>
+ #include <malloc.h>
+ #include <micrel.h>
+ #include <miiphy.h>
+ #include <netdev.h>
+ #include <linux/fb.h>
+ #include <ipu_pixfmt.h>
+ #include <asm/arch/crm_regs.h>
+ #include <asm/arch/mxc_hdmi.h>
+ #include <i2c.h>
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+ #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+ #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+ #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+ #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+ #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+ int dram_init(void)
+ {
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+ }
+
+ iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+
+ iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+
+ #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+ /* I2C1, SGTL5000 */
+ struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+ };
+
+ /* I2C2 Camera, MIPI */
+ struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+ };
+
+ /* I2C3, J15 - RGB connector */
+ struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+ };
+
+ iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO_7_0, /* CD */
+ };
+
+ iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */
+ };
+
+ iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ MX6_PAD_RGMII_RXC__GPIO_6_30,
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO_6_25,
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO_6_27,
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO_6_28,
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO_6_29,
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24,
+ /* pin 42 PHY nRST */
+ MX6_PAD_EIM_D23__GPIO_3_23,
+ };
+
+ iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ };
+
+ /* Button assignments for J14 */
+ static iomux_v3_cfg_t const button_pads[] = {
+ /* Menu */
+ MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Back */
+ MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Labelled Search (mapped to Power under Android) */
+ MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Home */
+ MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Down */
+ MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Up */
+ MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ };
+
+ static void setup_iomux_enet(void)
+ {
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+ gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+ /* Need delay 10ms according to KSZ9021 spec */
+ udelay(1000 * 10);
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ }
+
+ iomux_v3_cfg_t const usb_pads[] = {
+ MX6_PAD_GPIO_17__GPIO_7_12,
+ };
+
+ static void setup_iomux_uart(void)
+ {
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ }
+
+ #ifdef CONFIG_USB_EHCI_MX6
+ int board_ehci_hcd_init(int port)
+ {
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+ /* Reset USB hub */
+ gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(7, 12), 1);
+
+ return 0;
+ }
+ #endif
+
+ #ifdef CONFIG_FSL_ESDHC
+ struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+ };
+
+ int board_mmc_getcd(struct mmc *mmc)
+ {
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+ gpio_direction_input(IMX_GPIO_NR(7, 0));
+ ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
+ } else {
+ gpio_direction_input(IMX_GPIO_NR(2, 6));
+ ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
+ }
+
+ return ret;
+ }
+
+ int board_mmc_init(bd_t *bis)
+ {
+ s32 status = 0;
+ u32 index = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].max_bus_width = 4;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ }
+
+ return status;
+ }
+ #endif
+
+ #ifdef CONFIG_MXC_SPI
+ iomux_v3_cfg_t const ecspi1_pads[] = {
+ /* SS1 */
+ MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ };
+
+ void setup_spi(void)
+ {
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ ARRAY_SIZE(ecspi1_pads));
+ }
+ #endif
+
+ int board_phy_config(struct phy_device *phydev)
+ {
+ /* min rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+ /* min tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+ /* max rx/tx clock delay, min rx/tx control */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+ }
+
+ int board_eth_init(bd_t *bis)
+ {
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+
+ #ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ /* scan phy 4,5,6,7 */
+ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ free(bus);
+ return 0;
+ }
+ printf("using phy at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+ #endif
+ return 0;
+ }
+
+ static void setup_buttons(void)
+ {
+ imx_iomux_v3_setup_multiple_pads(button_pads,
+ ARRAY_SIZE(button_pads));
+ }
+
+ #ifdef CONFIG_CMD_SATA
+
+ int setup_sata(void)
+ {
++ struct iomuxc *const iomuxc_regs = (void *)IOMUXC_BASE_ADDR;
+ int ret = enable_sata_clock();
++
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(&iomuxc_regs->gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+ }
+ #endif
+
+ #if defined(CONFIG_VIDEO_IPUV3)
+
+ static iomux_v3_cfg_t const backlight_pads[] = {
+ /* Backlight on RGB connector: J15 */
+ MX6_PAD_SD1_DAT3__GPIO_1_21,
+ #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
+
+ /* Backlight on LVDS connector: J6 */
+ MX6_PAD_SD1_CMD__GPIO_1_18,
+ #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
+ };
+
+ static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+ MX6_PAD_DI0_PIN4__GPIO_4_20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ };
+
+ struct display_info_t {
+ int bus;
+ int addr;
+ int pixfmt;
+ int (*detect)(struct display_info_t const *dev);
+ void (*enable)(struct display_info_t const *dev);
+ struct fb_videomode mode;
+ };
+
+
+ static int detect_hdmi(struct display_info_t const *dev)
+ {
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
+ }
+
+ static void enable_hdmi(struct display_info_t const *dev)
+ {
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ u8 reg;
+ printf("%s: setup HDMI monitor\n", __func__);
+ reg = readb(&hdmi->phy_conf0);
+ reg |= HDMI_PHY_CONF0_PDZ_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+ }
+
+ static int detect_i2c(struct display_info_t const *dev)
+ {
+ return ((0 == i2c_set_bus_num(dev->bus))
+ &&
+ (0 == i2c_probe(dev->addr)));
+ }
+
+ static void enable_lvds(struct display_info_t const *dev)
+ {
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+ writel(reg, &iomux->gpr[2]);
+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+ }
+
+ static void enable_rgb(struct display_info_t const *dev)
+ {
+ imx_iomux_v3_setup_multiple_pads(
+ rgb_pads,
+ ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+ }
+
+ static struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ } }, {
+ .bus = 2,
+ .addr = 0x4,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ } }, {
+ .bus = 2,
+ .addr = 0x38,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "wsvga-lvds",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ } }, {
+ .bus = 2,
+ .addr = 0x48,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = detect_i2c,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "wvga-rgb",
+ .refresh = 57,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 37037,
+ .left_margin = 40,
+ .right_margin = 60,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+ } } };
+
+ int board_video_skip(void)
+ {
+ int i;
+ int ret;
+ char const *panel = getenv("panel");
+ if (!panel) {
+ for (i = 0; i < ARRAY_SIZE(displays); i++) {
+ struct display_info_t const *dev = displays+i;
+ if (dev->detect(dev)) {
+ panel = dev->mode.name;
+ printf("auto-detected panel %s\n", panel);
+ break;
+ }
+ }
+ if (!panel) {
+ panel = displays[0].mode.name;
+ printf("No panel detected: default to %s\n", panel);
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(displays); i++) {
+ if (!strcmp(panel, displays[i].mode.name))
+ break;
+ }
+ }
+ if (i < ARRAY_SIZE(displays)) {
+ ret = ipuv3_fb_init(&displays[i].mode, 0,
+ displays[i].pixfmt);
+ if (!ret) {
+ displays[i].enable(displays+i);
+ printf("Display: %s (%ux%u)\n",
+ displays[i].mode.name,
+ displays[i].mode.xres,
+ displays[i].mode.yres);
+ } else
+ printf("LCD %s cannot be configured: %d\n",
+ displays[i].mode.name, ret);
+ } else {
+ printf("unsupported panel %s\n", panel);
+ ret = -EINVAL;
+ }
+ return (0 != ret);
+ }
+
+ static void setup_display(void)
+ {
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+
+ int reg;
+
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
+ |MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* Turn on HDMI PHY clock */
+ reg = __raw_readl(&mxc_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
+ |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+ writel(reg, &mxc_ccm->CCGR2);
+
+ /* clear HDMI PHY reset */
+ writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+
+ /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
+ writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
+ writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
+ |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
+ |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+ |(CHSCCDR_PODF_DIVIDE_BY_3
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+ |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ /* backlights off until needed */
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+ gpio_direction_input(LVDS_BACKLIGHT_GP);
+ gpio_direction_input(RGB_BACKLIGHT_GP);
+ }
+ #endif
+
+ int board_early_init_f(void)
+ {
+ setup_iomux_uart();
+ setup_buttons();
+
+ #if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+ #endif
+ return 0;
+ }
+
+ /*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+ int overwrite_console(void)
+ {
+ return 1;
+ }
+
+ int board_init(void)
+ {
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ #ifdef CONFIG_MXC_SPI
+ setup_spi();
+ #endif
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+ #ifdef CONFIG_CMD_SATA
+ setup_sata();
+ #endif
+
+ return 0;
+ }
+
+ int checkboard(void)
+ {
+ puts("Board: MX6Q-Sabre Lite\n");
+
+ return 0;
+ }
+
+ struct button_key {
+ char const *name;
+ unsigned gpnum;
+ char ident;
+ };
+
+ static struct button_key const buttons[] = {
+ {"back", IMX_GPIO_NR(2, 2), 'B'},
+ {"home", IMX_GPIO_NR(2, 4), 'H'},
+ {"menu", IMX_GPIO_NR(2, 1), 'M'},
+ {"search", IMX_GPIO_NR(2, 3), 'S'},
+ {"volup", IMX_GPIO_NR(7, 13), 'V'},
+ {"voldown", IMX_GPIO_NR(4, 5), 'v'},
+ };
+
+ /*
+ * generate a null-terminated string containing the buttons pressed
+ * returns number of keys pressed
+ */
+ static int read_keys(char *buf)
+ {
+ int i, numpressed = 0;
+ for (i = 0; i < ARRAY_SIZE(buttons); i++) {
+ if (!gpio_get_value(buttons[i].gpnum))
+ buf[numpressed++] = buttons[i].ident;
+ }
+ buf[numpressed] = '\0';
+ return numpressed;
+ }
+
+ static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ char envvalue[ARRAY_SIZE(buttons)+1];
+ int numpressed = read_keys(envvalue);
+ setenv("keybd", envvalue);
+ return numpressed == 0;
+ }
+
+ U_BOOT_CMD(
+ kbd, 1, 1, do_kbd,
+ "Tests for keypresses, sets 'keybd' environment variable",
+ "Returns 0 (true) to shell if key is pressed."
+ );
+
+ #ifdef CONFIG_PREBOOT
+ static char const kbd_magic_prefix[] = "key_magic";
+ static char const kbd_command_prefix[] = "key_cmd";
+
+ static void preboot_keys(void)
+ {
+ int numpressed;
+ char keypress[ARRAY_SIZE(buttons)+1];
+ numpressed = read_keys(keypress);
+ if (numpressed) {
+ char *kbd_magic_keys = getenv("magic_keys");
+ char *suffix;
+ /*
+ * loop over all magic keys
+ */
+ for (suffix = kbd_magic_keys; *suffix; ++suffix) {
+ char *keys;
+ char magic[sizeof(kbd_magic_prefix) + 1];
+ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+ keys = getenv(magic);
+ if (keys) {
+ if (!strcmp(keys, keypress))
+ break;
+ }
+ }
+ if (*suffix) {
+ char cmd_name[sizeof(kbd_command_prefix) + 1];
+ char *cmd;
+ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv(cmd_name);
+ if (cmd) {
+ setenv("preboot", cmd);
+ return;
+ }
+ }
+ }
+ }
+ #endif
+
+ #ifdef CONFIG_CMD_BMODE
+ static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+ };
+ #endif
+
+ int misc_init_r(void)
+ {
+ #ifdef CONFIG_PREBOOT
+ preboot_keys();
+ #endif
+
+ #ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+ #endif
+ return 0;
+ }
return 0;
}
-iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-iomux_v3_cfg_t const enet_pads[] = {
+static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
- MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_ENET_CRS_DV__GPIO_1_25,
++ MX6_PAD_ENET_CRS_DV__GPIO1_IO25,
};
static void setup_iomux_enet(void)
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
-iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D2__GPIO_2_2, /* CD */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++ MX6_PAD_NANDF_D2__GPIO2_IO02, /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++ MX6_PAD_NANDF_D0__GPIO2_IO00, /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D0__GPIO_2_0, /* CD */
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_KEY_ROW1__GPIO4_IO09,
};
-iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+static iomux_v3_cfg_t const rgb_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
++ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
++ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
++ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
++ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04,
++ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
++ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
++ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
++ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
++ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
++ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
++ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
++ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
++ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
++ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
++ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
++ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
++ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
++ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
++ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
++ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
++ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
++ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
++ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
++ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
++ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
++ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
++ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
++ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
++ MX6_PAD_SD1_DAT3__GPIO1_IO21,
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+iomux_v3_cfg_t const pcie_pads[] = {
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
- MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
++ MX6_PAD_EIM_D19__GPIO3_IO19, /* POWER */
++ MX6_PAD_GPIO_17__GPIO7_IO12, /* RESET */
+};
+
+static void setup_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+iomux_v3_cfg_t const di0_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
};
static void setup_iomux_uart(void)
return 0;
}
-int board_eth_init(bd_t *bis)
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
{
- int ret;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ int reg = readl(&iomux->gpr[2]);
+
+ reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+
+ writel(reg, &iomux->gpr[2]);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ disable_lvds(dev);
+ imx_enable_hdmi_phy();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
+ writel(reg, &iomux->gpr[2]);
+}
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "SEIKO-WVGA",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29850,
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+ imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
+ | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
+ | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
setup_iomux_enet();
+ setup_pcie();
+
+ return cpu_eth_init(bis);
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
- ret = cpu_eth_init(bis);
- if (ret)
- printf("FEC MXC: %s:failed\n", __func__);
+static iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_EIM_D22__USB_OTG_PWR,
++ MX6_PAD_ENET_RX_ER__USB_OTG_ID,
+};
+
+static iomux_v3_cfg_t const usb_hc1_pads[] = {
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_ENET_TXD1__GPIO1_IO29,
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+
+ imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+ ARRAY_SIZE(usb_hc1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ break;
+ case 1:
+ if (on)
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+ else
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
return 0;
}
--- /dev/null
-# (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ #
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
++# (C) Copyright 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
+ #
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB = $(obj)lib$(VENDOR).o
-
++# SPDX-License-Identifier: GPL-2.0+
+ #
+
- COBJS-$(CONFIG_OF_BOARD_SETUP) += fdt.o
- COBJS-$(CONFIG_SPLASH_SCREEN) += splashimage.o
+ ifeq ($(CONFIG_SPL_BUILD),)
-COBJS-$(CONFIG_CMD_NAND) += nand.o
-COBJS-$(CONFIG_ENV_IS_IN_MMC) += mmc.o
-COBJS-y += env.o
-COBJS := $(COBJS-y)
-SOBJS :=
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-all: $(LIB)
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
++ obj-$(CONFIG_OF_LIBFDT) += fdt.o
++ obj-$(CONFIG_SPLASH_SCREEN) += splashimage.o
+ endif
++obj-$(CONFIG_CMD_NAND) += nand.o
++obj-$(CONFIG_ENV_IS_IN_MMC) += mmc.o
++obj-y += env.o
--- /dev/null
+ /*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+ struct fb_videomode;
+
+ #ifdef CONFIG_SYS_LVDS_IF
+ #define is_lvds() 1
+ #else
+ #define is_lvds() 0
+ #endif
+
+ void env_cleanup(void);
+
+ #ifdef CONFIG_OF_LIBFDT
+ void karo_fdt_remove_node(void *blob, const char *node);
+ void karo_fdt_move_fdt(void);
+ void karo_fdt_fixup_touchpanel(void *blob, const char *panels[],
+ size_t num_panels);
+ void karo_fdt_fixup_usb_otg(void *blob, const char *node, const char *phy,
+ const char *phy_supply);
+ void karo_fdt_fixup_flexcan(void *blob, int xcvr_present);
+ void karo_fdt_del_prop(void *blob, const char *compat, u32 offs,
+ const char *prop);
+ void karo_fdt_enable_node(void *blob, const char *node, int enable);
+ int karo_fdt_get_fb_mode(void *blob, const char *name,
+ struct fb_videomode *fb_mode);
+ int karo_fdt_update_fb_mode(void *blob, const char *name);
+ int karo_fdt_create_fb_mode(void *blob, const char *name,
+ struct fb_videomode *mode);
+ int karo_fdt_get_backlight_polarity(const void *blob);
+ #else
+ static inline void karo_fdt_remove_node(void *blob, const char *node)
+ {
+ }
+ static inline void karo_fdt_move_fdt(void)
+ {
+ }
+ static inline void karo_fdt_fixup_touchpanel(void *blob, const char *panels[],
+ size_t num_panels)
+ {
+ }
+ static inline void karo_fdt_fixup_usb_otg(void *blob, const char *node,
+ const char *phy,
+ const char *phy_supply)
+ {
+ }
+ static inline void karo_fdt_fixup_flexcan(void *blob, int xcvr_present)
+ {
+ }
+ static inline void karo_fdt_del_prop(void *blob, const char *compat,
+ u32 offs, const char *prop)
+ {
+ }
+ static inline void karo_fdt_enable_node(void *blob, const char *node,
+ int enable)
+ {
+ }
+ static inline int karo_fdt_get_fb_mode(void *blob, const char *name,
+ struct fb_videomode *fb_mode)
+ {
+ return 0;
+ }
+ static inline int karo_fdt_update_fb_mode(void *blob, const char *name)
+ {
+ return 0;
+ }
+ static inline int karo_fdt_create_fb_mode(void *blob,
+ const char *name,
+ struct fb_videomode *mode)
+ {
+ return 0;
+ }
+ static inline int karo_fdt_get_backlight_polarity(const void *blob)
+ {
+ return getenv_yesno("backlight_polarity");
+ }
+ #endif
+
+ #if defined(CONFIG_SYS_LVDS_IF) && defined(CONFIG_OF_LIBFDT)
+ int karo_fdt_get_lcd_bus_width(const void *blob, int default_width);
+ int karo_fdt_get_lvds_mapping(const void *blob, int default_mapping);
+ u8 karo_fdt_get_lvds_channels(const void *blob);
+ #else
+ static inline int karo_fdt_get_lcd_bus_width(const void *blob, int default_width)
+ {
+ return default_width;
+ }
+ static inline int karo_fdt_get_lvds_mapping(const void *blob, int default_mapping)
+ {
+ return default_mapping;
+ }
+ static inline u8 karo_fdt_get_lvds_channels(const void *blob)
+ {
+ return 0;
+ }
+ #endif
+
+ static inline const char *karo_get_vmode(const char *video_mode)
+ {
+ const char *vmode = NULL;
+
+ if (video_mode == NULL || strlen(video_mode) == 0)
+ return NULL;
+
+ vmode = strchr(video_mode, ':');
+ return vmode ? vmode + 1 : video_mode;
+ }
+
+ #ifdef CONFIG_SPLASH_SCREEN
+ int karo_load_splashimage(int mode);
+ #else
+ static inline int karo_load_splashimage(int mode)
+ {
+ return 0;
+ }
+ #endif
+
+ #ifdef CONFIG_CMD_NAND
+ int karo_load_nand_part(const char *part, void *addr, size_t len);
+ #else
+ static inline int karo_load_nand_part(const char *part, void *addr, size_t len)
+ {
+ return -EOPNOTSUPP;
+ }
+ #endif
+
+ #ifdef CONFIG_ENV_IS_IN_MMC
+ int karo_load_mmc_part(const char *part, void *addr, size_t len);
+ #else
+ static inline int karo_load_mmc_part(const char *part, void *addr, size_t len)
+ {
+ return -EOPNOTSUPP;
+ }
+ #endif
+
+ static inline int karo_load_part(const char *part, void *addr, size_t len)
+ {
+ int ret;
+
+ ret = karo_load_nand_part(part, addr, len);
+ if (ret == -EOPNOTSUPP)
+ return karo_load_mmc_part(part, addr, len);
+ return ret;
+ }
++
++#define DIV_ROUND(n, d) (((n) + (d) / 2) / (d))
--- /dev/null
- int len_read;
-
- printf("Reading file %s from mmc partition %d\n", part, 0);
- len_read = fs_read(part, (ulong)addr, 0, len);
+ /*
+ * (C) Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <libfdt.h>
+ #include <fdt_support.h>
+ #include <mmc.h>
+ #include <mxcfb.h>
+ #include <fs.h>
+ #include <fat.h>
+ #include <malloc.h>
+ #include <linux/list.h>
+ #include <linux/fb.h>
+ #include <jffs2/load_kernel.h>
+
+ #include "karo.h"
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define MAX_SEARCH_PARTITIONS 16
+
+ static int find_partitions(const char *ifname, int devno, int fstype,
+ block_dev_desc_t **dev_desc, disk_partition_t *info)
+ {
+ int ret = -1;
+ char *dup_str = NULL;
+ int p;
+ int part;
+ block_dev_desc_t *dd;
+
+ dd = get_dev(ifname, devno);
+ if (!dd || dd->type == DEV_TYPE_UNKNOWN) {
+ printf("** Bad device %s %d **\n", ifname, devno);
+ return -1;
+ }
+ init_part(dd);
+
+ /*
+ * No partition table on device,
+ * or user requested partition 0 (entire device).
+ */
+ if (dd->part_type == PART_TYPE_UNKNOWN) {
+ printf("** No partition table on device %s %d **\n",
+ ifname, devno);
+ goto cleanup;
+ }
+
+ part = 0;
+ for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
+ ret = get_partition_info(dd, p, info);
+ if (ret)
+ continue;
+
+ if (fat_register_device(dd, p) == 0) {
+ part = p;
+ dd->log2blksz = LOG2(dd->blksz);
+ break;
+ }
+ }
+ if (!part) {
+ printf("** No valid partition on device %s %d **\n",
+ ifname, devno);
+ ret = -1;
+ goto cleanup;
+ }
+
+ ret = part;
+ *dev_desc = dd;
+
+ cleanup:
+ free(dup_str);
+ return ret;
+ }
+
+ static int karo_mmc_find_part(struct mmc *mmc, const char *part, int devno,
+ disk_partition_t *part_info)
+ {
+ int ret;
+ block_dev_desc_t *mmc_dev;
+
+ #if defined(CONFIG_SYS_DTB_OFFSET) && defined(CONFIG_SYS_MMC_ENV_PART)
+ if (strcmp(part, "dtb") == 0) {
+ const int partnum = CONFIG_SYS_MMC_ENV_PART;
+
+ part_info->blksz = mmc->read_bl_len;
+ part_info->start = CONFIG_SYS_DTB_OFFSET / part_info->blksz;
+ part_info->size = CONFIG_SYS_DTB_PART_SIZE / part_info->blksz;
+ printf("Using virtual partition %s(%d) ["LBAF".."LBAF"]\n",
+ part, partnum, part_info->start,
+ part_info->start + part_info->size - 1);
+ return partnum;
+ }
+ #endif
+ ret = find_partitions("mmc", devno, FS_TYPE_FAT, &mmc_dev, part_info);
+ if (ret < 0) {
+ printf("No (e)MMC partition found: %d\n", ret);
+ return ret;
+ }
+ return 0;
+ }
+
+ int karo_load_mmc_part(const char *part, void *addr, size_t len)
+ {
+ int ret;
+ struct mmc *mmc;
+ disk_partition_t part_info;
+ int devno = CONFIG_SYS_MMC_ENV_DEV;
+ lbaint_t blk_cnt;
+ int partnum;
+
+ mmc = find_mmc_device(devno);
+ if (!mmc) {
+ printf("Failed to find mmc%u\n", devno);
+ return -ENODEV;
+ }
+
+ if (mmc_init(mmc)) {
+ printf("Failed to init MMC device %d\n", devno);
+ return -EIO;
+ }
+
+ blk_cnt = DIV_ROUND_UP(len, mmc->read_bl_len);
+
+ partnum = karo_mmc_find_part(mmc, part, devno, &part_info);
+ if (partnum > 0) {
+ if (part_info.start + blk_cnt < part_info.start) {
+ printf("%s: given length 0x%08x exceeds size of partition\n",
+ __func__, len);
+ return -EINVAL;
+ }
+ if (part_info.start + blk_cnt > mmc->block_dev.lba)
+ blk_cnt = mmc->block_dev.lba - part_info.start;
+
+ mmc_switch_part(devno, partnum);
+
+ memset(addr, 0xee, len);
+
+ debug("Reading 0x"LBAF" blks from MMC partition %d offset 0x"LBAF" to %p\n",
+ blk_cnt, partnum, part_info.start, addr);
+ ret = mmc->block_dev.block_read(devno, part_info.start, blk_cnt, addr);
+ if (ret == 0) {
+ printf("Failed to read MMC partition %s\n", part);
+ ret = -EIO;
+ goto out;
+ }
+ debug("Read %u (%u) byte from partition '%s' @ offset 0x"LBAF"\n",
+ ret * mmc->read_bl_len, len, part, part_info.start);
+ } else if (partnum == 0) {
- printf("Read only %u of %u bytes\n", len_read, len);
++ loff_t len_read;
++
++ debug("Reading file %s from mmc partition %d\n", part,
++ partnum);
++ ret = fs_read(part, (ulong)addr, 0, len, &len_read);
++ if (ret < 0) {
++ printf("Failed to read %u byte from mmc partition %d\n",
++ len, partnum);
++ goto out;
++ }
+ if (len_read < len) {
++ printf("Read only %llu of %u bytes\n", (u64)len_read, len);
+ }
+ } else {
+ ret = partnum;
+ goto out;
+ }
+ ret = 0;
+ out:
+ if (partnum > 0)
+ mmc_switch_part(devno, 0);
+ return ret < 0 ? ret : 0;
+ }
--- /dev/null
- debug("Found partition '%s': offset=%08x size=%08x\n",
- part, part_info->offset, part_info->size);
+ /*
+ * (C) Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <libfdt.h>
+ #include <fdt_support.h>
+ #include <nand.h>
+ #include <mxcfb.h>
+ #include <linux/list.h>
+ #include <linux/fb.h>
+ #include <jffs2/load_kernel.h>
+ #include <malloc.h>
+
+ #include "karo.h"
+
+ #ifdef CONFIG_MAX_DTB_SIZE
+ #define MAX_DTB_SIZE CONFIG_MAX_DTB_SIZE
+ #else
+ #define MAX_DTB_SIZE SZ_64K
+ #endif
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int karo_load_nand_part(const char *part, void *addr, size_t len)
+ {
+ int ret;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ u8 part_num;
+
+ debug("Initializing mtd_parts\n");
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ debug("Trying to find NAND partition '%s'\n", part);
+ ret = find_dev_and_part(part, &dev, &part_num, &part_info);
+ if (ret) {
+ printf("Failed to find flash partition '%s': %d\n",
+ part, ret);
+
+ return ret;
+ }
- debug("Read %u byte from partition '%s' @ offset %08x\n",
- len, part, part_info->offset);
++ debug("Found partition '%s': offset=%08llx size=%08llx\n",
++ part, (u64)part_info->offset, (u64)part_info->size);
+
+ if (part_info->size < len)
+ len = part_info->size;
+
+ debug("Reading NAND partition '%s' to %p\n", part, addr);
+ ret = nand_read_skip_bad(&nand_info[0], part_info->offset, &len,
+ NULL, part_info->size, addr);
+ if (ret) {
+ printf("Failed to load partition '%s' to %p\n", part, addr);
+ return ret;
+ }
+
++ debug("Read %u byte from partition '%s' @ offset %08llx\n",
++ len, part, (u64)part_info->offset);
+ return 0;
+ }
+
+ #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MTDPARTS)
+ static int erase_flash(loff_t offs, size_t len)
+ {
+ nand_erase_options_t nand_erase_options;
+
+ memset(&nand_erase_options, 0, sizeof(nand_erase_options));
+ nand_erase_options.length = len;
+ nand_erase_options.offset = offs;
+
+ return nand_erase_opts(&nand_info[0], &nand_erase_options);
+ }
+
+ int do_fbdump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int ret;
+ size_t fbsize = calc_fbsize();
+ const char *part = "logo";
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ u8 part_num;
+ u_char *addr = (u_char *)gd->fb_base;
+
+ if (argc > 2)
+ return CMD_RET_USAGE;
+
+ if (argc == 2)
+ part = argv[1];
+
+ if (!addr) {
+ printf("fb address unknown\n");
+ return CMD_RET_FAILURE;
+ }
+
+ debug("Initializing mtd_parts\n");
+ ret = mtdparts_init();
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ debug("Trying to find NAND partition '%s'\n", part);
+ ret = find_dev_and_part(part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find flash partition '%s': %d\n",
+ part, ret);
+ return CMD_RET_FAILURE;
+ }
+ debug("Found partition '%s': offset=%08x size=%08x\n",
+ part, part_info->offset, part_info->size);
+ if (part_info->size < fbsize) {
+ printf("Error: partition '%s' smaller than frame buffer size: %u\n",
+ part, fbsize);
+ return CMD_RET_FAILURE;
+ }
+ debug("Writing framebuffer %p to NAND partition '%s'\n",
+ addr, part);
+
+ ret = erase_flash(part_info->offset, fbsize);
+ if (ret) {
+ printf("Failed to erase partition '%s'\n", part);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = nand_write_skip_bad(&nand_info[0], part_info->offset,
+ &fbsize, NULL, part_info->size,
+ addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to write partition '%s'\n", part);
+ return CMD_RET_FAILURE;
+ }
+
+ debug("Wrote %u byte from %p to partition '%s' @ offset %08x\n",
+ fbsize, addr, part, part_info->offset);
+
+ return CMD_RET_SUCCESS;
+ }
+
+ U_BOOT_CMD(fbdump, 2, 0, do_fbdump, "dump framebuffer contents to flash",
+ "[partition name]\n"
+ " default partition name: 'logo'\n");
+ #endif
--- /dev/null
--- /dev/null
++if TARGET_TX28_40X1
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-40x1"
++
++endif
++
++if TARGET_TX28_40X1_NOENV
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-40x1_noenv"
++
++endif
++
++if TARGET_TX28_40X2
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-40x2"
++
++endif
++
++if TARGET_TX28_40X2_NOENV
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-40x2_noenv"
++
++endif
++
++if TARGET_TX28_40X3
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-40x3"
++
++endif
++
++if TARGET_TX28_40X3_NOENV
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-40x3_noenv"
++
++endif
++
++if TARGET_TX28_41X0
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-41x0"
++
++endif
++
++if TARGET_TX28_41X0_NOENV
++
++config SYS_BOARD
++ default "tx28"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mxs"
++
++config SYS_CONFIG_NAME
++ default "tx28-41x0_noenv"
++
++endif
--- /dev/null
-# (C) Copyright 2009 DENX Software Engineering
-# Author: John Rigby <jcrigby@gmail.com>
+ #
-# See file CREDITS for list of people who contributed to this
-# project.
++# (C) Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
++# SPDX-License-Identifier: GPL-2.0+
+ #
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := tx28.o
-ifeq ($(CONFIG_SPL_BUILD),y)
- COBJS += spl_boot.o
-else
-ifeq ($(CONFIG_CMD_ROMUPDATE),y)
- COBJS += flash.o
-endif
+
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-$(obj)u-boot.db: u-boot.db.in
- sed "s:@@BUILD_DIR@@:${BUILD_DIR:-.}/:" $< > $@
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
++obj-y += tx28.o
++obj-$(CONFIG_SPL_BUILD) += spl_boot.o
++ifneq ($(CONFIG_SPL_BUILD),y)
++ obj-$(CONFIG_CMD_ROMUPDATE) += flash.o
+ endif
--- /dev/null
-#include <asm/sizes.h>
+ /*
+ * Copyright (C) 2011-2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <malloc.h>
+ #include <nand.h>
+ #include <errno.h>
+
+ #include <linux/err.h>
+ #include <jffs2/load_kernel.h>
+
+ #include <asm/io.h>
++#include <linux/sizes.h>
+ #include <asm/arch/regs-base.h>
+ #include <asm/imx-common/regs-gpmi.h>
+ #include <asm/imx-common/regs-bch.h>
+
+ struct mx28_nand_timing {
+ u8 data_setup;
+ u8 data_hold;
+ u8 address_setup;
+ u8 dsample_time;
+ u8 nand_timing_state;
+ u8 tREA;
+ u8 tRLOH;
+ u8 tRHOH;
+ };
+
+ struct mx28_fcb {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ struct mx28_nand_timing timing;
+ u32 page_data_size;
+ u32 total_page_size;
+ u32 sectors_per_block;
+ u32 number_of_nands; /* not used by ROM code */
+ u32 total_internal_die; /* not used by ROM code */
+ u32 cell_type; /* not used by ROM code */
+ u32 ecc_blockn_type;
+ u32 ecc_block0_size;
+ u32 ecc_blockn_size;
+ u32 ecc_block0_type;
+ u32 metadata_size;
+ u32 ecc_blocks_per_page;
+ u32 rsrvd[6]; /* not used by ROM code */
+ u32 bch_mode;
+ u32 boot_patch;
+ u32 patch_sectors;
+ u32 fw1_start_page;
+ u32 fw2_start_page;
+ u32 fw1_sectors;
+ u32 fw2_sectors;
+ u32 dbbt_search_area;
+ u32 bb_mark_byte;
+ u32 bb_mark_startbit;
+ u32 bb_mark_phys_offset;
+ };
+
+ #define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
+
+ static nand_info_t *mtd = &nand_info[0];
+
+ extern void *_start;
+
+ #define BIT(v,n) (((v) >> (n)) & 0x1)
+
+ static u8 calculate_parity_13_8(u8 d)
+ {
+ u8 p = 0;
+
+ p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0;
+ p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1;
+ p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2;
+ p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3;
+ p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4;
+ return p;
+ }
+
+ static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+ {
+ int i;
+ u8 *src = _src;
+ u8 *ecc = _ecc;
+
+ for (i = 0; i < size; i++)
+ ecc[i] = calculate_parity_13_8(src[i]);
+ }
+
+ static u32 calc_chksum(void *buf, size_t size)
+ {
+ u32 chksum = 0;
+ u8 *bp = buf;
+ size_t i;
+
+ for (i = 0; i < size; i++) {
+ chksum += bp[i];
+ }
+ return ~chksum;
+ }
+
+ /*
+ Physical organisation of data in NAND flash:
+ metadata
+ payload chunk 0 (may be empty)
+ ecc for metadata + payload chunk 0
+ payload chunk 1
+ ecc for payload chunk 1
+ ...
+ payload chunk n
+ ecc for payload chunk n
+ */
+
+ static int calc_bb_offset(nand_info_t *mtd, struct mx28_fcb *fcb)
+ {
+ int bb_mark_offset;
+ int chunk_data_size = fcb->ecc_blockn_size * 8;
+ int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
+ int chunk_total_size = chunk_data_size + chunk_ecc_size;
+ int bb_mark_chunk, bb_mark_chunk_offs;
+
+ bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
+ if (fcb->ecc_block0_size == 0)
+ bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
+
+ bb_mark_chunk = bb_mark_offset / chunk_total_size;
+ bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size);
+ if (bb_mark_chunk_offs > chunk_data_size) {
+ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
+ bb_mark_chunk_offs);
+ return -EINVAL;
+ }
+ bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
+ return bb_mark_offset;
+ }
+
+ /*
+ * return number of blocks to skip for a contiguous partition
+ * of given # blocks
+ */
+ static int find_contig_space(int block, int num_blocks, int max_blocks)
+ {
+ int skip = 0;
+ int found = 0;
+ int last = block + max_blocks;
+
+ debug("Searching %u contiguous blocks from %d..%d\n",
+ num_blocks, block, block + max_blocks - 1);
+ for (; block < last; block++) {
+ if (nand_block_isbad(mtd, block * mtd->erasesize)) {
+ skip += found + 1;
+ found = 0;
+ debug("Skipping %u blocks to %u\n",
+ skip, block + 1);
+ } else {
+ found++;
+ if (found >= num_blocks) {
+ debug("Found %u good blocks from %d..%d\n",
+ found, block - found + 1, block);
+ return skip;
+ }
+ }
+ }
+ return -ENOSPC;
+ }
+
+ #define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n)
+
+ static struct mx28_fcb *create_fcb(void *buf, int fw1_start_block,
+ int fw2_start_block, int fw_num_blocks)
+ {
+ struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS;
+ struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS;
+ u32 fl0, fl1;
+ u32 t0;
+ int metadata_size;
+ int bb_mark_bit_offs;
+ struct mx28_fcb *fcb;
+ int fcb_offs;
+
+ if (gpmi_base == NULL || bch_base == NULL) {
+ return ERR_PTR(-ENOMEM);
+ }
+
+ fl0 = readl(&bch_base->hw_bch_flash0layout0);
+ fl1 = readl(&bch_base->hw_bch_flash0layout1);
+ t0 = readl(&gpmi_base->hw_gpmi_timing0);
+
+ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+
+ fcb = buf + ALIGN(metadata_size, 4);
+ fcb_offs = (void *)fcb - buf;
+
+ memset(buf, 0xff, fcb_offs);
+ memset(fcb, 0x00, sizeof(*fcb));
+ memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
+
+ strncpy((char *)&fcb->fingerprint, "FCB ", 4);
+ fcb->version = cpu_to_be32(1);
+
+ /* ROM code assumes GPMI clock of 25 MHz */
+ fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP) * 40;
+ fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD) * 40;
+ fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP) * 40;
+
+ fcb->page_data_size = mtd->writesize;
+ fcb->total_page_size = mtd->writesize + mtd->oobsize;
+ fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
+
+ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
+ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE);
+ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
+ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE);
+
+ pr_fcb_val(fcb, ecc_block0_type);
+ pr_fcb_val(fcb, ecc_blockn_type);
+ pr_fcb_val(fcb, ecc_block0_size);
+ pr_fcb_val(fcb, ecc_blockn_size);
+
+ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
+ fcb->bch_mode = readl(&bch_base->hw_bch_mode);
+
+ fcb->fw1_start_page = fw1_start_block * fcb->sectors_per_block;
+ fcb->fw1_sectors = fw_num_blocks * fcb->sectors_per_block;
+ pr_fcb_val(fcb, fw1_start_page);
+ pr_fcb_val(fcb, fw1_sectors);
+
+ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
+ fcb->fw2_start_page = fw2_start_block * fcb->sectors_per_block;
+ fcb->fw2_sectors = fcb->fw1_sectors;
+ pr_fcb_val(fcb, fw2_start_page);
+ pr_fcb_val(fcb, fw2_sectors);
+ }
+
+ fcb->dbbt_search_area = 1;
+
+ bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
+ if (bb_mark_bit_offs < 0)
+ return ERR_PTR(bb_mark_bit_offs);
+ fcb->bb_mark_byte = bb_mark_bit_offs / 8;
+ fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
+ fcb->bb_mark_phys_offset = mtd->writesize;
+
+ pr_fcb_val(fcb, bb_mark_byte);
+ pr_fcb_val(fcb, bb_mark_startbit);
+ pr_fcb_val(fcb, bb_mark_phys_offset);
+
+ fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
+ return fcb;
+ }
+
+ static int find_fcb(void *ref, int page)
+ {
+ int ret = 0;
+ struct nand_chip *chip = mtd->priv;
+ void *buf = malloc(mtd->erasesize);
+
+ if (buf == NULL) {
+ return -ENOMEM;
+ }
+ chip->select_chip(mtd, 0);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
+ if (ret) {
+ printf("Failed to read FCB from page %u: %d\n", page, ret);
+ goto out;
+ }
+ if (memcmp(buf, ref, mtd->writesize) == 0) {
+ debug("Found FCB in page %u (%08x)\n",
+ page, page * mtd->writesize);
+ ret = 1;
+ }
+ out:
+ chip->select_chip(mtd, -1);
+ free(buf);
+ return ret;
+ }
+
+ static int write_fcb(void *buf, int block)
+ {
+ int ret;
+ struct nand_chip *chip = mtd->priv;
+ int page = block * mtd->erasesize / mtd->writesize;
+
+ ret = find_fcb(buf, page);
+ if (ret > 0) {
+ printf("FCB at block %d is up to date\n", block);
+ return 0;
+ }
+
+ ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize);
+ if (ret) {
+ printf("Failed to erase FCB block %u\n", block);
+ return ret;
+ }
+
+ printf("Writing FCB to block %d @ %08llx\n", block,
+ (u64)block * mtd->erasesize);
+ chip->select_chip(mtd, 0);
+ ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1);
+ if (ret) {
+ printf("Failed to write FCB to block %u: %d\n", block, ret);
+ }
+ chip->select_chip(mtd, -1);
+ return ret;
+ }
+
+ #define chk_overlap(a,b) \
+ ((a##_start_block <= b##_end_block && \
+ a##_end_block >= b##_start_block) || \
+ (b##_start_block <= a##_end_block && \
+ b##_end_block >= a##_start_block))
+
+ #define fail_if_overlap(a,b,m1,m2) do { \
+ if (chk_overlap(a, b)) { \
+ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \
+ m1, a##_start_block, a##_end_block, \
+ m2, b##_start_block, b##_end_block); \
+ return -EINVAL; \
+ } \
+ } while (0)
+
+ static int tx28_prog_uboot(void *addr, int start_block, int skip,
+ size_t size, size_t max_len)
+ {
+ int ret;
+ nand_erase_options_t erase_opts = { 0, };
+ size_t actual;
+ size_t prg_length = max_len - skip * mtd->erasesize;
+ int prg_start = (start_block + skip) * mtd->erasesize;
+
+ erase_opts.offset = start_block * mtd->erasesize;
+ erase_opts.length = max_len;
+ erase_opts.quiet = 1;
+
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+
+ printf("Programming flash @ %08llx..%08llx from %p\n",
+ (u64)start_block * mtd->erasesize,
+ (u64)start_block * mtd->erasesize + size - 1, addr);
+ actual = size;
+ ret = nand_write_skip_bad(mtd, prg_start, &actual, NULL,
+ prg_length, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ if (actual < size) {
+ printf("Could only write %u of %u bytes\n", actual, size);
+ return -EIO;
+ }
+ return 0;
+ }
+
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ #ifndef CONFIG_ENV_OFFSET_REDUND
+ #define TOTAL_ENV_SIZE CONFIG_ENV_RANGE
+ #else
+ #define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2)
+ #endif
+ #endif
+
+ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int ret;
+ const unsigned long fcb_start_block = 0, fcb_end_block = 0;
+ int erase_size = mtd->erasesize;
+ int page_size = mtd->writesize;
+ void *buf;
+ char *load_addr;
+ char *file_size;
+ size_t size = 0;
+ void *addr = NULL;
+ struct mx28_fcb *fcb;
+ unsigned long mtd_num_blocks = mtd->size / mtd->erasesize;
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize;
+ unsigned long env_end_block = env_start_block +
+ DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1;
+ #endif
+ int optind;
+ int fw2_set = 0;
+ unsigned long fw1_start_block = 0, fw1_end_block;
+ unsigned long fw2_start_block = 0, fw2_end_block;
+ unsigned long fw_num_blocks;
+ int fw1_skip, fw2_skip;
+ unsigned long extra_blocks = 0;
+ size_t max_len1, max_len2;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ struct part_info *redund_part_info;
+ const char *uboot_part = "u-boot";
+ const char *redund_part = NULL;
+ u8 part_num;
+ u8 redund_part_num;
+
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ for (optind = 1; optind < argc; optind++) {
+ char *endp;
+
+ if (strcmp(argv[optind], "-f") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fw1_start_block = simple_strtoul(argv[optind], &endp, 0);
+ if (*endp != '\0') {
+ uboot_part = argv[optind];
+ continue;
+ }
+ uboot_part = NULL;
+ if (fw1_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw1_start_block, mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-r") == 0) {
+ fw2_set = 1;
+ if (optind < argc - 1 && argv[optind + 1][0] != '-') {
+ optind++;
+ fw2_start_block = simple_strtoul(argv[optind],
+ &endp, 0);
+ if (*endp != '\0') {
+ redund_part = argv[optind];
+ continue;
+ }
+ if (fw2_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw2_start_block,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ }
+ } else if (strcmp(argv[optind], "-e") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ extra_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (extra_blocks >= mtd_num_blocks) {
+ printf("Extra block count %lu is out of range: 0..%lu\n",
+ extra_blocks,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (argv[optind][0] == '-') {
+ printf("Unrecognized option %s\n", argv[optind]);
+ return -EINVAL;
+ } else {
+ break;
+ }
+ }
+
+ load_addr = getenv("fileaddr");
+ file_size = getenv("filesize");
+
+ if (argc - optind < 1 && load_addr == NULL) {
+ printf("Load address not specified\n");
+ return -EINVAL;
+ }
+ if (argc - optind < 2 && file_size == NULL) {
+ printf("WARNING: Image size not specified; overwriting whole uboot partition\n");
+ }
+ if (argc > optind) {
+ load_addr = NULL;
+ addr = (void *)simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (argc > optind) {
+ file_size = NULL;
+ size = simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (load_addr != NULL) {
+ addr = (void *)simple_strtoul(load_addr, NULL, 16);
+ printf("Using default load address %p\n", addr);
+ }
+ if (file_size != NULL) {
+ size = simple_strtoul(file_size, NULL, 16);
+ printf("Using default file size %08x\n", size);
+ }
+ if (size > 0) {
+ fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize);
+ } else {
+ fw_num_blocks = part_info->size / mtd->erasesize -
+ extra_blocks;
+ size = fw_num_blocks * mtd->erasesize;
+ }
+
+ if (uboot_part) {
+ ret = find_dev_and_part(uboot_part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ uboot_part, ret);
+ return ret;
+ }
+ fw1_start_block = part_info->offset / mtd->erasesize;
+ max_len1 = part_info->size;
+ } else {
+ max_len1 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
+ }
+
+ if (redund_part) {
+ ret = find_dev_and_part(redund_part, &dev, &redund_part_num,
+ &redund_part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ redund_part, ret);
+ return ret;
+ }
+ fw2_start_block = redund_part_info->offset / mtd->erasesize;
+ max_len2 = redund_part_info->size;
+ } else if (fw2_set) {
+ max_len2 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
+ } else {
+ max_len2 = 0;
+ }
+
+ fw1_skip = find_contig_space(fw1_start_block, fw_num_blocks,
+ max_len1 / mtd->erasesize);
+ if (fw1_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for fw image\n",
+ fw_num_blocks);
+ if (uboot_part) {
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ if (part_info->offset <= CONFIG_ENV_OFFSET + TOTAL_ENV_SIZE) {
+ printf("Use a different partition\n");
+ } else {
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+ }
+ #else
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+ #endif
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
+ fw1_end_block = fw1_start_block + fw1_skip + fw_num_blocks - 1;
+
+ if (fw2_set && fw2_start_block == 0)
+ fw2_start_block = fw1_end_block + 1;
+ if (fw2_start_block > 0) {
+ fw2_skip = find_contig_space(fw2_start_block, fw_num_blocks,
+ max_len2 / mtd->erasesize);
+ if (fw2_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for redundant fw image\n",
+ fw_num_blocks);
+ if (redund_part) {
+ printf("Increase the size of the '%s' partition or use a different partition\n",
+ redund_part);
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
+ } else {
+ fw2_skip = 0;
+ }
+ fw2_end_block = fw2_start_block + fw2_skip + fw_num_blocks - 1;
+
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fcb, env, "FCB", "Environment");
+ fail_if_overlap(fw1, env, "FW1", "Environment");
+ #endif
+ fail_if_overlap(fcb, fw1, "FCB", "FW1");
+ if (fw2_set) {
+ fail_if_overlap(fcb, fw2, "FCB", "FW2");
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fw2, env, "FW2", "Environment");
+ #endif
+ fail_if_overlap(fw1, fw2, "FW1", "FW2");
+ }
+
+ buf = malloc(erase_size);
+ if (buf == NULL) {
+ printf("Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ fcb = create_fcb(buf, fw1_start_block + fw1_skip,
+ fw2_start_block + fw2_skip, fw_num_blocks);
+ if (IS_ERR(fcb)) {
+ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+ free(buf);
+ return PTR_ERR(fcb);
+ }
+ encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
+
+ ret = write_fcb(buf, fcb_start_block);
+ free(buf);
+ if (ret) {
+ printf("Failed to write FCB to block %lu\n", fcb_start_block);
+ return ret;
+ }
+
+ if (size & (page_size - 1)) {
+ memset(addr + size, 0xff, size & (page_size - 1));
+ size = ALIGN(size, page_size);
+ }
+
+ printf("Programming U-Boot image from %p to block %lu @ %08llx\n",
+ addr, fw1_start_block + fw1_skip,
+ (u64)(fw1_start_block + fw1_skip) * mtd->erasesize);
+ ret = tx28_prog_uboot(addr, fw1_start_block, fw1_skip, size,
+ max_len1);
+
+ if (fw2_start_block == 0) {
+ return ret;
+ }
+
+ printf("Programming redundant U-Boot image to block %lu @ %08llx\n",
+ fw2_start_block + fw2_skip,
+ (u64)(fw2_start_block + fw2_skip) * mtd->erasesize);
+ ret = tx28_prog_uboot(addr, fw2_start_block, fw2_skip, fw_num_blocks,
+ max_len2);
+ return ret;
+ }
+
+ U_BOOT_CMD(romupdate, 11, 0, do_update,
+ "Creates an FCB data structure and writes an U-Boot image to flash",
+ "[-f {<part>|block#}] [-r [{<part>|block#}]] [-e #] [<address>] [<length>]\n"
+ "\t-f <part>\twrite bootloader image to partition <part>\n"
+ "\t-f #\twrite bootloader image at block # (decimal)\n"
+ "\t-r\twrite redundant bootloader image at next free block after first image\n"
+ "\t-r <part>\twrite redundant bootloader image to partition <part>\n"
+ "\t-r #\twrite redundant bootloader image at block # (decimal)\n"
+ "\t-e #\tspecify number of redundant blocks per boot loader image\n"
+ "\t\tonly valid if -f or -r specify a flash address rather than a partition name\n"
+ "\t<address>\tRAM address of bootloader image (default: ${fileaddr}\n"
+ "\t<length>\tlength of bootloader image in RAM (default: ${filesize}"
+ );
--- /dev/null
- { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
- { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
- { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
- { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
- { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
+ /*
+ * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <libfdt.h>
+ #include <fdt_support.h>
+ #include <lcd.h>
+ #include <netdev.h>
+ #include <mmc.h>
+ #include <mxcfb.h>
+ #include <linux/list.h>
+ #include <linux/fb.h>
+ #include <asm/io.h>
+ #include <asm/gpio.h>
+ #include <asm/arch/iomux-mx28.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/sys_proto.h>
+
+ #include "../common/karo.h"
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define MXS_GPIO_NR(p, o) (((p) << 5) | (o))
+
+ #define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31
+ #define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30
+ #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
+
+ #define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27
+ #define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20
+ #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
+ #define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19
+ #define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18
+
+ #define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10
+
+ #define STK5_CAN_XCVR_GPIO MX28_PAD_LCD_D00__GPIO_1_0
+
+ static const struct gpio tx28_gpios[] = {
- .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
++ { TX28_USBH_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBH VBUSEN", },
++ { TX28_USBH_OC_GPIO, GPIOFLAG_INPUT, "USBH OC", },
++ { TX28_USBOTG_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
++ { TX28_USBOTG_OC_GPIO, GPIOFLAG_INPUT, "USBOTG OC", },
++ { TX28_USBOTG_ID_GPIO, GPIOFLAG_INPUT, "USBOTG ID", },
+ };
+
+ static const iomux_cfg_t tx28_pads[] = {
+ /* UART pads */
+ #if CONFIG_CONS_INDEX == 0
+ MX28_PAD_AUART0_RX__DUART_CTS,
+ MX28_PAD_AUART0_TX__DUART_RTS,
+ MX28_PAD_AUART0_CTS__DUART_RX,
+ MX28_PAD_AUART0_RTS__DUART_TX,
+ #elif CONFIG_CONS_INDEX == 1
+ MX28_PAD_AUART1_RX__AUART1_RX,
+ MX28_PAD_AUART1_TX__AUART1_TX,
+ MX28_PAD_AUART1_CTS__AUART1_CTS,
+ MX28_PAD_AUART1_RTS__AUART1_RTS,
+ #elif CONFIG_CONS_INDEX == 2
+ MX28_PAD_AUART3_RX__AUART3_RX,
+ MX28_PAD_AUART3_TX__AUART3_TX,
+ MX28_PAD_AUART3_CTS__AUART3_CTS,
+ MX28_PAD_AUART3_RTS__AUART3_RTS,
+ #endif
+ /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* USBH VBUSEN, OC */
+ MX28_PAD_SPDIF__GPIO_3_27,
+ MX28_PAD_JTAG_RTCK__GPIO_4_20,
+
+ /* USBOTG VBUSEN, OC, ID */
+ MX28_PAD_GPMI_CE2N__GPIO_0_18,
+ MX28_PAD_GPMI_CE3N__GPIO_0_19,
+ MX28_PAD_PWM2__GPIO_3_18,
+ };
+
+ /*
+ * Functions
+ */
+
+ /* provide at least _some_ sort of randomness */
+ #define MAX_LOOPS 100
+
+ static u32 random;
+
+ static inline void random_init(void)
+ {
+ struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
+ u32 seed = 0;
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ u32 hclk = readl(&digctl_regs->hw_digctl_hclkcount);
+ u32 entropy = readl(&digctl_regs->hw_digctl_entropy);
+ u32 usec = readl(&digctl_regs->hw_digctl_microseconds);
+
+ seed = get_timer(hclk ^ entropy ^ usec ^ random ^ seed);
+ srand(seed);
+ random = rand();
+ }
+ }
+
+ #define RTC_PERSISTENT0_CLK32_MASK (RTC_PERSISTENT0_CLOCKSOURCE | \
+ RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
+ static u32 boot_cause __attribute__((section("data")));
+
+ int board_early_init_f(void)
+ {
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
+ u32 rtc_stat;
+ int timeout = 5000;
+
+ random_init();
+
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+ gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
+ mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
+
+ while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
+ RTC_STAT_STALE_REGS_PERSISTENT0) {
+ if (timeout-- < 0)
+ return 1;
+ udelay(1);
+ }
+ boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
+ if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
+ RTC_PERSISTENT0_CLK32_MASK) {
+ if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
+ goto rtc_err;
+ writel(RTC_PERSISTENT0_CLK32_MASK,
+ &rtc_regs->hw_rtc_persistent0_set);
+ }
+ return 0;
+
+ rtc_err:
+ serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
+ return 1;
+ }
+
+ int board_init(void)
+ {
+ if (ctrlc()) {
+ printf("CTRL-C detected; safeboot enabled\n");
+ return 1;
+ }
+
+ /* Address of boot parameters */
+ #ifdef CONFIG_OF_LIBFDT
+ gd->bd->bi_arch_number = -1;
+ #endif
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+ return 0;
+ }
+
+ int dram_init(void)
+ {
+ return mxs_dram_init();
+ }
+
+ #ifdef CONFIG_CMD_MMC
+ static int tx28_mmc_wp(int dev_no)
+ {
+ return 0;
+ }
+
+ int board_mmc_init(bd_t *bis)
+ {
+ return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
+ }
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_FEC_MXC
+ #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+
+ #ifdef CONFIG_FEC_MXC_MULTI
+ #define FEC_MAX_IDX 1
+ #else
+ #define FEC_MAX_IDX 0
+ #endif
+ #ifndef ETH_ALEN
+ #define ETH_ALEN 6
+ #endif
+
+ static int fec_get_mac_addr(int index)
+ {
+ int timeout = 1000;
+ struct mxs_ocotp_regs *ocotp_regs =
+ (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
+ u32 *cust = &ocotp_regs->hw_ocotp_cust0;
+ u8 mac[ETH_ALEN];
+ char env_name[] = "eth.addr";
+ u32 val = 0;
+ int i;
+
+ if (index < 0 || index > FEC_MAX_IDX)
+ return -EINVAL;
+
+ /* set this bit to open the OTP banks for reading */
+ writel(OCOTP_CTRL_RD_BANK_OPEN,
+ &ocotp_regs->hw_ocotp_ctrl_set);
+
+ /* wait until OTP contents are readable */
+ while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
+ if (timeout-- < 0)
+ return -ETIMEDOUT;
+ udelay(100);
+ }
+
+ for (i = 0; i < sizeof(mac); i++) {
+ int shift = 24 - i % 4 * 8;
+
+ if (i % 4 == 0)
+ val = readl(&cust[index * 8 + i]);
+ mac[i] = val >> shift;
+ }
+ if (!is_valid_ether_addr(mac)) {
+ if (index == 0)
+ printf("No valid MAC address programmed\n");
+ return 0;
+ }
+
+ if (index == 0) {
+ printf("MAC addr from fuse: %pM\n", mac);
+ snprintf(env_name, sizeof(env_name), "ethaddr");
+ } else {
+ snprintf(env_name, sizeof(env_name), "eth%daddr", index);
+ }
+ eth_setenv_enetaddr(env_name, mac);
+ return 0;
+ }
+ #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
+
+ static const iomux_cfg_t tx28_fec_pads[] = {
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1,
+ };
+
+ int board_eth_init(bd_t *bis)
+ {
+ int ret;
+
+ /* Reset the external phy */
+ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+
+ /* Power on the external phy */
+ gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
+
+ /* Pull strap pins to high */
+ gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
+ gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
+ gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
+ gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
+
+ udelay(25000);
+ gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+ udelay(100);
+
+ mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("cpu_eth_init() failed: %d\n", ret);
+ return ret;
+ }
+
+ #ifdef CONFIG_FEC_MXC_MULTI
+ if (getenv("ethaddr")) {
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+ }
+
+ if (getenv("eth1addr")) {
+ ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+ }
+ #else
+ if (getenv("ethaddr")) {
+ ret = fecmxc_initialize(bis);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC\n");
+ return ret;
+ }
+ }
+ #endif
+ return 0;
+ }
+ #endif /* CONFIG_FEC_MXC */
+
+ enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+ };
+
+ void show_activity(int arg)
+ {
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX28_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX28_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX28_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+ }
+
+ static const iomux_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX28_PAD_ENET0_RXD3__GPIO_4_10,
+ };
+
+ static const struct gpio stk5_gpios[] = {
+ };
+
+ #ifdef CONFIG_LCD
+ static ushort tx28_cmap[256];
+ vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1600,
+ .vl_row = 1200,
+
- { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
- { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
- { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
++ .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx28_cmap,
+ };
+
+ static struct fb_videomode tx28_fb_modes[] = {
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ };
+
+ static int lcd_enabled = 1;
+ static int lcd_bl_polarity;
+
+ static int lcd_backlight_polarity(void)
+ {
+ return lcd_bl_polarity;
+ }
+
+ void lcd_enable(void)
+ {
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ karo_load_splashimage(1);
+ if (lcd_enabled) {
+ debug("Switching LCD on\n");
+ gpio_set_value(TX28_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX28_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
+ }
+ }
+
+ void lcd_disable(void)
+ {
+ }
+
+ void lcd_panel_disable(void)
+ {
+ if (lcd_enabled) {
+ debug("Switching LCD off\n");
+ gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
+ gpio_set_value(TX28_LCD_RST_GPIO, 0);
+ gpio_set_value(TX28_LCD_PWR_GPIO, 0);
+ }
+ }
+
+ static const iomux_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
+ /* LCD POWER_ENABLE */
+ MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
+ /* LCD Backlight (PWM) */
+ MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
+
+ /* Display */
+ MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
+ MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
+ MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
+ };
+
+ static const struct gpio stk5_lcd_gpios[] = {
- panel_info.vl_bpix = LCD_COLOR24;
++ { TX28_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
++ { TX28_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
++ { TX28_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ };
+
+ extern void video_hw_init(void *lcdbase);
+
+ void lcd_ctrl_init(void *lcdbase)
+ {
+ int color_depth = 24;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = tx28_fb_modes;
+ struct fb_videomode fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (had_ctrlc()) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ setenv("splashimage", NULL);
+ return;
+ }
+
+ karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
+
+ if (video_mode == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres > panel_info.vl_col ||
+ fb_mode.yres > panel_info.vl_row) {
+ printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
+ fb_mode.xres, fb_mode.yres,
+ panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 8:
+ case 16:
+ case 18:
+ case 24:
+ color_depth = val;
+ break;
+
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
+ }
+ if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
+ printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
+ p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ panel_info.vl_col = p->xres;
+ panel_info.vl_row = p->yres;
+
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = LCD_COLOR8;
+ break;
+ case 16:
+ panel_info.vl_bpix = LCD_COLOR16;
+ break;
+ default:
- gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOF_OUTPUT_INIT_HIGH,
++ panel_info.vl_bpix = LCD_COLOR32;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
+
+ if (p != &fb_mode) {
+ int ret;
+
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
+ if (ret)
+ printf("Failed to create new display-timing node from '%s': %d\n",
+ video_mode, ret);
+ }
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
+ color_depth, refresh);
+
+ if (karo_load_splashimage(0) == 0) {
+ char vmode[128];
+
+ /* setup env variable for mxsfb display driver */
+ snprintf(vmode, sizeof(vmode),
+ "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
+ p->xres, p->yres, p->left_margin, p->right_margin,
+ p->upper_margin, p->lower_margin, p->hsync_len,
+ p->vsync_len, p->sync, p->pixclock, color_depth);
+ setenv("videomode", vmode);
+
+ debug("Initializing LCD controller\n");
+ video_hw_init(lcdbase);
+ setenv("videomode", NULL);
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+ }
+ #else
+ #define lcd_enabled 0
+ #endif /* CONFIG_LCD */
+
+ static void stk5_board_init(void)
+ {
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+ }
+
+ static void stk5v3_board_init(void)
+ {
+ stk5_board_init();
+ }
+
+ static void stk5v5_board_init(void)
+ {
+ stk5_board_init();
+
+ /* init flexcan transceiver enable GPIO */
- mxs_iomux_setup_pad(STK5_CAN_XCVR_GPIO);
++ gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
-void ft_board_setup(void *blob, bd_t *bd)
++ SETUP_IOMUX_PAD(STK5_CAN_XCVR_GPIO);
+ }
+
+ int tx28_fec1_enabled(void)
+ {
+ const char *status;
+ int off;
+
+ if (!gd->fdt_blob)
+ return 0;
+
+ off = fdt_path_offset(gd->fdt_blob, "ethernet1");
+ if (off < 0)
+ return 0;
+
+ status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
+ return status && (strcmp(status, "okay") == 0);
+ }
+
+ static void tx28_init_mac(void)
+ {
+ int ret;
+
+ ret = fec_get_mac_addr(0);
+ if (ret < 0) {
+ printf("Failed to read FEC0 MAC address from OCOTP\n");
+ return;
+ }
+ #ifdef CONFIG_FEC_MXC_MULTI
+ if (tx28_fec1_enabled()) {
+ ret = fec_get_mac_addr(1);
+ if (ret < 0) {
+ printf("Failed to read FEC1 MAC address from OCOTP\n");
+ return;
+ }
+ }
+ #endif
+ }
+
+ int board_late_init(void)
+ {
+ int ret = 0;
+ const char *baseboard;
+
+ env_cleanup();
+
+ if (had_ctrlc())
+ setenv_ulong("safeboot", 1);
+ else
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ printf("Baseboard: %s\n", baseboard);
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && strcmp(otg_mode, "host") == 0) {
+ printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
+ otg_mode, baseboard);
+ setenv("otg_mode", "none");
+ }
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+ exit:
+ tx28_init_mac();
+ clear_ctrlc();
+ return ret;
+ }
+
+ #define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
+ RTC_PERSISTENT0_ALARM_WAKE | \
+ RTC_PERSISTENT0_THERMAL_RESET)
+
+ static void thermal_init(void)
+ {
+ struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
+
+ writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
+ POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
+ &power_regs->hw_power_thermal);
+
+ writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
+ CLKCTRL_RESET_THERMAL_RESET_ENABLE,
+ &clkctrl_regs->hw_clkctrl_reset);
+ }
+
+ int checkboard(void)
+ {
+ struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+ u32 pwr_sts = readl(&power_regs->hw_power_sts);
+ u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
+ const char *dlm = "";
+
+ printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
+ CONFIG_SDRAM_SIZE / SZ_128M +
+ CONFIG_SYS_NAND_BLOCKS / 2048 * 2);
+
+ printf("POWERUP Source: ");
+ if (pwrup_src & (3 << 0)) {
+ printf("%sPSWITCH %s voltage", dlm,
+ pwrup_src & (1 << 1) ? "HIGH" : "MID");
+ dlm = " | ";
+ }
+ if (pwrup_src & (1 << 4)) {
+ printf("%sRTC", dlm);
+ dlm = " | ";
+ }
+ if (pwrup_src & (1 << 5)) {
+ printf("%s5V", dlm);
+ dlm = " | ";
+ }
+ printf("\n");
+
+ if (boot_cause & BOOT_CAUSE_MASK) {
+ dlm="";
+ printf("Last boot cause: ");
+ if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
+ printf("%sEXTERNAL", dlm);
+ dlm = " | ";
+ }
+ if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
+ printf("%sTHERMAL", dlm);
+ dlm = " | ";
+ }
+ if (*dlm != '\0')
+ printf(" RESET");
+ if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
+ printf("%sALARM WAKE", dlm);
+ dlm = " | ";
+ }
+ printf("\n");
+ }
+
+ while (pwr_sts & POWER_STS_THERMAL_WARNING) {
+ static int first = 1;
+
+ if (first) {
+ printf("CPU too hot to boot\n");
+ first = 0;
+ }
+ if (tstc())
+ break;
+ pwr_sts = readl(&power_regs->hw_power_sts);
+ }
+
+ if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
+ thermal_init();
+
+ return 0;
+ }
+
+ #if defined(CONFIG_OF_BOARD_SETUP)
+ #ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ #include <jffs2/jffs2.h>
+ #include <mtd_node.h>
+ static struct node_info tx28_nand_nodes[] = {
+ { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
+ };
+ #else
+ #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+ #endif
+
+ static const char *tx28_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+ "fsl,imx28-lradc",
+ };
+
- if (ret)
++int ft_board_setup(void *blob, bd_t *bd)
+ {
+ const char *baseboard = getenv("baseboard");
+ int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
-
++ if (ret) {
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
++ return ret;
++ }
+ #ifdef CONFIG_TX28_S
+ /* TX28-41xx (aka TX28S) has no external RTC
+ * and no I2C GPIO extender
+ */
+ karo_fdt_remove_node(blob, "ds1339");
+ karo_fdt_remove_node(blob, "gpio5");
+ #endif
+ if (stk5_v5)
+ karo_fdt_enable_node(blob, "stk5led", 0);
+
+ fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
+ ARRAY_SIZE(tx28_touchpanels));
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
+ karo_fdt_fixup_flexcan(blob, stk5_v5);
+ karo_fdt_update_fb_mode(blob, video_mode);
++
++ return 0;
+ }
+ #endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
--- /dev/null
++if TARGET_TX48
++
++config SYS_BOARD
++ default "tx48"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "am33xx"
++
++config SYS_CONFIG_NAME
++ default "tx48"
++
++endif
--- /dev/null
-# Makefile
+ #
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
++# (C) Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation version 2.
-#
-# This program is distributed "as is" WITHOUT ANY WARRANTY of any
-# kind, whether express or implied; without even the implied warranty
-# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-include $(TOPDIR)/config.mk
++# SPDX-License-Identifier: GPL-2.0+
+ #
-LIB = $(obj)lib$(BOARD).o
-
-ifeq ($(CONFIG_SPL_BUILD),)
- COBJS := tx48.o
+
- COBJS := spl.o
++ifneq ($(CONFIG_SPL_BUILD),y)
++ obj-y += tx48.o
+ else
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
++ obj-y += spl.o
+ endif
--- /dev/null
- { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ /*
+ * board/karo/tx48/spl.c
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <miiphy.h>
+ #include <netdev.h>
+ #include <serial.h>
+ #include <libfdt.h>
+ #include <fdt_support.h>
+ #include <nand.h>
+ #include <net.h>
+ #include <spl.h>
+ #include <linux/mtd/nand.h>
+ #include <asm/gpio.h>
+ #include <asm/cache.h>
+ #include <asm/omap_common.h>
+ #include <asm/io.h>
+ #include <asm/arch/cpu.h>
+ #include <asm/arch/hardware.h>
+ #include <asm/arch/mmc_host_def.h>
+ #include <asm/arch/ddr_defs.h>
+ #include <asm/arch/sys_proto.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/mem.h>
+ #include <video_fb.h>
+ #include <asm/arch/da8xx-fb.h>
+
+ #include "flash.h"
+
+ #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
+ #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
+ #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
+ #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
+ #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
+
+ #define GMII_SEL (CTRL_BASE + 0x650)
+
+ /* UART Defines */
+ #define UART_SYSCFG_OFFSET 0x54
+ #define UART_SYSSTS_OFFSET 0x58
+
+ #define UART_RESET (0x1 << 1)
+ #define UART_RESETDONE (1 << 0)
+ #define UART_IDLE_MODE(m) (((m) << 3) & UART_IDLE_MODE_MASK)
+ #define UART_IDLE_MODE_MASK (0x3 << 3)
+
+ /* Timer Defines */
+ #define TSICR_REG 0x54
+ #define TIOCP_CFG_REG 0x10
+ #define TCLR_REG 0x38
+
+ /* RGMII mode define */
+ #define RGMII_MODE_ENABLE 0xA
+ #define RMII_MODE_ENABLE 0x5
+ #define MII_MODE_ENABLE 0x0
+
+ #define NO_OF_MAC_ADDR 1
+ #define ETH_ALEN 6
+
+ /* PAD Control Fields */
+ #define SLEWCTRL (0x1 << 6)
+ #define RXACTIVE (0x1 << 5)
+ #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+ #define PULLUDEN (0x0 << 3) /* Pull up enabled */
+ #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+ #define MODE(val) (val)
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+ struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+ };
+
+ struct pin_mux {
+ short reg_offset;
+ uint8_t val;
+ };
+
+ #define PAD_CTRL_BASE 0x800
+ #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+ static struct pin_mux tx48_pins[] = {
+ #ifdef CONFIG_CMD_NAND
+ { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */
+ { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */
+ { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */
+ { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */
+ { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */
+ { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */
+ { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */
+ { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */
+ { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */
+ { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */
+ { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */
+ { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */
+ { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */
+ { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */
+ { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */
+ #endif
+ /* I2C0 */
+ { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */
+ { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */
+
+ #ifndef CONFIG_NO_ETH
+ /* RMII1 */
+ { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */
+ { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */
+ { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */
+ { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */
+ { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */
+ { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */
+ { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */
+ { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */
+ { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */
+ { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */
+ { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */
+ { OFFSET(emu1), MODE(7), }, /* nRST */
+ #endif
+ };
+
+ static struct gpio tx48_gpios[] = {
+ /* configure this pin early to prevent flicker of the LCD */
++ { TX48_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ };
+
+ static struct pin_mux tx48_mmc_pins[] = {
+ #ifdef CONFIG_OMAP_HSMMC
+ /* MMC1 */
+ { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */
+ { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */
+ { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */
+ { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */
+ { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */
+ { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */
+ { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */
+ #endif
+ };
+
+ /*
+ * Configure the pin mux for the module
+ */
+ static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
+ int num_pins)
+ {
+ int i;
+
+ for (i = 0; i < num_pins; i++)
+ writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
+ }
+
+ static struct pin_mux tx48_uart0_pins[] = {
+ #ifdef CONFIG_SYS_NS16550_COM1
+ /* UART0 for early boot messages */
+ { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */
+ { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */
+ { OFFSET(uart0_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART0_CTS */
+ { OFFSET(uart0_rtsn), MODE(0) | PULLUDEN, }, /* UART0_RTS */
+ #endif
+ #ifdef CONFIG_SYS_NS16550_COM2
+ /* UART1 */
+ { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */
+ { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */
+ { OFFSET(uart1_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART1_CTS */
+ { OFFSET(uart1_rtsn), MODE(0) | PULLUDEN, }, /* UART1_RTS */
+ #endif
+ #ifdef CONFIG_SYS_NS16550_COM3
+ /* UART5 */
+ { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART5_RXD */
+ { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART5_TXD */
+ { OFFSET(mmc0_dat1), MODE(2) | PULLUP_EN | RXACTIVE, }, /* UART5_CTS */
+ { OFFSET(mmc0_dat0), MODE(2) | PULLUDEN, }, /* UART5_RTS */
+ #endif
+ };
+
+ /*
+ * early system init of muxing and clocks.
+ */
+ static void enable_uart0_pin_mux(void)
+ {
+ tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins));
+ }
+
+ static void enable_mmc0_pin_mux(void)
+ {
+ tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins));
+ }
+
+ static const u32 gpmc_nand_cfg[GPMC_MAX_REG] = {
+ TX48_NAND_GPMC_CONFIG1,
+ TX48_NAND_GPMC_CONFIG2,
+ TX48_NAND_GPMC_CONFIG3,
+ TX48_NAND_GPMC_CONFIG4,
+ TX48_NAND_GPMC_CONFIG5,
+ TX48_NAND_GPMC_CONFIG6,
+ };
+
+ #define SDRAM_CLK CONFIG_SYS_DDR_CLK
+
+ #define ns_TO_ck(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+ #define ck_TO_ns(ck) ((ck) * 1000 / SDRAM_CLK)
+
+ #ifdef DEBUG
+ static inline unsigned ck_val_check(unsigned ck, unsigned offs, unsigned max,
+ const char *name)
+ {
+ if (ck < offs) {
+ printf("value %u for parameter %s is out of range (min: %u\n",
+ ck, name, offs);
+ hang();
+ }
+ if (ck > max) {
+ printf("value %u for parameter %s is out of range (max: %u\n",
+ ck, name, max);
+ hang();
+ }
+ return ck - offs;
+ }
+ #define CK_VAL(ck, offs, max) ck_val_check(ck, offs, max, #ck)
+ #else
+ #define CK_VAL(ck, offs, max) ((ck) - (offs))
+ #endif
+
+ #define DDR3_NT5CB128 1
+ #define DDR3_H5TQ2G8 2
+
+ #if 1
+ #define SDRAM_TYPE DDR3_NT5CB128
+ #else
+ #define SDRAM_TYPE DDR3_H5TQ2G8
+ #endif
+
+ #ifndef SDRAM_TYPE
+ #error No SDRAM_TYPE specified
+ #elif (SDRAM_TYPE == DDR3_NT5CB128) || (SDRAM_TYPE == DDR3_H5TQ2G8)
+ #define tRP ns_TO_ck(14)
+ #define tRCD ns_TO_ck(14)
+ #define tWR ns_TO_ck(15)
+ #define tRAS ns_TO_ck(35)
+ #define tRC ns_TO_ck(49)
+ #define tRRD max(ns_TO_ck(8), 4)
+ #define tWTR max(ns_TO_ck(8), 4)
+
+ #define tXP max(ns_TO_ck(6), 3)
+ #define tXPR max(5, ns_TO_ck(ck_TO_ns(tRFC + 1) + 10))
+ #define tODT ns_TO_ck(9)
+ #define tXSNR max(5, ns_TO_ck(ck_TO_ns(tRFC + 1) + 10))
+ #define tXSRD 512
+ #define tRTP max(ns_TO_ck(8), 4)
+ #define tCKE max(ns_TO_ck(6), 3)
+
+ #define tPDLL_UL 512
+ #define tZQCS 64
+ #define tRFC ns_TO_ck(160)
+ #define tRAS_MAX 0xf
+
+ static inline int cwl(u32 sdram_clk)
+ {
+ if (sdram_clk <= 300)
+ return 5;
+ else if (sdram_clk > 300 && sdram_clk <= 333)
+ return 5;
+ else if (sdram_clk > 333 && sdram_clk <= 400)
+ return 5;
+ else if (sdram_clk > 400 && sdram_clk <= 533)
+ return 6;
+ else if (sdram_clk > 533 && sdram_clk <= 666)
+ return 7;
+ else if (SDRAM_TYPE != DDR3_H5TQ2G8)
+ ;
+ else if (sdram_clk > 666 && sdram_clk <= 800)
+ return 8;
+
+ printf("SDRAM clock out of range\n");
+ hang();
+ }
+ #define CWL cwl(SDRAM_CLK)
+
+ static inline int cl(u32 sdram_clk)
+ {
+ if (sdram_clk <= 300)
+ return 5;
+ else if (sdram_clk > 300 && sdram_clk <= 333)
+ return 5;
+ else if (sdram_clk > 333 && sdram_clk <= 400)
+ return 6;
+ else if (sdram_clk > 400 && sdram_clk <= 533)
+ return 8;
+ else if (sdram_clk > 533 && sdram_clk <= 666)
+ return (SDRAM_TYPE == DDR3_H5TQ2G8) ? 10 : 9;
+ else if (SDRAM_TYPE != DDR3_H5TQ2G8)
+ ;
+ else if (sdram_clk > 666 && sdram_clk <= 800)
+ return 11;
+
+ printf("SDRAM clock out of range\n");
+ hang();
+ }
+ #define CL cl(SDRAM_CLK)
+
+ #define ROW_ADDR_BITS 14
+ #define SDRAM_PG_SIZE 1024
+ #else
+ #error Unsupported SDRAM_TYPE specified
+ #endif
+
+ #define SDRAM_CONFIG_VAL ( \
+ (3 << 29) /* SDRAM type: 0: DDR1 1: LPDDR1 2: DDR2 3: DDR3 */ | \
+ (0 << 27) /* IBANK pos */ | \
+ (2 << 24) /* termination resistor value 0: disable 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ | \
+ (0 << 23) /* DDR2 differential DQS */ | \
+ (1 << 21) /* dynamic ODT 0: off 1: RZQ/4 2: RZQ/2 */ | \
+ (0 << 20) /* DLL disable */ | \
+ (1 << 18) /* drive strength 0: RZQ/6 1: RZQ/7 */ | \
+ ((CWL - 5) << 16) /* CWL 0: 5 ... 3: 8 */ | \
+ (1 << 14) /* SDRAM data bus width 0: 32 1: 16 */ | \
+ (((CL - 4) * 2) << 10) /* CAS latency 2: 5 4: 6 6: 8 ... 14: 11 (DDR3) */ | \
+ ((ROW_ADDR_BITS - 9) << 7) /* # of row addr bits 0: 9 ... 7: 16 */ | \
+ (3 << 4) /* # of SDRAM internal banks 0: 1 1: 2 2: 4 3: 8 */ | \
+ (0 << 3) /* # of CS lines */ | \
+ ((ffs(SDRAM_PG_SIZE / 256) - 1) << 0) /* page size 0: 256 1: 512 2: 1024 3:2048 */ | \
+ 0)
+
+ #define SDREF_VAL ( \
+ (0 << 31) /* */ | \
+ (1 << 29) /* self refresh temperature range 1: extended temp range */ | \
+ (0 << 28) /* auto self refresh enable */ | \
+ (0 << 24) /* partial array self refresh */ | \
+ ((SDRAM_CLK * 7800 / 1000) << 0) /* refresh interval */ | \
+ 0)
+
+ #define tFAW ns_TO_ck(45)
+
+ #define SDRAM_TIM1_VAL ((CK_VAL(tRP, 1, 16) << 25) | \
+ (CK_VAL(tRCD, 1, 16) << 21) | \
+ (CK_VAL(tWR, 1, 16) << 17) | \
+ (CK_VAL(tRAS, 1, 32) << 12) | \
+ (CK_VAL(tRC, 1, 64) << 6) | \
+ (CK_VAL(tRRD, 1, 8) << 3) | \
+ (CK_VAL(tWTR, 1, 8) << 0))
+
+ #define SDRAM_TIM2_VAL ((CK_VAL(max(tCKE, tXP), 1, 8) << 28) | \
+ (CK_VAL(tODT, 0, 8) << 25) | \
+ (CK_VAL(tXSNR, 1, 128) << 16) | \
+ (CK_VAL(tXSRD, 1, 1024) << 6) | \
+ (CK_VAL(tRTP, 1, 8) << 3) | \
+ (CK_VAL(tCKE, 1, 8) << 0))
+
+ #define SDRAM_TIM3_VAL ((CK_VAL(DIV_ROUND_UP(tPDLL_UL, 128), 0, 16) << 28) | \
+ (CK_VAL(tZQCS, 1, 64) << 15) | \
+ (CK_VAL(tRFC, 1, 1024) << 4) | \
+ (CK_VAL(tRAS_MAX, 0, 16) << 0))
+
+ #define ZQ_CONFIG_VAL ( \
+ (1 << 31) /* ZQ calib for CS1 */ | \
+ (0 << 30) /* ZQ calib for CS0 */ | \
+ (0 << 29) /* dual calib */ | \
+ (1 << 28) /* ZQ calib on SR/PWDN exit */ | \
+ (2 << 18) /* ZQCL intervals for ZQINIT */ | \
+ (4 << 16) /* ZQCS intervals for ZQCL */ | \
+ (80 << 0) /* refr periods between ZQCS commands */ | \
+ 0)
+
+ static struct ddr_data tx48_ddr3_data = {
+ /* reset defaults */
+ .datardsratio0 = 0x04010040,
+ .datawdsratio0 = 0x0,
+ .datafwsratio0 = 0x0,
+ .datawrsratio0 = 0x04010040,
+ .datadldiff0 = 0x4,
+ };
+
+ static struct cmd_control tx48_ddr3_cmd_ctrl_data = {
+ /* reset defaults */
+ .cmd0csratio = 0x80,
+ .cmd0dldiff = 0x04,
+ .cmd1csratio = 0x80,
+ .cmd1dldiff = 0x04,
+ .cmd2csratio = 0x80,
+ .cmd2dldiff = 0x04,
+ };
+
+ static void ddr3_calib_start(void)
+ {
+ static struct emif_reg_struct *emif_reg = (void *)EMIF4_0_CFG_BASE;
+ int loops = 0;
+ u32 regval;
+ u32 emif_status;
+
+ debug("Starting DDR3 calibration\n");
+
+ /* wait for DDR PHY ready */
+ while (!((emif_status = readl(&emif_reg->emif_status)) & (1 << 2))) {
+ if (loops++ > 100000)
+ break;
+ udelay(1);
+ }
+ debug("EMIF status: %08x after %u loops\n", emif_status, loops);
+
+ /* enable DDR3 write levelling */
+ loops = 0;
+ writel(EMIF_REG_RDWRLVLFULL_START_MASK, &emif_reg->emif_rd_wr_lvl_ctl);
+ do {
+ regval = readl(&emif_reg->emif_rd_wr_lvl_ctl);
+ if (!(regval & EMIF_REG_RDWRLVLFULL_START_MASK))
+ break;
+ udelay(1);
+ } while (loops++ < 100000);
+ if (regval & EMIF_REG_RDWRLVLFULL_START_MASK) {
+ printf("Full WRLVL timed out\n");
+ } else {
+ debug("Full Write Levelling done after %u us\n", loops);
+ }
+ writel(0, &emif_reg->emif_rd_wr_lvl_rmp_ctl);
+ writel(0, &emif_reg->emif_rd_wr_lvl_rmp_win);
+ writel(0x0f808080, &emif_reg->emif_rd_wr_lvl_ctl);
+ debug("DDR3 calibration done\n");
+ }
+
+ static void tx48_ddr_init(void)
+ {
+ struct emif_regs r = {0};
+
+ debug("Initialising SDRAM timing for %u MHz DDR clock\n", SDRAM_CLK);
+
+ r.sdram_config = SDRAM_CONFIG_VAL;
+ r.ref_ctrl = SDREF_VAL;
+ r.sdram_tim1 = SDRAM_TIM1_VAL;
+ r.sdram_tim2 = SDRAM_TIM2_VAL;
+ r.sdram_tim3 = SDRAM_TIM3_VAL;
+ r.zq_config = ZQ_CONFIG_VAL;
+ r.emif_ddr_phy_ctlr_1 = 0x0000030b;
+
+ config_ddr(SDRAM_CLK, 0x04, &tx48_ddr3_data,
+ &tx48_ddr3_cmd_ctrl_data, &r, 0);
+
+ ddr3_calib_start();
+
+ debug("%s: config_ddr done\n", __func__);
+ }
+
+ #ifdef CONFIG_HW_WATCHDOG
+ static inline void tx48_wdog_disable(void)
+ {
+ }
+ #else
+ static inline void tx48_wdog_disable(void)
+ {
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ /* WDT1 is already running when the bootloader gets control
+ * Disable it to avoid "random" resets
+ */
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ }
+ #endif
+
+ void s_init(void)
+ {
+ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
+ int timeout = 1000;
+
+ gd = &gdata;
+
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+ save_omap_boot_params();
+
+ /* Setup the PLLs and the clocks for the peripherals */
+ pll_init();
+
+ tx48_wdog_disable();
+
+ enable_uart0_pin_mux();
+
+ /* UART softreset */
+ writel(readl(&uart_base->uartsyscfg) | UART_RESET,
+ &uart_base->uartsyscfg);
+ while (!(readl(&uart_base->uartsyssts) & UART_RESETDONE)) {
+ udelay(1);
+ if (timeout-- <= 0)
+ break;
+ }
+
+ /* Disable smart idle */
+ writel((readl(&uart_base->uartsyscfg) & ~UART_IDLE_MODE_MASK) |
+ UART_IDLE_MODE(1), &uart_base->uartsyscfg);
+
+ preloader_console_init();
+
+ if (timeout <= 0)
+ printf("Timeout waiting for UART RESET\n");
+
+ timer_init();
+
+ tx48_ddr_init();
+
+ gpmc_init();
+ enable_gpmc_cs_config(gpmc_nand_cfg, &gpmc_cfg->cs[0],
+ CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_SIZE);
+
+ /* Enable MMC0 */
+ enable_mmc0_pin_mux();
+
+ gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
+ tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins));
+ }
--- /dev/null
- { AM33XX_GPIO_NR(3, 5), GPIOF_INPUT, "I2C1_SDA", },
- { AM33XX_GPIO_NR(3, 6), GPIOF_INPUT, "I2C1_SCL", },
- { AM33XX_GPIO_NR(3, 8), GPIOF_OUTPUT_INIT_LOW, "ETH_PHY_RESET", },
+ /*
+ * Copyright (C) 2012-2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * based on evm.c
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <miiphy.h>
+ #include <netdev.h>
+ #include <serial.h>
+ #include <libfdt.h>
+ #include <lcd.h>
+ #include <fdt_support.h>
+ #include <nand.h>
+ #include <net.h>
+ #include <linux/mtd/nand.h>
+ #include <linux/fb.h>
+ #include <asm/gpio.h>
+ #include <asm/cache.h>
+ #include <asm/omap_common.h>
+ #include <asm/io.h>
+ #include <asm/arch/cpu.h>
+ #include <asm/arch/hardware.h>
+ #include <asm/arch/mmc_host_def.h>
+ #include <asm/arch/sys_proto.h>
+ #include <asm/arch/clock.h>
+ #include <video_fb.h>
+ #include <asm/arch/da8xx-fb.h>
+
+ #include "../common/karo.h"
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
+ #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
+ #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
+ #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
+ #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
+ #define TX48_MMC_CD_GPIO AM33XX_GPIO_NR(3, 15)
+
+ #define GMII_SEL (CTRL_BASE + 0x650)
+
+ /* UART Defines */
+ #define UART_SYSCFG_OFFSET 0x54
+ #define UART_SYSSTS_OFFSET 0x58
+
+ #define UART_RESET (0x1 << 1)
+ #define UART_CLK_RUNNING_MASK 0x1
+ #define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+ /* Timer Defines */
+ #define TSICR_REG 0x54
+ #define TIOCP_CFG_REG 0x10
+ #define TCLR_REG 0x38
+
+ /* RGMII mode define */
+ #define RGMII_MODE_ENABLE 0xA
+ #define RMII_MODE_ENABLE 0x5
+ #define MII_MODE_ENABLE 0x0
+
+ #define NO_OF_MAC_ADDR 1
+ #define ETH_ALEN 6
+
+ /* PAD Control Fields */
+ #define SLEWCTRL (0x1 << 6)
+ #define RXACTIVE (0x1 << 5)
+ #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+ #define PULLUDEN (0x0 << 3) /* Pull up enabled */
+ #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+ #define MODE(val) (val)
+
+ /*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+ struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+ };
+
+ struct pin_mux {
+ short reg_offset;
+ uint8_t val;
+ };
+
+ #define PAD_CTRL_BASE 0x800
+ #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+ /*
+ * Configure the pin mux for the module
+ */
+ static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
+ int num_pins)
+ {
+ int i;
+
+ for (i = 0; i < num_pins; i++)
+ writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
+ }
+
+ #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
+ #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
+ #define PRM_RSTST_WDT1_RST (1 << 4)
+ #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
+ #define PRM_RSTST_ICEPICK_RST (1 << 9)
+
+ static u32 prm_rstst __attribute__((section(".data")));
+
+ /*
+ * Basic board specific setup
+ */
+ static const struct pin_mux tx48_pads[] = {
+ { OFFSET(i2c0_sda), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
+ { OFFSET(i2c0_scl), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
+ { OFFSET(emu1), MODE(7), }, /* ETH PHY Reset */
+ };
+
+ static const struct pin_mux tx48_i2c_pads[] = {
+ { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
+ { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
+ };
+
+ static const struct gpio tx48_gpios[] = {
- { TX48_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
- { TX48_MMC_CD_GPIO, GPIOF_INPUT, "MMC0 CD", },
++ { AM33XX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "I2C1_SDA", },
++ { AM33XX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "I2C1_SCL", },
++ { AM33XX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "ETH_PHY_RESET", },
+ };
+
+ static const struct pin_mux stk5_pads[] = {
+ /* heartbeat LED */
+ { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
+ /* LCD RESET */
+ { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
+ /* LCD POWER_ENABLE */
+ { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
+ /* LCD Backlight (PWM) */
+ { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
+ /* MMC CD */
+ { OFFSET(mcasp0_fsx), MODE(7) | PULLUDEN | PULLUP_EN, },
+ };
+
+ static const struct gpio stk5_gpios[] = {
- { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
- { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
- { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
++ { TX48_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
++ { TX48_MMC_CD_GPIO, GPIOFLAG_INPUT, "MMC0 CD", },
+ };
+
+ static const struct pin_mux stk5_lcd_pads[] = {
+ /* LCD data bus */
+ { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
+ /* LCD control signals */
+ { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
+ };
+
+ static const struct gpio stk5_lcd_gpios[] = {
- { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
++ { AM33XX_GPIO_NR(1, 19), GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
++ { AM33XX_GPIO_NR(1, 22), GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
++ { AM33XX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ };
+
+ static const struct pin_mux stk5v5_pads[] = {
+ /* CAN transceiver control */
+ { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
+ };
+
+ static const struct gpio stk5v5_gpios[] = {
- .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
++ { AM33XX_GPIO_NR(0, 22), GPIOFLAG_OUTPUT_INIT_HIGH, "CAN XCVR", },
+ };
+
+ #ifdef CONFIG_LCD
+ static u16 tx48_cmap[256];
+ vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1366,
+ .vl_row = 768,
+
- panel_info.vl_bpix = LCD_COLOR24;
++ .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx48_cmap,
+ };
+
+ #define FB_SYNC_OE_LOW_ACT (1 << 31)
+ #define FB_SYNC_CLK_LAT_FALL (1 << 30)
+
+ static struct fb_videomode tx48_fb_modes[] = {
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .refresh = 60,
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ };
+
+ void *lcd_base; /* Start of framebuffer memory */
+ void *lcd_console_address; /* Start of console buffer */
+
+ int lcd_color_fg;
+ int lcd_color_bg;
+
+ short console_col;
+ short console_row;
+
+ static int lcd_enabled = 1;
+ static int lcd_bl_polarity;
+
+ static int lcd_backlight_polarity(void)
+ {
+ return lcd_bl_polarity;
+ }
+
+ void lcd_initcolregs(void)
+ {
+ }
+
+ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+ {
+ }
+
+ void lcd_enable(void)
+ {
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ if (lcd_enabled) {
+ karo_load_splashimage(1);
+
+ debug("Switching LCD on\n");
+ gpio_set_value(TX48_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX48_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
+ }
+ }
+
+ void lcd_disable(void)
+ {
+ if (lcd_enabled) {
+ printf("Disabling LCD\n");
+ da8xx_fb_disable();
+ lcd_enabled = 0;
+ }
+ }
+
+ static void tx48_lcd_panel_setup(struct da8xx_panel *p,
+ struct fb_videomode *fb)
+ {
+ p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
+
+ p->width = fb->xres;
+ p->hbp = fb->left_margin;
+ p->hsw = fb->hsync_len;
+ p->hfp = fb->right_margin;
+
+ p->height = fb->yres;
+ p->vbp = fb->upper_margin;
+ p->vsw = fb->vsync_len;
+ p->vfp = fb->lower_margin;
+
+ p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
+ }
+
+ void lcd_panel_disable(void)
+ {
+ if (lcd_enabled) {
+ debug("Switching LCD off\n");
+ gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
+ gpio_set_value(TX48_LCD_PWR_GPIO, 0);
+ gpio_set_value(TX48_LCD_RST_GPIO, 0);
+ }
+ }
+
+ void lcd_ctrl_init(void *lcdbase)
+ {
+ int color_depth = 24;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx48_fb_modes[0];
+ struct fb_videomode fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ setenv("splashimage", NULL);
+ return;
+ }
+
+ karo_fdt_move_fdt();
+
+ if (video_mode == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres > panel_info.vl_col ||
+ fb_mode.yres > panel_info.vl_row) {
+ printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
+ fb_mode.xres, fb_mode.yres,
+ panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 24:
+ case 16:
+ case 8:
+ color_depth = val;
+ break;
+
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
+ }
+ if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
+ printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
+ p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ panel_info.vl_col = p->xres;
+ panel_info.vl_row = p->yres;
+
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = LCD_COLOR8;
+ break;
+ case 16:
+ panel_info.vl_bpix = LCD_COLOR16;
+ break;
+ default:
-void ft_board_setup(void *blob, bd_t *bd)
++ panel_info.vl_bpix = LCD_COLOR32;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
+ / 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000,
+ PICOS2KHZ(p->pixclock) % 1000);
+
+ if (p != &fb_mode) {
+ int ret;
+
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
+ if (ret)
+ printf("Failed to create new display-timing node from '%s': %d\n",
+ video_mode, ret);
+ }
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
+
+ if (karo_load_splashimage(0) == 0) {
+ struct da8xx_panel da8xx_panel = { };
+
+ debug("Initializing FB driver\n");
+ tx48_lcd_panel_setup(&da8xx_panel, p);
+ da8xx_video_init(&da8xx_panel, color_depth);
+
+ debug("Initializing LCD controller\n");
+ video_hw_init();
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+ }
+ #else
+ #define lcd_enabled 0
+ #endif /* CONFIG_LCD */
+
+ static void stk5_board_init(void)
+ {
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
+ }
+
+ static void stk5v3_board_init(void)
+ {
+ stk5_board_init();
+ }
+
+ static void stk5v5_board_init(void)
+ {
+ stk5_board_init();
+
+ gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
+ tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
+ }
+
+ /* called with default environment! */
+ int board_init(void)
+ {
+ int i;
+
+ /* mach type passed to kernel */
+ #ifdef CONFIG_OF_LIBFDT
+ gd->bd->bi_arch_number = -1;
+ #endif
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ if (ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
+ if (prm_rstst & PRM_RSTST_WDT1_RST)
+ printf("WDOG RESET detected\n");
+ else
+ printf("<CTRL-C> detected; safeboot enabled\n");
+ }
+
+ gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
+ tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_pads));
+
+ for (i = 0; i < ARRAY_SIZE(tx48_gpios); i++) {
+ int gpio = tx48_gpios[i].gpio;
+
+ if (gpio_get_value(gpio) == 0)
+ gpio_direction_output(gpio, 1);
+ }
+
+ tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_i2c_pads));
+ return 0;
+ }
+
+ static void show_reset_cause(u32 prm_rstst)
+ {
+ const char *dlm = "";
+
+ printf("RESET cause: ");
+ if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
+ printf("%sSW", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_WDT1_RST) {
+ printf("%sWATCHDOG", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
+ printf("%sWARM", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
+ printf("%sJTAG", dlm);
+ dlm = " | ";
+ }
+ if (*dlm == '\0')
+ printf("unknown");
+
+ printf(" RESET\n");
+ }
+
+ /* called with default environment! */
+ int checkboard(void)
+ {
+ prm_rstst = readl(PRM_RSTST);
+ show_reset_cause(prm_rstst);
+
+ printf("Board: Ka-Ro TX48-7020\n");
+
+ timer_init();
+ return 0;
+ }
+
+ static void tx48_set_cpu_clock(void)
+ {
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+ unsigned long act_cpu_clk;
+
+ if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
+ return;
+
+ if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
+ printf("%s detected; skipping cpu clock change\n",
+ (prm_rstst & PRM_RSTST_WDT1_RST) ?
+ "WDOG RESET" : "<CTRL-C>");
+ return;
+ }
+
+ mpu_pll_config_val(cpu_clk);
+
+ act_cpu_clk = mpu_clk_rate();
+ if (cpu_clk * 1000000 != act_cpu_clk) {
+ printf("Failed to set CPU clock to %lu MHz; using %lu.%03lu MHz instead\n",
+ cpu_clk, act_cpu_clk / 1000000,
+ act_cpu_clk / 1000 % 1000);
+ } else {
+ printf("CPU clock set to %lu.%03lu MHz\n",
+ act_cpu_clk / 1000000, act_cpu_clk / 1000 % 1000);
+ }
+ }
+
+ static void tx48_init_mac(void)
+ {
+ uint8_t mac_addr[ETH_ALEN];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = __raw_readl(MAC_ID0_LO);
+ mac_hi = __raw_readl(MAC_ID0_HI);
+
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!is_valid_ether_addr(mac_addr)) {
+ printf("No valid MAC address programmed\n");
+ return;
+ }
+ printf("MAC addr from fuse: %pM\n", mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ /* called with environment from NAND or MMC */
+ int board_late_init(void)
+ {
+ int ret = 0;
+ const char *baseboard;
+
+ env_cleanup();
+
+ tx48_set_cpu_clock();
+
+ if (had_ctrlc())
+ setenv_ulong("safeboot", 1);
+ else if (prm_rstst & PRM_RSTST_WDT1_RST)
+ setenv_ulong("wdreset", 1);
+ else
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ printf("Baseboard: %s\n", baseboard);
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+ exit:
+ tx48_init_mac();
+ clear_ctrlc();
+ return ret;
+ }
+
+ #ifdef CONFIG_DRIVER_TI_CPSW
+ static void tx48_phy_init(void)
+ {
+ debug("%s: Resetting ethernet PHY\n", __func__);
+
+ gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
+
+ udelay(100);
+
+ /* Release nRST */
+ gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
+
+ /* Wait for PHY internal POR signal to deassert */
+ udelay(25000);
+ }
+
+ static void cpsw_control(int enabled)
+ {
+ /* nothing for now */
+ /* TODO : VTP was here before */
+ }
+
+ static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+ };
+
+ void s_init(void)
+ {
+ /* Nothing to be done here */
+ }
+
+ static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = ARRAY_SIZE(cpsw_slaves),
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .mac_control = (1 << 5) /* MIIEN */,
+ .control = cpsw_control,
+ .gigabit_en = 0,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+ };
+
+ int board_eth_init(bd_t *bis)
+ {
+ __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
+ __raw_writel(0x5D, GMII_SEL);
+ tx48_phy_init();
+ return cpsw_register(&cpsw_data);
+ }
+ #endif /* CONFIG_DRIVER_TI_CPSW */
+
+ #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+ int cpu_mmc_init(bd_t *bis)
+ {
+ return omap_mmc_init(1, 0, 0, TX48_MMC_CD_GPIO, -1);
+ }
+ #endif
+
+ void tx48_disable_watchdog(void)
+ {
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ while (readl(&wdtimer->wdtwwps) & (1 << 4))
+ ;
+ writel(0xaaaa, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) & (1 << 4))
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ }
+
+ enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+ };
+
+ void show_activity(int arg)
+ {
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX48_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX48_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX48_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+ }
+
+ #ifdef CONFIG_OF_BOARD_SETUP
+ #ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ #include <jffs2/jffs2.h>
+ #include <mtd_node.h>
+ static struct node_info nodes[] = {
+ { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+ { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
+ };
+
+ #else
+ #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+ #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
+
+ static const char *tx48_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+ "ti,am3359-tscadc",
+ };
+
- if (ret)
++int ft_board_setup(void *blob, bd_t *bd)
+ {
+ const char *baseboard = getenv("baseboard");
+ int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
-
++ if (ret) {
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
++ return ret;
++ }
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
+ ARRAY_SIZE(tx48_touchpanels));
+ karo_fdt_fixup_usb_otg(blob, "usb0", "phys", "vcc-supply");
+ karo_fdt_fixup_flexcan(blob, stk5_v5);
+
+ karo_fdt_update_fb_mode(blob, video_mode);
+
+ tx48_disable_watchdog();
+
+ if (get_cpu_rev() == 0) {
+ karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34, "interrupts");
+ karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34,
+ "interrupt-parent");
+ }
++
++ return 0;
+ }
+ #endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
--- /dev/null
++if TARGET_TX51_8XX0
++
++config SYS_BOARD
++ default "tx51"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mx5"
++
++config SYS_CONFIG_NAME
++ default "tx51-8xx0"
++
++endif
++
++if TARGET_TX51_8XX1_2
++
++config SYS_BOARD
++ default "tx51"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mx5"
++
++config SYS_CONFIG_NAME
++ default "tx51-8xx1_2"
++
++endif
--- /dev/null
-# (C) Copyright 2009 DENX Software Engineering
-# Author: John Rigby <jcrigby@gmail.com>
+ #
-# See file CREDITS for list of people who contributed to this
-# project.
++# (C) Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LDSCRIPT := $(BOARDDIR)/u-boot.lds
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := tx51.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
++# SPDX-License-Identifier: GPL-2.0+
+ #
-#########################################################################
+
++obj-y += tx51.o lowlevel_init.o
--- /dev/null
- { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
+ /*
+ * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <libfdt.h>
+ #include <fdt_support.h>
+ #include <lcd.h>
+ #include <netdev.h>
+ #include <mmc.h>
+ #include <fsl_esdhc.h>
+ #include <video_fb.h>
+ #include <ipu.h>
+ #include <mxcfb.h>
+ #include <linux/fb.h>
+ #include <asm/io.h>
+ #include <asm/gpio.h>
+ #include <asm/arch/iomux-mx51.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/crm_regs.h>
+ #include <asm/arch/sys_proto.h>
+
+ #include "../common/karo.h"
+
+ #define TX51_FEC_RST_GPIO IMX_GPIO_NR(2, 14)
+ #define TX51_FEC_PWR_GPIO IMX_GPIO_NR(1, 3)
+ #define TX51_FEC_INT_GPIO IMX_GPIO_NR(3, 18)
+ #define TX51_LED_GPIO IMX_GPIO_NR(4, 10)
+
+ #define TX51_LCD_PWR_GPIO IMX_GPIO_NR(4, 14)
+ #define TX51_LCD_RST_GPIO IMX_GPIO_NR(4, 13)
+ #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
+
+ #define TX51_RESET_OUT_GPIO IMX_GPIO_NR(2, 15)
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define IOMUX_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
+
+ #define FEC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+ #define FEC_PAD_CTRL2 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+ #define GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
+
+ static iomux_v3_cfg_t tx51_pads[] = {
+ /* NAND flash pads are set up in lowlevel_init.S */
+
+ /* RESET_OUT */
+ MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
+
+ /* UART pads */
+ #if CONFIG_MXC_UART_BASE == UART1_BASE
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ MX51_PAD_UART1_RTS__UART1_RTS,
+ MX51_PAD_UART1_CTS__UART1_CTS,
+ #endif
+ #if CONFIG_MXC_UART_BASE == UART2_BASE
+ MX51_PAD_UART2_RXD__UART2_RXD,
+ MX51_PAD_UART2_TXD__UART2_TXD,
+ MX51_PAD_EIM_D26__UART2_RTS,
+ MX51_PAD_EIM_D25__UART2_CTS,
+ #endif
+ #if CONFIG_MXC_UART_BASE == UART3_BASE
+ MX51_PAD_UART3_RXD__UART3_RXD,
+ MX51_PAD_UART3_TXD__UART3_TXD,
+ MX51_PAD_EIM_D18__UART3_RTS,
+ MX51_PAD_EIM_D17__UART3_CTS,
+ #endif
+ /* internal I2C */
+ MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
+ MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
+
+ /* FEC PHY GPIO functions */
+ MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL, /* PHY POWER */
+ MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL, /* PHY RESET */
+ MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
+
+ /* FEC functions */
+ MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
+ MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
+
+ /* strap pins for PHY configuration */
+ MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
+ MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL, /* RXD0/Mode0 */
+ MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL, /* RXD1/Mode1 */
+ MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL, /* RXD2/Mode2 */
+ MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL, /* RXD3/nINTSEL */
+ MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
+ MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL, /* CRS/PHYAD4 */
+
+ /* unusable pins on TX51 */
+ MX51_PAD_GPIO1_0__GPIO1_0,
+ MX51_PAD_GPIO1_1__GPIO1_1,
+ };
+
+ static const struct gpio tx51_gpios[] = {
+ /* RESET_OUT */
- { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
- { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
- { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
++ { TX51_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "RESET_OUT", },
+
+ /* FEC PHY control GPIOs */
- { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
- { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
- { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
- { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
- { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
- { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
- { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
++ { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
++ { TX51_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
++ { TX51_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
+
+ /* FEC PHY strap pins */
- { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
- { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
++ { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
++ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
++ { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
++ { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
++ { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
++ { IMX_GPIO_NR(3, 10), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
++ { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+
+ /* module internal I2C bus */
- { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
- { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
++ { IMX_GPIO_NR(4, 17), GPIOFLAG_INPUT, "I2C1 SDA", },
++ { IMX_GPIO_NR(4, 16), GPIOFLAG_INPUT, "I2C1 SCL", },
+
+ /* Unconnected pins */
- GPIOF_INPUT, "MMC CD");
++ { IMX_GPIO_NR(1, 0), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", },
++ { IMX_GPIO_NR(1, 1), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", },
+ };
+
+ /*
+ * Functions
+ */
+ /* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+ static u32 wrsr __attribute__((section(".data")));
+
+ #define WRSR_POR (1 << 4)
+ #define WRSR_TOUT (1 << 1)
+ #define WRSR_SFTW (1 << 0)
+
+ static void print_reset_cause(void)
+ {
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+ }
+
+ static void tx51_print_cpuinfo(void)
+ {
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n",
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_reset_cause();
+ }
+
+ int board_early_init_f(void)
+ {
+ struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
+
+ gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
+
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
+
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
+
+ writel(0xffcfffff, &ccm_regs->CCGR0);
+ writel(0x003fffff, &ccm_regs->CCGR1);
+ writel(0x030c003c, &ccm_regs->CCGR2);
+ writel(0x000000ff, &ccm_regs->CCGR3);
+ writel(0x00000000, &ccm_regs->CCGR4);
+ writel(0x003fc003, &ccm_regs->CCGR5);
+ writel(0x00000000, &ccm_regs->CCGR6);
+ writel(0x00000000, &ccm_regs->cmeor);
+ #ifdef CONFIG_CMD_BOOTCE
+ /* WinCE fails to enable these clocks */
+ writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
+ writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
+ writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
+ #endif
+ return 0;
+ }
+
+ int board_init(void)
+ {
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+
+ if (ctrlc() || (wrsr & WRSR_TOUT)) {
+ if (wrsr & WRSR_TOUT)
+ printf("WDOG RESET detected\n");
+ else
+ printf("<CTRL-C> detected; safeboot enabled\n");
+ return 1;
+ }
+ return 0;
+ }
+
+ int dram_init(void)
+ {
+ int ret;
+
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+
+ ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
+ CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
+ if (ret)
+ printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
+ CONFIG_SYS_SDRAM_CLK, ret);
+ else
+ debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
+ __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
+ mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
+ CONFIG_SYS_SDRAM_CLK);
+ return ret;
+ }
+
+ void dram_init_banksize(void)
+ {
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ #if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+ #endif
+ }
+
+ #ifdef CONFIG_CMD_MMC
+ static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX51_PAD_SD1_CMD__SD1_CMD,
+ MX51_PAD_SD1_CLK__SD1_CLK,
+ MX51_PAD_SD1_DATA0__SD1_DATA0,
+ MX51_PAD_SD1_DATA1__SD1_DATA1,
+ MX51_PAD_SD1_DATA2__SD1_DATA2,
+ MX51_PAD_SD1_DATA3__SD1_DATA3,
+ /* SD1 CD */
+ MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
+ };
+
+ static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX51_PAD_SD2_CMD__SD2_CMD,
+ MX51_PAD_SD2_CLK__SD2_CLK,
+ MX51_PAD_SD2_DATA0__SD2_DATA0,
+ MX51_PAD_SD2_DATA1__SD2_DATA1,
+ MX51_PAD_SD2_DATA2__SD2_DATA2,
+ MX51_PAD_SD2_DATA3__SD2_DATA3,
+ /* SD2 CD */
+ MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
+ };
+
+ static struct tx51_esdhc_cfg {
+ const iomux_v3_cfg_t *pads;
+ int num_pads;
+ struct fsl_esdhc_cfg cfg;
+ int cd_gpio;
+ } tx51_esdhc_cfg[] = {
+ {
+ .pads = mmc0_pads,
+ .num_pads = ARRAY_SIZE(mmc0_pads),
+ .cfg = {
+ .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = IMX_GPIO_NR(3, 8),
+ },
+ {
+ .pads = mmc1_pads,
+ .num_pads = ARRAY_SIZE(mmc1_pads),
+ .cfg = {
+ .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = IMX_GPIO_NR(3, 6),
+ },
+ };
+
+ static inline struct tx51_esdhc_cfg *to_tx51_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+ {
+ return container_of(cfg, struct tx51_esdhc_cfg, cfg);
+ }
+
+ int board_mmc_getcd(struct mmc *mmc)
+ {
+ struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
+
+ if (cfg->cd_gpio < 0)
+ return cfg->cd_gpio;
+
+ debug("SD card %d is %spresent\n",
+ cfg - tx51_esdhc_cfg,
+ gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
+ return !gpio_get_value(cfg->cd_gpio);
+ }
+
+ int board_mmc_init(bd_t *bis)
+ {
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
+ struct mmc *mmc;
+ struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(cfg->pads,
+ cfg->num_pads);
+ cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ ret = gpio_request_one(cfg->cd_gpio,
- { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
- { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
- { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
- { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
- { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
++ GPIOFLAG_INPUT, "MMC CD");
+ if (ret) {
+ printf("Error %d requesting GPIO%d_%d\n",
+ ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+ continue;
+ }
+
+ debug("%s: Initializing MMC slot %d\n", __func__, i);
+ fsl_esdhc_initialize(bis, &cfg->cfg);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc) > 0)
+ mmc_init(mmc);
+ }
+ return 0;
+ }
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_FEC_MXC
+
+ #ifndef ETH_ALEN
+ #define ETH_ALEN 6
+ #endif
+
+ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+ {
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[1];
+ struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ if (dev_id > 0)
+ return;
+
+ for (i = 0; i < ETH_ALEN; i++)
+ mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
+ }
+
+ static iomux_v3_cfg_t tx51_fec_pads[] = {
+ /* reconfigure strap pins for FEC function */
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
+ };
+
+ /* take bit 4 of PHY address from configured PHY address or
+ * set it to 0 if PHYADDR is -1 (probe for PHY)
+ */
+ #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
+
+ static struct gpio tx51_fec_gpios[] = {
- { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
++ { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
++ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
++ { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
++ { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
++ { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
+ #if PHYAD4
- { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
++ { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+ #else
- { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
++ { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+ #endif
+ };
+
+ int board_eth_init(bd_t *bis)
+ {
+ int ret;
+
+ /* Power up the external phy and assert strap options */
+ gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
+
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX51_FEC_RST_GPIO, 1);
+
+ /* Without this delay the PHY won't work, though nothing in
+ * the datasheets suggests that it should be necessary!
+ */
+ udelay(400);
+ imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
+ ARRAY_SIZE(tx51_fec_pads));
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("cpu_eth_init() failed: %d\n", ret);
+
+ return ret;
+ }
+ #endif /* CONFIG_FEC_MXC */
+
+ enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+ };
+
+ void show_activity(int arg)
+ {
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX51_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX51_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX51_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+ }
+
+ static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
+
+ /* USB PHY reset */
+ MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
+ /* USBOTG OC */
+ MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
+ /* USB PHY clock enable */
+ MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
+ /* USBH1 VBUS enable */
+ MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
+ /* USBH1 OC */
+ MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
+ };
+
+ static const struct gpio stk5_gpios[] = {
- { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
- { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
- { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
- { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
- { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
++ { TX51_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
- .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
++ { IMX_GPIO_NR(1, 4), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
++ { IMX_GPIO_NR(1, 6), GPIOFLAG_INPUT, "USBOTG OC", },
++ { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY reset", },
++ { IMX_GPIO_NR(1, 8), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
++ { IMX_GPIO_NR(1, 9), GPIOFLAG_INPUT, "USBH1 OC", },
+ };
+
+ #ifdef CONFIG_LCD
+ static u16 tx51_cmap[256];
+ vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1600,
+ .vl_row = 1200,
+
- { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
- { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
- { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
++ .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx51_cmap,
+ };
+
+ static struct fb_videomode tx51_fb_modes[] = {
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .refresh = 60,
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ };
+
+ static int lcd_enabled = 1;
+ static int lcd_bl_polarity;
+
+ static int lcd_backlight_polarity(void)
+ {
+ return lcd_bl_polarity;
+ }
+
+ void lcd_enable(void)
+ {
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ if (lcd_enabled) {
+ karo_load_splashimage(1);
+
+ debug("Switching LCD on\n");
+ gpio_set_value(TX51_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX51_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
+ }
+ }
+
+ void lcd_disable(void)
+ {
+ if (lcd_enabled) {
+ printf("Disabling LCD\n");
+ ipuv3_fb_shutdown();
+ }
+ }
+
+ void lcd_panel_disable(void)
+ {
+ if (lcd_enabled) {
+ debug("Switching LCD off\n");
+ gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
+ gpio_set_value(TX51_LCD_RST_GPIO, 0);
+ gpio_set_value(TX51_LCD_PWR_GPIO, 0);
+ }
+ }
+
+ static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX51_PAD_CSI2_VSYNC__GPIO4_13,
+ /* LCD POWER_ENABLE */
+ MX51_PAD_CSI2_HSYNC__GPIO4_14,
+ /* LCD Backlight (PWM) */
+ MX51_PAD_GPIO1_2__GPIO1_2,
+
+ /* Display */
+ MX51_PAD_DISP1_DAT0__DISP1_DAT0,
+ MX51_PAD_DISP1_DAT1__DISP1_DAT1,
+ MX51_PAD_DISP1_DAT2__DISP1_DAT2,
+ MX51_PAD_DISP1_DAT3__DISP1_DAT3,
+ MX51_PAD_DISP1_DAT4__DISP1_DAT4,
+ MX51_PAD_DISP1_DAT5__DISP1_DAT5,
+ MX51_PAD_DISP1_DAT6__DISP1_DAT6,
+ MX51_PAD_DISP1_DAT7__DISP1_DAT7,
+ MX51_PAD_DISP1_DAT8__DISP1_DAT8,
+ MX51_PAD_DISP1_DAT9__DISP1_DAT9,
+ MX51_PAD_DISP1_DAT10__DISP1_DAT10,
+ MX51_PAD_DISP1_DAT11__DISP1_DAT11,
+ MX51_PAD_DISP1_DAT12__DISP1_DAT12,
+ MX51_PAD_DISP1_DAT13__DISP1_DAT13,
+ MX51_PAD_DISP1_DAT14__DISP1_DAT14,
+ MX51_PAD_DISP1_DAT15__DISP1_DAT15,
+ MX51_PAD_DISP1_DAT16__DISP1_DAT16,
+ MX51_PAD_DISP1_DAT17__DISP1_DAT17,
+ MX51_PAD_DISP1_DAT18__DISP1_DAT18,
+ MX51_PAD_DISP1_DAT19__DISP1_DAT19,
+ MX51_PAD_DISP1_DAT20__DISP1_DAT20,
+ MX51_PAD_DISP1_DAT21__DISP1_DAT21,
+ MX51_PAD_DISP1_DAT22__DISP1_DAT22,
+ MX51_PAD_DISP1_DAT23__DISP1_DAT23,
+ MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
+ MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
+ };
+
+ static const struct gpio stk5_lcd_gpios[] = {
- panel_info.vl_bpix = LCD_COLOR24;
++ { TX51_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
++ { TX51_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
++ { TX51_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ };
+
+ void lcd_ctrl_init(void *lcdbase)
+ {
+ int color_depth = 24;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx51_fb_modes[0];
+ struct fb_videomode fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt;
+ int lcd_bus_width;
+ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+ unsigned long di_clk_rate = 65000000;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ setenv("splashimage", NULL);
+ return;
+ }
+
+ karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
+
+ if (video_mode == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres > panel_info.vl_col ||
+ fb_mode.yres > panel_info.vl_row) {
+ printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
+ fb_mode.xres, fb_mode.yres,
+ panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 8:
+ case 16:
+ case 24:
+ case 32:
+ color_depth = val;
+ break;
+
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
+ }
+ if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
+ printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
+ p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ panel_info.vl_col = p->xres;
+ panel_info.vl_row = p->yres;
+
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = LCD_COLOR8;
+ break;
+ case 16:
+ panel_info.vl_bpix = LCD_COLOR16;
+ break;
+ default:
-void ft_board_setup(void *blob, bd_t *bd)
++ panel_info.vl_bpix = LCD_COLOR32;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000,
+ PICOS2KHZ(p->pixclock) % 1000);
+
+ if (p != &fb_mode) {
+ int ret;
+
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
+ if (ret)
+ printf("Failed to create new display-timing node from '%s': %d\n",
+ video_mode, ret);
+ }
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+ switch (lcd_bus_width) {
+ case 24:
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ break;
+
+ case 18:
+ pix_fmt = IPU_PIX_FMT_RGB666;
+ break;
+
+ case 16:
+ pix_fmt = IPU_PIX_FMT_RGB565;
+ break;
+
+ default:
+ lcd_enabled = 0;
+ printf("Invalid LCD bus width: %d\n", lcd_bus_width);
+ return;
+ }
+ if (karo_load_splashimage(0) == 0) {
+ int ret;
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ u32 ccgr4 = readl(&ccm_regs->CCGR4);
+
+ /* MIPI HSC clock is required for initialization */
+ writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
+
+ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3DEX;
+
+ debug("Initializing LCD controller\n");
+ ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+ writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
+ if (ret) {
+ printf("Failed to initialize FB driver: %d\n", ret);
+ lcd_enabled = 0;
+ }
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+ }
+ #else
+ #define lcd_enabled 0
+ #endif /* CONFIG_LCD */
+
+ static void stk5_board_init(void)
+ {
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+ }
+
+ static void stk5v3_board_init(void)
+ {
+ stk5_board_init();
+ }
+
+ static void tx51_set_cpu_clock(void)
+ {
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT))
+ return;
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
+ cpu_clk = mxc_get_clock(MXC_ARM_CLK);
+ printf("CPU clock set to %lu.%03lu MHz\n",
+ cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+ } else {
+ printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ }
+ }
+
+ static void tx51_init_mac(void)
+ {
+ u8 mac[ETH_ALEN];
+
+ imx_get_mac_from_fuse(0, mac);
+ if (!is_valid_ether_addr(mac)) {
+ printf("No valid MAC address programmed\n");
+ return;
+ }
+
+ printf("MAC addr from fuse: %pM\n", mac);
+ eth_setenv_enetaddr("ethaddr", mac);
+ }
+
+ int board_late_init(void)
+ {
+ int ret = 0;
+ const char *baseboard;
+
+ env_cleanup();
+
+ tx51_set_cpu_clock();
+
+ if (had_ctrlc())
+ setenv_ulong("safeboot", 1);
+ else if (wrsr & WRSR_TOUT)
+ setenv_ulong("wdreset", 1);
+ else
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ printf("Baseboard: %s\n", baseboard);
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
+ baseboard);
+ stk5v3_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+ exit:
+ tx51_init_mac();
+
+ gpio_set_value(TX51_RESET_OUT_GPIO, 1);
+ clear_ctrlc();
+ return ret;
+ }
+
+ int checkboard(void)
+ {
+ tx51_print_cpuinfo();
+ #if CONFIG_NR_DRAM_BANKS > 1
+ printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
+ #else
+ printf("Board: Ka-Ro TX51-8xx0\n");
+ #endif
+ return 0;
+ }
+
+ #if defined(CONFIG_OF_BOARD_SETUP)
+ #ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ #include <jffs2/jffs2.h>
+ #include <mtd_node.h>
+ static struct node_info nodes[] = {
+ { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
+ };
+ #else
+ #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+ #endif
+
+ static const char *tx51_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+ };
+
- if (ret)
++int ft_board_setup(void *blob, bd_t *bd)
+ {
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
-
++ if (ret) {
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
++ return ret;
++ }
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
+ ARRAY_SIZE(tx51_touchpanels));
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
+ karo_fdt_update_fb_mode(blob, video_mode);
++
++ return 0;
+ }
+ #endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
--- /dev/null
++if TARGET_TX53
++
++config SYS_BOARD
++ default "tx53"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mx5"
++
++config SYS_CONFIG_NAME
++ default "tx53"
++
++config CMD_ROMUPDATE
++ bool
++
++config MX5
++ bool
++
++config MX53
++ bool
++ default y
++ select CPU_V7
++ select MX5
++
++config TX53
++ bool
++ default y
++ select CC_OPTIMIZE_LIBS_FOR_SPEED
++ select CMD_BMP if LCD
++ select CMD_BOOTCE
++ select CMD_BOOTZ
++ select CMD_CACHE
++ select CMD_I2C if I2C
++ select CMD_MEMINFO
++ select CMD_MEMTEST
++ select CMD_NAND
++ select CMD_NAND_TRIMFFS
++ select CMD_ROMUPDATE
++ select CMD_TIME
++ select DM
++ select DM_GPIO
++ select FDT_FIXUP_PARTITIONS if OF_LIBFDT
++ select GET_FEC_MAC_ADDR_FROM_IIM
++ select IMX_WATCHDOG
++ select MTD_PARTITIONS
++ select MTD_DEVICE
++ select MX53
++ select NAND
++ select NAND_MXC
++ select OF_LIBFDT
++ select OF_BOARD_SETUP
++ select PHYLIB
++ select PHY_SMSC
++ select SYS_I2C
++ select SYS_I2C_MXC
++ select SYS_NAND_USE_FLASH_BBT if NAND_MXC
++
++#
++# variables selected depending on module variant
++#
++
++config SYS_LVDS_IF
++ bool
++
++config NR_DRAM_BANKS
++ int
++ default 1
++
++choice
++ prompt "TX53 module variant"
++
++config TARGET_TX53_X030
++ bool "TX53-8030 and TX53-1030"
++
++config TARGET_TX53_X130
++ bool "TX53-8030 and TX53-1030"
++
++config TARGET_TX53_X131
++ bool "TX53-8131 and TX53-1131"
++
++config TARGET_TX53_1232
++ bool "TX53-1232
++
++endchoice
++
++choice
++ prompt "U-Boot image variant"
++
++config TX53_UBOOT
++ bool "Standard U-Boot image"
++
++config TX53_UBOOT_NOENV
++ bool "U-Boot using only built-in environment"
++
++endchoice
++
++endif
--- /dev/null
-# (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ #
-# See file CREDITS for list of people who contributed to this
-# project.
++# (C) Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-include $(TOPDIR)/config.mk
++# SPDX-License-Identifier: GPL-2.0+
+ #
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := tx53.o
-ifeq ($(CONFIG_CMD_ROMUPDATE),y)
- COBJS += flash.o
-endif
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+
+ LDSCRIPT := $(BOARDDIR)/u-boot.lds
+
++obj-y += lowlevel_init.o tx53.o
++obj-$(CONFIG_CMD_ROMUPDATE) += flash.o
--- /dev/null
- ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1);
+ /*
+ * Copyright (C) 2011-2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <malloc.h>
+ #include <nand.h>
+ #include <errno.h>
+
+ #include <linux/err.h>
+ #include <jffs2/load_kernel.h>
+
+ struct mx53_fcb {
+ u32 rsrvd0;
+ u32 fingerprint;
+ u32 version;
+ u32 rsrvd1[23];
+ u32 fw1_start_page;
+ u32 fw2_start_page;
+ u32 rsrvd2[2];
+ u32 dbbt_search_area;
+ u32 bb_mark_phys_offset;
+ u32 rsrvd3[11];
+ u32 bb_swap;
+ u32 bb_mark_byte;
+ u32 rsrvd4[83];
+ };
+
+ static nand_info_t *mtd = &nand_info[0];
+ static bool doit;
+
+ static inline int calc_bb_offset(struct mx53_fcb *fcb)
+ {
+ int ecc_block_size = 512;
+ int ecc_size = mtd->oobsize / (mtd->writesize / ecc_block_size);
+ int bb_mark_chunk, bb_mark_chunk_offs;
+
+ bb_mark_chunk = mtd->writesize / (ecc_block_size + ecc_size);
+ bb_mark_chunk_offs = mtd->writesize % (ecc_block_size + ecc_size);
+ if (bb_mark_chunk_offs > ecc_block_size) {
+ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
+ bb_mark_chunk_offs);
+ return -EINVAL;
+ }
+ printf("BB mark is in block %d offset %d\n",
+ bb_mark_chunk, bb_mark_chunk_offs);
+
+ return bb_mark_chunk * ecc_block_size + bb_mark_chunk_offs;
+ }
+
+ /*
+ * return number of blocks to skip for a contiguous partition
+ * of given # blocks
+ */
+ static int find_contig_space(int block, int num_blocks, int max_blocks)
+ {
+ int skip = 0;
+ int found = 0;
+ int last = block + max_blocks;
+
+ debug("Searching %u contiguous blocks from %d..%d\n",
+ num_blocks, block, block + max_blocks - 1);
+ for (; block < last; block++) {
+ if (nand_block_isbad(mtd, block * mtd->erasesize)) {
+ skip += found + 1;
+ found = 0;
+ debug("Skipping %u blocks to %u\n",
+ skip, block + 1);
+ } else {
+ found++;
+ if (found >= num_blocks) {
+ debug("Found %u good blocks from %d..%d\n",
+ found, block - found + 1, block);
+ return skip;
+ }
+ }
+ }
+ return -ENOSPC;
+ }
+
+ #define offset_of(p, m) ((void *)&(p)->m - (void *)(p))
+ #define pr_fcb_val(p, n) debug("%-24s[%02x]=%08x(%d)\n", #n, offset_of(p, n), (p)->n, (p)->n)
+
+ static struct mx53_fcb *create_fcb(void *buf, int fw1_start_block,
+ int fw2_start_block, int fw_num_blocks)
+ {
+ struct mx53_fcb *fcb;
+ u32 sectors_per_block = mtd->erasesize / mtd->writesize;
+
+ fcb = buf;
+
+ memset(fcb, 0x00, sizeof(*fcb));
+ memset(fcb + 1, 0xff, mtd->erasesize - sizeof(*fcb));
+
+ strncpy((char *)&fcb->fingerprint, "FCB ", 4);
+ fcb->version = 1;
+
+ fcb->fw1_start_page = fw1_start_block * sectors_per_block;
+ pr_fcb_val(fcb, fw1_start_page);
+
+ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
+ fcb->fw2_start_page = fw2_start_block * sectors_per_block;
+ pr_fcb_val(fcb, fw2_start_page);
+ }
+
+ return fcb;
+ }
+
+ static int find_fcb(void *ref, int page)
+ {
+ int ret = 0;
+ struct nand_chip *chip = mtd->priv;
+ void *buf = malloc(mtd->erasesize);
+
+ if (buf == NULL) {
+ return -ENOMEM;
+ }
+ chip->select_chip(mtd, 0);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
+ if (ret) {
+ printf("Failed to read FCB from page %u: %d\n", page, ret);
+ goto out;
+ }
+ if (memcmp(buf, ref, mtd->writesize) == 0) {
+ debug("Found FCB in page %u (%08x)\n",
+ page, page * mtd->writesize);
+ ret = 1;
+ }
+ out:
+ chip->select_chip(mtd, -1);
+ free(buf);
+ return ret;
+ }
+
+ static int write_fcb(void *buf, int block)
+ {
+ int ret;
+ struct nand_chip *chip = mtd->priv;
+ int page = block * mtd->erasesize / mtd->writesize;
+
+ ret = find_fcb(buf, page);
+ if (ret > 0) {
+ printf("FCB at block %d is up to date\n", block);
+ return 0;
+ }
+
+ printf("Erasing FCB block %08x..%08x\n", block * mtd->erasesize,
+ block * mtd->erasesize + mtd->erasesize - 1);
+ if (doit) {
+ ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize);
+ if (ret) {
+ printf("Failed to erase FCB block %u\n", block);
+ return ret;
+ }
+ }
+
+ printf("Writing FCB to block %d @ %08llx\n", block,
+ (u64)block * mtd->erasesize);
+ if (doit) {
+ chip->select_chip(mtd, 0);
++ ret = chip->write_page(mtd, chip, 0, mtd->writesize,
++ buf, 1, page, 0, 0);
+ if (ret) {
+ printf("Failed to write FCB to block %u: %d\n", block, ret);
+ }
+ chip->select_chip(mtd, -1);
+ }
+ return ret;
+ }
+
+ #define chk_overlap(a,b) \
+ ((a##_start_block <= b##_end_block && \
+ a##_end_block >= b##_start_block) || \
+ (b##_start_block <= a##_end_block && \
+ b##_end_block >= a##_start_block))
+
+ #define fail_if_overlap(a,b,m1,m2) do { \
+ if (!doit) \
+ printf("check: %s[%lu..%lu] <> %s[%lu..%lu]\n", \
+ m1, a##_start_block, a##_end_block, \
+ m2, b##_start_block, b##_end_block); \
+ if (a##_end_block < a##_start_block) \
+ printf("Invalid start/end block # for %s\n", m1); \
+ if (b##_end_block < b##_start_block) \
+ printf("Invalid start/end block # for %s\n", m2); \
+ if (chk_overlap(a, b)) { \
+ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \
+ m1, a##_start_block, a##_end_block, \
+ m2, b##_start_block, b##_end_block); \
+ return -EINVAL; \
+ } \
+ } while (0)
+
+ static int tx53_prog_uboot(void *addr, int start_block, int skip,
+ size_t size, size_t max_len)
+ {
+ int ret;
+ nand_erase_options_t erase_opts = { 0, };
+ size_t actual;
+ size_t prg_length = max_len - skip * mtd->erasesize;
+ int prg_start = start_block * mtd->erasesize;
+
+ erase_opts.offset = (start_block - skip) * mtd->erasesize;
+ erase_opts.length = max_len;
+ erase_opts.quiet = 1;
+
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+ if (doit) {
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+ }
+
+ printf("Programming flash @ %08x..%08x from %p\n",
+ prg_start, prg_start + size - 1, addr);
+ if (doit) {
+ actual = size;
+ ret = nand_write_skip_bad(mtd, prg_start, &actual, NULL,
+ prg_length, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ if (actual < size) {
+ printf("Could only write %u of %u bytes\n", actual, size);
+ return -EIO;
+ }
+ }
+ return 0;
+ }
+
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ #ifndef CONFIG_ENV_OFFSET_REDUND
+ #define TOTAL_ENV_SIZE CONFIG_ENV_RANGE
+ #else
+ #define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2)
+ #endif
+ #endif
+
+ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int ret;
+ const unsigned long fcb_start_block = 0, fcb_end_block = 0;
+ int erase_size = mtd->erasesize;
+ int page_size = mtd->writesize;
+ void *buf;
+ char *load_addr;
+ char *file_size;
+ size_t size = 0;
+ void *addr = NULL;
+ struct mx53_fcb *fcb;
+ unsigned long mtd_num_blocks = mtd->size / mtd->erasesize;
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize;
+ unsigned long env_end_block = env_start_block +
+ DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1;
+ #endif
+ int optind;
+ int fw2_set = 0;
+ unsigned long fw1_start_block = 0, fw1_end_block;
+ unsigned long fw2_start_block = 0, fw2_end_block;
+ unsigned long fw_num_blocks;
+ int fw1_skip, fw2_skip;
+ unsigned long extra_blocks = 0;
+ size_t max_len1, max_len2;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ struct part_info *redund_part_info;
+ const char *uboot_part = "u-boot";
+ const char *redund_part = NULL;
+ u8 part_num;
+ u8 redund_part_num;
+
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ doit = true;
+ for (optind = 1; optind < argc; optind++) {
+ char *endp;
+
+ if (strcmp(argv[optind], "-f") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fw1_start_block = simple_strtoul(argv[optind], &endp, 0);
+ if (*endp != '\0') {
+ uboot_part = argv[optind];
+ continue;
+ }
+ uboot_part = NULL;
+ if (fw1_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw1_start_block, mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-r") == 0) {
+ fw2_set = 1;
+ if (optind < argc - 1 && argv[optind + 1][0] != '-') {
+ optind++;
+ fw2_start_block = simple_strtoul(argv[optind],
+ &endp, 0);
+ if (*endp != '\0') {
+ redund_part = argv[optind];
+ continue;
+ }
+ if (fw2_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw2_start_block,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ }
+ } else if (strcmp(argv[optind], "-e") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ extra_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (extra_blocks >= mtd_num_blocks) {
+ printf("Extra block count %lu is out of range: 0..%lu\n",
+ extra_blocks,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-n") == 0) {
+ doit = false;
+ } else if (argv[optind][0] == '-') {
+ printf("Unrecognized option %s\n", argv[optind]);
+ return -EINVAL;
+ } else {
+ break;
+ }
+ }
+
+ load_addr = getenv("fileaddr");
+ file_size = getenv("filesize");
+
+ if (argc - optind < 1 && load_addr == NULL) {
+ printf("Load address not specified\n");
+ return -EINVAL;
+ }
+ if (argc - optind < 2 && file_size == NULL) {
+ if (uboot_part) {
+ printf("WARNING: Image size not specified; overwriting whole '%s' partition\n",
+ uboot_part);
+ printf("This will only work, if there are no bad blocks inside this partition!\n");
+ } else {
+ printf("ERROR: Image size must be specified\n");
+ return -EINVAL;
+ }
+ }
+ if (argc > optind) {
+ load_addr = NULL;
+ addr = (void *)simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (argc > optind) {
+ file_size = NULL;
+ size = simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (load_addr != NULL) {
+ addr = (void *)simple_strtoul(load_addr, NULL, 16);
+ printf("Using default load address %p\n", addr);
+ }
+ if (file_size != NULL) {
+ size = simple_strtoul(file_size, NULL, 16);
+ printf("Using default file size %08x\n", size);
+ }
+ if (size > 0)
+ fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize);
+ else
+ fw_num_blocks = 0;
+
+ if (uboot_part) {
+ ret = find_dev_and_part(uboot_part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ uboot_part, ret);
+ return ret;
+ }
+ fw1_start_block = part_info->offset / mtd->erasesize;
+ max_len1 = part_info->size;
+ /*
+ * Skip one block, if the U-Boot image resides in the
+ * same partition as the FCB
+ */
+ if (fw1_start_block == fcb_start_block) {
+ fw1_start_block++;
+ max_len1 -= mtd->erasesize;
+ }
+ if (size == 0)
+ fw_num_blocks = max_len1 / mtd->erasesize;
+ } else {
+ max_len1 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
+ }
+
+ if (redund_part) {
+ ret = find_dev_and_part(redund_part, &dev, &redund_part_num,
+ &redund_part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ redund_part, ret);
+ return ret;
+ }
+ fw2_start_block = redund_part_info->offset / mtd->erasesize;
+ max_len2 = redund_part_info->size;
+ if (fw2_start_block == fcb_start_block) {
+ fw2_start_block++;
+ max_len2 -= mtd->erasesize;
+ }
+ if (size == 0)
+ fw_num_blocks = max_len2 / mtd->erasesize;
+ } else if (fw2_set) {
+ max_len2 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
+ } else {
+ max_len2 = 0;
+ }
+
+ fw1_skip = find_contig_space(fw1_start_block, fw_num_blocks,
+ max_len1 / mtd->erasesize);
+ if (fw1_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for fw image in blocks %lu..%lu\n",
+ fw_num_blocks, fw1_start_block,
+ fw1_start_block + max_len1 / mtd->erasesize - 1);
+ if (uboot_part) {
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ if (part_info->offset <= CONFIG_ENV_OFFSET + TOTAL_ENV_SIZE) {
+ printf("Use a different partition\n");
+ } else {
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+ }
+ #else
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+ #endif
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
+ if (extra_blocks)
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ else
+ fw1_end_block = fw1_start_block + fw_num_blocks + fw1_skip - 1;
+
+ if (fw2_set && fw2_start_block == 0)
+ fw2_start_block = fw1_end_block + 1;
+ if (fw2_start_block > 0) {
+ fw2_skip = find_contig_space(fw2_start_block, fw_num_blocks,
+ max_len2 / mtd->erasesize);
+ if (fw2_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for redundant fw image in blocks %lu..%lu\n",
+ fw_num_blocks, fw2_start_block,
+ fw2_start_block + max_len2 / mtd->erasesize - 1);
+ if (redund_part) {
+ printf("Increase the size of the '%s' partition or use a different partition\n",
+ redund_part);
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
+ } else {
+ fw2_skip = 0;
+ }
+ if (extra_blocks)
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ else
+ fw2_end_block = fw2_start_block + fw_num_blocks + fw2_skip - 1;
+
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fcb, env, "FCB", "Environment");
+ fail_if_overlap(fw1, env, "FW1", "Environment");
+ #endif
+ fail_if_overlap(fw1, fcb, "FW1", "FCB");
+ if (fw2_set) {
+ fail_if_overlap(fw2, fcb, "FW2", "FCB");
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fw2, env, "FW2", "Environment");
+ #endif
+ fail_if_overlap(fw1, fw2, "FW1", "FW2");
+ }
+ fw1_start_block += fw1_skip;
+ fw2_start_block += fw2_skip;
+
+ buf = malloc(erase_size);
+ if (buf == NULL) {
+ printf("Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ fcb = create_fcb(buf, fw1_start_block,
+ fw2_start_block, fw_num_blocks);
+ if (IS_ERR(fcb)) {
+ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+ free(buf);
+ return PTR_ERR(fcb);
+ }
+
+ ret = write_fcb(buf, fcb_start_block);
+ free(buf);
+ if (ret) {
+ printf("Failed to write FCB to block %lu\n", fcb_start_block);
+ return ret;
+ }
+
+ if (size & (page_size - 1)) {
+ memset(addr + size, 0xff, size & (page_size - 1));
+ size = ALIGN(size, page_size);
+ }
+
+ printf("Programming U-Boot image from %p to block %lu @ %08llx\n",
+ addr, fw1_start_block, (u64)fw1_start_block * mtd->erasesize);
+ ret = tx53_prog_uboot(addr, fw1_start_block, fw1_skip, size,
+ max_len1);
+ if (ret || fw2_start_block == 0)
+ return ret;
+
+ printf("Programming redundant U-Boot image to block %lu @ %08llx\n",
+ fw2_start_block, (u64)fw2_start_block * mtd->erasesize);
+ ret = tx53_prog_uboot(addr, fw2_start_block, fw2_skip, size,
+ max_len2);
+ return ret;
+ }
+
+ U_BOOT_CMD(romupdate, 11, 0, do_update,
+ "Creates an FCB data structure and writes an U-Boot image to flash",
+ "[-f {<part>|block#}] [-r [{<part>|block#}]] [-e #] [<address>] [<length>]\n"
+ "\t-f <part>\twrite bootloader image to partition <part>\n"
+ "\t-f #\t\twrite bootloader image at block # (decimal)\n"
+ "\t-r\t\twrite redundant bootloader image at next free block after first image\n"
+ "\t-r <part>\twrite redundant bootloader image to partition <part>\n"
+ "\t-r #\t\twrite redundant bootloader image at block # (decimal)\n"
+ "\t-e #\t\tspecify number of redundant blocks per boot loader image\n"
+ "\t\t\t(only valid if -f or -r specify a flash address rather than a partition name)\n"
+ "\t-n\t\tshow what would be done without actually updating the flash\n"
+ "\t<address>\tRAM address of bootloader image (default: ${fileaddr})\n"
+ "\t<length>\tlength of bootloader image in RAM (default: ${filesize})"
+ );
--- /dev/null
- { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
- { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
- { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
- { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
+ /*
+ * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <libfdt.h>
+ #include <fdt_support.h>
+ #include <i2c.h>
+ #include <lcd.h>
+ #include <netdev.h>
+ #include <mmc.h>
+ #include <fsl_esdhc.h>
+ #include <video_fb.h>
+ #include <ipu.h>
+ #include <mxcfb.h>
+ #include <linux/fb.h>
+ #include <asm/io.h>
+ #include <asm/gpio.h>
+ #include <asm/arch/iomux-mx53.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/crm_regs.h>
+ #include <asm/arch/sys_proto.h>
+
+ #include "../common/karo.h"
+
+ #define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
+ #define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
+ #define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
+ #define TX53_LED_GPIO IMX_GPIO_NR(2, 20)
+
+ #define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
+ #define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
+ #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
+
+ #define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
+
+ #define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
+
+ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
+
+ static iomux_v3_cfg_t tx53_pads[] = {
+ /* NAND flash pads are set up in lowlevel_init.S */
+
+ /* UART pads */
+ #if CONFIG_MXC_UART_BASE == UART1_BASE
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+ MX53_PAD_PATA_IORDY__UART1_RTS,
+ MX53_PAD_PATA_RESET_B__UART1_CTS,
+ #endif
+ #if CONFIG_MXC_UART_BASE == UART2_BASE
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+ MX53_PAD_PATA_DIOR__UART2_RTS,
+ MX53_PAD_PATA_INTRQ__UART2_CTS,
+ #endif
+ #if CONFIG_MXC_UART_BASE == UART3_BASE
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
+ MX53_PAD_PATA_DA_2__UART3_RTS,
+ MX53_PAD_PATA_DA_1__UART3_CTS,
+ #endif
+ /* internal I2C */
+ MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
+ MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
+
+ /* FEC PHY GPIO functions */
+ MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
+ MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
+ MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
+
+ /* FEC functions */
+ MX53_PAD_FEC_MDC__FEC_MDC,
+ MX53_PAD_FEC_MDIO__FEC_MDIO,
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1,
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0,
+ };
+
+ static const struct gpio tx53_gpios[] = {
- GPIOF_INPUT, "MMC CD");
++ { TX53_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
++ { TX53_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
++ { TX53_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
++ { TX53_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
+ };
+
+ /*
+ * Functions
+ */
+ /* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+ static u32 wrsr __attribute__((section(".data")));
+
+ #define WRSR_POR (1 << 4)
+ #define WRSR_TOUT (1 << 1)
+ #define WRSR_SFTW (1 << 0)
+
+ static void print_reset_cause(void)
+ {
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+ }
+
+ #define pr_lpgr_val(v, n, b, c) do { \
+ u32 __v = ((v) >> (b)) & ((1 << (c)) - 1); \
+ if (__v) \
+ printf(" %s=%0*x", #n, DIV_ROUND_UP(c, 4), __v); \
+ } while (0)
+
+ static inline void print_lpgr(u32 lpgr)
+ {
+ if (!lpgr)
+ return;
+
+ printf("LPGR=%08x:", lpgr);
+ pr_lpgr_val(lpgr, SW_ISO, 31, 1);
+ pr_lpgr_val(lpgr, SECONDARY_BOOT, 30, 1);
+ pr_lpgr_val(lpgr, BLOCK_REWRITE, 29, 1);
+ pr_lpgr_val(lpgr, WDOG_BOOT, 28, 1);
+ pr_lpgr_val(lpgr, SBMR_SHADOW, 0, 26);
+ printf("\n");
+ }
+
+ static void tx53_print_cpuinfo(void)
+ {
+ u32 cpurev;
+ struct srtc_regs *srtc_regs = (void *)SRTC_BASE_ADDR;
+ u32 lpgr = readl(&srtc_regs->lpgr);
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n",
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_reset_cause();
+
+ print_lpgr(lpgr);
+
+ if (lpgr & (1 << 30))
+ printf("WARNING: U-Boot started from secondary bootstrap image\n");
+
+ if (lpgr) {
+ struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
+ u32 ccgr4 = readl(&ccm_regs->CCGR4);
+
+ writel(ccgr4 | MXC_CCM_CCGR4_SRTC(3), &ccm_regs->CCGR4);
+ writel(0, &srtc_regs->lpgr);
+ writel(ccgr4, &ccm_regs->CCGR4);
+ }
+ }
+
+ enum LTC3589_REGS {
+ LTC3589_SCR1 = 0x07,
+ LTC3589_SCR2 = 0x12,
+ LTC3589_VCCR = 0x20,
+ LTC3589_CLIRQ = 0x21,
+ LTC3589_B1DTV1 = 0x23,
+ LTC3589_B1DTV2 = 0x24,
+ LTC3589_VRRCR = 0x25,
+ LTC3589_B2DTV1 = 0x26,
+ LTC3589_B2DTV2 = 0x27,
+ LTC3589_B3DTV1 = 0x29,
+ LTC3589_B3DTV2 = 0x2a,
+ LTC3589_L2DTV1 = 0x32,
+ LTC3589_L2DTV2 = 0x33,
+ };
+
+ #define LTC3589_BnDTV1_PGOOD_MASK (1 << 5)
+ #define LTC3589_BnDTV1_SLEW(n) (((n) & 3) << 6)
+
+ #define LTC3589_CLK_RATE_LOW (1 << 5)
+
+ #define LTC3589_SCR2_PGOOD_SHUTDWN (1 << 7)
+
+ #define VDD_LDO2_VAL mV_to_regval(vout_to_vref(1325 * 10, 2))
+ #define VDD_CORE_VAL mV_to_regval(vout_to_vref(1100 * 10, 3))
+ #define VDD_SOC_VAL mV_to_regval(vout_to_vref(1325 * 10, 4))
+ #define VDD_BUCK3_VAL mV_to_regval(vout_to_vref(2500 * 10, 5))
+
+ #ifndef CONFIG_SYS_TX53_HWREV_2
+ /* LDO2 vref divider */
+ #define R1_2 180
+ #define R2_2 191
+ /* BUCK1 vref divider */
+ #define R1_3 150
+ #define R2_3 180
+ /* BUCK2 vref divider */
+ #define R1_4 180
+ #define R2_4 191
+ /* BUCK3 vref divider */
+ #define R1_5 270
+ #define R2_5 100
+ #else
+ /* no dividers on vref */
+ #define R1_2 0
+ #define R2_2 1
+ #define R1_3 0
+ #define R2_3 1
+ #define R1_4 0
+ #define R2_4 1
+ #define R1_5 0
+ #define R2_5 1
+ #endif
+
+ /* calculate voltages in 10mV */
+ #define R1(idx) R1_##idx
+ #define R2(idx) R2_##idx
+
+ #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
+ #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
+
+ #define mV_to_regval(mV) DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
+ #define regval_to_mV(v) (((v) * 125 + 3625))
+
+ static struct pmic_regs {
+ enum LTC3589_REGS addr;
+ u8 val;
+ } ltc3589_regs[] = {
+ { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
+ { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
+
+ { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
+ { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
+
+ { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
+ { LTC3589_B1DTV2, VDD_CORE_VAL, },
+
+ { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
+ { LTC3589_B2DTV2, VDD_SOC_VAL, },
+
+ { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
+ { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
+
+ /* Select ref 0 for all regulators and enable slew */
+ { LTC3589_VCCR, 0x55, },
+
+ { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
+ };
+
+ static int setup_pmic_voltages(void)
+ {
+ int ret;
+ unsigned char value;
+ int i;
+
+ ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
+ if (ret != 0) {
+ printf("Failed to initialize I2C\n");
+ return ret;
+ }
+
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
+ if (ret) {
+ printf("%s: i2c_read error: %d\n", __func__, ret);
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
+ &value, 1);
+ debug("Writing %02x to reg %02x (%02x)\n",
+ ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
+ <c3589_regs[i].val, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, ltc3589_regs[i].addr, ret);
+ return ret;
+ }
+ }
+ printf("VDDCORE set to %umV\n",
+ DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
+
+ printf("VDDSOC set to %umV\n",
+ DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
+ return 0;
+ }
+
+ static struct {
+ u32 max_freq;
+ u32 mV;
+ } tx53_core_voltages[] = {
+ { 800000000, 1100, },
+ { 1000000000, 1240, },
+ { 1200000000, 1350, },
+ };
+
+ int adjust_core_voltage(u32 freq)
+ {
+ int ret;
+ int i;
+
+ printf("%s@%d\n", __func__, __LINE__);
+
+ for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
+ if (freq <= tx53_core_voltages[i].max_freq) {
+ int retries = 0;
+ const int max_tries = 10;
+ const int delay_us = 1;
+ u32 mV = tx53_core_voltages[i].mV;
+ u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
+ u8 v;
+
+ debug("regval[%umV]=%02x\n", mV, val);
+
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_B1DTV1, ret);
+ return ret;
+ }
+ debug("Changing reg %02x from %02x to %02x\n",
+ LTC3589_B1DTV1, v, (v & ~0x1f) |
+ mV_to_regval(vout_to_vref(mV * 10, 3)));
+ v &= ~0x1f;
+ v |= mV_to_regval(vout_to_vref(mV * 10, 3));
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, LTC3589_B1DTV1, ret);
+ return ret;
+ }
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ v |= 0x1;
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ for (retries = 0; retries < max_tries; retries++) {
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
+ LTC3589_VCCR, 1, &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ if (!(v & 1))
+ break;
+ udelay(delay_us);
+ }
+ if (v & 1) {
+ printf("change of VDDCORE did not complete after %uµs\n",
+ retries * delay_us);
+ return -ETIMEDOUT;
+ }
+
+ printf("VDDCORE set to %umV after %u loops\n",
+ DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
+ 10), retries);
+ return 0;
+ }
+ }
+ return -EINVAL;
+ }
+
+ int board_early_init_f(void)
+ {
+ struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
+
+ gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
+
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
+
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
+
+ writel(0xffcf0fff, &ccm_regs->CCGR0);
+ writel(0x000fffcf, &ccm_regs->CCGR1);
+ writel(0x033c0000, &ccm_regs->CCGR2);
+ writel(0x000000ff, &ccm_regs->CCGR3);
+ writel(0x00000000, &ccm_regs->CCGR4);
+ writel(0x00fff033, &ccm_regs->CCGR5);
+ writel(0x0f00030f, &ccm_regs->CCGR6);
+ writel(0xfff00000, &ccm_regs->CCGR7);
+ writel(0x00000000, &ccm_regs->cmeor);
+
+ return 0;
+ }
+
+ int board_init(void)
+ {
+ int ret;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+
+ if (ctrlc() || (wrsr & WRSR_TOUT)) {
+ if (wrsr & WRSR_TOUT)
+ printf("WDOG RESET detected; Skipping PMIC setup\n");
+ else
+ printf("<CTRL-C> detected; safeboot enabled\n");
+ return 1;
+ }
+
+ ret = setup_pmic_voltages();
+ if (ret) {
+ printf("Failed to setup PMIC voltages\n");
+ hang();
+ }
+ return 0;
+ }
+
+ int dram_init(void)
+ {
+ int ret;
+
+ /*
+ * U-Boot doesn't support RAM banks with intervening holes,
+ * so let U-Boot only know about the first bank for its
+ * internal data structures. The size reported to Linux is
+ * determined from the individual bank sizes.
+ */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G);
+
+ ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
+ CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
+ if (ret)
+ printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
+ CONFIG_SYS_SDRAM_CLK, ret);
+ else
+ debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
+ __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
+ mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
+ CONFIG_SYS_SDRAM_CLK);
+ return ret;
+ }
+
+ void dram_init_banksize(void)
+ {
+ long total_size = gd->ram_size;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ #if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G);
+
+ if (gd->bd->bi_dram[1].size) {
+ debug("Found %luMiB SDRAM in bank 2\n",
+ gd->bd->bi_dram[1].size / SZ_1M);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ total_size += gd->bd->bi_dram[1].size;
+ }
+ #endif
+ if (total_size != CONFIG_SYS_SDRAM_SIZE)
+ printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n",
+ CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M);
+ }
+
+ #ifdef CONFIG_CMD_MMC
+ static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
+ /* SD1 CD */
+ MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
+ };
+
+ static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
+ /* SD2 CD */
+ MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
+ };
+
+ static struct tx53_esdhc_cfg {
+ const iomux_v3_cfg_t *pads;
+ int num_pads;
+ struct fsl_esdhc_cfg cfg;
+ int cd_gpio;
+ } tx53_esdhc_cfg[] = {
+ {
+ .pads = mmc0_pads,
+ .num_pads = ARRAY_SIZE(mmc0_pads),
+ .cfg = {
+ .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = IMX_GPIO_NR(3, 24),
+ },
+ {
+ .pads = mmc1_pads,
+ .num_pads = ARRAY_SIZE(mmc1_pads),
+ .cfg = {
+ .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = IMX_GPIO_NR(3, 25),
+ },
+ };
+
+ static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+ {
+ return container_of(cfg, struct tx53_esdhc_cfg, cfg);
+ }
+
+ int board_mmc_getcd(struct mmc *mmc)
+ {
+ struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
+
+ if (cfg->cd_gpio < 0)
+ return cfg->cd_gpio;
+
+ debug("SD card %d is %spresent\n",
+ cfg - tx53_esdhc_cfg,
+ gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
+ return !gpio_get_value(cfg->cd_gpio);
+ }
+
+ int board_mmc_init(bd_t *bis)
+ {
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
+ struct mmc *mmc;
+ struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
+ cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ ret = gpio_request_one(cfg->cd_gpio,
- { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
++ GPIOFLAG_INPUT, "MMC CD");
+ if (ret) {
+ printf("Error %d requesting GPIO%d_%d\n",
+ ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+ continue;
+ }
+
+ debug("%s: Initializing MMC slot %d\n", __func__, i);
+ fsl_esdhc_initialize(bis, &cfg->cfg);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc) > 0)
+ mmc_init(mmc);
+ }
+ return 0;
+ }
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_FEC_MXC
+
+ #ifndef ETH_ALEN
+ #define ETH_ALEN 6
+ #endif
+
+ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+ {
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[1];
+ struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ if (dev_id > 0)
+ return;
+
+ for (i = 0; i < ETH_ALEN; i++)
+ mac[i] = readl(&fuse->mac_addr[i]);
+ }
+
+ #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+ #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+ #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+ int board_eth_init(bd_t *bis)
+ {
+ int ret;
+
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX53_FEC_RST_GPIO, 1);
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("cpu_eth_init() failed: %d\n", ret);
+
+ return ret;
+ }
+ #endif /* CONFIG_FEC_MXC */
+
+ enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+ };
+
+ void show_activity(int arg)
+ {
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX53_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX53_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX53_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+ }
+
+ static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX53_PAD_EIM_A18__GPIO2_20,
+
+ /* I2C bus on DIMM pins 40/41 */
+ MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
+ MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
+
+ /* TSC200x PEN IRQ */
+ MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
+
+ /* EDT-FT5x06 Polytouch panel */
+ MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
+ MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
+ MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
+
+ /* USBH1 */
+ MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
+ MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
+ /* USBOTG */
+ MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
+ MX53_PAD_GPIO_8__GPIO1_8, /* OC */
+
+ /* DS1339 Interrupt */
+ MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
+ };
+
+ static const struct gpio stk5_gpios[] = {
- { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
- { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
- { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
- { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
++ { TX53_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
- .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
++ { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
++ { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
++ { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
++ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+ };
+
+ #ifdef CONFIG_LCD
+ static u16 tx53_cmap[256];
+ vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1600,
+ .vl_row = 1200,
+
- { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
- { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
- { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
++ .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx53_cmap,
+ };
+
+ static struct fb_videomode tx53_fb_modes[] = {
+ #ifndef CONFIG_SYS_LVDS_IF
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ #else
+ {
+ /* HannStar HSD100PXN1
+ * 202.7m mm x 152.06 mm display area.
+ */
+ .name = "HSD100PXN1",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = KHZ2PICOS(65000),
+ .left_margin = 0,
+ .hsync_len = 0,
+ .right_margin = 320,
+ .upper_margin = 0,
+ .vsync_len = 0,
+ .lower_margin = 38,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ #endif
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .refresh = 60,
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ };
+
+ static int lcd_enabled = 1;
+ static int lcd_bl_polarity;
+
+ static int lcd_backlight_polarity(void)
+ {
+ return lcd_bl_polarity;
+ }
+
+ void lcd_enable(void)
+ {
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ if (lcd_enabled) {
+ karo_load_splashimage(1);
+
+ debug("Switching LCD on\n");
+ gpio_set_value(TX53_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX53_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
+ }
+ }
+
+ void lcd_disable(void)
+ {
+ if (lcd_enabled) {
+ printf("Disabling LCD\n");
+ ipuv3_fb_shutdown();
+ }
+ }
+
+ void lcd_panel_disable(void)
+ {
+ if (lcd_enabled) {
+ debug("Switching LCD off\n");
+ gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
+ gpio_set_value(TX53_LCD_RST_GPIO, 0);
+ gpio_set_value(TX53_LCD_PWR_GPIO, 0);
+ }
+ }
+
+ static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
+ /* LCD POWER_ENABLE */
+ MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
+ /* LCD Backlight (PWM) */
+ MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
+
+ /* Display */
+ #ifndef CONFIG_SYS_LVDS_IF
+ /* LCD option */
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+ #else
+ /* LVDS option */
+ MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+ MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+ MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+ MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+ MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+ MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+ MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+ MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+ MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+ #endif
+ };
+
+ static const struct gpio stk5_lcd_gpios[] = {
- panel_info.vl_bpix = LCD_COLOR24;
++ { TX53_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
++ { TX53_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
++ { TX53_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ };
+
+ void lcd_ctrl_init(void *lcdbase)
+ {
+ int color_depth = 24;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx53_fb_modes[0];
+ struct fb_videomode fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt;
+ int lcd_bus_width;
+ ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
+ unsigned long di_clk_rate = 65000000;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ setenv("splashimage", NULL);
+ return;
+ }
+
+ karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
+
+ if (video_mode == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres > panel_info.vl_col ||
+ fb_mode.yres > panel_info.vl_row) {
+ printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
+ fb_mode.xres, fb_mode.yres,
+ panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 32:
+ case 24:
+ if (is_lvds())
+ pix_fmt = IPU_PIX_FMT_LVDS888;
+ /* fallthru */
+ case 16:
+ case 8:
+ color_depth = val;
+ break;
+
+ case 18:
+ if (is_lvds()) {
+ color_depth = val;
+ break;
+ }
+ /* fallthru */
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
+ }
+ if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
+ printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
+ p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ panel_info.vl_col = p->xres;
+ panel_info.vl_row = p->yres;
+
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = LCD_COLOR8;
+ break;
+ case 16:
+ panel_info.vl_bpix = LCD_COLOR16;
+ break;
+ default:
- gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
++ panel_info.vl_bpix = LCD_COLOR32;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
+
+ if (p != &fb_mode) {
+ int ret;
+
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
+ if (ret)
+ printf("Failed to create new display-timing node from '%s': %d\n",
+ video_mode, ret);
+ }
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+ switch (lcd_bus_width) {
+ case 24:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
+ break;
+
+ case 18:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
+ break;
+
+ case 16:
+ if (!is_lvds()) {
+ pix_fmt = IPU_PIX_FMT_RGB565;
+ break;
+ }
+ /* fallthru */
+ default:
+ lcd_enabled = 0;
+ printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
+ lcd_bus_width);
+ return;
+ }
+ if (is_lvds()) {
+ int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
+ int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
+ uint32_t gpr2;
+
+ if (lvds_chan_mask == 0) {
+ printf("No LVDS channel active\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
+ if (lcd_bus_width == 24)
+ gpr2 |= (1 << 5) | (1 << 7);
+ gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
+ gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
+ debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+ writel(gpr2, IOMUXC_BASE_ADDR + 8);
+ }
+ if (karo_load_splashimage(0) == 0) {
+ int ret;
+
+ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
+
+ debug("Initializing LCD controller\n");
+ ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+ if (ret) {
+ printf("Failed to initialize FB driver: %d\n", ret);
+ lcd_enabled = 0;
+ }
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+ }
+ #else
+ #define lcd_enabled 0
+ #endif /* CONFIG_LCD */
+
+ static void stk5_board_init(void)
+ {
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+ }
+
+ static void stk5v3_board_init(void)
+ {
+ stk5_board_init();
+ }
+
+ static void stk5v5_board_init(void)
+ {
+ stk5_board_init();
+
-void ft_board_setup(void *blob, bd_t *bd)
++ gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
+ imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
+ }
+
+ static void tx53_set_cpu_clock(void)
+ {
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+ printf("%s detected; skipping cpu clock change\n",
+ (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
+ return;
+ }
+
+ if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
+ cpu_clk = mxc_get_clock(MXC_ARM_CLK);
+ printf("CPU clock set to %lu.%03lu MHz\n",
+ cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+ } else {
+ printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ }
+ }
+
+ static void tx53_init_mac(void)
+ {
+ u8 mac[ETH_ALEN];
+
+ imx_get_mac_from_fuse(0, mac);
+ if (!is_valid_ether_addr(mac)) {
+ printf("No valid MAC address programmed\n");
+ return;
+ }
+
+ printf("MAC addr from fuse: %pM\n", mac);
+ eth_setenv_enetaddr("ethaddr", mac);
+ }
+
+ int board_late_init(void)
+ {
+ int ret = 0;
+ const char *baseboard;
+
+ env_cleanup();
+
+ tx53_set_cpu_clock();
+
+ if (had_ctrlc())
+ setenv_ulong("safeboot", 1);
+ else if (wrsr & WRSR_TOUT)
+ setenv_ulong("wdreset", 1);
+ else
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ printf("Baseboard: %s\n", baseboard);
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && strcmp(otg_mode, "host") == 0) {
+ printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
+ otg_mode, baseboard);
+ setenv("otg_mode", "none");
+ }
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+ exit:
+ tx53_init_mac();
+
+ gpio_set_value(TX53_RESET_OUT_GPIO, 1);
+ clear_ctrlc();
+ return ret;
+ }
+
+ int checkboard(void)
+ {
+ tx53_print_cpuinfo();
+ #if CONFIG_SYS_SDRAM_SIZE < SZ_1G
+ printf("Board: Ka-Ro TX53-8%d3%c\n",
+ is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
+ #elif CONFIG_SYS_SDRAM_SIZE < SZ_2G
+ printf("Board: Ka-Ro TX53-1%d3%c\n",
+ is_lvds() + 2, '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
+ #else
+ printf("Board: Ka-Ro TX53-123%c\n",
+ '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
+ #endif
+ return 0;
+ }
+
+ #if defined(CONFIG_OF_BOARD_SETUP)
+ #ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ #include <jffs2/jffs2.h>
+ #include <mtd_node.h>
+ static struct node_info nodes[] = {
+ { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
+ };
+ #else
+ #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+ #endif
+
+ #ifdef CONFIG_SYS_TX53_HWREV_2
+ static void tx53_fixup_rtc(void *blob)
+ {
+ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
+ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
+ }
+ #else
+ static inline void tx53_fixup_rtc(void *blob)
+ {
+ }
+ #endif /* CONFIG_SYS_TX53_HWREV_2 */
+
+ static const char *tx53_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+ "eeti,egalax_ts",
+ };
+
- if (ret)
++int ft_board_setup(void *blob, bd_t *bd)
+ {
+ const char *baseboard = getenv("baseboard");
+ int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
-
++ if (ret) {
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
++ return ret;
++ }
+ if (stk5_v5)
+ karo_fdt_enable_node(blob, "stk5led", 0);
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
+ ARRAY_SIZE(tx53_touchpanels));
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
+ karo_fdt_fixup_flexcan(blob, stk5_v5);
+ tx53_fixup_rtc(blob);
+ karo_fdt_update_fb_mode(blob, video_mode);
++
++ return 0;
+ }
+ #endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
--- /dev/null
++if TARGET_TX6
++
++config MX6
++ bool
++ default y
++
++config MX6Q
++ bool
++
++config MX6DL
++ bool
++
++config MX6QDL
++ bool
++
++config MX6S
++ bool
++
++config MX6SL
++ bool
++
++config MX6SX
++ bool
++
++config SYS_BOARD
++ default "tx6"
++
++config SYS_VENDOR
++ default "karo"
++
++config SYS_SOC
++ default "mx6"
++
++config SYS_CONFIG_NAME
++ default "tx6"
++
++config CMD_ROMUPDATE
++ bool
++
++config TX6
++ bool
++ default y
++ select MX6
++ select CMD_BMP if LCD
++ select CMD_BOOTCE
++ select CMD_BOOTZ
++ select CMD_CACHE
++ select CMD_I2C if I2C
++ select CMD_MEMTEST
++ select CMD_TIME
++ select DM
++ select DM_GPIO
++ select SYS_I2C
++ select SYS_I2C_MXC
++ select GET_FEC_MAC_ADDR_FROM_IIM
++
++config TX6_NAND
++ bool
++ default ! TX6_EMMC
++ select CMD_NAND
++ select CMD_NAND_TRIMFFS
++ select CMD_MTDPARTS
++ select CMD_ROMUPDATE
++ select FDT_FIXUP_PARTITIONS if OF_LIBFDT
++ select MTD_PARTITIONS
++ select NAND_MXS_NO_BBM_SWAP if NAND_MXS
++ select SYS_NAND_USE_FLASH_BBT if NAND_MXS
++ select APBH_DMA
++ select APBH_DMA_BURST
++ select APBH_DMA_BURST8
++ select MTD_DEVICE
++
++config TX6_EMMC
++ bool
++ select SUPPORT_EMMC_BOOT
++
++#
++# variables selected depending on module variant
++#
++config SYS_LVDS_IF
++ bool
++
++config SYS_SDRAM_BUS_WIDTH_16
++ bool
++
++config SYS_SDRAM_BUS_WIDTH_32
++ bool
++
++
++choice
++ prompt "TX6 module variant"
++
++config TARGET_TX6Q_10X0
++ bool "TX6Q-1010 and TX6Q-1030"
++ select MX6Q
++
++config TARGET_TX6Q_1020
++ bool "TX6Q-1020"
++ select MX6Q
++ select TX6_EMMC
++ select TX6_REV_2
++
++config TARGET_TX6Q_11X0
++ bool "TX6Q-1110 and TX6Q-1130"
++ select MX6Q
++ select SYS_LVDS_IF
++
++config TARGET_TX6S_8034
++ bool "TX6S-8034"
++ select MX6S
++ select SYS_SDRAM_BUS_WIDTH_16
++
++config TARGET_TX6S_8035
++ bool "TX6S-8035"
++ select MX6S
++ select TX6_EMMC
++ select SYS_SDRAM_BUS_WIDTH_32
++
++config TARGET_TX6U_8010
++ bool "TX6U-8010 and TX6U-8030"
++ select MX6DL
++
++config TARGET_TX6U_8011
++ bool "TX6U-8011"
++ select MX6DL
++ select SYS_SDRAM_BUS_WIDTH_32
++ select TX6_REV_1
++
++config TARGET_TX6U_8012
++ bool "TX6U-8012"
++ select MX6DL
++ select TX6_REV_1
++
++config TARGET_TX6U_81X0
++ bool "TX6U-8110 and TX6U-8130"
++ select MX6DL
++ select SYS_LVDS_IF
++
++config TARGET_TX6U_8111
++ bool "TX6U-8111"
++ select MX6DL
++ select SYS_SDRAM_BUS_WIDTH_32
++ select SYS_LVDS_IF
++ select TX6_REV_1
++
++config TARGET_TX6U_8033
++ bool "TX6U-8033"
++ select MX6DL
++ select TX6_EMMC
++ select TX6_REV_3
++
++endchoice
++
++choice
++ prompt "U-Boot image variant"
++ default TX6_UBOOT
++
++config TX6_UBOOT
++ bool "Standard U-Boot image"
++
++config TX6_UBOOT_MFG
++ bool "U-Boot image for use with Freescale's MfGTool"
++
++config TX6_UBOOT_NOENV
++ bool "U-Boot using only built-in environment"
++
++endchoice
++
++endif
--- /dev/null
-# (C) Copyright 2009 DENX Software Engineering
-# Author: John Rigby <jcrigby@gmail.com>
+ #
-include $(TOPDIR)/config.mk
++# (C) Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ #
+ # SPDX-License-Identifier: GPL-2.0+
+ #
+
-LIB = $(obj)lib$(BOARD).o
++LDSCRIPT := $(BOARDDIR)/u-boot.lds
+
-COBJS-y := tx6qdl.o
-COBJS-$(CONFIG_LTC3676) += ltc3676.o
-COBJS-$(CONFIG_RN5T567) += rn5t567.o
-COBJS-$(CONFIG_RN5T618) += rn5t618.o
-
-COBJS-$(CONFIG_CMD_ROMUPDATE) += flash.o
-
-SOBJS-y := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
++obj-y += lowlevel_init.o pmic.o tx6qdl.o
++obj-$(CONFIG_LTC3676) += ltc3676.o
++obj-$(CONFIG_RN5T567) += rn5t567.o
++obj-$(CONFIG_RN5T618) += rn5t618.o
+
++obj-$(CONFIG_CMD_ROMUPDATE) += flash.o
--- /dev/null
-ifeq ($(CONFIG_NO_NAND),)
+ # stack is allocated below CONFIG_SYS_TEXT_BASE
+ CONFIG_SYS_TEXT_BASE := 0x10100000
+
++__HAVE_ARCH_GENERIC_BOARD := y
++
+ LOGO_BMP = logos/karo.bmp
+ #PLATFORM_CPPFLAGS += -DDEBUG
+ #PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable
+ PLATFORM_CPPFLAGS += -Werror
+
-endif # CONFIG_NO_NAND
++ifeq ($(CONFIG_TX6_NAND),y)
+ # calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size
+ CONFIG_SYS_NAND_BLOCK_SIZE := 131072
+ ifeq ($(CONFIG_SYS_NAND_BLOCKS),)
+ CONFIG_SYS_NAND_BLOCKS := 1024
+ endif
+ ifneq ($(CONFIG_SYS_NAND_BLOCK_SIZE),)
+ CONFIG_U_BOOT_IMG_SIZE := $(shell echo 'e=$(CONFIG_SYS_NAND_BLOCK_SIZE);s=640*1024;s + (e - s % e) % e + 3*e' | bc)
+ CONFIG_SYS_USERFS_SIZE := $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 12 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 38 \* 1048576)
+ CONFIG_SYS_USERFS_SIZE2 := $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 15 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 38 \* 1048576)
+ CONFIG_SYS_NAND_BBT_BLOCKS := 4
+ CONFIG_SYS_NAND_DTB_BLOCKS := 4
+
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BLOCKS=$(CONFIG_SYS_NAND_BLOCKS)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BLOCK_SIZE=$(CONFIG_SYS_NAND_BLOCK_SIZE)
+ PLATFORM_CPPFLAGS += -DCONFIG_U_BOOT_IMG_SIZE=$(CONFIG_U_BOOT_IMG_SIZE)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_U_BOOT_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_U_BOOT_IMG_SIZE) / 1024`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_U_BOOT_OFFS=$(shell printf "0x%x" `expr $(CONFIG_SYS_NAND_BLOCK_SIZE)`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_ENV_PART_SIZE=$(shell printf "%uk" `expr 3 \* $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE2=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_NAND_BLOCK_SIZE) \* $(CONFIG_SYS_NAND_BBT_BLOCKS) / 1024`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_DTB_OFFSET=$(shell printf "0x%x" `expr \( $(CONFIG_SYS_NAND_BLOCKS) - $(CONFIG_SYS_NAND_DTB_BLOCKS) - $(CONFIG_SYS_NAND_BBT_BLOCKS) \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE)`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_NAND_BBT_BLOCKS) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_OFFSET=$(shell printf "0x%x" `expr \( $(CONFIG_SYS_NAND_BLOCKS) - $(CONFIG_SYS_NAND_BBT_BLOCKS) \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE)`)
+ endif # CONFIG_SYS_NAND_BLOCK_SIZE
+ else
+ ifneq ($(CONFIG_MMC_BOOT_SIZE),)
+ CONFIG_SYS_MMC_BOOT_PART_SIZE := $(shell expr $(CONFIG_MMC_BOOT_SIZE) \* 1024)
+ else
+ CONFIG_SYS_MMC_BOOT_PART_SIZE := $(shell expr 4096 \* 1024)
+ endif
+ CONFIG_U_BOOT_IMG_SIZE := $(shell expr 1 \* 1048576)
+ CONFIG_MAX_DTB_SIZE := $(shell expr 64 \* 1024)
+ CONFIG_ENV_SIZE := $(shell expr 128 \* 1024)
+ CONFIG_ENV_OFFSET := $(shell expr $(CONFIG_SYS_MMC_BOOT_PART_SIZE) - $(CONFIG_ENV_SIZE))
+ CONFIG_SYS_DTB_OFFSET := $(shell expr $(CONFIG_ENV_OFFSET) - $(CONFIG_MAX_DTB_SIZE))
+
+ PLATFORM_CPPFLAGS += -DCONFIG_ENV_SIZE=$(CONFIG_ENV_SIZE)
+ PLATFORM_CPPFLAGS += -DCONFIG_U_BOOT_IMG_SIZE=$(CONFIG_U_BOOT_IMG_SIZE)
+ PLATFORM_CPPFLAGS += -DCONFIG_MAX_DTB_SIZE=$(CONFIG_MAX_DTB_SIZE)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(CONFIG_MAX_DTB_SIZE)
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_MMC_BOOT_PART_SIZE=$(CONFIG_SYS_MMC_BOOT_PART_SIZE)
+ PLATFORM_CPPFLAGS += -DCONFIG_ENV_OFFSET=$(shell printf "0x%x" $(CONFIG_ENV_OFFSET))
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_OFFSET=$(shell printf "0x%x" $(CONFIG_SYS_DTB_OFFSET))
+ PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_BLKNO=$(shell printf "0x%x" `expr $(CONFIG_SYS_DTB_OFFSET) / 512`)
++endif # CONFIG_TX6_NAND
--- /dev/null
-#include <asm/sizes.h>
+ /*
+ * Copyright (C) 2012-2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <malloc.h>
+ #include <nand.h>
+ #include <errno.h>
+
+ #include <linux/err.h>
+ #include <jffs2/load_kernel.h>
+
+ #include <asm/io.h>
- ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1);
++#include <linux/sizes.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/imx-common/regs-gpmi.h>
+ #include <asm/imx-common/regs-bch.h>
+
+ struct mx6_nand_timing {
+ u8 data_setup;
+ u8 data_hold;
+ u8 address_setup;
+ u8 dsample_time;
+ u8 nand_timing_state;
+ u8 tREA;
+ u8 tRLOH;
+ u8 tRHOH;
+ };
+
+ struct mx6_fcb {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ struct mx6_nand_timing timing;
+ u32 page_data_size;
+ u32 total_page_size;
+ u32 sectors_per_block;
+ u32 number_of_nands; /* not used by ROM code */
+ u32 total_internal_die; /* not used by ROM code */
+ u32 cell_type; /* not used by ROM code */
+ u32 ecc_blockn_type;
+ u32 ecc_block0_size;
+ u32 ecc_blockn_size;
+ u32 ecc_block0_type;
+ u32 metadata_size;
+ u32 ecc_blocks_per_page;
+ u32 rsrvd1[6]; /* not used by ROM code */
+ u32 bch_mode; /* erase_threshold */
+ u32 rsrvd2[2];
+ u32 fw1_start_page;
+ u32 fw2_start_page;
+ u32 fw1_sectors;
+ u32 fw2_sectors;
+ u32 dbbt_search_area;
+ u32 bb_mark_byte;
+ u32 bb_mark_startbit;
+ u32 bb_mark_phys_offset;
+ u32 bch_type;
+ u32 rsrvd3[8]; /* Toggle NAND timing parameters */
+ u32 disbbm;
+ u32 bb_mark_spare_offset;
+ u32 rsrvd4[9]; /* ONFI NAND parameters */
+ u32 disbb_search;
+ };
+
+ struct mx6_dbbt_header {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ u32 number_bb;
+ u32 number_pages;
+ u8 spare[492];
+ };
+
+ struct mx6_dbbt {
+ u32 nand_number;
+ u32 number_bb;
+ u32 bb_num[2040 / 4];
+ };
+
+ #define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
+
+ static nand_info_t *mtd = &nand_info[0];
+
+ extern void *_start;
+
+ #define BIT(v,n) (((v) >> (n)) & 0x1)
+
+ static u8 calculate_parity_13_8(u8 d)
+ {
+ u8 p = 0;
+
+ p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0;
+ p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1;
+ p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2;
+ p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3;
+ p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4;
+ return p;
+ }
+
+ static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+ {
+ int i;
+ u8 *src = _src;
+ u8 *ecc = _ecc;
+
+ for (i = 0; i < size; i++)
+ ecc[i] = calculate_parity_13_8(src[i]);
+ }
+
+ static u32 calc_chksum(void *buf, size_t size)
+ {
+ u32 chksum = 0;
+ u8 *bp = buf;
+ size_t i;
+
+ for (i = 0; i < size; i++) {
+ chksum += bp[i];
+ }
+ return ~chksum;
+ }
+
+ /*
+ Physical organisation of data in NAND flash:
+ metadata
+ payload chunk 0 (may be empty)
+ ecc for metadata + payload chunk 0
+ payload chunk 1
+ ecc for payload chunk 1
+ ...
+ payload chunk n
+ ecc for payload chunk n
+ */
+
+ static inline int calc_bb_offset(nand_info_t *mtd, struct mx6_fcb *fcb)
+ {
+ int bb_mark_offset;
+ int chunk_data_size = fcb->ecc_blockn_size * 8;
+ int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
+ int chunk_total_size = chunk_data_size + chunk_ecc_size;
+ int bb_mark_chunk, bb_mark_chunk_offs;
+
+ bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
+ if (fcb->ecc_block0_size == 0)
+ bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
+
+ bb_mark_chunk = bb_mark_offset / chunk_total_size;
+ bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size);
+ if (bb_mark_chunk_offs > chunk_data_size) {
+ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
+ bb_mark_chunk_offs);
+ return -EINVAL;
+ }
+ bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
+ return bb_mark_offset;
+ }
+
+ /*
+ * return number of blocks to skip for a contiguous partition
+ * of given # blocks
+ */
+ static int find_contig_space(int block, int num_blocks, int max_blocks)
+ {
+ int skip = 0;
+ int found = 0;
+ int last = block + max_blocks;
+
+ debug("Searching %u contiguous blocks from %d..%d\n",
+ num_blocks, block, block + max_blocks - 1);
+ for (; block < last; block++) {
+ if (nand_block_isbad(mtd, block * mtd->erasesize)) {
+ skip += found + 1;
+ found = 0;
+ debug("Skipping %u blocks to %u\n",
+ skip, block + 1);
+ } else {
+ found++;
+ if (found >= num_blocks) {
+ debug("Found %u good blocks from %d..%d\n",
+ found, block - found + 1, block);
+ return skip;
+ }
+ }
+ }
+ return -ENOSPC;
+ }
+
+ #define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n)
+
+ static struct mx6_fcb *create_fcb(void *buf, int fw1_start_block,
+ int fw2_start_block, int fw_num_blocks)
+ {
+ struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS;
+ struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS;
+ u32 fl0, fl1;
+ u32 t0;
+ int metadata_size;
+ int bb_mark_bit_offs;
+ struct mx6_fcb *fcb;
+ int fcb_offs;
+
+ if (gpmi_base == NULL || bch_base == NULL) {
+ return ERR_PTR(-ENOMEM);
+ }
+
+ fl0 = readl(&bch_base->hw_bch_flash0layout0);
+ fl1 = readl(&bch_base->hw_bch_flash0layout1);
+ t0 = readl(&gpmi_base->hw_gpmi_timing0);
+
+ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+
+ fcb = buf + ALIGN(metadata_size, 4);
+ fcb_offs = (void *)fcb - buf;
+
+ memset(buf, 0xff, fcb_offs);
+ memset(fcb, 0x00, sizeof(*fcb));
+ memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
+
+ strncpy((char *)&fcb->fingerprint, "FCB ", 4);
+ fcb->version = cpu_to_be32(1);
+
+ fcb->disbb_search = 0;
+ fcb->disbbm = 1;
+
+ /* ROM code assumes GPMI clock of 25 MHz */
+ fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP) * 40;
+ fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD) * 40;
+ fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP) * 40;
+
+ fcb->page_data_size = mtd->writesize;
+ fcb->total_page_size = mtd->writesize + mtd->oobsize;
+ fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
+
+ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
+ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE) * 4;
+ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
+ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE) * 4;
+
+ pr_fcb_val(fcb, ecc_block0_type);
+ pr_fcb_val(fcb, ecc_blockn_type);
+ pr_fcb_val(fcb, ecc_block0_size);
+ pr_fcb_val(fcb, ecc_blockn_size);
+
+ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
+ fcb->bch_mode = readl(&bch_base->hw_bch_mode);
+ fcb->bch_type = 0; /* BCH20 */
+
+ fcb->fw1_start_page = fw1_start_block * fcb->sectors_per_block;
+ fcb->fw1_sectors = fw_num_blocks * fcb->sectors_per_block;
+ pr_fcb_val(fcb, fw1_start_page);
+ pr_fcb_val(fcb, fw1_sectors);
+
+ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
+ fcb->fw2_start_page = fw2_start_block * fcb->sectors_per_block;
+ fcb->fw2_sectors = fcb->fw1_sectors;
+ pr_fcb_val(fcb, fw2_start_page);
+ pr_fcb_val(fcb, fw2_sectors);
+ }
+
+ fcb->dbbt_search_area = 0;
+
+ bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
+ if (bb_mark_bit_offs < 0)
+ return ERR_PTR(bb_mark_bit_offs);
+ fcb->bb_mark_byte = bb_mark_bit_offs / 8;
+ fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
+ fcb->bb_mark_phys_offset = mtd->writesize;
+
+ pr_fcb_val(fcb, bb_mark_byte);
+ pr_fcb_val(fcb, bb_mark_startbit);
+ pr_fcb_val(fcb, bb_mark_phys_offset);
+
+ fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
+ return fcb;
+ }
+
+ static int find_fcb(void *ref, int page)
+ {
+ int ret = 0;
+ struct nand_chip *chip = mtd->priv;
+ void *buf = malloc(mtd->erasesize);
+
+ if (buf == NULL) {
+ return -ENOMEM;
+ }
+ chip->select_chip(mtd, 0);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
+ if (ret) {
+ printf("Failed to read FCB from page %u: %d\n", page, ret);
+ goto out;
+ }
+ if (memcmp(buf, ref, mtd->writesize) == 0) {
+ debug("Found FCB in page %u (%08x)\n",
+ page, page * mtd->writesize);
+ ret = 1;
+ }
+ out:
+ chip->select_chip(mtd, -1);
+ free(buf);
+ return ret;
+ }
+
+ static int write_fcb(void *buf, int block)
+ {
+ int ret;
+ struct nand_chip *chip = mtd->priv;
+ int page = block * mtd->erasesize / mtd->writesize;
+
+ ret = find_fcb(buf, page);
+ if (ret > 0) {
+ printf("FCB at block %d is up to date\n", block);
+ return 0;
+ }
+
+ ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize);
+ if (ret) {
+ printf("Failed to erase FCB block %u\n", block);
+ return ret;
+ }
+
+ printf("Writing FCB to block %d @ %08llx\n", block,
+ (u64)block * mtd->erasesize);
+ chip->select_chip(mtd, 0);
++ ret = chip->write_page(mtd, chip, 0, mtd->writesize,
++ buf, 1, page, 0, 1);
+ if (ret) {
+ printf("Failed to write FCB to block %u: %d\n", block, ret);
+ }
+ chip->select_chip(mtd, -1);
+ return ret;
+ }
+
+ struct mx6_ivt {
+ u32 magic;
+ u32 entry;
+ u32 rsrvd1;
+ void *dcd;
+ void *boot_data;
+ void *self;
+ void *csf;
+ u32 rsrvd2;
+ };
+
+ struct mx6_boot_data {
+ u32 start;
+ u32 length;
+ u32 plugin;
+ };
+
+ static int find_ivt(void *buf)
+ {
+ struct mx6_ivt *ivt_hdr = buf + 0x400;
+
+ if ((ivt_hdr->magic & 0xff0000ff) != 0x400000d1)
+ return 0;
+
+ return 1;
+ }
+
+ static inline void *reloc(void *dst, void *base, void *ptr)
+ {
+ return dst + (ptr - base);
+ }
+
+ static int patch_ivt(void *buf, size_t fsize)
+ {
+ struct mx6_ivt *ivt_hdr = buf + 0x400;
+ struct mx6_boot_data *boot_data;
+
+ if (!find_ivt(buf)) {
+ printf("No IVT found in image at %p\n", buf);
+ return -EINVAL;
+ }
+ boot_data = reloc(ivt_hdr, ivt_hdr->self, ivt_hdr->boot_data);
+ boot_data->length = fsize;
+
+ return 0;
+ }
+
+ #define chk_overlap(a,b) \
+ ((a##_start_block <= b##_end_block && \
+ a##_end_block >= b##_start_block) || \
+ (b##_start_block <= a##_end_block && \
+ b##_end_block >= a##_start_block))
+
+ #define fail_if_overlap(a,b,m1,m2) do { \
+ if (chk_overlap(a, b)) { \
+ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \
+ m1, a##_start_block, a##_end_block, \
+ m2, b##_start_block, b##_end_block); \
+ return -EINVAL; \
+ } \
+ } while (0)
+
+ static int tx6_prog_uboot(void *addr, int start_block, int skip,
+ size_t size, size_t max_len)
+ {
+ int ret;
+ nand_erase_options_t erase_opts = { 0, };
+ size_t actual;
+ size_t prg_length = max_len - skip * mtd->erasesize;
+ int prg_start = (start_block + skip) * mtd->erasesize;
+
+ erase_opts.offset = start_block * mtd->erasesize;
+ erase_opts.length = max_len;
+ erase_opts.quiet = 1;
+
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+
+ printf("Programming flash @ %08llx..%08llx from %p\n",
+ (u64)start_block * mtd->erasesize,
+ (u64)start_block * mtd->erasesize + size - 1, addr);
+ actual = size;
+ ret = nand_write_skip_bad(mtd, prg_start, &actual, NULL,
+ prg_length, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ if (actual < size) {
+ printf("Could only write %u of %u bytes\n", actual, size);
+ return -EIO;
+ }
+ return 0;
+ }
+
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ #ifndef CONFIG_ENV_OFFSET_REDUND
+ #define TOTAL_ENV_SIZE CONFIG_ENV_RANGE
+ #else
+ #define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2)
+ #endif
+ #endif
+
+ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int ret;
+ const unsigned long fcb_start_block = 0, fcb_end_block = 0;
+ int erase_size = mtd->erasesize;
+ int page_size = mtd->writesize;
+ void *buf;
+ char *load_addr;
+ char *file_size;
+ size_t size = 0;
+ void *addr = NULL;
+ struct mx6_fcb *fcb;
+ unsigned long mtd_num_blocks = mtd->size / mtd->erasesize;
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize;
+ unsigned long env_end_block = env_start_block +
+ DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1;
+ #endif
+ int optind;
+ int fw2_set = 0;
+ unsigned long fw1_start_block = 0, fw1_end_block;
+ unsigned long fw2_start_block = 0, fw2_end_block;
+ unsigned long fw_num_blocks;
+ int fw1_skip, fw2_skip;
+ unsigned long extra_blocks = 0;
+ size_t max_len1, max_len2;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ struct part_info *redund_part_info;
+ const char *uboot_part = "u-boot";
+ const char *redund_part = NULL;
+ u8 part_num;
+ u8 redund_part_num;
+
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ for (optind = 1; optind < argc; optind++) {
+ char *endp;
+
+ if (strcmp(argv[optind], "-f") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fw1_start_block = simple_strtoul(argv[optind], &endp, 0);
+ if (*endp != '\0') {
+ uboot_part = argv[optind];
+ continue;
+ }
+ uboot_part = NULL;
+ if (fw1_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw1_start_block, mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-r") == 0) {
+ fw2_set = 1;
+ if (optind < argc - 1 && argv[optind + 1][0] != '-') {
+ optind++;
+ fw2_start_block = simple_strtoul(argv[optind],
+ &endp, 0);
+ if (*endp != '\0') {
+ redund_part = argv[optind];
+ continue;
+ }
+ if (fw2_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw2_start_block,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ }
+ } else if (strcmp(argv[optind], "-e") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ extra_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (extra_blocks >= mtd_num_blocks) {
+ printf("Extra block count %lu is out of range: 0..%lu\n",
+ extra_blocks,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (argv[optind][0] == '-') {
+ printf("Unrecognized option %s\n", argv[optind]);
+ return -EINVAL;
+ } else {
+ break;
+ }
+ }
+
+ load_addr = getenv("fileaddr");
+ file_size = getenv("filesize");
+
+ if (argc - optind < 1 && load_addr == NULL) {
+ printf("Load address not specified\n");
+ return -EINVAL;
+ }
+ if (argc - optind < 2 && file_size == NULL) {
+ printf("WARNING: Image size not specified; overwriting whole uboot partition\n");
+ }
+ if (argc > optind) {
+ load_addr = NULL;
+ addr = (void *)simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (argc > optind) {
+ file_size = NULL;
+ size = simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (load_addr != NULL) {
+ addr = (void *)simple_strtoul(load_addr, NULL, 16);
+ printf("Using default load address %p\n", addr);
+ }
+ if (file_size != NULL) {
+ size = simple_strtoul(file_size, NULL, 16);
+ printf("Using default file size %08x\n", size);
+ }
+ if (size > 0) {
+ fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize);
+ } else {
+ fw_num_blocks = part_info->size / mtd->erasesize -
+ extra_blocks;
+ size = fw_num_blocks * mtd->erasesize;
+ }
+
+ if (uboot_part) {
+ ret = find_dev_and_part(uboot_part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ uboot_part, ret);
+ return ret;
+ }
+ fw1_start_block = part_info->offset / mtd->erasesize;
+ max_len1 = part_info->size;
+ } else {
+ max_len1 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
+ }
+
+ if (redund_part) {
+ ret = find_dev_and_part(redund_part, &dev, &redund_part_num,
+ &redund_part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ redund_part, ret);
+ return ret;
+ }
+ fw2_start_block = redund_part_info->offset / mtd->erasesize;
+ max_len2 = redund_part_info->size;
+ } else if (fw2_set) {
+ max_len2 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
+ } else {
+ max_len2 = 0;
+ }
+
+ fw1_skip = find_contig_space(fw1_start_block, fw_num_blocks,
+ max_len1 / mtd->erasesize);
+ if (fw1_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for fw image\n",
+ fw_num_blocks);
+ if (uboot_part) {
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ if (part_info->offset <= CONFIG_ENV_OFFSET + TOTAL_ENV_SIZE) {
+ printf("Use a different partition\n");
+ } else {
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+ }
+ #else
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+ #endif
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
+ fw1_end_block = fw1_start_block + fw1_skip + fw_num_blocks - 1;
+
+ if (fw2_set && fw2_start_block == 0)
+ fw2_start_block = fw1_end_block + 1;
+ if (fw2_start_block > 0) {
+ fw2_skip = find_contig_space(fw2_start_block, fw_num_blocks,
+ max_len2 / mtd->erasesize);
+ if (fw2_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for redundant fw image\n",
+ fw_num_blocks);
+ if (redund_part) {
+ printf("Increase the size of the '%s' partition or use a different partition\n",
+ redund_part);
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
+ } else {
+ fw2_skip = 0;
+ }
+ fw2_end_block = fw2_start_block + fw2_skip + fw_num_blocks - 1;
+
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fcb, env, "FCB", "Environment");
+ fail_if_overlap(fw1, env, "FW1", "Environment");
+ #endif
+ fail_if_overlap(fcb, fw1, "FCB", "FW1");
+ if (fw2_set) {
+ fail_if_overlap(fcb, fw2, "FCB", "FW2");
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fw2, env, "FW2", "Environment");
+ #endif
+ fail_if_overlap(fw1, fw2, "FW1", "FW2");
+ }
+
+ buf = malloc(erase_size);
+ if (buf == NULL) {
+ printf("Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ fcb = create_fcb(buf, fw1_start_block + fw1_skip,
+ fw2_start_block + fw2_skip, fw_num_blocks);
+ if (IS_ERR(fcb)) {
+ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+ free(buf);
+ return PTR_ERR(fcb);
+ }
+ encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
+
+ ret = write_fcb(buf, fcb_start_block);
+ free(buf);
+ if (ret) {
+ printf("Failed to write FCB to block %lu\n", fcb_start_block);
+ return ret;
+ }
+ ret = patch_ivt(addr, size);
+ if (ret) {
+ return ret;
+ }
+
+ if (size & (page_size - 1)) {
+ memset(addr + size, 0xff, size & (page_size - 1));
+ size = ALIGN(size, page_size);
+ }
+
+ printf("Programming U-Boot image from %p to block %lu @ %08llx\n",
+ addr, fw1_start_block + fw1_skip,
+ (u64)(fw1_start_block + fw1_skip) * mtd->erasesize);
+ ret = tx6_prog_uboot(addr, fw1_start_block, fw1_skip, size,
+ max_len1);
+
+ if (fw2_start_block == 0) {
+ return ret;
+ }
+
+ printf("Programming redundant U-Boot image to block %lu @ %08llx\n",
+ fw2_start_block + fw2_skip,
+ (u64)(fw2_start_block + fw2_skip) * mtd->erasesize);
+ ret = tx6_prog_uboot(addr, fw2_start_block, fw2_skip, fw_num_blocks,
+ max_len2);
+ return ret;
+ }
+
+ U_BOOT_CMD(romupdate, 11, 0, do_update,
+ "Creates an FCB data structure and writes an U-Boot image to flash",
+ "[-f {<part>|block#}] [-r [{<part>|block#}]] [-e #] [<address>] [<length>]\n"
+ "\t-f <part>\twrite bootloader image to partition <part>\n"
+ "\t-f #\twrite bootloader image at block # (decimal)\n"
+ "\t-r\twrite redundant bootloader image at next free block after first image\n"
+ "\t-r <part>\twrite redundant bootloader image to partition <part>\n"
+ "\t-r #\twrite redundant bootloader image at block # (decimal)\n"
+ "\t-e #\tspecify number of redundant blocks per boot loader image\n"
+ "\t\tonly valid if -f or -r specify a flash address rather than a partition name\n"
+ "\t<address>\tRAM address of bootloader image (default: ${fileaddr}\n"
+ "\t<length>\tlength of bootloader image in RAM (default: ${filesize}"
+ );
--- /dev/null
-#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300 * 10, 5))
-#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100 * 10, 5))
-#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300 * 10, 5_2))
-#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100 * 10, 5_2))
-#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6))
-#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6))
-#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7))
-#define VDD_DDR_VAL_LP mV_to_regval(vout_to_vref(1500 * 10, 7))
-#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8))
-#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8))
+ /*
+ * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <i2c.h>
+ #include <asm/io.h>
++#include <asm/arch/imx-regs.h>
+
+ #include "pmic.h"
+
+ #define LTC3676_BUCK1 0x01
+ #define LTC3676_BUCK2 0x02
+ #define LTC3676_BUCK3 0x03
+ #define LTC3676_BUCK4 0x04
+ #define LTC3676_DVB1A 0x0A
+ #define LTC3676_DVB1B 0x0B
+ #define LTC3676_DVB2A 0x0C
+ #define LTC3676_DVB2B 0x0D
+ #define LTC3676_DVB3A 0x0E
+ #define LTC3676_DVB3B 0x0F
+ #define LTC3676_DVB4A 0x10
+ #define LTC3676_DVB4B 0x11
+ #define LTC3676_MSKPG 0x13
+ #define LTC3676_CLIRQ 0x1f
+
+ #define LTC3676_BUCK_DVDT_FAST (1 << 0)
+ #define LTC3676_BUCK_KEEP_ALIVE (1 << 1)
+ #define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
+ #define LTC3676_BUCK_PHASE_SEL (1 << 3)
+ #define LTC3676_BUCK_ENABLE_300 (1 << 4)
+ #define LTC3676_BUCK_PULSE_SKIP (0 << 5)
+ #define LTC3676_BUCK_BURST_MODE (1 << 5)
+ #define LTC3676_BUCK_CONTINUOUS (2 << 5)
+ #define LTC3676_BUCK_ENABLE (1 << 7)
+
+ #define LTC3676_PGOOD_MASK (1 << 5)
+
+ #define LTC3676_MSKPG_BUCK1 (1 << 0)
+ #define LTC3676_MSKPG_BUCK2 (1 << 1)
+ #define LTC3676_MSKPG_BUCK3 (1 << 2)
+ #define LTC3676_MSKPG_BUCK4 (1 << 3)
+ #define LTC3676_MSKPG_LDO2 (1 << 5)
+ #define LTC3676_MSKPG_LDO3 (1 << 6)
+ #define LTC3676_MSKPG_LDO4 (1 << 7)
+
-#define mV_to_regval(mV) DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
-#define regval_to_mV(v) (((v) * 125 + 4125))
++#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300, 5))
++#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100, 5))
++#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300, 5_2))
++#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100, 5_2))
++#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425, 6))
++#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900, 6))
++#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500, 7))
++#define VDD_DDR_VAL_LP mV_to_regval(vout_to_vref(1500, 7))
++#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425, 8))
++#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900, 8))
+
+ /* LDO1 */
+ #define R1_1 470
+ #define R2_1 150
+ /* LDO4 */
+ #define R1_4 470
+ #define R2_4 150
+ /* Buck1 */
+ #define R1_5 390
+ #define R2_5 110
+ #define R1_5_2 470
+ #define R2_5_2 150
+ /* Buck2 (SOC) */
+ #define R1_6 150
+ #define R2_6 180
+ /* Buck3 (DDR) */
+ #define R1_7 150
+ #define R2_7 140
+ /* Buck4 (CORE) */
+ #define R1_8 150
+ #define R2_8 180
+
+ /* calculate voltages in 10mV */
+ #define R1(idx) R1_##idx
+ #define R2(idx) R2_##idx
+
++#define v2r(v,n,m) DIV_ROUND_UP(((((v) < (n)) ? (n) : (v)) - (n)), (m))
++#define r2v(r,n,m) (((r) * (m) + (n)) / 10)
++
+ #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
+ #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
+
-static int ltc3676_setup_regs(struct ltc3676_regs *r, size_t count)
++#define mV_to_regval(mV) v2r((mV) * 10, 4125, 125)
++#define regval_to_mV(r) r2v(r, 4125, 125)
+
+ static struct ltc3676_regs {
+ u8 addr;
+ u8 val;
+ u8 mask;
+ } ltc3676_regs[] = {
+ { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
+ { LTC3676_DVB2B, VDD_SOC_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB3B, VDD_DDR_VAL_LP, ~0x3f, },
+ { LTC3676_DVB4B, VDD_CORE_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
+ { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
+ { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
+ { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
+ { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
+ { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
+ { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
+ { LTC3676_CLIRQ, 0, }, /* clear interrupt status */
+ };
+
+ static struct ltc3676_regs ltc3676_regs_1[] = {
+ { LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, },
+ };
+
+ static struct ltc3676_regs ltc3676_regs_2[] = {
+ { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
+ };
+
+ static int tx6_rev_2(void)
+ {
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs;
+ u32 pad_settings = readl(&fuse->pad_settings);
+
+ debug("Fuse pad_settings @ %p = %02x\n",
+ &fuse->pad_settings, pad_settings);
+ return pad_settings & 1;
+ }
+
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
++static int ltc3676_setup_regs(uchar slave_addr, struct ltc3676_regs *r,
++ size_t count)
+ {
+ int ret;
+ int i;
+
+ for (i = 0; i < count; i++, r++) {
+ #ifdef DEBUG
+ unsigned char value;
+
- ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
- r->addr, 1, &r->val, 1);
++ ret = i2c_read(slave_addr, r->addr, 1, &value, 1);
+ if ((value & ~r->mask) != r->val) {
+ printf("Changing PMIC reg %02x from %02x to %02x\n",
+ r->addr, value, r->val);
+ }
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
+ #endif
-int setup_pmic_voltages(void)
++ ret = i2c_write(slave_addr, r->addr, 1, &r->val, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
+ }
+ return 0;
+ }
+
- ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
- if (ret != 0) {
- printf("Failed to initialize I2C\n");
- return ret;
- }
-
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
++int ltc3676_pmic_setup(uchar slave_addr)
+ {
+ int ret;
+ unsigned char value;
+
- ret = ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs));
++ ret = i2c_read(slave_addr, 0x11, 1, &value, 1);
+ if (ret) {
+ printf("%s: i2c_read error: %d\n", __func__, ret);
+ return ret;
+ }
+
- printf("VDDCORE set to %umV\n",
- DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10));
- printf("VDDSOC set to %umV\n",
- DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10));
++ ret = ltc3676_setup_regs(slave_addr, ltc3676_regs,
++ ARRAY_SIZE(ltc3676_regs));
+ if (ret)
+ return ret;
+
- ret = ltc3676_setup_regs(ltc3676_regs_2,
++ ret = i2c_read(slave_addr, LTC3676_DVB4A, 1, &value, 1);
++ if (ret == 0) {
++ printf("VDDCORE set to %umV\n",
++ vref_to_vout(regval_to_mV(value), 8));
++ } else {
++ printf("Failed to read VDDCORE register setting\n");
++ }
++
++ ret = i2c_read(slave_addr, LTC3676_DVB2A, 1, &value, 1);
++ if (ret == 0) {
++ printf("VDDSOC set to %umV\n",
++ vref_to_vout(regval_to_mV(value), 6));
++ } else {
++ printf("Failed to read VDDSOC register setting\n");
++ }
+
+ if (tx6_rev_2()) {
- printf("VDDIO set to %umV\n",
- DIV_ROUND(vref_to_vout(
- regval_to_mV(VDD_IO_VAL_2), 5_2), 10));
++ ret = ltc3676_setup_regs(slave_addr, ltc3676_regs_2,
+ ARRAY_SIZE(ltc3676_regs_2));
- ret = ltc3676_setup_regs(ltc3676_regs_1,
++
++ ret = i2c_read(slave_addr, LTC3676_DVB1A, 1, &value, 1);
++ if (ret == 0) {
++ printf("VDDIO set to %umV\n",
++ vref_to_vout(regval_to_mV(value), 5_2));
++ } else {
++ printf("Failed to read VDDIO register setting\n");
++ }
+ } else {
++ ret = ltc3676_setup_regs(slave_addr, ltc3676_regs_1,
+ ARRAY_SIZE(ltc3676_regs_1));
+ }
+ return ret;
+ }
--- /dev/null
--- /dev/null
++/*
++ * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <common.h>
++#include <errno.h>
++#include <i2c.h>
++
++#include "pmic.h"
++
++static struct {
++ uchar addr;
++ int (*init)(uchar addr);
++} i2c_addrs[] = {
++#ifdef CONFIG_LTC3676
++ { 0x3c, ltc3676_pmic_setup, },
++#endif
++#ifdef CONFIG_RN5T618
++ { 0x32, rn5t618_pmic_setup, },
++#endif
++#ifdef CONFIG_RN5T567
++ { 0x33, rn5t567_pmic_setup, },
++#endif
++};
++
++int tx6_pmic_init(void)
++{
++ int ret = -ENODEV;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(i2c_addrs); i++) {
++ ret = i2c_probe(i2c_addrs[i].addr);
++ if (ret == 0) {
++ i2c_addrs[i].init(i2c_addrs[i].addr);
++ break;
++ }
++ }
++ return ret;
++}
--- /dev/null
-int setup_pmic_voltages(void);
+ /*
+ * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
++int ltc3676_pmic_setup(uchar addr);
++int rn5t618_pmic_setup(uchar addr);
++int rn5t567_pmic_setup(uchar addr);
++
++int tx6_pmic_init(void);
--- /dev/null
-#define VDD_RTC_VAL mV_to_regval_rtc(3000 * 10)
-#define VDD_HIGH_VAL mV_to_regval3(3000 * 10)
-#define VDD_HIGH_VAL_LP mV_to_regval3(3000 * 10)
-#define VDD_CORE_VAL mV_to_regval(1425 * 10)
-#define VDD_CORE_VAL_LP mV_to_regval(900 * 10)
-#define VDD_SOC_VAL mV_to_regval(1425 * 10)
-#define VDD_SOC_VAL_LP mV_to_regval(900 * 10)
-#define VDD_DDR_VAL mV_to_regval(1500 * 10)
-#define VDD_DDR_VAL_LP mV_to_regval(1500 * 10)
+ /*
+ * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <i2c.h>
+
+ #include "pmic.h"
+
+ #define RN5T567_NOETIMSET 0x11
+ #define RN5T567_LDORTC1_SLOT 0x2a
+ #define RN5T567_DC1CTL 0x2c
+ #define RN5T567_DC1CTL2 0x2d
+ #define RN5T567_DC2CTL 0x2e
+ #define RN5T567_DC2CTL2 0x2f
+ #define RN5T567_DC3CTL 0x30
+ #define RN5T567_DC3CTL2 0x31
+ #define RN5T567_DC1DAC 0x36 /* CORE */
+ #define RN5T567_DC2DAC 0x37 /* SOC */
+ #define RN5T567_DC3DAC 0x38 /* DDR */
+ #define RN5T567_DC1DAC_SLP 0x3b
+ #define RN5T567_DC2DAC_SLP 0x3c
+ #define RN5T567_DC3DAC_SLP 0x3d
+ #define RN5T567_LDOEN1 0x44
+ #define RN5T567_LDODIS 0x46
+ #define RN5T567_LDOEN2 0x48
+ #define RN5T567_LDO3DAC 0x4e /* IO */
+ #define RN5T567_LDORTC1DAC 0x56 /* VBACKUP */
+
+ #define NOETIMSET_DIS_OFF_NOE_TIM (1 << 3)
+
-#define mV_to_regval(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 125)
-#define regval_to_mV(v) (((v) * 125 + 6000))
++#define VDD_RTC_VAL mV_to_regval_rtc(3000)
++#define VDD_HIGH_VAL mV_to_regval3(3000)
++#define VDD_HIGH_VAL_LP mV_to_regval3(3000)
++#define VDD_CORE_VAL mV_to_regval(1350) /* DCDC1 */
++#define VDD_CORE_VAL_LP mV_to_regval(900)
++#define VDD_SOC_VAL mV_to_regval(1350) /* DCDC2 */
++#define VDD_SOC_VAL_LP mV_to_regval(900)
++#define VDD_DDR_VAL mV_to_regval(1350) /* DCDC3 */
++#define VDD_DDR_VAL_LP mV_to_regval(1350)
+
+ /* calculate voltages in 10mV */
++#define v2r(v,n,m) DIV_ROUND_UP(((((v) < (n)) ? (n) : (v)) - (n)), (m))
++#define r2v(r,n,m) (((r) * (m) + (n)) / 10)
++
+ /* DCDC1-3 */
-#define mV_to_regval2(mV) DIV_ROUND(((((mV) < 9000) ? 9000 : (mV)) - 9000), 250)
-#define regval2_to_mV(v) (((v) * 250 + 9000))
++#define mV_to_regval(mV) v2r((mV) * 10, 6000, 125)
++#define regval_to_mV(r) r2v(r, 6000, 125)
+
+ /* LDO1-2 */
-#define mV_to_regval3(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 250)
-#define regval3_to_mV(v) (((v) * 250 + 6000))
++#define mV_to_regval2(mV) v2r((mV) * 10, 9000, 250)
++#define regval2_to_mV(r) r2v(r, 9000, 250)
+
+ /* LDO3 */
-#define mV_to_regval_rtc(mV) DIV_ROUND(((((mV) < 17000) ? 17000 : (mV)) - 17000), 250)
-#define regval_rtc_to_mV(v) (((v) * 250 + 17000))
++#define mV_to_regval3(mV) v2r((mV) * 10, 6000, 250)
++#define regval3_to_mV(r) r2v(r, 6000, 250)
+
+ /* LDORTC */
-#if 0
++#define mV_to_regval_rtc(mV) v2r((mV) * 10, 17000, 250)
++#define regval_rtc_to_mV(r) r2v(r, 17000, 250)
+
+ static struct rn5t567_regs {
+ u8 addr;
+ u8 val;
+ u8 mask;
+ } rn5t567_regs[] = {
+ { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
- { RN5T567_LDORTCDAC, VDD_RTC_VAL, },
+ { RN5T567_DC1DAC, VDD_CORE_VAL, },
+ { RN5T567_DC2DAC, VDD_SOC_VAL, },
+ { RN5T567_DC3DAC, VDD_DDR_VAL, },
+ { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
+ { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
+ { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
+ { RN5T567_LDOEN1, 0x01f, ~0x1f, },
+ { RN5T567_LDOEN2, 0x10, ~0x30, },
+ { RN5T567_LDODIS, 0x00, },
+ { RN5T567_LDO3DAC, VDD_HIGH_VAL, },
-#endif
++ { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
+ { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
-static struct rn5t567_regs debug_regs[] __maybe_unused = {
- { 0x00, 4, },
- { 0x09, 4, },
- { 0x10, 16, },
- { 0x25, 26, },
- { 0x44, 3, },
- { 0x4c, 5, },
- { 0x56, 1, },
- { 0x58, 5, },
- { 0x97, 2, },
- { 0xb0, 1, },
- { 0xbc, 1, },
-};
-
-static int rn5t567_setup_regs(struct rn5t567_regs *r, size_t count)
+ };
+
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
++static int rn5t567_setup_regs(uchar slave_addr, struct rn5t567_regs *r,
++ size_t count)
+ {
+ int ret;
+ int i;
+
+ for (i = 0; i < count; i++, r++) {
+ #ifdef DEBUG
+ unsigned char value;
+
-// value = (value & ~r->mask) | r->val;
- ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
- r->addr, 1, &r->val, 1);
++ ret = i2c_read(slave_addr, r->addr, 1, &value, 1);
+ if ((value & ~r->mask) != r->val) {
+ printf("Changing PMIC reg %02x from %02x to %02x\n",
+ r->addr, value, r->val);
+ }
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
+ #endif
-#ifdef DEBUG
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
- printf("PMIC reg %02x is %02x\n", r->addr, value);
-#endif
++ ret = i2c_write(slave_addr, r->addr, 1, &r->val, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
-#if 0
- for (i = 0; i < ARRAY_SIZE(debug_regs); i++) {
- int j;
-
- r = &debug_regs[i];
- for (j = r->addr; j < r->addr + r->val; j++) {
- unsigned char value;
-
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, j, 1, &value, 1);
- printf("PMIC reg %02x = %02x\n",
- j, value);
- }
- }
-#endif
- debug("%s() complete\n", __func__);
+ }
-int setup_pmic_voltages(void)
+ return 0;
+ }
+
- ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
- if (ret != 0) {
- printf("Failed to initialize I2C\n");
- return ret;
- }
-
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
++int rn5t567_pmic_setup(uchar slave_addr)
+ {
+ int ret;
+ unsigned char value;
+
- ret = rn5t567_setup_regs(rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
++ ret = i2c_read(slave_addr, 0x11, 1, &value, 1);
+ if (ret) {
+ printf("%s: i2c_read error: %d\n", __func__, ret);
+ return ret;
+ }
+
- printf("VDDCORE set to %umV\n",
- DIV_ROUND(regval_to_mV(VDD_CORE_VAL), 10));
- printf("VDDSOC set to %umV\n",
- DIV_ROUND(regval_to_mV(VDD_SOC_VAL), 10));
++ ret = rn5t567_setup_regs(slave_addr, rn5t567_regs,
++ ARRAY_SIZE(rn5t567_regs));
+ if (ret)
+ return ret;
+
++ ret = i2c_read(slave_addr, RN5T567_DC1DAC, 1, &value, 1);
++ if (ret == 0) {
++ printf("VDDCORE set to %umV\n", regval_to_mV(value));
++ } else {
++ printf("Failed to read VDDCORE register setting\n");
++ }
++
++ ret = i2c_read(slave_addr, RN5T567_DC2DAC, 1, &value, 1);
++ if (ret == 0) {
++ printf("VDDSOC set to %umV\n", regval_to_mV(value));
++ } else {
++ printf("Failed to read VDDSOC register setting\n");
++ }
+
+ return ret;
+ }
--- /dev/null
-#define VDD_RTC_VAL mV_to_regval_rtc(3000 * 10)
-#define VDD_HIGH_VAL mV_to_regval3(3000 * 10)
-#define VDD_HIGH_VAL_LP mV_to_regval3(3000 * 10)
-#define VDD_CORE_VAL mV_to_regval(1425 * 10)
-#define VDD_CORE_VAL_LP mV_to_regval(900 * 10)
-#define VDD_SOC_VAL mV_to_regval(1425 * 10)
-#define VDD_SOC_VAL_LP mV_to_regval(900 * 10)
-#define VDD_DDR_VAL mV_to_regval(1500 * 10)
-#define VDD_DDR_VAL_LP mV_to_regval(1500 * 10)
+ /*
+ * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <i2c.h>
+
+ #include "pmic.h"
+
+ #define RN5T618_NOETIMSET 0x11
+ #define RN5T618_LDORTC1_SLOT 0x2a
+ #define RN5T618_DC1CTL 0x2c
+ #define RN5T618_DC1CTL2 0x2d
+ #define RN5T618_DC2CTL 0x2e
+ #define RN5T618_DC2CTL2 0x2f
+ #define RN5T618_DC3CTL 0x30
+ #define RN5T618_DC3CTL2 0x31
+ #define RN5T618_DC1DAC 0x36 /* CORE */
+ #define RN5T618_DC2DAC 0x37 /* SOC */
+ #define RN5T618_DC3DAC 0x38 /* DDR */
+ #define RN5T618_DC1DAC_SLP 0x3b
+ #define RN5T618_DC2DAC_SLP 0x3c
+ #define RN5T618_DC3DAC_SLP 0x3d
+ #define RN5T618_LDOEN1 0x44
+ #define RN5T618_LDODIS 0x46
+ #define RN5T618_LDOEN2 0x48
+ #define RN5T618_LDO3DAC 0x4e /* IO */
+ #define RN5T618_LDORTCDAC 0x56 /* VBACKUP */
+
-#define mV_to_regval(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 125)
-#define regval_to_mV(v) (((v) * 125 + 6000))
++#define VDD_RTC_VAL mV_to_regval_rtc(3000)
++#define VDD_HIGH_VAL mV_to_regval3(3000)
++#define VDD_HIGH_VAL_LP mV_to_regval3(3000)
++#define VDD_CORE_VAL mV_to_regval(1425) /* DCDC1 */
++#define VDD_CORE_VAL_LP mV_to_regval(900)
++#define VDD_SOC_VAL mV_to_regval(1425) /* DCDC2 */
++#define VDD_SOC_VAL_LP mV_to_regval(900)
++#define VDD_DDR_VAL mV_to_regval(1500) /* DCDC3 */
++#define VDD_DDR_VAL_LP mV_to_regval(1500)
+
+ /* calculate voltages in 10mV */
++#define v2r(v,n,m) DIV_ROUND_UP(((((v) < (n)) ? (n) : (v)) - (n)), (m))
++#define r2v(r,n,m) (((r) * (m) + (n)) / 10)
++
+ /* DCDC1-3 */
-#define mV_to_regval2(mV) DIV_ROUND(((((mV) < 9000) ? 9000 : (mV)) - 9000), 250)
-#define regval2_to_mV(v) (((v) * 250 + 9000))
++#define mV_to_regval(mV) v2r((mV) * 10, 6000, 125)
++#define regval_to_mV(r) r2v(r, 6000, 125)
+
+ /* LDO1-2 */
-#define mV_to_regval3(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 250)
-#define regval3_to_mV(v) (((v) * 250 + 6000))
++#define mV_to_regval2(mV) v2r((mV) * 10, 9000, 250)
++#define regval2_to_mV(r) r2v(r, 9000, 250)
+
+ /* LDO3 */
-#define mV_to_regval_rtc(mV) DIV_ROUND(((((mV) < 17000) ? 17000 : (mV)) - 17000), 250)
-#define regval_rtc_to_mV(v) (((v) * 250 + 17000))
++#define mV_to_regval3(mV) v2r((mV) * 10, 6000, 250)
++#define regval3_to_mV(r) r2v(r, 6000, 250)
+
+ /* LDORTC */
-#if CONFIG_TX6_REV == 2
- { RN5T618_NOETIMSET, 0, },
- { RN5T618_DC1DAC, VDD_CORE_VAL, },
- { RN5T618_DC2DAC, VDD_SOC_VAL, },
- { RN5T618_DC3DAC, VDD_DDR_VAL, },
- { RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, },
- { RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, },
- { RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, },
- { RN5T618_LDOEN1, 0x01f, ~0x1f, },
- { RN5T618_LDOEN2, 0x10, ~0x30, },
- { RN5T618_LDODIS, 0x00, },
- { RN5T618_LDO3DAC, VDD_HIGH_VAL, },
- { RN5T618_LDORTCDAC, VDD_RTC_VAL, },
- { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, },
-#elif CONFIG_TX6_REV == 3
++#define mV_to_regval_rtc(mV) v2r((mV) * 10, 17000, 250)
++#define regval_rtc_to_mV(r) r2v(r, 17000, 250)
+
+ static struct rn5t618_regs {
+ u8 addr;
+ u8 val;
+ u8 mask;
+ } rn5t618_regs[] = {
-#else
-#error Unsupported TX6 module revision
-#endif
+ { RN5T618_NOETIMSET, 0, },
+ { RN5T618_DC1DAC, VDD_CORE_VAL, },
+ { RN5T618_DC2DAC, VDD_SOC_VAL, },
+ { RN5T618_DC3DAC, VDD_DDR_VAL, },
+ { RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, },
+ { RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, },
+ { RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, },
+ { RN5T618_LDOEN1, 0x01f, ~0x1f, },
+ { RN5T618_LDOEN2, 0x10, ~0x30, },
+ { RN5T618_LDODIS, 0x00, },
+ { RN5T618_LDO3DAC, VDD_HIGH_VAL, },
+ { RN5T618_LDORTCDAC, VDD_RTC_VAL, },
+ { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, },
-static int rn5t618_setup_regs(struct rn5t618_regs *r, size_t count)
+ };
+
- for (i = 0; i < count; i++, r++) {
- unsigned char value;
-
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
- printf("PMIC reg %02x = %02x\n",
- r->addr, value);
- }
++static int rn5t618_setup_regs(uchar slave_addr, struct rn5t618_regs *r,
++ size_t count)
+ {
+ int ret;
+ int i;
+
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
+ for (i = 0; i < count; i++, r++) {
+ #ifdef DEBUG
+ unsigned char value;
+
- ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
- r->addr, 1, &r->val, 1);
++ ret = i2c_read(slave_addr, r->addr, 1, &value, 1);
+ if ((value & ~r->mask) != r->val) {
+ printf("Changing PMIC reg %02x from %02x to %02x\n",
+ r->addr, value, r->val);
+ }
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
+ #endif
-#ifdef DEBUG
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
- printf("PMIC reg %02x is %02x\n", r->addr, value);
-#endif
++ ret = i2c_write(slave_addr, r->addr, 1, &r->val, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
-int setup_pmic_voltages(void)
+ }
+ return 0;
+ }
+
- ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
- if (ret != 0) {
- printf("Failed to initialize I2C\n");
- return ret;
- }
-
- ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
++int rn5t618_pmic_setup(uchar slave_addr)
+ {
+ int ret;
+ unsigned char value;
+
- ret = rn5t618_setup_regs(rn5t618_regs, ARRAY_SIZE(rn5t618_regs));
++ ret = i2c_read(slave_addr, 0x11, 1, &value, 1);
+ if (ret) {
+ printf("%s: i2c_read error: %d\n", __func__, ret);
+ return ret;
+ }
+
- printf("VDDCORE set to %umV\n",
- DIV_ROUND(regval_to_mV(VDD_CORE_VAL), 10));
- printf("VDDSOC set to %umV\n",
- DIV_ROUND(regval_to_mV(VDD_SOC_VAL), 10));
++ ret = rn5t618_setup_regs(slave_addr, rn5t618_regs,
++ ARRAY_SIZE(rn5t618_regs));
+ if (ret)
+ return ret;
+
++ ret = i2c_read(slave_addr, RN5T618_DC1DAC, 1, &value, 1);
++ if (ret == 0) {
++ printf("VDDCORE set to %umV\n", regval_to_mV(value));
++ } else {
++ printf("Failed to read VDDCORE register setting\n");
++ }
++
++ ret = i2c_read(slave_addr, RN5T618_DC2DAC, 1, &value, 1);
++ if (ret == 0) {
++ printf("VDDSOC set to %umV\n", regval_to_mV(value));
++ } else {
++ printf("Failed to read VDDSOC register setting\n");
++ }
+
+ return ret;
+ }
--- /dev/null
- * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
+ /*
-
++ * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
-static const iomux_v3_cfg_t tx6qdl_pads[] = {
-#ifndef CONFIG_NO_NAND
+ #include <common.h>
+ #include <errno.h>
+ #include <libfdt.h>
+ #include <fdt_support.h>
+ #include <lcd.h>
+ #include <netdev.h>
+ #include <mmc.h>
+ #include <fsl_esdhc.h>
+ #include <video_fb.h>
+ #include <ipu.h>
+ #include <mxcfb.h>
+ #include <i2c.h>
+ #include <linux/fb.h>
+ #include <asm/io.h>
+ #include <asm/gpio.h>
+ #include <asm/arch/mx6-pins.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/crm_regs.h>
+ #include <asm/arch/sys_proto.h>
+
+ #include "../common/karo.h"
+ #include "pmic.h"
+
++#define __data __attribute__((section(".data")))
++
+ #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
+ #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
+ #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
+ #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
+
+ #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
+ #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
+ #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
+
+ #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
+
+ #ifdef CONFIG_MX6_TEMPERATURE_MIN
+ #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
+ #else
+ #define TEMPERATURE_MIN (-40)
+ #endif
+ #ifdef CONFIG_MX6_TEMPERATURE_HOT
+ #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
+ #else
+ #define TEMPERATURE_HOT 80
+ #endif
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
+
- MX6_PAD_NANDF_CLE__RAWNAND_CLE,
- MX6_PAD_NANDF_ALE__RAWNAND_ALE,
- MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
- MX6_PAD_NANDF_RB0__RAWNAND_READY0,
- MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
- MX6_PAD_SD4_CMD__RAWNAND_RDN,
- MX6_PAD_SD4_CLK__RAWNAND_WRN,
- MX6_PAD_NANDF_D0__RAWNAND_D0,
- MX6_PAD_NANDF_D1__RAWNAND_D1,
- MX6_PAD_NANDF_D2__RAWNAND_D2,
- MX6_PAD_NANDF_D3__RAWNAND_D3,
- MX6_PAD_NANDF_D4__RAWNAND_D4,
- MX6_PAD_NANDF_D5__RAWNAND_D5,
- MX6_PAD_NANDF_D6__RAWNAND_D6,
- MX6_PAD_NANDF_D7__RAWNAND_D7,
++enum {
++ MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
++};
++
++static const iomux_v3_cfg_t const tx6qdl_pads[] = {
++ MX6_PAD_GARBAGE,
++#ifdef CONFIG_TX6_NAND_
+ /* NAND flash pads */
- MX6_PAD_GPIO_17__GPIO_7_12,
++ MX6_PAD_NANDF_CLE__NAND_CLE,
++ MX6_PAD_NANDF_ALE__NAND_ALE,
++ MX6_PAD_NANDF_WP_B__NAND_RESETN,
++ MX6_PAD_NANDF_RB0__NAND_READY0,
++ MX6_PAD_NANDF_CS0__NAND_CE0N,
++ MX6_PAD_SD4_CMD__NAND_RDN,
++ MX6_PAD_SD4_CLK__NAND_WRN,
++ MX6_PAD_NANDF_D0__NAND_D0,
++ MX6_PAD_NANDF_D1__NAND_D1,
++ MX6_PAD_NANDF_D2__NAND_D2,
++ MX6_PAD_NANDF_D3__NAND_D3,
++ MX6_PAD_NANDF_D4__NAND_D4,
++ MX6_PAD_NANDF_D5__NAND_D5,
++ MX6_PAD_NANDF_D6__NAND_D6,
++ MX6_PAD_NANDF_D7__NAND_D7,
+ #endif
+ /* RESET_OUT */
- MX6_PAD_SD3_DAT7__UART1_TXD,
- MX6_PAD_SD3_DAT6__UART1_RXD,
- MX6_PAD_SD3_DAT1__UART1_RTS,
- MX6_PAD_SD3_DAT0__UART1_CTS,
++ MX6_PAD_GPIO_17__GPIO7_IO12,
+
+ /* UART pads */
+ #if CONFIG_MXC_UART_BASE == UART1_BASE
- MX6_PAD_SD4_DAT4__UART2_RXD,
- MX6_PAD_SD4_DAT7__UART2_TXD,
- MX6_PAD_SD4_DAT5__UART2_RTS,
- MX6_PAD_SD4_DAT6__UART2_CTS,
++ MX6_PAD_SD3_DAT7__UART1_TX_DATA,
++ MX6_PAD_SD3_DAT6__UART1_RX_DATA,
++ MX6_PAD_SD3_DAT1__UART1_RTS_B,
++ MX6_PAD_SD3_DAT0__UART1_CTS_B,
+ #endif
+ #if CONFIG_MXC_UART_BASE == UART2_BASE
- MX6_PAD_EIM_D24__UART3_TXD,
- MX6_PAD_EIM_D25__UART3_RXD,
- MX6_PAD_SD3_RST__UART3_RTS,
- MX6_PAD_SD3_DAT3__UART3_CTS,
++ MX6_PAD_SD4_DAT4__UART2_RX_DATA,
++ MX6_PAD_SD4_DAT7__UART2_TX_DATA,
++ MX6_PAD_SD4_DAT5__UART2_RTS_B,
++ MX6_PAD_SD4_DAT6__UART2_CTS_B,
+ #endif
+ #if CONFIG_MXC_UART_BASE == UART3_BASE
- MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
- MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
- MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
++ MX6_PAD_EIM_D24__UART3_TX_DATA,
++ MX6_PAD_EIM_D25__UART3_RX_DATA,
++ MX6_PAD_SD3_RST__UART3_RTS_B,
++ MX6_PAD_SD3_DAT3__UART3_CTS_B,
+ #endif
+ /* internal I2C */
+ MX6_PAD_EIM_D28__I2C1_SDA,
+ MX6_PAD_EIM_D21__I2C1_SCL,
+
+ /* FEC PHY GPIO functions */
-static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
++ MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
++ MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
++ MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
+ };
+
- MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
++static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
+ /* FEC functions */
+ MX6_PAD_ENET_MDC__ENET_MDC,
+ MX6_PAD_ENET_MDIO__ENET_MDIO,
- MX6_PAD_ENET_RXD1__ENET_RDATA_1,
- MX6_PAD_ENET_RXD0__ENET_RDATA_0,
++ MX6_PAD_GPIO_16__ENET_REF_CLK,
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER,
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
- MX6_PAD_ENET_TXD1__ENET_TDATA_1,
- MX6_PAD_ENET_TXD0__ENET_TDATA_0,
++ MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
++ MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN,
-static const struct gpio tx6qdl_gpios[] = {
- { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
- { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
- { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
- { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
++ MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
++ MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
+ };
+
-static const char *tx6_mod_suffix;
++static const struct gpio const tx6qdl_gpios[] = {
++ { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
++ { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
++ { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
++ { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
+ };
+
+ /*
+ * Functions
+ */
+ /* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+ static u32 wrsr __attribute__((section(".data")));
+
+ #define WRSR_POR (1 << 4)
+ #define WRSR_TOUT (1 << 1)
+ #define WRSR_SFTW (1 << 0)
+
+ static void print_reset_cause(void)
+ {
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+ }
+
- ret = setup_pmic_voltages();
++static const char __data *tx6_mod_suffix;
+
+ static void tx6qdl_print_cpuinfo(void)
+ {
+ u32 cpurev = get_cpu_rev();
+ char *cpu_str = "?";
+
+ switch ((cpurev >> 12) & 0xff) {
+ case MXC_CPU_MX6SL:
+ cpu_str = "SL";
+ tx6_mod_suffix = "?";
+ break;
+ case MXC_CPU_MX6DL:
+ cpu_str = "DL";
+ tx6_mod_suffix = "U";
+ break;
+ case MXC_CPU_MX6SOLO:
+ cpu_str = "SOLO";
+ tx6_mod_suffix = "S";
+ break;
+ case MXC_CPU_MX6Q:
+ cpu_str = "Q";
+ tx6_mod_suffix = "Q";
+ break;
+ }
+
+ printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
+ cpu_str,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_reset_cause();
+ #ifdef CONFIG_MX6_TEMPERATURE_HOT
+ check_cpu_temperature(1);
+ #endif
+ }
+
+ int board_early_init_f(void)
+ {
+ gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
+
+ return 0;
+ }
+
+ #ifndef CONFIG_MX6_TEMPERATURE_HOT
+ static bool tx6_temp_check_enabled = true;
+ #else
+ #define tx6_temp_check_enabled 0
+ #endif
+
+ int board_init(void)
+ {
+ int ret;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+ gd->bd->bi_arch_number = -1;
+
+ if (ctrlc() || (wrsr & WRSR_TOUT)) {
+ if (wrsr & WRSR_TOUT)
+ printf("WDOG RESET detected; Skipping PMIC setup\n");
+ else
+ printf("<CTRL-C> detected; safeboot enabled\n");
+ #ifndef CONFIG_MX6_TEMPERATURE_HOT
+ tx6_temp_check_enabled = false;
+ #endif
+ return 1;
+ }
+
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
++ ret = tx6_pmic_init();
+ if (ret) {
+ printf("Failed to setup PMIC voltages\n");
+ hang();
+ }
+ return 0;
+ }
+
+ int dram_init(void)
+ {
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+ }
+
+ void dram_init_banksize(void)
+ {
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ #if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+ #endif
+ }
+
+ #ifdef CONFIG_CMD_MMC
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+ static const iomux_v3_cfg_t mmc0_pads[] = {
- MX6_PAD_SD3_CMD__GPIO_7_2,
++ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+ /* SD1 CD */
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6_PAD_SD3_CMD__GPIO7_IO02,
+ };
+
+ static const iomux_v3_cfg_t mmc1_pads[] = {
- MX6_PAD_SD3_CLK__GPIO_7_3,
++ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+ /* SD2 CD */
-#ifdef CONFIG_MMC_BOOT_SIZE
++ MX6_PAD_SD3_CLK__GPIO7_IO03,
+ };
+
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++#ifdef CONFIG_TX6_EMMC
+ static const iomux_v3_cfg_t mmc3_pads[] = {
- MX6_PAD_NANDF_ALE__USDHC4_RST,
++ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
++ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+ /* eMMC RESET */
-#ifdef CONFIG_MMC_BOOT_SIZE
++ MX6_PAD_NANDF_ALE__SD4_RESET,
+ };
+ #endif
+
+ static struct tx6_esdhc_cfg {
+ const iomux_v3_cfg_t *pads;
+ int num_pads;
+ enum mxc_clock clkid;
+ struct fsl_esdhc_cfg cfg;
+ int cd_gpio;
+ } tx6qdl_esdhc_cfg[] = {
- debug("SD card %d is %spresent\n",
++#ifdef CONFIG_TX6_EMMC
+ {
+ .pads = mmc3_pads,
+ .num_pads = ARRAY_SIZE(mmc3_pads),
+ .clkid = MXC_ESDHC4_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = -EINVAL,
+ },
+ #endif
+ {
+ .pads = mmc0_pads,
+ .num_pads = ARRAY_SIZE(mmc0_pads),
+ .clkid = MXC_ESDHC_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = IMX_GPIO_NR(7, 2),
+ },
+ {
+ .pads = mmc1_pads,
+ .num_pads = ARRAY_SIZE(mmc1_pads),
+ .clkid = MXC_ESDHC2_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = IMX_GPIO_NR(7, 3),
+ },
+ };
+
+ static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+ {
+ return container_of(cfg, struct tx6_esdhc_cfg, cfg);
+ }
+
+ int board_mmc_getcd(struct mmc *mmc)
+ {
+ struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
+
+ if (cfg->cd_gpio < 0)
+ return 1;
+
- gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
++ debug("SD card %d is %spresent (GPIO %d)\n",
+ cfg - tx6qdl_esdhc_cfg,
- GPIOF_INPUT, "MMC CD");
++ gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
++ cfg->cd_gpio);
+ return !gpio_get_value(cfg->cd_gpio);
+ }
+
+ int board_mmc_init(bd_t *bis)
+ {
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
+ struct mmc *mmc;
+ struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
+ int ret;
+
+ cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
+ imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
+
+ if (cfg->cd_gpio >= 0) {
+ ret = gpio_request_one(cfg->cd_gpio,
- imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
++ GPIOFLAG_INPUT, "MMC CD");
+ if (ret) {
+ printf("Error %d requesting GPIO%d_%d\n",
+ ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+ continue;
+ }
+ }
+
+ debug("%s: Initializing MMC slot %d\n", __func__, i);
+ fsl_esdhc_initialize(bis, &cfg->cfg);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc))
+ mmc_init(mmc);
+ }
+ return 0;
+ }
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_FEC_MXC
+
+ #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+ #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+ #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+ #ifndef ETH_ALEN
+ #define ETH_ALEN 6
+ #endif
+
+ int board_eth_init(bd_t *bis)
+ {
+ int ret;
+
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
- MX6_PAD_EIM_A18__GPIO_2_20,
++ imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
++ ARRAY_SIZE(tx6qdl_fec_pads));
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX6_FEC_RST_GPIO, 1);
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("cpu_eth_init() failed: %d\n", ret);
+
+ return ret;
+ }
++
++static void tx6_init_mac(void)
++{
++ u8 mac[ETH_ALEN];
++
++ imx_get_mac_from_fuse(-1, mac);
++ if (!is_valid_ether_addr(mac)) {
++ printf("No valid MAC address programmed\n");
++ return;
++ }
++
++ printf("MAC addr from fuse: %pM\n", mac);
++ eth_setenv_enetaddr("ethaddr", mac);
++}
++#else
++static inline void tx6_init_mac(void)
++{
++}
+ #endif /* CONFIG_FEC_MXC */
+
+ enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+ };
+
+ static inline int calc_blink_rate(void)
+ {
+ if (!tx6_temp_check_enabled)
+ return CONFIG_SYS_HZ;
+
+ return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
+ (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
+ (TEMPERATURE_HOT - TEMPERATURE_MIN);
+ }
+
+ void show_activity(int arg)
+ {
+ static int led_state = LED_STATE_INIT;
+ static int blink_rate;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX6_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ blink_rate = calc_blink_rate();
+ } else {
+ if (get_timer(last) > blink_rate) {
+ blink_rate = calc_blink_rate();
+ last = get_timer_masked();
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX6_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX6_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+ }
+
+ static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
- MX6_PAD_EIM_D26__GPIO_3_26,
++ MX6_PAD_EIM_A18__GPIO2_IO20,
+
+ /* I2C bus on DIMM pins 40/41 */
+ MX6_PAD_GPIO_6__I2C3_SDA,
+ MX6_PAD_GPIO_3__I2C3_SCL,
+
+ /* TSC200x PEN IRQ */
- MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
- MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
- MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
++ MX6_PAD_EIM_D26__GPIO3_IO26,
+
+ /* EDT-FT5x06 Polytouch panel */
- MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
- MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
++ MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
++ MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
++ MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
+
+ /* USBH1 */
- MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
- MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
- MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
++ MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
++ MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
+ /* USBOTG */
- { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
++ MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
++ MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
++ MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
+ };
+
+ static const struct gpio stk5_gpios[] = {
- { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
- { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
- { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
- { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
- { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
++ { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
- .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
++ { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
++ { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
++ { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
++ { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
++ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+ };
+
+ #ifdef CONFIG_LCD
+ static u16 tx6_cmap[256];
+ vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1920,
+ .vl_row = 1080,
+
- MX6_PAD_EIM_D29__GPIO_3_29,
++ .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx6_cmap,
+ };
+
+ static struct fb_videomode tx6_fb_modes[] = {
+ #ifndef CONFIG_SYS_LVDS_IF
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET070001DM6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET070001DM6",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = 0,
+ },
+ #else
+ {
+ /* HannStar HSD100PXN1
+ * 202.7m mm x 152.06 mm display area.
+ */
+ .name = "HSD100PXN1",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = KHZ2PICOS(65000),
+ .left_margin = 0,
+ .hsync_len = 0,
+ .right_margin = 320,
+ .upper_margin = 0,
+ .vsync_len = 0,
+ .lower_margin = 38,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ #endif
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .refresh = 60,
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ };
+
+ static int lcd_enabled = 1;
+ static int lcd_bl_polarity;
+
+ static int lcd_backlight_polarity(void)
+ {
+ return lcd_bl_polarity;
+ }
+
+ void lcd_enable(void)
+ {
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ karo_load_splashimage(1);
+
+ if (lcd_enabled) {
+ debug("Switching LCD on\n");
+ gpio_set_value(TX6_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX6_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
+ }
+ }
+
+ void lcd_disable(void)
+ {
+ if (lcd_enabled) {
+ printf("Disabling LCD\n");
+ ipuv3_fb_shutdown();
+ }
+ }
+
+ void lcd_panel_disable(void)
+ {
+ if (lcd_enabled) {
+ debug("Switching LCD off\n");
+ gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
+ gpio_set_value(TX6_LCD_RST_GPIO, 0);
+ gpio_set_value(TX6_LCD_PWR_GPIO, 0);
+ }
+ }
+
+ static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
- MX6_PAD_EIM_EB3__GPIO_2_31,
++ MX6_PAD_EIM_D29__GPIO3_IO29,
+ /* LCD POWER_ENABLE */
- MX6_PAD_GPIO_1__GPIO_1_1,
++ MX6_PAD_EIM_EB3__GPIO2_IO31,
+ /* LCD Backlight (PWM) */
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
- MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
- MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
- MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
- MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
- MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
- MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
++ MX6_PAD_GPIO_1__GPIO1_IO01,
+
+ #ifndef CONFIG_SYS_LVDS_IF
+ /* Display */
- { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
- { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
- { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
++ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
++ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
++ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
++ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
++ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
++ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
++ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
++ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
++ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
++ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
++ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
++ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
++ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
++ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
++ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
++ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
++ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
++ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
++ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
++ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
++ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
++ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
++ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
++ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
++ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
++ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+ #endif
+ };
+
+ static const struct gpio stk5_lcd_gpios[] = {
- panel_info.vl_bpix = LCD_COLOR24;
++ { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
++ { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
++ { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ };
+
+ void lcd_ctrl_init(void *lcdbase)
+ {
+ int color_depth = 24;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx6_fb_modes[0];
+ struct fb_videomode fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt;
+ int lcd_bus_width;
+ unsigned long di_clk_rate = 65000000;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ setenv("splashimage", NULL);
+ return;
+ }
+
+ karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
+
+ if (video_mode == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres > panel_info.vl_col ||
+ fb_mode.yres > panel_info.vl_row) {
+ printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
+ fb_mode.xres, fb_mode.yres,
+ panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 32:
+ case 24:
+ if (is_lvds())
+ pix_fmt = IPU_PIX_FMT_LVDS888;
+ /* fallthru */
+ case 16:
+ case 8:
+ color_depth = val;
+ break;
+
+ case 18:
+ if (is_lvds()) {
+ color_depth = val;
+ break;
+ }
+ /* fallthru */
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
+ }
+ if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
+ printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
+ p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ panel_info.vl_col = p->xres;
+ panel_info.vl_row = p->yres;
+
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = LCD_COLOR8;
+ break;
+ case 16:
+ panel_info.vl_bpix = LCD_COLOR16;
+ break;
+ default:
- gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
++ panel_info.vl_bpix = LCD_COLOR32;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
+
+ if (p != &fb_mode) {
+ int ret;
+
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
+ if (ret)
+ printf("Failed to create new display-timing node from '%s': %d\n",
+ video_mode, ret);
+ }
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+ switch (lcd_bus_width) {
+ case 24:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
+ break;
+
+ case 18:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
+ break;
+
+ case 16:
+ if (!is_lvds()) {
+ pix_fmt = IPU_PIX_FMT_RGB565;
+ break;
+ }
+ /* fallthru */
+ default:
+ lcd_enabled = 0;
+ printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
+ lcd_bus_width);
+ return;
+ }
+ if (is_lvds()) {
+ int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
+ int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
+ uint32_t gpr2;
++ uint32_t gpr3;
+
+ if (lvds_chan_mask == 0) {
+ printf("No LVDS channel active\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
+ if (lcd_bus_width == 24)
+ gpr2 |= (1 << 5) | (1 << 7);
+ gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
+ gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
+ debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+ writel(gpr2, IOMUXC_BASE_ADDR + 8);
++
++ gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
++ gpr3 &= ~((3 << 8) | (3 << 6));
++ writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
+ }
+ if (karo_load_splashimage(0) == 0) {
+ int ret;
+
+ debug("Initializing LCD controller\n");
+ ret = ipuv3_fb_init(p, 0, pix_fmt,
+ is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
+ di_clk_rate, -1);
+ if (ret) {
+ printf("Failed to initialize FB driver: %d\n", ret);
+ lcd_enabled = 0;
+ }
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+ }
+ #else
+ #define lcd_enabled 0
+ #endif /* CONFIG_LCD */
+
+ static void stk5_board_init(void)
+ {
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+ }
+
+ static void stk5v3_board_init(void)
+ {
+ stk5_board_init();
+ }
+
+ static void stk5v5_board_init(void)
+ {
+ stk5_board_init();
+
- imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
++ gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
-static void tx6_init_mac(void)
-{
- u8 mac[ETH_ALEN];
-
- imx_get_mac_from_fuse(-1, mac);
- if (!is_valid_ether_addr(mac)) {
- printf("No valid MAC address programmed\n");
- return;
- }
-
- printf("MAC addr from fuse: %pM\n", mac);
- eth_setenv_enetaddr("ethaddr", mac);
-}
-
++ imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
+ }
+
+ static void tx6qdl_set_cpu_clock(void)
+ {
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+ printf("%s detected; skipping cpu clock change\n",
+ (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
+ return;
+ }
+ if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
+ cpu_clk = mxc_get_clock(MXC_ARM_CLK);
+ printf("CPU clock set to %lu.%03lu MHz\n",
+ cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+ } else {
+ printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ }
+ }
+
-#ifdef CONFIG_NO_NAND
+ int board_late_init(void)
+ {
+ int ret = 0;
+ const char *baseboard;
+
+ env_cleanup();
+
+ if (tx6_temp_check_enabled)
+ check_cpu_temperature(1);
+
+ tx6qdl_set_cpu_clock();
+
+ if (had_ctrlc())
+ setenv_ulong("safeboot", 1);
+ else if (wrsr & WRSR_TOUT)
+ setenv_ulong("wdreset", 1);
+ else
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ printf("Baseboard: %s\n", baseboard);
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && strcmp(otg_mode, "host") == 0) {
+ printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
+ otg_mode, baseboard);
+ setenv("otg_mode", "none");
+ }
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+ exit:
+ tx6_init_mac();
+
+ gpio_set_value(TX6_RESET_OUT_GPIO, 1);
+ clear_ctrlc();
+ return ret;
+ }
+
-#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 1024 - 1 + 2)
++#ifdef CONFIG_TX6_NAND
++#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
++#else
+ #ifdef CONFIG_MMC_BOOT_SIZE
-#define TX6_FLASH_SZ 3
++#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
+ #else
-#else /* CONFIG_NO_NAND */
-#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
-#endif /* CONFIG_NO_NAND */
++#define TX6_FLASH_SZ 2
+ #endif
-#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
-#define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
-#else
-#define TX6_DDR_SZ 2
-#endif
++#endif /* CONFIG_TX6_NAND */
+
-#if CONFIG_TX6_REV >= 0x3
++#define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
+
- '4', /* 256MiB SDRAM; 128MiB NAND */
- '1', /* 512MiB SDRAM; 128MiB NAND */
- '0', /* 1GiB SDRAM; 128MiB NAND */
- '?', /* 256MiB SDRAM; 256MiB NAND */
- '?', /* 512MiB SDRAM; 256MiB NAND */
- '2', /* 1GiB SDRAM; 256MiB NAND */
- '?', /* 256MiB SDRAM; 4GiB eMMC */
- '5', /* 512MiB SDRAM; 4GiB eMMC */
- '3', /* 1GiB SDRAM; 4GiB eMMC */
- '?', /* 256MiB SDRAM; 8GiB eMMC */
- '?', /* 512MiB SDRAM; 8GiB eMMC */
- '?', /* 1GiB SDRAM; 8GiB eMMC */
+ static char tx6_mem_table[] = {
-#else /* CONFIG_TX6_REV >= 0x3 */
-static inline char tx6_mem_suffix(void)
++ '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
++ '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
++ '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
++ '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
++ '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
++ '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
++ '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
++ '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
++ '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
++ '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
++ '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
++ '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
+ };
+
+ static inline char tx6_mem_suffix(void)
+ {
+ size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
+
+ debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
+ TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
+
+ if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
+ return '?';
+
+ return tx6_mem_table[mem_idx];
+ };
-#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
- if (CONFIG_SYS_SDRAM_BUS_WIDTH == 32)
- return '1';
-#endif
-#ifdef CONFIG_SYS_NAND_BLOCKS
- if (CONFIG_SYS_NAND_BLOCKS == 2048)
- return '2';
-#endif
- return '0';
++
++static struct {
++ uchar addr;
++ uchar rev;
++} tx6_mod_revs[] = {
++ { 0x3c, 1, },
++ { 0x32, 2, },
++ { 0x33, 3, },
++};
++
++static int tx6_get_mod_rev(void)
+ {
-#endif /* CONFIG_TX6_REV >= 0x3 */
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
++ int ret = i2c_probe(tx6_mod_revs[i].addr);
++ if (ret == 0) {
++ debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr);
++ return tx6_mod_revs[i].rev;
++ }
++ debug("I2C probe returned %d for addr %02x\n", ret,
++ tx6_mod_revs[i].addr);
++ }
++ return 0;
+ }
- is_lvds(), CONFIG_TX6_REV,
+
+ int checkboard(void)
+ {
+ u32 cpurev = get_cpu_rev();
+ int cpu_variant = (cpurev >> 12) & 0xff;
+
+ tx6qdl_print_cpuinfo();
+
++ i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */);
++
+ printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
+ tx6_mod_suffix,
+ cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
-void ft_board_setup(void *blob, bd_t *bd)
++ is_lvds(), tx6_get_mod_rev(),
+ tx6_mem_suffix());
+
+ return 0;
+ }
+
+ #ifdef CONFIG_SERIAL_TAG
+ void get_board_serial(struct tag_serialnr *serialnr)
+ {
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
+
+ serialnr->low = readl(&fuse->cfg0);
+ serialnr->high = readl(&fuse->cfg1);
+ }
+ #endif
+
+ #if defined(CONFIG_OF_BOARD_SETUP)
+ #ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ #include <jffs2/jffs2.h>
+ #include <mtd_node.h>
+ static struct node_info nodes[] = {
+ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
+ };
+ #else
+ #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+ #endif
+
+ static const char *tx6_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+ "eeti,egalax_ts",
+ };
+
- if (ret)
++int ft_board_setup(void *blob, bd_t *bd)
+ {
+ const char *baseboard = getenv("baseboard");
+ int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
-
++ if (ret) {
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
++ return ret;
++ }
+ if (stk5_v5)
+ karo_fdt_enable_node(blob, "stk5led", 0);
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
+ ARRAY_SIZE(tx6_touchpanels));
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
+ karo_fdt_fixup_flexcan(blob, stk5_v5);
+
+ karo_fdt_update_fb_mode(blob, video_mode);
++
++ return 0;
+ }
+ #endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
- _end = .;
+ /*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+ OUTPUT_ARCH(arm)
+ ENTRY(_start)
+ SECTIONS
+ {
+ . = 0x00000000;
+ .text :
+ {
+ *(.__image_copy_start)
++ *(.vectors)
+ CPUDIR/start.o (.text*)
+ . = 0x400;
+ KEEP(board/karo/tx6/lowlevel_init.o (.text*))
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn :
+ {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
++ .end :
++ {
++ *(.__end)
++ }
++
++ _image_binary_end = .;
+
+ /*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
++ .dynsym _image_binary_end : { *(.dynsym) }
++ .dynbss : { *(.dynbss) }
++ .dynstr : { *(.dynstr*) }
++ .dynamic : { *(.dynamic*) }
++ .plt : { *(.plt*) }
++ .interp : { *(.interp*) }
++ .gnu.hash : { *(.gnu.hash) }
++ .gnu : { *(.gnu*) }
++ .ARM.exidx : { *(.ARM.exidx*) }
++ .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
++
++/*
+ /DISCARD/ : { *(.bss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynsym*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.hash*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
++*/
+ }
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* Carrier MicroSD Card Detect */
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO_2__GPIO_1_2,
++ MX6_PAD_GPIO_2__GPIO1_IO02,
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* SOM MicroSD Card Detect */
- MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_DA9__GPIO_3_9,
++ MX6_PAD_EIM_DA9__GPIO3_IO09,
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
- MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D29__GPIO_3_29,
++ MX6_PAD_EIM_D29__GPIO3_IO29,
};
static void setup_iomux_uart(void)
}
#if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(void)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
-
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
-}
+struct i2c_pads_info i2c2_pad_info = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
-static struct fb_videomode const hdmi = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
+static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
+ | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
+
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+
- MX6_PAD_SD4_DAT2__GPIO2_IO10
- | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */
- MX6_PAD_SD4_DAT3__GPIO2_IO11
- | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */
++ MX6_PAD_SD4_DAT2__GPIO2_IO10, /* DISP0_BKLEN */
++ MX6_PAD_SD4_DAT3__GPIO2_IO11, /* DISP0_VDDEN */
};
-int board_video_skip(void)
+static void do_enable_hdmi(struct display_info_t const *dev)
{
- int ret;
-
- ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+ imx_enable_hdmi_phy();
+}
- if (ret)
- printf("HDMI cannot be configured: %d\n", ret);
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return (0 == i2c_set_bus_num(dev->bus)) &&
+ (0 == i2c_probe(dev->addr));
+}
- enable_hdmi();
+static void enable_fwadapt_7wvga(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ fwadapt_7wvga_pads,
+ ARRAY_SIZE(fwadapt_7wvga_pads));
- return ret;
+ gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
}
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 1,
+ .addr = 0x10,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = detect_i2c,
+ .enable = enable_fwadapt_7wvga,
+ .mode = {
+ .name = "FWBADAPT-LCD-F07A-0102",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin = 128,
+ .right_margin = 128,
+ .upper_margin = 22,
+ .lower_margin = 22,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
--- /dev/null
+menu "Command line interface"
+ depends on !SPL_BUILD
+
+config HUSH_PARSER
+ bool "Use hush shell"
+ select SYS_HUSH_PARSER
+ help
+ This option enables the "hush" shell (from Busybox) as command line
+ interpreter, thus enabling powerful command line syntax like
+ if...then...else...fi conditionals or `&&' and '||'
+ constructs ("shell scripts").
+
+ If disabled, you get the old, much simpler behaviour with a somewhat
+ smaller memory footprint.
+
+config SYS_HUSH_PARSER
+ bool
+ help
+ Backward compatibility.
+
+comment "Commands"
+
+menu "Info commands"
+
+config CMD_BDI
+ bool "bdinfo"
+ help
+ Print board info
+
+config CMD_CONSOLE
+ bool "coninfo"
+ help
+ Print console devices and information.
+
+config CMD_LICENSE
+ bool "license"
+ help
+ Print GPL license text
+
+endmenu
+
+menu "Boot commands"
+
+config CMD_BOOTD
+ bool "bootd"
+ help
+ Run the command stored in the environment "bootcmd", i.e.
+ "bootd" does the same thing as "run bootcmd".
+
+config CMD_BOOTM
+ bool "bootm"
+ default y
+ help
+ Boot an application image from the memory.
+
++config CMD_BOOTZ
++ bool "bootz"
++ default y
++ help
++ Boot a Linux kernel zImage.
++
++config CMD_BOOTCE
++ bool "bootce"
++ help
++ Boot a WindowsCE image.
++
+config CMD_GO
+ bool "go"
+ default y
+ help
+ Start an application at a given address.
+
+config CMD_RUN
+ bool "run"
+ help
+ Run the command in the given environment variable.
+
+config CMD_IMI
+ bool "iminfo"
+ help
+ Print header information for application image.
+
+config CMD_IMLS
+ bool "imls"
+ help
+ List all images found in flash
+
+config CMD_XIMG
+ bool "imxtract"
+ help
+ Extract a part of a multi-image.
+
+endmenu
+
++menu "DTB support"
++
++config OF_LIBFDT
++ bool "Enable FDT commands"
++
++config OF_BOARD_SETUP
++ bool "Support DT modifications by board code"
++ depends on OF_LIBFDT
++
++endmenu
++
+menu "Environment commands"
+
+config CMD_EXPORTENV
+ bool "env export"
+ default y
+ help
+ Export environments.
+
+config CMD_IMPORTENV
+ bool "env import"
+ default y
+ help
+ Import environments.
+
+config CMD_EDITENV
+ bool "editenv"
+ help
+ Edit environment variable.
+
+config CMD_SAVEENV
+ bool "saveenv"
+ help
+ Run the command in the given environment variable.
+
+endmenu
+
++menu "Environment configuration settings"
++
++choice
++ prompt "Select environment non-volatile storage"
++
++config ENV_IS_NOWHERE
++ bool "do not store environment"
++
++config ENV_IS_IN_NAND
++ bool "store environment in NAND"
++ depends on NAND
++
++config ENV_IS_IN_MMC
++ bool "store environment in MMC"
++ depends on MMC
++
++endchoice
++
++endmenu
++
+menu "Memory commands"
+
+config CMD_MEMORY
+ bool "md, mm, nm, mw, cp, cmp, base, loop"
+ help
+ Memeory commands.
+ md - memory display
+ mm - memory modify (auto-incrementing address)
+ nm - memory modify (constant address)
+ mw - memory write (fill)
+ cp - memory copy
+ cmp - memory compare
+ base - print or set address offset
+ loop - initinite loop on address range
+
+config CMD_CRC32
+ bool "crc32"
+ default y
+ help
+ Compute CRC32.
+
+config LOOPW
+ bool "loopw"
+ help
+ Infinite write loop on address range
+
+config CMD_MEMTEST
+ bool "crc32"
+ help
+ Simple RAM read/write test.
+
+config CMD_MX_CYCLIC
+ bool "mdc, mwc"
+ help
+ mdc - memory display cyclic
+ mwc - memory write cyclic
+
+config CMD_MEMINFO
+ bool "meminfo"
+ help
+ Display memory information.
+
+endmenu
+
+menu "Device access commands"
+
+config CMD_LOADB
+ bool "loadb"
+ help
+ Load a binary file over serial line.
+
+config CMD_LOADS
+ bool "loads"
+ help
+ Load an S-Record file over serial line
+
+config CMD_FLASH
+ bool "flinfo, erase, protect"
+ help
+ NOR flash support.
+ flinfo - print FLASH memory information
+ erase - FLASH memory
+ protect - enable or disable FLASH write protection
+
++config MTD_DEVICE
++ bool "MTD device support"
++
++config CMD_MTDPARTS
++ bool "MTD partitioning support"
++ default y
++ depends on MTD_DEVICE && (CMD_FLASH || CMD_NAND)
++
+config CMD_NAND
+ bool "nand"
+ help
+ NAND support.
+
++config CMD_NAND_TRIMFFS
++ bool "Enable nand write.trimffs command"
++ help
++ Enable command to leave page sized runs of 0xff patterns in
++ erased state rather than overwriting them. This is required
++ for using NAND flash filesystems on NAND controllers with
++ a non-0xff ECC code for all 0xff data.
++
++config CMD_MMC
++ bool "mmc/sd"
++ help
++ MMC/SD support.
++
+config CMD_SPI
+ bool "sspi"
+ help
+ SPI utility command.
+
+config CMD_I2C
+ bool "i2c"
+ help
+ I2C support.
+
+config CMD_USB
+ bool "usb"
+ help
+ USB support.
+
+config CMD_FPGA
+ bool "fpga"
+ help
+ FPGA support.
+
+endmenu
+
+
+menu "Shell scripting commands"
+
+config CMD_ECHO
+ bool "echo"
+ help
+ Echo args to console
+
+config CMD_ITEST
+ bool "itest"
+ help
+ Return true/false on integer compare.
+
+config CMD_SOURCE
+ bool "source"
+ help
+ Run script from memory
+
+endmenu
+
+menu "Network commands"
+
+config CMD_NET
+ bool "bootp, tftpboot"
+ help
+ Network commands.
+ bootp - boot image via network using BOOTP/TFTP protocol
+ tftpboot - boot image via network using TFTP protocol
+
+config CMD_TFTPPUT
+ bool "tftp put"
+ help
+ TFTP put command, for uploading files to a server
+
+config CMD_TFTPSRV
+ bool "tftpsrv"
+ help
+ Act as a TFTP server and boot the first received file
+
+config CMD_RARP
+ bool "rarpboot"
+ help
+ Boot image via network using RARP/TFTP protocol
+
+config CMD_DHCP
+ bool "dhcp"
+ help
+ Boot image via network using DHCP/TFTP protocol
+
+config CMD_NFS
+ bool "nfs"
+ help
+ Boot image via network using NFS protocol.
+
+config CMD_PING
+ bool "ping"
+ help
+ Send ICMP ECHO_REQUEST to network host
+
+config CMD_CDP
+ bool "cdp"
+ help
+ Perform CDP network configuration
+
+config CMD_SNTP
+ bool "sntp"
+ help
+ Synchronize RTC via network
+
+config CMD_DNS
+ bool "dns"
+ help
+ Lookup the IP of a hostname
+
+config CMD_DNS
+ bool "dns"
+ help
+ Lookup the IP of a hostname
+
+config CMD_LINK_LOCAL
+ bool "linklocal"
+ help
+ Acquire a network IP address using the link-local protocol
+
+endmenu
+
+menu "Misc commands"
+
++config CMD_CACHE
++ bool "cache control"
++ help
++ Enable commands to switch data cache on/off.
++
+config CMD_TIME
+ bool "time"
+ help
+ Run commands and summarize execution time.
+
+# TODO: rename to CMD_SLEEP
+config CMD_MISC
+ bool "sleep"
+ help
+ Delay execution for some time
+
+config CMD_TIMER
+ bool "timer"
+ help
+ Access the system timer.
+
+config CMD_SETGETDCR
+ bool "getdcr, setdcr, getidcr, setidcr"
+ depends on 4xx
+ help
+ getdcr - Get an AMCC PPC 4xx DCR's value
+ setdcr - Set an AMCC PPC 4xx DCR's value
+ getidcr - Get a register value via indirect DCR addressing
+ setidcr - Set a register value via indirect DCR addressing
+
+endmenu
+
+endmenu
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)libcommon.o
-
# core
ifndef CONFIG_SPL_BUILD
-COBJS-y += main.o
-COBJS-y += command.o
-COBJS-y += exports.o
-COBJS-y += hash.o
-COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
-COBJS-y += s_record.o
-COBJS-y += xyzModem.o
-COBJS-y += cmd_disk.o
+obj-y += main.o
+obj-y += exports.o
+obj-y += hash.o
+ifdef CONFIG_SYS_HUSH_PARSER
+obj-y += cli_hush.o
+endif
+
+# This option is not just y/n - it can have a numeric value
+ifdef CONFIG_BOOTDELAY
+obj-y += autoboot.o
+endif
+
+# This option is not just y/n - it can have a numeric value
+ifdef CONFIG_BOOT_RETRY_TIME
+obj-y += bootretry.o
+endif
# boards
-COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
-COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
+obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
# core command
-COBJS-y += cmd_boot.o
-COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
-COBJS-y += cmd_help.o
-COBJS-y += cmd_version.o
+obj-y += cmd_boot.o
+obj-$(CONFIG_CMD_BOOTM) += cmd_bootm.o bootm.o bootm_os.o
+obj-y += cmd_help.o
+obj-y += cmd_version.o
# environment
-COBJS-y += env_attr.o
-COBJS-y += env_callback.o
-COBJS-y += env_flags.o
-COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
-COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
-XCOBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
-COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
-XCOBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
-COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
-COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
-COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
-COBJS-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
-COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
-COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
-COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
-COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
-COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
-COBJS-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
-COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+obj-y += env_attr.o
+obj-y += env_callback.o
+obj-y += env_flags.o
+obj-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
+obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
+extra-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
+obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
+extra-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
+obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
+obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
+obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
+obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
+obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
+obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
+obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
+obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command
-COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
-COBJS-$(CONFIG_SOURCE) += cmd_source.o
-COBJS-$(CONFIG_CMD_SOURCE) += cmd_source.o
-COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
-COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
-COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o
-COBJS-$(CONFIG_CMD_BOOTCE) += cmd_bootce.o
-COBJS-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
-COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
-COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
-COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o
-COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
-COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
-COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
-COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
-COBJS-$(CONFIG_CMD_DATE) += cmd_date.o
-COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o
+obj-$(CONFIG_CMD_AES) += cmd_aes.o
+obj-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
+obj-$(CONFIG_SOURCE) += cmd_source.o
+obj-$(CONFIG_CMD_SOURCE) += cmd_source.o
+obj-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
+obj-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
+obj-$(CONFIG_CMD_BMP) += cmd_bmp.o
++obj-$(CONFIG_CMD_BOOTCE) += cmd_bootce.o
+obj-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
+obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
+obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
+obj-$(CONFIG_CMD_CACHE) += cmd_cache.o
+obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
+obj-$(CONFIG_CMD_CLK) += cmd_clk.o
+obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
+obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
+obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
+obj-$(CONFIG_CMD_DATE) += cmd_date.o
+obj-$(CONFIG_CMD_DEMO) += cmd_demo.o
+obj-$(CONFIG_CMD_SOUND) += cmd_sound.o
ifdef CONFIG_4xx
-COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
+obj-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
endif
ifdef CONFIG_POST
-COBJS-$(CONFIG_CMD_DIAG) += cmd_diag.o
+obj-$(CONFIG_CMD_DIAG) += cmd_diag.o
endif
-COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
-COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
-COBJS-$(CONFIG_CMD_ECHO) += cmd_echo.o
-COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
-COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
-COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
-COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
-COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o
-COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
-COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
-COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
-COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
-COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
-COBJS-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
-COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
+obj-$(CONFIG_CMD_DISPLAY) += cmd_display.o
+obj-$(CONFIG_CMD_DTT) += cmd_dtt.o
+obj-$(CONFIG_CMD_ECHO) += cmd_echo.o
+obj-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
+obj-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
+obj-$(CONFIG_CMD_ELF) += cmd_elf.o
+obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
+obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o
+obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o
+obj-$(CONFIG_CMD_FAT) += cmd_fat.o
+obj-$(CONFIG_CMD_FDC) += cmd_fdc.o
+obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
+obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
+obj-$(CONFIG_CMD_FLASH) += cmd_flash.o
ifdef CONFIG_FPGA
-COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
+obj-$(CONFIG_CMD_FPGA) += cmd_fpga.o
endif
-COBJS-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
-COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
-COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o
-COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
-COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
-COBJS-$(CONFIG_CMD_IIM) += cmd_iim.o
-COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
-COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o
-COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
-COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
-COBJS-$(CONFIG_CMD_INI) += cmd_ini.o
-COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
-COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
-COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
-COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
-COBJS-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
-COBJS-$(CONFIG_CMD_LED) += cmd_led.o
-COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o
-COBJS-y += cmd_load.o
-COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
-COBJS-$(CONFIG_ID_EEPROM) += cmd_mac.o
-COBJS-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
-COBJS-$(CONFIG_CMD_MEMORY) += cmd_mem.o
-COBJS-$(CONFIG_CMD_IO) += cmd_io.o
-COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
-COBJS-$(CONFIG_MII) += miiphyutil.o
-COBJS-$(CONFIG_CMD_MII) += miiphyutil.o
-COBJS-$(CONFIG_PHYLIB) += miiphyutil.o
-COBJS-$(CONFIG_CMD_MII) += cmd_mii.o
+obj-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
+obj-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
+obj-$(CONFIG_CMD_FUSE) += cmd_fuse.o
+obj-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
+obj-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+obj-$(CONFIG_CMD_I2C) += cmd_i2c.o
+obj-$(CONFIG_CMD_IOTRACE) += cmd_iotrace.o
+obj-$(CONFIG_CMD_HASH) += cmd_hash.o
+obj-$(CONFIG_CMD_IDE) += cmd_ide.o
+obj-$(CONFIG_CMD_IMMAP) += cmd_immap.o
+obj-$(CONFIG_CMD_INI) += cmd_ini.o
+obj-$(CONFIG_CMD_IRQ) += cmd_irq.o
+obj-$(CONFIG_CMD_ITEST) += cmd_itest.o
+obj-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
+obj-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
+obj-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
+obj-$(CONFIG_CMD_LED) += cmd_led.o
+obj-$(CONFIG_CMD_LICENSE) += cmd_license.o
+obj-y += cmd_load.o
+obj-$(CONFIG_LOGBUFFER) += cmd_log.o
+obj-$(CONFIG_ID_EEPROM) += cmd_mac.o
+obj-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
+obj-$(CONFIG_CMD_MEMORY) += cmd_mem.o
+obj-$(CONFIG_CMD_IO) += cmd_io.o
+obj-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
+obj-$(CONFIG_MII) += miiphyutil.o
+obj-$(CONFIG_CMD_MII) += miiphyutil.o
+obj-$(CONFIG_PHYLIB) += miiphyutil.o
+obj-$(CONFIG_CMD_MII) += cmd_mii.o
ifdef CONFIG_PHYLIB
-COBJS-$(CONFIG_CMD_MII) += cmd_mdio.o
+obj-$(CONFIG_CMD_MII) += cmd_mdio.o
endif
-COBJS-$(CONFIG_CMD_MISC) += cmd_misc.o
-COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
-COBJS-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
-COBJS-$(CONFIG_MP) += cmd_mp.o
-COBJS-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
-COBJS-$(CONFIG_CMD_NAND) += cmd_nand.o
-COBJS-$(CONFIG_CMD_NET) += cmd_net.o
-COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
-COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
-COBJS-$(CONFIG_CMD_PART) += cmd_part.o
-COBJS-$(CONFIG_CMD_PATA) += cmd_pata.o
+obj-$(CONFIG_CMD_MISC) += cmd_misc.o
+obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
+obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
+obj-$(CONFIG_MP) += cmd_mp.o
+obj-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
+obj-$(CONFIG_CMD_NAND) += cmd_nand.o
+obj-$(CONFIG_CMD_NET) += cmd_net.o
+obj-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
+obj-$(CONFIG_CMD_OTP) += cmd_otp.o
+obj-$(CONFIG_CMD_PART) += cmd_part.o
ifdef CONFIG_PCI
-COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
+obj-$(CONFIG_CMD_PCI) += cmd_pci.o
+endif
+obj-y += cmd_pcmcia.o
+obj-$(CONFIG_CMD_PORTIO) += cmd_portio.o
+obj-$(CONFIG_CMD_PXE) += cmd_pxe.o
+obj-$(CONFIG_CMD_READ) += cmd_read.o
+obj-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
+obj-$(CONFIG_CMD_REISER) += cmd_reiser.o
+obj-$(CONFIG_SANDBOX) += cmd_sandbox.o
+obj-$(CONFIG_CMD_SATA) += cmd_sata.o
+obj-$(CONFIG_CMD_SF) += cmd_sf.o
+obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
+obj-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
+obj-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
+obj-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
+obj-$(CONFIG_CMD_SPI) += cmd_spi.o
+obj-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
+obj-$(CONFIG_CMD_STRINGS) += cmd_strings.o
+obj-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
+obj-$(CONFIG_CMD_TIME) += cmd_time.o
+obj-$(CONFIG_CMD_TRACE) += cmd_trace.o
+obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
+obj-$(CONFIG_CMD_TPM) += cmd_tpm.o
+obj-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
+obj-$(CONFIG_CMD_UBI) += cmd_ubi.o
+obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
+obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
+obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
+ifdef CONFIG_LZMA
+obj-$(CONFIG_CMD_LZMADEC) += cmd_lzmadec.o
endif
-COBJS-y += cmd_pcmcia.o
-COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o
-COBJS-$(CONFIG_CMD_PXE) += cmd_pxe.o
-COBJS-$(CONFIG_CMD_READ) += cmd_read.o
-COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
-COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
-COBJS-$(CONFIG_SANDBOX) += cmd_sandbox.o
-COBJS-$(CONFIG_CMD_SATA) += cmd_sata.o
-COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
-COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
-COBJS-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
-COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
-COBJS-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
-COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
-COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
-COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
-COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
-COBJS-$(CONFIG_CMD_TIME) += cmd_time.o
-COBJS-$(CONFIG_CMD_TRACE) += cmd_trace.o
-COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
-COBJS-$(CONFIG_CMD_TPM) += cmd_tpm.o
-COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
-COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
-COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
-COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
-COBJS-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
ifdef CONFIG_CMD_USB
-COBJS-y += cmd_usb.o
-COBJS-y += usb.o usb_hub.o
-COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
+obj-y += cmd_usb.o
+obj-y += usb.o usb_hub.o
+obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
-COBJS-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
-COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
-COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
-COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o
-COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o
-COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
+obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
+obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o
+
+obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
+obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
+obj-$(CONFIG_CMD_XIMG) += cmd_ximg.o
+obj-$(CONFIG_YAFFS2) += cmd_yaffs2.o
+obj-$(CONFIG_CMD_SPL) += cmd_spl.o
+obj-$(CONFIG_CMD_ZIP) += cmd_zip.o
+obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o
# others
-COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o
-COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
-COBJS-y += flash.o
-COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
-COBJS-$(CONFIG_I2C_EDID) += edid.o
-COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
-COBJS-y += splash.o
-COBJS-$(CONFIG_LCD) += lcd.o
-COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
-COBJS-$(CONFIG_MENU) += menu.o
-COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
-COBJS-$(CONFIG_UPDATE_TFTP) += update.o
-COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
-COBJS-$(CONFIG_CMD_DFU) += cmd_dfu.o
-COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o
+obj-$(CONFIG_BOOTSTAGE) += bootstage.o
+obj-$(CONFIG_CONSOLE_MUX) += iomux.o
+obj-y += flash.o
+obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
+obj-$(CONFIG_I2C_EDID) += edid.o
+obj-$(CONFIG_KALLSYMS) += kallsyms.o
+obj-y += splash.o
+obj-$(CONFIG_LCD) += lcd.o
+obj-$(CONFIG_LYNXKDI) += lynxkdi.o
+obj-$(CONFIG_MENU) += menu.o
+obj-$(CONFIG_MODEM_SUPPORT) += modem.o
+obj-$(CONFIG_UPDATE_TFTP) += update.o
+obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
+obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
+obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
endif
ifdef CONFIG_SPL_BUILD
--- /dev/null
-#define UINT_MAX ~0UL
-
+ /*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: code from RedBoot (C) Uwe Steinkohl <US@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ #include <common.h>
+ #include <command.h>
+ #include <net.h>
+ #include <wince.h>
+ #include <nand.h>
+ #include <malloc.h>
+ #include <asm/errno.h>
+ #include <jffs2/load_kernel.h>
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define WINCE_VRAM_BASE 0x80000000
+ #define CE_FIX_ADDRESS(a) ((void *)((a) - WINCE_VRAM_BASE + CONFIG_SYS_SDRAM_BASE))
+
+ #ifndef INT_MAX
+ #define INT_MAX ((int)(~0U >> 1))
+ #endif
+
+ /* Bin image parse states */
+ #define CE_PS_RTI_ADDR 0
+ #define CE_PS_RTI_LEN 1
+ #define CE_PS_E_ADDR 2
+ #define CE_PS_E_LEN 3
+ #define CE_PS_E_CHKSUM 4
+ #define CE_PS_E_DATA 5
+
+ #define CE_MIN(a, b) (((a) < (b)) ? (a) : (b))
+ #define CE_MAX(a, b) (((a) > (b)) ? (a) : (b))
+
+ static ce_bin __attribute__ ((aligned (32))) g_bin;
+ static ce_net __attribute__ ((aligned (32))) g_net;
+ static IPaddr_t server_ip;
+
+ static void ce_init_bin(ce_bin *bin, unsigned char *dataBuffer)
+ {
+ memset(bin, 0, sizeof(*bin));
+
+ bin->data = dataBuffer;
+ bin->parseState = CE_PS_RTI_ADDR;
+ bin->parsePtr = (unsigned char *)bin;
+ }
+
+ static int ce_is_bin_image(void *image, int imglen)
+ {
+ if (imglen < CE_BIN_SIGN_LEN) {
+ return 0;
+ }
+
+ return memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0;
+ }
+
+ static const struct ce_magic {
+ char magic[8];
+ size_t size;
+ ce_std_driver_globals drv_glb;
+ } ce_magic_template = {
+ .magic = "KARO_CE6",
+ .size = sizeof(ce_std_driver_globals),
+ .drv_glb = {
+ .header = {
+ .signature = STD_DRV_GLB_SIGNATURE,
+ .oalVersion = 1,
+ .bspVersion = 2,
+ },
+ },
+ };
+
+ #ifdef DEBUG
+ static void __attribute__((unused)) ce_dump_block(void *ptr, int length)
+ {
+ char *p = ptr;
+ int i;
+ int j;
+
+ for (i = 0; i < length; i++) {
+ if (!(i % 16)) {
+ printf("\n%p: ", ptr + i);
+ }
+
+ printf("%02x ", p[i]);
+ if (!((i + 1) % 16)){
+ printf(" ");
+ for (j = i - 15; j <= i; j++){
+ if((p[j] > 0x1f) && (p[j] < 0x7f)) {
+ printf("%c", p[j]);
+ } else {
+ printf(".");
+ }
+ }
+ }
+ }
+ printf("\n");
+ }
+ #else
+ static inline void ce_dump_block(void *ptr, int length)
+ {
+ }
+ #endif
+
+ static void ce_setup_std_drv_globals(ce_std_driver_globals *std_drv_glb)
+ {
+ char *mtdparts = getenv("mtdparts");
+ size_t max_len = ALIGN((unsigned long)std_drv_glb, SZ_4K) -
+ (unsigned long)&std_drv_glb->mtdparts;
+
+ if (eth_get_dev()) {
+ memcpy(&std_drv_glb->kitl.mac, eth_get_dev()->enetaddr,
+ sizeof(std_drv_glb->kitl.mac));
+ }
+ snprintf(std_drv_glb->deviceId, sizeof(std_drv_glb->deviceId),
+ "Triton%02X", eth_get_dev()->enetaddr[5]);
+
+ NetCopyIP(&std_drv_glb->kitl.ipAddress, &NetOurIP);
+ std_drv_glb->kitl.ipMask = getenv_IPaddr("netmask");
+ std_drv_glb->kitl.ipRoute = getenv_IPaddr("gatewayip");
+
+ if (mtdparts) {
+ strncpy(std_drv_glb->mtdparts, mtdparts, max_len);
+ std_drv_glb->mtdparts[max_len - 1] = '\0';
+ } else {
+ printf("Failed to get mtdparts environment variable\n");
+ }
+ }
+
+ static void ce_init_drv_globals(void)
+ {
+ struct ce_magic *ce_magic = (void *)CONFIG_SYS_SDRAM_BASE + 0x160;
+ ce_std_driver_globals *std_drv_glb = &ce_magic->drv_glb;
+
+ debug("Copying CE MAGIC from %p to %p..%p\n",
+ &ce_magic_template, ce_magic,
+ (void *)ce_magic + sizeof(*ce_magic) - 1);
+ memcpy(ce_magic, &ce_magic_template, sizeof(*ce_magic));
+
+ ce_setup_std_drv_globals(std_drv_glb);
+ ce_magic->size = sizeof(*std_drv_glb) +
+ strlen(std_drv_glb->mtdparts) + 1;
+ ce_dump_block(ce_magic, offsetof(struct ce_magic, drv_glb) +
+ ce_magic->size);
+ }
+
+ static void ce_prepare_run_bin(ce_bin *bin)
+ {
+ /* Clear os RAM area (if needed) */
+ if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) {
+ debug("cleaning memory from %p to %p\n",
+ bin->eRamStart, bin->eRamStart + bin->eRamLen);
+
+ printf("Preparing clean boot ... ");
+ memset(bin->eRamStart, 0, bin->eRamLen);
+ printf("ok\n");
+ }
+
+ ce_init_drv_globals();
+
+ /*
+ * Make sure, all the above makes it into SDRAM because
+ * WinCE switches the cache & MMU off, obviously without
+ * flushing it first!
+ */
+ flush_dcache_all();
+ }
+
+ static int ce_lookup_ep_bin(ce_bin *bin)
+ {
+ ce_rom_hdr *header;
+ ce_toc_entry *tentry;
+ e32_rom *e32;
+ unsigned int i;
+ uint32_t *sig = (uint32_t *)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET);
+
+ debug("Looking for TOC signature at %p\n", sig);
+
+ /* Check image Table Of Contents (TOC) signature */
+ if (*sig != ROM_SIGNATURE) {
+ printf("Error: Did not find image TOC signature!\n");
+ printf("Expected %08x at address %p; found %08x instead\n",
+ ROM_SIGNATURE, sig, *sig);
+ return 0;
+ }
+
+ /* Lookup entry point */
+ header = CE_FIX_ADDRESS(*(unsigned int *)(bin->rtiPhysAddr +
+ ROM_SIGNATURE_OFFSET +
+ sizeof(unsigned int)));
+ tentry = (ce_toc_entry *)(header + 1);
+
+ for (i = 0; i < header->nummods; i++) {
+ // Look for 'nk.exe' module
+ if (strcmp(CE_FIX_ADDRESS(tentry[i].fileName), "nk.exe") == 0) {
+ // Save entry point and RAM addresses
+
+ e32 = CE_FIX_ADDRESS(tentry[i].e32Offset);
+
+ bin->eEntryPoint = CE_FIX_ADDRESS(tentry[i].loadOffset) +
+ e32->e32_entryrva;
+ bin->eRamStart = CE_FIX_ADDRESS(header->ramStart);
+ bin->eRamLen = header->ramEnd - header->ramStart;
+ return 1;
+ }
+ }
+
+ // Error: Did not find 'nk.exe' module
+ return 0;
+ }
+
+ static int ce_parse_bin(ce_bin *bin)
+ {
+ unsigned char *pbData = bin->data;
+ int len = bin->dataLen;
+ int copyLen;
+
+ debug("starting ce image parsing:\n\tbin->binLen: 0x%08X\n", bin->binLen);
+
+ if (len) {
+ if (bin->binLen == 0) {
+ // Check for the .BIN signature first
+ if (!ce_is_bin_image(pbData, len)) {
+ printf("Error: Invalid or corrupted .BIN image!\n");
+ return CE_PR_ERROR;
+ }
+
+ printf("Loading Windows CE .BIN image ...\n");
+ // Skip signature
+ len -= CE_BIN_SIGN_LEN;
+ pbData += CE_BIN_SIGN_LEN;
+ }
+
+ while (len) {
+ switch (bin->parseState) {
+ case CE_PS_RTI_ADDR:
+ case CE_PS_RTI_LEN:
+ case CE_PS_E_ADDR:
+ case CE_PS_E_LEN:
+ case CE_PS_E_CHKSUM:
+ copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, len);
+ memcpy(&bin->parsePtr[bin->parseLen], pbData, copyLen);
+
+ bin->parseLen += copyLen;
+ len -= copyLen;
+ pbData += copyLen;
+
+ if (bin->parseLen == sizeof(unsigned int)) {
+ if (bin->parseState == CE_PS_RTI_ADDR)
+ bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr);
+ else if (bin->parseState == CE_PS_E_ADDR &&
+ bin->ePhysAddr)
+ bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr);
+
+ bin->parseState++;
+ bin->parseLen = 0;
+ bin->parsePtr += sizeof(unsigned int);
+
+ if (bin->parseState == CE_PS_E_DATA) {
+ if (bin->ePhysAddr) {
+ bin->parsePtr = bin->ePhysAddr;
+ bin->parseChkSum = 0;
+ } else {
+ /* EOF */
+ len = 0;
+ bin->endOfBin = 1;
+ }
+ }
+ }
+ break;
+
+ case CE_PS_E_DATA:
+ debug("ePhysAddr=%p physlen=%08x parselen=%08x\n",
+ bin->ePhysAddr, bin->ePhysLen, bin->parseLen);
+ if (bin->ePhysAddr) {
+ copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, len);
+ bin->parseLen += copyLen;
+ len -= copyLen;
+
+ while (copyLen--) {
+ bin->parseChkSum += *pbData;
+ *bin->parsePtr++ = *pbData++;
+ }
+
+ if (bin->parseLen == bin->ePhysLen) {
+ printf("Section [%02d]: address %p, size 0x%08X, checksum %s\n",
+ bin->section,
+ bin->ePhysAddr,
+ bin->ePhysLen,
+ (bin->eChkSum == bin->parseChkSum) ? "ok" : "fail");
+
+ if (bin->eChkSum != bin->parseChkSum) {
+ printf("Error: Checksum error, corrupted .BIN file!\n");
+ printf("checksum calculated: 0x%08x from file: 0x%08x\n",
+ bin->parseChkSum, bin->eChkSum);
+ bin->binLen = 0;
+ return CE_PR_ERROR;
+ }
+
+ bin->section++;
+ bin->parseState = CE_PS_E_ADDR;
+ bin->parseLen = 0;
+ bin->parsePtr = (unsigned char *)&bin->ePhysAddr;
+ }
+ } else {
+ bin->parseLen = 0;
+ bin->endOfBin = 1;
+ len = 0;
+ }
+ break;
+ }
+ }
+ }
+
+ if (bin->endOfBin) {
+ if (!ce_lookup_ep_bin(bin)) {
+ printf("Error: entry point not found!\n");
+ bin->binLen = 0;
+ return CE_PR_ERROR;
+ }
+
+ printf("Entry point: %p, address range: %p-%p\n",
+ bin->eEntryPoint,
+ bin->rtiPhysAddr,
+ bin->rtiPhysAddr + bin->rtiPhysLen);
+
+ return CE_PR_EOF;
+ }
+
+ /* Need more data */
+ bin->binLen += bin->dataLen;
+ return CE_PR_MORE;
+ }
+
+ static int ce_bin_load(void *image, int imglen)
+ {
+ ce_init_bin(&g_bin, image);
+ g_bin.dataLen = imglen;
+ if (ce_parse_bin(&g_bin) == CE_PR_EOF) {
+ ce_prepare_run_bin(&g_bin);
+ return 1;
+ }
+
+ return 0;
+ }
+
+ static void ce_run_bin(void (*entry)(void))
+ {
+ printf("Launching Windows CE ...\n");
+ #ifdef TEST_LAUNCH
+ return;
+ #endif
+ entry();
+ }
+
+ static int do_bootce(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ void *addr;
+ size_t image_size;
+
+ if (argc > 1) {
+ if (strcmp(argv[1], "-i") == 0) {
+ ce_init_drv_globals();
+ return CMD_RET_SUCCESS;
+ }
+ addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ image_size = INT_MAX; /* actually we do not know the image size */
+ } else if (getenv("fileaddr") != NULL) {
+ addr = (void *)getenv_ulong("fileaddr", 16, 0);
+ image_size = getenv_ulong("filesize", 16, INT_MAX);
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ printf ("## Booting Windows CE Image from address %p ...\n", addr);
+
+ /* check if there is a valid windows CE image */
+ if (ce_is_bin_image(addr, image_size)) {
+ if (!ce_bin_load(addr, image_size)) {
+ /* Ops! Corrupted .BIN image! */
+ /* Handle error here ... */
+ printf("corrupted .BIN image !!!\n");
+ return CMD_RET_FAILURE;
+ }
+ if (getenv_yesno("autostart") != 1) {
+ /*
+ * just use bootce to load the image to SDRAM;
+ * Do not start it automatically.
+ */
+ setenv_addr("fileaddr", g_bin.eEntryPoint);
+ return CMD_RET_SUCCESS;
+ }
+ ce_run_bin(g_bin.eEntryPoint); /* start the image */
+ } else {
+ printf("Image does not seem to be a valid Windows CE image!\n");
+ return CMD_RET_FAILURE;
+ }
+ return CMD_RET_FAILURE; /* never reached - just to keep compiler happy */
+ }
+ U_BOOT_CMD(
+ bootce, 2, 0, do_bootce,
+ "Boot a Windows CE image from RAM",
+ "[addr]\n"
+ "\taddr\t\tboot image from address addr (default ${fileaddr})\n"
+ "or\n"
+ "\t-i\t\tinitialize the WinCE globals data structure (before loading a .nb0 image)"
+ );
+
+ #ifdef CONFIG_CMD_NAND
+ static int ce_nand_load(ce_bin *bin, loff_t *offset, void *buf, size_t max_len)
+ {
+ int ret;
+ size_t len = max_len;
+ nand_info_t *nand = &nand_info[0];
+
+ while (nand_block_isbad(nand, *offset & ~(max_len - 1))) {
+ printf("Skipping bad block 0x%08llx\n",
+ *offset & ~(max_len - 1));
+ *offset += max_len;
+ if (*offset + max_len > nand->size)
+ return -EINVAL;
+ }
+
+ ret = nand_read(nand, *offset, &len, buf);
+ if (ret < 0)
+ return ret;
+
+ bin->dataLen = len;
+ return len;
+ }
+
+ static int do_nbootce(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int ret;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ u8 part_num;
+ loff_t offset;
+ char *end;
+ void *buffer;
+ size_t bufsize = nand_info[0].erasesize, len;
+
+ if (argc < 2 || argc > 3)
+ return CMD_RET_USAGE;
+
+ ret = mtdparts_init();
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ offset = simple_strtoul(argv[1], &end, 16);
+ if (*end != '\0') {
+ ret = find_dev_and_part(argv[1], &dev, &part_num,
+ &part_info);
+ if (ret != 0) {
+ printf("Partition '%s' not found\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ offset = part_info->offset;
+ printf ("## Booting Windows CE Image from NAND partition %s at offset %08llx\n",
+ argv[1], offset);
+ } else {
+ printf ("## Booting Windows CE Image from NAND offset %08llx\n",
+ offset);
+ }
+
+ buffer = malloc(bufsize);
+ if (buffer == NULL) {
+ printf("Failed to allocate %u byte buffer\n", bufsize);
+ return CMD_RET_FAILURE;
+ }
+
+ ce_init_bin(&g_bin, buffer);
+
+ ret = ce_nand_load(&g_bin, &offset, buffer, bufsize);
+ if (ret < 0) {
+ printf("Failed to read NAND: %d\n", ret);
+ goto err;
+ }
+ len = ret;
+ /* check if there is a valid windows CE image header */
+ if (ce_is_bin_image(buffer, len)) {
+ do {
+ ret = ce_parse_bin(&g_bin);
+ switch (ret) {
+ case CE_PR_MORE:
+ {
+ if (ctrlc()) {
+ printf("NBOOTCE - canceled by user\n");
+ goto err;
+ }
+ offset += len;
+ len = ce_nand_load(&g_bin, &offset, buffer,
+ bufsize);
+ if (len < 0) {
+ printf("Nand read error: %d\n", len);
+ ret = len;
+ goto err;
+ }
+ }
+ break;
+
+ case CE_PR_EOF:
+ ce_prepare_run_bin(&g_bin);
+ break;
+
+ case CE_PR_ERROR:
+ break;
+ }
+ } while (ret == CE_PR_MORE);
+ free(buffer);
+ if (ret != CE_PR_EOF)
+ return CMD_RET_FAILURE;
+
+ if (getenv_yesno("autostart") != 1) {
+ /*
+ * just use bootce to load the image to SDRAM;
+ * Do not start it automatically.
+ */
+ setenv_addr("fileaddr", g_bin.eEntryPoint);
+ return CMD_RET_SUCCESS;
+ }
+ ce_run_bin(g_bin.eEntryPoint); /* start the image */
+ } else {
+ printf("Image does not seem to be a valid Windows CE image!\n");
+ }
+ err:
+ free(buffer);
+ return CMD_RET_FAILURE;
+ }
+ U_BOOT_CMD(
+ nbootce, 2, 0, do_nbootce,
+ "Boot a Windows CE image from NAND",
+ "off|partitition\n"
+ "\toff\t\t- flash offset (hex)\n"
+ "\tpartition\t- partition name"
+ );
+ #endif
+
+ static int ce_send_write_ack(ce_net *net)
+ {
+ int ret;
+ unsigned short wdata[2];
+ int retries = 0;
+
+ wdata[0] = htons(EDBG_CMD_WRITE_ACK);
+ wdata[1] = htons(net->blockNum);
+ net->dataLen = sizeof(wdata);
+ memcpy(net->data, wdata, net->dataLen);
+
+ do {
+ ret = bootme_send_frame(net->data, net->dataLen);
+ if (ret) {
+ printf("Failed to send write ack %d; retries=%d\n",
+ ret, retries);
+ }
+ } while (ret != 0 && retries-- > 0);
+ return ret;
+ }
+
+ static enum bootme_state ce_process_download(ce_net *net, ce_bin *bin)
+ {
+ int ret = net->state;
+
+ if (net->dataLen >= 4) {
+ unsigned short command;
+ unsigned short blknum;
+
+ memcpy(&command, net->data, sizeof(command));
+ command = ntohs(command);
+ debug("command found: 0x%04X\n", command);
+
+ if (net->state == BOOTME_DOWNLOAD) {
+ unsigned short nxt = net->blockNum + 1;
+
+ memcpy(&blknum, &net->data[2], sizeof(blknum));
+ blknum = ntohs(blknum);
+ if (blknum == nxt) {
+ net->blockNum = blknum;
+ } else {
+ int rc = ce_send_write_ack(net);
+
+ if (net->verbose)
+ printf("Dropping out of sequence packet with ID %d (expected %d)\n",
+ blknum, nxt);
+ if (rc != 0)
+ return rc;
+
+ return ret;
+ }
+ }
+
+ switch (command) {
+ case EDBG_CMD_WRITE_REQ:
+ if (net->state == BOOTME_INIT) {
+ // Check file name for WRITE request
+ // CE EShell uses "boot.bin" file name
+ if (strncmp((char *)&net->data[2],
+ "boot.bin", 8) == 0) {
+ // Some diag output
+ if (net->verbose) {
+ printf("Locked Down download link, IP: %pI4\n",
+ &NetServerIP);
+ printf("Sending BOOTME request [%d] to %pI4\n",
+ net->seqNum, &NetServerIP);
+ }
+
+ // Lock down EShell download link
+ ret = BOOTME_DOWNLOAD;
+ } else {
+ // Unknown link
+ printf("Unknown link\n");
+ }
+
+ if (ret == BOOTME_DOWNLOAD) {
+ int rc = ce_send_write_ack(net);
+ if (rc != 0)
+ return rc;
+ }
+ }
+ break;
+
+ case EDBG_CMD_WRITE:
+ /* Fixup data len */
+ bin->data = &net->data[4];
+ bin->dataLen = net->dataLen - 4;
+ ret = ce_parse_bin(bin);
+ if (ret != CE_PR_ERROR) {
+ int rc = ce_send_write_ack(net);
+ if (rc)
+ return rc;
+ if (ret == CE_PR_EOF)
+ ret = BOOTME_DONE;
+ } else {
+ ret = BOOTME_ERROR;
+ }
+ break;
+
+ case EDBG_CMD_READ_REQ:
+ printf("Ignoring EDBG_CMD_READ_REQ\n");
+ /* Read requests are not supported
+ * Do nothing ...
+ */
+ break;
+
+ case EDBG_CMD_ERROR:
+ printf("Error: unknown error on the host side\n");
+
+ bin->binLen = 0;
+ ret = BOOTME_ERROR;
+ break;
+
+ default:
+ printf("unknown command 0x%04X\n", command);
+ net->state = BOOTME_ERROR;
+ }
+ }
+ return ret;
+ }
+
+ static enum bootme_state ce_process_edbg(ce_net *net, ce_bin *bin)
+ {
+ enum bootme_state ret = net->state;
+ eth_dbg_hdr header;
+
+ if (net->dataLen < sizeof(header)) {
+ /* Bad packet */
+ printf("Invalid packet size %u\n", net->dataLen);
+ net->dataLen = 0;
+ return ret;
+ }
+ memcpy(&header, net->data, sizeof(header));
+ if (header.id != EDBG_ID) {
+ /* Bad packet */
+ printf("Bad EDBG ID %08x\n", header.id);
+ net->dataLen = 0;
+ return ret;
+ }
+
+ if (header.service != EDBG_SVC_ADMIN) {
+ /* Unknown service */
+ printf("Bad EDBG service %02x\n", header.service);
+ net->dataLen = 0;
+ return ret;
+ }
+
+ if (net->state == BOOTME_INIT) {
+ /* Some diag output */
+ if (net->verbose) {
+ printf("Locked Down EDBG service link, IP: %pI4\n",
+ &NetServerIP);
+ }
+
+ /* Lock down EDBG link */
+ net->state = BOOTME_DEBUG;
+ }
+
+ switch (header.cmd) {
+ case EDBG_CMD_JUMPIMG:
+ net->gotJumpingRequest = 1;
+
+ if (net->verbose) {
+ printf("Received JUMPING command\n");
+ }
+ /* Just pass through and copy CONFIG structure */
+ ret = BOOTME_DONE;
+ case EDBG_CMD_OS_CONFIG:
+ /* Copy config structure */
+ memcpy(&bin->edbgConfig, &net->data[sizeof(header)],
+ sizeof(edbg_os_config_data));
+ if (net->verbose) {
+ printf("Received CONFIG command\n");
+ if (bin->edbgConfig.flags & EDBG_FL_DBGMSG) {
+ printf("--> Enabling DBGMSG service, IP: %pI4, port: %d\n",
+ &bin->edbgConfig.dbgMsgIPAddr,
+ ntohs(bin->edbgConfig.dbgMsgPort));
+ }
+
+ if (bin->edbgConfig.flags & EDBG_FL_PPSH) {
+ printf("--> Enabling PPSH service, IP: %pI4, port: %d\n",
+ &bin->edbgConfig.ppshIPAddr,
+ ntohs(bin->edbgConfig.ppshPort));
+ }
+
+ if (bin->edbgConfig.flags & EDBG_FL_KDBG) {
+ printf("--> Enabling KDBG service, IP: %pI4, port: %d\n",
+ &bin->edbgConfig.kdbgIPAddr,
+ ntohs(bin->edbgConfig.kdbgPort));
+ }
+
+ if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) {
+ printf("--> Force clean boot\n");
+ }
+ }
+ break;
+
+ default:
+ if (net->verbose) {
+ printf("Received unknown command: %08X\n", header.cmd);
+ }
+ return BOOTME_ERROR;
+ }
+
+ /* Respond with ack */
+ header.flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK;
+ memcpy(net->data, &header, sizeof(header));
+ net->dataLen = EDBG_DATA_OFFSET;
+
+ int retries = 10;
+ int rc;
+ do {
+ rc = bootme_send_frame(net->data, net->dataLen);
+ if (rc != 0) {
+ printf("Failed to send ACK: %d\n", rc);
+ }
+ } while (rc && retries-- > 0);
+ return rc ?: ret;
+ }
+
+ static enum bootme_state ce_edbg_handler(const void *buf, size_t len)
+ {
+ if (len == 0)
+ return BOOTME_DONE;
+
+ g_net.data = (void *)buf;
+ g_net.dataLen = len;
+
+ return ce_process_edbg(&g_net, &g_bin);
+ }
+
+ static void ce_init_edbg_link(ce_net *net)
+ {
+ /* Initialize EDBG link for commands */
+ net->state = BOOTME_INIT;
+ }
+
+ static enum bootme_state ce_download_handler(const void *buf, size_t len)
+ {
+ g_net.data = (void *)buf;
+ g_net.dataLen = len;
+
+ g_net.state = ce_process_download(&g_net, &g_bin);
+ return g_net.state;
+ }
+
+ static int ce_send_bootme(ce_net *net)
+ {
+ eth_dbg_hdr *header;
+ edbg_bootme_data *data;
+ unsigned char txbuf[PKTSIZE_ALIGN];
+ #ifdef DEBUG
+ int i;
+ unsigned char *pkt;
+ #endif
+ /* Fill out BOOTME packet */
+ net->data = txbuf;
+
+ memset(net->data, 0, PKTSIZE);
+ header = (eth_dbg_hdr *)net->data;
+ data = (edbg_bootme_data *)header->data;
+
+ header->id = EDBG_ID;
+ header->service = EDBG_SVC_ADMIN;
+ header->flags = EDBG_FL_FROM_DEV;
+ header->seqNum = net->seqNum++;
+ header->cmd = EDBG_CMD_BOOTME;
+
+ data->versionMajor = 0;
+ data->versionMinor = 0;
+ data->cpuId = EDBG_CPU_TYPE_ARM;
+ data->bootmeVer = EDBG_CURRENT_BOOTME_VERSION;
+ data->bootFlags = 0;
+ data->downloadPort = 0;
+ data->svcPort = 0;
+
+ /* MAC address from environment*/
+ if (!eth_getenv_enetaddr("ethaddr", data->macAddr)) {
+ printf("'ethaddr' is not set or invalid\n");
+ memset(data->macAddr, 0, sizeof(data->macAddr));
+ }
+
+ /* IP address from active config */
+ NetCopyIP(&data->ipAddr, &NetOurIP);
+
+ // Device name string (NULL terminated). Should include
+ // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc)
+
+ // We will use lower MAC address segment to create device name
+ // eg. MAC '00-0C-C6-69-09-05', device name 'Triton05'
+
+ strncpy(data->platformId, "Triton", sizeof(data->platformId));
+ snprintf(data->deviceName, sizeof(data->deviceName), "%s%02X",
+ data->platformId, data->macAddr[5]);
+
+ #ifdef DEBUG
+ printf("header->id: %08X\n", header->id);
+ printf("header->service: %08X\n", header->service);
+ printf("header->flags: %08X\n", header->flags);
+ printf("header->seqNum: %08X\n", header->seqNum);
+ printf("header->cmd: %08X\n\n", header->cmd);
+
+ printf("data->versionMajor: %08X\n", data->versionMajor);
+ printf("data->versionMinor: %08X\n", data->versionMinor);
+ printf("data->cpuId: %08X\n", data->cpuId);
+ printf("data->bootmeVer: %08X\n", data->bootmeVer);
+ printf("data->bootFlags: %08X\n", data->bootFlags);
+ printf("data->svcPort: %08X\n\n", ntohs(data->svcPort));
+
+ printf("data->macAddr: %pM\n", data->macAddr);
+ printf("data->ipAddr: %pI4\n", &data->ipAddr);
+ printf("data->platformId: %s\n", data->platformId);
+ printf("data->deviceName: %s\n", data->deviceName);
+ #endif
+ // Some diag output ...
+ if (net->verbose) {
+ printf("Sending BOOTME request [%d] to %pI4\n", net->seqNum,
+ &server_ip);
+ }
+
+ net->dataLen = BOOTME_PKT_SIZE;
+ // net->status = CE_PR_MORE;
+ net->state = BOOTME_INIT;
+ #ifdef DEBUG
+ debug("Start of buffer: %p\n", net->data);
+ debug("Start of ethernet buffer: %p\n", net->data);
+ debug("Start of CE header: %p\n", header);
+ debug("Start of CE data: %p\n", data);
+
+ pkt = net->data;
+ debug("packet to send (ceconnect): \n");
+ for (i = 0; i < net->dataLen; i++) {
+ debug("0x%02X ", pkt[i]);
+ if (!((i + 1) % 16))
+ debug("\n");
+ }
+ debug("\n");
+ #endif
+ return BootMeRequest(server_ip, net->data, net->dataLen, 1);
+ }
+
+ static inline int ce_init_download_link(ce_net *net, ce_bin *bin, int verbose)
+ {
+ if (!eth_get_dev()) {
+ printf("No network interface available\n");
+ return -ENODEV;
+ }
+ printf("Using device '%s'\n", eth_get_name());
+
+ /* Initialize EDBG link for download */
+ memset(net, 0, sizeof(*net));
+
+ net->verbose = verbose;
+
+ /* buffer will be dynamically assigned in ce_download_handler() */
+ ce_init_bin(bin, NULL);
+ return 0;
+ }
+
- printf("Timeout value %lu out of range (max.: %lu)\n",
+ static inline int ce_download_file(ce_net *net, ulong timeout)
+ {
+ ulong start = get_timer_masked();
+
+ while (net->state == BOOTME_INIT) {
+ int ret;
+
+ if (timeout && get_timer(start) > timeout) {
+ printf("CELOAD - Canceled, timeout\n");
+ return 1;
+ }
+
+ if (ctrlc()) {
+ printf("CELOAD - canceled by user\n");
+ return 1;
+ }
+
+ if (ce_send_bootme(&g_net)) {
+ printf("CELOAD - error while sending BOOTME request\n");
+ return 1;
+ }
+ if (net->verbose) {
+ if (timeout) {
+ printf("Waiting for connection, timeout %lu sec\n",
+ DIV_ROUND_UP(timeout - get_timer(start),
+ CONFIG_SYS_HZ));
+ } else {
+ printf("Waiting for connection, enter ^C to abort\n");
+ }
+ }
+
+ ret = BootMeDownload(ce_download_handler);
+ if (ret == BOOTME_ERROR) {
+ printf("CELOAD - aborted\n");
+ return 1;
+ }
+ }
+ return 0;
+ }
+
+ static void ce_disconnect(void)
+ {
+ net_set_udp_handler(NULL);
+ eth_halt();
+ }
+
+ static int do_ceconnect(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int verbose = 0;
+ ulong timeout = 0;
+ int ret = 1;
+ int i;
+
+ server_ip = 0;
+
+ for (i = 1; i < argc; i++){
+ if (*argv[i] != '-')
+ break;
+ if (argv[i][1] == 'v') {
+ verbose = 1;
+ } else if (argv[i][1] == 't') {
+ i++;
+ if (argc > i) {
+ timeout = simple_strtoul(argv[i],
+ NULL, 0);
+ if (timeout >= UINT_MAX / CONFIG_SYS_HZ) {
++ printf("Timeout value %lu out of range (max.: %u)\n",
+ timeout, UINT_MAX / CONFIG_SYS_HZ - 1);
+ return CMD_RET_USAGE;
+ }
+ timeout *= CONFIG_SYS_HZ;
+ } else {
+ printf("Option requires an argument - t\n");
+ return CMD_RET_USAGE;
+ }
+ } else if (argv[i][1] == 'h') {
+ i++;
+ if (argc > i) {
+ server_ip = string_to_ip(argv[i]);
+ printf("Using server %pI4\n", &server_ip);
+ } else {
+ printf("Option requires an argument - h\n");
+ return CMD_RET_USAGE;
+ }
+ }
+ }
+
+ if (ce_init_download_link(&g_net, &g_bin, verbose) != 0)
+ goto err;
+
+ if (ce_download_file(&g_net, timeout))
+ goto err;
+
+ if (g_bin.binLen) {
+ // Try to receive edbg commands from host
+ ce_init_edbg_link(&g_net);
+ if (verbose)
+ printf("Waiting for EDBG commands ...\n");
+
+ ret = BootMeDebugStart(ce_edbg_handler);
+ if (ret != BOOTME_DONE)
+ goto err;
+
+ // Prepare WinCE image for execution
+ ce_prepare_run_bin(&g_bin);
+
+ // Launch WinCE, if necessary
+ if (g_net.gotJumpingRequest)
+ ce_run_bin(g_bin.eEntryPoint);
+ }
+ ret = 0;
+ err:
+ ce_disconnect();
+ return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
+ }
+ U_BOOT_CMD(
+ ceconnect, 6, 1, do_ceconnect,
+ "Set up a connection to the CE host PC over TCP/IP and download the run-time image",
+ "[-v] [-t <timeout>] [-h host]\n"
+ " -v - verbose operation\n"
+ " -t <timeout> - max wait time (#sec) for the connection\n"
+ " -h <host> - send BOOTME requests to <host> (default: broadcast address 255.255.255.255)"
+ );
* Only one eraseregion (NAND, OneNAND or uniform NOR),
* checking for alignment is easy here
*/
- if ((unsigned long)part->offset % mtd->erasesize) {
+ offset = part->offset;
+ if (do_div(offset, mtd->erasesize)) {
- printf("%s%d: partition (%s) start offset"
- "alignment incorrect\n",
+ printf("%s%d: partition (%s) start offset alignment incorrect\n",
MTD_DEV_TYPE(id->type), id->num, part->name);
return 1;
}
opts.spread = spread;
if (scrub) {
- if (!scrub_yes)
- puts(scrub_warn);
-
- if (scrub_yes)
+ if (scrub_yes) {
opts.scrub = 1;
- else if (getc() == 'y') {
- puts("y");
- if (getc() == '\r')
+ } else {
+ puts(scrub_warn);
+ if (confirm_yesno()) {
opts.scrub = 1;
- else {
+ } else {
puts("scrub aborted\n");
- return 1;
+ return CMD_RET_FAILURE;
}
- } else {
- puts("scrub aborted\n");
- return CMD_RET_FAILURE;
}
}
ret = nand_erase_opts(nand, &opts);
#endif
#if LCD_BPP == LCD_MONOCHROME
-- ushort off = x * (1 << LCD_BPP) % 8;
++ ushort off = x * NBITS(LCD_BPP) % 8;
#endif
- dest = (uchar *)(lcd_base + y * lcd_line_length + x * NBITS(LCD_BPP)/8);
- dest = lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8;
++ dest = lcd_base + y * lcd_line_length + x * NBITS(LCD_BPP) / 8;
for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
uchar *s = str;
CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN,
};
-#elif LCD_BPP == LCD_COLOR24
+ #if LCD_BPP == LCD_COLOR8
+ typedef uchar pix_t;
+ #elif LCD_BPP == LCD_COLOR16
+ typedef ushort pix_t;
++#elif LCD_BPP == LCD_COLOR32
+ typedef ulong pix_t;
+ #else
+ #error Unsupported pixelformat
+ #endif
+
static void test_pattern(void)
{
ushort v_max = panel_info.vl_row;
test_pattern();
#else
/* set framebuffer to background color */
+#if (LCD_BPP != LCD_COLOR32)
memset((char *)lcd_base,
- COLOR_MASK(lcd_getbgcolor()),
+ COLOR_MASK(lcd_color_bg),
lcd_line_length * panel_info.vl_row);
+#else
+ u32 *ppix = lcd_base;
+ u32 i;
+ for (i = 0;
+ i < (lcd_line_length * panel_info.vl_row)/NBYTES(panel_info.vl_bpix);
+ i++) {
+ *ppix++ = COLOR_MASK(lcd_color_bg);
+ }
+#endif
#endif
/* Paint the logo and retrieve LCD base address */
- debug("[LCD] Drawing the logo...\n");
+ debug("[LCD] Drawing the logo @ %p...\n", lcd_base);
lcd_console_address = lcd_logo();
console_col = 0;
#endif
#endif /* CONFIG_BMP_16BPP */
+ static inline bmp_color_table_entry_t *get_color_table(bmp_image_t *bmp)
+ {
+ bmp_header_t *bh = &bmp->header;
+ return (void *)bmp + offsetof(bmp_header_t, size) + bh->size;
+ }
+
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
-#if !defined(CONFIG_MCC200)
ushort *cmap = NULL;
-#endif
ushort *cmap_base = NULL;
ushort i, j;
uchar *fb;
- bmp_image_t *bmp=(bmp_image_t *)bmp_image;
+ bmp_image_t *bmp = (bmp_image_t *)map_sysmem(bmp_image, 0);
uchar *bmap;
ushort padded_width;
- unsigned long width, height, byte_width;
+ unsigned long width, height;
unsigned long pwidth = panel_info.vl_col;
- unsigned colors, bpix, bmp_bpix;
+ unsigned long long colors;
+ unsigned bpix, bmp_bpix;
+ bmp_color_table_entry_t *cte;
if (!bmp || !(bmp->header.signature[0] == 'B' &&
bmp->header.signature[1] == 'M')) {
return 1;
}
- debug("Display-bmp: %d x %d with %d colors\n",
- (int)width, (int)height, (int)colors);
+ debug("Display-bmp: %lu x %lu with %llu colors\n",
+ width, height, colors);
-#if !defined(CONFIG_MCC200)
- /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
+ cte = get_color_table(bmp);
if (bmp_bpix == 8) {
cmap = configuration_get_cmap();
cmap_base = cmap;
#endif
}
}
-#endif
-
- /*
- * BMP format for Monochrome assumes that the state of a
- * pixel is described on a per Bit basis, not per Byte.
- * So, in case of Monochrome BMP we should align widths
- * on a byte boundary and convert them from Bit to Byte
- * units.
- * Probably, PXA250 and MPC823 process 1bpp BMP images in
- * their own ways, so make the converting to be MCC200
- * specific.
- */
-#if defined(CONFIG_MCC200)
- if (bpix == 1) {
- width = ALIGN(width, 8) >> 3;
- x = ALIGN(x, 8) >> 3;
- pwidth= ALIGN(pwidth, 8) >> 3;
- }
-#endif
- padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width);
+ padded_width = ALIGN(width, 4);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
splash_align_axis(&x, pwidth, width);
splash_align_axis(&y, panel_info.vl_row, height);
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
- bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
++ bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
if ((x + width) > pwidth)
width = pwidth - x;
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
for (j = 0; j < width; j++) {
- if (bpix != 16) {
- FB_PUT_BYTE(fb, bmap);
- } else {
+ if (bpix == 32) {
+ int i = *bmap++;
+
+ fb[3] = 0; /* T */
+ fb[0] = cte[i].blue;
+ fb[1] = cte[i].green;
+ fb[2] = cte[i].red;
+ fb += sizeof(uint32_t) / sizeof(*fb);
+ } else if (bpix == 16) {
*(uint16_t *)fb = cmap_base[*(bmap++)];
fb += sizeof(uint16_t) / sizeof(*fb);
+ } else {
+ FB_PUT_BYTE(fb, bmap);
}
}
- bmap += (padded_width - width);
- fb -= byte_width + lcd_line_length;
+ if (bpix > 8) {
+ bmap += padded_width - width;
+ fb -= width * bpix / 8 + lcd_line_length;
+ } else {
+ bmap += padded_width;
+ fb -= lcd_line_length;
+ }
}
break;
-
+ }
#if defined(CONFIG_BMP_16BPP)
case 16:
for (i = 0; i < height; ++i) {
}
break;
#endif /* CONFIG_BMP_16BPP */
- #endif /* CONFIG_BMP_24BMP */
+#if defined(CONFIG_BMP_24BMP)
+ case 24:
+ for (i = 0; i < height; ++i) {
+ for (j = 0; j < width; j++) {
+ *(fb++) = *(bmap++);
+ *(fb++) = *(bmap++);
+ *(fb++) = *(bmap++);
+ *(fb++) = 0;
+ }
+ fb -= lcd_line_length + width * (bpix / 8);
+ }
+ break;
++#endif /* CONFIG_BMP_24BPP */
+#if defined(CONFIG_BMP_32BPP)
case 32:
for (i = 0; i < height; ++i) {
+ WATCHDOG_RESET();
for (j = 0; j < width; j++) {
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
+ fb[3] = *bmap++; /* T */
+ fb[0] = *bmap++; /* B */
+ fb[1] = *bmap++; /* G */
+ fb[2] = *bmap++; /* R */
+ fb += 4;
}
+ bmap += (padded_width - width) * 4;
fb -= lcd_line_length + width * (bpix / 8);
}
break;
- default:
- break;
+#endif /* CONFIG_BMP_32BPP */
};
- lcd_sync();
return 0;
}
#endif
#include <asm/io.h>
#include <nand.h>
- void spl_nand_load_image(void)
+#if defined(CONFIG_SPL_NAND_RAW_ONLY)
- nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
++int spl_nand_load_image(void)
+{
++ int ret;
++
+ nand_init();
+
- spl_set_header_raw_uboot();
++ ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
- void spl_nand_load_image(void)
+ nand_deselect();
++ if (ret)
++ return ret;
++
++ spl_set_header_raw_uboot();
++ return 0;
+}
+#else
+ int spl_nand_load_image(void)
{
+ int ret;
struct image_header *header;
int *src __attribute__((unused));
int *dst __attribute__((unused));
#endif
#endif
/* Load u-boot */
- nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- sizeof(*header), (void *)header);
- spl_parse_image_header(header);
- nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- spl_image.size, (void *)spl_image.load_addr);
+ ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+ if (ret == 0) {
+ spl_parse_image_header(header);
+ ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ spl_image.size, (void *)spl_image.load_addr);
+ }
nand_deselect();
+ return ret;
}
+#endif
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28,SDRAM_SIZE=SZ_128M
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28,SDRAM_SIZE=SZ_128M,ENV_IS_NOWHERE
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28,SDRAM_SIZE=SZ_256M
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28,SDRAM_SIZE=SZ_256M,ENV_IS_NOWHERE
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28,SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28,SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048,ENV_IS_NOWHERE
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28_S,SDRAM_SIZE=SZ_64M
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX28_S,SDRAM_SIZE=SZ_64M,ENV_IS_NOWHERE
++CONFIG_ARM=y
++CONFIG_TARGET_TX28=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_MPU_CLK=720,SYS_DDR_CLK=400
++CONFIG_ARM=y
++CONFIG_TARGET_TX48=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_CPU_CLK=800,NR_DRAM_BANKS=1
++CONFIG_ARM=y
++CONFIG_TARGET_TX51=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_CPU_CLK=800,NR_DRAM_BANKS=2
++CONFIG_ARM=y
++CONFIG_TARGET_TX51=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=NR_DRAM_BANKS=2,SYS_SDRAM_SIZE=SZ_2G
++CONFIG_ARM=y
++CONFIG_TARGET_TX53=y
++CONFIG_TARGET_TX53_1232=y
++CONFIG_TX53_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_ENV_IS_IN_NAND=y
++CONFIG_FEC_MXC_PHYADDR=0
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=NR_DRAM_BANKS=1
++CONFIG_ARM=y
++CONFIG_TARGET_TX53=y
++CONFIG_TARGET_TX53_X030=y
++CONFIG_TX53_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_CMD_I2C=y
++CONFIG_ENV_IS_IN_NAND=y
++CONFIG_FEC_MXC_PHYADDR=0
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=NR_DRAM_BANKS=1,SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_TARGET_TX53=y
++CONFIG_TARGET_TX53_X130=y
++CONFIG_TX53_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_ENV_IS_IN_NAND=y
++CONFIG_FEC_MXC_PHYADDR=0
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=NR_DRAM_BANKS=2,SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_TARGET_TX53=y
++CONFIG_TARGET_TX53_X131=y
++CONFIG_TX53_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_ENV_IS_IN_NAND=y
++CONFIG_FEC_MXC_PHYADDR=0
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX6_REV=0x2
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_1020=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX6_REV=0x2
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_1020=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=TX6_REV=0x2
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_1020=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_10X0=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_10X0=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_10X0=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_11X0=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_11X0=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_MX6Q=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6Q_11X0=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=16
++CONFIG_ARM=y
++CONFIG_MX6S=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6S_8034=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=16
++CONFIG_ARM=y
++CONFIG_MX6S=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6S_8034=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=16
++CONFIG_ARM=y
++CONFIG_MX6S=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6S_8034=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32
++CONFIG_ARM=y
++CONFIG_MX6S=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6S_8035=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32
++CONFIG_ARM=y
++CONFIG_MX6S=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6S_8035=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32
++CONFIG_ARM=y
++CONFIG_MX6S=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6S_8035=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=32
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8011=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=32
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8011=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=32
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8011=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_NAND_BLOCKS=2048
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8012=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_NAND_BLOCKS=2048
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8012=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_NAND_BLOCKS=2048
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8012=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=MMC_BOOT_SIZE=1024
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8033=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=MMC_BOOT_SIZE=1024
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8033=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=MMC_BOOT_SIZE=1024
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_8033=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_80X0=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_80X0=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_80X0=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_81X0=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_81X0=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_SYS_EXTRA_OPTIONS=SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_81X0=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_81X0=y
++CONFIG_TX6_UBOOT=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_81X0=y
++CONFIG_TX6_UBOOT_MFG=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
--- /dev/null
++CONFIG_ARM=y
++CONFIG_MX6DL=y
++CONFIG_TARGET_TX6=y
++CONFIG_TARGET_TX6U_81X0=y
++CONFIG_TX6_UBOOT_NOENV=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_PING=y
++CONFIG_BOOTP_SUBNETMASK=y
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_DNS=y
++CONFIG_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_FSL_USDHC=y
++CONFIG_LCD=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_FEC_MXC=y
++CONFIG_IMX_WATCHDOG=y
++CONFIG_CMD_I2C=y
++CONFIG_NAND=y
++CONFIG_NAND_MXS=y
--- /dev/null
++config APBH_DMA
++ bool "Freescale MXS and i.MX6 APBH DMA support"
++ default y
++ depends on MX28 || MX6
++
++config APBH_DMA_BURST
++ bool "Enable DMA burst mode"
++ default y
++ depends on APBH_DMA
++
++config APBH_DMA_BURST8
++ bool "Use 8-beat DMA bursts"
++ default y
++ depends on APBH_DMA_BURST
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)libgpio.o
-
-COBJS-y += gpiolib.o
-
-COBJS-$(CONFIG_AM33XX_GPIO) += am33xx_gpio.o
-COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
-COBJS-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
-COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
-COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
-COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
-COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
-COBJS-$(CONFIG_MXS_GPIO) += mxs_gpio.o
-COBJS-$(CONFIG_PCA953X) += pca953x.o
-COBJS-$(CONFIG_PCA9698) += pca9698.o
-COBJS-$(CONFIG_S5P) += s5p_gpio.o
-COBJS-$(CONFIG_SANDBOX_GPIO) += sandbox.o
-COBJS-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
-COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
-COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
-COBJS-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
-COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
-COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
-COBJS-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
-COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
-COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
-COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
-COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
-COBJS-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o
-COBJS-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
-
-COBJS := $(COBJS-y)
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-all: $(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
+endif
+
- obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
++obj-$(CONFIG_AM33XX_GPIO) += am33xx_gpio.o
++obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
+obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
+obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
- obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
++obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
+obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
+obj-$(CONFIG_MARVELL_MFP) += mvmfp.o
- obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
- obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
++obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
++obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
+obj-$(CONFIG_PCA953X) += pca953x.o
+obj-$(CONFIG_PCA9698) += pca9698.o
+obj-$(CONFIG_S5P) += s5p_gpio.o
+obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
+obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
+obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
+obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
+obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
+obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
+obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
- obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
++obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
+obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
+obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
+obj-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
+obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o
- obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
++obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
+obj-$(CONFIG_TCA642X) += tca642x.o
+oby-$(CONFIG_SX151X) += sx151x.o
+obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
--- /dev/null
-#include <asm/sizes.h>
+ /*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ #include <common.h>
+ #include <errno.h>
+ #include <asm/io.h>
+ #include <asm/bitops.h>
++#include <linux/sizes.h>
+ #include <asm/arch/hardware.h>
+ #include <asm/arch/gpio.h>
+
+ struct gpio_regs {
+ unsigned int res1[0x134 / 4];
+ unsigned int oe; /* 0x134 */
+ unsigned int datain; /* 0x138 */
+ unsigned int res2[0x54 / 4];
+ unsigned int cleardataout; /* 0x190 */
+ unsigned int setdataout; /* 0x194 */
+ };
+
+ static const struct gpio_regs *gpio_base[] = {
+ (struct gpio_regs *)AM33XX_GPIO0_BASE,
+ (struct gpio_regs *)AM33XX_GPIO1_BASE,
+ (struct gpio_regs *)AM33XX_GPIO2_BASE,
+ (struct gpio_regs *)AM33XX_GPIO3_BASE,
+ };
+
+ static unsigned long gpio_map[ARRAY_SIZE(gpio_base)] __attribute__((section("data")));
+
+ #define MAX_GPIO (ARRAY_SIZE(gpio_base) * 32)
+
+ int gpio_request(unsigned gpio, const char *name)
+ {
+ if (gpio >= MAX_GPIO) {
+ printf("ERROR: Invalid GPIO: %u (GPIO%u_%u)\n", gpio,
+ gpio / 32, gpio % 32);
+ return -EINVAL;
+ }
+ if (test_and_set_bit(gpio, gpio_map))
+ return -EBUSY;
+ return 0;
+ }
+
+ int gpio_free(unsigned gpio)
+ {
+ if (gpio >= MAX_GPIO) {
+ printf("ERROR: Invalid GPIO: %u (GPIO%u_%u)\n", gpio,
+ gpio / 32, gpio % 32);
+ return -EINVAL;
+ }
+ if (test_bit(gpio, gpio_map))
+ __clear_bit(gpio, gpio_map);
+ else
+ printf("ERROR: trying to free unclaimed GPIO %u\n", gpio);
+
+ return 0;
+ }
+
+ int gpio_set_value(unsigned gpio, int val)
+ {
+ int bank = gpio / 32;
+ int mask = 1 << (gpio % 32);
+
+ if (bank >= ARRAY_SIZE(gpio_base)) {
+ printf("ERROR: Invalid GPIO: %u (GPIO%u_%u)\n", gpio,
+ gpio / 32, gpio % 32);
+ return -EINVAL;
+ }
+ if (val)
+ writel(mask, &gpio_base[bank]->setdataout);
+ else
+ writel(mask, &gpio_base[bank]->cleardataout);
+ return 0;
+ }
+
+ int gpio_get_value(unsigned gpio)
+ {
+ int bank = gpio / 32;
+ int mask = 1 << (gpio % 32);
+
+ if (bank >= ARRAY_SIZE(gpio_base)) {
+ printf("ERROR: Invalid GPIO: %u (GPIO%u_%u)\n", gpio,
+ gpio / 32, gpio % 32);
+ return -EINVAL;
+ }
+ return (readl(&gpio_base[bank]->datain) & mask) != 0;
+ }
+
+ int gpio_direction_input(unsigned gpio)
+ {
+ int bank = gpio / 32;
+ int mask = 1 << (gpio % 32);
+
+ if (bank >= ARRAY_SIZE(gpio_base)) {
+ printf("ERROR: Invalid GPIO: %u (GPIO%u_%u)\n", gpio,
+ gpio / 32, gpio % 32);
+ return -EINVAL;
+ }
+ writel(readl(&gpio_base[bank]->oe) | mask, &gpio_base[bank]->oe);
+ return 0;
+ }
+
+ int gpio_direction_output(unsigned gpio, int val)
+ {
+ int bank = gpio / 32;
+ int mask = 1 << (gpio % 32);
+
+ if (bank >= ARRAY_SIZE(gpio_base)) {
+ printf("ERROR: Invalid GPIO: %u (GPIO%u_%u)\n", gpio,
+ gpio / 32, gpio % 32);
+ return -EINVAL;
+ }
+ gpio_set_value(gpio, val);
+ writel(readl(&gpio_base[bank]->oe) & ~mask, &gpio_base[bank]->oe);
+ return 0;
+ }
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/gpio.h>
+#include <linux/ctype.h>
+
+/**
+ * gpio_to_device() - Convert global GPIO number to device, number
+ * gpio: The numeric representation of the GPIO
+ *
+ * Convert the GPIO number to an entry in the list of GPIOs
+ * or GPIO blocks registered with the GPIO controller. Returns
+ * entry on success, NULL on error.
+ */
+static int gpio_to_device(unsigned int gpio, struct udevice **devp,
+ unsigned int *offset)
+{
+ struct gpio_dev_priv *uc_priv;
+ struct udevice *dev;
+ int ret;
+
+ for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+ dev;
+ ret = uclass_next_device(&dev)) {
+ uc_priv = dev->uclass_priv;
+ if (gpio >= uc_priv->gpio_base &&
+ gpio < uc_priv->gpio_base + uc_priv->gpio_count) {
+ *devp = dev;
+ *offset = gpio - uc_priv->gpio_base;
+ return 0;
+ }
+ }
+
+ /* No such GPIO */
+ return ret ? ret : -EINVAL;
+}
+
+int gpio_lookup_name(const char *name, struct udevice **devp,
+ unsigned int *offsetp, unsigned int *gpiop)
+{
+ struct gpio_dev_priv *uc_priv = NULL;
+ struct udevice *dev;
+ ulong offset;
+ int numeric;
+ int ret;
+
+ if (devp)
+ *devp = NULL;
+ numeric = isdigit(*name) ? simple_strtoul(name, NULL, 10) : -1;
+ for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+ dev;
+ ret = uclass_next_device(&dev)) {
+ int len;
+
+ uc_priv = dev->uclass_priv;
+ if (numeric != -1) {
+ offset = numeric - uc_priv->gpio_base;
+ /* Allow GPIOs to be numbered from 0 */
+ if (offset >= 0 && offset < uc_priv->gpio_count)
+ break;
+ }
+
+ len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0;
+
+ if (!strncasecmp(name, uc_priv->bank_name, len)) {
+ if (!strict_strtoul(name + len, 10, &offset))
+ break;
+ }
+ }
+
+ if (!dev)
+ return ret ? ret : -EINVAL;
+
+ if (devp)
+ *devp = dev;
+ if (offsetp)
+ *offsetp = offset;
+ if (gpiop)
+ *gpiop = uc_priv->gpio_base + offset;
+
+ return 0;
+}
+
+/**
+ * gpio_request() - [COMPAT] Request GPIO
+ * gpio: GPIO number
+ * label: Name for the requested GPIO
+ *
+ * The label is copied and allocated so the caller does not need to keep
+ * the pointer around.
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_request(unsigned gpio, const char *label)
+{
+ struct gpio_dev_priv *uc_priv;
+ unsigned int offset;
+ struct udevice *dev;
+ char *str;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ uc_priv = dev->uclass_priv;
+ if (uc_priv->name[offset])
+ return -EBUSY;
+ str = strdup(label);
+ if (!str)
+ return -ENOMEM;
+ if (gpio_get_ops(dev)->request) {
+ ret = gpio_get_ops(dev)->request(dev, offset, label);
+ if (ret) {
+ free(str);
+ return ret;
+ }
+ }
+ uc_priv->name[offset] = str;
+
+ return 0;
+}
+
+/**
+ * gpio_requestf() - [COMPAT] Request GPIO
+ * @gpio: GPIO number
+ * @fmt: Format string for the requested GPIO
+ * @...: Arguments for the printf() format string
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_requestf(unsigned gpio, const char *fmt, ...)
+{
+ va_list args;
+ char buf[40];
+
+ va_start(args, fmt);
+ vscnprintf(buf, sizeof(buf), fmt, args);
+ va_end(args);
+ return gpio_request(gpio, buf);
+}
+
++int gpio_request_one(unsigned int gpio, enum gpio_flags flags,
++ const char *label)
++{
++ int ret;
++
++ ret = gpio_request(gpio, label);
++ if (ret)
++ return ret;
++
++ if (flags == GPIOFLAG_INPUT)
++ gpio_direction_input(gpio);
++ else if (flags == GPIOFLAG_OUTPUT_INIT_LOW)
++ gpio_direction_output(gpio, 0);
++ else if (flags == GPIOFLAG_OUTPUT_INIT_HIGH)
++ gpio_direction_output(gpio, 1);
++
++ return ret;
++}
++
++int gpio_request_array(const struct gpio *gpios, int count)
++{
++ int ret;
++ int i;
++
++ for (i = 0; i < count; i++) {
++ ret = gpio_request_one(gpios[i].gpio, gpios[i].flags,
++ gpios[i].label);
++ if (ret) {
++ printf("Failed to request GPIO%d (%u of %u): %d\n",
++ gpios[i].gpio, i, count, ret);
++ goto error;
++ }
++ }
++ return 0;
++
++error:
++ while (--i >= 0)
++ gpio_free(gpios[i].gpio);
++
++ return ret;
++}
++
+/**
+ * gpio_free() - [COMPAT] Relinquish GPIO
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_free(unsigned gpio)
+{
+ struct gpio_dev_priv *uc_priv;
+ unsigned int offset;
+ struct udevice *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ uc_priv = dev->uclass_priv;
+ if (!uc_priv->name[offset])
+ return -ENXIO;
+ if (gpio_get_ops(dev)->free) {
+ ret = gpio_get_ops(dev)->free(dev, offset);
+ if (ret)
+ return ret;
+ }
+
+ free(uc_priv->name[offset]);
+ uc_priv->name[offset] = NULL;
+
+ return 0;
+}
+
++int gpio_free_array(const struct gpio *gpios, int count)
++{
++ int ret = 0;
++ int i;
++
++ for (i = 0; i < count; i++)
++ ret |= gpio_free(gpios[i].gpio);
++
++ return ret;
++}
++
+static int check_reserved(struct udevice *dev, unsigned offset,
+ const char *func)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ if (!uc_priv->name[offset]) {
+ printf("%s: %s: error: gpio %s%d not reserved\n",
+ dev->name, func,
+ uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+/**
+ * gpio_direction_input() - [COMPAT] Set GPIO direction to input
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_direction_input(unsigned gpio)
+{
+ unsigned int offset;
+ struct udevice *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+ ret = check_reserved(dev, offset, "dir_input");
+
+ return ret ? ret : gpio_get_ops(dev)->direction_input(dev, offset);
+}
+
+/**
+ * gpio_direction_output() - [COMPAT] Set GPIO direction to output and set value
+ * gpio: GPIO number
+ * value: Logical value to be set on the GPIO pin
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_direction_output(unsigned gpio, int value)
+{
+ unsigned int offset;
+ struct udevice *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+ ret = check_reserved(dev, offset, "dir_output");
+
+ return ret ? ret :
+ gpio_get_ops(dev)->direction_output(dev, offset, value);
+}
+
+/**
+ * gpio_get_value() - [COMPAT] Sample GPIO pin and return it's value
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns the value of the GPIO pin, or negative value
+ * on error.
+ */
+int gpio_get_value(unsigned gpio)
+{
+ unsigned int offset;
+ struct udevice *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+ ret = check_reserved(dev, offset, "get_value");
+
+ return ret ? ret : gpio_get_ops(dev)->get_value(dev, offset);
+}
+
+/**
+ * gpio_set_value() - [COMPAT] Configure logical value on GPIO pin
+ * gpio: GPIO number
+ * value: Logical value to be set on the GPIO pin.
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned int offset;
+ struct udevice *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+ ret = check_reserved(dev, offset, "set_value");
+
+ return ret ? ret : gpio_get_ops(dev)->set_value(dev, offset, value);
+}
+
+const char *gpio_get_bank_info(struct udevice *dev, int *bit_count)
+{
+ struct gpio_dev_priv *priv;
+
+ /* Must be called on an active device */
+ priv = dev->uclass_priv;
+ assert(priv);
+
+ *bit_count = priv->gpio_count;
+ return priv->bank_name;
+}
+
+static const char * const gpio_function[GPIOF_COUNT] = {
+ "input",
+ "output",
+ "unused",
+ "unknown",
+ "func",
+};
+
+int get_function(struct udevice *dev, int offset, bool skip_unused,
+ const char **namep)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct dm_gpio_ops *ops = gpio_get_ops(dev);
+
+ BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
+ if (!device_active(dev))
+ return -ENODEV;
+ if (offset < 0 || offset >= uc_priv->gpio_count)
+ return -EINVAL;
+ if (namep)
+ *namep = uc_priv->name[offset];
+ if (skip_unused && !uc_priv->name[offset])
+ return GPIOF_UNUSED;
+ if (ops->get_function) {
+ int ret;
+
+ ret = ops->get_function(dev, offset);
+ if (ret < 0)
+ return ret;
+ if (ret >= ARRAY_SIZE(gpio_function))
+ return -ENODATA;
+ return ret;
+ }
+
+ return GPIOF_UNKNOWN;
+}
+
+int gpio_get_function(struct udevice *dev, int offset, const char **namep)
+{
+ return get_function(dev, offset, true, namep);
+}
+
+int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep)
+{
+ return get_function(dev, offset, false, namep);
+}
+
+int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize)
+{
+ struct dm_gpio_ops *ops = gpio_get_ops(dev);
+ struct gpio_dev_priv *priv;
+ char *str = buf;
+ int func;
+ int ret;
+ int len;
+
+ BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
+
+ *buf = 0;
+ priv = dev->uclass_priv;
+ ret = gpio_get_raw_function(dev, offset, NULL);
+ if (ret < 0)
+ return ret;
+ func = ret;
+ len = snprintf(str, buffsize, "%s%d: %s",
+ priv->bank_name ? priv->bank_name : "",
+ offset, gpio_function[func]);
+ if (func == GPIOF_INPUT || func == GPIOF_OUTPUT ||
+ func == GPIOF_UNUSED) {
+ const char *label;
+ bool used;
+
+ ret = ops->get_value(dev, offset);
+ if (ret < 0)
+ return ret;
+ used = gpio_get_function(dev, offset, &label) != GPIOF_UNUSED;
+ snprintf(str + len, buffsize - len, ": %d [%c]%s%s",
+ ret,
+ used ? 'x' : ' ',
+ used ? " " : "",
+ label ? label : "");
+ }
+
+ return 0;
+}
+
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned gpio_get_values_as_int(const int *gpio_num_array)
+{
+ int gpio;
+ unsigned bitmask = 1;
+ unsigned vector = 0;
+
+ while (bitmask &&
+ ((gpio = *gpio_num_array++) != -1)) {
+ if (gpio_get_value(gpio))
+ vector |= bitmask;
+ bitmask <<= 1;
+ }
+ return vector;
+}
+
+/* We need to renumber the GPIOs when any driver is probed/removed */
+static int gpio_renumber(struct udevice *removed_dev)
+{
+ struct gpio_dev_priv *uc_priv;
+ struct udevice *dev;
+ struct uclass *uc;
+ unsigned base;
+ int ret;
+
+ ret = uclass_get(UCLASS_GPIO, &uc);
+ if (ret)
+ return ret;
+
+ /* Ensure that we have a base for each bank */
+ base = 0;
+ uclass_foreach_dev(dev, uc) {
+ if (device_active(dev) && dev != removed_dev) {
+ uc_priv = dev->uclass_priv;
+ uc_priv->gpio_base = base;
+ base += uc_priv->gpio_count;
+ }
+ }
+
+ return 0;
+}
+
+static int gpio_post_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ uc_priv->name = calloc(uc_priv->gpio_count, sizeof(char *));
+ if (!uc_priv->name)
+ return -ENOMEM;
+
+ return gpio_renumber(NULL);
+}
+
+static int gpio_pre_remove(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ int i;
+
+ for (i = 0; i < uc_priv->gpio_count; i++) {
+ if (uc_priv->name[i])
+ free(uc_priv->name[i]);
+ }
+ free(uc_priv->name);
+
+ return gpio_renumber(dev);
+}
+
+UCLASS_DRIVER(gpio) = {
+ .id = UCLASS_GPIO,
+ .name = "gpio",
+ .post_probe = gpio_post_probe,
+ .pre_remove = gpio_pre_remove,
+ .per_device_auto_alloc_size = sizeof(struct gpio_dev_priv),
+};
--- /dev/null
- if (flags == GPIOF_INPUT)
+ #include <common.h>
+ #include <asm-generic/gpio.h>
+
+ int gpio_request_one(unsigned int gpio, enum gpio_flags flags,
+ const char *label)
+ {
+ int ret;
+
+ ret = gpio_request(gpio, label);
+ if (ret)
+ return ret;
+
- else if (flags == GPIOF_OUTPUT_INIT_LOW)
++ if (flags == GPIOFLAG_INPUT)
+ gpio_direction_input(gpio);
- else if (flags == GPIOF_OUTPUT_INIT_HIGH)
++ else if (flags == GPIOFLAG_OUTPUT_INIT_LOW)
+ gpio_direction_output(gpio, 0);
++ else if (flags == GPIOFLAG_OUTPUT_INIT_HIGH)
+ gpio_direction_output(gpio, 1);
+
+ return ret;
+ }
+
+ int gpio_request_array(const struct gpio *gpios, int count)
+ {
+ int ret;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ ret = gpio_request_one(gpios[i].gpio, gpios[i].flags,
+ gpios[i].label);
+ if (ret) {
+ printf("Failed to request GPIO%d (%u of %u): %d\n",
+ gpios[i].gpio, i, count, ret);
+ goto error;
+ }
+ }
+ return 0;
+
+ error:
+ while (--i >= 0)
+ gpio_free(gpios[i].gpio);
+
+ return ret;
+ }
+
+ int gpio_free_array(const struct gpio *gpios, int count)
+ {
+ int ret = 0;
+ int i;
+
+ for (i = 0; i < count; i++)
+ ret |= gpio_free(gpios[i].gpio);
+
+ return ret;
+ }
MXC_GPIO_DIRECTION_OUT,
};
- #define GPIO_TO_PORT(n) (n / 32)
+#define GPIO_PER_BANK 32
+
+struct mxc_gpio_plat {
+ struct gpio_regs *regs;
+};
+
+struct mxc_bank_info {
+ struct gpio_regs *regs;
+};
+
+#ifndef CONFIG_DM_GPIO
+ #define GPIO_TO_PORT(n) ((n) / 32)
/* GPIO port description */
static unsigned long gpio_ports[] = {
--- /dev/null
++menuconfig SYS_I2C
++ bool "I2C device support"
++
++if SYS_I2C
++
++config HARD_I2C
++ bool
++
++config SYS_I2C_MXC
++ bool "Freescale i.MX I2C controller"
++ select HARD_I2C
++ select I2C_QUIRK_REG if FSL_LSCH3 || LS102XA
++
++endif
--- /dev/null
++menuconfig MMC
++ bool "MMC/SD device support"
++ select CMD_MMC
++
++if MMC
++
++config GENERIC_MMC
++ bool
++
++config FSL_ESDHC
++ bool "Freescale ESDHC controller"
++ select GENERIC_MMC
++
++config FSL_USDHC
++ bool "Support USDHC"
++ depends on MX6Q
++ depends on FSL_ESDHC
++
++config SUPPORT_EMMC_BOOT
++ bool "Support boot from eMMC"
++ depends on MMC
++
++endif
{
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-
+ struct fsl_esdhc *regs = cfg->esdhc_base;
-#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
uint wml_value;
- wml_value = data->blocksize/4;
+ wml_value = data->blocksize / 4;
if (data->flags & MMC_DATA_READ) {
if (wml_value > WML_RD_WML_MAX)
if (wml_value > WML_WR_WML_MAX)
wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
- printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
- return TIMEOUT;
+ printf("The SD card is locked. Can not write to a locked card.\n");
+ return UNUSABLE_ERR;
}
+ flush_dcache_range((unsigned long)data->src,
+ (unsigned long)data->src + data->blocks * data->blocksize);
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_write32(®s->dsaddr, (u32)data->src);
+#endif
}
-#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
- if (!(data->flags & MMC_DATA_READ)) {
- if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
- printf("The SD card is locked. Can not write to a locked card.\n");
- return UNUSABLE_ERR;
- }
- esdhc_write32(®s->dsaddr, (u32)data->src);
- } else {
- esdhc_write32(®s->dsaddr, (u32)data->dest);
- }
-#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
- esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
+ esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize);
/* Calculate the timeout period for data transactions */
/*
/* Set up for a data transfer if we have one */
if (data) {
- int err;
-
err = esdhc_setup_data(mmc, data);
- if(err)
+ if (err)
return err;
}
#endif
}
- esdhc_write32(®s->irqstat, -1);
+out:
+ /* Reset CMD and DATA portions on error */
+ if (err) {
+ esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
+ SYSCTL_RSTC);
+ while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
+ ;
+
+ if (data) {
+ esdhc_write32(®s->sysctl,
+ esdhc_read32(®s->sysctl) |
+ SYSCTL_RSTD);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
+ ;
+ }
+ }
+
+ esdhc_write32(®s->irqstat, irqstat);
- return 0;
+ return err;
}
static void set_sysctl(struct mmc *mmc, uint clock)
static int esdhc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
int timeout = 1000;
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+ if (CONFIG_ESDHC_DETECT_QUIRK)
+ return 1;
+#endif
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
udelay(1000);
u32 caps, voltage_caps;
if (!cfg)
- return -1;
+ return -EINVAL;
- mmc = kzalloc(sizeof(struct mmc), GFP_KERNEL);
- if (!mmc)
- return -ENOMEM;
-
- sprintf(mmc->name, "FSL_SDHC");
- regs = cfg->esdhc_base;
+ regs = (struct fsl_esdhc *)cfg->esdhc_base;
/* First reset the eSDHC controller */
esdhc_reset(regs);
if (caps & ESDHC_HOSTCAPBLT_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->cfg.name = "FSL_SDHC";
+ cfg->cfg.ops = &esdhc_ops;
#ifdef CONFIG_SYS_SD_VOLTAGE
- mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
+ cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
#else
- mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
- if ((mmc->voltages & voltage_caps) == 0) {
+ if ((cfg->cfg.voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
- return -1;
+ return -EINVAL;
}
- mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+ cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
if (cfg->max_bus_width > 0) {
if (cfg->max_bus_width < 8)
return 0;
}
+static const struct mmc_ops mxsmmc_ops = {
+ .send_cmd = mxsmmc_send_cmd,
+ .set_ios = mxsmmc_set_ios,
+ .init = mxsmmc_init,
+};
+
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
{
-- struct mmc *mmc = NULL;
-- struct mxsmmc_priv *priv = NULL;
++ struct mmc *mmc;
++ struct mxsmmc_priv *priv;
int ret;
const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
if (!mxs_ssp_bus_id_valid(id))
return -ENODEV;
- priv = malloc(sizeof(struct mxsmmc_priv));
- mmc = calloc(sizeof(struct mmc), 1);
- if (!mmc)
- return -ENOMEM;
-
+ priv = calloc(sizeof(struct mxsmmc_priv), 1);
- if (!priv) {
- free(mmc);
+ if (!priv)
return -ENOMEM;
- }
priv->desc = mxs_dma_desc_alloc();
if (!priv->desc) {
-- free(priv);
- free(mmc);
-- return -ENOMEM;
++ ret = -ENOMEM;
++ goto free_priv;
}
ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
if (ret)
-- return ret;
++ goto free_priv;
priv->mmc_is_wp = wp;
priv->mmc_cd = cd;
* CLOCK_DIVIDE has to be an even value from 2 to 254, and
* CLOCK_RATE could be any integer from 0 to 255.
*/
- mmc->f_min = 400000;
- mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
- mmc->b_max = 0x20;
-
- mmc_register(mmc);
+ priv->cfg.f_min = 400000;
+ priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
+ priv->cfg.b_max = 0x20;
+
+ mmc = mmc_create(&priv->cfg, priv);
+ if (mmc == NULL) {
- mxs_dma_desc_free(priv->desc);
- free(priv);
- return -ENOMEM;
++ ret = -ENOMEM;
++ goto free_dma;
+ }
return 0;
++
++free_dma:
++ mxs_dma_desc_free(priv->desc);
++free_priv:
++ free(priv);
++ return ret;
}
writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}
-static int mmc_init_setup(struct mmc *mmc)
+
+static int omap_hsmmc_init_setup(struct mmc *mmc)
{
- struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv_data = mmc->priv;
+ struct hsmmc *mmc_base = priv_data->base_addr;
unsigned int reg_val;
unsigned int dsor;
ulong start;
mmc_reg_out(&mmc_base->sysctl, bit, bit);
+ /*
+ * CMD(DAT) lines reset procedures are slightly different
+ * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
+ * According to OMAP3 TRM:
+ * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
+ * returns to 0x0.
+ * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
+ * procedure steps must be as follows:
+ * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
+ * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
+ * 2. Poll the SRC(SRD) bit until it is set to 0x1.
+ * 3. Wait until the SRC (SRD) bit returns to 0x0
+ * (reset procedure is completed).
+ */
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
+ defined(CONFIG_AM33XX)
+ if (!(readl(&mmc_base->sysctl) & bit)) {
+ start = get_timer(0);
+ while (!(readl(&mmc_base->sysctl) & bit)) {
+ if (get_timer(0) - start > MAX_RETRY_MS)
+ return;
+ }
+ }
+#endif
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & bit) != 0) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for sysctl %x to clear\n",
- __func__, bit);
- return;
- }
+ if (get_timer(0) - start > MAX_RETRY_MS)
+ break;
+ }
+ if ((readl(&mmc_base->sysctl) & bit) != 0) {
+ printf("%s: timedout waiting for sysctl %x to clear\n", __func__, bit);
+ return;
}
}
-static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv_data = mmc->priv;
+ struct hsmmc *mmc_base = priv_data->base_addr;
unsigned int flags, mmc_stat;
ulong start;
return 0;
}
-static void mmc_set_ios(struct mmc *mmc)
+static void omap_hsmmc_set_ios(struct mmc *mmc)
{
- struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv_data = mmc->priv;
+ struct hsmmc *mmc_base = priv_data->base_addr;
unsigned int dsor = 0;
ulong start;
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
++ int ret;
struct mmc *mmc;
struct omap_hsmmc_data *priv_data;
- unsigned long base_addr;
+ struct mmc_config *cfg;
+ uint host_caps_val;
+
- priv_data = malloc(sizeof(*priv_data));
++ priv_data = calloc(sizeof(*priv_data), 1);
+ if (priv_data == NULL)
- return -1;
++ return -ENOMEM;
+
+ host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
+ MMC_MODE_HC;
switch (dev_index) {
case 0:
break;
#endif
default:
- priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
- return 1;
+ printf("Invalid MMC device index: %d\n", dev_index);
- return 1;
++ ret = 1;
++ goto out;
}
-
- mmc = &hsmmc_dev[dev_index];
- priv_data = &hsmmc_dev_data[dev_index];
- priv_data->base_addr = (void *)base_addr;
-
- sprintf(mmc->name, "OMAP SD/MMC");
- mmc->send_cmd = mmc_send_cmd;
- mmc->set_ios = mmc_set_ios;
- mmc->init = mmc_init_setup;
- mmc->priv = priv_data;
-
+#ifdef OMAP_HSMMC_USE_GPIO
+ /* on error gpio values are set to -1, which is what we want */
priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
- if (priv_data->cd_gpio != -1)
- mmc->getcd = omap_mmc_getcd;
-
priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
- if (priv_data->wp_gpio != -1)
- mmc->getwp = omap_mmc_getwp;
+#endif
+
+ cfg = &priv_data->cfg;
- mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
- MMC_MODE_HC) & ~host_caps_mask;
+ cfg->name = "OMAP SD/MMC";
+ cfg->ops = &omap_hsmmc_ops;
- mmc->f_min = 400000;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ cfg->host_caps = host_caps_val & ~host_caps_mask;
+
+ cfg->f_min = 400000;
if (f_max != 0)
- mmc->f_max = f_max;
+ cfg->f_max = f_max;
else {
- if (mmc->host_caps & MMC_MODE_HS) {
- if (mmc->host_caps & MMC_MODE_HS_52MHz)
- mmc->f_max = 52000000;
+ if (cfg->host_caps & MMC_MODE_HS) {
+ if (cfg->host_caps & MMC_MODE_HS_52MHz)
+ cfg->f_max = 52000000;
else
- mmc->f_max = 26000000;
+ cfg->f_max = 26000000;
} else
- mmc->f_max = 20000000;
+ cfg->f_max = 20000000;
}
- mmc->b_max = 0;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
- mmc->b_max = 1;
+ cfg->b_max = 1;
#endif
-
- mmc_register(mmc);
+ mmc = mmc_create(cfg, priv_data);
- if (mmc == NULL)
- return -1;
++ if (mmc == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
return 0;
++
++out:
++ free(priv_data);
++ return ret;
}
--- /dev/null
++menuconfig NOR_FLASH
++ bool "NOR flash support"
++
++if NOR_FLASH
++
++config CONFIG_FLASH_CFI_DRIVER
++ bool "CFI flash driver"
++
++endif
++
++config SYS_NO_FLASH
++ bool
++ default y
++ depends on !NOR_FLASH
++
++config MTD_PARTITIONS
++ bool "Support MTD partition tables"
++ depends on MTD_DEVICE
++ default y
++
+source "drivers/mtd/nand/Kconfig"
--- /dev/null
- menu "NAND Device Support"
++menuconfig NAND
++ bool "NAND Device Support"
++
++if NAND
++
++config SYS_NAND_USE_FLASH_BBT
++ bool "Use a flash based bad block table"
+
+config SYS_NAND_SELF_INIT
+ bool
+ help
+ This option, if enabled, provides more flexible and linux-like
+ NAND initialization process.
+
+if !SPL_BUILD
+
+config NAND_DENALI
+ bool "Support Denali NAND controller"
+ select SYS_NAND_SELF_INIT
+ help
+ Enable support for the Denali NAND controller.
+
+config SYS_NAND_DENALI_64BIT
+ bool "Use 64-bit variant of Denali NAND controller"
+ depends on NAND_DENALI
+ help
+ The Denali NAND controller IP has some variations in terms of
+ the bus interface. The DMA setup sequence is completely differenct
+ between 32bit / 64bit AXI bus variants.
+
+ If your Denali NAND controller is the 64-bit variant, say Y.
+ Otherwise (32 bit), say N.
+
+config NAND_DENALI_SPARE_AREA_SKIP_BYTES
+ int "Number of bytes skipped in OOB area"
+ depends on NAND_DENALI
+ range 0 63
+ help
+ This option specifies the number of bytes to skip from the beginning
+ of OOB area before last ECC sector data starts. This is potentially
+ used to preserve the bad block marker in the OOB area.
+
+endif
+
+if SPL_BUILD
+
+config SPL_NAND_DENALI
+ bool "Support Denali NAND controller for SPL"
+ help
+ This is a small implementation of the Denali NAND controller
+ for use on SPL.
+
+endif
+
- endmenu
++config NAND_MXC
++ bool "Support Freescale i.MX NAND controller"
++ select SYS_NAND_SELF_INIT if SPL
++ help
++ Enable support for the Freescale NAND controller found on
++ i.MX processors.
++
++config NAND_MXS
++ bool "Support Freescale GPMI NAND controller"
++ select SYS_NAND_SELF_INIT if SPL
++ help
++ Enable support for the Freescale GPMI NAND controller found
++ on i.MX28 and i.MX6 processors.
++
++config NAND_MXS_NO_BBM_SWAP
++ bool "disable bad block mark swapping"
++ depends on NAND_MXS && MX6
++ select SYS_NAND_USE_FLASH_BBT
++
++endif
return NULL;
}
- #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
++#define NOTALIGNED(x) (((x) & (chip->subpagesize - 1)) != 0)
+
/**
* nand_do_write_ops - [INTERN] NAND write with ECC
* @mtd: MTD device structure
* Set the number of read / write steps for one page depending on ECC
* mode.
*/
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
+ ecc->steps = mtd->writesize / ecc->size;
+ if (ecc->steps * ecc->size != mtd->writesize) {
pr_warn("Invalid ECC parameters\n");
+ pr_warn("steps=%d size=%d writesize=%d\n",
+ chip->ecc.steps, chip->ecc.size, mtd->writesize);
BUG();
}
- chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
+ ecc->total = ecc->steps * ecc->bytes;
/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
- if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
- !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
- switch (chip->ecc.steps) {
+ if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
+ switch (ecc->steps) {
case 2:
mtd->subpage_sft = 1;
break;
#include <linux/bch.h>
#include <linux/compiler.h>
#include <nand.h>
-#ifdef CONFIG_AM33XX
-#include <asm/arch/elm.h>
+#include <linux/mtd/omap_elm.h>
+
+#define BADBLOCK_MARKER_LENGTH 2
+#define SECTOR_BYTES 512
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+/* 4 bit padding to make byte aligned, 56 = 52 + 4 */
+#define BCH4_BIT_PAD 4
+
+#ifdef CONFIG_BCH
+static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
+ 0x97, 0x79, 0xe5, 0x24, 0xb5};
#endif
+static uint8_t cs_next;
+static __maybe_unused struct nand_ecclayout omap_ecclayout;
-static uint8_t cs;
-static __maybe_unused struct nand_ecclayout hw_nand_oob =
- GPMC_NAND_HW_ECC_LAYOUT;
-static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
- GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+/*
+ * Driver configurations
+ */
+struct omap_nand_info {
+ struct bch_control *control;
+ enum omap_ecc ecc_scheme;
+ int cs;
+};
+
+/* We are wasting a bit of memory but al least we are safe */
+static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
+ static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE;
+
+ #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
+ static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+ static struct nand_bbt_descr bbt_main_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 0, /* may be overwritten depending on ECC layout */
+ .len = 4,
+ .veroffs = 4, /* may be overwritten depending on ECC layout */
+ .maxblocks = 4,
+ .pattern = bbt_pattern,
+ };
+
+ static struct nand_bbt_descr bbt_mirror_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 0, /* may be overwritten depending on ECC layout */
+ .len = 4,
+ .veroffs = 4, /* may be overwritten depending on ECC layout */
+ .maxblocks = 4,
+ .pattern = mirror_pattern,
+ };
+ #endif
+
+ #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
+ #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
+
+ #define PREFETCH_ENABLEOPTIMIZEDACCESS (0x1 << 27)
+
+ #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) (((val) >> 24) & 0x7F)
+ #define GPMC_PREFETCH_STATUS_COUNT(val) ((val) & 0x00003fff)
+
+ #define CS_NUM_SHIFT 24
+ #define ENABLE_PREFETCH (0x1 << 7)
+ #define DMA_MPU_MODE 2
+
+ #define OMAP_NAND_TIMEOUT_MS 5000
+
+ #define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
+
+ #ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
+ /**
+ * gpmc_prefetch_enable - configures and starts prefetch transfer
+ * @cs: cs (chip select) number
+ * @fifo_th: fifo threshold to be used for read/ write
+ * @count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ */
+ static inline void gpmc_prefetch_enable(int cs, int fifo_th,
+ unsigned int count, int is_write)
+ {
+ writel(count, &gpmc_cfg->pref_config2);
+
+ /* Set the prefetch read / post write and enable the engine.
+ * Set which cs is has requested for.
+ */
+ uint32_t val = (cs << CS_NUM_SHIFT) |
+ PREFETCH_ENABLEOPTIMIZEDACCESS |
+ PREFETCH_FIFOTHRESHOLD(fifo_th) |
+ ENABLE_PREFETCH |
+ !!is_write;
+ writel(val, &gpmc_cfg->pref_config1);
+
+ /* Start the prefetch engine */
+ writel(0x1, &gpmc_cfg->pref_control);
+ }
+
+ /**
+ * gpmc_prefetch_reset - disables and stops the prefetch engine
+ */
+ static inline void gpmc_prefetch_reset(void)
+ {
+ /* Stop the PFPW engine */
+ writel(0x0, &gpmc_cfg->pref_control);
+
+ /* Reset/disable the PFPW engine */
+ writel(0x0, &gpmc_cfg->pref_config1);
+ }
+
+ //#define FIFO_IOADDR (nand->IO_ADDR_R)
+ #define FIFO_IOADDR PISMO1_NAND_BASE
+
+ /**
+ * read_buf_pref - read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+ static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
+ {
+ gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 0);
+ do {
+ // Get number of bytes waiting in the FIFO
+ uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
+
+ if (read_bytes == 0)
+ continue;
+ // Alignment of Destination Buffer
+ while (read_bytes && ((unsigned int)buf & 3)) {
+ *buf++ = readb(FIFO_IOADDR);
+ read_bytes--;
+ len--;
+ }
+ // Use maximum word size (32bit) inside this loop, because speed is limited by
+ // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
+ len -= read_bytes & ~3;
+ while (read_bytes >= 4) {
+ *((uint32_t*)buf) = readl(FIFO_IOADDR);
+ buf += 4;
+ read_bytes -= 4;
+ }
+ // Transfer the last (non-aligned) bytes only at the last iteration,
+ // to maintain full speed up to the end of the transfer.
+ if (read_bytes == len) {
+ while (read_bytes) {
+ *buf++ = readb(FIFO_IOADDR);
+ read_bytes--;
+ }
+ len = 0;
+ }
+ } while (len > 0);
+ gpmc_prefetch_reset();
+ }
+
+ /*
+ * write_buf_pref - write buffer to NAND controller
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+ static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len)
+ {
+ /* configure and start prefetch transfer */
+ gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 1);
+
+ while (len) {
+ // Get number of free bytes in the FIFO
+ uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
+
+ // don't write more bytes than requested
+ if (write_bytes > len)
+ write_bytes = len;
+
+ // Alignment of Source Buffer
+ while (write_bytes && ((unsigned int)buf & 3)) {
+ writeb(*buf++, FIFO_IOADDR);
+ write_bytes--;
+ len--;
+ }
+
+ // Use maximum word size (32bit) inside this loop, because speed is limited by
+ // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
+ len -= write_bytes & ~3;
+ while (write_bytes >= 4) {
+ writel(*((uint32_t*)buf), FIFO_IOADDR);
+ buf += 4;
+ write_bytes -= 4;
+ }
+
+ // Transfer the last (non-aligned) bytes only at the last iteration,
+ // to maintain full speed up to the end of the transfer.
+ if (write_bytes == len) {
+ while (write_bytes) {
+ writeb(*buf++, FIFO_IOADDR);
+ write_bytes--;
+ }
+ len = 0;
+ }
+ }
+
+ /* wait for data to be flushed out before resetting the prefetch */
+ while ((len = GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status)))) {
+ debug("%u bytes still in FIFO\n", PREFETCH_FIFOTHRESHOLD_MAX - len);
+ ndelay(1);
+ }
+
+ /* disable and stop the PFPW engine */
+ gpmc_prefetch_reset();
+ }
+ #endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */
+
/*
* omap_nand_hwcontrol - Set the address pointers corretly for the
* following address/data/command operation
writeb(cmd, this->IO_ADDR_W);
}
-#ifdef CONFIG_SPL_BUILD
/* Check wait pin as dev ready indicator */
-int omap_spl_dev_ready(struct mtd_info *mtd)
+static int omap_dev_ready(struct mtd_info *mtd)
{
- return gpmc_cfg->status & (1 << 8);
+ return readl(&gpmc_cfg->status) & (1 << 8);
}
-#endif
-
-/*
- * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
- * GPMC controller
- * @mtd: MTD device structure
- *
- */
-static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
-{
- /*
- * Init ECC Control Register
- * Clear all ECC | Enable Reg1
- */
- writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
- writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
-}
/*
* gen_true_ecc - This function will generate true ECC value, which
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
-
- nand->cmd_ctrl = omap_nand_hwcontrol;
- nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_SUBPAGE_WRITE;
- /* If we are 16 bit dev, our gpmc config tells us that */
- if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
- nand->options |= NAND_BUSWIDTH_16;
-
+ omap_nand_info[cs].control = NULL;
+ omap_nand_info[cs].cs = cs;
+ nand->priv = &omap_nand_info[cs];
+ nand->cmd_ctrl = omap_nand_hwcontrol;
+ nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
nand->chip_delay = 100;
+ nand->ecc.layout = &omap_ecclayout;
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
-#ifdef CONFIG_AM33XX
- /* AM33xx uses the ELM */
- /* required in case of BCH */
- elm_init();
-#else
- /*
- * Whereas other OMAP based SoC do not have the ELM, they use the BCH
- * SW library.
- */
- bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
- if (!bch_priv.control) {
- printf("Failed to initialize BCH engine\n");
- return -ENODEV;
- }
-#endif
- /* BCH info that will be correct for SPL or overridden otherwise. */
- nand->priv = &bch_priv;
-#endif
-
- /* Default ECC mode */
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_bch8_nand_oob;
-#ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE * 4;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES * 4;
+ /* configure driver and controller based on NAND device bus-width */
+ gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
+#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
+ nand->options |= NAND_BUSWIDTH_16;
+ writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
#else
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
-#endif
- nand->ecc.strength = 8;
- nand->ecc.hwctl = omap_enable_ecc_bch;
- nand->ecc.correct = omap_correct_data_bch;
- nand->ecc.calculate = omap_calculate_ecc_bch;
-#ifdef CONFIG_AM33XX
- nand->ecc.read_page = omap_read_page_bch;
+ nand->options &= ~NAND_BUSWIDTH_16;
+ writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
#endif
- omap_hwecc_init_bch(nand, NAND_ECC_READ);
+ /* select ECC scheme */
+#if defined(CONFIG_NAND_OMAP_ECCSCHEME)
+ err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
+ CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
#else
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
- nand->ecc.mode = NAND_ECC_SOFT;
-#else
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_nand_oob;
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
- nand->ecc.hwctl = omap_enable_hwecc;
- nand->ecc.correct = omap_correct_data;
- nand->ecc.calculate = omap_calculate_ecc;
- nand->ecc.strength = 1;
- omap_hwecc_init(nand);
-#endif
+ /* pagesize and oobsize are not required to configure sw ecc-scheme */
+ err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ 0, 0);
#endif
+ if (err)
+ return err;
+ #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ if (nand->ecc.layout) {
+ bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
+ bbt_main_descr.veroffs = bbt_main_descr.offs +
+ sizeof(bbt_pattern);
+
+ bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
+ bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
+ sizeof(mirror_pattern);
+ }
+
+ nand->bbt_options |= NAND_BBT_USE_FLASH;
+ nand->bbt_td = &bbt_main_descr;
+ nand->bbt_md = &bbt_mirror_descr;
+ #endif
#ifdef CONFIG_SPL_BUILD
if (nand->options & NAND_BUSWIDTH_16)
--- /dev/null
++menuconfig NETDEVICES
++ bool "Network device support"
++ depends on NET
++
++if NETDEVICES
++
++config MII
++ bool
++
++config FEC_MXC
++ bool "Freescale FEC ethernet controller"
++ select MII
++
++config GET_FEC_MAC_ADDR_FROM_IIM
++ bool "Read FEC MAC address from fuses"
++ depends on FEC_MXC
++
++if FEC_MXC
++
++config FEC_MXC_MULTI
++ bool "Support multiple ethernet interfaces"
++ depends on MX28 || MX6
++
++config FEC_MXC_PHYADDR
++ int "FEC Ethernet PHY address"
++ default 0
++ depends on !FEC_MXC_MULTI
++
++endif
++
++source "drivers/net/phy/Kconfig"
++
++endif
#define CPDMA_RXCP_VER1 0x160
#define CPDMA_RXCP_VER2 0x260
-#define CPDMA_RAM_ADDR 0x4a102000
-
+ #define DMACONTROL_CMD_IDLE BIT(3)
+
+ #define DMASTATUS_IDLE BIT(31)
+
/* Descriptor mode bits */
#define CPDMA_DESC_SOP BIT(31)
#define CPDMA_DESC_EOP BIT(30)
#define chan_read(chan, fld) __raw_readl((chan)->fld)
#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
+#define for_active_slave(slave, priv) \
+ slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
#define for_each_slave(slave, priv) \
for (slave = (priv)->slaves; slave != (priv)->slaves + \
- (priv)->data.slaves; slave++)
+ (priv)->data->slaves; slave++)
struct cpsw_priv {
struct eth_device *dev;
static void cpsw_slave_update_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, int *link)
{
- struct phy_device *phy = priv->phydev;
+ struct phy_device *phy;
u32 mac_control = 0;
-
- phy = priv->phydev;
-
- if (!phy)
- return;
-
- phy_startup(phy);
- *link = phy->link;
-
- if (*link) { /* link up */
- mac_control = priv->data.mac_control;
- if (phy->speed == 1000)
- mac_control |= GIGABITEN;
- if (phy->duplex == DUPLEX_FULL)
- mac_control |= FULLDUPLEXEN;
- if (phy->speed == 100)
- mac_control |= MIIEN;
- }
+ int retries = NUM_TRIES;
+
+ do {
+ phy_startup(phy);
+ *link = phy->link;
+
+ if (*link) { /* link up */
+ mac_control = priv->data->mac_control;
+ if (phy->speed == 1000)
+ mac_control |= GIGABITEN;
+ if (phy->duplex == DUPLEX_FULL)
+ mac_control |= FULLDUPLEXEN;
+ if (phy->speed == 100)
+ mac_control |= MIIEN;
+ } else {
+ udelay(10000);
+ }
+ } while (!*link && retries-- > 0);
+ debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
+ slave->mac_control, mac_control, NUM_TRIES - retries);
if (mac_control == slave->mac_control)
return;
cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
- priv->phy_mask |= 1 << slave->data->phy_id;
+ priv->phy_mask |= 1 << slave->data->phy_addr;
}
- static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
+ static void cpdma_desc_get(struct cpsw_desc *desc)
+ {
+ invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
+ }
+
+ static void cpdma_desc_put(struct cpsw_desc *desc)
+ {
+ flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
+ }
+
+ static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
{
- struct cpdma_desc *desc = priv->desc_free;
+ struct cpsw_desc *desc = priv->desc_free;
- if (desc)
- priv->desc_free = desc_read_ptr(desc, hw_next);
+ if (desc) {
+ cpdma_desc_get(desc);
+ priv->desc_free = desc->next;
+ }
return desc;
}
static int cpsw_send(struct eth_device *dev, void *packet, int length)
{
- struct cpsw_priv *priv = dev->priv;
+ struct cpsw_priv *priv = dev->priv;
void *buffer;
int len;
- int timeout = CPDMA_TIMEOUT;
- flush_dcache_range((unsigned long)packet,
- (unsigned long)packet + length);
- if (!priv->data->mac_control && !cpsw_check_link(priv)) {
- printf("%s: Cannot send packet; link is down\n", __func__);
- return -EIO;
- }
/* first reap completed packets */
- while (timeout-- &&
- (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
- ;
-
- if (timeout == -1) {
- printf("cpdma_process timeout\n");
- return -ETIMEDOUT;
- }
+ while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
+ /* NOP */;
return cpdma_submit(priv, &priv->tx_chan, packet, length);
}
{
struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
struct phy_device *phydev;
- u32 supported = (SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_1000baseT_Full);
+ u32 supported = PHY_GBIT_FEATURES;
- phydev = phy_connect(priv->bus,
- slave->data->phy_addr,
- dev,
- slave->data->phy_if);
+ if (slave->data->phy_id < 0) {
+ u32 phy_addr;
+
+ for (phy_addr = 0; phy_addr < 32; phy_addr++) {
+ debug("Trying to connect to PHY @ addr %02x\n",
+ phy_addr);
+ phydev = phy_connect(priv->bus, phy_addr,
+ dev, slave->data->phy_if);
+ if (phydev)
+ break;
+ }
+ } else {
+ phydev = phy_connect(priv->bus,
+ slave->data->phy_id,
+ dev,
+ slave->data->phy_if);
+ }
+ if (!phydev) {
+ printf("Failed to connect to PHY\n");
+ return -EINVAL;
+ }
+ if (!phydev)
+ return -1;
+
phydev->supported &= supported;
phydev->advertising = phydev->supported;
priv->host_port_regs = regs + data->host_port_reg_ofs;
priv->dma_regs = regs + data->cpdma_reg_ofs;
priv->ale_regs = regs + data->ale_reg_ofs;
+ priv->descs = (void *)regs + data->bd_ram_ofs;
- int idx = 0;
-
for_each_slave(slave, priv) {
cpsw_slave_setup(slave, idx, priv);
idx = idx + 1;
cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
priv->bus = miiphy_get_dev_by_name(dev->name);
- for_active_slave(slave, priv)
- cpsw_phy_init(dev, slave);
-
- return 1;
- for_each_slave(slave, priv) {
++ for_active_slave(slave, priv) {
+ ret = cpsw_phy_init(dev, slave);
+ if (ret < 0)
+ break;
+ }
+ return ret;
}
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <miiphy.h>
- #include "fec_mxc.h"
+ #include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
static int fec_init(struct eth_device *dev, bd_t* bd)
{
- struct fec_priv *fec = (struct fec_priv *)dev->priv;
- uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
+ struct fec_priv *fec = dev->priv;
+ uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop;
- uint32_t size;
- int i, ret;
+ int i;
/* Initialize MAC address */
fec_set_hwaddr(dev);
goto err2;
}
- memset(edev, 0, sizeof(*edev));
- memset(fec, 0, sizeof(*fec));
-
+ ret = fec_alloc_descs(fec);
+ if (ret)
+ goto err3;
+
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
eth_register(edev);
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
- debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
+ if (dev_id < 0)
+ debug("got MAC address from fuse: %pM\n", ethaddr);
+ else
+ debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
+ if (!getenv("ethaddr"))
+ eth_setenv_enetaddr("ethaddr", ethaddr);
}
return ret;
+err4:
+ fec_free_descs(fec);
err3:
free(fec);
err2:
--- /dev/null
--- /dev/null
++config PHYLIB
++ bool "Generic PHY support"
++
++config PHY_SMSC
++ bool "SMSC PHY support"
/* Setup standard advertisement */
oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
--
if (adv < 0)
return adv;
if (phydev->supported & (SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full)) {
oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
--
if (adv < 0)
return adv;
int ctl;
ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
--
if (ctl < 0)
return ctl;
{
int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
+ if (mii_reg < 0)
+ return mii_reg;
+
/* We're using autonegotiation */
- if (mii_reg & BMSR_ANEGCAPABLE) {
+ if (phydev->supported & SUPPORTED_Autoneg) {
+ int ret;
- u16 lpa;
- u16 gblpa = 0;
- int estatus = 0;
+ u32 lpa = 0;
- int gblpa = 0;
++ u32 gblpa = 0;
+ u32 estatus = 0;
/* Check for gigabit capability */
- if (mii_reg & BMSR_ERCAP) {
+ if (phydev->supported & (SUPPORTED_1000baseT_Full |
+ SUPPORTED_1000baseT_Half)) {
/* We want a list of states supported by
* both PHYs in the link
*/
- gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
- if (gblpa < 0) {
+ ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
- if (ret < 0)
- return ret;
++ if (ret < 0) {
+ debug("Could not read MII_STAT1000. Ignoring gigabit capability\n");
- gblpa = 0;
++ ret = 0;
+ }
- gblpa &= phy_read(phydev,
- MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
+ gblpa = ret;
+
+ ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
+ if (ret < 0)
+ return ret;
+ gblpa &= ret << 2;
}
/* Set the baseline so we only have to set them
/* Do we support autonegotiation? */
val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
--
if (val < 0)
return val;
* Copyright (c) 2006 Herbert Valerio Riedel <hvr@gnu.org>
*/
#include <miiphy.h>
+ #include <errno.h>
+
+ #define MII_LAN83C185_CTRL_STATUS 17 /* Mode/Status Register */
+ #define MII_LAN83C185_EDPWRDOWN (1 << 13) /* EDPWRDOWN */
+ #define MII_LAN83C185_ENERGYON (1 << 1) /* ENERGYON */
+/* This code does not check the partner abilities. */
static int smsc_parse_status(struct phy_device *phydev)
{
- int mii_reg;
+ int bmcr;
+ int aneg_exp;
+ int mii_adv;
+ int lpa;
+
+ aneg_exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION);
+ if (aneg_exp < 0)
+ return aneg_exp;
+
+ if (aneg_exp & EXPANSION_MFAULTS) {
+ /* second read to clear latched status */
+ aneg_exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION);
+ if (aneg_exp & EXPANSION_MFAULTS)
+ return -EIO;
+ }
- mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
+ bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+ if (bmcr & BMCR_ANENABLE) {
+ lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+ mii_adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
+ if (mii_adv < 0)
+ return mii_adv;
+ lpa &= mii_adv;
- if (mii_reg & (BMSR_100FULL | BMSR_100HALF))
- phydev->speed = SPEED_100;
- else
- phydev->speed = SPEED_10;
+ if (!(aneg_exp & EXPANSION_NWAY)) {
+ /* parallel detection */
+ phydev->duplex = DUPLEX_HALF;
+ if (lpa & (LPA_100HALF | LPA_100FULL))
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+ }
- if (mii_reg & (BMSR_10FULL | BMSR_100FULL))
- phydev->duplex = DUPLEX_FULL;
- else
- phydev->duplex = DUPLEX_HALF;
+ if (lpa & (LPA_100FULL | LPA_100HALF)) {
+ phydev->speed = SPEED_100;
+ if (lpa & LPA_100FULL)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ } else if (lpa & (LPA_10FULL | LPA_10HALF)) {
+ phydev->speed = SPEED_10;
+ if (lpa & LPA_10FULL)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ } else {
+ return -EINVAL;
+ }
+ } else {
+ if (bmcr & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ }
return 0;
}
.name = "SMSC LAN8710/LAN8720",
.uid = 0x0007c0f0,
.mask = 0xffff0,
- .features = PHY_GBIT_FEATURES,
+ .features = PHY_BASIC_FEATURES,
- .config = &genphy_config_aneg,
- .startup = &genphy_startup,
+ .config = &smsc_config,
+ .startup = &smsc_startup,
.shutdown = &genphy_shutdown,
};
#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
--#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
--#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
--#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
--#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
++#define ANADIG_USB_PLL_480_CTRL_BYPASS 0x00010000
++#define ANADIG_USB_PLL_480_CTRL_ENABLE 0x00002000
++#define ANADIG_USB_PLL_480_CTRL_POWER 0x00001000
++#define ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS 0x00000040
#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
*/
__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
- &anatop->usb2_chrg_detect);
+ chrg_detect);
-- __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
- &anatop->usb2_pll_480_ctrl_clr);
++ __raw_writel(ANADIG_USB_PLL_480_CTRL_BYPASS,
+ pll_480_ctrl_clr);
-- __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
-- ANADIG_USB2_PLL_480_CTRL_POWER |
-- ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
- &anatop->usb2_pll_480_ctrl_set);
++ __raw_writel(ANADIG_USB_PLL_480_CTRL_ENABLE |
++ ANADIG_USB_PLL_480_CTRL_POWER |
++ ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS,
+ pll_480_ctrl_set);
}
-static int usbh1_phy_enable(void)
+/* Return 0 : host node, <>0 : device mode */
+static int usb_phy_enable(int index, struct usb_ehci *ehci)
{
- void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
- void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
- void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
- USB_H1REGS_OFFSET +
- UH1_USBCMD_OFFSET);
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ void __iomem *usb_cmd;
u32 val;
+ if (index >= ARRAY_SIZE(phy_bases))
+ return 0;
+
+ phy_reg = (void __iomem *)phy_bases[index];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+ usb_cmd = (void __iomem *)&ehci->usbcmd;
+
/* Stop then Reset */
val = __raw_readl(usb_cmd);
val &= ~UCMD_RUN_STOP;
/* IPU_PIX_FMT_LVDS666 */
ipu_dc_map_clear(4);
ipu_dc_map_config(4, 0, 5, 0xFC);
- ipu_dc_map_config(4, 1, 13, 0xFC);
- ipu_dc_map_config(4, 2, 21, 0xFC);
+ ipu_dc_map_config(4, 1, 11, 0xFC);
+ ipu_dc_map_config(4, 2, 17, 0xFC);
}
-int ipu_pixfmt_to_map(uint32_t fmt)
+static int ipu_pixfmt_to_map(uint32_t fmt)
{
switch (fmt) {
case IPU_PIX_FMT_GENERIC:
return 4;
}
- return -1;
+ return -EINVAL;
}
-/*
- * This function is called to adapt synchronous LCD panel to IPU restriction.
- */
-void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
- uint16_t width, uint16_t height,
- uint16_t h_start_width,
- uint16_t h_end_width,
- uint16_t v_start_width,
- uint16_t *v_end_width)
-{
- if (*v_end_width < 2) {
- uint16_t total_width = width + h_start_width + h_end_width;
- uint16_t total_height_old = height + v_start_width +
- (*v_end_width);
- uint16_t total_height_new = height + v_start_width + 2;
- *v_end_width = 2;
- *pixel_clk = (*pixel_clk) * total_width * total_height_new /
- (total_width * total_height_old);
- printf("WARNING: adapt panel end blank lines\n");
- }
-}
-
/*
* This function is called to initialize a synchronous LCD panel.
*
v_total = height + v_sync_width + v_start_width + v_end_width;
/* Init clocking */
- debug("pixel clk = %d\n", pixel_clk);
+ debug("pixel clk = %dHz\n", pixel_clk);
if (sig.ext_clk) {
- if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/
+ if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */
/*
* Set the PLL to be an even multiple
* of the pixel clock.
if (sig.Vsync_pol)
di_gen |= DI_GEN_POLARITY_3;
- if (sig.clk_pol)
+ if (!sig.clk_pol)
di_gen |= DI_GEN_POL_CLK;
+ /* Set the clock to stop at counter 6. */
+ di_gen |= 0x6000000;
}
__raw_writel(di_gen, DI_GENERAL(disp));
#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
+ #define IPU_PM (&IPU_CM_REG->pm)
#define IPU_GPR (&IPU_CM_REG->gpr)
- #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
+ #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[(ch) / 32])
- #define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
+ #define IPU_STAT ((struct ipu_stat *)(IPU_DISP_REG_BASE_ADDR + \
IPU_STAT_REG_BASE))
- #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
- #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
- #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
+#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1])
+ #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[(ch) / 32])
+ #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[(ch) / 32])
+ #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[(ch) / 32])
+#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32))
+#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))
#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
* SPDX-License-Identifier: GPL-2.0+
*/
+ /* #define DEBUG */
#include <common.h>
#include <asm/errno.h>
+#include <asm/global_data.h>
#include <linux/string.h>
#include <linux/list.h>
#include <linux/fb.h>
fbi->fix.smem_len = fbi->var.yres_virtual *
fbi->fix.line_length;
}
- fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
- fbi->fix.smem_len);
- fbi->fix.smem_start = (unsigned long)fbi->screen_base;
- if (fbi->screen_base == 0) {
++
+ fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
- fbi->screen_base = malloc(fbi->fix.smem_len);
+ if (gd->fb_base)
+ fbi->screen_base = (void *)gd->fb_base;
+ else
++ fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
++ fbi->fix.smem_len);
+ if (fbi->screen_base == NULL) {
puts("Unable to allocate framebuffer memory\n");
fbi->fix.smem_len = 0;
- fbi->fix.smem_start = 0;
return -EBUSY;
}
+ fbi->fix.smem_start = (unsigned long)fbi->screen_base;
debug("allocated fb @ paddr=0x%08X, size=%d.\n",
(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
fbi->screen_size = fbi->fix.smem_len;
- /* Clear the screen */
- memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
-
+ gd->fb_base = fbi->fix.smem_start;
+
return 0;
}
#define PS2KHZ(ps) (1000000000UL / (ps))
+ DECLARE_GLOBAL_DATA_PTR;
+
static GraphicDevice panel;
+struct mxs_dma_desc desc;
+
+/**
+ * mxsfb_system_setup() - Fine-tune LCDIF configuration
+ *
+ * This function is used to adjust the LCDIF configuration. This is usually
+ * needed when driving the controller in System-Mode to operate an 8080 or
+ * 6800 connected SmartLCD.
+ */
+__weak void mxsfb_system_setup(void)
+{
+}
/*
* DENX M28EVK:
--- /dev/null
++config HW_WATCHDOG
++ bool "Generic SoC specific watchdog support"
++ depends on !MX6
++
++config IMX_WATCHDOG
++ bool "Freescale i.MX watchdog support"
++ depends on MX31 || MX35 || MX5 || MX6 || VF610 || LS102XA
# SPDX-License-Identifier: GPL-2.0+
#
- obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
- obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
- ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
- obj-y += imx_watchdog.o
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)libwatchdog.o
-
-COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
-COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
-COBJS-y += imx_watchdog.o
--endif
- obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
- obj-$(CONFIG_S5P) += s5p_wdt.o
- obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
- obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
- obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
- obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
-COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
-COBJS-$(CONFIG_S5P) += s5p_wdt.o
-COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
-COBJS-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
-
-COBJS := $(COBJS-y)
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-all: $(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
++obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
++obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
++obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
++obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
++obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o
++obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
++obj-$(CONFIG_S5P) += s5p_wdt.o
++obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
++obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
--- /dev/null
+#
+# Device Tree Control
+#
+# TODO:
+# This feature is not currently supported for SPL,
+# but this restriction should be removed in the future.
+
+config SUPPORT_OF_CONTROL
+ bool
+
+menu "Device Tree Control"
+ depends on !SPL_BUILD
+ depends on SUPPORT_OF_CONTROL
+
+config OF_CONTROL
+ bool "Run-time configuration via Device Tree"
+ help
+ This feature provides for run-time configuration of U-Boot
+ via a flattened device tree.
+
+choice
+ prompt "Provider of DTB for DT control"
+ depends on OF_CONTROL
+
+config OF_SEPARATE
+ bool "Separate DTB for DT control"
+ depends on !SANDBOX
+ help
+ If this option is enabled, the device tree will be built and
+ placed as a separate u-boot.dtb file alongside the U-Boot image.
+
+config OF_EMBED
+ bool "Embedded DTB for DT control"
+ help
+ If this option is enabled, the device tree will be picked up and
+ built into the U-Boot image.
+
+config OF_HOSTFILE
+ bool "Host filed DTB for DT control"
+ depends on SANDBOX
+ help
+ If this option is enabled, DTB will be read from a file on startup.
+ This is only useful for Sandbox. Use the -d flag to U-Boot to
+ specify the file to read.
+
+endchoice
+
+config DEFAULT_DEVICE_TREE
+ string "Default Device Tree for DT control"
+ help
+ This option specifies the default Device Tree used for DT control.
+ It can be overridden from the command line:
+ $ make DEVICE_TREE=<device-tree-name>
+
++config FDT_FIXUP_PARTITIONS
++ bool
++ depends on MTD_PARTITIONS && OF_LIBFDT
++
+endmenu
* an error value of -1.
*/
- GPIOF_INPUT,
- GPIOF_OUTPUT_INIT_LOW,
- GPIOF_OUTPUT_INIT_HIGH,
+ enum gpio_flags {
++ GPIOFLAG_INPUT,
++ GPIOFLAG_OUTPUT_INIT_LOW,
++ GPIOFLAG_OUTPUT_INIT_HIGH,
+ };
+
+ struct gpio {
+ unsigned int gpio;
+ enum gpio_flags flags;
+ const char *label;
+ };
+
/**
- * Request a gpio. This should be called before any of the other functions
- * are used on this gpio.
+ * Request a GPIO. This should be called before any of the other functions
+ * are used on this GPIO.
+ *
+ * Note: With driver model, the label is allocated so there is no need for
+ * the caller to preserve it.
*
* @param gp GPIO number
* @param label User label for this GPIO
*/
int gpio_request(unsigned gpio, const char *label);
++/**
++ * Request a GPIO and configure it
++ * @param gpios pointer to array of gpio defs
++ * @param count number of GPIOs to set up
++ */
++int gpio_request_one(unsigned gpio, enum gpio_flags flags, const char *label);
++
++/**
++ * Request a set of GPIOs and configure them
++ * @param gpios pointer to array of gpio defs
++ * @param count number of GPIOs to set up
++ */
++int gpio_request_array(const struct gpio *gpios, int count);
++
/**
* Stop using the GPIO. This function should not alter pin configuration.
*
*/
int gpio_free(unsigned gpio);
++/**
++ * Release a set of GPIOs
++ * @param gpios pointer to array of gpio defs
++ * @param count number of GPIOs to set up
++ */
++int gpio_free_array(const struct gpio *gpios, int count);
++
/**
* Make a GPIO an input.
*
* Flash & Environment
*/
/* No NOR flash present */
--#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
/* NAND */
--#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (0xBB000000)
/* U-Boot commands */
#include <config_cmd_default.h>
--#define CONFIG_CMD_NAND
--#define CONFIG_CMD_CACHE
/*
* Ethernet
*/
--#define CONFIG_FEC_MXC
--#define CONFIG_FEC_MXC_PHYADDR 0x1f
--#define CONFIG_MII
--#define CONFIG_CMD_NET
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ENV_OVERWRITE
--- /dev/null
-#include <asm/sizes.h>
+ /*
+ * Copyright (C) 2012 <LW@KARO-electronics.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+
+ #define CONFIG_MX28 /* must be defined before including regs-base.h */
+
-#define LCD_BPP LCD_COLOR24
++#include <linux/sizes.h>
+ #include <asm/arch/regs-base.h>
+
+ /*
+ * Ka-Ro TX28 board - SoC configuration
+ */
+ #define CONFIG_MXS_GPIO /* GPIO control */
+ #define CONFIG_SYS_HZ 1000 /* Ticks per second */
+ #define PHYS_SDRAM_1_SIZE CONFIG_SDRAM_SIZE
+ #ifdef CONFIG_TX28_S
+ #define TX28_MOD_SUFFIX "1"
+ #else
+ #define CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
+ #define TX28_MOD_SUFFIX "0"
+ #endif
+ #define IRAM_BASE_ADDR 0x00000000
+
+ #ifndef CONFIG_SPL_BUILD
+ #define CONFIG_SKIP_LOWLEVEL_INIT
+ #define CONFIG_SHOW_ACTIVITY
+ #define CONFIG_ARCH_CPU_INIT
+ #define CONFIG_ARCH_MISC_INIT /* init vector table after relocation */
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+ #define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_BOARD_EARLY_INIT_F
+
+ /* LCD Logo and Splash screen support */
+ #define CONFIG_LCD
+ #ifdef CONFIG_LCD
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_SPLASH_SCREEN_ALIGN
+ #define CONFIG_VIDEO_MXS
+ #define CONFIG_LCD_LOGO
-#define CONFIG_SYS_NO_FLASH
++#define LCD_BPP LCD_COLOR32
+ #define CONFIG_CMD_BMP
+ #define CONFIG_VIDEO_BMP_RLE8
+ #endif /* CONFIG_LCD */
+ #endif /* CONFIG_SPL_BUILD */
+
+ /*
+ * Memory configuration options
+ */
+ #define CONFIG_NR_DRAM_BANKS 0x1 /* 1 bank of SDRAM */
+ #define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
+ #define CONFIG_STACKSIZE SZ_64K
+ #define CONFIG_SYS_MALLOC_LEN SZ_4M
+ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
+
+ /*
+ * U-Boot general configurations
+ */
+ #define CONFIG_SYS_LONGHELP
+ #define CONFIG_SYS_PROMPT "TX28 U-Boot > "
+ #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+ #define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+ #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
+ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+ #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+ #define CONFIG_AUTO_COMPLETE /* Command auto complete */
+ #define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+ #define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_OF_LIBFDT
+
+ /*
+ * Flattened Device Tree (FDT) support
+ */
-#define CONFIG_FDT_FIXUP_PARTITIONS
-#define CONFIG_OF_BOARD_SETUP
+ #ifdef CONFIG_OF_LIBFDT
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_BOOTCE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_MEMTEST
+ #endif
+
+ /*
+ * Boot Linux
+ */
+ #define xstr(s) str(s)
+ #define str(s) #s
+ #define __pfx(x, s) (x##s)
+ #define _pfx(x, s) __pfx(x, s)
+
+ #define CONFIG_CMDLINE_TAG
+ #define CONFIG_SETUP_MEMORY_TAGS
+ #define CONFIG_BOOTDELAY 3
+ #define CONFIG_ZERO_BOOTDELAY_CHECK
+ #define CONFIG_SYS_AUTOLOAD "no"
+ #define CONFIG_BOOTFILE "uImage"
+ #define CONFIG_BOOTARGS "init=/linuxrc console=ttyAMA0,115200 ro debug panic=1"
+ #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
+ #ifdef CONFIG_TX28_S
+ #define CONFIG_LOADADDR 41000000
+ #else
+ #define CONFIG_LOADADDR 43000000
+ #endif
+ #define CONFIG_FDTADDR 41000000
+ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+ #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
+ #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+
+ /*
+ * Extra Environment Settings
+ */
+ #ifdef CONFIG_ENV_IS_NOWHERE
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "autoload=no\0" \
+ "bootdelay=-1\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0"
+ #else
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p3 rootwait\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
+ " ip=dhcp\0" \
+ "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
+ "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
+ ";nboot linux\0" \
+ "bootcmd_mmc=set autostart no;run bootargs_mmc" \
+ ";fatload mmc 0 ${loadaddr} uImage\0" \
+ "bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0"\
+ "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
+ ";dhcp\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
+ "boot_mode=nand\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " ${append_bootargs}\0" \
+ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
+ "fdtsave=fdt resize;nand erase.part dtb" \
+ ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA\0"
+ #endif /* CONFIG_ENV_IS_NOWHERE */
+
+ #define MTD_NAME "gpmi-nand"
+ #define MTDIDS_DEFAULT "nand0=" MTD_NAME
+
+ /*
+ * U-Boot Commands
+ */
+ #include <config_cmd_default.h>
-#define CONFIG_FEC_MXC
+
+ /*
+ * Serial Driver
+ */
+ #define CONFIG_PL011_SERIAL
+ #define CONFIG_PL011_CLOCK 24000000
+ #define CONFIG_PL01x_PORTS { \
+ (void *)MXS_UARTDBG_BASE, \
+ }
+ #define CONFIG_CONS_INDEX 0 /* do not change! */
+ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
+ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+ #define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+ /*
+ * Ethernet Driver
+ */
-#define CONFIG_FEC_MXC_MULTI
+ #ifdef CONFIG_FEC_MXC
+ /* This is required for the FEC driver to work with cache enabled */
+ #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+ #define CONFIG_SYS_CACHELINE_SIZE 32
+
+ #ifndef CONFIG_TX28_S
-#define CONFIG_FEC_MXC_PHYADDR 0x00
+ #else
+ #define IMX_FEC_BASE MXS_ENET0_BASE
-#define CONFIG_PHY_SMSC
-#define CONFIG_PHYLIB
-#define CONFIG_MII
+ #endif
+
-#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+ #define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
+ #define CONFIG_NET_MULTI
+ #define CONFIG_CMD_MII
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_IS_IN_MMC
+ /* Add for working with "strict" DHCP server */
+ #define CONFIG_BOOTP_SUBNETMASK
+ #define CONFIG_BOOTP_GATEWAY
+ #define CONFIG_BOOTP_DNS
+ #define CONFIG_BOOTP_RANDOM_ID
+ #endif
+
+ #ifndef CONFIG_ENV_IS_NOWHERE
+ /* define one of the following options:
-#define CONFIG_ENV_IS_IN_NAND
+ */
-#define CONFIG_MTD_DEVICE
+ #endif
+ #define CONFIG_ENV_OVERWRITE
+
+ /*
+ * NAND flash driver
+ */
+ #ifdef CONFIG_CMD_NAND
+ #define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
-#define CONFIG_CMD_NAND_TRIMFFS
+ #define CONFIG_NAND_MXS
+ #define CONFIG_APBH_DMA
+ #define CONFIG_APBH_DMA_BURST
+ #define CONFIG_APBH_DMA_BURST8
+ #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
+ #define CONFIG_SYS_MXS_DMA_CHANNEL 4
+ #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
+ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_CMD_ROMUPDATE
+ #define CONFIG_SYS_NAND_BASE 0x00000000
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
+ #else
+ #undef CONFIG_ENV_IS_IN_NAND
+ #endif /* CONFIG_CMD_NAND */
+
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
+ #define CONFIG_ENV_SIZE SZ_128K
+ #define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+ #endif /* CONFIG_ENV_IS_IN_NAND */
+
+ #ifdef CONFIG_ENV_OFFSET_REDUND
+ #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
+ "(env)," \
+ xstr(CONFIG_SYS_ENV_PART_SIZE) \
+ "(env2),"
+ #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE2) "(userfs)"
+ #else
+ #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
+ "(env),"
+ #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE) "(userfs)"
+ #endif /* CONFIG_ENV_OFFSET_REDUND */
+
+ /*
+ * MMC Driver
+ */
+ #ifdef CONFIG_CMD_MMC
+ #define CONFIG_MXS_MMC
+ #define CONFIG_BOUNCE_BUFFER
+
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_CMD_FAT
+ #define CONFIG_FAT_WRITE
+ #define CONFIG_CMD_EXT2
+
+ /*
+ * Environments on MMC
+ */
+ #ifdef CONFIG_ENV_IS_IN_MMC
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ /* Associated with the MMC layout defined in mmcops.c */
+ #define CONFIG_ENV_OFFSET SZ_1K
+ #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+ #endif /* CONFIG_ENV_IS_IN_MMC */
+ #else
+ #undef CONFIG_ENV_IS_IN_MMC
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_ENV_IS_NOWHERE
+ #undef CONFIG_ENV_SIZE
+ #define CONFIG_ENV_SIZE SZ_4K
+ #endif
+
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
+ CONFIG_SYS_ENV_PART_STR \
+ "6m(linux),32m(rootfs)," CONFIG_SYS_USERFS_PART_STR \
+ ",512k@" xstr(CONFIG_SYS_NAND_DTB_OFFSET) "(dtb)" \
+ ",512k@" xstr(CONFIG_SYS_NAND_BBT_OFFSET) "(bbt)ro"
+
+ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+ /* Defines for SPL */
+ #define CONFIG_SPL
+ #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+ #define CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define CONFIG_SPL_LIBGENERIC_SUPPORT
+ #define CONFIG_SPL_SERIAL_SUPPORT
+ #define CONFIG_SPL_GPIO_SUPPORT
+ #define CONFIG_SYS_SPL_VDDD_VAL 1500
+ #define CONFIG_SYS_SPL_BATT_BO_LEVEL 2800
+ #define CONFIG_SYS_SPL_VDDMEM_VAL 0 /* VDDMEM is not utilized on TX28 */
+
+ #endif /* __CONFIGS_TX28_H */
--- /dev/null
-#include <asm/sizes.h>
+ /*
+ * tx48.h
+ *
+ * Copyright (C) 2012-2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * based on: am335x_evm
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+
+ #define CONFIG_AM33XX /* must be set before including omap.h */
+
-#define CONFIG_VIDEO_DA8XX
++#include <linux/sizes.h>
+ #include <asm/arch/omap.h>
+
+ /*
+ * Ka-Ro TX48 board - SoC configuration
+ */
+ #define CONFIG_OMAP
+ #define CONFIG_AM33XX_GPIO
+ #define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+ #ifndef CONFIG_SPL_BUILD
+ #define CONFIG_SKIP_LOWLEVEL_INIT
+ #define CONFIG_SHOW_ACTIVITY
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+ #define CONFIG_BOARD_LATE_INIT
+
+ /* LCD Logo and Splash screen support */
+ #define CONFIG_LCD
+ #ifdef CONFIG_LCD
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_SPLASH_SCREEN_ALIGN
-#define LCD_BPP LCD_COLOR24
++#define CONFIG_AM335X_LCD
+ #define DAVINCI_LCD_CNTL_BASE 0x4830e000
+ #define CONFIG_LCD_LOGO
-#define CONFIG_SYS_NO_FLASH
++#define LCD_BPP LCD_COLOR32
+ #define CONFIG_CMD_BMP
+ #define CONFIG_VIDEO_BMP_RLE8
+ #endif /* CONFIG_LCD */
+ #endif /* CONFIG_SPL_BUILD */
+
+ /* Clock Defines */
+ #define V_OSCK 24000000 /* Clock output from T2 */
+ #define V_SCLK V_OSCK
+
+ /*
+ * Memory configuration options
+ */
+ #define CONFIG_SYS_SDRAM_DDR3
+ #define CONFIG_NR_DRAM_BANKS 0x1 /* '1' would be converted to 'y' by define2mk.sed */
+ #define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
+ #define CONFIG_MAX_RAM_BANK_SIZE SZ_1G
+
+ #define CONFIG_STACKSIZE SZ_64K
+ #define CONFIG_SYS_MALLOC_LEN SZ_4M
+
+ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_64M)
+ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_8M)
+
+ #define CONFIG_SYS_CACHELINE_SIZE 64
+
+ /*
+ * U-Boot general configurations
+ */
+ #define CONFIG_SYS_LONGHELP
+ #define CONFIG_SYS_PROMPT "TX48 U-Boot > "
+ #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+ #define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+ #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
+ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+ #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+ #define CONFIG_AUTO_COMPLETE /* Command auto complete */
+ #define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+ #define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
+
+ /*
+ * Flattened Device Tree (FDT) support
+ */
-#define CONFIG_HW_WATCHDOG
+
+ /*
+ * Boot Linux
+ */
+ #define xstr(s) str(s)
+ #define str(s) #s
+ #define __pfx(x, s) (x##s)
+ #define _pfx(x, s) __pfx(x, s)
+
+ #define CONFIG_CMDLINE_TAG
+ #define CONFIG_SETUP_MEMORY_TAGS
+ #define CONFIG_BOOTDELAY 3
+ #define CONFIG_ZERO_BOOTDELAY_CHECK
+ #define CONFIG_SYS_AUTOLOAD "no"
+ #define CONFIG_BOOTFILE "uImage"
+ #define CONFIG_BOOTARGS "init=/linuxrc console=ttyO0,115200 ro debug panic=1"
+ #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
+ #define CONFIG_LOADADDR 83000000
+ #define CONFIG_FDTADDR 81000000
+ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+ #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
+ #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
-#define CONFIG_FDT_FIXUP_PARTITIONS
+
+ /*
+ * Extra Environment Settings
+ */
+ #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK)
+
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock4 rootfstype=jffs2\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p2 rootwait\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
+ " ip=dhcp\0" \
+ "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
+ "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
+ ";nboot linux\0" \
+ "bootcmd_mmc=set autostart no;run bootargs_mmc" \
+ ";fatload mmc 0 ${loadaddr} uImage\0" \
+ "bootcmd_nand=set autostart no;run bootargs_ubifs" \
+ ";nboot linux\0" \
+ "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
+ ";dhcp\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
+ "boot_mode=nand\0" \
+ "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " ${append_bootargs}\0" \
+ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
+ "fdtsave=fdt resize;nand erase.part dtb" \
+ ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA\0"
+
+ #define MTD_NAME "omap2-nand.0"
+ #define MTDIDS_DEFAULT "nand0=" MTD_NAME
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_BOOTCE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_MEMTEST
+
+ /*
+ * U-Boot Commands
+ */
+ #include <config_cmd_default.h>
-#define CONFIG_PHY_SMSC
-#define CONFIG_PHYLIB
-#define CONFIG_MII
+
+ /*
+ * Serial Driver
+ */
+ #define CONFIG_SYS_NS16550
+ #define CONFIG_SYS_NS16550_SERIAL
+ #define CONFIG_SYS_NS16550_MEM32
+ #define CONFIG_SYS_NS16550_REG_SIZE (-4)
+ #define CONFIG_SYS_NS16550_CLK 48000000
+ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+
+ #define CONFIG_SYS_NS16550_COM3 0x481aa000 /* UART2 */
+ #define CONFIG_SYS_NS16550_COM4 0x481aa000 /* UART3 */
+ #define CONFIG_SYS_NS16550_COM5 0x481aa000 /* UART4 */
+ #define CONFIG_CONS_INDEX 1 /* one based! */
+ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
+ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+ #define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+ /*
+ * Ethernet Driver
+ */
+ #ifdef CONFIG_CMD_NET
+ #define CONFIG_DRIVER_TI_CPSW
+ #define CONFIG_NET_MULTI
+ #define CONFIG_PHY_GIGE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
+ #define CONFIG_CMD_MII
-#define CONFIG_MTD_DEVICE
-#define CONFIG_ENV_IS_IN_NAND
+ /* Add for working with "strict" DHCP server */
+ #define CONFIG_BOOTP_SUBNETMASK
+ #define CONFIG_BOOTP_GATEWAY
+ #define CONFIG_BOOTP_DNS
+ #define CONFIG_BOOTP_DNS2
+ #endif
+
+ /*
+ * NAND flash driver
+ */
+ #ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
+ #define CONFIG_NAND_OMAP_GPMC
+ #ifndef CONFIG_SPL_BUILD
+ #define CONFIG_SYS_GPMC_PREFETCH_ENABLE
+ #endif
+ #define GPMC_NAND_ECC_LP_x8_LAYOUT
+ #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL GPMC_NAND_HW_ECC_LAYOUT
+ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+ #define CONFIG_SYS_NAND_PAGE_SIZE 2048
+ #define CONFIG_SYS_NAND_OOBSIZE 64
+ #define CONFIG_SYS_NAND_ECCSIZE 512
+ #define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
+ #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
+ #define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */
+ #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
+ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_ENV_IS_IN_MMC
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ #define CONFIG_ENV_OVERWRITE
+ #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
+ #define CONFIG_ENV_SIZE SZ_128K
+ #define CONFIG_ENV_RANGE 0x60000
+ #endif /* CONFIG_ENV_IS_IN_NAND */
+ #define CONFIG_SYS_NAND_BASE 0x00100000
+ #define CONFIG_SYS_NAND_SIZE SZ_128M
+ #define NAND_BASE CONFIG_SYS_NAND_BASE
+ #endif /* CONFIG_CMD_NAND */
+
+ /*
+ * MMC Driver
+ */
+ #ifdef CONFIG_CMD_MMC
+ #ifndef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
+ #endif
+ #define CONFIG_OMAP_HSMMC
+ #define CONFIG_OMAP_MMC_DEV_1
+
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_CMD_FAT
+ #define CONFIG_FAT_WRITE
+ #define CONFIG_CMD_EXT2
+
+ /*
+ * Environments on MMC
+ */
+ #ifdef CONFIG_ENV_IS_IN_MMC
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_ENV_OVERWRITE
+ /* Associated with the MMC layout defined in mmcops.c */
+ #define CONFIG_ENV_OFFSET SZ_1K
+ #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+ #endif /* CONFIG_ENV_IS_IN_MMC */
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_ENV_OFFSET_REDUND
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "128k(u-boot-spl)," \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),6m(linux),32m(rootfs),89216k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
+ #else
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "128k(u-boot-spl)," \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),6m(linux),32m(rootfs),89600k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
+ #endif
+
+ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+ #define SRAM0_SIZE SZ_64K
+ #define OCMC_SRAM_BASE 0x40300000
+ #define CONFIG_SPL_STACK (OCMC_SRAM_BASE + 0xb800)
+ #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + SZ_32K)
+
+ /* Platform/Board specific defs */
+ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+ /* Defines for SPL */
+ #define CONFIG_SPL
+ #define CONFIG_SPL_FRAMEWORK
+ #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
+ #define CONFIG_SPL_GPIO_SUPPORT
+ #ifdef CONFIG_NAND_OMAP_GPMC
+ #define CONFIG_SPL_NAND_SUPPORT
+ #define CONFIG_SPL_NAND_DRIVERS
+ #define CONFIG_SPL_NAND_BASE
+ #define CONFIG_SPL_NAND_ECC
+ #define CONFIG_SPL_NAND_AM33XX_BCH
+ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
+ #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+ #define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
+ #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+ #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+ #endif
+
+ #define CONFIG_SPL_BSS_START_ADDR PHYS_SDRAM_1
+ #define CONFIG_SPL_BSS_MAX_SIZE SZ_512K
+
+ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+
+ #define CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define CONFIG_SPL_LIBGENERIC_SUPPORT
+ #define CONFIG_SPL_SERIAL_SUPPORT
+ #define CONFIG_SPL_YMODEM_SUPPORT
+ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+ /*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+ #define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
+ #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
+
+ #endif /* __CONFIG_H */
--- /dev/null
-#include <asm/sizes.h>
+ /*
+ * Copyright (C) 2012-2014 <LW@KARO-electronics.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+
+ #define CONFIG_MX51 /* must be set before including imx-regs.h */
+
-#define LCD_BPP LCD_COLOR24
++#include <linux/sizes.h>
+ #include <asm/arch/imx-regs.h>
+
+ /*
+ * Ka-Ro TX51 board - SoC configuration
+ */
+ #define CONFIG_SYS_MX5_IOMUX_V3
+ #define CONFIG_MXC_GPIO /* GPIO control */
+ #define CONFIG_SYS_MX5_HCLK 24000000
+ #define CONFIG_SYS_DDR_CLKSEL 0
+ #define CONFIG_SYS_HZ 1000 /* Ticks per second */
+ #define CONFIG_SHOW_ACTIVITY
+ #define CONFIG_DISPLAY_BOARDINFO
+ #define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_BOARD_EARLY_INIT_F
+
+ #if CONFIG_SYS_CPU_CLK == 600
+ #define TX51_MOD_PREFIX "6"
+ #elif CONFIG_SYS_CPU_CLK == 800
+ #define TX51_MOD_PREFIX "8"
+ #define CONFIG_MX51_PLL_ERRATA
+ #else
+ #error Invalid CPU clock
+ #endif
+
+ /* LCD Logo and Splash screen support */
+ #define CONFIG_LCD
+ #ifdef CONFIG_LCD
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_SPLASH_SCREEN_ALIGN
+ #define CONFIG_VIDEO_IPUV3
+ #define CONFIG_IPUV3_CLK 133000000
+ #define CONFIG_LCD_LOGO
-#define CONFIG_SYS_NO_FLASH
++#define LCD_BPP LCD_COLOR32
+ #define CONFIG_CMD_BMP
+ #define CONFIG_VIDEO_BMP_RLE8
+ #endif /* CONFIG_LCD */
+
+ /*
+ * Memory configuration options
+ */
+ #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
+ #define PHYS_SDRAM_1_SIZE SZ_128M
+ #if CONFIG_NR_DRAM_BANKS > 1
+ #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
+ #define PHYS_SDRAM_2_SIZE SZ_128M
+ #endif
+ #define CONFIG_STACKSIZE SZ_128K
+ #define CONFIG_SYS_MALLOC_LEN SZ_8M
+ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+ #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
+ #define CONFIG_SYS_SDRAM_CLK 166
+ #define CONFIG_SYS_CLKTL_CBCDR 0x01e35100
+
+ /*
+ * U-Boot general configurations
+ */
+ #define CONFIG_SYS_LONGHELP
+ #define CONFIG_SYS_PROMPT "TX51 U-Boot > "
+ #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+ #define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+ #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
+ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+ #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+ #define CONFIG_AUTO_COMPLETE /* Command auto complete */
+ #define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+ #define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
+
+ /*
+ * Flattened Device Tree (FDT) support
+ */
-#define CONFIG_HW_WATCHDOG
+
+ /*
+ * Boot Linux
+ */
+ #define xstr(s) str(s)
+ #define str(s) #s
+ #define __pfx(x, s) (x##s)
+ #define _pfx(x, s) __pfx(x, s)
+
+ #define CONFIG_CMDLINE_TAG
+ #define CONFIG_SETUP_MEMORY_TAGS
+ #define CONFIG_BOOTDELAY 3
+ #define CONFIG_ZERO_BOOTDELAY_CHECK
+ #define CONFIG_SYS_AUTOLOAD "no"
+ #define CONFIG_BOOTFILE "uImage"
+ #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
+ #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
+ #define CONFIG_LOADADDR 94000000
+ #define CONFIG_FDTADDR 91000000
+ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+ #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
+ #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
-#define CONFIG_FDT_FIXUP_PARTITIONS
+
+ /*
+ * Extra Environment Settings
+ */
+ #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_CPU_CLK)
+
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p2 rootwait\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
+ " ip=dhcp\0" \
+ "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
+ "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
+ ";nboot linux\0" \
+ "bootcmd_mmc=set autostart no;run bootargs_mmc" \
+ ";fatload mmc 0 ${loadaddr} uImage\0" \
+ "bootcmd_nand=set autostart no;run bootargs_ubifs" \
+ ";nboot linux\0" \
+ "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
+ ";dhcp\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
+ "boot_mode=nand\0" \
+ "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " ${append_bootargs}\0" \
+ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
+ "fdtsave=fdt resize;nand erase.part dtb" \
+ ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA\0"
+
+ #define MTD_NAME "mxc_nand"
+ #define MTDIDS_DEFAULT "nand0=" MTD_NAME
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_BOOTCE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_MEMTEST
+
+ /*
+ * U-Boot Commands
+ */
+ #include <config_cmd_default.h>
-#define CONFIG_FEC_MXC
+
+ /*
+ * Serial Driver
+ */
+ #define CONFIG_MXC_UART
+ #define CONFIG_MXC_UART_BASE UART1_BASE
+ #define CONFIG_MXC_GPIO
+ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
+ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+ #define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+ /*
+ * Ethernet Driver
+ */
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_SMSC
-#define CONFIG_MII
+ #ifdef CONFIG_FEC_MXC
+ #define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+ #define CONFIG_FEC_XCV_TYPE MII100
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
+ #define CONFIG_CMD_MII
-#define CONFIG_MTD_DEVICE
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_NAND_MXC
+ /* Add for working with "strict" DHCP server */
+ #define CONFIG_BOOTP_SUBNETMASK
+ #define CONFIG_BOOTP_GATEWAY
+ #define CONFIG_BOOTP_DNS
+ #endif
+
+ /*
+ * NAND flash driver
+ */
+ #ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
+ #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
+ #define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
+ #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
+ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_CMD_ROMUPDATE
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ #define CONFIG_ENV_OVERWRITE
+ #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
+ #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
+ #define CONFIG_ENV_RANGE 0x60000
+ #endif
+ #define CONFIG_SYS_NAND_BASE 0x00000000
-#define CONFIG_ENV_IS_IN_MMC
+ #endif /* CONFIG_CMD_NAND */
+
+ /*
+ * MMC Driver
+ */
+ #ifdef CONFIG_CMD_MMC
+ #ifndef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_FSL_ESDHC
+ #endif
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_CMD_FAT
+ #define CONFIG_FAT_WRITE
+ #define CONFIG_CMD_EXT2
+
+ /*
+ * Environments on MMC
+ */
+ #ifdef CONFIG_ENV_IS_IN_MMC
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_ENV_OVERWRITE
+ /* Associated with the MMC layout defined in mmcops.c */
+ #define CONFIG_ENV_OFFSET SZ_1K
+ #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+ #endif /* CONFIG_ENV_IS_IN_MMC */
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_ENV_OFFSET_REDUND
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),6m(linux),32m(rootfs),89344k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
+ #else
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),6m(linux),32m(rootfs),89728k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
+ #endif
+
+ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+ #ifdef CONFIG_CMD_IIM
+ #define CONFIG_FSL_IIM
+ #endif
+
+ #endif /* __CONFIG_H */
--- /dev/null
-#define CONFIG_MX53 /* must be set before including imx-regs.h */
-
-#include <asm/sizes.h>
+ /*
+ * Copyright (C) 2012-2014 <LW@KARO-electronics.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+
-#define CONFIG_TX53 /* TX53 SoM */
++#include <linux/sizes.h>
+ #include <asm/arch/imx-regs.h>
+
+ /*
+ * Ka-Ro TX53 board - SoC configuration
+ */
-#define LCD_BPP LCD_COLOR24
+ #define CONFIG_SYS_MX5_IOMUX_V3
+ #define CONFIG_MXC_GPIO /* GPIO control */
+ #define CONFIG_SYS_MX5_HCLK 24000000
+ #define CONFIG_SYS_DDR_CLKSEL 0
+ #define CONFIG_SYS_HZ 1000 /* Ticks per second */
+ #define CONFIG_SHOW_ACTIVITY
+ #define CONFIG_DISPLAY_BOARDINFO
+ #define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_BOARD_EARLY_INIT_F
+
+ /* LCD Logo and Splash screen support */
+ #define CONFIG_LCD
+ #ifdef CONFIG_LCD
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_SPLASH_SCREEN_ALIGN
+ #define CONFIG_VIDEO_IPUV3
+ #define CONFIG_IPUV3_CLK 200000000
+ #define CONFIG_LCD_LOGO
-#define CONFIG_SYS_NO_FLASH
++#define LCD_BPP LCD_COLOR32
+ #define CONFIG_CMD_BMP
+ #define CONFIG_VIDEO_BMP_RLE8
+ #endif /* CONFIG_LCD */
+
+ /*
+ * Memory configuration options
+ */
+ #ifndef CONFIG_SYS_SDRAM_SIZE
+ #define CONFIG_SYS_SDRAM_SIZE (SZ_512M * CONFIG_NR_DRAM_BANKS)
+ #endif
+
+ #define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */
+ #define PHYS_SDRAM_1_SIZE (CONFIG_SYS_SDRAM_SIZE / CONFIG_NR_DRAM_BANKS)
+ #if CONFIG_NR_DRAM_BANKS > 1
+ #define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */
+ #define PHYS_SDRAM_2_SIZE PHYS_SDRAM_1_SIZE
+ #endif
+ #define CONFIG_STACKSIZE SZ_128K
+ #define CONFIG_SYS_MALLOC_LEN SZ_8M
+ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
+ #define CONFIG_SYS_SDRAM_CLK 400
+
+ /*
+ * U-Boot general configurations
+ */
+ #define CONFIG_SYS_LONGHELP
+ #define CONFIG_SYS_PROMPT "TX53 U-Boot > "
+ #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+ #define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+ #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
+ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+ #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+ #define CONFIG_AUTO_COMPLETE /* Command auto complete */
+ #define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+ #define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
+
+ /*
+ * Flattened Device Tree (FDT) support
+ */
-#define CONFIG_HW_WATCHDOG
+
+ /*
+ * Boot Linux
+ */
+ #define xstr(s) str(s)
+ #define str(s) #s
+ #define __pfx(x, s) (x##s)
+ #define _pfx(x, s) __pfx(x, s)
+
+ #define CONFIG_CMDLINE_TAG
+ #define CONFIG_SETUP_MEMORY_TAGS
+ #define CONFIG_BOOTDELAY 3
+ #define CONFIG_ZERO_BOOTDELAY_CHECK
+ #define CONFIG_SYS_AUTOLOAD "no"
+ #define CONFIG_BOOTFILE "uImage"
+ #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
+ #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
+ #define CONFIG_LOADADDR 78000000
+ #define CONFIG_FDTADDR 71000000
+ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+ #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
+ #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
-#define CONFIG_FDT_FIXUP_PARTITIONS
+ #ifndef CONFIG_SYS_LVDS_IF
+ #define DEFAULT_VIDEO_MODE "VGA"
+ #else
+ #define DEFAULT_VIDEO_MODE "HSD100PXN1"
+ #endif
+
+ /*
+ * Extra Environment Settings
+ */
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p2 rootwait\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
+ " ip=dhcp\0" \
+ "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
+ "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
+ ";nboot linux\0" \
+ "bootcmd_mmc=set autostart no;run bootargs_mmc" \
+ ";fatload mmc 0 ${loadaddr} uImage\0" \
+ "bootcmd_nand=set autostart no;run bootargs_ubifs" \
+ ";nboot linux\0" \
+ "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
+ ";dhcp\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
+ "boot_mode=nand\0" \
+ "cpu_clk=800\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " ${append_bootargs}\0" \
+ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
+ "fdtsave=fdt resize;nand erase.part dtb" \
+ ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=" DEFAULT_VIDEO_MODE "\0"
+
+ #define MTD_NAME "mxc_nand"
+ #define MTDIDS_DEFAULT "nand0=" MTD_NAME
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_BOOTCE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMTEST
+
+ /*
+ * U-Boot Commands
+ */
+ #include <config_cmd_default.h>
-#define CONFIG_FEC_MXC
+
+ /*
+ * Serial Driver
+ */
+ #define CONFIG_MXC_UART
+ #define CONFIG_MXC_UART_BASE UART1_BASE
+ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
+ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+ #define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+ /*
+ * GPIO driver
+ */
+ #define CONFIG_MXC_GPIO
+
+ /*
+ * Ethernet Driver
+ */
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_SMSC
-#define CONFIG_MII
+ #ifdef CONFIG_FEC_MXC
+ #define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+ #define CONFIG_FEC_XCV_TYPE MII100
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
+ #define CONFIG_CMD_MII
-#define CONFIG_HARD_I2C
+ /* Add for working with "strict" DHCP server */
+ #define CONFIG_BOOTP_SUBNETMASK
+ #define CONFIG_BOOTP_GATEWAY
+ #define CONFIG_BOOTP_DNS
+ #endif
+
+ /*
+ * I2C Configs
+ */
+ #ifdef CONFIG_CMD_I2C
-#define CONFIG_MTD_DEVICE
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_NAND_MXC
+ #define CONFIG_I2C_MXC
+ #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
+ #define CONFIG_SYS_I2C_MX6_PORT1
+ #define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 0x34
+ #endif
+
+ /*
+ * NAND flash driver
+ */
+ #ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
+ #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
+ #define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
+ #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
+ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_CMD_ROMUPDATE
+ #ifdef CONFIG_ENV_IS_IN_NAND
+ #define CONFIG_ENV_OVERWRITE
+ #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
+ #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
+ #define CONFIG_ENV_RANGE 0x60000
+ #endif
+ #define CONFIG_SYS_NAND_BASE 0x00000000
-#define CONFIG_ENV_IS_IN_MMC
+ #endif /* CONFIG_CMD_NAND */
+
+ /*
+ * MMC Driver
+ */
+ #ifdef CONFIG_CMD_MMC
+ #ifndef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_FSL_ESDHC
+ #endif
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_CMD_FAT
+ #define CONFIG_FAT_WRITE
+ #define CONFIG_CMD_EXT2
+
+ /*
+ * Environments on MMC
+ */
+ #ifdef CONFIG_ENV_IS_IN_MMC
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_ENV_OVERWRITE
+ /* Associated with the MMC layout defined in mmcops.c */
+ #define CONFIG_ENV_OFFSET SZ_1K
+ #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+ #endif /* CONFIG_ENV_IS_IN_MMC */
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_ENV_OFFSET_REDUND
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),6m(linux),32m(rootfs),89344k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
+ #else
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),6m(linux),32m(rootfs),89728k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
+ #endif
+
+ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+ #ifdef CONFIG_CMD_IIM
+ #define CONFIG_FSL_IIM
+ #endif
+
+ #endif /* __CONFIG_H */
--- /dev/null
- * Copyright (C) 2012 <LW@KARO-electronics.de>
+ /*
-#include <asm/sizes.h>
++ * Copyright (C) 2012-2015 <LW@KARO-electronics.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+
-#ifndef CONFIG_TX6_REV
-#define CONFIG_TX6_REV 0x1 /* '1' would be converted to 'y' by define2mk.sed */
-#endif
-#define CONFIG_MX6
++#include <linux/sizes.h>
+ #include <asm/arch/imx-regs.h>
++#include "mx6_common.h"
+
+ /*
+ * Ka-Ro TX6 board - SoC configuration
+ */
-#ifndef CONFIG_MFG
+ #define CONFIG_SYS_MX6_HCLK 24000000
+ #define CONFIG_SYS_MX6_CLK32 32768
+ #define CONFIG_SYS_HZ 1000 /* Ticks per second */
+ #define CONFIG_SHOW_ACTIVITY
+ #define CONFIG_ARCH_CPU_INIT
+ #define CONFIG_DISPLAY_BOARDINFO
+ #define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_BOARD_EARLY_INIT_F
++#define CONFIG_SYS_GENERIC_BOARD
+
-#define LCD_BPP LCD_COLOR24
++#ifndef CONFIG_TX6_UBOOT_MFG
+ /* LCD Logo and Splash screen support */
+ #define CONFIG_LCD
+ #ifdef CONFIG_LCD
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_SPLASH_SCREEN_ALIGN
+ #define CONFIG_VIDEO_IPUV3
+ #define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2)
+ #define CONFIG_LCD_LOGO
-#endif /* CONFIG_MFG */
++#define LCD_BPP LCD_COLOR32
+ #define CONFIG_CMD_BMP
+ #define CONFIG_VIDEO_BMP_RLE8
+ #endif /* CONFIG_LCD */
-#define CONFIG_SYS_NO_FLASH
++#endif /* CONFIG_TX6_UBOOT_MFG */
+
+ /*
+ * Memory configuration options
+ */
+ #define CONFIG_NR_DRAM_BANKS 0x1 /* # of SDRAM banks */
+ #define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
+ #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
+ #define PHYS_SDRAM_1_WIDTH CONFIG_SYS_SDRAM_BUS_WIDTH
++#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
++#define PHYS_SDRAM_1_WIDTH 32
++#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16)
++#define PHYS_SDRAM_1_WIDTH 16
+ #else
+ #define PHYS_SDRAM_1_WIDTH 64
+ #endif
+ #define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH)
+ #ifdef CONFIG_MX6Q
+ #define CONFIG_SYS_SDRAM_CLK 528
+ #else
+ #define CONFIG_SYS_SDRAM_CLK 400
+ #endif
+ #define CONFIG_STACKSIZE SZ_128K
+ #define CONFIG_SYS_MALLOC_LEN SZ_8M
+ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
+
+ /*
+ * U-Boot general configurations
+ */
+ #define CONFIG_SYS_LONGHELP
+ #if defined(CONFIG_MX6Q)
+ #define CONFIG_SYS_PROMPT "TX6Q U-Boot > "
+ #elif defined(CONFIG_MX6DL)
+ #define CONFIG_SYS_PROMPT "TX6DL U-Boot > "
+ #elif defined(CONFIG_MX6S)
+ #define CONFIG_SYS_PROMPT "TX6S U-Boot > "
+ #else
+ #error Unsupported i.MX6 processor variant
+ #endif
+ #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+ #define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+ #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
+ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+ #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+ #define CONFIG_AUTO_COMPLETE /* Command auto complete */
+ #define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+ #define CONFIG_SYS_64BIT_VSPRINTF
-#ifndef CONFIG_MFG
-#define CONFIG_OF_LIBFDT
+
+ /*
+ * Flattened Device Tree (FDT) support
+ */
-#ifndef CONFIG_NO_NAND
-#define CONFIG_FDT_FIXUP_PARTITIONS
+ #ifdef CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
++#ifdef CONFIG_TX6_NAND
+ #endif
-#endif /* CONFIG_MFG */
+ #endif /* CONFIG_OF_LIBFDT */
-#ifndef CONFIG_MFG
+
+ /*
+ * Boot Linux
+ */
+ #define xstr(s) str(s)
+ #define str(s) #s
+ #define __pfx(x, s) (x##s)
+ #define _pfx(x, s) __pfx(x, s)
+
+ #define CONFIG_CMDLINE_TAG
+ #define CONFIG_INITRD_TAG
+ #define CONFIG_SETUP_MEMORY_TAGS
-#ifndef CONFIG_MFG
++#ifndef CONFIG_TX6_UBOOT_MFG
+ #define CONFIG_BOOTDELAY 1
+ #else
+ #define CONFIG_BOOTDELAY 0
+ #endif
+ #define CONFIG_ZERO_BOOTDELAY_CHECK
+ #define CONFIG_SYS_AUTOLOAD "no"
-#endif /* CONFIG_MFG */
++#ifndef CONFIG_TX6_UBOOT_MFG
+ #define CONFIG_BOOTFILE "uImage"
+ #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
+ #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
+ #else
+ #define CONFIG_BOOTCOMMAND "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg"
+ #define CONFIG_BOOTCMD_MFG_LOADADDR 10500000
+ #define CONFIG_DELAY_ENVIRONMENT
-#define CONFIG_HW_WATCHDOG
++#endif /* CONFIG_TX6_UBOOT_MFG */
+ #define CONFIG_LOADADDR 18000000
+ #define CONFIG_FDTADDR 11000000
+ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+ #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
-#ifndef CONFIG_MFG
+ #ifndef CONFIG_SYS_LVDS_IF
+ #define DEFAULT_VIDEO_MODE "VGA"
+ #else
+ #define DEFAULT_VIDEO_MODE "HSD100PXN1"
+ #endif
+
+ /*
+ * Extra Environments
+ */
-#endif /* CONFIG_MFG */
++#ifndef CONFIG_TX6_UBOOT_MFG
+ #ifdef CONFIG_ENV_IS_NOWHERE
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "autoload=no\0" \
+ "bootdelay=-1\0" \
+ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0"
+ #else
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ MMC_ROOT_STR \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
+ " ip=dhcp\0" \
+ "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
+ "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
+ ";nboot linux\0" \
+ "bootcmd_mmc=set autostart no;run bootargs_mmc" \
+ ";fatload mmc 0 ${loadaddr} uImage\0" \
+ CONFIG_SYS_BOOT_CMD_NAND \
+ "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
+ ";dhcp\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
+ "boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \
+ "cpu_clk=800\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " ${append_bootargs}\0" \
+ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
+ CONFIG_SYS_FDTSAVE_CMD \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ ROOTPART_UUID_STR \
+ "touchpanel=tsc2007\0" \
+ "video_mode=" DEFAULT_VIDEO_MODE "\0"
+ #endif /* CONFIG_ENV_IS_NOWHERE */
-#ifndef CONFIG_NO_NAND
++#endif /* CONFIG_TX6_UBOOT_MFG */
+
-#define MMC_ROOT_STR " root=dev/mmcblk0p2 rootwait\0"
++#ifdef CONFIG_TX6_NAND
+ #define CONFIG_SYS_DEFAULT_BOOT_MODE "nand"
+ #define CONFIG_SYS_BOOT_CMD_NAND \
+ "bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0"
+ #define CONFIG_SYS_FDTSAVE_CMD \
+ "fdtsave=fdt resize;nand erase.part dtb" \
+ ";nand write ${fdtaddr} dtb ${fdtsize}\0"
+ #define MTD_NAME "gpmi-nand"
+ #define MTDIDS_DEFAULT "nand0=" MTD_NAME
+ #define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_MMC_BOOT_DEV 0
++#define MMC_ROOT_STR " root=/dev/mmcblk0p2 rootwait\0"
+ #define ROOTPART_UUID_STR ""
+ #else
+ #define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc"
+ #define CONFIG_SYS_BOOT_CMD_NAND ""
+ #define CONFIG_SYS_FDTSAVE_CMD \
+ "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " \
+ xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0"
+ #define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0"
+ #define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0"
+ #define MTD_NAME ""
+ #define MTDIDS_DEFAULT ""
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MMC
-#ifndef CONFIG_NO_NAND
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#endif
-#define CONFIG_CMD_BOOTCE
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMTEST
++#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ #endif
++#endif /* CONFIG_TX6_NAND */
+
+ /*
+ * U-Boot Commands
+ */
+ #include <config_cmd_default.h>
-#define CONFIG_FEC_MXC
+
+ /*
+ * Serial Driver
+ */
+ #define CONFIG_MXC_UART
+ #define CONFIG_MXC_UART_BASE UART1_BASE
+ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
+ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+ #define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+ /*
+ * GPIO driver
+ */
+ #define CONFIG_MXC_GPIO
+
+ /*
+ * Ethernet Driver
+ */
-#define CONFIG_SYS_CACHELINE_SIZE 64
+ #ifdef CONFIG_FEC_MXC
+ /* This is required for the FEC driver to work with cache enabled */
+ #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_SMSC
-#define CONFIG_MII
+
+ #define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-/* Add for working with "strict" DHCP server */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
+ #define CONFIG_FEC_XCV_TYPE RMII
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
+ #endif
+
+ /*
+ * I2C Configs
+ */
-#define CONFIG_SYS_I2C_MX6_PORT1
++#ifdef CONFIG_SYS_I2C
+ #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
-#endif
+ #define CONFIG_SYS_I2C_SPEED 400000
++#if defined(CONFIG_TX6_REV)
+ #if CONFIG_TX6_REV == 0x1
+ #define CONFIG_SYS_I2C_SLAVE 0x3c
+ #define CONFIG_LTC3676
+ #elif CONFIG_TX6_REV == 0x2
+ #define CONFIG_SYS_I2C_SLAVE 0x32
+ #define CONFIG_RN5T618
+ #elif CONFIG_TX6_REV == 0x3
+ #define CONFIG_SYS_I2C_SLAVE 0x33
+ #define CONFIG_RN5T567
+ #else
+ #error Unsupported TX6 module revision
+ #endif
-#ifndef CONFIG_ENV_IS_NOWHERE
-/* define one of the following options:
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_IS_IN_MMC
-*/
-#define CONFIG_ENV_IS_IN_NAND
-#endif
++#endif /* CONFIG_TX6_REV */
++/* autodetect which PMIC is present to derive TX6_REV */
++#define CONFIG_LTC3676 /* TX6_REV == 1 */
++#define CONFIG_RN5T567 /* TX6_REV == 3 */
++#endif /* CONFIG_CMD_I2C */
+
-#ifndef CONFIG_NO_NAND
-#define CONFIG_MTD_DEVICE
-#if 0
-#define CONFIG_MTD_DEBUG
-#define CONFIG_MTD_DEBUG_VERBOSE 4
-#endif
-#define CONFIG_NAND_MXS
-#define CONFIG_NAND_MXS_NO_BBM_SWAP
-#define CONFIG_APBH_DMA
-#define CONFIG_APBH_DMA_BURST
-#define CONFIG_APBH_DMA_BURST8
-#define CONFIG_CMD_NAND_TRIMFFS
+ #define CONFIG_ENV_OVERWRITE
+
+ /*
+ * NAND flash driver
+ */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
++#ifdef CONFIG_TX6_NAND
+ #define CONFIG_SYS_MXS_DMA_CHANNEL 4
+ #define CONFIG_SYS_MAX_FLASH_BANKS 0x1
+ #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
-#define CONFIG_CMD_ROMUPDATE
+ #define CONFIG_SYS_NAND_BASE 0x00000000
-#endif /* CONFIG_NO_NAND */
++#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+ #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
+ #define CONFIG_ENV_SIZE SZ_128K
+ #define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+ #else
+ #undef CONFIG_ENV_IS_IN_NAND
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
++#endif /* CONFIG_TX6_NAND */
+
+ #ifdef CONFIG_ENV_OFFSET_REDUND
+ #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
+ "(env)," \
+ xstr(CONFIG_SYS_ENV_PART_SIZE) \
+ "(env2),"
+ #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE) "(userfs)"
+ #else
+ #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
+ "(env),"
+ #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE2) "(userfs)"
+ #endif /* CONFIG_ENV_OFFSET_REDUND */
+
+ /*
+ * MMC Driver
+ */
-
++#ifdef CONFIG_FSL_ESDHC
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#ifndef CONFIG_NO_NAND
++#endif
++#ifdef CONFIG_CMD_MMC
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_CMD_FAT
+ #define CONFIG_FAT_WRITE
+ #define CONFIG_CMD_EXT2
+
+ /*
+ * Environments on MMC
+ */
+ #ifdef CONFIG_ENV_IS_IN_MMC
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_SYS_MMC_ENV_PART 0x1
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+ #endif /* CONFIG_ENV_IS_IN_MMC */
+ #else
+ #undef CONFIG_ENV_IS_IN_MMC
+ #endif /* CONFIG_CMD_MMC */
+
+ #ifdef CONFIG_ENV_IS_NOWHERE
+ #undef CONFIG_ENV_SIZE
+ #define CONFIG_ENV_SIZE SZ_4K
+ #endif
+
++#ifdef CONFIG_TX6_NAND
+ #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \
+ "@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) \
+ "(u-boot)," \
+ CONFIG_SYS_ENV_PART_STR \
+ "6m(linux),32m(rootfs)," CONFIG_SYS_USERFS_PART_STR "," \
+ xstr(CONFIG_SYS_DTB_PART_SIZE) \
+ "@" xstr(CONFIG_SYS_NAND_DTB_OFFSET) "(dtb)," \
+ xstr(CONFIG_SYS_NAND_BBT_SIZE) \
+ "@" xstr(CONFIG_SYS_NAND_BBT_OFFSET) "(bbt)ro"
+ #else
+ #define MTDPARTS_DEFAULT ""
+ #endif
+
+ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+ #endif /* __CONFIG_H */
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
struct fsl_esdhc_cfg {
- u32 esdhc_base;
+ void __iomem *esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
+ struct mmc_config cfg;
};
/* Select the correct accessors depending on endianess */
# define CONSOLE_COLOR_GREY 14
# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
- #else
+#elif LCD_BPP == LCD_COLOR32
+/*
+ * 32bpp color definitions
+ */
+# define CONSOLE_COLOR_RED 0x00ff0000
+# define CONSOLE_COLOR_GREEN 0x0000ff00
+# define CONSOLE_COLOR_YELLOW 0x00ffff00
+# define CONSOLE_COLOR_BLUE 0x000000ff
+# define CONSOLE_COLOR_MAGENTA 0x00ff00ff
+# define CONSOLE_COLOR_CYAN 0x0000ffff
+# define CONSOLE_COLOR_GREY 0x00aaaaaa
+# define CONSOLE_COLOR_BLACK 0x00000000
+# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest*/
+# define NBYTES(bit_code) (NBITS(bit_code) >> 3)
+
+ #elif LCD_BPP == LCD_COLOR16
/*
* 16bpp color definitions
*/
# define CONSOLE_COLOR_BLACK 0x0000
+ # define CONSOLE_COLOR_RED 0xf800
+ # define CONSOLE_COLOR_GREEN 0x07e0
+ # define CONSOLE_COLOR_YELLOW 0xffe0
+ # define CONSOLE_COLOR_BLUE 0x001f
+ # define CONSOLE_COLOR_MAGENTA 0xf81f
+ # define CONSOLE_COLOR_CYAN 0x07ff
+ # define CONSOLE_COLOR_GREY 0xcccc
# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
-#elif LCD_BPP == LCD_COLOR24
-/*
- * 16bpp color definitions
- */
-# define CONSOLE_COLOR_BLACK 0x00000000
-# define CONSOLE_COLOR_RED 0x00ff0000
-# define CONSOLE_COLOR_GREEN 0x0000ff00
-# define CONSOLE_COLOR_YELLOW 0x00ffff00
-# define CONSOLE_COLOR_BLUE 0x000000ff
-# define CONSOLE_COLOR_MAGENTA 0x00ff00ff
-# define CONSOLE_COLOR_CYAN 0x0000ffff
-# define CONSOLE_COLOR_GREY 0x00cccccc
-# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest */
+ #else
+ #error Invalid LCD_BPP setting
#endif /* color definitions */
/************************************************************************/
#include <config.h>
--/*
-- * All boards using a given driver must convert to self-init
-- * at the same time, so do it here. When all drivers are
-- * converted, this will go away.
-- */
- #ifdef CONFIG_SPL_BUILD
- #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
- #define CONFIG_SYS_NAND_SELF_INIT
- #endif
- #else
--#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
- || defined(CONFIG_NAND_FSL_IFC)
- || defined(CONFIG_NAND_FSL_IFC) || defined(CONFIG_NAND_MXC)
--#define CONFIG_SYS_NAND_SELF_INIT
- #endif
--#endif
--
extern void nand_init(void);
#include <linux/compat.h>
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
-
-# CFLAGS += -DDEBUG
-
-LIB = $(obj)libnet.o
-
-COBJS-$(CONFIG_CMD_BOOTCE) += bootme.o
-COBJS-$(CONFIG_CMD_NET) += arp.o
-COBJS-$(CONFIG_CMD_NET) += bootp.o
-COBJS-$(CONFIG_CMD_CDP) += cdp.o
-COBJS-$(CONFIG_CMD_DNS) += dns.o
-COBJS-$(CONFIG_CMD_NET) += eth.o
-COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
-COBJS-$(CONFIG_CMD_NET) += net.o
-COBJS-$(CONFIG_CMD_NFS) += nfs.o
-COBJS-$(CONFIG_CMD_PING) += ping.o
-COBJS-$(CONFIG_CMD_RARP) += rarp.o
-COBJS-$(CONFIG_CMD_SNTP) += sntp.o
-COBJS-$(CONFIG_CMD_NET) += tftp.o
-
-COBJS := $(sort $(COBJS-y))
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-all: $(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+#ccflags-y += -DDEBUG
+
+obj-$(CONFIG_CMD_NET) += arp.o
++obj-$(CONFIG_CMD_BOOTCE) += bootme.o
+obj-$(CONFIG_CMD_NET) += bootp.o
+obj-$(CONFIG_CMD_CDP) += cdp.o
+obj-$(CONFIG_CMD_DNS) += dns.o
+obj-$(CONFIG_CMD_NET) += eth.o
+obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
+obj-$(CONFIG_CMD_NET) += net.o
+obj-$(CONFIG_CMD_NFS) += nfs.o
+obj-$(CONFIG_CMD_PING) += ping.o
+obj-$(CONFIG_CMD_RARP) += rarp.o
+obj-$(CONFIG_CMD_SNTP) += sntp.o
+obj-$(CONFIG_CMD_NET) += tftp.o
| ((ulong)NetOurEther[4] << 8)
| (ulong)NetOurEther[5];
BootpID += get_timer(0);
- BootpID = htonl(BootpID);
+ BootpID = htonl(BootpID);
+ bootp_add_id(BootpID);
+ #endif
NetCopyLong(&bp->bp_id, &BootpID);
/*
ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y
CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y)
-# Generated executable files
-BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
-BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
-BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
-BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
-BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
-BIN_FILES-y += mkenvimage$(SFX)
-BIN_FILES-y += mkimage$(SFX)
-BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
-BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
-BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
-BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
-BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
-BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
-BIN_FILES-y += proftool(SFX)
-
-# Source files which exist outside the tools directory
-EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
-EXT_OBJ_FILES-y += common/image.o
-EXT_OBJ_FILES-$(CONFIG_FIT) += common/image-fit.o
-EXT_OBJ_FILES-y += common/image-sig.o
-EXT_OBJ_FILES-y += lib/crc32.o
-EXT_OBJ_FILES-y += lib/md5.o
-EXT_OBJ_FILES-y += lib/sha1.o
-
-# Source files located in the tools directory
-OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
-OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
-NOPED_OBJ_FILES-y += default_image.o
-NOPED_OBJ_FILES-y += proftool.o
-OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
-NOPED_OBJ_FILES-y += fit_image.o
-OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
-OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
-OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
-NOPED_OBJ_FILES-y += aisimage.o
-NOPED_OBJ_FILES-y += kwbimage.o
-NOPED_OBJ_FILES-y += pblimage.o
-NOPED_OBJ_FILES-y += imximage.o
-NOPED_OBJ_FILES-y += image-host.o
-NOPED_OBJ_FILES-y += omapimage.o
-NOPED_OBJ_FILES-y += mkenvimage.o
-NOPED_OBJ_FILES-y += mkimage.o
-OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
-OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
-OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
-OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
-NOPED_OBJ_FILES-y += os_support.o
-OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
-NOPED_OBJ_FILES-y += ublimage.o
-OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
+hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params
-# Don't build by default
-#ifeq ($(ARCH),ppc)
-#BIN_FILES-y += mpc86x_clk$(SFX)
-#OBJ_FILES-y += mpc86x_clk.o
-#endif
+# TODO: CONFIG_CMD_LICENSE does not work
+hostprogs-$(CONFIG_CMD_LICENSE) += bin2header
+hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo
+hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo
+HOSTCFLAGS_bmp_logo.o := -pedantic
+
+hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc
+envcrc-objs := envcrc.o lib/crc32.o common/env_embedded.o lib/sha1.o
+
+hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr
+HOSTCFLAGS_gen_eth_addr.o := -pedantic
+
+hostprogs-$(CONFIG_CMD_LOADS) += img2srec
+HOSTCFLAGS_img2srec.o := -pedantic
- hostprogs-y += dumpimage mkimage
+hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes
+HOSTCFLAGS_xway-swap-bytes.o := -pedantic
+
+hostprogs-y += mkenvimage
+mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
+
++#hostprogs-y += dumpimage mkimage
+hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
+
+FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o
# Flattened device tree objects
-LIBFDT_OBJ_FILES-y += fdt.o
-LIBFDT_OBJ_FILES-y += fdt_ro.o
-LIBFDT_OBJ_FILES-y += fdt_rw.o
-LIBFDT_OBJ_FILES-y += fdt_strerror.o
-LIBFDT_OBJ_FILES-y += fdt_wip.o
+LIBFDT_OBJS := $(addprefix lib/libfdt/, \
+ fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o)
+RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
+ rsa-sign.o rsa-verify.o rsa-checksum.o)
+
+# common objs for dumpimage and mkimage
+dumpimage-mkimage-objs := aisimage.o \
+ atmelimage.o \
+ $(FIT_SIG_OBJS-y) \
+ common/bootm.o \
+ lib/crc32.o \
+ default_image.o \
+ lib/fdtdec_common.o \
+ lib/fdtdec.o \
+ fit_common.o \
+ fit_image.o \
+ gpimage.o \
+ gpimage-common.o \
+ common/image-fit.o \
+ image-host.o \
+ common/image.o \
+ imagetool.o \
+ imximage.o \
+ kwbimage.o \
+ lib/md5.o \
+ mxsimage.o \
+ omapimage.o \
+ os_support.o \
+ pblimage.o \
+ pbl_crc32.o \
+ socfpgaimage.o \
+ lib/sha1.o \
+ lib/sha256.o \
+ ublimage.o \
+ $(LIBFDT_OBJS) \
+ $(RSA_OBJS-y)
+
+dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
+mkimage-objs := $(dumpimage-mkimage-objs) mkimage.o
+fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o
+fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
+
+# TODO(sjg@chromium.org): Is this correct on Mac OS?
+
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
+# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
+# the mxsimage support within tools/mxsimage.c .
+HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
+endif
+
+ifdef CONFIG_FIT_SIGNATURE
+# This affects include/image.h, but including the board config file
+# is tricky, so manually define this options here.
+HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE
+endif
+
+# MXSImage needs LibSSL
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
+HOSTLOADLIBES_mkimage += -lssl -lcrypto
+endif
+
+HOSTLOADLIBES_dumpimage := $(HOSTLOADLIBES_mkimage)
+HOSTLOADLIBES_fit_info := $(HOSTLOADLIBES_mkimage)
+HOSTLOADLIBES_fit_check_sign := $(HOSTLOADLIBES_mkimage)
+
+hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl
+hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
+HOSTCFLAGS_mkexynosspl.o := -pedantic
-# RSA objects
-RSA_OBJ_FILES-$(CONFIG_FIT_SIGNATURE) += rsa-sign.o
+ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o
+hostprogs-$(CONFIG_X86) += ifdtool
+
+hostprogs-$(CONFIG_MX23) += mxsboot
+hostprogs-$(CONFIG_MX28) += mxsboot
+HOSTCFLAGS_mxsboot.o := -pedantic
+
+hostprogs-$(CONFIG_SUNXI) += mksunxiboot
+
+hostprogs-$(CONFIG_NETCONSOLE) += ncb
+hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1
+
+ubsha1-objs := os_support.o ubsha1.o lib/sha1.o
+
+HOSTCFLAGS_ubsha1.o := -pedantic
+
+hostprogs-$(CONFIG_KIRKWOOD) += kwboot
+hostprogs-$(CONFIG_ARMADA_XP) += kwboot
+hostprogs-y += proftool
+hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
+
+# We build some files with extra pedantic flags to try to minimize things
+# that won't build on some weird host compiler -- though there are lots of
+# exceptions for files that aren't complaint.
+HOSTCFLAGS_crc32.o := -pedantic
+HOSTCFLAGS_md5.o := -pedantic
+HOSTCFLAGS_sha1.o := -pedantic
+HOSTCFLAGS_sha256.o := -pedantic
+
+# Don't build by default
+#hostprogs-$(CONFIG_PPC) += mpc86x_clk
+#HOSTCFLAGS_mpc86x_clk.o := -pedantic
+
+quiet_cmd_wrap = WRAP $@
+cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@
+
+$(obj)/lib/%.c $(obj)/common/%.c:
+ $(call cmd,wrap)
+
+clean-dirs := lib common
+
+always := $(hostprogs-y)
# Generated LCD/video logo
-LOGO_H = $(OBJTREE)/include/bmp_logo.h
-LOGO_DATA_H = $(OBJTREE)/include/bmp_logo_data.h
+LOGO_H = $(objtree)/include/bmp_logo.h
+LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h
LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_H)
LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H)
LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H)
#
# Use native tools and options
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
+# Define _GNU_SOURCE to obtain the getline prototype from stdio.h
#
-HOSTCPPFLAGS = -include $(SRCTREE)/include/libfdt_env.h \
- -idirafter $(SRCTREE)/include \
- -idirafter $(OBJTREE)/include2 \
- -idirafter $(OBJTREE)/include \
- -I $(SRCTREE)/lib/libfdt \
- -I $(SRCTREE)/tools \
+HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \
+ $(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \
+ -I$(srctree)/lib/libfdt \
+ -I$(srctree)/tools \
++ -include $(srctree)/include/linux/kconfig.h \
++ -Wno-variadic-macros \
-DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-DUSE_HOSTCC \
- -D__KERNEL_STRICT_NAMES
-
-
-all: $(obj).depend $(BINS) $(LOGO-y) subdirs
-
-$(obj)bin2header$(SFX): $(obj)bin2header.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)bmp_logo$(SFX): $(obj)bmp_logo.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)proftool(SFX): $(obj)proftool.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)envcrc$(SFX): $(obj)crc32.o $(obj)env_embedded.o $(obj)envcrc.o $(obj)sha1.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)img2srec$(SFX): $(obj)img2srec.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o \
- $(obj)os_support.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)mkimage$(SFX): $(obj)aisimage.o \
- $(obj)crc32.o \
- $(obj)default_image.o \
- $(obj)fit_image.o \
- $(obj)image-fit.o \
- $(obj)image.o \
- $(obj)image-host.o \
- $(FIT_SIG_OBJS) \
- $(obj)imximage.o \
- $(obj)kwbimage.o \
- $(obj)pblimage.o \
- $(obj)md5.o \
- $(obj)mkimage.o \
- $(obj)os_support.o \
- $(obj)omapimage.o \
- $(obj)sha1.o \
- $(obj)ublimage.o \
- $(LIBFDT_OBJS) \
- $(RSA_OBJS)
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTLIBS)
- $(HOSTSTRIP) $@
-
-$(obj)mk$(BOARD)spl$(SFX): $(obj)mkexynosspl.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)mxsboot$(SFX): $(obj)mxsboot.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)ncb$(SFX): $(obj)ncb.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
+ -D__KERNEL_STRICT_NAMES \
+ -D_GNU_SOURCE
-$(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+__build: $(LOGO-y)
-$(obj)kwboot$(SFX): $(obj)kwboot.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
+$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP)
+ $(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@
-# Some of the tool objects need to be accessed from outside the tools directory
-$(obj)%.o: $(SRCTREE)/common/%.c
- $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
+$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP)
+ $(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@
-$(obj)%.o: $(SRCTREE)/lib/%.c
- $(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $<
+# Let clean descend into subdirs
+subdir- += env
-$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c
- $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
+ifneq ($(CROSS_BUILD_TOOLS),)
+HOSTCC = $(CC)
-$(obj)%.o: $(SRCTREE)/lib/rsa/%.c
- $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
+quiet_cmd_crosstools_strip = STRIP $^
+ cmd_crosstools_strip = $(STRIP) $^; touch $@
+$(obj)/.strip: $(call objectify,$(filter $(always),$(hostprogs-y)))
+ $(call cmd,crosstools_strip)
-subdirs:
-ifeq ($(TOOLSUBDIRS),)
- @:
-else
- @for dir in $(TOOLSUBDIRS) ; do \
- $(MAKE) \
- HOSTOS=$(HOSTOS) \
- HOSTARCH=$(HOSTARCH) \
- -C $$dir || exit 1 ; \
- done
+always += .strip
endif
-
-$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
- $(obj)./bmp_logo --gen-info $(LOGO_BMP) > $@
-
-$(LOGO_DATA_H): $(obj)bmp_logo $(LOGO_BMP)
- $(obj)./bmp_logo --gen-data $(LOGO_BMP) > $@
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+clean-files += .strip
projects / karo-tx-uboot.git / commitdiff