add TX53 support

diff --git a/README.KARO-FDT b/README.KARO-FDT
new file mode 100644 (file)
index 0000000..9556f6c
--- /dev/null
+++ b/README.KARO-FDT
@@ -0,0 +1,52 @@
+                                 Managing the device tree data in U-Boot
+                                =======================================
+
+The 'fdt' command can be used to manipulate the device tree (DT) data
+that is passed from U-Boot to Linux.
+
+- 'fdt boardsetup' will trim out some device nodes according to
+  environment settings:
+
+Environment setting            removed nodes
+otg_mode=host                  usbh1
+otg_mode=device                        usbotg
+otg_mode=<UNSET>               <both of the above> + usbphy
+
+touchpanel=edt-ft5x06          ti,tsc2007
+touchpanel=tsc2007             edt,edt-ft5x06
+touchpanel=<UNSET>             <both of the above>
+
+Note: This command is automatically executed when booting Linux via
+      the 'bootm_cmd' environment variable.
+
+- 'fdt rm' and 'fdt add' can be used to remove/create additional nodes
+
+The whole DT data can be saved to and reloaded from the 'dtb' (or any
+other) partition:
+  nand erase.part dtb
+  nand write.jffs2 ${fdtcontroladdr} dtb
+
+Note: To prevent U-Boot from overwriting data in the succeeding
+partition when encountering bad blocks in the 'dtb' partition, it is
+wise to explicitly specify the write size according to 'totalsize'
+displayed by the command 'fdt header':
+TX53 U-Boot > fdt header
+magic:                  0xd00dfeed
+totalsize:              0x3f9e (16286)
+off_dt_struct:          0x78
+off_dt_strings:         0x2bb8
+off_mem_rsvmap:         0x28
+version:                17
+last_comp_version:      16
+boot_cpuid_phys:        0x0
+size_dt_strings:        0x3e6
+size_dt_struct:         0x2b40
+number mem_rsv:         0x0
+TX53 U-Boot > nand write.jffs2 ${fdtcontroladdr} dtb 3f9e
+
+If a DT is loaded from flash which should not be further manipulated
+upon booting Linux, the string 'fdt boardsetup;' should be removed
+from the 'bootm_cmd' environment variable.
+
+Loading the DT data:
+  nand read ${fdtcontroladdr} dtb

diff --git a/README.KARO-TX53 b/README.KARO-TX53
new file mode 100644 (file)
index 0000000..92ad39a
--- /dev/null
+++ b/README.KARO-TX53
@@ -0,0 +1,36 @@
+                             Building & Flashing U-Boot for TX53
+                             ===================================
+
+Building U-Boot
+---------------
+
+Note: There are currently two variants of the TX53 module, that
+      require slightly different U-Boot configurations. They are
+      distinguished through the last digit of the module name. Replace
+      the '?' in the following description with the corresponding
+      number from your TX51 module.
+      E.g. TX53-8031 => 'make tx53-xx31_config'
+
+Unpacking the source
+--------------------
+mkdir u-boot
+cd u-boot
+tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2
+
+Compiling U-Boot
+----------------
+export ARCH=arm
+export CROSS_COMPILE=arm-cortexa8-linux-gnueabi-
+make tx53-xx3?_config            (see above Note!)
+make
+
+
+Flashing U-Boot Image
+---------------------
+If you want to replace a working U-Boot with a new version, you can
+load the new U-Boot image via TFTP and program it like any other flash
+partition with:
+nand erase.part u-boot;nand write ${fileaddr} u-boot ${filesize}
+
+If you want to revive a bricked module, you can use one of the
+flashtools provided with the BSP to reprogram the flash.

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 9c2990dcce491d9968f1e9dade83ca0570630e7b..383379d15cfc5abd517fc1c6685331d0bcc38dd7 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -182,6 +182,8 @@
 1:     ldr r1, [r0, #CLKCTL_CDHIPR]
        cmp r1, #0x0
        bne 1b
+#elif defined(CONFIG_TX53)
+       @ CCGR registers have been setup via DCD
 #else
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]
@@ -233,6 +235,46 @@
        ldr r1, =0x000020C0
        orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
        str r1, [r0, #CLKCTL_CBCMR]
+#elif defined(CONFIG_TX53)
+       setup_pll PLL3_BASE_ADDR, 400
+
+       /* Switch peripheral to PLL 3 */
+       ldr r1, [r0, #CLKCTL_CBCMR]
+       bic r1, #(0x3 << 12)
+       orr r1, r1, #(1 << 12)
+       str r1, [r0, #CLKCTL_CBCMR]
+
+       ldr r1, [r0, #CLKCTL_CBCDR]
+       orr r1, r1, #(1 << 25)
+       str r1, [r0, #CLKCTL_CBCDR]
+1:
+       /* make sure change is effective */
+       ldr     r1, [r0, #CLKCTL_CDHIPR]
+       tst     r1, #0x7f
+       bne     1b
+#if CONFIG_SYS_SDRAM_CLK == 400
+       setup_pll PLL2_BASE_ADDR, 400
+#elif CONFIG_SYS_SDRAM_CLK == 333
+ä     setup_pll PLL2_BASE_ADDR, 333
+#else
+#error Unsupported CONFIG_SYS_SDRAM_CLK
+#endif
+       /* Switch peripheral to PLL2 */
+       ldr r0, =CCM_BASE_ADDR
+       ldr r1, [r0, #CLKCTL_CBCDR]
+       bic r1, #(1 << 25)
+       str r1, [r0, #CLKCTL_CBCDR]
+
+       ldr r1, [r0, #CLKCTL_CBCMR]
+       bic r1, #(3 << 12)
+       orr r1, #(2 << 12)
+       str r1, [r0, #CLKCTL_CBCMR]
+
+       /* make sure change is effective */
+1:
+       ldr     r1, [r0, #CLKCTL_CDHIPR]
+       cmp     r1, #0x0
+       bne     1b
 #endif
        setup_pll PLL3_BASE_ADDR, 216
 
@@ -268,7 +310,7 @@
        ldr r1, =CONFIG_SYS_CLKTL_CBCDR
        str r1, [r0, #CLKCTL_CBCDR]
 #endif
-
+#ifndef CONFIG_TX53
        /* Restore the default values in the Gate registers */
        ldr r1, =0xFFFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]
@@ -281,7 +323,9 @@
 #if defined(CONFIG_MX53)
        str r1, [r0, #CLKCTL_CCGR7]
 #endif
+#endif
 
+#if !defined(CONFIG_TX53)
 #if defined(CONFIG_MX51)
        /* Use PLL 2 for UART's, get 66.5MHz from it */
        ldr r1, =0xA5A2A020
@@ -312,7 +356,7 @@
 1:     ldr r1, [r0, #CLKCTL_CDHIPR]
        cmp r1, #0x0
        bne 1b
-
+#endif
        mov r1, #0x0
        str r1, [r0, #CLKCTL_CCDR]
 
@@ -367,6 +411,12 @@ W_DP_MFN_665:             .word DP_MFN_665
 W_DP_OP_600:              .word DP_OP_600
 W_DP_MFD_600:             .word DP_MFD_600
 W_DP_MFN_600:             .word DP_MFN_600
+W_DP_OP_400:              .word DP_OP_400
+W_DP_MFD_400:             .word DP_MFD_400
+W_DP_MFN_400:             .word DP_MFN_400
+W_DP_OP_333:              .word DP_OP_333
+W_DP_MFD_333:             .word DP_MFD_333
+W_DP_MFN_333:             .word DP_MFN_333
 W_DP_OP_216:              .word DP_OP_216
 W_DP_MFD_216:             .word DP_MFD_216
 W_DP_MFN_216:             .word DP_MFN_216

diff --git a/arch/arm/dts/mx53.dtsi b/arch/arm/dts/mx53.dtsi
new file mode 100644 (file)
index 0000000..759b5a7
--- /dev/null
+++ b/arch/arm/dts/mx53.dtsi
@@ -0,0 +1,489 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       aliases {
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               serial4 = &uart5;
+       };
+
+       tzic: tz-interrupt-controller@0fffc000 {
+               compatible = "fsl,imx53-tzic", "fsl,tzic";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               reg = <0x0fffc000 0x4000>;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ckil {
+                       compatible = "fsl,imx-ckil", "fixed-clock";
+                       clock-frequency = <32768>;
+               };
+
+               ckih1 {
+                       compatible = "fsl,imx-ckih1", "fixed-clock";
+                       clock-frequency = <22579200>;
+               };
+
+               ckih2 {
+                       compatible = "fsl,imx-ckih2", "fixed-clock";
+                       clock-frequency = <0>;
+               };
+
+               osc {
+                       compatible = "fsl,imx-osc", "fixed-clock";
+                       clock-frequency = <24000000>;
+               };
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               interrupt-parent = <&tzic>;
+               ranges;
+
+               aips@50000000 { /* AIPS1 */
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x50000000 0x10000000>;
+                       ranges;
+
+                       spba@50000000 {
+                               compatible = "fsl,spba-bus", "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0x50000000 0x40000>;
+                               ranges;
+
+                               ssi2: ssi@50014000 {
+                                       compatible = "fsl,imx-ssi";
+                                       reg = <0x50014000 0x4000>;
+                                       interrupts = <30>;
+                                       status = "disabled";
+                               };
+
+                               esdhc@50004000 { /* ESDHC1 */
+                                       compatible = "fsl,imx53-esdhc";
+                                       reg = <0x50004000 0x4000>;
+                                       interrupts = <1>;
+                                       status = "disabled";
+                               };
+
+                               esdhc@50008000 { /* ESDHC2 */
+                                       compatible = "fsl,imx53-esdhc";
+                                       reg = <0x50008000 0x4000>;
+                                       interrupts = <2>;
+                                       status = "disabled";
+                               };
+
+                               uart3: uart@5000c000 {
+                                       compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                                       reg = <0x5000c000 0x4000>;
+                                       interrupts = <33>;
+                                       status = "disabled";
+                               };
+
+                               ecspi@50010000 { /* ECSPI1 */
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
+                                       reg = <0x50010000 0x4000>;
+                                       interrupts = <36>;
+                                       status = "disabled";
+                               };
+
+                               esdhc@50020000 { /* ESDHC3 */
+                                       compatible = "fsl,imx53-esdhc";
+                                       reg = <0x50020000 0x4000>;
+                                       interrupts = <3>;
+                                       status = "disabled";
+                               };
+
+                               esdhc@50024000 { /* ESDHC4 */
+                                       compatible = "fsl,imx53-esdhc";
+                                       reg = <0x50024000 0x4000>;
+                                       interrupts = <4>;
+                                       status = "disabled";
+                               };
+                       };
+
+                       imxotg@53f80000 {
+                               compatible = "fsl,imx-otg";
+                               reg = <0x53f80000 0x200>;
+                               interrupts = <18>;
+                               status = "disabled";
+
+                               phy-mode = "utmi-wide";
+                               host-device-name = "mxc-ehci";
+                               host-device-id = <0>;
+                               gadget-device-name = "fsl-usb2-udc";
+
+                       };
+
+                       imxotg@53f80200 {
+                               compatible = "fsl,imx-otg";
+                               reg = <0x53f80200 0x200>;
+                               interrupts = <14>;
+                               status = "disabled";
+
+                               phy-mode = "utmi-wide";
+                               host-device-name = "mxc-ehci";
+                               host-device-id = <1>;
+                       };
+
+                       mxc-ehci@53f80400 {
+                               compatible = "fsl,mxc-ehci";
+                               reg = <0x53f80400 0x200>;
+                               interrupts = <16>;
+                               status = "disabled";
+                       };
+
+                       mxc-ehci@53f80600 {
+                               compatible = "fsl,mxc-ehci";
+                               reg = <0x53f80600 0x200>;
+                               interrupts = <17>;
+                               status = "disabled";
+                       };
+
+                       imx-usb-phy@53f80800 {
+                               compatible = "fsl,imx53-usb-phy", "fsl,imx-usb-phy";
+                               reg = <0x53f80800 0x200>;
+                               status = "disabled";
+                       };
+
+                       gpio1: gpio@53f84000 {
+                               compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                               reg = <0x53f84000 0x4000>;
+                               interrupts = <50 51>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio2: gpio@53f88000 {
+                               compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                               reg = <0x53f88000 0x4000>;
+                               interrupts = <52 53>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio3: gpio@53f8c000 {
+                               compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                               reg = <0x53f8c000 0x4000>;
+                               interrupts = <54 55>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio4: gpio@53f90000 {
+                               compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                               reg = <0x53f90000 0x4000>;
+                               interrupts = <56 57>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       keypad@53f94000 {
+                               compatible = "fsl,imx-keypad";
+                               reg = <0x53f94000 0x4000>;
+                               interrupts = <60>;
+                               status = "disabled";
+                       };
+
+                       wdog@53f98000 { /* WDOG1 */
+                               compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
+                               reg = <0x53f98000 0x4000>;
+                               interrupts = <58>;
+                               status = "disabled";
+                       };
+
+                       wdog@53f9c000 { /* WDOG2 */
+                               compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
+                               reg = <0x53f9c000 0x4000>;
+                               interrupts = <59>;
+                               status = "disabled";
+                       };
+
+                       pwm@53fb4000 {
+                               compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+                               reg = <0x53fb4000 0x4000>;
+                               interrupts = <61>;
+                               status = "disabled";
+                       };
+
+                       pwm@53fb8000 {
+                               compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+                               reg = <0x53fb8000 0x4000>;
+                               interrupts = <94>;
+                               status = "disabled";
+                       };
+
+                       uart1: uart@53fbc000 {
+                               compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                               reg = <0x53fbc000 0x4000>;
+                               interrupts = <31>;
+                               status = "disabled";
+                       };
+
+                       uart2: uart@53fc0000 {
+                               compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                               reg = <0x53fc0000 0x4000>;
+                               interrupts = <32>;
+                               status = "disabled";
+                       };
+
+                       can1: flexcan@53fc8000 {
+                               compatible = "fsl,p1010-flexcan";
+                               reg = <0x53fc8000 0x4000>;
+                               interrupts = <82>;
+                               status = "disabled";
+                       };
+
+                       can2: flexcan@53fcc000 {
+                               compatible = "fsl,p1010-flexcan";
+                               reg = <0x53fcc000 0x4000>;
+                               interrupts = <83>;
+                               status = "disabled";
+                       };
+
+                       gpio5: gpio@53fdc000 {
+                               compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                               reg = <0x53fdc000 0x4000>;
+                               interrupts = <103 104>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio6: gpio@53fe0000 {
+                               compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                               reg = <0x53fe0000 0x4000>;
+                               interrupts = <105 106>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio7: gpio@53fe4000 {
+                               compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                               reg = <0x53fe4000 0x4000>;
+                               interrupts = <107 108>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+/*
+                       gpio: gpio@0 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               gpio1: gpio@53f84000 {
+                                       compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                       reg = <0x53f84000 0x4000>;
+                                       interrupts = <50 51>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
+                               gpio2: gpio@53f88000 {
+                                       compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                       reg = <0x53f88000 0x4000>;
+                                       interrupts = <52 53>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
+
+                               gpio3: gpio@53f8c000 {
+                                       compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                       reg = <0x53f8c000 0x4000>;
+                                       interrupts = <54 55>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
+
+                               gpio4: gpio@53f90000 {
+                                       compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                       reg = <0x53f90000 0x4000>;
+                                       interrupts = <56 57>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
+                               gpio5: gpio@53fdc000 {
+                                       compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                       reg = <0x53fdc000 0x4000>;
+                                       interrupts = <103 104>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
+
+                               gpio6: gpio@53fe0000 {
+                                       compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                       reg = <0x53fe0000 0x4000>;
+                                       interrupts = <105 106>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
+
+                               gpio7: gpio@53fe4000 {
+                                       compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                       reg = <0x53fe4000 0x4000>;
+                                       interrupts = <107 108>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                               };
+                       };
+*/
+                       i2c@53fec000 { /* I2C3 */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                               reg = <0x53fec000 0x4000>;
+                               interrupts = <64>;
+                               status = "disabled";
+                       };
+
+                       uart4: uart@53ff0000 {
+                               compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                               reg = <0x53ff0000 0x4000>;
+                               interrupts = <13>;
+                               status = "disabled";
+                       };
+               };
+
+               aips@60000000 { /* AIPS2 */
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x60000000 0x10000000>;
+                       ranges;
+
+                       uart5: uart@63f90000 {
+                               compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                               reg = <0x63f90000 0x4000>;
+                               interrupts = <86>;
+                               status = "disabled";
+                       };
+
+                       ecspi@63fac000 { /* ECSPI2 */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
+                               reg = <0x63fac000 0x4000>;
+                               interrupts = <37>;
+                               status = "disabled";
+                       };
+
+                       sdma@63fb0000 {
+                               compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
+                               reg = <0x63fb0000 0x4000>;
+                               interrupts = <6>;
+                       };
+
+                       cspi@63fc0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
+                               reg = <0x63fc0000 0x4000>;
+                               interrupts = <38>;
+                               status = "disabled";
+                       };
+
+                       i2c@63fc4000 { /* I2C2 */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                               reg = <0x63fc4000 0x4000>;
+                               interrupts = <63>;
+                               status = "disabled";
+                       };
+
+                       i2c@63fc8000 { /* I2C1 */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                               reg = <0x63fc8000 0x4000>;
+                               interrupts = <62>;
+                               status = "disabled";
+                       };
+
+                       ssi1: ssi@63fcc000 {
+                               compatible = "fsl,imx-ssi";
+                               reg = <0x63fcc000 0x4000>;
+                               interrupts = <29>;
+                               status = "disabled";
+                       };
+
+                       audmux@63fd0000 {
+                               compatible = "fsl,imx31-audmux";
+                               reg = <0x63fd0000 0x4000>;
+                               ssi-ports = <0 1 2>;
+                               ext-ports = <3 4 5 6>;
+                               status = "disabled";
+                       };
+
+                       nand@63fdb000 {
+                               compatible = "fsl,imx53-nand", "mxc_nand";
+                               reg = <0xf7ff0000 0x10000>, <0x63fdb000 0x4000>;
+                               interrupts = <8>;
+                               status = "disabled";
+                       };
+
+                       ssi3: ssi@63fe8000 {
+                               compatible = "fsl,imx-ssi";
+                               reg = <0x63fe8000 0x4000>;
+                               interrupts = <96>;
+                               status = "disabled";
+                       };
+
+                       ethernet@63fec000 {
+                               compatible = "fsl,imx53-fec", "fsl,imx25-fec";
+                               reg = <0x63fec000 0x4000>;
+                               interrupts = <87>;
+                               status = "disabled";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
new file mode 100644 (file)
index 0000000..4361cd6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
@@ -0,0 +1,1219 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc..
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_IOMUX_MX53_H__
+#define __MACH_IOMUX_MX53_H__
+
+#include "iomux-v3.h"
+
+/* These 2 defines are for pins that may not have a mux register, but could
+ * have a pad setting register, and vice-versa. */
+#define __NA_  0x00
+
+#define MX53_UART_PAD_CTRL             (PAD_CTL_PKE | PAD_CTL_PUE |    \
+               PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+                               PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
+                               PAD_CTL_SRE_FAST)
+
+
+#define MX53_PAD_GPIO_19__KPP_COL_5                    IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__GPIO4_5                      IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__CCM_CLKO                     IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SPDIF_OUT1                   IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2         IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__ECSPI1_RDY                   IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__FEC_TDATA_3                  IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT                 IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__KPP_COL_0                   IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__GPIO4_6                     IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC             IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX               IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK                 IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3                 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST              IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0                   IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__GPIO4_7                     IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD             IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX               IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI                 IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER                   IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__KPP_COL_1                   IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__GPIO4_8                     IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS            IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX               IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO                 IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK                  IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY             IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1                   IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__GPIO4_9                     IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD             IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX               IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0                  IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__FEC_COL                     IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID             IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__KPP_COL_2                   IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__GPIO4_10                    IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN                  IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_MDIO                    IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1                  IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2                 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE            IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2                   IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__GPIO4_11                    IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN                  IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_MDC                     IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2                  IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2                 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR             IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__KPP_COL_3                   IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__GPIO4_12                    IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP                        IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__SPDIF_IN1                   IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__I2C2_SCL                    IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3                  IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__FEC_CRS                     IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK            IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3                   IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__GPIO4_13                    IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM                        IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK            IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__I2C2_SDA                    IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT              IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                        IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0         IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__KPP_COL_4                   IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__GPIO4_14                    IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN                  IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__IPU_SISG_4                  IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__UART5_RTS                   IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC            IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1         IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4                   IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__GPIO4_15                    IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN                  IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5                  IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__UART5_CTS                   IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR           IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID           IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK                IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16                        IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR                IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0         IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID          IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15              IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__GPIO4_17                   IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC            IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1    IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1            IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID             IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                        IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__GPIO4_18                    IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD             IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2     IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2             IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION          IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                        IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__GPIO4_19                    IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS            IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3     IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3             IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG               IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                        IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__GPIO4_20                    IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD             IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP                   IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD            IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4             IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT      IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0           IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__GPIO4_21                  IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK                 IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0       IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN       IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5           IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY           IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1           IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__GPIO4_22                  IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI                 IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1       IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL      \
+                                                       IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6           IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID           IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2           IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__GPIO4_23                  IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO                 IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2       IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE           IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7           IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE          IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3           IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__GPIO4_24                  IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0                  IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3       IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR      IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8           IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR           IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4           IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__GPIO4_25                  IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1                  IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4       IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9           IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK          IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5           IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__GPIO4_26                  IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2                  IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5       IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS  IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10          IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0       IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6           IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__GPIO4_27                  IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3                  IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6       IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11          IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1       IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7           IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__GPIO4_28                  IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY                  IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7       IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0        IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12          IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID         IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8           IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__GPIO4_29                  IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO                 IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B              IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1        IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13          IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID            IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9           IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__GPIO4_30                  IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO                 IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B              IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2        IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14          IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0         IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10         IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__GPIO4_31                 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP         IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3       \
+                                                       IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15         IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1                IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11         IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__GPIO5_5                  IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT         IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4       \
+                                                       IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16         IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2                IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12         IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__GPIO5_6                  IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK         IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5       \
+                                                       IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17         IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3                IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13         IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__GPIO5_7                  IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS         IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0       \
+                                                       IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18         IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4                IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14         IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__GPIO5_8                  IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC          IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1       \
+                                                       IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19         IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5                IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15         IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__GPIO5_9                  IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1               IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1               IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2       \
+                                                       IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20         IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6                IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16         IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__GPIO5_10                 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI              IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC          IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0         IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3       \
+                                                       IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21         IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7                IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17         IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__GPIO5_11                 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO              IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD          IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1         IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4       \
+                                                       IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22         IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18         IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__GPIO5_12                 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0               IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS         IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS         IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5       \
+                                                       IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23         IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2            IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19         IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__GPIO5_13                 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK              IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD          IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC          IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6       \
+                                                       IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24         IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3            IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20         IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__GPIO5_14                 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK              IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC          IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7       \
+                                                       IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25         IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI             IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21         IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__GPIO5_15                 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI              IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD          IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0  IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26         IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO             IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22         IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__GPIO5_16                 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO              IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS         IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1  IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27         IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK             IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23         IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__GPIO5_17                 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0               IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD          IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2  IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28         IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS             IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK          IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18                 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0          IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29         IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC             IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__GPIO5_19                   IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK              IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1            IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30           IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL                 IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN                IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20                        IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2         IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31                IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK              IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC            IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21                  IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3           IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32          IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0              IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4               IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__GPIO5_22                   IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5                  IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                        IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP           IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC            IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33           IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1               IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5               IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__GPIO5_23                   IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5                  IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                        IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT           IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD            IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34           IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2               IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6               IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__GPIO5_24                   IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6                  IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO                        IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK           IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS           IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35           IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3               IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7               IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__GPIO5_25                   IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6                  IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0                 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR           IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD            IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36           IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4               IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8               IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__GPIO5_26                   IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7                  IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                        IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC            IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA                   IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37           IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5               IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9               IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__GPIO5_27                   IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7                  IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                        IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR           IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL                   IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38           IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6               IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10             IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__GPIO5_28                  IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX             IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO               IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC           IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4           IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39          IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7              IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11             IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__GPIO5_29                  IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX             IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0                        IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS          IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5           IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40          IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8              IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12             IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__GPIO5_30                  IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX             IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0       IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6           IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41          IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9              IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13             IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__GPIO5_31                  IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX             IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1       IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7           IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42          IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10             IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14             IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__GPIO6_0                   IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX             IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2       IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8           IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43          IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11             IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15             IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__GPIO6_1                   IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX             IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3       IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9           IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44          IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12             IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16             IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__GPIO6_2                   IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__UART4_RTS                 IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4       IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10          IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45          IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13             IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17             IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__GPIO6_3                   IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__UART4_CTS                 IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5       IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11          IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46          IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14             IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18             IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__GPIO6_4                   IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__UART5_RTS                 IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6       IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12          IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47          IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15             IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19             IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__GPIO6_5                   IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__UART5_CTS                 IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7       IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13          IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48          IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK            IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25                        IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__GPIO5_2                      IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__ECSPI2_RDY                   IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12                        IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__CSPI_SS1                     IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS                        IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK               IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                        IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__GPIO2_30                     IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK              IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS             IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0                   IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__I2C2_SCL                     IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16                        IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__GPIO3_16                     IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5                 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK           IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK                  IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__I2C2_SDA                     IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17                        IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__GPIO3_17                     IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6                 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN           IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__ECSPI1_MISO                  IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__I2C3_SCL                     IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18                        IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__GPIO3_18                     IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7                 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO           IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI                  IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__I2C3_SDA                     IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS                        IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19                        IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__GPIO3_19                     IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8                 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS            IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__ECSPI1_SS1                   IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__EPIT1_EPITO                  IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__UART1_CTS                    IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC              IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20                        IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__GPIO3_20                     IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16                        IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS             IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__CSPI_SS0                     IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__EPIT2_EPITO                  IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__UART1_RTS                    IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR             IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21                        IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__GPIO3_21                     IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17                        IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK           IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__CSPI_SCLK                    IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__I2C1_SCL                     IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC             IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22                        IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__GPIO3_22                     IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1                 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN           IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__CSPI_MISO                    IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR            IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23                        IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__GPIO3_23                     IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__UART3_CTS                    IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D23__UART1_DCD                    IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS                        IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2                 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN             IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14                        IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                        IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__GPIO2_31                     IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__UART3_RTS                    IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__UART1_RI                     IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3                 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC               IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16                        IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24                        IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__GPIO3_24                     IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX                        IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D24__ECSPI1_SS2                   IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__CSPI_SS2                     IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS             IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__ECSPI2_SS2                   IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__UART1_DTR                    IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25                        IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__GPIO3_25                     IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX                        IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D25__ECSPI1_SS3                   IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__CSPI_SS3                     IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC              IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__ECSPI2_SS3                   IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__UART1_DSR                    IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26                        IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__GPIO3_26                     IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX                        IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D26__FIRI_RXD                     IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1                 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11                        IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_SISG_2                   IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22             IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27                        IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__GPIO3_27                     IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX                        IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D27__FIRI_TXD                     IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0                 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13                        IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_SISG_3                   IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23             IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28                        IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__GPIO3_28                     IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__UART2_CTS                    IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO           IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__CSPI_MOSI                    IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__I2C1_SDA                     IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG                 IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13                        IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29                        IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__GPIO3_29                     IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__UART2_RTS                    IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS            IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__CSPI_SS0                     IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15                        IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC               IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14                        IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30                        IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__GPIO3_30                     IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__UART3_CTS                    IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3                 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11                        IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21             IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC              IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC              IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31                        IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__GPIO3_31                     IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__UART3_RTS                    IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2                 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12                        IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20             IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR             IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR             IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24                        IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__GPIO5_4                      IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19             IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19                        IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_SISG_2                   IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID               IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23                        IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__GPIO6_6                      IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18             IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18                        IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_SISG_3                   IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION           IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22                        IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__GPIO2_16                     IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17             IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17                        IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7                        IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21                        IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__GPIO2_17                     IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16             IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16                        IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6                        IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20                        IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__GPIO2_18                     IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15             IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15                        IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5                        IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19                        IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__GPIO2_19                     IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14             IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14                        IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4                        IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18                        IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__GPIO2_20                     IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13             IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13                        IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3                        IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17                        IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__GPIO2_21                     IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12             IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12                        IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2                        IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16                        IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__GPIO2_22                     IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK             IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK              IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1                        IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                        IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__GPIO2_23                     IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK                  IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5                 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                        IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__GPIO2_24                     IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI                  IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6                 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE                   IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__GPIO2_25                      IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__ECSPI2_MISO                   IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7                  IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG                 IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW                   IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__GPIO2_26                      IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__ECSPI2_SS0                    IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8                  IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT                IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA                 IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__GPIO2_27                     IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1                   IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17                        IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                        IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                        IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPIO2_28                     IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11             IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11                        IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY                 IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                        IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                        IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__GPIO2_29                     IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10             IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10                        IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                        IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0           IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__GPIO3_0                      IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9              IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9                 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                        IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1           IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__GPIO3_1                      IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8              IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8                 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                        IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2           IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__GPIO3_2                      IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7              IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7                 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                        IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3           IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__GPIO3_3                      IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6              IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6                 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                        IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4           IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__GPIO3_4                      IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5              IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5                 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                        IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5           IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__GPIO3_5                      IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4              IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4                 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                        IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6           IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__GPIO3_6                      IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3              IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3                 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                        IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7           IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__GPIO3_7                      IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2              IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2                 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                        IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8           IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__GPIO3_8                      IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1              IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1                 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                        IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9           IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__GPIO3_9                      IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0              IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0                 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                        IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10         IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__GPIO3_10                    IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15               IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN            IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1               IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11         IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__GPIO3_11                    IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2                        IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC              IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12         IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__GPIO3_12                    IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3                        IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC              IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13         IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__GPIO3_13                    IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS               IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK             IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14         IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__GPIO3_14                    IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS               IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK             IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15         IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__GPIO3_15                    IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1                        IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4                        IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B            IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__GPIO6_12                  IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B            IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__GPIO6_13                  IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT               IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__GPIO5_0                     IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B            IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22                 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3            IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24                 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2            IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26                 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK            IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28                 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1            IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30                 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0            IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22                 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3            IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24                 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK            IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26                 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2            IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28                 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1            IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30                 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0            IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__GPIO4_0                      IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT               IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_11__GPIO4_1                      IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_12__GPIO4_2                      IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_13__GPIO4_3                      IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_14__GPIO4_4                      IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE              IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__GPIO6_7                    IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0          IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE              IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__GPIO6_8                    IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1          IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B            IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__GPIO6_9                   IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2         IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0             IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__GPIO6_10                   IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3          IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0             IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__GPIO6_11                   IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4          IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1             IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__GPIO6_14                   IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK                 IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5          IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2             IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__GPIO6_15                   IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0                 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0                  IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE               IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK              IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG                 IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6          IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3             IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__GPIO6_16                   IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1                 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1                  IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26              IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT                 IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7          IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__FEC_MDIO                    IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__GPIO1_22                    IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR                  IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__FEC_COL                     IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2              IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3     IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49            IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK               IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23                 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR                        IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4  IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50         IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER                  IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__GPIO1_24                   IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR                 IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK                 IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3             IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV                 IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25                  IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                        IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1                 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__GPIO1_26                    IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__ESAI1_FST                   IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG                  IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1              IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0                 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__GPIO1_27                    IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT                  IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT              IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN                  IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__GPIO1_28                   IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2              IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1                 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__GPIO1_29                    IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3               IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK                  IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK         IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0                 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__GPIO1_30                    IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1               IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0           IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__FEC_MDC                      IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__GPIO1_31                     IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                        IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT                   IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG       IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1            IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__PATA_DIOW                  IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__GPIO6_17                   IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX              IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2          IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__PATA_DMACK                        IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__GPIO6_18                  IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX             IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3         IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ                        IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__GPIO7_0                   IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX             IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0             IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4         IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN                IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1               IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX         IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1         IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5     IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ                        IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__GPIO7_2                   IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__UART2_CTS                 IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN                        IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2             IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6         IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__PATA_DIOR                  IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__GPIO7_3                    IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__UART2_RTS                  IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN                 IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7          IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B       IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__GPIO7_4                 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD              IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__UART1_CTS               IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN              IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0       IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__PATA_IORDY                        IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__GPIO7_5                   IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK                        IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__UART1_RTS                 IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN                        IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1         IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__PATA_DA_0                  IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__GPIO7_6                    IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST                 IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE                 IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2          IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__PATA_DA_1                  IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__GPIO7_7                    IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD                 IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__UART3_CTS                  IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3          IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__PATA_DA_2                  IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__GPIO7_8                    IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK                 IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__UART3_RTS                  IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4          IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__PATA_CS_0                  IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__GPIO7_9                    IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX              IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5          IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__PATA_CS_1                  IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__GPIO7_10                   IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX              IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6          IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0               IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__GPIO2_0                   IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0             IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4               IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0     IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0            IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7         IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1               IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__GPIO2_1                   IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1             IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5               IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1     IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1            IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2               IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__GPIO2_2                   IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2             IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6               IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2     IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2            IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3               IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__GPIO2_3                   IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3             IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7               IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3     IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3            IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4               IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__GPIO2_4                   IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4             IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4               IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4     IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4            IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5               IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__GPIO2_5                   IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5             IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5               IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5     IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5            IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6               IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__GPIO2_6                   IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6             IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6               IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6     IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6            IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7               IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__GPIO2_7                   IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7             IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7               IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7     IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7            IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8               IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__GPIO2_8                   IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4               IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8             IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0               IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8     IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8            IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9               IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__GPIO2_9                   IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5               IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9             IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1               IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9     IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9            IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10             IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__GPIO2_10                 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6              IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10           IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2              IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10   IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10          IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11             IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__GPIO2_11                 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7              IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11           IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3              IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11   IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11          IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12             IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__GPIO2_12                 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4              IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12           IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0              IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12   IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12          IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13             IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__GPIO2_13                 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5              IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13           IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1              IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13   IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13          IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14             IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__GPIO2_14                 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6              IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14           IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2              IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14   IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14          IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15             IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__GPIO2_15                 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7              IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15           IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3              IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15   IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15          IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0                        IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPIO1_16                   IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1                 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__CSPI_MISO                  IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP               IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1                        IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPIO1_17                   IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2                 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__CSPI_SS0                   IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP               IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD                   IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPIO1_18                     IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1                  IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__CSPI_MOSI                    IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP                 IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2                        IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPIO1_19                   IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2                        IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO                  IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B               IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__CSPI_SS1                   IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB       IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP               IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK                   IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPIO1_20                     IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT               IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPT_CLKIN                    IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__CSPI_SCLK                    IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0               IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3                        IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPIO1_21                   IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3                        IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO                  IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B               IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__CSPI_SS2                   IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB       IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1             IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK                   IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__GPIO1_10                     IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__KPP_COL_5                    IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS             IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__CSPI_SCLK                    IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V                 IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD                   IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__GPIO1_11                     IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__KPP_ROW_5                    IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC              IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__CSPI_MOSI                    IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__SCC_RANDOM                   IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3                        IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__GPIO1_12                   IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__KPP_COL_6                  IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC            IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__CSPI_SS2                   IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__SJC_DONE                   IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2                        IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__GPIO1_13                   IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6                  IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD            IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__CSPI_SS1                   IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__SJC_FAIL                   IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1                        IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__GPIO1_14                   IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__KPP_COL_7                  IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS           IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__CSPI_SS0                   IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO               IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0                        IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__GPIO1_15                   IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7                  IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD            IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__CSPI_MISO                  IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT              IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CCM_CLKO                      IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__GPIO1_0                       IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__KPP_COL_5                     IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK              IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__EPIT1_EPITO                   IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB                        IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR              IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CSU_TD                                IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__ESAI1_SCKR                    IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__GPIO1_1                       IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__KPP_ROW_5                     IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK              IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__PWM2_PWMO                     IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B                  IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__ESDHC1_CD                     IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK                        IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__ESAI1_FSR                     IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__GPIO1_9                       IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__KPP_COL_6                     IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B                  IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__PWM1_PWMO                     IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B                  IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__ESDHC1_WP                     IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE                        IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__ESAI1_HCKR                    IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__GPIO1_3                       IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__I2C3_SCL                      IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                        IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__CCM_CLKO2                     IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0    IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC               IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__MLB_MLBCLK                    IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__ESAI1_SCKT                    IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__GPIO1_6                       IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__I2C3_SDA                      IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0                 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB               IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1    IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL                   IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__MLB_MLBSIG                    IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__ESAI1_FST                     IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__GPIO1_2                       IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__KPP_ROW_6                     IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1                 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0           IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2    IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__ESDHC2_WP                     IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__MLB_MLBDAT                    IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__ESAI1_HCKT                    IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__GPIO1_4                       IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__KPP_COL_7                     IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2                 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1           IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3    IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__ESDHC2_CD                     IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE                 IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3                 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__GPIO1_5                       IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__KPP_ROW_7                     IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CCM_CLKO                      IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2           IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4    IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__I2C3_SCL                      IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP                  IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1                 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__GPIO1_7                       IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__EPIT1_EPITO                   IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__CAN1_TXCAN                    IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX                 IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_GPIO_7__FIRI_RXD                      IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK                   IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP                  IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__GPIO1_8                       IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__EPIT2_EPITO                   IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__CAN1_RXCAN                    IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX                 IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
+#define MX53_PAD_GPIO_8__FIRI_TXD                      IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK                   IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP                  IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2                        IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__GPIO7_11                     IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT             IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1         IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__SPDIF_IN1                    IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__I2C3_SDA                     IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__SJC_DE_B                     IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__ESAI1_TX0                    IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPIO7_12                     IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0             IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY                 IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG          IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SPDIF_OUT1                   IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__IPU_SNOOP2                   IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT                 IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESAI1_TX1                    IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__GPIO7_13                     IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1             IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__OWIRE_LINE                   IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG       IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK             IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL                  IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST               IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
+
+#endif /* __MACH_IOMUX_MX53_H__ */

diff --git a/board/karo/dts/tx53.dts b/board/karo/dts/tx53.dts
new file mode 100644 (file)
index 0000000..7557e18
--- /dev/null
+++ b/board/karo/dts/tx53.dts
@@ -0,0 +1,374 @@
+/*
+ * Copyright 2012 <LW@KARO-electronics.de>
+ * based on imx53-qsb.dts
+ *   Copyright 2011 Freescale Semiconductor, Inc.
+ *   Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+       model = "Ka-Ro electronics TX53 module";
+       compatible = "karo,tx53", "fsl,imx53";
+
+       chosen {
+               bootargs = "init=/linuxrc console=ttymxc0,115200 root=/dev/mtdblock1 ro debug panic=1";
+       };
+
+       aliases {
+               usbh1 = &usbh1;
+               usbotg = &usbotg;
+               usbphy = &usbphy;
+       };
+
+       clocks {
+               ckih1 {
+                       clock-frequency = <0>;
+               };
+       };
+
+       soc {
+               extmc: extmc@00000000 {
+                       compatible = "fsl,extmc-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x00000000 0x40000000>;
+                       ranges;
+
+                       ipu@1e000000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx-ipuv3";
+                               reg = <0x1e000000 0x02000000>;
+                               interrupts = <10 11>;
+                               status = "disabled";
+                       };
+               };
+
+               extmc: extmc@00000000 {
+                       ipu: ipu@1e000000 {
+                               status = "okay";
+                       };
+               };
+
+               aips1: aips@50000000 { /* AIPS1 */
+                       spba@50000000 {
+                               mmc0: esdhc@50004000 { /* ESDHC1 */
+                                       cd-gpios = <&gpio3 24 0>;
+                                       fsl,wp-controller;
+                                       status = "okay";
+                               };
+
+                               mmc1: esdhc@50008000 { /* ESDHC2 */
+                                       cd-gpios = <&gpio3 25 0>;
+                                       status = "okay";
+                               };
+
+                               uart3: uart@5000c000 {
+                                       status = "okay";
+                                       fsl,uart-has-rtscts;
+                               };
+
+                               spi0: ecspi@50010000 { /* ECSPI1 */
+                                       fsl,spi-num-chipselects = <2>;
+                                       cs-gpios = <&gpio2 30 0 &gpio3 19 0>;
+                                       status = "okay";
+
+                                       spidev0: spi@0 {
+                                               compatible = "spidev";
+                                               reg = <0>;
+                                               spi-max-frequency = <54000000>;
+                                       };
+                               };
+                       };
+
+                       usbotg: imxotg@53f80000 {
+                               status = "okay";
+
+                               ignore-overcurrent;
+                               enable-wakeup;
+                               vbus-gpio = <&usbotg_vbus>;
+                       };
+
+                       usbh1: imxotg@53f80200 {
+                               status = "okay";
+
+                               ignore-overcurrent;
+                               enable-wakeup;
+                               vbus-gpio = <&usbh1_vbus>;
+                       };
+
+                       usbphy: imx-usb-phy@53f80800 {
+                               status = "okay";
+
+                               device-ports = <&usbotg>;
+                               host-ports = <&usbotg &usbh1>;
+                       };
+
+                       keypad@53f94000 {
+                               status = "okay";
+                               /* sample keymap */
+                               /* row/col 0,1 are mapped to KPP row/col 6,7 */
+                               linux,keymap = < 0x06060074 /* row 6, col 6, KEY_POWER */
+                                                0x06070052 /* row 6, col 7, KEY_KP0 */
+                                                0x0602004f /* row 6, col 2, KEY_KP1 */
+                                                0x06030050 /* row 6, col 3, KEY_KP2 */
+                                                0x07060051 /* row 7, col 6, KEY_KP3 */
+                                                0x0707004b /* row 7, col 7, KEY_KP4 */
+                                                0x0702004c /* row 7, col 2, KEY_KP5 */
+                                                0x0703004d /* row 7, col 3, KEY_KP6 */
+                                                0x02060047 /* row 2, col 6, KEY_KP7 */
+                                                0x02070048 /* row 2, col 7, KEY_KP8 */
+                                                0x02020049 /* row 2, col 2, KEY_KP9 */
+                                                >;
+                       };
+
+                       wdog@53f98000 { /* WDOG1 */
+                               status = "okay";
+                       };
+
+                       iomuxc@53fa8000 {
+                               compatible = "fsl,imx53-iomuxc-tx53";
+                               reg = <0x53fa8000 0x4000>;
+                       };
+
+                       pwm2: pwm@53fb8000 {
+                               status = "okay";
+                       };
+
+                       uart1: uart@53fbc000 {
+                               status = "okay";
+                               fsl,uart-has-rtscts;
+                       };
+
+                       uart2: uart@53fc0000 {
+                               status = "okay";
+                               fsl,uart-has-rtscts;
+                       };
+
+                       can1: flexcan@53fc8000 {
+                               status = "okay";
+                               transceiver-switch = <&flexcan_transceiver>;
+                       };
+
+                       can2: flexcan@53fcc000 {
+                               status = "okay";
+                               transceiver-switch = <&flexcan_transceiver>;
+                       };
+
+                       i2c@53fec000 { /* I2C3 */
+                               status = "okay";
+
+                               codec: sgtl5000@0a {
+                                       compatible = "fsl,sgtl5000";
+                                       reg = <0x0a>;
+                                       VDDA-supply = <&reg_2p5v>;
+                                       VDDIO-supply = <&reg_3p3v>;
+                               };
+
+                               touchscreen: tsc2007@48 {
+                                       compatible = "ti,tsc2007";
+                                       reg = <0x48>;
+                                       interrupt-parent = <&gpio3>;
+                                       interrupts = <26 0>;
+                                       pendown-gpio = <&gpio3 26 1>;
+                                       model = "2007";
+                                       x-plate-ohms = <660>;
+                               };
+
+                               polytouch: edt-ft5x06@ {
+                                       compatible = "edt,edt-ft5x06";
+                                       reg = <0x38>;
+                                       interrupt-parent = <&gpio6>;
+                                       interrupts = <15>;
+                                       reset-switch = <&edt_ft5x06_reset>;
+                                       wake-switch = <&edt_ft5x06_wake>;
+                               };
+                       };
+               };
+
+               aips2: aips@60000000 {  /* AIPS2 */
+
+                       sdma@63fb0000 {
+                               fsl,sdma-ram-script-name = "sdma-imx53.bin";
+                       };
+
+                       i2c@63fc8000 { /* I2C1 */
+                               status = "okay";
+
+                               rtc1: ds1339@68 {
+                                       compatible = "dallas,ds1339";
+                                       reg = <0x68>;
+                                       trickle-charge = <0xa5>;
+/**/
+                                       interrupt-parent = <&gpio4>;
+                                       interrupts = <20 0>;
+/**/
+                               };
+
+                               pmic: lt3589@48 {
+                                       compatible = "lt,lt3589";
+                                       reg = <0x48>;
+                               };
+                       };
+
+                       ssi@63fcc000 {
+                               status = "okay";
+                               rx-dma = <28>;
+                               tx-dma = <29>;
+                               i2s-sync-mode;
+                       };
+
+                       ssi@50014000 {
+                               status = "okay";
+                       };
+
+                       audmux@63fd0000 {
+                               status = "okay";
+                       };
+
+                       sound-card@0 {
+                               compatible = "fsl,imx-sgtl5000";
+                               status = "okay";
+                               /* '1' based port numbers according to datasheet names */
+                               ssi-port = <1>;
+                               audmux-port = <5>;
+                               sysclk = <26000000>;
+                       };
+
+                       nand@63fdb000 {
+                               status = "okay";
+
+                               nand-bus-width = <8>;
+                               nand-ecc-mode = "hw";
+                               nand-on-flash-bbt;
+                       };
+
+                       ethernet@63fec000 {
+                               phy-mode = "rmii";
+                               phy-reset-gpios = <&gpio7 6 0>;
+                               status = "okay";
+                               phy-handle = <&phy0>;
+                               mac-address = [000000000000];
+
+                               phy0: ethernet-phy@0 {
+                                       interrupt-parent = <&gpio2>;
+                                       interrupts = <4>;
+                                       device_type = "ethernet-phy";
+                               };
+                       };
+               };
+       };
+
+       gpio-switch {
+               compatible = "gpio-switches", "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               flexcan_transceiver: gpio-switch@0 {
+                       compatible = "linux,gpio-switch";
+                       gpio = <&gpio4 21 1>;
+                       label = "Flexcan Transceiver Enable";
+                       gpio-shared;
+                       init-state = <0>;
+               };
+
+               lcd_power: gpio-switch@1 {
+                       compatible = "linux,gpio-switch";
+                       gpio = <&gpio2 31 0>;
+                       label = "LCD Power Enable";
+                       init-state = <0>;
+               };
+
+               lcd_reset: gpio-switch@2 {
+                       compatible = "linux,gpio-switch";
+                       gpio = <&gpio3 29 1>;
+                       label = "LCD Reset";
+                       init-state = <1>;
+               };
+
+               edt_ft5x06_reset: gpio-switch@3 {
+                       compatible = "linux,gpio-switch";
+                       gpio = <&gpio2 22 1>;
+                       label = "EDT-FT5x06 RESET";
+               };
+
+               edt_ft5x06_wake: gpio-switch@4 {
+                       compatible = "linux,gpio-switch";
+                       gpio = <&gpio2 21 0>;
+                       label = "EDT-FT5x06 WAKE";
+                       init-state = <1>;
+               };
+
+               usbotg_vbus: gpio-switch@5 {
+                       compatible = "linux,gpio-switch";
+                       gpio = <&gpio1 7 0>;
+                       label = "USBOTG VBUS";
+               };
+
+               usbh1_vbus: gpio-switch@6 {
+                       compatible = "linux,gpio-switch";
+                       gpio = <&gpio3 31 0>;
+                       label = "USBH1 VBUS";
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               user {
+                       label = "Heartbeat";
+                       gpios = <&gpio2 20 0>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       lcd {
+               compatible = "of-gpio-lcd";
+               parent = <&ipu>;
+
+               power-switch = <&lcd_power>;
+/*
+               reset-switch = <&lcd_reset>;
+               reset-delay-us = <300>;
+*/
+       };
+
+       backlight: pwm-backlight {
+               compatible = "pwm-backlight";
+
+               pwm = <&pwm2>;
+               inverted;
+               max-brightness = <100>;
+               dft-brightness = <50>;
+               pwm-period-ns = <1000000>;
+       };
+
+       regulators {
+               compatible = "simple-bus";
+
+               reg_2p5v: 2p5v {
+                       compatible = "regulator-fixed";
+                       regulator-name = "2P5V";
+                       regulator-min-microvolt = <2500000>;
+                       regulator-max-microvolt = <2500000>;
+                       regulator-always-on;
+               };
+
+               reg_3p3v: 3p3v {
+                       compatible = "regulator-fixed";
+                       regulator-name = "3P3V";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+               };
+       };
+};

diff --git a/board/karo/tx53/Makefile b/board/karo/tx53/Makefile
new file mode 100644 (file)
index 0000000..3c10666
--- /dev/null
+++ b/board/karo/tx53/Makefile
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT := $(BOARDDIR)/u-boot.lds
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := tx53.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/karo/tx53/config.mk b/board/karo/tx53/config.mk
new file mode 100644 (file)
index 0000000..e765c3a
--- /dev/null
+++ b/board/karo/tx53/config.mk
@@ -0,0 +1,5 @@
+# stack is allocated below CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE := 0x70100000
+
+PLATFORM_CPPFLAGS += -Werror
+LOGO_BMP = logos/karo.bmp

diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S
new file mode 100644 (file)
index 0000000..c7cf769
--- /dev/null
+++ b/board/karo/tx53/lowlevel_init.S
@@ -0,0 +1,484 @@
+#include <config.h>
+#include <configs/tx53.h>
+#include <asm/arch/imx-regs.h>
+
+#define DEBUG_LED_BIT                  20
+#define LED_GPIO_BASE                  GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET                 0x174
+#define LED_MUX_MODE                   0x11
+
+#define DCDGEN(type, addr, data)  .long type, addr, data
+
+#define SDRAM_CLK              CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE             (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE             PHYS_SDRAM_1_SIZE
+#endif
+
+//#define ESDCTL_BASE_ADDR     0x63fd9000
+#define REG_ESDCTL0            0x00
+#define REG_ESDCFG0            0x04
+#define REG_ESDCTL1            0x08
+#define REG_ESDCFG1            0x0c
+#define REG_ESDMISC            0x10
+#define REG_ESDSCR             0x14
+#define REG_ESDGPR             0x34
+
+//#define IOMUXC_BASE_ADDR     0x53fa8000
+
+#define CPU_2_BE_32(l)                 \
+       ((((l) << 24) & 0xFF000000) |   \
+       (((l) << 8) & 0x00FF0000) |     \
+       (((l) >> 8) & 0x0000FF00) |     \
+       (((l) >> 24) & 0x000000FF))
+
+#define MXC_DCD_ITEM(addr, val)                \
+       .word   CPU_2_BE_32(addr), CPU_2_BE_32(val)
+
+#define MXC_DCD_CMD_SZ_BYTE            1
+#define MXC_DCD_CMD_SZ_SHORT           2
+#define MXC_DCD_CMD_SZ_WORD            4
+#define MXC_DCD_CMD_FLAG_WRITE         0x0
+#define MXC_DCD_CMD_FLAG_CLR           0x1
+#define MXC_DCD_CMD_FLAG_SET           0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY       (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET       (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR       (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next)                                     \
+       .word   CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask)                               \
+       .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+               CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)                    \
+       .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+               CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP()                                                      \
+       .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck)   (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)
+
+       .macro          CK_VAL, name, clks, offs, max
+       .iflt           \clks - \offs
+       .set            \name, 0
+       .else
+       .ifle           \clks - \offs - \max
+       .set            \name, \clks - \offs
+       .endif
+       .endif
+       .endm
+
+       .macro          NS_VAL, name, ns, offs, max
+       .iflt           \ns - \offs
+       .set            \name, 0
+       .else
+       CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
+       .endif
+       .endm
+
+       .macro          CK_MAX, name, ck1, ck2, offs, max
+       .ifgt           \ck1 - \ck2
+       CK_VAL          \name, \ck1, \offs, \max
+       .else
+       CK_VAL          \name, \ck2, \offs, \max
+       .endif
+       .endm
+
+#define ESDMISC_DDR_TYPE_DDR3          0
+#define ESDMISC_DDR_TYPE_LPDDR2                1
+#define ESDMISC_DDR_TYPE_DDR2          2
+
+#define DIV_ROUND_UP(m,d)              (((m) + (d) - 1) / (d))
+
+#define CKIL_FREQ_Hz                   32768
+#define ESDOR_CLK_PERIOD_ns            (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > RAM_BANK0_SIZE
+#define BANK_ADDR_BITS                 2
+#else
+#define BANK_ADDR_BITS                 1
+#endif
+#define SDRAM_BURST_LENGTH             8
+#define RALAT                          5
+#define WALAT                          1
+#define ADDR_MIRROR                    0
+#define DDR_TYPE                       ESDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* ESDCFG0 0x0c */
+NS_VAL tRFC,   160, 1, 255             /* clks - 1 (0..255) */
+CK_MAX tXS,    tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP,    3, NS_TO_CK(6), 1, 7    /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
+NS_VAL tFAW,   45, 1, 31               /* clks - 1 (0..31) */
+CK_VAL tCL,    9, 3, 8                 /* clks - 3 (0..8) CAS Latency */
+
+/* ESDCFG1 0x10 */
+NS_VAL tRCD,   14, 1, 7                /* clks - 1 (0..7) */
+NS_VAL tRP,    14, 1, 7                /* clks - 1 (0..7) */
+NS_VAL tRC,    50, 1, 31               /* clks - 1 (0..31) */
+NS_VAL tRAS,   36, 1, 31               /* clks - 1 (0..31) */
+CK_VAL tRPA,   0, 0, 1                 /* clks     (0..1) */
+NS_VAL tWR,    15, 1, 15               /* clks - 1 (0..15) */
+CK_VAL tMRD,   4, 1, 15                /* clks - 1 (0..15) */
+CK_VAL tCWL,   5, 2, 6                 /* clks - 2 (0..6) */
+
+/* ESDCFG2 0x14 */
+CK_VAL tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
+CK_MAX tRTP,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
+CK_MAX tWTR,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
+CK_MAX tRRD,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
+
+/* ESDOR 0x30 */
+CK_MAX tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+
+/* ESDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7                 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7                 /* clks - 1 (0..7) */
+CK_VAL tANPD,  tCWL, 1, 15             /* clks - 1 (0..15) */
+CK_VAL tAXPD,  tCWL, 1, 15             /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL - 1, 1, 7          /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL - 1, 1, 31        /* clks - 1 (0..31) */
+
+#define tSDE_RST                       (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
+
+                                       /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
+                                        * erroneous Erratum Engcm12377
+                                        */
+#define tRST_CKE                       (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
+
+#define ROW_ADDR_BITS                  14
+#define COL_ADDR_BITS                  10
+
+       .iflt   tWR - 7
+       .set    mrs_val, (0x8080 | \
+                       (3 << 4) /* MRS command */ | \
+                       ((1 << 8) /* DLL Reset */ | \
+                       ((tWR + 1 - 4) << 9) | \
+                       (((tCL + 3) - 4) << 4)) << 16)
+       .else
+       .set    mrs_val, (0x8080 | \
+                       (3 << 4) /* MRS command */ | \
+                       ((1 << 8) /* DLL Reset */ | \
+                       (((tWR + 1) / 2) << 9) | \
+                       (((tCL + 3) - 4) << 4)) << 16)
+       .endif
+#define ESDSCR_MRS_VAL(cs)     (mrs_val | ((cs) << 3))
+
+#define ESDCFG0_VAL    (               \
+       (tRFC << 24) |                  \
+       (tXS << 16) |                   \
+       (tXP << 13) |                   \
+       (tXPDLL << 9) |                 \
+       (tFAW << 4) |                   \
+       (tCL << 0))                     \
+
+#define ESDCFG1_VAL    (               \
+       (tRCD << 29) |                  \
+       (tRP << 26) |                   \
+       (tRC << 21) |                   \
+       (tRAS << 16) |                  \
+       (tRPA << 15) |                  \
+       (tWR << 9) |                    \
+       (tMRD << 5) |                   \
+       (tCWL << 0))                    \
+
+#define ESDCFG2_VAL    (               \
+       (tDLLK << 16) |                 \
+       (tRTP << 6) |                   \
+       (tWTR << 3) |                   \
+       (tRRD << 0))
+
+#define BURST_LEN                      (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define ESDCTL_VAL                     (((ROW_ADDR_BITS - 11) << 24) | \
+                                       ((COL_ADDR_BITS - 9) << 20) | \
+                                       (BURST_LEN << 19) | \
+                                       (1 << 16) | /* SDRAM bus width */ \
+                                       ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define ESDMISC_VAL                    ((1 << 12) | \
+                                       (0x3 << 9) | \
+                                       (RALAT << 6) | \
+                                       (WALAT << 16) | \
+                                       (ADDR_MIRROR << 19) | \
+                                       (DDR_TYPE << 3))
+
+#define ESDOR_VAL              ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define ESDOTC_VAL             ((tAOFPD << 27) |       \
+                               (tAONPD << 24) |        \
+                               (tANPD << 20) |         \
+                               (tAXPD << 16) |         \
+                               (tODTLon << 12) |       \
+                               (tODTLoff << 4))
+
+fcb_start:
+       b       _start
+       .word   0x20424346      /* "FCB " marker */
+       .word   0x01    /* FCB version number */
+       .org    0x68
+       .word   0x0     /* primary image starting page number */
+       .word   0x0     /* secondary image starting page number */
+       .word   0x6b
+       .word   0x6b
+       .word   0x0     /* DBBT start page (0 == NO DBBT) */
+       .word   0       /* Bad block marker offset in main area (unused) */
+       .org    0xac
+       .word   0       /* BI Swap disabled */
+       .word   0       /* Bad Block marker offset in spare area */
+fcb_end:
+
+       .org    0x400
+ivt_header:
+       .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+       .long   _start
+       .long   0x0
+dcd_ptr:
+       .long   dcd_hdr
+boot_data_ptr:
+       .word   boot_data
+self_ptr:
+       .word   ivt_header
+app_code_csf:
+       .word   0x0
+       .word   0x0
+boot_data:
+       .long   fcb_start
+image_len:
+       .long   CONFIG_U_BOOT_IMG_SIZE
+plugin:
+       .word   0
+ivt_end:
+#define DCD_VERSION    0x40
+
+#define CLKCTL_CCGR0   0x68
+#define CLKCTL_CCGR1   0x6c
+#define CLKCTL_CCGR2   0x70
+#define CLKCTL_CCGR3   0x74
+#define CLKCTL_CCGR4   0x78
+#define CLKCTL_CCGR5   0x7c
+#define CLKCTL_CCGR6   0x80
+#define CLKCTL_CCGR7   0x84
+#define CLKCTL_CMEOR   0x88
+
+dcd_hdr:
+       .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+       /* disable all irrelevant clocks */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcf0fff)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR2, 0x033c0000)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR3, 0x000000ff)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR4, 0x00000000)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR5, 0x00fff033)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR6, 0x0f00030f)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR7, 0xfff00000)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CMEOR, 0x00000000)
+
+       MXC_DCD_ITEM(IOMUXC_BASE_ADDR + LED_MUX_OFFSET, LED_MUX_MODE)   /* EIM_D18 => GPIO2[20] STK5-LED */
+       MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x318, 0x11)    /* GPIO_1 => LCD Backlight */
+
+       MXC_DCD_ITEM(0x63fd800c, 0x00000000)    /* M4IF: MUX NFC signals on WEIM */
+#if SDRAM_CLK > 333
+       MXC_DCD_ITEM(0x53fd4014, 0x00888944)    /* CBCDR */
+#else
+       MXC_DCD_ITEM(0x53fd4014, 0x00888644)    /* CBCDR */
+#endif
+       MXC_DCD_ITEM(0x53fd4018, 0x00016154)    /* CBCMR */
+
+       MXC_DCD_ITEM(0x53fd401c, 0xa6a2a020)    /* CSCMR1 */
+       MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a)    /* CSCMR2 */
+       MXC_DCD_ITEM(0x53fd4024, 0x00080b18)    /* CSCDR1 */
+
+#define DDR_SEL_VAL    2
+#define DSE_VAL                5
+#define ODT_VAL                2
+
+#define DDR_SEL_SHIFT  25
+#define ODT_SHIFT      22
+#define DSE_SHIFT      19
+#define DDR_INPUT_SHIFT        9
+#define HYS_SHIFT      8
+#define PKE_SHIFT      7
+#define PUE_SHIFT      6
+#define PUS_SHIFT      4
+
+#define DDR_SEL_MASK   (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DSE_MASK       (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK       (ODT_VAL << ODT_SHIFT)
+
+#define DQM_VAL                DSE_MASK
+#define SDQS_VAL       (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT))
+#define SDODT_VAL      (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_VAL      DSE_MASK
+#define SDCKE_VAL      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+
+       MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */
+       MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */
+       MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */
+       MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */
+       MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */
+       MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */
+
+       MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */
+       MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */
+       MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */
+       MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */
+
+       MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */
+       MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */
+       MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */
+       MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */
+
+       MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */
+       MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */
+
+       MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */
+       MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */
+
+       MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */
+       MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */
+
+       MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */
+       MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */
+
+       MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */
+       MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */
+       MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */
+       MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */
+       MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */
+       MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */
+
+       /* calibration defaults */
+       MXC_DCD_ITEM(0x63fd904c, 0x001f001f)
+       MXC_DCD_ITEM(0x63fd9050, 0x001f001f)
+       MXC_DCD_ITEM(0x63fd907c, 0x011e011e)
+       MXC_DCD_ITEM(0x63fd9080, 0x011f0120)
+       MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b)
+       MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f)
+
+       MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL)
+       MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
+       MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
+       MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
+       MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
+
+       MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
+       MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
+       MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
+       MXC_DCD_ITEM(0x63fd9004, 0x00030012)
+
+       /* MR0 - CS0 */
+       MXC_DCD_ITEM(0x63fd901c, 0x00008032) /* MRS: MR2 */
+       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: MR3 */
+       MXC_DCD_ITEM(0x63fd901c, 0x00408031) /* MRS: MR1 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0)) /* MRS: MR0 */
+       /* MR0 - CS1 */
+#if BANK_ADDR_BITS > 1
+       MXC_DCD_ITEM(0x63fd901c, 0x0000803a) /* MRS: MR2 */
+       MXC_DCD_ITEM(0x63fd901c, 0x0000803b) /* MRS: MR3 */
+       MXC_DCD_ITEM(0x63fd901c, 0x00408039) /* MRS: MR1 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1)) /* MRS: MR0 */
+#endif
+       MXC_DCD_ITEM(0x63fd9020, 0x00005800) /* refresh interval */
+       MXC_DCD_ITEM(0x63fd9058, 0x00011112)
+
+       MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
+
+       /* ZQ calibration */
+       MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+       MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
+       MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
+zq_calib:
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+
+       /* Write Leveling */
+       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd901c, 0x00848231) /* MRS: start write leveling */
+       MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+       MXC_DCD_ITEM(0x63fd9048, 0x00000001)
+wl_calib:
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+       MXC_DCD_ITEM(0x63fd901c, 0x00048031) /* MRS: end write leveling */
+       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+       /* DQS calibration */
+       MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
+dqs_calib:
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+       /* WR DL calibration */
+       MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+       MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
+wr_dl_calib: /* 6c4 */
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+       /* RD DL calibration */
+       MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
+rd_dl_calib: /* 70c */
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
+       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+       MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+
+       MXC_DCD_ITEM(0x53fa8004, 0x00194005)    @ set LDO to 1.3V
+
+       /* setup NFC pads */
+       /* MUX_SEL */
+       MXC_DCD_ITEM(0x53fa819c, 0x00000000)    @ EIM_DA0
+       MXC_DCD_ITEM(0x53fa81a0, 0x00000000)    @ EIM_DA1
+       MXC_DCD_ITEM(0x53fa81a4, 0x00000000)    @ EIM_DA2
+       MXC_DCD_ITEM(0x53fa81a8, 0x00000000)    @ EIM_DA3
+       MXC_DCD_ITEM(0x53fa81ac, 0x00000000)    @ EIM_DA4
+       MXC_DCD_ITEM(0x53fa81b0, 0x00000000)    @ EIM_DA5
+       MXC_DCD_ITEM(0x53fa81b4, 0x00000000)    @ EIM_DA6
+       MXC_DCD_ITEM(0x53fa81b8, 0x00000000)    @ EIM_DA7
+       MXC_DCD_ITEM(0x53fa81dc, 0x00000000)    @ WE_B
+       MXC_DCD_ITEM(0x53fa81e0, 0x00000000)    @ RE_B
+       MXC_DCD_ITEM(0x53fa8228, 0x00000000)    @ CLE
+       MXC_DCD_ITEM(0x53fa822c, 0x00000000)    @ ALE
+       MXC_DCD_ITEM(0x53fa8230, 0x00000000)    @ WP_B
+       MXC_DCD_ITEM(0x53fa8234, 0x00000000)    @ RB0
+       MXC_DCD_ITEM(0x53fa8238, 0x00000000)    @ CS0
+       /* PAD_CTL */
+       MXC_DCD_ITEM(0x53fa84ec, 0x000000e4)    @ EIM_DA0
+       MXC_DCD_ITEM(0x53fa84f0, 0x000000e4)    @ EIM_DA1
+       MXC_DCD_ITEM(0x53fa84f4, 0x000000e4)    @ EIM_DA2
+       MXC_DCD_ITEM(0x53fa84f8, 0x000000e4)    @ EIM_DA3
+       MXC_DCD_ITEM(0x53fa84fc, 0x000000e4)    @ EIM_DA4
+       MXC_DCD_ITEM(0x53fa8500, 0x000000e4)    @ EIM_DA5
+       MXC_DCD_ITEM(0x53fa8504, 0x000000e4)    @ EIM_DA6
+       MXC_DCD_ITEM(0x53fa8508, 0x000000e4)    @ EIM_DA7
+       MXC_DCD_ITEM(0x53fa852c, 0x00000004)    @ NANDF_WE_B
+       MXC_DCD_ITEM(0x53fa8530, 0x00000004)    @ NANDF_RE_B
+       MXC_DCD_ITEM(0x53fa85a0, 0x00000004)    @ NANDF_CLE_B
+       MXC_DCD_ITEM(0x53fa85a4, 0x00000004)    @ NANDF_ALE_B
+       MXC_DCD_ITEM(0x53fa85a8, 0x000000e4)    @ NANDF_WE_B
+       MXC_DCD_ITEM(0x53fa85ac, 0x000000e4)    @ NANDF_RB0
+       MXC_DCD_ITEM(0x53fa85b0, 0x00000004)    @ NANDF_CS0
+dcd_end:
+       .ifgt   dcd_end - dcd_start - 1768
+       DCD too large!
+       .endif

diff --git a/board/karo/tx53/tx53.c b/board/karo/tx53/tx53.c
new file mode 100644 (file)
index 0000000..8d8a275
--- /dev/null
+++ b/board/karo/tx53/tx53.c
@@ -0,0 +1,952 @@
+/*
+ * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <video_fb.h>
+#include <ipu_pixfmt.h>
+#include <mx2fb.h>
+#include <linux/fb.h>
+#include <asm/string.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+
+#define IMX_GPIO_NR(b, o)      ((((b) - 1) << 5) | (o))
+
+#define TX53_FEC_RST_GPIO      IMX_GPIO_NR(7, 6)
+#define TX53_FEC_PWR_GPIO      IMX_GPIO_NR(3, 20)
+#define TX53_FEC_INT_GPIO      IMX_GPIO_NR(2, 4)
+#define TX53_LED_GPIO          IMX_GPIO_NR(2, 20)
+
+#define TX53_LCD_PWR_GPIO      IMX_GPIO_NR(2, 31)
+#define TX53_LCD_RST_GPIO      IMX_GPIO_NR(3, 29)
+#define TX53_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(1, 1)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IOMUX_SION             IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
+
+#define MX53_GPIO_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_PUE |            \
+                               PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
+
+#define TX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_DSE_HIGH |      \
+                               PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN)
+
+static iomux_v3_cfg_t tx53_pads[] = {
+       /* UART pads */
+       MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+       MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+       MX53_PAD_PATA_IORDY__UART1_RTS,
+       MX53_PAD_PATA_RESET_B__UART1_CTS,
+
+       MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+       MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+       MX53_PAD_PATA_DIOR__UART2_RTS,
+       MX53_PAD_PATA_INTRQ__UART2_CTS,
+
+       MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+       MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
+       MX53_PAD_PATA_DA_2__UART3_RTS,
+       MX53_PAD_PATA_DA_1__UART3_CTS,
+
+       /* I2C */
+       NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL),
+
+       /* SW controlled LED on STK5 baseboard */
+       MX53_PAD_EIM_A18__GPIO2_20,
+
+       /* FEC */
+       MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
+       MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
+       MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
+
+       /* FEC functions */
+       MX53_PAD_FEC_MDC__FEC_MDC,
+       MX53_PAD_FEC_MDIO__FEC_MDIO,
+       MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+       MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+       MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+       MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+       MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+       MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+       MX53_PAD_FEC_TXD1__FEC_TDATA_1,
+       MX53_PAD_FEC_TXD0__FEC_TDATA_0,
+};
+
+static const struct gpio tx53_gpios[] = {
+       { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
+       { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
+       { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
+};
+
+/*
+ * Functions
+ */
+static u32 srsr;
+static u32 wrsr;
+
+#define WRSR_POR       (1 << 4)
+#define WRSR_TOUT      (1 << 1)
+#define WRSR_SFTW      (1 << 0)
+
+static void print_reset_cause(void)
+{
+       struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+       void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+       char *dlm = "";
+
+       printf("Reset cause: ");
+
+       srsr = readl(&src_regs->srsr);
+       wrsr = readw(wdt_base + 4);
+
+       if (wrsr & WRSR_POR) {
+               printf("%sPOR", dlm);
+               dlm = " | ";
+       }
+       if (srsr & 0x00004) {
+               printf("%sCSU", dlm);
+               dlm = " | ";
+       }
+       if (srsr & 0x00008) {
+               printf("%sIPP USER", dlm);
+               dlm = " | ";
+       }
+       if (srsr & 0x00010) {
+               if (wrsr & WRSR_SFTW) {
+                       printf("%sSOFT", dlm);
+                       dlm = " | ";
+               }
+               if (wrsr & WRSR_TOUT) {
+                       printf("%sWDOG", dlm);
+                       dlm = " | ";
+               }
+       }
+       if (srsr & 0x00020) {
+               printf("%sJTAG HIGH-Z", dlm);
+               dlm = " | ";
+       }
+       if (srsr & 0x00040) {
+               printf("%sJTAG SW", dlm);
+               dlm = " | ";
+       }
+       if (srsr & 0x10000) {
+               printf("%sWARM BOOT", dlm);
+               dlm = " | ";
+       }
+       if (dlm[0] == '\0')
+               printf("unknown");
+
+       printf("\n");
+}
+
+static void print_cpuinfo(void)
+{
+       u32 cpurev;
+
+       cpurev = get_cpu_rev();
+
+       printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
+               (cpurev & 0x000F0) >> 4,
+               (cpurev & 0x0000F) >> 0,
+               mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+       print_reset_cause();
+}
+
+int board_early_init_f(void)
+{
+       gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
+       mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
+
+       return 0;
+}
+
+void coloured_LED_init(void)
+{
+       /* Switch LED off */
+       gpio_set_value(TX53_LED_GPIO, 0);
+}
+
+int board_init(void)
+{
+       /* Address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+       return 0;
+}
+
+int dram_init(void)
+{
+       int ret;
+
+       /* dram_init must store complete ramsize in gd->ram_size */
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                               PHYS_SDRAM_1_SIZE);
+
+       ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
+               CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
+       if (ret)
+               printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
+                       CONFIG_SYS_SDRAM_CLK, ret);
+       else
+               debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
+                       __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
+                       mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
+                       CONFIG_SYS_SDRAM_CLK);
+       return ret;
+}
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+                       PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+                       PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = mmc->priv;
+
+       if (cfg->cd_gpio < 0)
+               return cfg->cd_gpio;
+
+       return !gpio_get_value(cfg->cd_gpio);
+}
+
+static struct fsl_esdhc_cfg esdhc_cfg[] = {
+       {
+               .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
+               .no_snoop = 1,
+               .cd_gpio = IMX_GPIO_NR(3, 24),
+               .wp_gpio = -EINVAL,
+       },
+       {
+               .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
+               .no_snoop = 1,
+               .cd_gpio = IMX_GPIO_NR(3, 25),
+               .wp_gpio = -EINVAL,
+       },
+};
+
+static const iomux_v3_cfg_t mmc0_pads[] = {
+       NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL),
+       /* SD1 CD */
+       NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t mmc1_pads[] = {
+       NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL),
+       /* SD2 CD */
+       NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL),
+};
+
+static struct {
+       const iomux_v3_cfg_t *pads;
+       int count;
+} mmc_pad_config[] = {
+       { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
+       { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
+};
+
+int board_mmc_init(bd_t *bis)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
+//             struct mmc *mmc;
+
+               if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
+                       break;
+               mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
+                                               mmc_pad_config[i].count);
+               fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
+#if 0
+               mmc = find_mmc_device(i);
+               if (mmc == NULL)
+                       continue;
+               if (board_mmc_getcd(mmc) > 0)
+                       mmc_init(mmc);
+#endif
+       }
+       return 0;
+}
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_FEC_MXC
+
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+       int i;
+       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+       struct fuse_bank *bank = &iim->bank[1];
+       struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
+
+       if (dev_id > 0)
+               return;
+
+       for (i = 0; i < ETH_ALEN; i++)
+               mac[i] = readl(&fuse->mac_addr[i]);
+}
+
+#define FEC_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+                       PAD_CTL_SRE_FAST)
+#define FEC_PAD_CTL2   (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+#define GPIO_PAD_CTL   (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+int board_eth_init(bd_t *bis)
+{
+       int ret;
+       unsigned char mac[ETH_ALEN];
+       char mac_str[ETH_ALEN * 3] = "";
+
+       /* delay at least 21ms for the PHY internal POR signal to deassert */
+       udelay(22000);
+       /* Deassert RESET to the external phy */
+       gpio_set_value(TX53_FEC_RST_GPIO, 1);
+
+       ret = cpu_eth_init(bis);
+       if (ret) {
+               printf("cpu_eth_init() failed: %d\n", ret);
+       }
+
+       imx_get_mac_from_fuse(0, mac);
+       snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
+               mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+       setenv("ethaddr", mac_str);
+
+       return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+enum {
+       LED_STATE_INIT = -1,
+       LED_STATE_OFF,
+       LED_STATE_ON,
+};
+
+void show_activity(int arg)
+{
+       static int led_state = LED_STATE_INIT;
+       static ulong last;
+
+       if (led_state == LED_STATE_INIT) {
+               last = get_timer(0);
+               gpio_set_value(TX53_LED_GPIO, 1);
+               led_state = LED_STATE_ON;
+       } else {
+               if (get_timer(last) > CONFIG_SYS_HZ) {
+                       last = get_timer(0);
+                       if (led_state == LED_STATE_ON) {
+                               gpio_set_value(TX53_LED_GPIO, 0);
+                       } else {
+                               gpio_set_value(TX53_LED_GPIO, 1);
+                       }
+                       led_state = 1 - led_state;
+               }
+       }
+}
+
+static const iomux_v3_cfg_t stk5_pads[] = {
+       /* SW controlled LED on STK5 baseboard */
+       MX53_PAD_EIM_A18__GPIO2_20,
+
+       /* I2C bus on DIMM pins 40/41 */
+       NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL),
+       NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL),
+
+       /* TSC200x PEN IRQ */
+       NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL),
+
+       /* EDT-FT5x06 Polytouch panel */
+       NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */
+       NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */
+       NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */
+
+       /* USBH1 */
+       NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */
+       NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */
+       /* USBOTG */
+       MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
+       MX53_PAD_GPIO_8__GPIO1_8, /* OC */
+
+       /* DS1339 Interrupt */
+       NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL),
+};
+
+static const struct gpio stk5_gpios[] = {
+       { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
+       { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
+       { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
+       { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
+       { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+};
+
+#ifdef CONFIG_LCD
+static u16 tx53_cmap[256];
+vidinfo_t panel_info = {
+       /* set to max. size supported by SoC */
+       .vl_col = 1600,
+       .vl_row = 1200,
+
+       .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+       .cmap = tx53_cmap,
+};
+
+static struct fb_videomode tx53_fb_mode = {
+       /* Standard VGA timing */
+       .name           = "VGA",
+       .refresh        = 60,
+       .xres           = 640,
+       .yres           = 480,
+       .pixclock       = KHZ2PICOS(25175),
+       .left_margin    = 48,
+       .hsync_len      = 96,
+       .right_margin   = 16,
+       .upper_margin   = 31,
+       .vsync_len      = 2,
+       .lower_margin   = 12,
+       .sync           = FB_SYNC_CLK_LAT_FALL,
+       .vmode          = FB_VMODE_NONINTERLACED,
+};
+
+void *lcd_base;                        /* Start of framebuffer memory  */
+void *lcd_console_address;     /* Start of console buffer      */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_enable(void)
+{
+       /* HACK ALERT:
+        * global variable from common/lcd.c
+        * Set to 0 here to prevent messages from going to LCD
+        * rather than serial console
+        */
+       lcd_is_enabled = 0;
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+static int lcd_enabled = 1;
+
+static inline int tx53_load_splashimage(void)
+{
+       int ret = 0;
+#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD)
+       int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]);
+       cmd_tbl_t *cmd = find_cmd("nand");
+       char *loadaddr = getenv("splashimage");
+       char *argv[] = {
+               "nand",
+               "read",
+               loadaddr,
+               "logo",
+       };
+       const int argc = ARRAY_SIZE(argv);
+       unsigned long la;
+
+       if (!loadaddr)
+               return 0;
+
+       if (tstc() || (wrsr & WRSR_TOUT))
+               return -ENODEV;
+
+       if (!cmd)
+               return -EINVAL;
+
+       la = simple_strtoul(loadaddr, NULL, 16);
+       if (la == 0)
+               return -EINVAL;
+
+       /* clear BMP header in memory */
+       memset((void *)la, 0, 64);
+
+       ret = do_nand(cmd, 0, argc, argv);
+       if (ret) {
+               printf("Failed to load logo: %d\n", ret);
+               return ret;
+       }
+#endif
+       return ret;
+}
+
+static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+       /* LCD RESET */
+       NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL),
+       /* LCD POWER_ENABLE */
+       NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL),
+       /* LCD Backlight (PWM) */
+       NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL),
+
+       /* Display */
+       MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+       MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+       MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+       MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+       MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+       MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+       MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+       MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+       MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+       MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+       MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+       MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+       MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+       MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+       MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+       MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+       MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+       MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+       MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+       MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+       MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+       MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+       MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+       MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+       MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+       MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+       MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+       MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+
+       /* LVDS option */
+       MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+       MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+       MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+       MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+       MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+       MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+       MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+       MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+       MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+       MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+       { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+       { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+       { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+       int color_depth = 24;
+       char *vm;
+       unsigned long val;
+       int refresh = 60;
+       struct fb_videomode *p = &tx53_fb_mode;
+       int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+       int pix_fmt = 0;
+
+       if (!lcd_enabled) {
+               printf("LCD disabled\n");
+               return;
+       }
+
+       if (tstc() || (wrsr & WRSR_TOUT)) {
+               printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
+               lcd_enabled = 0;
+               return;
+       }
+
+       vm = getenv("video_mode");
+       if (vm == NULL) {
+               printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
+               lcd_enabled = 0;
+               return;
+       }
+       while (*vm != '\0') {
+               if (*vm >= '0' && *vm <= '9') {
+                       char *end;
+
+                       val = simple_strtoul(vm, &end, 0);
+                       if (end > vm) {
+                               if (!xres_set) {
+                                       if (val > panel_info.vl_col)
+                                               val = panel_info.vl_col;
+                                       p->xres = val;
+                                       panel_info.vl_col = val;
+                                       xres_set = 1;
+                               } else if (!yres_set) {
+                                       if (val > panel_info.vl_row)
+                                               val = panel_info.vl_row;
+                                       p->yres = val;
+                                       panel_info.vl_row = val;
+                                       yres_set = 1;
+                               } else if (!bpp_set) {
+                                       switch (val) {
+                                       case 24:
+                                               if (pix_fmt == IPU_PIX_FMT_LVDS666)
+                                                       pix_fmt = IPU_PIX_FMT_LVDS888;
+                                               /* fallthru */
+                                       case 16:
+                                       case 8:
+                                               color_depth = val;
+                                               break;
+
+                                       case 18:
+                                               if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+                                                       color_depth = val;
+                                                       break;
+                                               }
+                                               /* fallthru */
+                                       default:
+                                               printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+                                                       end - vm, vm, color_depth);
+                                       }
+                                       bpp_set = 1;
+                               } else if (!refresh_set) {
+                                       refresh = val;
+                                       refresh_set = 1;
+                               }
+                       }
+                       vm = end;
+               }
+               switch (*vm) {
+               case '@':
+                       bpp_set = 1;
+                       /* fallthru */
+               case '-':
+                       yres_set = 1;
+                       /* fallthru */
+               case 'x':
+                       xres_set = 1;
+                       /* fallthru */
+               case 'M':
+               case 'R':
+                       vm++;
+                       break;
+
+               default:
+                       if (!pix_fmt) {
+                               char *tmp;
+
+                               if (strncmp(vm, "LVDS", 4) == 0)
+                                       pix_fmt = IPU_PIX_FMT_LVDS666;
+                               else
+                                       pix_fmt = IPU_PIX_FMT_RGB24;
+                               tmp = strchr(vm, ':');
+                               if (tmp)
+                                       vm = tmp;
+                       }
+                       if (*vm != '\0')
+                               vm++;
+               }
+       }
+       switch (color_depth) {
+       case 8:
+               panel_info.vl_bpix = 3;
+               break;
+
+       case 16:
+               panel_info.vl_bpix = 4;
+               break;
+
+       case 18:
+       case 24:
+               panel_info.vl_bpix = 5;
+       }
+       lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
+
+       p->pixclock = KHZ2PICOS(refresh *
+               (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+               (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
+               / 1000);
+       debug("Pixel clock set to %lu.%03lu MHz\n",
+               PICOS2KHZ(p->pixclock) / 1000,
+               PICOS2KHZ(p->pixclock) % 1000);
+
+       gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+       mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
+
+       debug("Initializing FB driver\n");
+       if (!pix_fmt)
+               pix_fmt = IPU_PIX_FMT_RGB24;
+       else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+               writel(0x01, IOMUXC_BASE_ADDR + 8);
+       } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
+               writel(0x21, IOMUXC_BASE_ADDR + 8);
+       }
+       if (pix_fmt != IPU_PIX_FMT_RGB24) {
+               struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+               /* enable LDB & DI0 clock */
+               writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
+                       &ccm_regs->CCGR6);
+       }
+
+       mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix);
+
+       if (tx53_load_splashimage() == 0) {
+               debug("Initializing LCD controller\n");
+               video_hw_init();
+       } else {
+               debug("Skipping initialization of LCD controller\n");
+       }
+}
+
+ulong calc_fbsize(void)
+{
+       return panel_info.vl_row * panel_info.vl_col * 2 *
+               NBITS(panel_info.vl_bpix) / 8;
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+       gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+       mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+}
+
+static void stk5v3_board_init(void)
+{
+       stk5_board_init();
+}
+
+static void stk5v5_board_init(void)
+{
+       stk5_board_init();
+}
+
+static void tx53_move_fdt(void)
+{
+       unsigned long fdt_addr = getenv_ulong("fdtcontroladdr", 16, 0);
+       void *fdt = NULL;
+
+       if (!fdt_addr)
+               return;
+
+#ifdef CONFIG_OF_EMBED
+       fdt = _binary_dt_dtb_start;
+#elif defined CONFIG_OF_SEPARATE
+       fdt = (void *)(_end_ofs + _TEXT_BASE);
+#endif
+       if (!fdt)
+               return;
+
+       if (fdt_check_header(fdt)) {
+               printf("ERROR: No valid FDT found at %p\n", fdt);
+               return;
+       }
+       size_t fdt_len = fdt_totalsize(fdt);
+
+       memmove((void *)fdt_addr, fdt, fdt_len);
+       set_working_fdt_addr((void *)fdt_addr);
+}
+
+static void tx53_set_cpu_clock(void)
+{
+       unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+       int ret;
+
+       if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+               return;
+
+       ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
+       if (ret != 0) {
+               printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
+               return;
+       }
+       printf("CPU clock set to %u.%03u MHz\n",
+               mxc_get_clock(MXC_ARM_CLK) / 1000000,
+               mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
+}
+
+int board_late_init(void)
+{
+       const char *baseboard;
+
+       tx53_set_cpu_clock();
+       tx53_move_fdt();
+
+       baseboard = getenv("baseboard");
+       if (!baseboard)
+               return 0;
+
+       if (strncmp(baseboard, "stk5", 4) == 0) {
+               printf("Baseboard: %s\n", baseboard);
+               if ((strlen(baseboard) == 4) ||
+                       strcmp(baseboard, "stk5-v3") == 0) {
+                       stk5v3_board_init();
+               } else if (strcmp(baseboard, "stk5-v5") == 0) {
+                       stk5v5_board_init();
+               } else {
+                       printf("WARNING: Unsupported STK5 board rev.: %s\n",
+                               baseboard + 4);
+               }
+       } else {
+               printf("WARNING: Unsupported baseboard: '%s'\n",
+                       baseboard);
+               return -EINVAL;
+       }
+       if (lcd_enabled) {
+               printf("Switching LCD on\n");
+               gpio_set_value(TX53_LCD_PWR_GPIO, 1);
+               udelay(100);
+               gpio_set_value(TX53_LCD_RST_GPIO, 1);
+               udelay(300000);
+               gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
+       }
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       print_cpuinfo();
+
+       printf("Board: Ka-Ro TX53-xx3%s\n",
+               TX53_MOD_SUFFIX);
+
+       return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+struct node_info nodes[] = {
+       { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
+};
+
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif
+
+static const char *tx53_touchpanels[] = {
+       "ti,tsc2007",
+       "edt,edt-ft5x06",
+};
+
+static void fdt_del_node_by_name(void *blob, const char *name)
+{
+       int offs = fdt_node_offset_by_compatible(blob, -1, name);
+
+       if (offs < 0) {
+               debug("node '%s' not found: %d\n", name, offs);
+               return;
+       }
+       debug("Removing node '%s' from DT\n", name);
+       fdt_del_node(blob, offs);
+}
+
+static void tx53_fixup_touchpanel(void *blob)
+{
+       int i;
+       const char *model = getenv("touchpanel");
+
+       for (i = 0; i < ARRAY_SIZE(tx53_touchpanels); i++) {
+               const char *tp = tx53_touchpanels[i];
+
+               if (model != NULL && strcmp(model, tp) == 0)
+                       continue;
+
+               tp = strchr(tp, ',');
+               if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0)
+                       continue;
+
+               fdt_del_node_by_name(blob, tx53_touchpanels[i]);
+       }
+}
+
+static void tx53_fixup_usb_otg(void *blob)
+{
+       const char *otg_mode = getenv("otg_mode");
+       int usbphy = 2;
+
+       if (otg_mode == NULL || strcmp(otg_mode, "host") != 0) {
+               debug("Removing node %s from DT\n", "usbh1");
+               fdt_del_node_and_alias(blob, "usbh1");
+               usbphy--;
+       }
+       if (otg_mode == NULL || strcmp(otg_mode, "device") != 0) {
+               debug("Removing node %s from DT\n", "usbotg");
+               fdt_del_node_and_alias(blob, "usbotg");
+               usbphy--;
+       }
+       if (!usbphy) {
+               debug("Removing node %s from DT\n", "usbphy");
+               fdt_del_node_and_alias(blob, "usbphy");
+       }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+       fdt_fixup_ethernet(blob);
+
+       tx53_fixup_touchpanel(blob);
+       tx53_fixup_usb_otg(blob);
+}
+#endif

diff --git a/board/karo/tx53/u-boot.lds b/board/karo/tx53/u-boot.lds
new file mode 100644 (file)
index 0000000..7842ff8
--- /dev/null
+++ b/board/karo/tx53/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2012  Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+        . = 0x00000000;
+
+        . = ALIGN(4);
+        .text :
+        {
+               board/karo/tx53/lowlevel_init.o (.text)
+                __image_copy_start = .;
+                CPUDIR/start.o (.text)
+                *(.text)
+        }
+
+        . = ALIGN(4);
+        .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+        . = ALIGN(4);
+        .data : {
+                *(.data)
+        }
+
+        . = ALIGN(4);
+
+        . = .;
+        __u_boot_cmd_start = .;
+        .u_boot_cmd : { *(.u_boot_cmd) }
+        __u_boot_cmd_end = .;
+
+        . = ALIGN(4);
+
+        __image_copy_end = .;
+
+        .rel.dyn : {
+                __rel_dyn_start = .;
+                *(.rel*)
+                __rel_dyn_end = .;
+        }
+
+        .dynsym : {
+                __dynsym_start = .;
+                *(.dynsym)
+        }
+
+        _end = .;
+
+        .bss __rel_dyn_start (OVERLAY) : {
+                __bss_start = .;
+                *(.bss)
+                 . = ALIGN(4);
+                __bss_end__ = .;
+        }
+
+        /DISCARD/ : { *(.dynstr*) }
+        /DISCARD/ : { *(.dynamic*) }
+        /DISCARD/ : { *(.plt*) }
+        /DISCARD/ : { *(.interp*) }
+        /DISCARD/ : { *(.gnu*) }
+}

diff --git a/boards.cfg b/boards.cfg
index 22987d40853c3b36983705c14a490e907d04a31b..eff54fdd6328944ed142067e8dd6ac34b8882bd4 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -204,6 +204,8 @@ tx51-60x2                    arm         armv7       tx51                karo
 tx51-80x0                    arm         armv7       tx51                karo           mx5            tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166
 tx51-80x1                    arm         armv7       tx51                karo           mx5            tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200
 tx51-80x2                    arm         armv7       tx51                karo           mx5            tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166
+tx53-xx30                   arm         armv7       tx53                karo           mx5             tx53:NR_DRAM_BANKS=1
+tx53-xx31                   arm         armv7       tx53                karo           mx5             tx53:NR_DRAM_BANKS=2
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6            mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6            mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
 cm_t35                       arm         armv7       cm_t35              -              omap3

diff --git a/include/configs/tx53.h b/include/configs/tx53.h
new file mode 100644 (file)
index 0000000..da6f769
--- /dev/null
+++ b/include/configs/tx53.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2012 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ */
+#ifndef __TX53_H
+#define __TX53_H
+
+#include <config.h>
+#include <asm/sizes.h>
+
+/*
+ * Ka-Ro TX53 board - SoC configuration
+ */
+#define CONFIG_TX53                            /* TX53 SoM */
+#define CONFIG_MX53                            /* i.MX53 SoC */
+#define CONFIG_SYS_MX5_IOMUX_V3
+#define        CONFIG_MXC_GPIO                         /* GPIO control */
+#define CONFIG_SYS_MX5_HCLK    24000000
+#define CONFIG_SYS_MX5_CLK32   32768
+#define CONFIG_SYS_DDR_CLKSEL  0
+#define CONFIG_SYS_HZ          1000            /* Ticks per second */
+#define CONFIG_SHOW_ACTIVITY
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* LCD Logo and Splash screen support */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_MX5
+#define CONFIG_LCD_LOGO
+#define LCD_BPP                                LCD_COLOR24
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif /* CONFIG_LCD */
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1           0x70000000      /* Base address of bank 1 */
+#define PHYS_SDRAM_1_SIZE      SZ_512M
+#if CONFIG_NR_DRAM_BANKS > 1
+#define PHYS_SDRAM_2           0xb0000000      /* Base address of bank 2 */
+#define PHYS_SDRAM_2_SIZE      SZ_512M
+#define TX53_MOD_SUFFIX                "1"
+#else
+#define TX53_MOD_SUFFIX                "0"
+#endif
+#define CONFIG_STACKSIZE       SZ_128K
+#define CONFIG_SYS_MALLOC_LEN  SZ_8M
+#define CONFIG_SYS_GBL_DATA_SIZE 128           /* Reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1  /* Memtest start address */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M)  /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_CLK   400
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT      "TX53 U-Boot > "
+#define CONFIG_SYS_CBSIZE      2048            /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+                                               /* Print buffer size */
+#define CONFIG_SYS_MAXARGS     64              /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
+                                               /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE                        /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE                   /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING                 /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Flattened Device Tree (FDT) support
+*/
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_EMBED
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_DEFAULT_DEVICE_TREE     tx53
+#define CONFIG_ARCH_DEVICE_TREE                mx53
+
+/*
+ * Boot Linux
+ */
+#define xstr(s)        str(s)
+#define str(s) #s
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY       3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_BOOTFILE                "uImage"
+#define CONFIG_BOOTARGS                "console=ttymxc0,115200 ro debug panic=1"
+#define CONFIG_BOOTCOMMAND     "run bootcmd_nand"
+#define CONFIG_LOADADDR                0x78000000
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Extra Environments
+ */
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "autostart=no\0"                                                \
+       "baseboard=stk5-v3\0"                                           \
+       "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}"    \
+       " root=/dev/mmcblk0p3 rootwait\0"                               \
+       "bootargs_nand=run default_bootargs;set bootargs ${bootargs}"   \
+       " root=/dev/mtdblock3 rootfstype=jffs2\0"                       \
+       "nfsroot=/tftpboot/rootfs\0"                                    \
+       "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}"    \
+       " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+       "bootcmd_mmc=set autostart no;run bootargs_mmc;"                \
+       "mmc read ${loadaddr} 100 3000;run bootm_cmd\0"                 \
+       "bootcmd_nand=set autostart no;run bootargs_nand;"              \
+       "nboot linux;run bootm_cmd\0"                                   \
+       "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;"           \
+       "run bootm_cmd\0"                                               \
+       "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0"     \
+       "default_bootargs=set bootargs " CONFIG_BOOTARGS                \
+       " ${mtdparts} video=${video_mode} ${append_bootargs}\0"         \
+       "cpu_clk=800\0"                                                 \
+       "fdtcontroladdr=70004000\0"                                     \
+       "mtdids=" MTDIDS_DEFAULT "\0"                                   \
+       "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
+       "otg_mode=device\0"                                             \
+       "touchpanel=tsc2007\0"                                          \
+       "video_mode=VGA-1:640x480MR-24@60\0"
+
+#define MTD_NAME                       "mxc_nand"
+#define MTDIDS_DEFAULT                 "nand0=" MTD_NAME
+#define CONFIG_FDT_FIXUP_PARTITIONS
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IIM
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_BOOTCE
+#define CONFIG_CMD_TIME
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE           UART1_BASE
+#define CONFIG_MXC_GPIO
+#define        CONFIG_CONS_INDEX               0
+#define CONFIG_BAUDRATE                        115200          /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * FEC Driver
+ */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+#define IMX_FEC_BASE                   FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR         0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE            MII100
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_ETH_PRIME
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#endif
+
+/*
+ * NAND flash driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE      0xf7ff0000
+#define CONFIG_MXC_NAND_IP_BASE                0x63fdb000
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MAX_FLASH_SECT      1024
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_NAND_MAX_CHIPS      1
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define        CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET              CONFIG_U_BOOT_IMG_SIZE
+#define CONFIG_ENV_SIZE                        0x20000 /* 128 KiB */
+#if 0
+#define CONFIG_ENV_OFFSET_REDUND       0x20000
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+#endif
+#endif
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_NAND_BASE           0xa0000000
+#define CONFIG_FIT
+#else
+#define CONFIG_SYS_NAND_BASE           0x00000000
+#define CONFIG_CMD_ROMUPDATE
+#endif
+#endif /* CONFIG_CMD_NAND */
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#ifndef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+#define CONFIG_MMC
+#define        CONFIG_GENERIC_MMC
+#define        CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_NUM       2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+
+#define CONFIG_BOOT_PARTITION_ACCESS
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environments on MMC
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_OVERWRITE
+/* Associated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET              0x400 /* 1 KB */
+#define CONFIG_ENV_SIZE                        (0x20000 - 0x400) /* 127 KB */
+#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif /* CONFIG_ENV_IS_IN_MMC */
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+#define MTDPARTS_DEFAULT               "mtdparts=" MTD_NAME ":"        \
+       "1m(u-boot),"                                                   \
+       xstr(CONFIG_ENV_SIZE)                                           \
+       "(env),"                                                        \
+       xstr(CONFIG_ENV_SIZE)                                           \
+       "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#else
+#define MTDPARTS_DEFAULT               "mtdparts=" MTD_NAME ":"        \
+       "1m(u-boot),"                                                   \
+       xstr(CONFIG_ENV_SIZE)                                           \
+       "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+                                       GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_CMD_IIM
+#define CONFIG_IMX_IIM
+#endif
+
+#endif /* __CONFIG_H */