]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
arm: rmobile: lager: Update Qos setting to version 0.955
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Tue, 29 Jul 2014 03:13:16 +0000 (12:13 +0900)
committerNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Thu, 9 Oct 2014 05:45:03 +0000 (14:45 +0900)
This updates QoS version 0.955 for ES1 of lager board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
board/renesas/lager/qos.c

index 374275747dbd9e30ae0dec739df70ecdac62730e..930fe8d99bd1fd98aaa63703d409a705c86b9a1c 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/rmobile.h>
 
-/* QoS version 0.955 */
+/* QoS version 0.955 for ES1
 
 enum {
-       DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
-       DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09,
-       DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14,
-       DBSC3_R15,
-       DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04,
-       DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09,
-       DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14,
-       DBSC3_W15,
+       DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+       DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+       DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+       DBSC3_15,
        DBSC3_NR,
 };
 
-static const u32 dbsc3_qos_addr[DBSC3_NR] = {
-       [DBSC3_R00] = DBSC3_0_QOS_R0_BASE,
-       [DBSC3_R01] = DBSC3_0_QOS_R1_BASE,
-       [DBSC3_R02] = DBSC3_0_QOS_R2_BASE,
-       [DBSC3_R03] = DBSC3_0_QOS_R3_BASE,
-       [DBSC3_R04] = DBSC3_0_QOS_R4_BASE,
-       [DBSC3_R05] = DBSC3_0_QOS_R5_BASE,
-       [DBSC3_R06] = DBSC3_0_QOS_R6_BASE,
-       [DBSC3_R07] = DBSC3_0_QOS_R7_BASE,
-       [DBSC3_R08] = DBSC3_0_QOS_R8_BASE,
-       [DBSC3_R09] = DBSC3_0_QOS_R9_BASE,
-       [DBSC3_R10] = DBSC3_0_QOS_R10_BASE,
-       [DBSC3_R11] = DBSC3_0_QOS_R11_BASE,
-       [DBSC3_R12] = DBSC3_0_QOS_R12_BASE,
-       [DBSC3_R13] = DBSC3_0_QOS_R13_BASE,
-       [DBSC3_R14] = DBSC3_0_QOS_R14_BASE,
-       [DBSC3_R15] = DBSC3_0_QOS_R15_BASE,
-       [DBSC3_W00] = DBSC3_0_QOS_W0_BASE,
-       [DBSC3_W01] = DBSC3_0_QOS_W1_BASE,
-       [DBSC3_W02] = DBSC3_0_QOS_W2_BASE,
-       [DBSC3_W03] = DBSC3_0_QOS_W3_BASE,
-       [DBSC3_W04] = DBSC3_0_QOS_W4_BASE,
-       [DBSC3_W05] = DBSC3_0_QOS_W5_BASE,
-       [DBSC3_W06] = DBSC3_0_QOS_W6_BASE,
-       [DBSC3_W07] = DBSC3_0_QOS_W7_BASE,
-       [DBSC3_W08] = DBSC3_0_QOS_W8_BASE,
-       [DBSC3_W09] = DBSC3_0_QOS_W9_BASE,
-       [DBSC3_W10] = DBSC3_0_QOS_W10_BASE,
-       [DBSC3_W11] = DBSC3_0_QOS_W11_BASE,
-       [DBSC3_W12] = DBSC3_0_QOS_W12_BASE,
-       [DBSC3_W13] = DBSC3_0_QOS_W13_BASE,
-       [DBSC3_W14] = DBSC3_0_QOS_W14_BASE,
-       [DBSC3_W15] = DBSC3_0_QOS_W15_BASE,
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
 };
 
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+/* QoS version 0.955 for ES1 */
 void qos_init(void)
 {
        int i;
@@ -115,7 +115,6 @@ void qos_init(void)
        writel(0x20142032, &s3c_qos->s3cqos8);
 
        s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
-
        writel(0x00810089, &s3c_qos->s3cqos0);
        writel(0x20410001, &s3c_qos->s3cqos1);
        writel(0x200A2023, &s3c_qos->s3cqos2);
@@ -129,9 +128,24 @@ void qos_init(void)
        writel(0x00200808, &s3c->s3carcr11);
 
        /* DBSC -QoS */
-       /* DBSC0 - Read/Write */
-       for (i = DBSC3_R00; i < DBSC3_NR; i++) {
-               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_qos_addr[i];
+       /* DBSC0 - Read */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+               writel(0x00000203, &qos_addr->dblgcnt);
+               writel(0x00002064, &qos_addr->dbtmval0);
+               writel(0x00002048, &qos_addr->dbtmval1);
+               writel(0x00002032, &qos_addr->dbtmval2);
+               writel(0x00002019, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002019, &qos_addr->dbthres0);
+               writel(0x00002019, &qos_addr->dbthres1);
+               writel(0x00002019, &qos_addr->dbthres2);
+               writel(0x00000000, &qos_addr->dblgqon);
+       }
+
+       /* DBSC0 - Write */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
                writel(0x00000203, &qos_addr->dblgcnt);
                writel(0x00002064, &qos_addr->dbtmval0);
                writel(0x00002048, &qos_addr->dbtmval1);
@@ -143,6 +157,7 @@ void qos_init(void)
                writel(0x00002019, &qos_addr->dbthres2);
                writel(0x00000000, &qos_addr->dblgqon);
        }
+
        /* CCI-400 -QoS */
        writel(0x20001000, CCI_400_MAXOT_1);
        writel(0x20001000, CCI_400_MAXOT_2);