karo: cleanup after merge of v2015.10-rc2
authorLothar Waßmann <LW@KARO-electronics.de>
Thu, 17 Sep 2015 05:31:36 +0000 (07:31 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 17 Sep 2015 05:31:36 +0000 (07:31 +0200)
201 files changed:
MAINTAINERS
README
arch/arc/include/asm/config.h
arch/arm/Kconfig
arch/arm/cpu/arm926ejs/cpu.c
arch/arm/cpu/arm926ejs/mxs/Makefile
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/cpu/armv7/cpu.c
arch/arm/cpu/armv7/mx5/Kconfig
arch/arm/cpu/armv7/mx6/Kconfig
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/imx-common/iomux-v3.c
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/da8xx-fb.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6-pins.h
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/armv7/Makefile
arch/arm/mach-at91/include/mach/at91_pmc.h
arch/arm/mach-at91/include/mach/atmel_usba_udc.h
arch/arm/mach-at91/include/mach/hardware.h
arch/arm/mach-at91/mpddrc.c
arch/arm/mach-at91/spl_atmel.c
arch/arm/mach-exynos/include/mach/system.h
arch/arm/mach-uniphier/ph1-ld4/Makefile
arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c
arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
arch/arm/mach-uniphier/ph1-ld4/sg_init.c
arch/arm/mach-uniphier/ph1-pro4/Makefile
arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
arch/arm/mach-uniphier/ph1-pro4/sg_init.c
arch/arm/mach-uniphier/ph1-sld8/Makefile
arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
arch/arm/mach-uniphier/smp.S [deleted file]
arch/m68k/config.mk
arch/m68k/lib/Makefile
board/karo/common/env.c
board/karo/common/fdt.c
board/karo/tx28/Kconfig
board/karo/tx28/config.mk
board/karo/tx48/Kconfig
board/karo/tx48/config.mk
board/karo/tx48/spl.c
board/karo/tx48/tx48.c
board/karo/tx48/u-boot.lds
board/karo/tx51/Kconfig
board/karo/tx51/u-boot.lds
board/karo/tx53/Kconfig
board/karo/tx6/Kconfig
board/karo/tx6/config.mk
board/karo/tx6/lowlevel_init.S
board/karo/tx6/tx6qdl.c
board/karo/tx6/u-boot.lds
board/karo/txa5/Kconfig
common/Kconfig
common/cmd_bootce.c
common/lcd.c
configs/sama5d4_xplained_mmc_defconfig
configs/sama5d4_xplained_nandflash_defconfig
configs/sama5d4_xplained_spiflash_defconfig
configs/sama5d4ek_mmc_defconfig
configs/sama5d4ek_nandflash_defconfig
configs/sama5d4ek_spiflash_defconfig
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig
configs/tqma6q_mba6_mmc_defconfig
configs/tqma6q_mba6_spi_defconfig
configs/tqma6s_mba6_mmc_defconfig
configs/tqma6s_mba6_spi_defconfig
configs/tx28-40x1_defconfig
configs/tx28-40x1_noenv_defconfig
configs/tx28-40x2_defconfig
configs/tx28-40x2_noenv_defconfig
configs/tx28-40x3_defconfig
configs/tx28-40x3_noenv_defconfig
configs/tx28-41x0_defconfig
configs/tx28-41x0_noenv_defconfig
configs/tx48_defconfig
configs/tx51-8xx0_defconfig
configs/tx51-8xx0_noenv_defconfig
configs/tx51-8xx1_2_defconfig
configs/tx51-8xx1_2_noenv_defconfig
configs/tx53-1232_defconfig
configs/tx53-1232_noenv_defconfig [new file with mode: 0644]
configs/tx53-1232_sec_defconfig
configs/tx53-x030_defconfig
configs/tx53-x030_noenv_defconfig [new file with mode: 0644]
configs/tx53-x030_sec_defconfig
configs/tx53-x130_defconfig
configs/tx53-x130_noenv_defconfig [new file with mode: 0644]
configs/tx53-x130_sec_defconfig
configs/tx53-x131_defconfig
configs/tx53-x131_noenv_defconfig [new file with mode: 0644]
configs/tx53-x131_sec_defconfig
configs/tx6q-1020_defconfig
configs/tx6q-1020_mfg_defconfig
configs/tx6q-1020_noenv_defconfig
configs/tx6q-1020_sec_defconfig
configs/tx6q-1033_defconfig
configs/tx6q-1033_mfg_defconfig
configs/tx6q-1033_noenv_defconfig
configs/tx6q-1033_sec_defconfig
configs/tx6q-10x0_defconfig
configs/tx6q-10x0_mfg_defconfig
configs/tx6q-10x0_noenv_defconfig
configs/tx6q-10x0_sec_defconfig
configs/tx6q-11x0_defconfig
configs/tx6q-11x0_mfg_defconfig
configs/tx6q-11x0_noenv_defconfig
configs/tx6q-11x0_sec_defconfig [new file with mode: 0644]
configs/tx6s-8034_defconfig
configs/tx6s-8034_mfg_defconfig
configs/tx6s-8034_noenv_defconfig
configs/tx6s-8034_sec_defconfig
configs/tx6s-8035_defconfig
configs/tx6s-8035_mfg_defconfig
configs/tx6s-8035_noenv_defconfig
configs/tx6s-8035_sec_defconfig
configs/tx6u-8011_defconfig
configs/tx6u-8011_mfg_defconfig
configs/tx6u-8011_noenv_defconfig
configs/tx6u-8011_sec_defconfig
configs/tx6u-8012_defconfig
configs/tx6u-8012_mfg_defconfig
configs/tx6u-8012_noenv_defconfig
configs/tx6u-8012_sec_defconfig
configs/tx6u-8033_defconfig
configs/tx6u-8033_mfg_defconfig
configs/tx6u-8033_noenv_defconfig
configs/tx6u-8033_sec_defconfig
configs/tx6u-80x0_defconfig
configs/tx6u-80x0_mfg_defconfig
configs/tx6u-80x0_noenv_defconfig
configs/tx6u-80x0_sec_defconfig
configs/tx6u-8111_defconfig
configs/tx6u-8111_mfg_defconfig
configs/tx6u-8111_noenv_defconfig
configs/tx6u-8111_sec_defconfig
configs/tx6u-81x0_defconfig
configs/tx6u-81x0_mfg_defconfig
configs/tx6u-81x0_noenv_defconfig
configs/tx6u-81x0_sec_defconfig
configs/txa5-5010_defconfig
configs/txa5-5011_defconfig
drivers/core/Kconfig
drivers/mmc/Kconfig
drivers/mmc/omap_hsmmc.c
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/omap_gpmc.c
drivers/net/cpsw.c
drivers/net/fec_mxc.c
drivers/spi/Kconfig
drivers/usb/host/ehci-mx6.c
drivers/video/atmel_hlcdfb.c
drivers/video/da8xx-fb.c
drivers/video/da8xx-fb.h [deleted file]
include/atmel_lcd.h
include/configs/amcore.h
include/configs/calimain.h
include/configs/da830evm.h
include/configs/da850evm.h
include/configs/davinci_dm355evm.h
include/configs/davinci_dm355leopard.h
include/configs/davinci_dm365evm.h
include/configs/davinci_dm6467evm.h
include/configs/davinci_dvevm.h
include/configs/davinci_schmoogie.h
include/configs/davinci_sffsdr.h
include/configs/davinci_sonata.h
include/configs/dbau1x00.h
include/configs/ea20.h
include/configs/embestmx6boards.h
include/configs/enbw_cmc.h
include/configs/flea3.h
include/configs/ipam390.h
include/configs/k2e_evm.h
include/configs/k2hk_evm.h
include/configs/k2l_evm.h
include/configs/pb1x00.h
include/configs/socfpga_cyclone5.h
include/configs/ti_armv7_keystone2.h
include/configs/tqma6.h
include/configs/tx28.h
include/configs/tx48.h
include/configs/tx51.h
include/configs/tx53.h
include/configs/tx6.h
include/configs/txa5.h
include/configs/wandboard.h
include/linux/mtd/omap_gpmc.h
include/netdev.h
net/bootme.c
net/tftp.c
tools/elftosb/common/EncoreBootImage.h
tools/elftosb/makefile
tools/elftosb/makefile.rules

index b478c8c..bf60c67 100644 (file)
@@ -99,7 +99,6 @@ M:    Luka Perkov <luka.perkov@sartura.hr>
 S:     Maintained
 T:     git git://git.denx.de/u-boot-marvell.git
 F:     arch/arm/mach-kirkwood/
-F:     arch/arm/include/asm/arch-kirkwood/
 
 ARM MARVELL PXA
 M:     Marek Vasut <marex@denx.de>
diff --git a/README b/README
index 5980f6d..de436ce 100644 (file)
--- a/README
+++ b/README
@@ -701,6 +701,9 @@ The following options need to be configured:
                NOTE: The following can be machine specific errata. These
                do have ability to provide rudimentary version and machine
                specific checks, but expect no product checks.
+               CONFIG_ARM_ERRATA_430973
+               CONFIG_ARM_ERRATA_454179
+               CONFIG_ARM_ERRATA_621766
                CONFIG_ARM_ERRATA_798870
                CONFIG_ARM_ERRATA_801819
 
@@ -711,119 +714,6 @@ The following options need to be configured:
                impossible actions will be skipped if the CPU is in NS mode,
                such as ARM architectural timer initialization.
 
-- Driver Model
-               Driver model is a new framework for devices in U-Boot
-               introduced in early 2014. U-Boot is being progressively
-               moved over to this. It offers a consistent device structure,
-               supports grouping devices into classes and has built-in
-               handling of platform data and device tree.
-
-               To enable transition to driver model in a relatively
-               painful fashion, each subsystem can be independently
-               switched between the legacy/ad-hoc approach and the new
-               driver model using the options below. Also, many uclass
-               interfaces include compatibility features which may be
-               removed once the conversion of that subsystem is complete.
-               As a result, the API provided by the subsystem may in fact
-               not change with driver model.
-
-               See doc/driver-model/README.txt for more information.
-
-               CONFIG_DM
-
-               Enable driver model. This brings in the core support,
-               including scanning of platform data on start-up. If
-               CONFIG_OF_CONTROL is enabled, the device tree will be
-               scanned also when available.
-
-               CONFIG_CMD_DM
-
-               Enable driver model test commands. These allow you to print
-               out the driver model tree and the uclasses.
-
-               CONFIG_DM_DEMO
-
-               Enable some demo devices and the 'demo' command. These are
-               really only useful for playing around while trying to
-               understand driver model in sandbox.
-
-               CONFIG_SPL_DM
-
-               Enable driver model in SPL. You will need to provide a
-               suitable malloc() implementation. If you are not using the
-               full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
-               consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
-               must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
-               In most cases driver model will only allocate a few uclasses
-               and devices in SPL, so 1KB should be enable. See
-               CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
-               it.
-
-               CONFIG_DM_SERIAL
-
-               Enable driver model for serial. This replaces
-               drivers/serial/serial.c with the serial uclass, which
-               implements serial_putc() etc. The uclass interface is
-               defined in include/serial.h.
-
-               CONFIG_DM_GPIO
-
-               Enable driver model for GPIO access. The standard GPIO
-               interface (gpio_get_value(), etc.) is then implemented by
-               the GPIO uclass. Drivers provide methods to query the
-               particular GPIOs that they provide. The uclass interface
-               is defined in include/asm-generic/gpio.h.
-
-               CONFIG_DM_SPI
-
-               Enable driver model for SPI. The SPI slave interface
-               (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
-               the SPI uclass. Drivers provide methods to access the SPI
-               buses that they control. The uclass interface is defined in
-               include/spi.h. The existing spi_slave structure is attached
-               as 'parent data' to every slave on each bus. Slaves
-               typically use driver-private data instead of extending the
-               spi_slave structure.
-
-               CONFIG_DM_SPI_FLASH
-
-               Enable driver model for SPI flash. This SPI flash interface
-               (spi_flash_probe(), spi_flash_write(), etc.) is then
-               implemented by the SPI flash uclass. There is one standard
-               SPI flash driver which knows how to probe most chips
-               supported by U-Boot. The uclass interface is defined in
-               include/spi_flash.h, but is currently fully compatible
-               with the old interface to avoid confusion and duplication
-               during the transition parent. SPI and SPI flash must be
-               enabled together (it is not possible to use driver model
-               for one and not the other).
-
-               CONFIG_DM_CROS_EC
-
-               Enable driver model for the Chrome OS EC interface. This
-               allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
-               but otherwise makes few changes. Since cros_ec also supports
-               I2C and LPC (which don't support driver model yet), a full
-               conversion is not yet possible.
-
-
-               ** Code size options: The following options are enabled by
-               default except in SPL. Enable them explicitly to get these
-               features in SPL.
-
-               CONFIG_DM_WARN
-
-               Enable the dm_warn() function. This can use up quite a bit
-               of space for its strings.
-
-               CONFIG_DM_STDIO
-
-               Enable registering a serial device with the stdio library.
-
-               CONFIG_DM_DEVICE_REMOVE
-
-               Enable removing of devices.
-
 - Linux Kernel Interface:
                CONFIG_CLOCKS_IN_MHZ
 
index 8936f5c..d2d7919 100644 (file)
@@ -7,7 +7,6 @@
 #ifndef __ASM_ARC_CONFIG_H_
 #define __ASM_ARC_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_ARCH_EARLY_INIT_R
 
index 28c97ae..67982f5 100644 (file)
@@ -42,6 +42,9 @@ config CPU_PXA
 config CPU_SA1100
         bool
 
+config OMAP_COMMON
+       bool
+
 config SYS_CPU
         default "arm720t" if CPU_ARM720T
         default "arm920t" if CPU_ARM920T
@@ -216,10 +219,6 @@ config TARGET_TX6
        bool "Support tx6"
        select SOC_MX6
 
-config TARGET_TXA5
-       bool "Support txA5"
-       select SOC_SAMA5D4
-
 config TARGET_ZMX25
        bool "Support zmx25"
        select CPU_ARM926EJS
@@ -930,11 +929,11 @@ source "arch/arm/mach-keystone/Kconfig"
 
 source "arch/arm/mach-kirkwood/Kconfig"
 
-source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/cpu/armv7/mx6/Kconfig"
 
 source "arch/arm/cpu/armv7/mx5/Kconfig"
 
-source "arch/arm/cpu/armv7/mx6/Kconfig"
+source "arch/arm/mach-nomadik/Kconfig"
 
 source "arch/arm/cpu/armv7/omap3/Kconfig"
 
index d1d2a17..a90ce30 100644 (file)
@@ -15,7 +15,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <lcd.h>
 #include <asm/system.h>
 
 static void cache_flush(void);
@@ -31,14 +30,6 @@ int cleanup_before_linux (void)
 
        disable_interrupts ();
 
-#ifdef CONFIG_LCD
-       {
-               /* switch off LCD panel */
-               lcd_panel_disable();
-               /* disable LCD controller */
-               lcd_disable();
-       }
-#endif
 
        /* turn off I/D-cache */
        icache_disable();
index e80867e..d66577c 100644 (file)
@@ -86,8 +86,8 @@ ELFTOSB_TARGET-$(CONFIG_SOC_MX28) = imx28
 u-boot.bd: $(KBUILD_SRC)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
        sed "s@OBJTREE@$(objtree)@g" $^ > $@
 
-u-boot.sb: u-boot spl/u-boot-spl $(objtree)/u-boot.bd $(KBUILD_SRC)/tools/elftosb/bld/linux/elftosb
-               $(KBUILD_SRC)/tools/elftosb/bld/linux/elftosb -V -zf $(ELFTOSB_TARGET-y) -c u-boot.bd -o u-boot.sb
+u-boot.sb: u-boot spl/u-boot-spl $(objtree)/u-boot.bd $(KBUILD_OUTPUT)/tools/elftosb/bld/linux/elftosb
+               $(KBUILD_OUTPUT)/tools/elftosb/bld/linux/elftosb -V -zf $(ELFTOSB_TARGET-y) -c u-boot.bd -o u-boot.sb
 
 u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE
        $(call if_changed,mkimage_mxs)
index 311104b..59dfe45 100644 (file)
@@ -122,7 +122,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
                        EMIF_REG_INITREF_DIS_MASK);
 
        writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-       writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+       writel(regs->sdram_config, &cstat->emif_sdram_config);
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 
@@ -165,7 +165,7 @@ void config_sdram(const struct emif_regs *regs, int nr)
 {
        if (regs->zq_config) {
                writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
-               writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+               writel(regs->sdram_config, &cstat->emif_sdram_config);
                writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
                writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
                writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
index f5160b9..0b0e500 100644 (file)
@@ -17,7 +17,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <lcd.h>
 #include <asm/system.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
index 9f250c6..ca3c655 100644 (file)
@@ -1,13 +1,13 @@
 if ARCH_MX5
 
-config MX5
+config SOC_MX5
        bool
        default y
 
-config MX51
+config SOC_MX51
        bool
 
-config MX53
+config SOC_MX53
        bool
 
 choice
index dce7ffc..373ef3f 100644 (file)
@@ -1,31 +1,31 @@
 if ARCH_MX6
 
-config MX6
+config SOC_MX6
        bool
        default y
 
-config MX6D
+config SOC_MX6D
        bool
 
-config MX6DL
+config SOC_MX6DL
        bool
 
-config MX6Q
+config SOC_MX6Q
        bool
 
-config MX6QDL
+config SOC_MX6QDL
        bool
 
-config MX6S
+config SOC_MX6S
        bool
 
-config MX6SL
+config SOC_MX6SL
        bool
 
-config MX6SX
+config SOC_MX6SX
        bool
 
-config MX6UL
+config SOC_MX6UL
        select SYS_L2CACHE_OFF
        bool
 
index 63d250f..eefb58e 100644 (file)
@@ -8,24 +8,24 @@
  */
 
 #include <common.h>
-#include <stdbool.h>
-#include <dm.h>
 #include <div64.h>
 #include <ipu.h>
-#include <imx_thermal.h>
 #include <asm/armv7.h>
 #include <asm/bootm.h>
 #include <asm/pl310.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/regs-ocotp.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/regs-ocotp.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
+#include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <imx_thermal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
index c002530..f429876 100644 (file)
@@ -41,8 +41,8 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
        }
 #endif
 #ifdef DEBUG
-       printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
-               i, pad, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
+       printf("PAD=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
+               pad, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
                pad & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
 #endif
 
index e34f71c..16273c8 100644 (file)
@@ -605,6 +605,7 @@ struct pwmss_ecap_regs {
 
 unsigned long __clk_get_rate(u32 m_n, u32 div_m2);
 
+unsigned long lcdc_clk_rate(void);
 unsigned long mpu_clk_rate(void);
 
 #endif /* __ASSEMBLY__ */
index 208b232..a4220c3 100644 (file)
@@ -29,7 +29,8 @@
 #define DA8XX_FB_H
 
 enum panel_type {
-       QVGA = 0
+       QVGA,
+       WVGA,
 };
 
 enum panel_shade {
@@ -121,6 +122,7 @@ struct lcd_sync_arg {
 };
 
 void da8xx_fb_disable(void);
-void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+void da8xx_video_init(const struct da8xx_panel *panel,
+               const struct lcd_ctrl_config *lcd_cfg, int bits_pixel);
 
 #endif  /* ifndef DA8XX_FB_H */
index 960d8ee..b6b6130 100644 (file)
@@ -11,7 +11,7 @@
 
 #define CONFIG_SYS_CACHELINE_SIZE 64
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000
 #define SPBA0_BASE_ADDR                0x70000000
index c0f8f4a..49a124e 100644 (file)
@@ -11,7 +11,7 @@
 
 #define ARCH_MXC
 
-#ifdef CONFIG_MX6UL
+#ifdef CONFIG_SOC_MX6UL
 #define CONFIG_SYS_CACHELINE_SIZE      64
 #else
 #define CONFIG_SYS_CACHELINE_SIZE      32
index f1a9fae..708eaaa 100644 (file)
@@ -37,7 +37,7 @@ enum {
 #include "mx6sl_pins.h"
 #elif defined(CONFIG_SOC_MX6SX)
 #include "mx6sx_pins.h"
-#elif defined(CONFIG_MX6UL)
+#elif defined(CONFIG_SOC_MX6UL)
 #include "mx6ul_pins.h"
 #else
 #error "Please select cpu"
index f9f148d..9d0cc83 100644 (file)
@@ -134,6 +134,10 @@ config TARGET_SMARTWEB
        select CPU_ARM926EJS
        select SUPPORT_SPL
 
+config TARGET_TXA5
+       bool "Support txA5"
+       select SOC_SAMA5D4
+
 endchoice
 
 config SYS_SOC
index 313eb47..cbf205e 100644 (file)
@@ -6,7 +6,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
+obj-$(CONFIG_SOC_SAMA5D4) += mpddrc.o spl_atmel.o
 obj-y += spl.o
 endif
 
index f4f35a4..4c8ff81 100644 (file)
@@ -9,7 +9,7 @@
 #
 
 obj-$(CONFIG_SAMA5D3)  += sama5d3_devices.o
-obj-$(CONFIG_SAMA5D4)  += sama5d4_devices.o
+obj-$(CONFIG_SOC_SAMA5D4)      += sama5d4_devices.o
 obj-y += clock.o
 obj-y += cpu.o
 obj-y += reset.o
index 8a3fb94..6ea18b5 100644 (file)
@@ -78,7 +78,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_PLLXR_DIV(x)          (x & 0xFF)
 #define AT91_PMC_PLLXR_PLLCOUNT(x)     ((x & 0x3F) << 8)
 #define AT91_PMC_PLLXR_OUT(x)          ((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SOC_SAMA5D4)
 #define AT91_PMC_PLLXR_MUL(x)          ((x & 0x7F) << 18)
 #else
 #define AT91_PMC_PLLXR_MUL(x)          ((x & 0x7FF) << 16)
@@ -97,7 +97,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_PLLB         0x00000003
 #define AT91_PMC_MCKR_CSS_MASK         0x00000003
 
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SOC_SAMA5D4) || \
        defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_PRES_1           0x00000000
 #define AT91_PMC_MCKR_PRES_2           0x00000010
@@ -127,7 +127,7 @@ typedef struct at91_pmc {
 #else
 #define AT91_PMC_MCKR_MDIV_1           0x00000000
 #define AT91_PMC_MCKR_MDIV_2           0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SOC_SAMA5D4) || \
        defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_MDIV_3           0x00000300
 #endif
index 38b5012..f90a1c3 100644 (file)
@@ -31,7 +31,7 @@ static struct usba_ep_data usba_udc_ep[] = {
        EP("ep5", 5, 1024, 3, 1, 1),
        EP("ep6", 6, 1024, 3, 1, 1),
 };
-#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SOC_SAMA5D4)
 static struct usba_ep_data usba_udc_ep[] = {
        EP("ep0", 0, 64, 1, 0, 0),
        EP("ep1", 1, 1024, 3, 1, 0),
index ff6b71b..1bba84d 100644 (file)
@@ -25,7 +25,7 @@
 # include <asm/arch/at91sam9x5.h>
 #elif defined(CONFIG_SAMA5D3)
 # include <asm/arch/sama5d3.h>
-#elif defined(CONFIG_SAMA5D4)
+#elif defined(CONFIG_SOC_SAMA5D4)
 # include <asm/arch/sama5d4.h>
 #else
 # error "Unsupported AT91 processor"
index 47e6e5a..82047f8 100644 (file)
@@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
 
 static int ddr2_decodtype_is_seq(u32 cr)
 {
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SOC_SAMA5D4) || \
        defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
        if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
                return 0;
index 8ac5335..16277e5 100644 (file)
@@ -51,7 +51,7 @@ static void switch_to_main_crystal_osc(void)
        while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY))
                ;
 
-#ifndef CONFIG_SAMA5D4
+#ifndef CONFIG_SOC_SAMA5D4
        tmp = readl(&pmc->mor);
        tmp &= ~AT91_PMC_MOR_MOSCRCEN;
        tmp &= ~AT91_PMC_MOR_KEY(0xff);
index 6ad62b2..3ffb296 100644 (file)
@@ -10,7 +10,7 @@
 
 #ifndef __ASSEMBLY__
 struct exynos4_sysreg {
-       unsigned int    res1[0x210 / 4];
+       unsigned char   res1[0x210];
        unsigned int    display_ctrl;
        unsigned int    display_ctrl2;
        unsigned int    camera_control;
@@ -19,7 +19,7 @@ struct exynos4_sysreg {
 };
 
 struct exynos5_sysreg {
-       unsigned int    res1[0x214 / 4];
+       unsigned char   res1[0x214];
        unsigned int    disp1blk_cfg;
        unsigned int    disp2blk_cfg;
        unsigned int    hdcp_e_fuse;
@@ -28,7 +28,7 @@ struct exynos5_sysreg {
        unsigned int    reserved;
        unsigned int    ispblk_cfg;
        unsigned int    usb20phy_cfg;
-       unsigned int    res2[0x29c / 4];
+       unsigned char   res2[0x29c];
        unsigned int    mipi_dphy;
        unsigned int    dptx_dphy;
        unsigned int    phyclk_sel;
index 6ab2dd5..1410b12 100644 (file)
@@ -9,8 +9,7 @@ obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
 else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 endif
 
 obj-y += boot-mode.o
index 1bbd944..2de81f0 100644 (file)
@@ -13,15 +13,29 @@ void clkrst_init(void)
 
        /* deassert reset */
        tmp = readl(SC_RSTCTRL);
-       tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-               | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+#ifdef CONFIG_UNIPHIER_ETH
+       tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+       tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+       tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
        writel(tmp, SC_RSTCTRL);
        readl(SC_RSTCTRL); /* dummy read */
 
        /* privide clocks */
        tmp = readl(SC_CLKCTRL);
-       tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-            | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+#ifdef CONFIG_UNIPHIER_ETH
+       tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+       tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+       tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
        writel(tmp, SC_CLKCTRL);
        readl(SC_CLKCTRL); /* dummy read */
 }
index cc74907..8e25792 100644 (file)
@@ -18,33 +18,32 @@ void sbc_init(void)
        tmp &= 0xfffffcff;
        writel(tmp, PC0CTRL);
 
-       /* XECS1: sub/boot memory (boot swap = off/on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+       /*
+        * Only CS1 is connected to support card.
+        * BKSZ[1:0] should be set to "01".
+        */
+       writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+       writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+       writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+       writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
 
-#if !defined(CONFIG_SPL_BUILD)
-       /* XECS0: boot/sub memory (boot swap = off/on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-       /* XECS3: peripherals */
-       writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
-       writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
-       writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
-       writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
-       /* base address regsiters */
-       writel(0x0000bc01, SBBASE0);
-       writel(0x0400bc01, SBBASE1);
-       writel(0x0800bf01, SBBASE3);
-
-#if !defined(CONFIG_SPL_BUILD)
-       /* enable access to sub memory when boot swap is on */
-       sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-#endif
-       sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
+       if (boot_is_swapped()) {
+               /*
+                * Boot Swap On: boot from external NOR/SRAM
+                * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+                *
+                * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
+                * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+                */
+               writel(0x0000bc01, SBBASE0);
+       } else {
+               /*
+                * Boot Swap Off: boot from mask ROM
+                * 0x00000000-0x01ffffff: mask ROM
+                * 0x02000000-0x03efffff: memory bank (31MB)
+                * 0x03f00000-0x03ffffff: peripherals (1MB)
+                */
+               writel(0x0000be01, SBBASE0); /* dummy */
+               writel(0x0200be01, SBBASE1);
+       }
 }
index de83962..dab56e9 100644 (file)
@@ -11,14 +11,6 @@ void sg_init(void)
 {
        u32 tmp;
 
-       /* Set DDR size */
-       tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
-       tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
-       tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
-       writel(tmp, SG_MEMCONF);
-
        /* Input ports must be enabled before deasserting reset of cores */
        tmp = readl(SG_IECTRL);
        tmp |= 0x1;
index 78b4389..229f443 100644 (file)
@@ -9,8 +9,7 @@ obj-y += sg_init.o pll_init.o early_clkrst_init.o \
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
 else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 endif
 
 obj-y += boot-mode.o
index 1bbd944..46cace7 100644 (file)
@@ -13,15 +13,44 @@ void clkrst_init(void)
 
        /* deassert reset */
        tmp = readl(SC_RSTCTRL);
-       tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-               | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+       tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
+               SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+       tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+       tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+       tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
        writel(tmp, SC_RSTCTRL);
        readl(SC_RSTCTRL); /* dummy read */
 
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+       tmp = readl(SC_RSTCTRL2);
+       tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
+       writel(tmp, SC_RSTCTRL2);
+       readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
        /* privide clocks */
        tmp = readl(SC_CLKCTRL);
-       tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-            | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+       tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+               SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+       tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+       tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+       tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
        writel(tmp, SC_CLKCTRL);
        readl(SC_CLKCTRL); /* dummy read */
 }
index b195c9d..533739c 100644 (file)
@@ -11,7 +11,6 @@
 
 void sbc_init(void)
 {
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
        /*
         * Only CS1 is connected to support card.
         * BKSZ[1:0] should be set to "01".
@@ -34,41 +33,10 @@ void sbc_init(void)
                /*
                 * Boot Swap Off: boot from mask ROM
                 * 0x00000000-0x01ffffff: mask ROM
-                * 0x02000000-0x3effffff: memory bank (31MB)
-                * 0x03f00000-0x3fffffff: peripherals (1MB)
+                * 0x02000000-0x03efffff: memory bank (31MB)
+                * 0x03f00000-0x03ffffff: peripherals (1MB)
                 */
                writel(0x0000be01, SBBASE0); /* dummy */
                writel(0x0200be01, SBBASE1);
        }
-#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-#if !defined(CONFIG_SPL_BUILD)
-       /* XECS0: boot/sub memory (boot swap = off/on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-       /* XECS1: sub/boot memory (boot swap = off/on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-       /* XECS3: peripherals */
-       writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
-       writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
-       writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
-       writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
-       writel(0x0000bc01, SBBASE0); /* boot memory */
-       writel(0x0400bc01, SBBASE1); /* sub memory */
-       writel(0x0800bf01, SBBASE3); /* peripherals */
-
-#if !defined(CONFIG_SPL_BUILD)
-       sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-#endif
-       sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
-       writel(0x00000001, SG_LOADPINCTRL);
-
-#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
 }
index 18c4f1a..d6ccffb 100644 (file)
@@ -11,14 +11,6 @@ void sg_init(void)
 {
        u32 tmp;
 
-       /* Set DDR size */
-       tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
-       tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
-       tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
-       writel(tmp, SG_MEMCONF);
-
        /* Input ports must be enabled before deasserting reset of cores */
        tmp = readl(SG_IECTRL);
        tmp |= 1 << 6;
index 72f4663..8eb575e 100644 (file)
@@ -1,14 +1 @@
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
-       pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
+include $(src)/../ph1-ld4/Makefile
index 18965a9..8d3435d 100644 (file)
@@ -1,29 +1 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
-       u32 tmp;
-
-       /* deassert reset */
-       tmp = readl(SC_RSTCTRL);
-       tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-               | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
-       writel(tmp, SC_RSTCTRL);
-       readl(SC_RSTCTRL); /* dummy read */
-
-       /* privide clocks */
-       tmp = readl(SC_CLKCTRL);
-       tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-            | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
-       writel(tmp, SC_CLKCTRL);
-       readl(SC_CLKCTRL); /* dummy read */
-}
+#include "../ph1-ld4/clkrst_init.c"
index 5efee9c..225c0d2 100644 (file)
@@ -1,58 +1 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-       u32 tmp;
-
-       /* system bus output enable */
-       tmp = readl(PC0CTRL);
-       tmp &= 0xfffffcff;
-       writel(tmp, PC0CTRL);
-
-#if !defined(CONFIG_SPL_BUILD)
-       /* XECS0 : dummy */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-       /* XECS1 : boot memory (always boot swap = on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-       /* XECS4 : sub memory */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
-
-       /* XECS5 : peripherals */
-       writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
-       writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
-       writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
-       writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
-
-       /* base address regsiters */
-       writel(0x0000bc01, SBBASE0); /* boot memory */
-       writel(0x0900bfff, SBBASE1); /* dummy */
-       writel(0x0400bc01, SBBASE4); /* sub memory */
-       writel(0x0800bf01, SBBASE5); /* peripherals */
-
-       sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
-       sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
-
-       /* dummy read to assure write process */
-       readl(SG_PINCTRL(33));
-}
+#include "../ph1-ld4/sbc_init.c"
diff --git a/arch/arm/mach-uniphier/smp.S b/arch/arm/mach-uniphier/smp.S
deleted file mode 100644 (file)
index 25ba981..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2013 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/arch/led.h>
-#include <asm/arch/sbc-regs.h>
-
-/* Entry point of U-Boot main program for the secondary CPU */
-LENTRY(secondary_entry)
-       mrc     p15, 0, r0, c1, c0, 0   @ SCTLR (System Contrl Register)
-       bic     r0, r0, #(CR_C | CR_M)  @ MMU and Dcache disable
-       mcr     p15, 0, r0, c1, c0, 0
-       mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
-       mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
-       dsb
-       led_write(C,0,,)
-       ldr     r1, =ROM_BOOT_ROMRSV2
-       mov     r0, #0
-       str     r0, [r1]
-0:     wfe
-       ldr     r4, [r1]                @ r4: entry point for secondary CPUs
-       cmp     r4, #0
-       beq     0b
-       led_write(C, P, U, 1)
-       bx      r4                      @ secondary CPUs jump to linux
-ENDPROC(secondary_entry)
-
-ENTRY(wakeup_secondary)
-       ldr     r1, =ROM_BOOT_ROMRSV2
-0:     ldr     r0, [r1]
-       cmp     r0, #0
-       bne     0b
-
-       /* set entry address and send event to the secondary CPU */
-       ldr     r0, =secondary_entry
-       str     r0, [r1]
-       ldr     r0, [r1]        @ make sure store is complete
-       mov     r0, #0x100
-0:     subs    r0, r0, #1      @ I don't know the reason, but without this wait
-       bne     0b              @ fails to wake up the secondary CPU
-       sev
-
-       /* wait until the secondary CPU reach to secondary_entry */
-0:     ldr     r0, [r1]
-       cmp     r0, #0
-       bne     0b
-       bx      lr
-ENDPROC(wakeup_secondary)
index a629b68..3b3a7e8 100644 (file)
@@ -11,9 +11,6 @@ endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
 
-# Support generic board on m68k
-__HAVE_ARCH_GENERIC_BOARD := y
-
 PLATFORM_CPPFLAGS += -D__M68K__
 PLATFORM_LDFLAGS  += -n
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
index d0e1a84..73d40bd 100644 (file)
@@ -5,9 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y   += board.o
-endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y  += cache.o
 obj-y  += interrupts.o
index 7dbb7c8..2b347cd 100644 (file)
 #include <errno.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <environment.h>
 
 #include "karo.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_UBOOT_IGNORE_ENV
+void env_cleanup(void)
+{
+       set_default_env(NULL);
+}
+#else
 static const char const *cleanup_vars[] = {
        "bootargs",
        "fileaddr",
@@ -40,3 +47,4 @@ void env_cleanup(void)
                setenv(cleanup_vars[i], NULL);
        }
 }
+#endif
index c6f4dcc..d43a117 100644 (file)
@@ -123,7 +123,7 @@ void karo_fdt_move_fdt(void)
                        fdt_addr, fdt_addr + fdt_totalsize(fdt) - 1);
                memmove((void *)fdt_addr, fdt, fdt_totalsize(fdt));
        }
-       set_working_fdt_addr((void *)fdt_addr);
+       set_working_fdt_addr(fdt_addr);
        gd->fdt_blob = fdt;
        karo_set_fdtsize(fdt);
 }
index 7c18a45..aad93e6 100644 (file)
@@ -15,50 +15,37 @@ config SYS_CONFIG_NAME
 config TX28
        bool
        default y
-       select SPL
        select SOC_MX28
+       select SPL
        select APBH_DMA
        select APBH_DMA_BURST
        select APBH_DMA_BURST8
        select CC_OPTIMIZE_LIBS_FOR_SPEED
-       select CMD_BMP if LCD
        select CMD_NAND_TRIMFFS if CMD_NAND
-       select CMD_ROMUPDATE if !SPL_BUILD
-       select FDT_FIXUP_PARTITIONS if OF_LIBFDT
+       select FDT_FIXUP_PARTITIONS
        select GET_FEC_MAC_ADDR_FROM_IIM if FEC_MXC
        select LIB_RAND
-       select MTD_PARTITIONS if CMD_NAND
-       select MTD_DEVICE if CMD_NAND
-       select SYS_NAND_USE_FLASH_BBT if NAND
-
-config TARGET_TX28_40X1_NOENV
-       bool
-       select TX28
+       select MTD_DEVICE
+       select MTD_PARTITIONS
+       select MXS_MMC if MMC
+       select NAND
+       select NAND_MXS
+       select OF_BOARD_SETUP
+       select OF_LIBFDT
+       select SYS_NAND_USE_FLASH_BBT
 
 config TARGET_TX28_40X2
        bool
        select TX28
 
-config TARGET_TX28_40X2_NOENV
-       bool
-       select TX28
-
 config TARGET_TX28_40X3
        bool
        select TX28
 
-config TARGET_TX28_40X3_NOENV
-       bool
-       select TX28
-
 config TARGET_TX28_41X0
        bool
        select TX28
 
-config TARGET_TX28_41X0_NOENV
-       bool
-       select TX28
-
 choice
        prompt "U-Boot image variant"
        default TX28_UBOOT
@@ -68,6 +55,7 @@ config TX28_UBOOT
 
 config TX28_UBOOT_NOENV
        bool "U-Boot using only built-in environment"
+       select UBOOT_IGNORE_ENV
 
 endchoice
 
index 0d3b1fd..1f65d69 100644 (file)
@@ -2,8 +2,6 @@
 CONFIG_SYS_TEXT_BASE := 0x40100000
 CONFIG_SPL_TEXT_BASE := 0x00000000
 
-__HAVE_ARCH_GENERIC_BOARD := y
-
 LOGO_BMP = logos/karo.bmp
 
 PLATFORM_CPPFLAGS += -Werror
index ea17d4c..87430d6 100644 (file)
@@ -12,4 +12,10 @@ config SYS_SOC
 config SYS_CONFIG_NAME
        default "tx48"
 
+config TX48
+       bool
+       default y
+       select PHYLIB
+       select SPL
+
 endif
index 51490f0..2d6ea0c 100644 (file)
@@ -1,6 +1,7 @@
 CONFIG_SYS_TEXT_BASE = 0x80800000
 ifneq ($(CONFIG_SPL_BUILD),)
        CONFIG_SPL_TEXT_BASE = 0x402F0400
+       PLATFORM_CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE)
 endif
 PLATFORM_CPPFLAGS += -Werror
 
index 2d71d49..7090817 100644 (file)
@@ -15,7 +15,7 @@
 #include <common.h>
 #include <errno.h>
 #include <miiphy.h>
-#include <netdev.h>
+#include <cpsw.h>
 #include <serial.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <linux/mtd/nand.h>
 #include <asm/gpio.h>
 #include <asm/cache.h>
-#include <asm/omap_common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/clocks_am33xx.h>
 #include <asm/arch/mem.h>
 #include <video_fb.h>
 #include <asm/arch/da8xx-fb.h>
 
 #include "flash.h"
 
-#define TX48_LED_GPIO          AM33XX_GPIO_NR(1, 26)
-#define TX48_ETH_PHY_RST_GPIO  AM33XX_GPIO_NR(3, 8)
-#define TX48_LCD_RST_GPIO      AM33XX_GPIO_NR(1, 19)
-#define TX48_LCD_PWR_GPIO      AM33XX_GPIO_NR(1, 22)
-#define TX48_LCD_BACKLIGHT_GPIO        AM33XX_GPIO_NR(3, 14)
-
-#define GMII_SEL               (CTRL_BASE + 0x650)
+DECLARE_GLOBAL_DATA_PTR;
 
-/* UART Defines */
-#define UART_SYSCFG_OFFSET     0x54
-#define UART_SYSSTS_OFFSET     0x58
+#define TX48_LCD_BACKLIGHT_GPIO        AM33XX_GPIO_NR(3, 14)
 
-#define UART_RESET             (0x1 << 1)
 #define UART_RESETDONE         (1 << 0)
 #define UART_IDLE_MODE(m)      (((m) << 3) & UART_IDLE_MODE_MASK)
 #define UART_IDLE_MODE_MASK    (0x3 << 3)
 
-/* Timer Defines */
-#define TSICR_REG              0x54
-#define TIOCP_CFG_REG          0x10
-#define TCLR_REG               0x38
-
-/* RGMII mode define */
-#define RGMII_MODE_ENABLE      0xA
-#define RMII_MODE_ENABLE       0x5
-#define MII_MODE_ENABLE                0x0
-
-#define NO_OF_MAC_ADDR         1
-#define ETH_ALEN               6
-
-/* PAD Control Fields */
-#define SLEWCTRL       (0x1 << 6)
-#define        RXACTIVE        (0x1 << 5)
-#define        PULLUP_EN       (0x1 << 4) /* Pull UP Selection */
-#define PULLUDEN       (0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS      (0x1 << 3) /* Pull up disabled */
-#define MODE(val)      (val)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-       int gpmc_ad0;
-       int gpmc_ad1;
-       int gpmc_ad2;
-       int gpmc_ad3;
-       int gpmc_ad4;
-       int gpmc_ad5;
-       int gpmc_ad6;
-       int gpmc_ad7;
-       int gpmc_ad8;
-       int gpmc_ad9;
-       int gpmc_ad10;
-       int gpmc_ad11;
-       int gpmc_ad12;
-       int gpmc_ad13;
-       int gpmc_ad14;
-       int gpmc_ad15;
-       int gpmc_a0;
-       int gpmc_a1;
-       int gpmc_a2;
-       int gpmc_a3;
-       int gpmc_a4;
-       int gpmc_a5;
-       int gpmc_a6;
-       int gpmc_a7;
-       int gpmc_a8;
-       int gpmc_a9;
-       int gpmc_a10;
-       int gpmc_a11;
-       int gpmc_wait0;
-       int gpmc_wpn;
-       int gpmc_be1n;
-       int gpmc_csn0;
-       int gpmc_csn1;
-       int gpmc_csn2;
-       int gpmc_csn3;
-       int gpmc_clk;
-       int gpmc_advn_ale;
-       int gpmc_oen_ren;
-       int gpmc_wen;
-       int gpmc_be0n_cle;
-       int lcd_data0;
-       int lcd_data1;
-       int lcd_data2;
-       int lcd_data3;
-       int lcd_data4;
-       int lcd_data5;
-       int lcd_data6;
-       int lcd_data7;
-       int lcd_data8;
-       int lcd_data9;
-       int lcd_data10;
-       int lcd_data11;
-       int lcd_data12;
-       int lcd_data13;
-       int lcd_data14;
-       int lcd_data15;
-       int lcd_vsync;
-       int lcd_hsync;
-       int lcd_pclk;
-       int lcd_ac_bias_en;
-       int mmc0_dat3;
-       int mmc0_dat2;
-       int mmc0_dat1;
-       int mmc0_dat0;
-       int mmc0_clk;
-       int mmc0_cmd;
-       int mii1_col;
-       int mii1_crs;
-       int mii1_rxerr;
-       int mii1_txen;
-       int mii1_rxdv;
-       int mii1_txd3;
-       int mii1_txd2;
-       int mii1_txd1;
-       int mii1_txd0;
-       int mii1_txclk;
-       int mii1_rxclk;
-       int mii1_rxd3;
-       int mii1_rxd2;
-       int mii1_rxd1;
-       int mii1_rxd0;
-       int rmii1_refclk;
-       int mdio_data;
-       int mdio_clk;
-       int spi0_sclk;
-       int spi0_d0;
-       int spi0_d1;
-       int spi0_cs0;
-       int spi0_cs1;
-       int ecap0_in_pwm0_out;
-       int uart0_ctsn;
-       int uart0_rtsn;
-       int uart0_rxd;
-       int uart0_txd;
-       int uart1_ctsn;
-       int uart1_rtsn;
-       int uart1_rxd;
-       int uart1_txd;
-       int i2c0_sda;
-       int i2c0_scl;
-       int mcasp0_aclkx;
-       int mcasp0_fsx;
-       int mcasp0_axr0;
-       int mcasp0_ahclkr;
-       int mcasp0_aclkr;
-       int mcasp0_fsr;
-       int mcasp0_axr1;
-       int mcasp0_ahclkx;
-       int xdma_event_intr0;
-       int xdma_event_intr1;
-       int nresetin_out;
-       int porz;
-       int nnmi;
-       int osc0_in;
-       int osc0_out;
-       int rsvd1;
-       int tms;
-       int tdi;
-       int tdo;
-       int tck;
-       int ntrst;
-       int emu0;
-       int emu1;
-       int osc1_in;
-       int osc1_out;
-       int pmic_power_en;
-       int rtc_porz;
-       int rsvd2;
-       int ext_wakeup;
-       int enz_kaldo_1p8v;
-       int usb0_dm;
-       int usb0_dp;
-       int usb0_ce;
-       int usb0_id;
-       int usb0_vbus;
-       int usb0_drvvbus;
-       int usb1_dm;
-       int usb1_dp;
-       int usb1_ce;
-       int usb1_id;
-       int usb1_vbus;
-       int usb1_drvvbus;
-       int ddr_resetn;
-       int ddr_csn0;
-       int ddr_cke;
-       int ddr_ck;
-       int ddr_nck;
-       int ddr_casn;
-       int ddr_rasn;
-       int ddr_wen;
-       int ddr_ba0;
-       int ddr_ba1;
-       int ddr_ba2;
-       int ddr_a0;
-       int ddr_a1;
-       int ddr_a2;
-       int ddr_a3;
-       int ddr_a4;
-       int ddr_a5;
-       int ddr_a6;
-       int ddr_a7;
-       int ddr_a8;
-       int ddr_a9;
-       int ddr_a10;
-       int ddr_a11;
-       int ddr_a12;
-       int ddr_a13;
-       int ddr_a14;
-       int ddr_a15;
-       int ddr_odt;
-       int ddr_d0;
-       int ddr_d1;
-       int ddr_d2;
-       int ddr_d3;
-       int ddr_d4;
-       int ddr_d5;
-       int ddr_d6;
-       int ddr_d7;
-       int ddr_d8;
-       int ddr_d9;
-       int ddr_d10;
-       int ddr_d11;
-       int ddr_d12;
-       int ddr_d13;
-       int ddr_d14;
-       int ddr_d15;
-       int ddr_dqm0;
-       int ddr_dqm1;
-       int ddr_dqs0;
-       int ddr_dqsn0;
-       int ddr_dqs1;
-       int ddr_dqsn1;
-       int ddr_vref;
-       int ddr_vtp;
-       int ddr_strben0;
-       int ddr_strben1;
-       int ain7;
-       int ain6;
-       int ain5;
-       int ain4;
-       int ain3;
-       int ain2;
-       int ain1;
-       int ain0;
-       int vrefp;
-       int vrefn;
-};
-
 struct pin_mux {
        short reg_offset;
        uint8_t val;
 };
 
-#define PAD_CTRL_BASE  0x800
-#define OFFSET(x)      (unsigned int) (&((struct pad_signals *) \
-                               (PAD_CTRL_BASE))->x)
+/*
+ * Configure the pin mux for the module
+ */
+static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
+                       int num_pins)
+{
+       int i;
+
+       for (i = 0; i < num_pins; i++)
+               writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
+}
 
 static struct pin_mux tx48_pins[] = {
-#ifdef CONFIG_CMD_NAND
+#ifdef CONFIG_NAND
        { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, },  /* NAND AD0 */
        { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, },  /* NAND AD1 */
        { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, },  /* NAND AD2 */
@@ -338,14 +102,6 @@ static struct pin_mux tx48_pins[] = {
        { OFFSET(emu0), MODE(7) | RXACTIVE},         /* nINT */
        { OFFSET(emu1), MODE(7), },                  /* nRST */
 #endif
-};
-
-static struct gpio tx48_gpios[] = {
-       /* configure this pin early to prevent flicker of the LCD */
-       { TX48_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
-};
-
-static struct pin_mux tx48_mmc_pins[] = {
 #ifdef CONFIG_OMAP_HSMMC
        /* MMC1 */
        { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */
@@ -358,19 +114,18 @@ static struct pin_mux tx48_mmc_pins[] = {
 #endif
 };
 
-/*
- * Configure the pin mux for the module
- */
-static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
-                       int num_pins)
-{
-       int i;
+static struct gpio tx48_gpios[] = {
+       /* configure this pin early to prevent flicker of the LCD */
+       { TX48_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
 
-       for (i = 0; i < num_pins; i++)
-               writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
+void set_mux_conf_regs(void)
+{
+       gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
+       tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins));
 }
 
-static struct pin_mux tx48_uart0_pins[] = {
+static struct pin_mux tx48_uart_pins[] = {
 #ifdef CONFIG_SYS_NS16550_COM1
        /* UART0 for early boot messages */
        { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */
@@ -397,14 +152,9 @@ static struct pin_mux tx48_uart0_pins[] = {
 /*
  * early system init of muxing and clocks.
  */
-static void enable_uart0_pin_mux(void)
-{
-       tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins));
-}
-
-static void enable_mmc0_pin_mux(void)
+void set_uart_mux_conf(void)
 {
-       tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins));
+       tx48_set_pin_mux(tx48_uart_pins, ARRAY_SIZE(tx48_uart_pins));
 }
 
 static const u32 gpmc_nand_cfg[GPMC_MAX_REG] = {
@@ -582,23 +332,20 @@ static inline int cl(u32 sdram_clk)
                (80 << 0) /* refr periods between ZQCS commands */ |    \
                0)
 
+#if 1
 static struct ddr_data tx48_ddr3_data = {
        /* reset defaults */
        .datardsratio0 = 0x04010040,
        .datawdsratio0 = 0x0,
        .datafwsratio0 = 0x0,
        .datawrsratio0 = 0x04010040,
-       .datadldiff0 = 0x4,
 };
 
 static struct cmd_control tx48_ddr3_cmd_ctrl_data = {
        /* reset defaults */
        .cmd0csratio = 0x80,
-       .cmd0dldiff = 0x04,
        .cmd1csratio = 0x80,
-       .cmd1dldiff = 0x04,
        .cmd2csratio = 0x80,
-       .cmd2dldiff = 0x04,
 };
 
 static void ddr3_calib_start(void)
@@ -638,7 +385,7 @@ static void ddr3_calib_start(void)
        debug("DDR3 calibration done\n");
 }
 
-static void tx48_ddr_init(void)
+void sdram_init(void)
 {
        struct emif_regs r = {0};
 
@@ -652,14 +399,15 @@ static void tx48_ddr_init(void)
        r.zq_config = ZQ_CONFIG_VAL;
        r.emif_ddr_phy_ctlr_1 = 0x0000030b;
 
-       config_ddr(SDRAM_CLK, 0x04, &tx48_ddr3_data,
+       config_ddr(SDRAM_CLK, NULL, &tx48_ddr3_data,
                &tx48_ddr3_cmd_ctrl_data, &r, 0);
 
        ddr3_calib_start();
 
        debug("%s: config_ddr done\n", __func__);
 }
-
+#endif
+#if 0
 #ifdef CONFIG_HW_WATCHDOG
 static inline void tx48_wdog_disable(void)
 {
@@ -680,58 +428,22 @@ static inline void tx48_wdog_disable(void)
                ;
 }
 #endif
+#endif
 
-void s_init(void)
-{
-       struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-       struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
-       int timeout = 1000;
-
-       gd = &gdata;
-
-       /*
-         * Save the boot parameters passed from romcode.
-         * We cannot delay the saving further than this,
-         * to prevent overwrites.
-         */
-       save_omap_boot_params();
-
-       /* Setup the PLLs and the clocks for the peripherals */
-       pll_init();
-
-       tx48_wdog_disable();
-
-       enable_uart0_pin_mux();
-
-       /* UART softreset */
-       writel(readl(&uart_base->uartsyscfg) | UART_RESET,
-               &uart_base->uartsyscfg);
-       while (!(readl(&uart_base->uartsyssts) & UART_RESETDONE)) {
-               udelay(1);
-               if (timeout-- <= 0)
-                       break;
-       }
-
-       /* Disable smart idle */
-       writel((readl(&uart_base->uartsyscfg) & ~UART_IDLE_MODE_MASK) |
-               UART_IDLE_MODE(1), &uart_base->uartsyscfg);
-
-       preloader_console_init();
-
-       if (timeout <= 0)
-               printf("Timeout waiting for UART RESET\n");
+#define OSC     (V_OSCK/1000000)
+static const struct dpll_params tx48_ddr_params = {
+       266, OSC-1, 1, -1, -1, -1, -1,
+};
 
-       timer_init();
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+       return &tx48_ddr_params;
+}
 
-       tx48_ddr_init();
+void am33xx_spl_board_init(void)
+{
+       struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
 
-       gpmc_init();
        enable_gpmc_cs_config(gpmc_nand_cfg, &gpmc_cfg->cs[0],
                        CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_SIZE);
-
-       /* Enable MMC0 */
-       enable_mmc0_pin_mux();
-
-       gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
-       tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins));
 }
index 95a98a9..028cfa8 100644 (file)
@@ -17,7 +17,7 @@
 #include <common.h>
 #include <errno.h>
 #include <miiphy.h>
-#include <netdev.h>
+#include <cpsw.h>
 #include <serial.h>
 #include <libfdt.h>
 #include <lcd.h>
 #include <linux/fb.h>
 #include <asm/gpio.h>
 #include <asm/cache.h>
-#include <asm/omap_common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/clock.h>
 #include <video_fb.h>
@@ -49,249 +49,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX48_LCD_BACKLIGHT_GPIO        AM33XX_GPIO_NR(3, 14)
 #define TX48_MMC_CD_GPIO       AM33XX_GPIO_NR(3, 15)
 
-#define GMII_SEL               (CTRL_BASE + 0x650)
-
-/* UART Defines */
-#define UART_SYSCFG_OFFSET     0x54
-#define UART_SYSSTS_OFFSET     0x58
-
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-
-/* Timer Defines */
-#define TSICR_REG              0x54
-#define TIOCP_CFG_REG          0x10
-#define TCLR_REG               0x38
-
-/* RGMII mode define */
-#define RGMII_MODE_ENABLE      0xA
-#define RMII_MODE_ENABLE       0x5
-#define MII_MODE_ENABLE                0x0
-
 #define NO_OF_MAC_ADDR         1
+#ifndef ETH_ALEN
 #define ETH_ALEN               6
-
-/* PAD Control Fields */
-#define SLEWCTRL       (0x1 << 6)
-#define        RXACTIVE        (0x1 << 5)
-#define        PULLUP_EN       (0x1 << 4) /* Pull UP Selection */
-#define PULLUDEN       (0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS      (0x1 << 3) /* Pull up disabled */
-#define MODE(val)      (val)
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-       int gpmc_ad0;
-       int gpmc_ad1;
-       int gpmc_ad2;
-       int gpmc_ad3;
-       int gpmc_ad4;
-       int gpmc_ad5;
-       int gpmc_ad6;
-       int gpmc_ad7;
-       int gpmc_ad8;
-       int gpmc_ad9;
-       int gpmc_ad10;
-       int gpmc_ad11;
-       int gpmc_ad12;
-       int gpmc_ad13;
-       int gpmc_ad14;
-       int gpmc_ad15;
-       int gpmc_a0;
-       int gpmc_a1;
-       int gpmc_a2;
-       int gpmc_a3;
-       int gpmc_a4;
-       int gpmc_a5;
-       int gpmc_a6;
-       int gpmc_a7;
-       int gpmc_a8;
-       int gpmc_a9;
-       int gpmc_a10;
-       int gpmc_a11;
-       int gpmc_wait0;
-       int gpmc_wpn;
-       int gpmc_be1n;
-       int gpmc_csn0;
-       int gpmc_csn1;
-       int gpmc_csn2;
-       int gpmc_csn3;
-       int gpmc_clk;
-       int gpmc_advn_ale;
-       int gpmc_oen_ren;
-       int gpmc_wen;
-       int gpmc_be0n_cle;
-       int lcd_data0;
-       int lcd_data1;
-       int lcd_data2;
-       int lcd_data3;
-       int lcd_data4;
-       int lcd_data5;
-       int lcd_data6;
-       int lcd_data7;
-       int lcd_data8;
-       int lcd_data9;
-       int lcd_data10;
-       int lcd_data11;
-       int lcd_data12;
-       int lcd_data13;
-       int lcd_data14;
-       int lcd_data15;
-       int lcd_vsync;
-       int lcd_hsync;
-       int lcd_pclk;
-       int lcd_ac_bias_en;
-       int mmc0_dat3;
-       int mmc0_dat2;
-       int mmc0_dat1;
-       int mmc0_dat0;
-       int mmc0_clk;
-       int mmc0_cmd;
-       int mii1_col;
-       int mii1_crs;
-       int mii1_rxerr;
-       int mii1_txen;
-       int mii1_rxdv;
-       int mii1_txd3;
-       int mii1_txd2;
-       int mii1_txd1;
-       int mii1_txd0;
-       int mii1_txclk;
-       int mii1_rxclk;
-       int mii1_rxd3;
-       int mii1_rxd2;
-       int mii1_rxd1;
-       int mii1_rxd0;
-       int rmii1_refclk;
-       int mdio_data;
-       int mdio_clk;
-       int spi0_sclk;
-       int spi0_d0;
-       int spi0_d1;
-       int spi0_cs0;
-       int spi0_cs1;
-       int ecap0_in_pwm0_out;
-       int uart0_ctsn;
-       int uart0_rtsn;
-       int uart0_rxd;
-       int uart0_txd;
-       int uart1_ctsn;
-       int uart1_rtsn;
-       int uart1_rxd;
-       int uart1_txd;
-       int i2c0_sda;
-       int i2c0_scl;
-       int mcasp0_aclkx;
-       int mcasp0_fsx;
-       int mcasp0_axr0;
-       int mcasp0_ahclkr;
-       int mcasp0_aclkr;
-       int mcasp0_fsr;
-       int mcasp0_axr1;
-       int mcasp0_ahclkx;
-       int xdma_event_intr0;
-       int xdma_event_intr1;
-       int nresetin_out;
-       int porz;
-       int nnmi;
-       int osc0_in;
-       int osc0_out;
-       int rsvd1;
-       int tms;
-       int tdi;
-       int tdo;
-       int tck;
-       int ntrst;
-       int emu0;
-       int emu1;
-       int osc1_in;
-       int osc1_out;
-       int pmic_power_en;
-       int rtc_porz;
-       int rsvd2;
-       int ext_wakeup;
-       int enz_kaldo_1p8v;
-       int usb0_dm;
-       int usb0_dp;
-       int usb0_ce;
-       int usb0_id;
-       int usb0_vbus;
-       int usb0_drvvbus;
-       int usb1_dm;
-       int usb1_dp;
-       int usb1_ce;
-       int usb1_id;
-       int usb1_vbus;
-       int usb1_drvvbus;
-       int ddr_resetn;
-       int ddr_csn0;
-       int ddr_cke;
-       int ddr_ck;
-       int ddr_nck;
-       int ddr_casn;
-       int ddr_rasn;
-       int ddr_wen;
-       int ddr_ba0;
-       int ddr_ba1;
-       int ddr_ba2;
-       int ddr_a0;
-       int ddr_a1;
-       int ddr_a2;
-       int ddr_a3;
-       int ddr_a4;
-       int ddr_a5;
-       int ddr_a6;
-       int ddr_a7;
-       int ddr_a8;
-       int ddr_a9;
-       int ddr_a10;
-       int ddr_a11;
-       int ddr_a12;
-       int ddr_a13;
-       int ddr_a14;
-       int ddr_a15;
-       int ddr_odt;
-       int ddr_d0;
-       int ddr_d1;
-       int ddr_d2;
-       int ddr_d3;
-       int ddr_d4;
-       int ddr_d5;
-       int ddr_d6;
-       int ddr_d7;
-       int ddr_d8;
-       int ddr_d9;
-       int ddr_d10;
-       int ddr_d11;
-       int ddr_d12;
-       int ddr_d13;
-       int ddr_d14;
-       int ddr_d15;
-       int ddr_dqm0;
-       int ddr_dqm1;
-       int ddr_dqs0;
-       int ddr_dqsn0;
-       int ddr_dqs1;
-       int ddr_dqsn1;
-       int ddr_vref;
-       int ddr_vtp;
-       int ddr_strben0;
-       int ddr_strben1;
-       int ain7;
-       int ain6;
-       int ain5;
-       int ain4;
-       int ain3;
-       int ain2;
-       int ain1;
-       int ain0;
-       int vrefp;
-       int vrefn;
-};
+#endif
 
 struct pin_mux {
        short reg_offset;
@@ -411,6 +172,10 @@ vidinfo_t panel_info = {
        .cmap = tx48_cmap,
 };
 
+static struct lcd_ctrl_config lcd_cfg = {
+       .bpp = 24,
+};
+
 #define FB_SYNC_OE_LOW_ACT     (1 << 31)
 #define FB_SYNC_CLK_LAT_FALL   (1 << 30)
 
@@ -803,7 +568,7 @@ void lcd_ctrl_init(void *lcdbase)
 
                debug("Initializing FB driver\n");
                tx48_lcd_panel_setup(&da8xx_panel, p);
-               da8xx_video_init(&da8xx_panel, color_depth);
+               da8xx_video_init(&da8xx_panel, &lcd_cfg, color_depth);
 
                debug("Initializing LCD controller\n");
                video_hw_init();
@@ -1032,7 +797,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
        {
                .slave_reg_ofs  = 0x208,
                .sliver_reg_ofs = 0xd80,
-               .phy_id         = 0,
+               .phy_addr       = 0,
                .phy_if         = PHY_INTERFACE_MODE_RMII,
        },
 };
@@ -1056,7 +821,6 @@ static struct cpsw_platform_data cpsw_data = {
        .hw_stats_reg_ofs       = 0x900,
        .mac_control            = (1 << 5) /* MIIEN */,
        .control                = cpsw_control,
-       .gigabit_en             = 0,
        .host_port_num          = 0,
        .version                = CPSW_CTRL_VERSION_2,
 };
@@ -1064,7 +828,6 @@ static struct cpsw_platform_data cpsw_data = {
 int board_eth_init(bd_t *bis)
 {
        __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
-       __raw_writel(0x5D, GMII_SEL);
        tx48_phy_init();
        return cpsw_register(&cpsw_data);
 }
index 493cc55..44e24d2 100644 (file)
@@ -74,8 +74,6 @@ SECTIONS
                *(.__rel_dyn_end)
        }
 
-       _end = .;
-
 /*
  * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
  * __bss_base and __bss_limit are for linker only (overlay ordering)
index 8f01051..cfdc540 100644 (file)
@@ -1,4 +1,4 @@
-if TARGET_TX51_8XX0
+if TARGET_TX51
 
 config SYS_BOARD
        default "tx51"
@@ -10,22 +10,66 @@ config SYS_SOC
        default "mx5"
 
 config SYS_CONFIG_NAME
-       default "tx51-8xx0"
+       default "tx51"
 
-endif
+config TX51
+       bool
+       default y
+       select CC_OPTIMIZE_LIBS_FOR_SPEED
+       select CMD_BMP if LCD
+       select CMD_BOOTCE
+       select CMD_BOOTZ
+       select CMD_CACHE
+       select CMD_MEMINFO
+       select CMD_MEMTEST
+       select CMD_MMC
+       select CMD_NAND
+       select CMD_NAND_TRIMFFS
+       select CMD_ROMUPDATE
+       select CMD_TIME
+       select DM
+       select DM_GPIO
+       select FDT_FIXUP_PARTITIONS if OF_LIBFDT
+       select GET_FEC_MAC_ADDR_FROM_IIM
+       select IMX_WATCHDOG
+       select LIB_RAND
+       select MMC
+       select MTD_PARTITIONS
+       select MTD_DEVICE
+       select NAND
+       select NAND_MXC
+       select OF_LIBFDT
+       select OF_BOARD_SETUP
+       select PHYLIB
+       select PHY_SMSC
+       select SOC_MX51
+       select SYS_NAND_USE_FLASH_BBT if NAND_MXC
 
-if TARGET_TX51_8XX1_2
+choice
+       prompt "TX51 module variant"
 
-config SYS_BOARD
-       default "tx51"
+config TARGET_TX51_8XX0
+       bool "TX51-8010 and TX51-8110"
 
-config SYS_VENDOR
-       default "karo"
+config TARGET_TX51_8XX1_2
+       bool "TX51-8021, TX51-8021, TX51-8022 and TX51-8122"
 
-config SYS_SOC
-       default "mx5"
+endchoice
 
-config SYS_CONFIG_NAME
-       default "tx51-8xx1_2"
+config NR_DRAM_BANKS
+       int
+       default 1
+
+choice
+       prompt "U-Boot image variant"
+
+config TX51_UBOOT
+       bool "Standard U-Boot image"
+
+config TX51_UBOOT_NOENV
+       bool "U-Boot using only built-in environment"
+       select UBOOT_IGNORE_ENV
+
+endchoice
 
 endif
index 7c9ca89..1ede960 100644 (file)
@@ -68,8 +68,6 @@ SECTIONS
                *(.__rel_dyn_end)
        }
 
-       _end = .;
-
 /*
  * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
  * __bss_base and __bss_limit are for linker only (overlay ordering)
index 2c30f58..631ac67 100644 (file)
@@ -87,7 +87,7 @@ config TX53_UBOOT
 
 config TX53_UBOOT_NOENV
        bool "U-Boot using only built-in environment"
-       select ENV_IS_NOWHERE
+       select UBOOT_IGNORE_ENV
 
 endchoice
 
index 091efde..702fc0c 100644 (file)
@@ -15,44 +15,41 @@ config SYS_CONFIG_NAME
 config TX6
        bool
        default y
-       select CMD_BMP if LCD
-       select CMD_BOOTCE
-       select CMD_BOOTZ
-       select CMD_CACHE
-       select CMD_I2C if I2C
-       select CMD_MEMTEST
-       select CMD_MMC
-       select CMD_TIME
+       select APBH_DMA
+       select APBH_DMA_BURST
+       select APBH_DMA_BURST8
+       select CC_OPTIMIZE_LIBS_FOR_SPEED
        select DM
        select DM_GPIO
+       select DM_THERMAL
+       select FSL_ESDHC if MMC
+       select FSL_USDHC if MMC
        select LIB_RAND
        select PHYLIB
        select SYS_I2C
        select SYS_I2C_MXC
-       select GET_FEC_MAC_ADDR_FROM_IIM
+       select GET_FEC_MAC_ADDR_FROM_IIM if FEC_MXC
+       select MXC_OCOTP if CMD_FUSE
        select OF_BOARD_SETUP
        select OF_LIBFDT
 
 config TX6_NAND
        bool
        default ! TX6_EMMC
-       select CMD_NAND
-       select CMD_NAND_TRIMFFS
-       select CMD_MTDPARTS
+       select CMD_NAND_TRIMFFS if CMD_NAND
        select CMD_ROMUPDATE
-       select FDT_FIXUP_PARTITIONS if OF_LIBFDT
+       select FDT_FIXUP_PARTITIONS
+       select MTD_DEVICE
        select MTD_PARTITIONS
        select NAND
        select NAND_MXS
        select NAND_MXS_NO_BBM_SWAP
        select SYS_NAND_USE_FLASH_BBT
-       select APBH_DMA
-       select APBH_DMA_BURST
-       select APBH_DMA_BURST8
-       select MTD_DEVICE
 
 config TX6_EMMC
        bool
+       select CMD_MMC
+       select MMC
        select SUPPORT_EMMC_BOOT
 
 #
@@ -71,15 +68,20 @@ config SYS_SDRAM_BUS_WIDTH_32
 choice
        prompt "TX6 module variant"
 
-config TARGET_TX6Q_10X0
-       bool "TX6Q-1010 and TX6Q-1030"
-       select SOC_MX6Q
-
 config TARGET_TX6Q_1020
        bool "TX6Q-1020"
        select SOC_MX6Q
        select TX6_EMMC
 
+config TARGET_TX6Q_1033
+       bool "TX6Q-1033"
+       select SOC_MX6Q
+       select TX6_EMMC
+
+config TARGET_TX6Q_10X0
+       bool "TX6Q-1010 and TX6Q-1030"
+       select SOC_MX6Q
+
 config TARGET_TX6Q_11X0
        bool "TX6Q-1110 and TX6Q-1130"
        select SOC_MX6Q
@@ -96,10 +98,6 @@ config TARGET_TX6S_8035
        select TX6_EMMC
        select SYS_SDRAM_BUS_WIDTH_32
 
-config TARGET_TX6U_80X0
-       bool "TX6U-8010 and TX6U-8030"
-       select SOC_MX6DL
-
 config TARGET_TX6U_8011
        bool "TX6U-8011"
        select SOC_MX6DL
@@ -109,10 +107,14 @@ config TARGET_TX6U_8012
        bool "TX6U-8012"
        select SOC_MX6DL
 
-config TARGET_TX6U_81X0
-       bool "TX6U-8110 and TX6U-8130"
+config TARGET_TX6U_8033
+       bool "TX6U-8033"
+       select SOC_MX6DL
+       select TX6_EMMC
+
+config TARGET_TX6U_80X0
+       bool "TX6U-8010 and TX6U-8030"
        select SOC_MX6DL
-       select SYS_LVDS_IF
 
 config TARGET_TX6U_8111
        bool "TX6U-8111"
@@ -120,10 +122,10 @@ config TARGET_TX6U_8111
        select SYS_SDRAM_BUS_WIDTH_32
        select SYS_LVDS_IF
 
-config TARGET_TX6U_8033
-       bool "TX6U-8033"
+config TARGET_TX6U_81X0
+       bool "TX6U-8110 and TX6U-8130"
        select SOC_MX6DL
-       select TX6_EMMC
+       select SYS_LVDS_IF
 
 endchoice
 
@@ -139,6 +141,7 @@ config TX6_UBOOT_MFG
 
 config TX6_UBOOT_NOENV
        bool "U-Boot using only built-in environment"
+       select UBOOT_IGNORE_ENV
 
 endchoice
 
index acb0cd0..42a4b1a 100644 (file)
@@ -1,7 +1,9 @@
 # stack is allocated below CONFIG_SYS_TEXT_BASE
-#CONFIG_SYS_TEXT_BASE := 0x10100000
-#CONFIG_SYS_TEXT_BASE := 0x177ff000
-CONFIG_SYS_TEXT_BASE := 0x100ff000
+ifeq ($(CONFIG_SOC_MX6SX)$(CONFIG_SOC_MX6SL)$(CONFIG_SOC_MX6UL),)
+       CONFIG_SYS_TEXT_BASE := 0x100ff000
+else
+       CONFIG_SYS_TEXT_BASE := 0x800ff000
+endif
 
 OBJCOPYFLAGS += -j .pad
 
@@ -9,9 +11,11 @@ LOGO_BMP = logos/karo.bmp
 #PLATFORM_CPPFLAGS += -DDEBUG
 #PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable
 PLATFORM_CPPFLAGS += -Werror
+
 ifneq ($(CONFIG_SECURE_BOOT),)
        PLATFORM_CPPFLAGS += -DCONFIG_SECURE_BOOT
 endif
+#PLATFORM_CPPFLAGS += -DDEBUG
 
 ifeq ($(CONFIG_TX6_NAND),y)
 # calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size
index 561a1d1..5999113 100644 (file)
@@ -596,7 +596,7 @@ ivt_end:
 
 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0898
 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e089c
-#define TX6_I2C1_SEL_INP_VAL                   1
+#define TX6_I2C1_SEL_INP_VAL                   0
 #endif
 
 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
index 1a5026d..090ade1 100644 (file)
@@ -125,6 +125,17 @@ static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
        MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 };
 
+#define TX6_I2C_GPIO_PAD_CTRL  (PAD_CTL_PUS_22K_UP |   \
+                               PAD_CTL_SPEED_MED |     \
+                               PAD_CTL_DSE_34ohm |     \
+                               PAD_CTL_SRE_FAST)
+
+static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
+       /* internal I2C */
+       MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
+       MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
+};
+
 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
        /* internal I2C */
        MX6_PAD_EIM_D28__I2C1_SDA,
@@ -142,9 +153,93 @@ static const struct gpio const tx6qdl_gpios[] = {
        { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 };
 
-/*
- * Functions
- */
+static int pmic_addr __data;
+
+#if defined(CONFIG_SOC_MX6Q)
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e00a4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e00c4
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e03b8
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e03d8
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0898
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e089c
+#define I2C1_SEL_INPUT_VAL                     0
+#endif
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e0158
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e0174
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e0528
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e0544
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0868
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e086c
+#define I2C1_SEL_INPUT_VAL                     1
+#endif
+
+#define GPIO_DR 0
+#define GPIO_DIR 4
+#define GPIO_PSR 8
+
+static void tx6_i2c_recover(void)
+{
+       int i;
+       int bad = 0;
+#define SCL_BIT                (1 << (TX6_I2C1_SCL_GPIO % 32))
+#define SDA_BIT                (1 << (TX6_I2C1_SDA_GPIO % 32))
+
+       if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
+                       (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
+               return;
+
+       debug("Clearing I2C bus\n");
+       if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
+               printf("I2C SCL stuck LOW\n");
+               bad++;
+
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DR);
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DIR);
+       }
+       if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
+               printf("I2C SDA stuck LOW\n");
+               bad++;
+
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DIR);
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DR);
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DIR);
+
+               imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
+                                               ARRAY_SIZE(tx6_i2c_gpio_pads));
+               udelay(10);
+
+               for (i = 0; i < 18; i++) {
+                       u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
+
+                       debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
+                       writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+                       udelay(10);
+                       if (reg & SCL_BIT &&
+                               readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
+                               break;
+               }
+       }
+       if (bad) {
+               u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
+
+               if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
+                       printf("I2C bus recovery succeeded\n");
+               } else {
+                       printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
+                               SCL_BIT | SDA_BIT);
+               }
+       }
+       debug("Setting up I2C Pads\n");
+       imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
+                                       ARRAY_SIZE(tx6_i2c_pads));
+}
+
 /* placed in section '.data' to prevent overwriting relocation info
  * overlayed with bss
  */
@@ -208,7 +303,7 @@ static void print_reset_cause(void)
 
 static const char __data *tx6_mod_suffix;
 
-static void tx6qdl_print_cpuinfo(void)
+int checkboard(void)
 {
        u32 cpurev = get_cpu_rev();
        char *cpu_str = "?";
@@ -242,10 +337,14 @@ static void tx6qdl_print_cpuinfo(void)
 #ifdef CONFIG_MX6_TEMPERATURE_HOT
        check_cpu_temperature(1);
 #endif
+       tx6_i2c_recover();
+       return 0;
 }
 
 int board_early_init_f(void)
 {
+       debug("%s@%d: \n", __func__, __LINE__);
+
        return 0;
 }
 
@@ -254,155 +353,129 @@ static bool tx6_temp_check_enabled = true;
 #else
 #define tx6_temp_check_enabled 0
 #endif
-static int pmic_addr __data;
 
-#if defined(CONFIG_SOC_MX6Q)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e00a4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e00c4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e03b8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e03d8
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0898
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e089c
-#define I2C1_SEL_INPUT_VAL                     0
-#endif
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e0158
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e0174
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e0528
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e0544
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0868
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e086c
-#define I2C1_SEL_INPUT_VAL                     1
+#ifdef CONFIG_TX6_NAND
+#define TX6_FLASH_SZ   (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
+#else
+#ifdef CONFIG_MMC_BOOT_SIZE
+#define TX6_FLASH_SZ   (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
+#else
+#define TX6_FLASH_SZ   2
 #endif
+#endif /* CONFIG_TX6_NAND */
 
-#define GPIO_DR 0
-#define GPIO_DIR 4
-#define GPIO_PSR 8
+#define TX6_DDR_SZ     (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
 
-static const struct i2c_gpio_regs {
-       const char *label;
-       u32 gpio;
-       unsigned long gpio_base;
-       unsigned long muxctl;
-       unsigned long padctl;
-       unsigned long sel_input;
-} tx6_i2c_iomux_regs[] = {
-       {
-               .label = "PMIC SCL",
-               .gpio = TX6_I2C1_SCL_GPIO,
-               .gpio_base = GPIO3_BASE_ADDR,
-               .muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21,
-               .padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21,
-               .sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21,
-       }, {
-               .label = "PMIC SDA",
-               .gpio = TX6_I2C1_SDA_GPIO,
-               .gpio_base = GPIO3_BASE_ADDR,
-               .muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28,
-               .padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28,
-               .sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28,
-       },
+static char tx6_mem_table[] = {
+       '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
+       '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
+       '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
+       '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
+       '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
+       '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
+       '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
+       '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
+       '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
+       '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
+       '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
+       '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
 };
 
-static inline u32 __tx6_readl(void *addr,
-                       const char *fn, int ln)
+static struct {
+       uchar addr;
+       uchar rev;
+} tx6_mod_revs[] = {
+       { 0x3c, 1, },
+       { 0x32, 2, },
+       { 0x33, 3, },
+};
+
+static inline char tx6_mem_suffix(void)
 {
-       u32 val = readl(addr);
-       debug("%s@%d: read %08x from %p\n", fn, ln, val, addr);
-       return val;
-}
-#undef readl
-#define readl(a)       __tx6_readl((void *)(a), __func__, __LINE__)
+       size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
+
+       debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
+               TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
+
+       if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
+               return '?';
 
-static inline void __tx6_writel(u32 val, void *addr,
-                               const char *fn, int ln)
+       return tx6_mem_table[mem_idx];
+};
+
+static int tx6_get_mod_rev(unsigned int pmic_id)
 {
-       debug("%s@%d: writing %08x to %p\n", fn, ln, val, addr);
-       writel(val, addr);
+       if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
+               return tx6_mod_revs[pmic_id].rev;
+
+       return 0;
 }
-#undef writel
-#define writel(v, a)   __tx6_writel(v, (void *)(a), __func__, __LINE__)
 
-static void tx6_i2c_recover(void)
+static int tx6_pmic_probe(void)
 {
        int i;
-       int bad = 0;
-       int failed = 0;
-#define MAX_TRIES 100
 
-       debug("Clearing I2C bus\n");
+       debug("%s@%d: \n", __func__, __LINE__);
 
-       for (i = 0; i < ARRAY_SIZE(tx6_i2c_iomux_regs); i++) {
-               int gpio = tx6_i2c_iomux_regs[i].gpio;
-               u32 gpio_mask = 1 << (gpio % 32);
-
-               void *gpio_base = (void *)tx6_i2c_iomux_regs[i].gpio_base;
-
-               if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) {
-                       int retries = MAX_TRIES;
-
-                       bad++;
-                       printf("%s (GPIO%u_%u) is not HIGH\n",
-                               tx6_i2c_iomux_regs[i].label,
-                               gpio / 32 + 1, gpio % 32);
-                       writel(readl(gpio_base + GPIO_DR) | gpio_mask,
-                               gpio_base + GPIO_DR);
-                       writel(readl(gpio_base + GPIO_DIR) | gpio_mask,
-                               gpio_base + GPIO_DIR);
-                       writel(0x15, tx6_i2c_iomux_regs[i].muxctl);
-                       writel(0x0f079, tx6_i2c_iomux_regs[i].padctl);
-                       writel(I2C1_SEL_INPUT_VAL, tx6_i2c_iomux_regs[i].sel_input);
-                       if ((readl(gpio_base + GPIO_DR) & gpio_mask) == 0)
-                               hang();
-                       if ((readl(gpio_base + GPIO_DIR) & gpio_mask) == 0)
-                               hang();
-                       while ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0 &&
-                               retries-- > 0) {
-                               udelay(100);
-                       }
-                       writel(readl(gpio_base + GPIO_DIR) & ~gpio_mask,
-                               gpio_base + GPIO_DIR);
-
-                       if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) {
-                               printf("Failed to force %s (GPIO%u_%u) HIGH\n",
-                                       tx6_i2c_iomux_regs[i].label,
-                                       gpio / 32 + 1, gpio % 32);
-                               failed++;
-                       } else if (retries < MAX_TRIES) {
-                               printf("%s (GPIO%u_%u) forced HIGH after %u loops\n",
-                                       tx6_i2c_iomux_regs[i].label,
-                                       gpio / 32 + 1, gpio % 32,
-                                       MAX_TRIES - retries);
-                       }
-               } else {
-                       debug("%s (GPIO%u_%u) is HIGH\n",
-                               tx6_i2c_iomux_regs[i].label,
-                               gpio / 32 + 1, gpio % 32);
+//     i2c_init_all();
+
+       for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
+               u8 i2c_addr = tx6_mod_revs[i].addr;
+               int ret = i2c_probe(i2c_addr);
+
+               if (ret == 0) {
+                       debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
+                       return i;
                }
+               debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
        }
-       debug("Setting up I2C Pads\n");
-       imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
-                                       ARRAY_SIZE(tx6_i2c_pads));
-       if (bad) {
-               if (failed)
-                       printf("I2C bus recovery FAILED\n");
-               else
-                       printf("I2C bus recovery succeeded\n");
-       }
+       return -EINVAL;
 }
 
-#define pr_reg(b, n)   debug("%12s@%p=%08x\n", #n, (void *)(b) + (n), readl((b) + (n)))
-
-static inline void dump_regs(void)
+static inline int __checkboard(void)
 {
-       pr_reg(GPIO3_BASE_ADDR, GPIO_DR);
-       pr_reg(GPIO3_BASE_ADDR, GPIO_DIR);
-       pr_reg(GPIO3_BASE_ADDR, GPIO_PSR);
+       u32 cpurev = get_cpu_rev();
+       int cpu_variant = (cpurev >> 12) & 0xff;
+       int pmic_id;
+
+       debug("%s@%d: \n", __func__, __LINE__);
+
+       pmic_id = tx6_pmic_probe();
+       if (pmic_id >= 0)
+               pmic_addr = tx6_mod_revs[pmic_id].addr;
+
+       printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
+               tx6_mod_suffix,
+               cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
+               is_lvds(), tx6_get_mod_rev(pmic_id),
+               tx6_mem_suffix());
+
+       get_hab_status();
+
+       debug("%s@%d: done\n", __func__, __LINE__);
+       return 0;
 }
 
 int board_init(void)
 {
        int ret;
+       u32 cpurev = get_cpu_rev();
+       int cpu_variant = (cpurev >> 12) & 0xff;
+       int pmic_id;
+
+       debug("%s@%d: \n", __func__, __LINE__);
+
+       pmic_id = tx6_pmic_probe();
+       if (pmic_id >= 0)
+               pmic_addr = tx6_mod_revs[pmic_id].addr;
+
+       printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
+               tx6_mod_suffix,
+               cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
+               is_lvds(), tx6_get_mod_rev(pmic_id),
+               tx6_mem_suffix());
+
+       get_hab_status();
 
        ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
        if (ret < 0) {
@@ -435,6 +508,8 @@ int board_init(void)
 
 int dram_init(void)
 {
+       debug("%s@%d: \n", __func__, __LINE__);
+
        /* dram_init must store complete ramsize in gd->ram_size */
        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
                                PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
@@ -443,6 +518,8 @@ int dram_init(void)
 
 void dram_init_banksize(void)
 {
+       debug("%s@%d: \n", __func__, __LINE__);
+
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
                        PHYS_SDRAM_1_SIZE);
@@ -558,6 +635,8 @@ int board_mmc_init(bd_t *bis)
 {
        int i;
 
+       debug("%s@%d: \n", __func__, __LINE__);
+
        for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
                struct mmc *mmc;
                struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
@@ -591,11 +670,6 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_FEC_MXC
 
-#define FEC_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
-                       PAD_CTL_SRE_FAST)
-#define FEC_PAD_CTL2   (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
-#define GPIO_PAD_CTL   (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
 #ifndef ETH_ALEN
 #define ETH_ALEN 6
 #endif
@@ -604,6 +678,8 @@ int board_eth_init(bd_t *bis)
 {
        int ret;
 
+       debug("%s@%d: \n", __func__, __LINE__);
+
        /* delay at least 21ms for the PHY internal POR signal to deassert */
        udelay(22000);
 
@@ -1301,6 +1377,8 @@ int board_late_init(void)
        writel(0x12, &fuse->cfg5);
 #endif
 
+       debug("%s@%d: \n", __func__, __LINE__);
+
        env_cleanup();
 
        if (tx6_temp_check_enabled)
@@ -1352,106 +1430,6 @@ exit:
        return ret;
 }
 
-#ifdef CONFIG_TX6_NAND
-#define TX6_FLASH_SZ   (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
-#else
-#ifdef CONFIG_MMC_BOOT_SIZE
-#define TX6_FLASH_SZ   (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
-#else
-#define TX6_FLASH_SZ   2
-#endif
-#endif /* CONFIG_TX6_NAND */
-
-#define TX6_DDR_SZ     (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
-
-static char tx6_mem_table[] = {
-       '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
-       '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
-       '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
-       '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
-       '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
-       '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
-       '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
-       '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
-       '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
-       '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
-       '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
-       '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
-};
-
-static inline char tx6_mem_suffix(void)
-{
-       size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
-
-       debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
-               TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
-
-       if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
-               return '?';
-
-       return tx6_mem_table[mem_idx];
-};
-
-static struct {
-       uchar addr;
-       uchar rev;
-} tx6_mod_revs[] = {
-       { 0x3c, 1, },
-       { 0x32, 2, },
-       { 0x33, 3, },
-};
-
-static int tx6_get_mod_rev(unsigned int pmic_id)
-{
-       if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
-               return tx6_mod_revs[pmic_id].rev;
-
-       return 0;
-}
-
-static int tx6_pmic_probe(void)
-{
-       int i;
-
-       tx6_i2c_recover();
-       i2c_init_all();
-
-       for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
-               u8 i2c_addr = tx6_mod_revs[i].addr;
-               int ret = i2c_probe(i2c_addr);
-
-               if (ret == 0) {
-                       debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
-                       return i;
-               }
-               debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
-       }
-       return -EINVAL;
-}
-
-int checkboard(void)
-{
-       u32 cpurev = get_cpu_rev();
-       int cpu_variant = (cpurev >> 12) & 0xff;
-       int pmic_id;
-
-       tx6qdl_print_cpuinfo();
-
-       pmic_id = tx6_pmic_probe();
-       if (pmic_id >= 0)
-               pmic_addr = tx6_mod_revs[pmic_id].addr;
-
-       printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
-               tx6_mod_suffix,
-               cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
-               is_lvds(), tx6_get_mod_rev(pmic_id),
-               tx6_mem_suffix());
-
-       get_hab_status();
-
-       return 0;
-}
-
 #ifdef CONFIG_SERIAL_TAG
 void get_board_serial(struct tag_serialnr *serialnr)
 {
index c4e0e21..2f0b886 100644 (file)
@@ -87,7 +87,7 @@ SECTIONS
        }
 
 #ifdef CONFIG_SECURE_BOOT
-       . = CONFIG_SYS_TEXT_BASE + 0x70000;
+       . = CONFIG_SYS_TEXT_BASE + 0x71000;
        .csf_data :
        {
                *(.__csf_data)
index 5daac1f..54a10ee 100644 (file)
@@ -43,7 +43,7 @@ config TXA5_NAND
        select CMD_NAND
        select CMD_NAND_TRIMFFS
        select CMD_ROMUPDATE
-       select ENV_IS_IN_NAND if !TXA5_UBOOT_NOENV
+       select ENV_IS_IN_NAND
        select FDT_FIXUP_PARTITIONS if OF_LIBFDT
        select MTD_PARTITIONS
        select MTD_DEVICE
@@ -55,7 +55,7 @@ config TXA5_EMMC
        bool
        select TXA5
        select SUPPORT_EMMC_BOOT
-       select ENV_IS_IN_MMC if !TXA5_UBOOT_NOENV
+       select ENV_IS_IN_MMC
 
 choice
        prompt "TXA5 module variant"
@@ -86,7 +86,7 @@ config TXA5_UBOOT
 
 config TXA5_UBOOT_NOENV
        bool "U-Boot using only built-in environment"
-       select ENV_IS_NOWHERE
+       select UBOOT_IGNORE_ENV
 
 endchoice
 
index 147fb45..bc6760e 100644 (file)
@@ -236,6 +236,12 @@ config CMD_ENV_EXISTS
          Check if a variable is defined in the environment for use in
          shell scripting.
 
+config UBOOT_IGNORE_ENV
+       bool
+       help
+         Ignore non-volatile environment settings and use default
+         environment only.
+
 endmenu
 
 menu "Memory commands"
index 8e4ad20..9ba4884 100644 (file)
@@ -134,8 +134,8 @@ static void ce_setup_std_drv_globals(ce_std_driver_globals *std_drv_glb)
                "Triton%02X", eth_get_dev()->enetaddr[5]);
 
        net_copy_ip(&std_drv_glb->kitl.ipAddress, &net_ip);
-       std_drv_glb->kitl.ipMask = getenv_ip("netmask");
-       std_drv_glb->kitl.ipRoute = getenv_ip("gatewayip");
+       std_drv_glb->kitl.ipMask = getenv_ip("netmask").s_addr;
+       std_drv_glb->kitl.ipRoute = getenv_ip("gatewayip").s_addr;
 
        if (mtdparts) {
                strncpy(std_drv_glb->mtdparts, mtdparts, max_len);
index 22dcd09..23c5021 100644 (file)
@@ -26,7 +26,7 @@
 #ifdef CONFIG_LCD_LOGO
 #include <bmp_logo.h>
 #include <bmp_logo_data.h>
-#if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP != LCD_COLOR16)
+#if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP < LCD_COLOR16)
 #error Default Color Map overlaps with Logo Color Map
 #endif
 #endif
@@ -706,8 +706,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
                                        *(uint16_t *)fb = val;
                                        bmap++;
                                        fb += sizeof(uint16_t) / sizeof(*fb);
-                               } else {
-                                       FB_PUT_BYTE(fb, bmap);
                                }
                        }
                        if (bpix > 8) {
index 42d302c..6f17c01 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="SOC_SAMA5D4,SYS_USE_MMC"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
index d27f572..7323279 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SOC_SAMA5D4,SYS_USE_NANDFLASH"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
index e5d026a..ed99143 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SOC_SAMA5D4,SYS_USE_SERIALFLASH"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
index 82fa9d4..86b3d7a 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="SOC_SAMA5D4,SYS_USE_MMC"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
index a333e06..d5f5fc6 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SOC_SAMA5D4,SYS_USE_NANDFLASH"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
index fc6dbb0..96899ee 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SOC_SAMA5D4,SYS_USE_SERIALFLASH"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
index 74184a0..cb460e8 100644 (file)
@@ -1,26 +1,18 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_ARRIA5=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_DM_SEQ_ALIAS=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
index 954c936..8a7f8cc 100644 (file)
@@ -1,26 +1,18 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_DM_SEQ_ALIAS=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
index 19eccc3..d767579 100644 (file)
@@ -1,26 +1,18 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_DM_SEQ_ALIAS=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
index 3fe50da..c590354 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
index 74981bb..7de3f99 100644 (file)
@@ -2,5 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6X_SPI_BOOT=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
index 5cc2234..7bf15d1 100644 (file)
@@ -2,5 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
index a97671c..ff38d0b 100644 (file)
@@ -3,5 +3,6 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y
 CONFIG_TQMA6X_SPI_BOOT=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
index c24af64..150b688 100644 (file)
@@ -1,11 +1,12 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_40X1=y
-+S:CONFIG_TX28_UBOOT=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_40X1=y
+CONFIG_TX28_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCE=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_CACHE=y
@@ -18,21 +19,14 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
-S:CONFIG_ENV_IS_NOWHERE=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
 CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index 84b0454..65a421b 100644 (file)
@@ -1,8 +1,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_40X1=y
-+S:CONFIG_TX28_UBOOT_NOENV=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_40X1=y
+CONFIG_TX28_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
@@ -18,19 +18,13 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
-CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index f84c66e..9eeefca 100644 (file)
@@ -1,11 +1,12 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_40X1=y
-+S:CONFIG_TX28_UBOOT=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_40X1=y
+CONFIG_TX28_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCE=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_CACHE=y
@@ -18,21 +19,14 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
-S:CONFIG_ENV_IS_NOWHERE=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
 CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index 942c540..5136c51 100644 (file)
@@ -1,8 +1,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_40X1=y
-+S:CONFIG_TX28_UBOOT_NOENV=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_40X1=y
+CONFIG_TX28_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
@@ -18,19 +18,13 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
-CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index 311022d..d92c8e2 100644 (file)
@@ -1,11 +1,12 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_40X1=y
-+S:CONFIG_TX28_UBOOT=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_40X1=y
+CONFIG_TX28_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCE=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_CACHE=y
@@ -18,21 +19,14 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
-S:CONFIG_ENV_IS_NOWHERE=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
 CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index 28fa3a2..29a4f10 100644 (file)
@@ -1,8 +1,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_40X1=y
-+S:CONFIG_TX28_UBOOT_NOENV=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_40X1=y
+CONFIG_TX28_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
@@ -18,19 +18,13 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
-CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index c5861bc..a4da654 100644 (file)
@@ -1,11 +1,12 @@
 CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_41X0=y
-+S:CONFIG_TX28_UBOOT=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_41X0=y
+CONFIG_TX28_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCE=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_CACHE=y
@@ -18,21 +19,14 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
-S:CONFIG_ENV_IS_NOWHERE=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
 CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index a707d59..79d642d 100644 (file)
@@ -1,8 +1,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX28=y
-+S:CONFIG_TARGET_TX28_41X0=y
-+S:CONFIG_TX28_UBOOT_NOENV=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX28=y
+CONFIG_TARGET_TX28_41X0=y
+CONFIG_TX28_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
@@ -18,19 +18,13 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FEC_MXC=y
-CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y
-CONFIG_LCD=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MXS_MMC=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_MXS=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX28 U-Boot > "
index 9105d2a..bab5178 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MPU_CLK=720,SYS_DDR_CLK=400"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX48=y
-+S:CONFIG_TX48_UBOOT=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX48=y
+CONFIG_TX48_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_SUBNETMASK=y
@@ -17,17 +17,18 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_ROMUPDATE=y
 CONFIG_CMD_TIME=y
-+S:CONFIG_DOS_PARTITION=y
+CONFIG_DOS_PARTITION=y
 CONFIG_DM=y
 CONFIG_ENV_IS_IN_NAND=y
-S:CONFIG_ENV_IS_NOWHERE=y
 CONFIG_LCD=y
 CONFIG_MTD_DEVICE=y
 CONFIG_MTD_PARTITIONS=y
-+S:CONFIG_NAND=y
-+S:CONFIG_NAND_OMAP_GPMC=y
+CONFIG_NAND=y
+CONFIG_NAND_OMAP_GPMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OMAP_HSMMC=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX48 U-Boot > "
index a29602b..10e2091 100644 (file)
@@ -18,3 +18,4 @@ CONFIG_NETDEVICES=y
 CONFIG_FEC_MXC=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX51 U-Boot > "
index 7b6ff0d..efe981f 100644 (file)
@@ -17,4 +17,5 @@ CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_FEC_MXC=y
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX51 U-Boot > "
index 97ba978..9457ea4 100644 (file)
@@ -18,3 +18,4 @@ CONFIG_NETDEVICES=y
 CONFIG_FEC_MXC=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX51 U-Boot > "
index 0af017c..99fb36b 100644 (file)
@@ -17,4 +17,5 @@ CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_FEC_MXC=y
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX51 U-Boot > "
index 0fcb12c..d471f28 100644 (file)
@@ -20,3 +20,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
diff --git a/configs/tx53-1232_noenv_defconfig b/configs/tx53-1232_noenv_defconfig
new file mode 100644 (file)
index 0000000..abbbe8b
--- /dev/null
@@ -0,0 +1,23 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_2G"
+CONFIG_ARM=y
+CONFIG_TARGET_TX53=y
+CONFIG_TARGET_TX53_1232=y
+CONFIG_TX53_UBOOT_NOENV=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_DNS=y
+CONFIG_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_CMD_I2C=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index 6fe8485..1313985 100644 (file)
@@ -20,3 +20,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index 25dcf97..a93032e 100644 (file)
@@ -19,3 +19,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
diff --git a/configs/tx53-x030_noenv_defconfig b/configs/tx53-x030_noenv_defconfig
new file mode 100644 (file)
index 0000000..97b8179
--- /dev/null
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_TARGET_TX53=y
+CONFIG_TARGET_TX53_X030=y
+CONFIG_TX53_UBOOT_NOENV=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_DNS=y
+CONFIG_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_CMD_I2C=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index f39b3e5..b2d7580 100644 (file)
@@ -20,3 +20,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index 9e8eb1a..a9a2768 100644 (file)
@@ -20,3 +20,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
diff --git a/configs/tx53-x130_noenv_defconfig b/configs/tx53-x130_noenv_defconfig
new file mode 100644 (file)
index 0000000..0d44afa
--- /dev/null
@@ -0,0 +1,23 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
+CONFIG_ARM=y
+CONFIG_TARGET_TX53=y
+CONFIG_TARGET_TX53_X130=y
+CONFIG_TX53_UBOOT_NOENV=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_DNS=y
+CONFIG_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_CMD_I2C=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index e7af1aa..f76a01f 100644 (file)
@@ -1,4 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_TARGET_TX53=y
 CONFIG_TARGET_TX53_X130=y
@@ -20,3 +20,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index b74eb35..1b8dfa2 100644 (file)
@@ -20,3 +20,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
diff --git a/configs/tx53-x131_noenv_defconfig b/configs/tx53-x131_noenv_defconfig
new file mode 100644 (file)
index 0000000..22db676
--- /dev/null
@@ -0,0 +1,23 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
+CONFIG_ARM=y
+CONFIG_TARGET_TX53=y
+CONFIG_TARGET_TX53_X131=y
+CONFIG_TX53_UBOOT_NOENV=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_DNS=y
+CONFIG_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_CMD_I2C=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index 41adf69..9c920e2 100644 (file)
@@ -1,4 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_TARGET_TX53=y
 CONFIG_TARGET_TX53_X131=y
@@ -20,3 +20,4 @@ CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TX53 U-Boot > "
index b03729a..6a236ef 100644 (file)
@@ -1,28 +1,31 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index d354c78..5f10b95 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -25,3 +24,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index f8d3f4d..1a3d560 100644 (file)
@@ -1,27 +1,31 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 66dc59b..76b24e6 100644 (file)
@@ -1,28 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index cae5aea..32f1fe5 100644 (file)
@@ -1,28 +1,32 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1033=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index d10572e..1ba92be 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1033=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -25,3 +24,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 3462dfa..f4237ba 100644 (file)
@@ -1,27 +1,32 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1033=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 2a42645..346e4d4 100644 (file)
@@ -1,28 +1,34 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1033=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 91960a8..f0c76b3 100644 (file)
@@ -1,29 +1,34 @@
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 77da179..f0a02af 100644 (file)
@@ -1,28 +1,34 @@
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT_MFG=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index b896343..7995c64 100644 (file)
@@ -1,28 +1,34 @@
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 8afcb7e..b0e5233 100644 (file)
@@ -1,30 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index adb4622..18479c6 100644 (file)
@@ -1,30 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 91e1385..d36f135 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -27,3 +26,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 6068f63..cf3b034 100644 (file)
@@ -1,29 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6Q=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
diff --git a/configs/tx6q-11x0_sec_defconfig b/configs/tx6q-11x0_sec_defconfig
new file mode 100644 (file)
index 0000000..dc1ec3b
--- /dev/null
@@ -0,0 +1,35 @@
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
+CONFIG_ARM=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6Q_11X0=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
index 8e65cbf..a45cd33 100644 (file)
@@ -1,30 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index cca3102..6113b67 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -27,3 +26,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index b9f7735..766b4af 100644 (file)
@@ -1,29 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index 3462556..9515491 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT=y
@@ -28,3 +27,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index 874704a..110062d 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT=y
@@ -26,3 +25,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index 7b65289..9acb708 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -25,3 +24,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index f704e17..74d2e8e 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT_NOENV=y
@@ -21,7 +20,9 @@ CONFIG_FEC_MXC=y
 CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index 0e6beb6..68bfe85 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6S=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT=y
@@ -26,3 +25,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
index c055fb1..a922a7e 100644 (file)
@@ -1,30 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index d682277..8c39e4d 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -27,3 +26,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index c1cc683..5c7779d 100644 (file)
@@ -1,29 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 74799ad..ec04f4e 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT=y
@@ -28,3 +27,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 86e8ce8..1b9322a 100644 (file)
@@ -1,30 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index fba2b06..37946f7 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -27,3 +26,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index e2c4819..7660732 100644 (file)
@@ -1,29 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 2fae611..32cf8c8 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT=y
@@ -28,3 +27,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 6e37e6b..cd98a83 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT=y
@@ -26,3 +25,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 414617e..e5d05b4 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -25,3 +24,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index eeb1615..5cfd39f 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT_NOENV=y
@@ -21,7 +20,9 @@ CONFIG_FEC_MXC=y
 CONFIG_IMX_WATCHDOG=y
 CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 3042b30..6042e13 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT=y
@@ -26,3 +25,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index dd728ac..844d295 100644 (file)
@@ -1,29 +1,34 @@
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index bb825fb..063694f 100644 (file)
@@ -1,5 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -26,3 +25,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 3965471..4a43e3c 100644 (file)
@@ -1,28 +1,34 @@
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 339feae..0f08e22 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT=y
@@ -28,3 +27,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 0c61bc5..61874b3 100644 (file)
@@ -1,30 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_81X0=y
+CONFIG_TARGET_TX6U_8111=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 428ed2a..547da7f 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -27,3 +26,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 9dd4b89..90e8931 100644 (file)
@@ -1,29 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_81X0=y
+CONFIG_TARGET_TX6U_8111=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 8a7a448..3d5c5fb 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT=y
@@ -28,3 +27,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 88b267c..ce30a31 100644 (file)
@@ -1,30 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
-CONFIG_LCD=y
-CONFIG_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
+CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 74e5289..4f72f0f 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_MFG=y
@@ -27,3 +26,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 616429a..fd87053 100644 (file)
@@ -1,29 +1,35 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_NOENV=y
-CONFIG_CMD_MII=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
-CONFIG_BOOTP_SUBNETMASK=y
-CONFIG_BOOTP_GATEWAY=y
-CONFIG_BOOTP_DNS=y
-CONFIG_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_USDHC=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
+CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_FEC_MXC=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_CMD_I2C=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DOS_PARTITION=y
-CONFIG_FEC_MXC_PHYADDR=0
-CONFIG_MXC_OCOTP=y
-CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 0659300..42b9eb8 100644 (file)
@@ -1,6 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SECURE_BOOT"
 CONFIG_ARM=y
-CONFIG_SOC_MX6DL=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT=y
@@ -28,3 +27,4 @@ CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_MXC_OCOTP=y
 CONFIG_CMD_FUSE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6DL U-Boot > "
index 78bec57..289af00 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TXA5=y
 CONFIG_TARGET_TXA5_5010=y
 CONFIG_TXA5_UBOOT=y
@@ -16,3 +17,4 @@ CONFIG_NETDEVICES=y
 #CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_PROMPT="TXA5 U-Boot > "
index a184de8..ec3b8cc 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TXA5=y
 CONFIG_TARGET_TXA5_5011=y
 CONFIG_TXA5_UBOOT=y
@@ -16,3 +17,4 @@ CONFIG_NETDEVICES=y
 #CONFIG_CMD_I2C=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_PROMPT="TXA5 U-Boot > "
index 41f4e69..6ff49b6 100644 (file)
@@ -1,5 +1,8 @@
 menu "Generic Driver Options"
 
+config BOUNCE_BUFFER
+       bool
+
 config DM
        bool "Enable Driver Model"
        help
index c9fb58d..d559e90 100644 (file)
@@ -1,11 +1,10 @@
-menu "MMC Host controller Support"
+menuconfig MMC
+       bool "MMC Host controller Support"
 
-config MMC
-       bool
+if MMC
 
 config GENERIC_MMC
        bool
-       select MMC
 
 config DM_MMC
        bool "Enable MMC controllers using Driver Model"
@@ -29,16 +28,19 @@ config FSL_ESDHC
 
 config FSL_USDHC
        bool "Support USDHC"
-       depends on SOC_MX6
-       depends on FSL_ESDHC
+       depends on FSL_ESDHC && SOC_MX6
 
 config MXS_MMC
        bool "i.MXS MMC/SDHC controller"
        depends on SOC_MXS || SOC_MX6
        select GENERIC_MMC
+       select BOUNCE_BUFFER
+
+config OMAP_HSMMC
+       bool "OMAP HSMMC controller"
+       select GENERIC_MMC
 
 config SUPPORT_EMMC_BOOT
        bool "Support boot from eMMC"
-       depends on MMC
 
-endmenu
+endif
index f8b4985..a02b9c4 100644 (file)
@@ -24,6 +24,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <errno.h>
 #include <malloc.h>
 #include <mmc.h>
 #include <part.h>
@@ -672,11 +673,11 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 
        switch (dev_index) {
        case 0:
-               base_addr = OMAP_HSMMC1_BASE;
+               priv_data->base_addr = (void *)OMAP_HSMMC1_BASE;
                break;
 #ifdef OMAP_HSMMC2_BASE
        case 1:
-               priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
+               priv_data->base_addr = (void *)OMAP_HSMMC2_BASE;
 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
        defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
        defined(CONFIG_AM43XX)) && defined(CONFIG_HSMMC2_8BIT)
@@ -687,7 +688,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 #endif
 #ifdef OMAP_HSMMC3_BASE
        case 2:
-               priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
+               priv_data->base_addr = (void *)OMAP_HSMMC3_BASE;
 #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
                /* Enable 8-bit interface for eMMC on DRA7XX */
                host_caps_val |= MMC_MODE_8BIT;
index 0d4f327..8ce764b 100644 (file)
@@ -1454,9 +1454,6 @@ int board_nand_init(struct nand_chip *nand)
        nand->dev_ready = at91_nand_wait_ready;
 #endif
        nand->chip_delay = 20;
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
-       nand->bbt_options |= NAND_BBT_USE_FLASH;
-#endif
 
 #ifdef CONFIG_ATMEL_NAND_HWECC
 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
@@ -1518,14 +1515,16 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
 #ifdef CONFIG_SYS_NAND_DBW_16
        nand->options = NAND_BUSWIDTH_16;
 #endif
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+       nand->bbt_options |= NAND_BBT_USE_FLASH;
+       nand->bbt_td->options |= NAND_BBT_CREATE;
+       nand->bbt_md->options |= NAND_BBT_CREATE;
+#endif
        nand->cmd_ctrl = at91_nand_hwcontrol;
 #ifdef CONFIG_SYS_NAND_READY_PIN
        nand->dev_ready = at91_nand_ready;
 #endif
        nand->chip_delay = 75;
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
-       nand->bbt_options |= NAND_BBT_USE_FLASH;
-#endif
 
        ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
        if (ret)
index e2bfd3e..8a78dba 100644 (file)
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/errno.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/mem.h>
 #include <linux/mtd/omap_gpmc.h>
 #include <linux/mtd/nand_ecc.h>
@@ -94,147 +95,6 @@ static struct nand_bbt_descr bbt_mirror_descr = {
 
 #define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
 
-#ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
-/**
- * gpmc_prefetch_enable - configures and starts prefetch transfer
- * @cs: cs (chip select) number
- * @fifo_th: fifo threshold to be used for read/ write
- * @count: number of bytes to be transferred
- * @is_write: prefetch read(0) or write post(1) mode
- */
-static inline void gpmc_prefetch_enable(int cs, int fifo_th,
-                                       unsigned int count, int is_write)
-{
-       writel(count, &gpmc_cfg->pref_config2);
-
-       /* Set the prefetch read / post write and enable the engine.
-        * Set which cs is has requested for.
-        */
-       uint32_t val = (cs << CS_NUM_SHIFT) |
-               PREFETCH_ENABLEOPTIMIZEDACCESS |
-               PREFETCH_FIFOTHRESHOLD(fifo_th) |
-               ENABLE_PREFETCH |
-               !!is_write;
-       writel(val, &gpmc_cfg->pref_config1);
-
-       /*  Start the prefetch engine */
-       writel(0x1, &gpmc_cfg->pref_control);
-}
-
-/**
- * gpmc_prefetch_reset - disables and stops the prefetch engine
- */
-static inline void gpmc_prefetch_reset(void)
-{
-       /* Stop the PFPW engine */
-       writel(0x0, &gpmc_cfg->pref_control);
-
-       /* Reset/disable the PFPW engine */
-       writel(0x0, &gpmc_cfg->pref_config1);
-}
-
-//#define FIFO_IOADDR          (nand->IO_ADDR_R)
-#define FIFO_IOADDR            PISMO1_NAND_BASE
-
-/**
- * read_buf_pref - read data from NAND controller into buffer
- * @mtd: MTD device structure
- * @buf: buffer to store date
- * @len: number of bytes to read
- */
-static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
-{
-       gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 0);
-       do {
-               // Get number of bytes waiting in the FIFO
-               uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
-
-               if (read_bytes == 0)
-                       continue;
-               // Alignment of Destination Buffer
-               while (read_bytes && ((unsigned int)buf & 3)) {
-                       *buf++ = readb(FIFO_IOADDR);
-                       read_bytes--;
-                       len--;
-               }
-               // Use maximum word size (32bit) inside this loop, because speed is limited by
-               // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
-               len -= read_bytes & ~3;
-               while (read_bytes >= 4) {
-                       *((uint32_t*)buf) = readl(FIFO_IOADDR);
-                       buf += 4;
-                       read_bytes -= 4;
-               }
-               // Transfer the last (non-aligned) bytes only at the last iteration,
-               // to maintain full speed up to the end of the transfer.
-               if (read_bytes == len) {
-                       while (read_bytes) {
-                               *buf++ = readb(FIFO_IOADDR);
-                               read_bytes--;
-                       }
-                       len = 0;
-               }
-       } while (len > 0);
-       gpmc_prefetch_reset();
-}
-
-/*
- * write_buf_pref - write buffer to NAND controller
- * @mtd: MTD device structure
- * @buf: data buffer
- * @len: number of bytes to write
- */
-static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len)
-{
-       /*  configure and start prefetch transfer */
-       gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 1);
-
-       while (len) {
-               // Get number of free bytes in the FIFO
-               uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
-
-               // don't write more bytes than requested
-               if (write_bytes > len)
-                       write_bytes = len;
-
-               // Alignment of Source Buffer
-               while (write_bytes && ((unsigned int)buf & 3)) {
-                       writeb(*buf++, FIFO_IOADDR);
-                       write_bytes--;
-                       len--;
-               }
-
-               // Use maximum word size (32bit) inside this loop, because speed is limited by
-               // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
-               len -= write_bytes & ~3;
-               while (write_bytes >= 4) {
-                       writel(*((uint32_t*)buf), FIFO_IOADDR);
-                       buf += 4;
-                       write_bytes -= 4;
-               }
-
-               // Transfer the last (non-aligned) bytes only at the last iteration,
-               // to maintain full speed up to the end of the transfer.
-               if (write_bytes == len) {
-                       while (write_bytes) {
-                               writeb(*buf++, FIFO_IOADDR);
-                               write_bytes--;
-                       }
-                       len = 0;
-               }
-       }
-
-       /* wait for data to be flushed out before resetting the prefetch */
-       while ((len = GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status)))) {
-               debug("%u bytes still in FIFO\n", PREFETCH_FIFOTHRESHOLD_MAX - len);
-               ndelay(1);
-       }
-
-       /* disable and stop the PFPW engine */
-       gpmc_prefetch_reset();
-}
-#endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */
-
 /*
  * omap_nand_hwcontrol - Set the address pointers corretly for the
  *                     following address/data/command operation
@@ -269,6 +129,8 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 /* Check wait pin as dev ready indicator */
 static int omap_dev_ready(struct mtd_info *mtd)
 {
+       struct nand_chip *this = mtd->priv;
+       struct omap_nand_info *info = this->priv;
        return !!(readl(&gpmc_cfg->status) & (1 << (8 + info->ws)));
 }
 
index eb8224d..5fd2b08 100644 (file)
@@ -15,6 +15,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <cpsw.h>
 #include <net.h>
 #include <miiphy.h>
 #include <malloc.h>
@@ -227,7 +228,7 @@ struct cpdma_chan {
 #define chan_read_ptr(chan, fld)       ((void *)__raw_readl((chan)->fld))
 
 #define for_active_slave(slave, priv) \
-       slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
+       slave = (priv)->slaves + (priv)->data->active_slave; if (slave)
 #define for_each_slave(slave, priv) \
        for (slave = (priv)->slaves; slave != (priv)->slaves + \
                                (priv)->data->slaves; slave++)
@@ -599,7 +600,7 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 static void cpsw_slave_update_link(struct cpsw_slave *slave,
                                   struct cpsw_priv *priv, int *link)
 {
-       struct phy_device *phy;
+       struct phy_device *phy = priv->phydev;
        u32 mac_control = 0;
        int retries = NUM_TRIES;
 
@@ -1007,7 +1008,7 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
        struct phy_device *phydev;
        u32 supported = PHY_GBIT_FEATURES;
 
-       if (slave->data->phy_id < 0) {
+       if (slave->data->phy_addr < 0) {
                u32 phy_addr;
 
                for (phy_addr = 0; phy_addr < 32; phy_addr++) {
@@ -1020,7 +1021,7 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
                }
        } else {
                phydev = phy_connect(priv->bus,
-                               slave->data->phy_id,
+                               slave->data->phy_addr,
                                dev,
                                slave->data->phy_if);
        }
@@ -1048,7 +1049,6 @@ int cpsw_register(struct cpsw_platform_data *data)
        struct cpsw_slave       *slave;
        void                    *regs = (void *)data->cpsw_base;
        struct eth_device       *dev;
-       int i;
        int idx = 0;
 
        debug("%s@%d\n", __func__, __LINE__);
@@ -1078,7 +1078,6 @@ int cpsw_register(struct cpsw_platform_data *data)
        priv->host_port_regs    = regs + data->host_port_reg_ofs;
        priv->dma_regs          = regs + data->cpdma_reg_ofs;
        priv->ale_regs          = regs + data->ale_reg_ofs;
-       priv->descs             = (void *)regs + data->bd_ram_ofs;
 
        for_each_slave(slave, priv) {
                cpsw_slave_setup(slave, idx, priv);
@@ -1097,10 +1096,8 @@ int cpsw_register(struct cpsw_platform_data *data)
 
        cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
        priv->bus = miiphy_get_dev_by_name(dev->name);
-       for_active_slave(slave, priv) {
+       for_active_slave(slave, priv)
                ret = cpsw_phy_init(dev, slave);
-               if (ret < 0)
-                       break;
-       }
+
        return ret;
 }
index 027c612..1ef3456 100644 (file)
@@ -256,7 +256,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
 
 static inline void fec_rx_task_enable(struct fec_priv *fec)
 {
-       writel(1 << 24, &fec->eth->r_des_active);
+       writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->r_des_active);
 }
 
 static inline void fec_rx_task_disable(struct fec_priv *fec)
@@ -265,7 +265,7 @@ static inline void fec_rx_task_disable(struct fec_priv *fec)
 
 static inline void fec_tx_task_enable(struct fec_priv *fec)
 {
-       writel(1 << 24, &fec->eth->x_des_active);
+       writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
 }
 
 static inline void fec_tx_task_disable(struct fec_priv *fec)
@@ -783,6 +783,7 @@ static int fec_recv(struct eth_device *dev)
        uint16_t bd_status;
        uint32_t addr, size, end;
        int i;
+       ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
 
        /*
         * Check if any critical events have happened
index 39b4753..935f85c 100644 (file)
@@ -1,7 +1,7 @@
-menu "SPI Support"
+menuconfig SPI
+       bool "SPI support"
 
-config SPI
-       bool "Enable SPI support"
+if SPI
 
 config DM_SPI
        bool "Enable Driver Model for SPI drivers"
@@ -141,4 +141,4 @@ config TI_QSPI
          Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
          This driver support spi flash single, quad and memory reads.
 
-endmenu # menu "SPI Support"
+endif
index 2666351..8933a6f 100644 (file)
@@ -56,7 +56,7 @@
 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
 #define UCMD_RESET             (1 << 1) /* controller reset */
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)
 static const unsigned phy_bases[] = {
        USB_PHY0_BASE_ADDR,
        USB_PHY1_BASE_ADDR,
@@ -211,7 +211,7 @@ struct usbnc_regs {
        u32     otg_phy_ctrl_0;
        u32     uh1_phy_ctrl_0;
 };
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_SOC_MX7)
 struct usbnc_regs {
        u32 ctrl1;
        u32 ctrl2;
@@ -253,11 +253,11 @@ int usb_phy_mode(int port)
 
 static void usb_oc_config(int index)
 {
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)
        struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
                        USB_OTHERREGS_OFFSET);
        void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_SOC_MX7)
        struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
                        (0x10000 * index) + USBNC_OFFSET);
        void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
@@ -270,9 +270,9 @@ static void usb_oc_config(int index)
        setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
 #endif
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)
        setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_SOC_MX7)
        setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
 #endif
 }
@@ -327,9 +327,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        enum usb_init_type type;
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)
        u32 controller_spacing = 0x200;
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_SOC_MX7)
        u32 controller_spacing = 0x10000;
 #endif
        struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
@@ -346,7 +346,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
        usb_power_config(index);
        usb_oc_config(index);
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)
        usb_internal_phy_clock_gate(index, 1);
        usb_phy_enable(index, ehci);
 #endif
index d8496f2..30c8ccb 100644 (file)
@@ -50,15 +50,6 @@ ushort *configuration_get_cmap(void)
 #endif
 }
 
-ushort *configuration_get_cmap(void)
-{
-#if defined(CONFIG_LCD_LOGO)
-       return bmp_logo_palette;
-#else
-       return NULL;
-#endif
-}
-
 void lcd_ctrl_init(void *lcdbase)
 {
        unsigned long value;
index e2b2144..7dd1c43 100644 (file)
 #include <video_fb.h>
 #include <linux/list.h>
 #include <linux/fb.h>
+#include <lcd.h>
 
 #include <asm/errno.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/da8xx-fb.h>
 
 #include "videomodes.h"
-#include "da8xx-fb.h"
 
 #if !defined(DA8XX_LCD_CNTL_BASE)
 #define DA8XX_LCD_CNTL_BASE    DAVINCI_LCD_CNTL_BASE
 #define LCD_VERSION_1  1
 #define LCD_VERSION_2  2
 
+#define BIT(x) (1 << (x))
+
 /* LCD Status Register */
-#define LCD_END_OF_FRAME1              (1 << 9)
-#define LCD_END_OF_FRAME0              (1 << 8)
-#define LCD_PL_LOAD_DONE               (1 << 6)
-#define LCD_FIFO_UNDERFLOW             (1 << 5)
-#define LCD_SYNC_LOST                  (1 << 2)
+#define LCD_END_OF_FRAME1              BIT(9)
+#define LCD_END_OF_FRAME0              BIT(8)
+#define LCD_PL_LOAD_DONE               BIT(6)
+#define LCD_FIFO_UNDERFLOW             BIT(5)
+#define LCD_SYNC_LOST                  BIT(2)
 
 /* LCD DMA Control Register */
 #define LCD_DMA_BURST_SIZE(x)          ((x) << 4)
+#define LCD_DMA_BURST_SIZE_MASK                (0x7 << 4)
 #define LCD_DMA_BURST_1                        0x0
 #define LCD_DMA_BURST_2                        0x1
 #define LCD_DMA_BURST_4                        0x2
 #define LCD_DMA_BURST_8                        0x3
 #define LCD_DMA_BURST_16               0x4
-#define LCD_V1_END_OF_FRAME_INT_ENA    (1 << 2)
-#define LCD_V2_END_OF_FRAME0_INT_ENA   (1 << 8)
-#define LCD_V2_END_OF_FRAME1_INT_ENA   (1 << 9)
-#define LCD_DUAL_FRAME_BUFFER_ENABLE   (1 << 0)
-
-#define LCD_V2_TFT_24BPP_MODE          (1 << 25)
-#define LCD_V2_TFT_24BPP_UNPACK                (1 << 26)
+#define LCD_V1_END_OF_FRAME_INT_ENA    BIT(2)
+#define LCD_V2_END_OF_FRAME0_INT_ENA   BIT(8)
+#define LCD_V2_END_OF_FRAME1_INT_ENA   BIT(9)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE   BIT(0)
 
 /* LCD Control Register */
 #define LCD_CLK_DIVISOR(x)             ((x) << 8)
 #define PALETTE_ONLY                   0x01
 #define DATA_ONLY                      0x02
 
-#define LCD_MONO_8BIT_MODE             (1 << 9)
-#define LCD_RASTER_ORDER               (1 << 8)
-#define LCD_TFT_MODE                   (1 << 7)
-#define LCD_V1_UNDERFLOW_INT_ENA       (1 << 6)
-#define LCD_V2_UNDERFLOW_INT_ENA       (1 << 5)
-#define LCD_V1_PL_INT_ENA              (1 << 4)
-#define LCD_V2_PL_INT_ENA              (1 << 6)
-#define LCD_MONOCHROME_MODE            (1 << 1)
-#define LCD_RASTER_ENABLE              (1 << 0)
-#define LCD_TFT_ALT_ENABLE             (1 << 23)
-#define LCD_STN_565_ENABLE             (1 << 24)
-#define LCD_V2_DMA_CLK_EN              (1 << 2)
-#define LCD_V2_LIDD_CLK_EN             (1 << 1)
-#define LCD_V2_CORE_CLK_EN             (1 << 0)
+#define LCD_MONO_8BIT_MODE             BIT(9)
+#define LCD_RASTER_ORDER               BIT(8)
+#define LCD_TFT_MODE                   BIT(7)
+#define LCD_V1_UNDERFLOW_INT_ENA       BIT(6)
+#define LCD_V2_UNDERFLOW_INT_ENA       BIT(5)
+#define LCD_V1_PL_INT_ENA              BIT(4)
+#define LCD_V2_PL_INT_ENA              BIT(6)
+#define LCD_MONOCHROME_MODE            BIT(1)
+#define LCD_RASTER_ENABLE              BIT(0)
+#define LCD_TFT_ALT_ENABLE             BIT(23)
+#define LCD_STN_565_ENABLE             BIT(24)
+#define LCD_TFT24                      BIT(25)
+#define LCD_TFT24_UNPACKED             BIT(26)
+#define LCD_V2_DMA_CLK_EN              BIT(2)
+#define LCD_V2_LIDD_CLK_EN             BIT(1)
+#define LCD_V2_CORE_CLK_EN             BIT(0)
 #define LCD_V2_LPP_B10                 26
 #define LCD_V2_TFT_24BPP_MODE          (1 << 25)
 #define LCD_V2_TFT_24BPP_UNPACK                (1 << 26)
 /* LCD Raster Timing 2 Register */
 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)     ((x) << 16)
 #define LCD_AC_BIAS_FREQUENCY(x)               ((x) << 8)
-#define LCD_SYNC_CTRL                          (1 << 25)
-#define LCD_SYNC_EDGE                          (1 << 24)
-#define LCD_INVERT_PIXEL_CLOCK                 (1 << 22)
-#define LCD_INVERT_LINE_CLOCK                  (1 << 21)
-#define LCD_INVERT_FRAME_CLOCK                 (1 << 20)
+#define LCD_SYNC_CTRL                          BIT(25)
+#define LCD_SYNC_EDGE                          BIT(24)
+#define LCD_INVERT_PIXEL_CLOCK                 BIT(22)
+#define LCD_INVERT_LINE_CLOCK                  BIT(21)
+#define LCD_INVERT_FRAME_CLOCK                 BIT(20)
+
+/* Clock reset register */
+#define  LCD_CLK_MAIN_RESET                    BIT(3)
 
 /* Clock registers available only on Version 2 */
-#define  LCD_CLK_MAIN_RESET                    (1 << 3)
 /* LCD Block */
 struct da8xx_lcd_regs {
-       u32     revid;
-       u32     ctrl;
-       u32     stat;
-       u32     lidd_ctrl;
-       u32     lidd_cs0_conf;
-       u32     lidd_cs0_addr;
-       u32     lidd_cs0_data;
-       u32     lidd_cs1_conf;
-       u32     lidd_cs1_addr;
-       u32     lidd_cs1_data;
-       u32     raster_ctrl;
-       u32     raster_timing_0;
-       u32     raster_timing_1;
-       u32     raster_timing_2;
-       u32     raster_subpanel;
-       u32     reserved;
-       u32     dma_ctrl;
-       u32     dma_frm_buf_base_addr_0;
-       u32     dma_frm_buf_ceiling_addr_0;
-       u32     dma_frm_buf_base_addr_1;
-       u32     dma_frm_buf_ceiling_addr_1;
-       u32     resv1;
-       u32     raw_stat;
-       u32     masked_stat;
-       u32     int_ena_set;
-       u32     int_ena_clr;
-       u32     end_of_int_ind;
+       u32     revid;                          /* 0x00 */
+       u32     ctrl;                           /* 0x04 */
+       u32     stat;                           /* 0x08 */
+       u32     lidd_ctrl;                      /* 0x0c */
+       u32     lidd_cs0_conf;                  /* 0x10 */
+       u32     lidd_cs0_addr;                  /* 0x14 */
+       u32     lidd_cs0_data;                  /* 0x18 */
+       u32     lidd_cs1_conf;                  /* 0x1c */
+       u32     lidd_cs1_addr;                  /* 0x20 */
+       u32     lidd_cs1_data;                  /* 0x24 */
+       u32     raster_ctrl;                    /* 0x28 */
+       u32     raster_timing_0;                /* 0x2c */
+       u32     raster_timing_1;                /* 0x30 */
+       u32     raster_timing_2;                /* 0x34 */
+       u32     raster_subpanel;                /* 0x38 */
+       u32     reserved;                       /* 0x3c */
+       u32     dma_ctrl;                       /* 0x40 */
+       u32     dma_frm_buf_base_addr_0;        /* 0x44 */
+       u32     dma_frm_buf_ceiling_addr_0;     /* 0x48 */
+       u32     dma_frm_buf_base_addr_1;        /* 0x4c */
+       u32     dma_frm_buf_ceiling_addr_1;     /* 0x50 */
+       u32     rsrvd1;                         /* 0x54 */
+       u32     raw_stat;                       /* 0x58 */
+       u32     masked_stat;                    /* 0x5c */
+       u32     int_ena_set;                    /* 0x60 */
+       u32     int_ena_clr;                    /* 0x64 */
+       u32     end_of_int_ind;                 /* 0x68 */
+       u32     clk_ena;                        /* 0x6c */
+       u32     clk_reset;                      /* 0x70 */
        /* Clock registers available only on Version 2 */
-       u32     clk_ena;
-       u32     clk_reset;
 };
 
 #define LCD_NUM_BUFFERS        1
@@ -141,7 +147,6 @@ struct da8xx_lcd_regs {
 #define WAIT_FOR_FRAME_DONE    true
 #define NO_WAIT_FOR_FRAME_DONE false
 
-#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
 
 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
 
@@ -153,11 +158,12 @@ static const struct da8xx_panel *lcd_panel;
 static struct fb_info *da8xx_fb_info;
 static int bits_x_pixel;
 static unsigned int lcd_revision;
+static u32 (*lcdc_irq_handler)(void);
 const struct lcd_ctrl_config *da8xx_lcd_cfg;
 
 static inline unsigned int lcdc_read(u32 *addr)
 {
-       return (unsigned int)readl(addr);
+       return readl(addr);
 }
 
 static inline void lcdc_write(unsigned int val, u32 *addr)
@@ -166,14 +172,14 @@ static inline void lcdc_write(unsigned int val, u32 *addr)
 }
 
 struct da8xx_fb_par {
-       u32                      p_palette_base;
-       unsigned char *v_palette_base;
+       unsigned long           p_palette_base;
+       void                    *v_palette_base;
        dma_addr_t              vram_phys;
        unsigned long           vram_size;
        void                    *vram_virt;
        unsigned int            dma_start;
        unsigned int            dma_end;
-       struct clk *lcdc_clk;
+       struct clk              *lcdc_clk;
        int irq;
        unsigned short pseudo_palette[16];
        unsigned int palette_sz;
@@ -183,7 +189,6 @@ struct da8xx_fb_par {
        int                     vsync_timeout;
 };
 
-
 /* Variable Screen Information */
 static struct fb_var_screeninfo da8xx_fb_var = {
        .xoffset = 0,
@@ -227,9 +232,7 @@ static inline void lcd_enable_raster(void)
        udelay(1000);
        /* Bring LCDC out of reset */
        if (lcd_revision == LCD_VERSION_2)
-               lcdc_write(0,
-                          &da8xx_fb_reg_base->clk_reset);
-
+               lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
        udelay(1000);
 
        reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
@@ -281,7 +284,6 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
        u32 end;
        u32 reg_ras;
        u32 reg_dma;
-       u32 reg_int;
 
        /* init reg to clear PLM (loading mode) fields */
        reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
@@ -297,11 +299,10 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
                if (lcd_revision == LCD_VERSION_1) {
                        reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
                } else {
-                       reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
-                               LCD_V2_END_OF_FRAME0_INT_ENA |
+                       lcdc_write(LCD_V2_END_OF_FRAME0_INT_ENA |
                                LCD_V2_END_OF_FRAME1_INT_ENA |
-                               LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
-                       lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
+                               LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST,
+                               &da8xx_fb_reg_base->int_ena_set);
                }
 
 #if (LCD_NUM_BUFFERS == 2)
@@ -317,18 +318,17 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
                lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
                lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 #endif
-
        } else if (load_mode == LOAD_PALETTE) {
                start    = par->p_palette_base;
                end      = start + par->palette_sz - 1;
 
                reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+
                if (lcd_revision == LCD_VERSION_1) {
                        reg_ras |= LCD_V1_PL_INT_ENA;
                } else {
-                       reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
-                               LCD_V2_PL_INT_ENA;
-                       lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
+                       lcdc_write(LCD_V2_PL_INT_ENA,
+                               &da8xx_fb_reg_base->int_ena_set);
                }
 
                lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
@@ -350,7 +350,8 @@ static int lcd_cfg_dma(int burst_size)
 {
        u32 reg;
 
-       reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
+       reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
+       reg &= ~LCD_DMA_BURST_SIZE_MASK;
        switch (burst_size) {
        case 1:
                reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
@@ -413,11 +414,12 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
 {
        u32 reg;
-       u32 reg_int;
 
        reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
                                                LCD_MONO_8BIT_MODE |
-                                               LCD_MONOCHROME_MODE);
+                                               LCD_MONOCHROME_MODE |
+                                               LCD_TFT24 |
+                                               LCD_TFT24_UNPACKED);
 
        switch (cfg->p_disp_panel->panel_shade) {
        case MONOCHROME:
@@ -444,9 +446,13 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
        if (lcd_revision == LCD_VERSION_1) {
                reg |= LCD_V1_UNDERFLOW_INT_ENA;
        } else {
-               reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
-                       LCD_V2_UNDERFLOW_INT_ENA;
-               lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
+               if (bits_x_pixel >= 24)
+                       reg |= LCD_TFT24;
+               if (cfg->bpp == 32)
+                       reg |= LCD_TFT24_UNPACKED;
+
+               lcdc_write(LCD_V2_UNDERFLOW_INT_ENA,
+                       &da8xx_fb_reg_base->int_ena_set);
        }
 
        lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
@@ -487,8 +493,8 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
        /* Pixels per line = (PPL + 1)*16 */
        if (lcd_revision == LCD_VERSION_1) {
                /*
-                * 0x3F in bits 4..9 gives max horisontal resolution = 1024
-                * pixels
+                * 0x3F in bits 4..9 gives max horizontal resolution = 1024
+                * pixels.
                 */
                width &= 0x3f0;
        } else {
@@ -498,6 +504,7 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
                 */
                width &= 0x7f0;
        }
+
        reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
        reg &= 0xfffffc00;
        if (lcd_revision == LCD_VERSION_1) {
@@ -560,7 +567,7 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
                              struct fb_info *info)
 {
        struct da8xx_fb_par *par = info->par;
-       unsigned short *palette = (unsigned short *) par->v_palette_base;
+       unsigned short *palette = par->v_palette_base;
        u_short pal;
        int update_hw = 0;
 
@@ -635,7 +642,6 @@ static void lcd_reset(struct da8xx_fb_par *par)
        lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
 
        if (lcd_revision == LCD_VERSION_2) {
-               lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
                /* Write 1 to reset */
                lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
                lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
@@ -646,16 +652,27 @@ static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
 {
        unsigned int lcd_clk, div;
 
+#ifndef CONFIG_AM33XX
        /* Get clock from sysclk2 */
        lcd_clk = clk_get(2);
-
-       div = lcd_clk / par->pxl_clk;
-       debug("LCD Clock: %d Divider: %d PixClk: %d\n",
-             lcd_clk, div, par->pxl_clk);
+#else
+       lcd_clk = lcdc_clk_rate();
+#endif
+       /* calculate divisor so that the resulting clock is rounded down */
+       div = (lcd_clk + par->pxl_clk - 1)/ par->pxl_clk;
+       if (div > 255)
+               div = 255;
+       if (div < 2)
+               div = 2;
+
+       debug("LCD Clock: %u.%03uMHz Divider: 0x%08x PixClk requested: %u.%03uMHz actual: %u.%03uMHz\n",
+               lcd_clk / 1000000, lcd_clk / 1000 % 1000, div,
+               par->pxl_clk / 1000000, par->pxl_clk / 1000 % 1000,
+               lcd_clk / div / 1000000, lcd_clk / div / 1000 % 1000);
 
        /* Configure the LCD clock divisor. */
-       lcdc_write(LCD_CLK_DIVISOR(div) |
-                       (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+       lcdc_write(LCD_CLK_DIVISOR(div) | LCD_RASTER_MODE,
+               &da8xx_fb_reg_base->ctrl);
 
        if (lcd_revision == LCD_VERSION_2)
                lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
@@ -695,7 +712,7 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
        lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
        lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
 
-       /* Configure for disply */
+       /* Configure for display */
        ret = lcd_cfg_display(cfg);
        if (ret < 0)
                return ret;
@@ -737,18 +754,21 @@ static void lcdc_dma_start(void)
                &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 }
 
-static u32 lcdc_irq_handler_rev01(void)
+/* IRQ handler for version 2 of LCDC */
+static u32 lcdc_irq_handler_rev02(void)
 {
+       u32 ret = 0;
        struct da8xx_fb_par *par = da8xx_fb_info->par;
-       u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
-       u32 reg_ras;
+       u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
+
+       debug("%s: stat=%08x\n", __func__, stat);
 
        if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
                debug("LCD_SYNC_LOST\n");
                lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
                lcdc_write(stat, &da8xx_fb_reg_base->stat);
                lcd_enable_raster();
-               return LCD_SYNC_LOST;
+               ret = LCD_SYNC_LOST;
        } else if (stat & LCD_PL_LOAD_DONE) {
                debug("LCD_PL_LOAD_DONE\n");
                /*
@@ -762,34 +782,44 @@ static u32 lcdc_irq_handler_rev01(void)
                lcdc_write(stat, &da8xx_fb_reg_base->stat);
 
                /* Disable PL completion inerrupt */
-               reg_ras  = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
-               reg_ras &= ~LCD_V1_PL_INT_ENA;
-               lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+               lcdc_write(LCD_V2_PL_INT_ENA,
+                       &da8xx_fb_reg_base->int_ena_clr);
 
                /* Setup and start data loading mode */
                lcd_blit(LOAD_DATA, par);
-               return LCD_PL_LOAD_DONE;
-       } else {
-               lcdc_write(stat, &da8xx_fb_reg_base->stat);
+               ret = LCD_PL_LOAD_DONE;
+       } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
+               par->vsync_flag = 1;
+               lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 
-               if (stat & LCD_END_OF_FRAME0)
+               if (stat & LCD_END_OF_FRAME0) {
                        debug("LCD_END_OF_FRAME0\n");
 
-               lcdc_write(par->dma_start,
-                       &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
-               lcdc_write(par->dma_end,
-                       &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
-               par->vsync_flag = 1;
-               return LCD_END_OF_FRAME0;
+                       lcdc_write(par->dma_start,
+                               &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+                       lcdc_write(par->dma_end,
+                               &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+               }
+               if (stat & LCD_END_OF_FRAME1) {
+                       debug("LCD_END_OF_FRAME1\n");
+                       lcdc_write(par->dma_start,
+                               &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+                       lcdc_write(par->dma_end,
+                               &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+                       par->vsync_flag = 1;
+               }
+               ret = (stat & LCD_END_OF_FRAME0) ?
+                       LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
        }
-       return stat;
+       lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
+       return ret;
 }
 
-static u32 lcdc_irq_handler_rev02(void)
+static u32 lcdc_irq_handler_rev01(void)
 {
        struct da8xx_fb_par *par = da8xx_fb_info->par;
-       u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
-       u32 reg_int;
+       u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
+       u32 reg_ras;
 
        if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
                debug("LCD_SYNC_LOST\n");
@@ -811,49 +841,53 @@ static u32 lcdc_irq_handler_rev02(void)
                lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 
                /* Disable PL completion inerrupt */
-               reg_int  = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
-                       (LCD_V2_PL_INT_ENA);
-               lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
+               reg_ras  = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+               reg_ras &= ~LCD_V1_PL_INT_ENA;
+               lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
 
                /* Setup and start data loading mode */
                lcd_blit(LOAD_DATA, par);
                lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
                return LCD_PL_LOAD_DONE;
-       } else {
-               lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+       } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
+               par->vsync_flag = 1;
+               lcdc_write(stat, &da8xx_fb_reg_base->stat);
 
-               if (stat & LCD_END_OF_FRAME0)
+               if (stat & LCD_END_OF_FRAME0) {
                        debug("LCD_END_OF_FRAME0\n");
 
-               lcdc_write(par->dma_start,
-                          &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
-               lcdc_write(par->dma_end,
-                          &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
-               par->vsync_flag = 1;
-               lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
-               return LCD_END_OF_FRAME0;
+                       lcdc_write(par->dma_start,
+                               &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+                       lcdc_write(par->dma_end,
+                               &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+               }
+
+               if (stat & LCD_END_OF_FRAME1) {
+                       debug("LCD_END_OF_FRAME1\n");
+                       lcdc_write(par->dma_start,
+                               &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+                       lcdc_write(par->dma_end,
+                               &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+               }
+
+               return (stat & LCD_END_OF_FRAME0) ?
+                       LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
        }
        lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
        return stat;
 }
 
-static u32 lcdc_irq_handler(void)
-{
-       if (lcd_revision == LCD_VERSION_1)
-               return lcdc_irq_handler_rev01();
-       else
-               return lcdc_irq_handler_rev02();
-}
-
 static u32 wait_for_event(u32 event)
 {
-       u32 timeout = 50000;
+       int timeout = 100;
        u32 ret;
 
        do {
                ret = lcdc_irq_handler();
+               if (ret & event)
+                       break;
                udelay(1000);
-       } while (!(ret & event));
+       } while (--timeout > 0);
 
        if (timeout <= 0) {
                printf("%s: event %d not hit\n", __func__, event);
@@ -868,13 +902,13 @@ void *video_hw_init(void)
 {
        struct da8xx_fb_par *par;
        u32 size;
-       u32 rev;
        char *p;
 
        if (!lcd_panel) {
                printf("Display not initialized\n");
                return NULL;
        }
+
        gpanel.winSizeX = lcd_panel->width;
        gpanel.winSizeY = lcd_panel->height;
        gpanel.plnSizeX = lcd_panel->width;
@@ -896,36 +930,36 @@ void *video_hw_init(void)
        default:
                gpanel.gdfBytesPP = 1;
                gpanel.gdfIndex = GDF__8BIT_INDEX;
-               break;
        }
 
        da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
 
        /* Determine LCD IP Version */
-       rev = lcdc_read(&da8xx_fb_reg_base->revid);
-       switch (rev) {
-       case 0x4C100102:
+
+       lcd_revision = lcdc_read(&da8xx_fb_reg_base->revid);
+       switch (lcd_revision & 0xfff00000) {
+       case 0x4C100000:
                lcd_revision = LCD_VERSION_1;
                break;
-       case 0x4F200800:
-       case 0x4F201000:
+
+       case 0x4F200000:
                lcd_revision = LCD_VERSION_2;
                break;
+
        default:
-               printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
-                      rev);
+               printf("Unknown PID Reg value 0x%08x, defaulting to LCD revision 1\n",
+                               lcd_revision);
                lcd_revision = LCD_VERSION_1;
-               break;
        }
 
-       debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
-             gpanel.winSizeX,
-             gpanel.winSizeY,
+       debug("Resolution: %dx%d %d\n",
+               gpanel.winSizeX,
+               gpanel.winSizeY,
              da8xx_lcd_cfg->bpp);
 
        size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
        da8xx_fb_info = malloc(size);
-       debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
+       debug("da8xx_fb_info at %p\n", da8xx_fb_info);
 
        if (!da8xx_fb_info) {
                printf("Memory allocation failed for fb_info\n");
@@ -934,7 +968,7 @@ void *video_hw_init(void)
        memset(da8xx_fb_info, 0, size);
        p = (char *)da8xx_fb_info;
        da8xx_fb_info->par = p +  sizeof(struct fb_info);
-       debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
+       debug("da8xx_par at %p\n", da8xx_fb_info->par);
 
        par = da8xx_fb_info->par;
        par->pxl_clk = lcd_panel->pxl_clk;
@@ -949,24 +983,27 @@ void *video_hw_init(void)
                        da8xx_lcd_cfg->bpp;
        par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
 
+#ifdef CONFIG_LCD
+       par->vram_virt = (void *)gd->fb_base;
+#else
        par->vram_virt = malloc(par->vram_size);
-
+#endif
        par->vram_phys = (dma_addr_t) par->vram_virt;
-       debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
-               (unsigned int)par->vram_size,
-               (unsigned int)par->vram_virt);
+       debug("Requesting 0x%lx bytes for framebuffer at 0x%p\n",
+               par->vram_size, par->vram_virt);
        if (!par->vram_virt) {
                printf("GLCD: malloc for frame buffer failed\n");
                goto err_release_fb;
        }
-       gd->fb_base = (int)par->vram_virt;
 
        gpanel.frameAdrs = (unsigned int)par->vram_virt;
-       da8xx_fb_info->screen_base = (char *) par->vram_virt;
+       da8xx_fb_info->screen_base = par->vram_virt;
        da8xx_fb_fix.smem_start = gpanel.frameAdrs;
        da8xx_fb_fix.smem_len = par->vram_size;
        da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
-
+       debug("%s: vram_virt: %p size %ux%u=%lu bpp %u\n", __func__,
+               par->vram_virt, lcd_panel->width, lcd_panel->height,
+               par->vram_size, da8xx_lcd_cfg->bpp);
        par->dma_start = par->vram_phys;
        par->dma_end   = par->dma_start + lcd_panel->height *
                da8xx_fb_fix.line_length - 1;
@@ -978,11 +1015,11 @@ void *video_hw_init(void)
                goto err_release_fb_mem;
        }
        memset(par->v_palette_base, 0, PALETTE_SIZE);
-       par->p_palette_base = (unsigned int)par->v_palette_base;
-
+       par->p_palette_base = (unsigned long)par->v_palette_base;
        /* Initialize par */
        da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
 
+       /* Initialize var */
        da8xx_fb_var.xres = lcd_panel->width;
        da8xx_fb_var.xres_virtual = lcd_panel->width;
 
@@ -1005,13 +1042,18 @@ void *video_hw_init(void)
                                FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
 
        /* Clear interrupt */
-       memset((void *)par->vram_virt, 0, par->vram_size);
+       memset(par->vram_virt, 0, par->vram_size);
        lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
        if (lcd_revision == LCD_VERSION_1)
-               lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+               lcdc_irq_handler = lcdc_irq_handler_rev01;
        else
-               lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
-       debug("Palette at 0x%x size %d\n", par->p_palette_base,
+               lcdc_irq_handler = lcdc_irq_handler_rev02;
+
+       /* Clear interrupt */
+       memset(par->vram_virt, 0, par->vram_size);
+       lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+       lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+       debug("Palette at 0x%08lx size %u\n", par->p_palette_base,
                par->palette_sz);
        lcdc_dma_start();
 
@@ -1024,10 +1066,12 @@ void *video_hw_init(void)
        /* Wait until DMA is working */
        wait_for_event(LCD_END_OF_FRAME0);
 
-       return (void *)&gpanel;
+       return &gpanel;
 
 err_release_fb_mem:
+#ifndef CONFIG_LCD
        free(par->vram_virt);
+#endif
 
 err_release_fb:
        free(da8xx_fb_info);
@@ -1035,6 +1079,19 @@ err_release_fb:
        return NULL;
 }
 
+void da8xx_fb_disable(void)
+{
+       lcd_reset(da8xx_fb_info->par);
+}
+
+void video_set_lut(unsigned int index, /* color number */
+                   unsigned char r,    /* red */
+                   unsigned char g,    /* green */
+                   unsigned char b     /* blue */
+                   )
+{
+}
+
 void da8xx_video_init(const struct da8xx_panel *panel,
                      const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
 {
diff --git a/drivers/video/da8xx-fb.h b/drivers/video/da8xx-fb.h
deleted file mode 100644 (file)
index 6447a40..0000000
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Porting to u-boot:
- *
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2008-2009 MontaVista Software Inc.
- * Copyright (C) 2008-2009 Texas Instruments Inc
- *
- * Based on the LCD driver for TI Avalanche processors written by
- * Ajay Singh and Shalom Hai.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef DA8XX_FB_H
-#define DA8XX_FB_H
-
-enum panel_type {
-       QVGA = 0,
-       WVGA
-};
-
-enum panel_shade {
-       MONOCHROME = 0,
-       COLOR_ACTIVE,
-       COLOR_PASSIVE,
-};
-
-enum raster_load_mode {
-       LOAD_DATA = 1,
-       LOAD_PALETTE,
-};
-
-struct display_panel {
-       enum panel_type panel_type; /* QVGA */
-       int max_bpp;
-       int min_bpp;
-       enum panel_shade panel_shade;
-};
-
-struct da8xx_panel {
-       const char      name[25];       /* Full name <vendor>_<model> */
-       unsigned short  width;
-       unsigned short  height;
-       int             hfp;            /* Horizontal front porch */
-       int             hbp;            /* Horizontal back porch */
-       int             hsw;            /* Horizontal Sync Pulse Width */
-       int             vfp;            /* Vertical front porch */
-       int             vbp;            /* Vertical back porch */
-       int             vsw;            /* Vertical Sync Pulse Width */
-       unsigned int    pxl_clk;        /* Pixel clock */
-       unsigned char   invert_pxl_clk; /* Invert Pixel clock */
-};
-
-struct da8xx_lcdc_platform_data {
-       const char manu_name[10];
-       void *controller_data;
-       const char type[25];
-       void (*panel_power_ctrl)(int);
-};
-
-struct lcd_ctrl_config {
-       const struct display_panel *p_disp_panel;
-
-       /* AC Bias Pin Frequency */
-       int ac_bias;
-
-       /* AC Bias Pin Transitions per Interrupt */
-       int ac_bias_intrpt;
-
-       /* DMA burst size */
-       int dma_burst_sz;
-
-       /* Bits per pixel */
-       int bpp;
-
-       /* FIFO DMA Request Delay */
-       int fdd;
-
-       /* TFT Alternative Signal Mapping (Only for active) */
-       unsigned char tft_alt_mode;
-
-       /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
-       unsigned char stn_565_mode;
-
-       /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
-       unsigned char mono_8bit_mode;
-
-       /* Invert line clock */
-       unsigned char invert_line_clock;
-
-       /* Invert frame clock  */
-       unsigned char invert_frm_clock;
-
-       /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
-       unsigned char sync_edge;
-
-       /* Horizontal and Vertical Sync: Control: 0=ignore */
-       unsigned char sync_ctrl;
-
-       /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
-       unsigned char raster_order;
-};
-
-struct lcd_sync_arg {
-       int back_porch;
-       int front_porch;
-       int pulse_width;
-};
-
-void da8xx_video_init(const struct da8xx_panel *panel,
-                     const struct lcd_ctrl_config *lcd_cfg,
-                     int bits_pixel);
-
-#endif  /* ifndef DA8XX_FB_H */
index 6993128..782e886 100644 (file)
@@ -33,7 +33,7 @@ typedef struct vidinfo {
        u_long vl_upper_margin; /* Time from sync to picture */
        u_long vl_lower_margin; /* Time from picture to sync */
 
-       u_long  mmio;           /* Memory mapped registers */
+       void __iomem *mmio;     /* Memory mapped registers */
 } vidinfo_t;
 
 #endif
index 4e3bab2..bbab8b2 100644 (file)
@@ -12,9 +12,6 @@
 #define CONFIG_AMCORE
 #define CONFIG_HOSTNAME                        AMCORE
 
-#define CONFIG_MCF530x
-#define CONFIG_M5307
-
 #define CONFIG_MCFTMR
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           0
index 2de5aeb..c8b15fb 100644 (file)
@@ -24,6 +24,8 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_CALIMAIN
+#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
+#define CONFIG_SOC_DA850               /* TI DA850 SoC */
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          calimain_get_osc_freq()
index 2df5987..7ac3224 100644 (file)
@@ -21,6 +21,8 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA830_EVM
+#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
+#define CONFIG_SOC_DA830               /* TI DA830 SoC */
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
index 4a5b33a..1cd11c0 100644 (file)
@@ -25,6 +25,8 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
+#define CONFIG_SOC_DA850               /* TI DA850 SoC */
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
index 0ac66fc..72296a0 100644 (file)
@@ -17,6 +17,7 @@
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */
+#define CONFIG_SOC_DM355</