imx: mx6 add i2c4 clock support for i.MX6SX
authorPeng Fan <Peng.Fan@freescale.com>
Wed, 1 Jul 2015 09:01:50 +0000 (17:01 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 8 Sep 2015 22:47:43 +0000 (00:47 +0200)
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.

Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/crm_regs.h

index 4de908f..980a6eb 100644 (file)
@@ -220,6 +220,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 reg;
        u32 mask;
+       u32 *addr;
 
        if (i2c_num > 3)
                return -EINVAL;
@@ -234,14 +235,19 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
-               mask = MXC_CCM_CCGR_CG_MASK
-                       << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
-               reg = __raw_readl(&imx_ccm->CCGR1);
+               if (is_cpu_type(MXC_CPU_MX6SX)) {
+                       mask = MXC_CCM_CCGR6_I2C4_MASK;
+                       addr = &imx_ccm->CCGR6;
+               } else {
+                       mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
+                       addr = &imx_ccm->CCGR1;
+               }
+               reg = __raw_readl(addr);
                if (enable)
                        reg |= mask;
                else
                        reg &= ~mask;
-               __raw_writel(reg, &imx_ccm->CCGR1);
+               __raw_writel(reg, addr);
        }
        return 0;
 }
index f4a42c4..08f5464 100644 (file)
@@ -654,706 +654,322 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET          30
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK            (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
 
-#define MXC_CCM_CCGR5_ROM_OFFSET                       0
-#define MXC_CCM_CCGR5_ROM_MASK                         (3 << MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_ROM_OFFSET                               0
+#define MXC_CCM_CCGR5_ROM_MASK                                 (3 << MXC_CCM_CCGR5_ROM_OFFSET)
 #ifndef CONFIG_SOC_MX6SX
-#define MXC_CCM_CCGR5_SATA_OFFSET                      4
-#define MXC_CCM_CCGR5_SATA_MASK                                (3 << MXC_CCM_CCGR5_SATA_OFFSET)
-#endif
-#define MXC_CCM_CCGR5_SDMA_OFFSET                      6
-#define MXC_CCM_CCGR5_SDMA_MASK                                (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
-#define MXC_CCM_CCGR5_SPBA_OFFSET                      12
-#define MXC_CCM_CCGR5_SPBA_MASK                                (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
-#define MXC_CCM_CCGR5_SPDIF_OFFSET                     14
-#define MXC_CCM_CCGR5_SPDIF_MASK                       (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
-#define MXC_CCM_CCGR5_SSI1_OFFSET                      18
-#define MXC_CCM_CCGR5_SSI1_MASK                                (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
-#define MXC_CCM_CCGR5_SSI2_OFFSET                      20
-#define MXC_CCM_CCGR5_SSI2_MASK                                (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
-#define MXC_CCM_CCGR5_SSI3_OFFSET                      22
-#define MXC_CCM_CCGR5_SSI3_MASK                                (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
-#define MXC_CCM_CCGR5_UART_OFFSET                      24
-#define MXC_CCM_CCGR5_UART_MASK                                (3 << MXC_CCM_CCGR5_UART_OFFSET)
-#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET               26
-#define MXC_CCM_CCGR5_UART_SERIAL_MASK                 (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#define MXC_CCM_CCGR5_SATA_OFFSET                              4
+#define MXC_CCM_CCGR5_SATA_MASK                                        (3 << MXC_CCM_CCGR5_SATA_OFFSET)
+#endif
+#define MXC_CCM_CCGR5_SDMA_OFFSET                              6
+#define MXC_CCM_CCGR5_SDMA_MASK                                        (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET                              12
+#define MXC_CCM_CCGR5_SPBA_MASK                                        (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET                             14
+#define MXC_CCM_CCGR5_SPDIF_MASK                               (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET                              18
+#define MXC_CCM_CCGR5_SSI1_MASK                                        (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET                              20
+#define MXC_CCM_CCGR5_SSI2_MASK                                        (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET                              22
+#define MXC_CCM_CCGR5_SSI3_MASK                                        (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET                              24
+#define MXC_CCM_CCGR5_UART_MASK                                        (3 << MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET                       26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK                         (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
 #ifdef CONFIG_SOC_MX6SX
-#define MXC_CCM_CCGR5_SAI1_OFFSET                      20
-#define MXC_CCM_CCGR5_SAI1_MASK                                (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
-#define MXC_CCM_CCGR5_SAI2_OFFSET                      30
-#define MXC_CCM_CCGR5_SAI2_MASK                                (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
-#endif
-
-#define MXC_CCM_CCGR6_USBOH3_OFFSET                    0
-#define MXC_CCM_CCGR6_USBOH3_MASK                      (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC1_OFFSET                    2
-#define MXC_CCM_CCGR6_USDHC1_MASK                      (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
-#define MXC_CCM_CCGR6_USDHC2_OFFSET                    4
-#define MXC_CCM_CCGR6_USDHC2_MASK                      (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
-#define MXC_CCM_CCGR6_USDHC3_OFFSET                    6
-#define MXC_CCM_CCGR6_USDHC3_MASK                      (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC4_OFFSET                    8
-#define MXC_CCM_CCGR6_USDHC4_MASK                      (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
-#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                  10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK                    (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
-#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET                 12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK                   (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
-
-#define ANATOP_PFD_480_PFD0_FRAC_SHIFT                 0
-#define ANATOP_PFD_480_PFD0_FRAC_MASK                  (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD0_STABLE_SHIFT               6
-#define ANATOP_PFD_480_PFD0_STABLE_MASK                        (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT              7
-#define ANATOP_PFD_480_PFD0_CLKGATE_MASK               (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD1_FRAC_SHIFT                 8
-#define ANATOP_PFD_480_PFD1_FRAC_MASK                  (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD1_STABLE_SHIFT               14
-#define ANATOP_PFD_480_PFD1_STABLE_MASK                        (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT              15
-#define ANATOP_PFD_480_PFD1_CLKGATE_MASK               (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD2_FRAC_SHIFT                 16
-#define ANATOP_PFD_480_PFD2_FRAC_MASK                  (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD2_STABLE_SHIFT               22
-#define ANATOP_PFD_480_PFD2_STABLE_MASK                        (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT              23
-#define ANATOP_PFD_480_PFD2_CLKGATE_MASK               (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD3_FRAC_SHIFT                 24
-#define ANATOP_PFD_480_PFD3_FRAC_MASK                  (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD3_STABLE_SHIFT               30
-#define ANATOP_PFD_480_PFD3_STABLE_MASK                        (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT              31
-
-#define BM_ANADIG_PLL_ARM_LOCK                         (1 << 31)
-#define BM_ANADIG_PLL_ARM_PLL_SEL                      (1 << 19)
-#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL               (1 << 18)
-#define BM_ANADIG_PLL_ARM_LVDS_SEL                     (1 << 17)
-#define BM_ANADIG_PLL_ARM_BYPASS                       (1 << 16)
-#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC               14
-#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC               (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v)         \
-       (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
-               BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M      0x0
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1     0x1
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2     0x2
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR          0x3
-#define BM_ANADIG_PLL_ARM_ENABLE                       (1 << 13)
-#define BM_ANADIG_PLL_ARM_POWERDOWN                    (1 << 12)
-#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF                        (1 << 11)
-#define BM_ANADIG_PLL_ARM_DOUBLE_CP                    (1 << 10)
-#define BM_ANADIG_PLL_ARM_HALF_CP                      (1 << 9)
-#define BM_ANADIG_PLL_ARM_DOUBLE_LF                    (1 << 8)
-#define BM_ANADIG_PLL_ARM_HALF_LF                      (1 << 7)
-#define BP_ANADIG_PLL_ARM_DIV_SELECT                   0
-#define BM_ANADIG_PLL_ARM_DIV_SELECT                   (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
-#define BF_ANADIG_PLL_ARM_DIV_SELECT(v)                 \
-       (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
-               BM_ANADIG_PLL_ARM_DIV_SELECT)
-
-#define BM_ANADIG_PLL_528_CTRL_LOCK                    (1 << 31)
-#define BM_ANADIG_PLL_528_PFD_OFFSET_EN                        (1 << 18)
-#define BM_ANADIG_PLL_528_DITHER_ENABLE                        (1 << 17)
-#define BM_ANADIG_PLL_528_CTRL_BYPASS                  (1 << 16)
-#define BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC          14
-#define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC          (0x3 << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC(v)         \
-       (((v) << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) & \
-               BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1        0x1
-#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_2        0x2
-#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__XOR     0x3
-#define BM_ANADIG_PLL_528_CTRL_ENABLE                  (1 << 13)
-#define BM_ANADIG_PLL_528_CTRL_POWER                   (1 << 12)
-#define BM_ANADIG_PLL_528_CTRL_HOLD_RING_OFF           (1 << 11)
-#define BM_ANADIG_PLL_528_CTRL_DOUBLE_CP               (1 << 10)
-#define BM_ANADIG_PLL_528_CTRL_HALF_CP                 (1 << 9)
-#define BM_ANADIG_PLL_528_CTRL_DOUBLE_LF               (1 << 8)
-#define BM_ANADIG_PLL_528_CTRL_HALF_LF                 (1 << 7)
-#define BM_ANADIG_PLL_528_CTRL_EN_USB_CLKS             (1 << 6)
-#define BP_ANADIG_PLL_528_CTRL_CONTROL0                        2
-#define BM_ANADIG_PLL_528_CTRL_CONTROL0                        (0x7 << BP_ANADIG_PLL_528_CTRL_CONTROL0)
-#define BF_ANADIG_PLL_528_CTRL_CONTROL0(v)             \
-       (((v) << BP_ANADIG_PLL_528_CTRL_CONTROL0) &     \
-               BM_ANADIG_PLL_528_CTRL_CONTROL0)
-#define BP_ANADIG_PLL_528_CTRL_DIV_SELECT              0
-#define BM_ANADIG_PLL_528_CTRL_DIV_SELECT              (0x3 << BP_ANADIG_PLL_528_CTRL_DIV_SELECT)
-#define BF_ANADIG_PLL_528_CTRL_DIV_SELECT(v)           \
-       (((v) << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) &   \
-               BM_ANADIG_PLL_528_CTRL_DIV_SELECT)
-
-#define BM_ANADIG_PLL_AUDIO_LOCK                       (1 << 31)
-#define BM_ANADIG_PLL_AUDIO_SSC_EN                     (1 << 21)
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT            19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT            (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)                         \
-       (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN              (1 << 18)
-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE              (1 << 17)
-#define BM_ANADIG_PLL_AUDIO_BYPASS                     (1 << 16)
-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC             14
-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC             (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)                          \
-       (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M    0x0
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1   0x1
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2   0x2
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR                0x3
-#define BM_ANADIG_PLL_AUDIO_ENABLE                     (1 << 13)
-#define BM_ANADIG_PLL_AUDIO_POWERDOWN                  (1 << 12)
-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF              (1 << 11)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP                  (1 << 10)
-#define BM_ANADIG_PLL_AUDIO_HALF_CP                    (1 << 9)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF                  (1 << 8)
-#define BM_ANADIG_PLL_AUDIO_HALF_LF                    (1 << 7)
-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT                 0
-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT                 (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)         \
-       (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
-               BM_ANADIG_PLL_AUDIO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_AUDIO_NUM_A                      0
-#define BM_ANADIG_PLL_AUDIO_NUM_A                      (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
-#define BF_ANADIG_PLL_AUDIO_NUM_A(v)         \
-       (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
-               BM_ANADIG_PLL_AUDIO_NUM_A)
-
-#define BP_ANADIG_PLL_AUDIO_DENOM_B                    0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B                    (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)         \
-       (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
-               BM_ANADIG_PLL_AUDIO_DENOM_B)
-
-#define BM_ANADIG_PLL_VIDEO_LOCK                       (1 << 31)
-#define BM_ANADIG_PLL_VIDEO_SSC_EN                     (1 << 21)
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT            19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT            (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)         \
-       (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & \
-               BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN              (1 << 18)
-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE              (1 << 17)
-#define BM_ANADIG_PLL_VIDEO_BYPASS                     (1 << 16)
-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC             14
-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC             (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)         \
-       (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
-               BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M    0x0
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1   0x1
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2   0x2
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR                0x3
-#define BM_ANADIG_PLL_VIDEO_ENABLE                     (1 << 13)
-#define BM_ANADIG_PLL_VIDEO_POWERDOWN                  (1 << 12)
-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF              (1 << 11)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP                  (1 << 10)
-#define BM_ANADIG_PLL_VIDEO_HALF_CP                    (1 << 9)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF                  (1 << 8)
-#define BM_ANADIG_PLL_VIDEO_HALF_LF                    (1 << 7)
-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT                 0
-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT                 (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)         \
-       (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
-               BM_ANADIG_PLL_VIDEO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_VIDEO_NUM_A                      0
-#define BM_ANADIG_PLL_VIDEO_NUM_A                      (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
-#define BF_ANADIG_PLL_VIDEO_NUM_A(v)         \
-       (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
-               BM_ANADIG_PLL_VIDEO_NUM_A)
-
-#define BP_ANADIG_PLL_VIDEO_DENOM_B                    0
-#define BM_ANADIG_PLL_VIDEO_DENOM_B                    (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)         \
-       (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
-               BM_ANADIG_PLL_VIDEO_DENOM_B)
-
-#define BM_ANADIG_PLL_MLB_LOCK                         (1 << 31)
-#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG          26
-#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG          (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v)         \
-       (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
-               BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG               23
-#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG               (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v)         \
-       (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
-               BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG                 20
-#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG                 (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v)         \
-       (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
-               BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG                 17
-#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG                 (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
-#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v)         \
-       (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
-               BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
-#define BM_ANADIG_PLL_MLB_BYPASS                       (1 << 16)
-#define BP_ANADIG_PLL_MLB_PHASE_SEL                    12
-#define BM_ANADIG_PLL_MLB_PHASE_SEL                    (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
-#define BF_ANADIG_PLL_MLB_PHASE_SEL(v)         \
-       (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
-               BM_ANADIG_PLL_MLB_PHASE_SEL)
-#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF                        (1 << 11)
-
-#define BM_ANADIG_PLL_ENET_LOCK                                (1 << 31)
-#define BM_ANADIG_PLL_ENET_ENABLE_SATA                 (1 << 20)
-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE                 (1 << 19)
-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN               (1 << 18)
-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE               (1 << 17)
-#define BM_ANADIG_PLL_ENET_BYPASS                      (1 << 16)
-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC              14
-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC              (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)         \
-       (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
-               BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M     0x0
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1    0x1
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2    0x2
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR         0x3
-#define BM_ANADIG_PLL_ENET_ENABLE                      (1 << 13)
-#define BM_ANADIG_PLL_ENET_POWERDOWN                   (1 << 12)
-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF               (1 << 11)
-#define BM_ANADIG_PLL_ENET_DOUBLE_CP                   (1 << 10)
-#define BM_ANADIG_PLL_ENET_HALF_CP                     (1 << 9)
-#define BM_ANADIG_PLL_ENET_DOUBLE_LF                   (1 << 8)
-#define BM_ANADIG_PLL_ENET_HALF_LF                     (1 << 7)
-#define BP_ANADIG_PLL_ENET_DIV_SELECT                  0
-#define BM_ANADIG_PLL_ENET_DIV_SELECT                  (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)         \
-       (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
-               BM_ANADIG_PLL_ENET_DIV_SELECT)
-
-#define BM_ANADIG_PFD_480_PFD3_CLKGATE                 (1 << 31)
-#define BM_ANADIG_PFD_480_PFD3_STABLE                  (1 << 30)
-#define BP_ANADIG_PFD_480_PFD3_FRAC                    24
-#define BM_ANADIG_PFD_480_PFD3_FRAC                    (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
-#define BF_ANADIG_PFD_480_PFD3_FRAC(v)         \
-       (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
-               BM_ANADIG_PFD_480_PFD3_FRAC)
-
-#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY              26
-#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY              (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
-#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)         \
-       (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
-               BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
-#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL               (1 << 25)
-#define BP_ANADIG_ANA_MISC0_ANAMUX                     21
-#define BM_ANADIG_ANA_MISC0_ANAMUX                     (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
-#define BF_ANADIG_ANA_MISC0_ANAMUX(v)         \
-       (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
-               BM_ANADIG_ANA_MISC0_ANAMUX)
-#define BM_ANADIG_ANA_MISC0_ANAMUX_EN                  (1 << 20)
-#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH            18
-#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH            (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
-#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v)         \
-       (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
-               BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
-#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN              (1 << 17)
-#define BM_ANADIG_ANA_MISC0_OSC_XTALOK                 (1 << 16)
-#define BP_ANADIG_ANA_MISC0_OSC_I                      14
-#define BM_ANADIG_ANA_MISC0_OSC_I                      (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
-#define BF_ANADIG_ANA_MISC0_OSC_I(v)         \
-       (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
-               BM_ANADIG_ANA_MISC0_OSC_I)
-#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN             (1 << 13)
-#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG           (1 << 12)
-#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST            8
-#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST            (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
-#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v)         \
-       (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
-               BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
-#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP               (1 << 7)
-#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ              4
-#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ              (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
-#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v)         \
-       (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
-               BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
-#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF          (1 << 3)
-#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER            (1 << 2)
-#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP            (1 << 1)
-#define BM_ANADIG_ANA_MISC0_REFTOP_PWD                 (1 << 0)
-
-#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO                 (1 << 31)
-#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO                 (1 << 30)
-#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO           (1 << 29)
-#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN              (1 << 13)
-#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN              (1 << 12)
-#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN              (1 << 11)
-#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN              (1 << 10)
-#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL              5
-#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL              (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
-#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v)         \
-       (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
-               BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
-#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL              0
-#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL              (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
-#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v)         \
-       (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
-               BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
-
-#define BP_ANADIG_ANA_MISC2_CONTROL3                   30
-#define BM_ANADIG_ANA_MISC2_CONTROL3                   (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
-#define BF_ANADIG_ANA_MISC2_CONTROL3(v)                 \
-       (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
-               BM_ANADIG_ANA_MISC2_CONTROL3)
-#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME             28
-#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME             (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
-#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v)         \
-       (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
-               BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
-#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME             26
-#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME             (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
-#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v)         \
-       (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
-               BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
-#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME             24
-#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME             (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
-#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v)         \
-       (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
-               BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
-#define BM_ANADIG_ANA_MISC2_CONTROL2                   (1 << 23)
-#define BM_ANADIG_ANA_MISC2_REG2_OK                    (1 << 22)
-#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO             (1 << 21)
-#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS             (1 << 19)
-#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET             16
-#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET             (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
-#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v)         \
-       (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
-               BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
-#define BM_ANADIG_ANA_MISC2_CONTROL1                   (1 << 15)
-#define BM_ANADIG_ANA_MISC2_REG1_OK                    (1 << 14)
-#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO             (1 << 13)
-#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS             (1 << 11)
-#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET             8
-#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET             (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
-#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v)         \
-       (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
-               BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
-#define BM_ANADIG_ANA_MISC2_CONTROL0                   (1 << 7)
-#define BM_ANADIG_ANA_MISC2_REG0_OK                    (1 << 6)
-#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO             (1 << 5)
-#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS             (1 << 3)
-#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET             0
-#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET             (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
-#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v)         \
-       (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
-               BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
-
-#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE               20
-#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE               (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
-#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v)         \
-       (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
-               BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
-#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE                        8
-#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE                        (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
-#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v)         \
-       (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
-               BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
-#define BM_ANADIG_TEMPSENSE0_TEST                      (1 << 6)
-#define BP_ANADIG_TEMPSENSE0_VBGADJ                    3
-#define BM_ANADIG_TEMPSENSE0_VBGADJ                    (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
-#define BF_ANADIG_TEMPSENSE0_VBGADJ(v)         \
-       (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
-               BM_ANADIG_TEMPSENSE0_VBGADJ)
-#define BM_ANADIG_TEMPSENSE0_FINISHED                  (1 << 2)
-#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP              (1 << 1)
-#define BM_ANADIG_TEMPSENSE0_POWER_DOWN                        (1 << 0)
-
-#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ              0
-#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ              (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
-#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v)         \
-       (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
-               BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
-
-#define MXC_CCM_CCGR6_USBOH3_OFFSET                    0
-#define MXC_CCM_CCGR6_USBOH3_MASK                      (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC1_OFFSET                    2
-#define MXC_CCM_CCGR6_USDHC1_MASK                      (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
-#define MXC_CCM_CCGR6_USDHC2_OFFSET                    4
-#define MXC_CCM_CCGR6_USDHC2_MASK                      (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
-#define MXC_CCM_CCGR6_USDHC3_OFFSET                    6
-#define MXC_CCM_CCGR6_USDHC3_MASK                      (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC4_OFFSET                    8
-#define MXC_CCM_CCGR6_USDHC4_MASK                      (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
-#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                  10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK                    (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
-#define MXC_CCM_CCGR6_PWM8_OFFSET                      16
-#define MXC_CCM_CCGR6_PWM8_MASK                                (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
-#define MXC_CCM_CCGR6_VADC_OFFSET                      20
-#define MXC_CCM_CCGR6_VADC_MASK                                (3 << MXC_CCM_CCGR6_VADC_OFFSET)
-#define MXC_CCM_CCGR6_GIS_OFFSET                       22
-#define MXC_CCM_CCGR6_GIS_MASK                         (3 << MXC_CCM_CCGR6_GIS_OFFSET)
-#define MXC_CCM_CCGR6_I2C4_OFFSET                      24
-#define MXC_CCM_CCGR6_I2C4_MASK                                (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
-#define MXC_CCM_CCGR6_PWM5_OFFSET                      26
-#define MXC_CCM_CCGR6_PWM5_MASK                                (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
-#define MXC_CCM_CCGR6_PWM6_OFFSET                      28
-#define MXC_CCM_CCGR6_PWM6_MASK                                (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
-#define MXC_CCM_CCGR6_PWM7_OFFSET                      30
-#define MXC_CCM_CCGR6_PWM7_MASK                                (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
-#else
-#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET                 12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK                   (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
-#endif
-
-#define BM_ANADIG_USB_PLL_480_CTRL_LOCK                (1 << 31)
-#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS              (1 << 16)
-#define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC      14
-#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC      (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v)          \
-       (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \
+#define MXC_CCM_CCGR5_SAI1_OFFSET                              20
+#define MXC_CCM_CCGR5_SAI1_MASK                                        (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
+#define MXC_CCM_CCGR5_SAI2_OFFSET                              30
+#define MXC_CCM_CCGR5_SAI2_MASK                                        (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET                            0
+#define MXC_CCM_CCGR6_USBOH3_MASK                              (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET                            2
+#define MXC_CCM_CCGR6_USDHC1_MASK                              (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET                            4
+#define MXC_CCM_CCGR6_USDHC2_MASK                              (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET                            6
+#define MXC_CCM_CCGR6_USDHC3_MASK                              (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET                            8
+#define MXC_CCM_CCGR6_USDHC4_MASK                              (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                          10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK                            (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+/* The following *CCGR6* exist only on i.MX6SX */
+#define MXC_CCM_CCGR6_PWM8_OFFSET                              16
+#define MXC_CCM_CCGR6_PWM8_MASK                                        (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
+#define MXC_CCM_CCGR6_VADC_OFFSET                              20
+#define MXC_CCM_CCGR6_VADC_MASK                                        (3 << MXC_CCM_CCGR6_VADC_OFFSET)
+#define MXC_CCM_CCGR6_GIS_OFFSET                               22
+#define MXC_CCM_CCGR6_GIS_MASK                                 (3 << MXC_CCM_CCGR6_GIS_OFFSET)
+#define MXC_CCM_CCGR6_I2C4_OFFSET                              24
+#define MXC_CCM_CCGR6_I2C4_MASK                                        (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
+#define MXC_CCM_CCGR6_PWM5_OFFSET                              26
+#define MXC_CCM_CCGR6_PWM5_MASK                                        (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
+#define MXC_CCM_CCGR6_PWM6_OFFSET                              28
+#define MXC_CCM_CCGR6_PWM6_MASK                                        (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
+#define MXC_CCM_CCGR6_PWM7_OFFSET                              30
+#define MXC_CCM_CCGR6_PWM7_MASK                                        (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
+/* These two do not exist on i.MX6SX */
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET                         12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK                           (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
+#define BM_ANADIG_USB_PLL_480_CTRL_LOCK                                (1 << 31)
+#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS                      (1 << 16)
+#define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC              14
+#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC              (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v)           \
+       (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) &   \
                BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M     0x0
 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1    0x1
 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2    0x2
 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR         0x3
-#define BM_ANADIG_USB_PLL_480_CTRL_ENABLE              (1 << 13)
-#define BM_ANADIG_USB_PLL_480_CTRL_POWER               (1 << 12)
-#define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF       (1 << 11)
-#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP           (1 << 10)
-#define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP             (1 << 9)
-#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF           (1 << 8)
-#define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF             (1 << 7)
-#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS         (1 << 6)
-#define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0            2
-#define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0            (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
-#define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v)          \
+#define BM_ANADIG_USB_PLL_480_CTRL_ENABLE                      (1 << 13)
+#define BM_ANADIG_USB_PLL_480_CTRL_POWER                       (1 << 12)
+#define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF               (1 << 11)
+#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP                   (1 << 10)
+#define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP                     (1 << 9)
+#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF                   (1 << 8)
+#define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF                     (1 << 7)
+#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS                 (1 << 6)
+#define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0                    2
+#define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0                    (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
+#define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v)         \
        (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
                BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT          0
-#define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT          (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
+#define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT                  0
+#define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT                  (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
 #define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v)          \
        (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
                BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
 
-#define BM_ANADIG_PLL_528_LOCK                         (1 << 31)
-#define BM_ANADIG_PLL_528_PLL_SEL                      (1 << 19)
-#define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL               (1 << 18)
-#define BM_ANADIG_PLL_528_LVDS_SEL                     (1 << 17)
-#define BM_ANADIG_PLL_528_BYPASS                       (1 << 16)
-#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC               14
-#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC               (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_528_LOCK                                 (1 << 31)
+#define BM_ANADIG_PLL_528_PLL_SEL                              (1 << 19)
+#define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL                       (1 << 18)
+#define BM_ANADIG_PLL_528_LVDS_SEL                             (1 << 17)
+#define BM_ANADIG_PLL_528_BYPASS                               (1 << 16)
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC                       14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC                       (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)         \
        (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
                BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M      0x0
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1     0x1
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2     0x2
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR          0x3
-#define BM_ANADIG_PLL_528_ENABLE                       (1 << 13)
-#define BM_ANADIG_PLL_528_POWERDOWN                    (1 << 12)
-#define BM_ANADIG_PLL_528_HOLD_RING_OFF                        (1 << 11)
-#define BM_ANADIG_PLL_528_DOUBLE_CP                    (1 << 10)
-#define BM_ANADIG_PLL_528_HALF_CP                      (1 << 9)
-#define BM_ANADIG_PLL_528_DOUBLE_LF                    (1 << 8)
-#define BM_ANADIG_PLL_528_HALF_LF                      (1 << 7)
-#define BP_ANADIG_PLL_528_DIV_SELECT                   0
-#define BM_ANADIG_PLL_528_DIV_SELECT                   (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M              0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1             0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2             0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR                  0x3
+#define BM_ANADIG_PLL_528_ENABLE                               (1 << 13)
+#define BM_ANADIG_PLL_528_POWERDOWN                            (1 << 12)
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF                                (1 << 11)
+#define BM_ANADIG_PLL_528_DOUBLE_CP                            (1 << 10)
+#define BM_ANADIG_PLL_528_HALF_CP                              (1 << 9)
+#define BM_ANADIG_PLL_528_DOUBLE_LF                            (1 << 8)
+#define BM_ANADIG_PLL_528_HALF_LF                              (1 << 7)
+#define BP_ANADIG_PLL_528_DIV_SELECT                           0
+#define BM_ANADIG_PLL_528_DIV_SELECT                           (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
 #define BF_ANADIG_PLL_528_DIV_SELECT(v)                 \
        (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
                BM_ANADIG_PLL_528_DIV_SELECT)
 
-#define BP_ANADIG_PLL_528_SS_STOP                      16
-#define BM_ANADIG_PLL_528_SS_STOP                      (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
+#define BP_ANADIG_PLL_528_SS_STOP                              16
+#define BM_ANADIG_PLL_528_SS_STOP                              (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
 #define BF_ANADIG_PLL_528_SS_STOP(v)         \
        (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
                BM_ANADIG_PLL_528_SS_STOP)
-#define BM_ANADIG_PLL_528_SS_ENABLE                    (1 << 15)
-#define BP_ANADIG_PLL_528_SS_STEP                      0
-#define BM_ANADIG_PLL_528_SS_STEP                      (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
+#define BM_ANADIG_PLL_528_SS_ENABLE                            (1 << 15)
+#define BP_ANADIG_PLL_528_SS_STEP                              0
+#define BM_ANADIG_PLL_528_SS_STEP                              (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
 #define BF_ANADIG_PLL_528_SS_STEP(v)         \
        (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
                BM_ANADIG_PLL_528_SS_STEP)
 
-#define BP_ANADIG_PLL_528_NUM_A                                0
-#define BM_ANADIG_PLL_528_NUM_A                                (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
+#define BP_ANADIG_PLL_528_NUM_A                                        0
+#define BM_ANADIG_PLL_528_NUM_A                                        (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
 #define BF_ANADIG_PLL_528_NUM_A(v)         \
        (((v) << BP_ANADIG_PLL_528_NUM_A) & \
                BM_ANADIG_PLL_528_NUM_A)
 
-#define BP_ANADIG_PLL_528_DENOM_B                      0
-#define BM_ANADIG_PLL_528_DENOM_B                      (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
+#define BP_ANADIG_PLL_528_DENOM_B                              0
+#define BM_ANADIG_PLL_528_DENOM_B                              (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
 #define BF_ANADIG_PLL_528_DENOM_B(v)         \
        (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
                BM_ANADIG_PLL_528_DENOM_B)
 
-#define BM_ANADIG_PLL_AUDIO_LOCK                       (1 << 31)
-#define BM_ANADIG_PLL_AUDIO_SSC_EN                     (1 << 21)
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT            19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT            (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_LOCK                               (1 << 31)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN                             (1 << 21)
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT                    19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT                    (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)         \
        (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
                BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN              (1 << 18)
-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE              (1 << 17)
-#define BM_ANADIG_PLL_AUDIO_BYPASS                     (1 << 16)
-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC             14
-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC             (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN                      (1 << 18)
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE                      (1 << 17)
+#define BM_ANADIG_PLL_AUDIO_BYPASS                             (1 << 16)
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC                     14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC                     (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)         \
        (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
                BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M    0x0
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1   0x1
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2   0x2
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR                0x3
-#define BM_ANADIG_PLL_AUDIO_ENABLE                     (1 << 13)
-#define BM_ANADIG_PLL_AUDIO_POWERDOWN                  (1 << 12)
-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF              (1 << 11)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP                  (1 << 10)
-#define BM_ANADIG_PLL_AUDIO_HALF_CP                    (1 << 9)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF                  (1 << 8)
-#define BM_ANADIG_PLL_AUDIO_HALF_LF                    (1 << 7)
-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT                 0
-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT                 (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M            0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1           0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2           0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR                        0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE                             (1 << 13)
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN                          (1 << 12)
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF                      (1 << 11)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP                          (1 << 10)
+#define BM_ANADIG_PLL_AUDIO_HALF_CP                            (1 << 9)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF                          (1 << 8)
+#define BM_ANADIG_PLL_AUDIO_HALF_LF                            (1 << 7)
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT                         0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT                         (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)         \
        (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
                BM_ANADIG_PLL_AUDIO_DIV_SELECT)
 
-#define BP_ANADIG_PLL_AUDIO_NUM_A                      0
-#define BM_ANADIG_PLL_AUDIO_NUM_A                      (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
+#define BP_ANADIG_PLL_AUDIO_NUM_A                              0
+#define BM_ANADIG_PLL_AUDIO_NUM_A                              (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
 #define BF_ANADIG_PLL_AUDIO_NUM_A(v)         \
        (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
                BM_ANADIG_PLL_AUDIO_NUM_A)
 
-#define BP_ANADIG_PLL_AUDIO_DENOM_B                    0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B                    (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
+#define BP_ANADIG_PLL_AUDIO_DENOM_B                            0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B                            (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v)         \
        (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
                BM_ANADIG_PLL_AUDIO_DENOM_B)
 
-#define BM_ANADIG_PLL_VIDEO_LOCK                       (1 << 31)
-#define BM_ANADIG_PLL_VIDEO_SSC_EN                     (1 << 21)
-#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT            19
-#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT            (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_LOCK                               (1 << 31)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN                             (1 << 21)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT                    19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT                    (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)         \
        (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
                BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN              (1 << 18)
-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE              (1 << 17)
-#define BM_ANADIG_PLL_VIDEO_BYPASS                     (1 << 16)
-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC             14
-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC             (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN                      (1 << 18)
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE                      (1 << 17)
+#define BM_ANADIG_PLL_VIDEO_BYPASS                             (1 << 16)
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC                     14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC                     (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)         \
        (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
                BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M    0x0
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1   0x1
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2   0x2
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR                0x3
-#define BM_ANADIG_PLL_VIDEO_ENABLE                     (1 << 13)
-#define BM_ANADIG_PLL_VIDEO_POWERDOWN                  (1 << 12)
-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF              (1 << 11)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP                  (1 << 10)
-#define BM_ANADIG_PLL_VIDEO_HALF_CP                    (1 << 9)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF                  (1 << 8)
-#define BM_ANADIG_PLL_VIDEO_HALF_LF                    (1 << 7)
-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT                 0
-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT                 (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M            0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1           0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2           0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR                        0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE                             (1 << 13)
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN                          (1 << 12)
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF                      (1 << 11)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP                          (1 << 10)
+#define BM_ANADIG_PLL_VIDEO_HALF_CP                            (1 << 9)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF                          (1 << 8)
+#define BM_ANADIG_PLL_VIDEO_HALF_LF                            (1 << 7)
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT                         0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT                         (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)         \
        (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
                BM_ANADIG_PLL_VIDEO_DIV_SELECT)
 
-#define BP_ANADIG_PLL_VIDEO_NUM_A                      0
-#define BM_ANADIG_PLL_VIDEO_NUM_A                      (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
+#define BP_ANADIG_PLL_VIDEO_NUM_A                              0
+#define BM_ANADIG_PLL_VIDEO_NUM_A                              (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
 #define BF_ANADIG_PLL_VIDEO_NUM_A(v)         \
        (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
                BM_ANADIG_PLL_VIDEO_NUM_A)
 
-#define BP_ANADIG_PLL_VIDEO_DENOM_B                    0
-#define BM_ANADIG_PLL_VIDEO_DENOM_B                    (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
+#define BP_ANADIG_PLL_VIDEO_DENOM_B                            0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B                            (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v)         \
        (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
                BM_ANADIG_PLL_VIDEO_DENOM_B)
 
-#define BM_ANADIG_PLL_ENET_LOCK                                (1 << 31)
-#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE              (1 << 21)
-#define BM_ANADIG_PLL_ENET_ENABLE_SATA                 (1 << 20)
-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE                 (1 << 19)
-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN               (1 << 18)
-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE               (1 << 17)
-#define BM_ANADIG_PLL_ENET_BYPASS                      (1 << 16)
-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC              14
-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC              (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_ENET_LOCK                                        (1 << 31)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE                      (1 << 21)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA                         (1 << 20)
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE                         (1 << 19)
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN                       (1 << 18)
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE                       (1 << 17)
+#define BM_ANADIG_PLL_ENET_BYPASS                              (1 << 16)
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC                      14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC                      (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)         \
        (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
                BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M     0x0
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1    0x1
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2    0x2
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR         0x3
-#define BM_ANADIG_PLL_ENET_ENABLE                      (1 << 13)
-#define BM_ANADIG_PLL_ENET_POWERDOWN                   (1 << 12)
-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF               (1 << 11)
-#define BM_ANADIG_PLL_ENET_DOUBLE_CP                   (1 << 10)
-#define BM_ANADIG_PLL_ENET_HALF_CP                     (1 << 9)
-#define BM_ANADIG_PLL_ENET_DOUBLE_LF                   (1 << 8)
-#define BM_ANADIG_PLL_ENET_HALF_LF                     (1 << 7)
-#define BP_ANADIG_PLL_ENET_DIV_SELECT                  0
-#define BM_ANADIG_PLL_ENET_DIV_SELECT                  (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M             0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1            0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2            0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR                 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE                              (1 << 13)
+#define BM_ANADIG_PLL_ENET_POWERDOWN                           (1 << 12)
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF                       (1 << 11)
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP                           (1 << 10)
+#define BM_ANADIG_PLL_ENET_HALF_CP                             (1 << 9)
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF                           (1 << 8)
+#define BM_ANADIG_PLL_ENET_HALF_LF                             (1 << 7)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT                          0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT                          (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)         \
        (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
                BM_ANADIG_PLL_ENET_DIV_SELECT)
 
-#define BM_ANADIG_PFD_480_PFD3_CLKGATE                 (1 << 31)
-#define BM_ANADIG_PFD_480_PFD3_STABLE                  (1 << 30)
-#define BP_ANADIG_PFD_480_PFD3_FRAC                    24
-#define BM_ANADIG_PFD_480_PFD3_FRAC                    (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE                         (1 << 31)
+#define BM_ANADIG_PFD_480_PFD3_STABLE                          (1 << 30)
+#define BP_ANADIG_PFD_480_PFD3_FRAC                            24
+#define BM_ANADIG_PFD_480_PFD3_FRAC                            (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
 #define BF_ANADIG_PFD_480_PFD3_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
                BM_ANADIG_PFD_480_PFD3_FRAC)
-#define BM_ANADIG_PFD_480_PFD2_CLKGATE                 (1 << 23)
-#define BM_ANADIG_PFD_480_PFD2_STABLE                  (1 << 22)
-#define BP_ANADIG_PFD_480_PFD2_FRAC                    16
-#define BM_ANADIG_PFD_480_PFD2_FRAC                    (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE                         (1 << 23)
+#define BM_ANADIG_PFD_480_PFD2_STABLE                          (1 << 22)
+#define BP_ANADIG_PFD_480_PFD2_FRAC                            16
+#define BM_ANADIG_PFD_480_PFD2_FRAC                            (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
 #define BF_ANADIG_PFD_480_PFD2_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
                BM_ANADIG_PFD_480_PFD2_FRAC)
-#define BM_ANADIG_PFD_480_PFD1_CLKGATE                 (1 << 15)
-#define BM_ANADIG_PFD_480_PFD1_STABLE                  (1 << 14)
-#define BP_ANADIG_PFD_480_PFD1_FRAC                    8
-#define BM_ANADIG_PFD_480_PFD1_FRAC                    (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE                         (1 << 15)
+#define BM_ANADIG_PFD_480_PFD1_STABLE                          (1 << 14)
+#define BP_ANADIG_PFD_480_PFD1_FRAC                            8
+#define BM_ANADIG_PFD_480_PFD1_FRAC                            (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
 #define BF_ANADIG_PFD_480_PFD1_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
                BM_ANADIG_PFD_480_PFD1_FRAC)
-#define BM_ANADIG_PFD_480_PFD0_CLKGATE                 (1 << 7)
-#define BM_ANADIG_PFD_480_PFD0_STABLE                  (1 << 6)
-#define BP_ANADIG_PFD_480_PFD0_FRAC                    0
-#define BM_ANADIG_PFD_480_PFD0_FRAC                    (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE                         (1 << 7)
+#define BM_ANADIG_PFD_480_PFD0_STABLE                          (1 << 6)
+#define BP_ANADIG_PFD_480_PFD0_FRAC                            0
+#define BM_ANADIG_PFD_480_PFD0_FRAC                            (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
 #define BF_ANADIG_PFD_480_PFD0_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
                BM_ANADIG_PFD_480_PFD0_FRAC)
 
-#define BM_ANADIG_PFD_528_PFD3_CLKGATE                 (1 << 31)
-#define BM_ANADIG_PFD_528_PFD3_STABLE                  (1 << 30)
-#define BP_ANADIG_PFD_528_PFD3_FRAC                    24
-#define BM_ANADIG_PFD_528_PFD3_FRAC                    (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE                         (1 << 31)
+#define BM_ANADIG_PFD_528_PFD3_STABLE                          (1 << 30)
+#define BP_ANADIG_PFD_528_PFD3_FRAC                            24
+#define BM_ANADIG_PFD_528_PFD3_FRAC                            (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
 #define BF_ANADIG_PFD_528_PFD3_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
                BM_ANADIG_PFD_528_PFD3_FRAC)
-#define BM_ANADIG_PFD_528_PFD2_CLKGATE                 (1 << 23)
-#define BM_ANADIG_PFD_528_PFD2_STABLE                  (1 << 22)
-#define BP_ANADIG_PFD_528_PFD2_FRAC                    16
-#define BM_ANADIG_PFD_528_PFD2_FRAC                    (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE                         (1 << 23)
+#define BM_ANADIG_PFD_528_PFD2_STABLE                          (1 << 22)
+#define BP_ANADIG_PFD_528_PFD2_FRAC                            16
+#define BM_ANADIG_PFD_528_PFD2_FRAC                            (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
 #define BF_ANADIG_PFD_528_PFD2_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
                BM_ANADIG_PFD_528_PFD2_FRAC)
-#define BM_ANADIG_PFD_528_PFD1_CLKGATE                 (1 << 15)
-#define BM_ANADIG_PFD_528_PFD1_STABLE                  (1 << 14)
-#define BP_ANADIG_PFD_528_PFD1_FRAC                    8
-#define BM_ANADIG_PFD_528_PFD1_FRAC                    (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE                         (1 << 15)
+#define BM_ANADIG_PFD_528_PFD1_STABLE                          (1 << 14)
+#define BP_ANADIG_PFD_528_PFD1_FRAC                            8
+#define BM_ANADIG_PFD_528_PFD1_FRAC                            (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
 #define BF_ANADIG_PFD_528_PFD1_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
                BM_ANADIG_PFD_528_PFD1_FRAC)
-#define BM_ANADIG_PFD_528_PFD0_CLKGATE                 (1 << 7)
-#define BM_ANADIG_PFD_528_PFD0_STABLE                  (1 << 6)
-#define BP_ANADIG_PFD_528_PFD0_FRAC                    0
-#define BM_ANADIG_PFD_528_PFD0_FRAC                    (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE                         (1 << 7)
+#define BM_ANADIG_PFD_528_PFD0_STABLE                          (1 << 6)
+#define BP_ANADIG_PFD_528_PFD0_FRAC                            0
+#define BM_ANADIG_PFD_528_PFD0_FRAC                            (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)         \
        (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
                BM_ANADIG_PFD_528_PFD0_FRAC)
 
-#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF                  (1 << 3)
 
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */