arm: mx6: fix definition of PLL2 PFD frequencies
authorLothar Waßmann <LW@KARO-electronics.de>
Fri, 9 Jan 2015 10:49:51 +0000 (11:49 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 9 Jan 2015 10:49:51 +0000 (11:49 +0100)
i.MX6Q and i.MX6DL have different values for the PLL2 PFD0 and PFD1
frequencies. Furthermore the actual value for the PFD2 frequency is
396MHz rather than 400MHz.

arch/arm/include/asm/arch-mx6/crm_regs.h

index c5e1ac2..e090f4b 100644 (file)
@@ -965,10 +965,15 @@ struct anatop_regs {
 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v)                   \
        (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
 
+#ifdef CONFIG_MX6Q
 #define PLL2_PFD0_FREQ         352000000
 #define PLL2_PFD1_FREQ         594000000
-#define PLL2_PFD2_FREQ         400000000
-#define PLL2_PFD2_DIV_FREQ     200000000
+#else
+#define PLL2_PFD0_FREQ         306580000
+#define PLL2_PFD1_FREQ         528000000
+#endif
+#define PLL2_PFD2_FREQ         396000000
+#define PLL2_PFD2_DIV_FREQ     (PLL2_PFD2_FREQ / 2)
 #define PLL3_PFD0_FREQ         720000000
 #define PLL3_PFD1_FREQ         540000000
 #define PLL3_PFD2_FREQ         508200000