sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
+ defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#else
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+#ifdef CONFIG_FSL_SATA_V2
SET_SATA_LIODN(1, 555),
SET_SATA_LIODN(2, 556),
+#endif
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-#if defined(CONFIG_PPC_T2080)
{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-#elif defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_PPC_T2081)
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
PCIE4, PCIE4, PCIE4, PCIE4} },
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += p1010rdb.o
obj-y += ddr.o
obj-y += law.o
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ console_init_f();
+
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+#ifdef CONFIG_P1010RDB_PB
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("\nTertiary program loader running in sram...");
+#else
+ puts("\nSecond program loader running in sram...");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
DECLARE_GLOBAL_DATA_PTR;
-
-void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- u32 ddr_ratio;
- unsigned long ddr_freq_mhz;
-
- ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
- ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000;
-
- /* mask off E bit */
- u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- if (ddr_freq_mhz < 700) {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
- } else {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
- }
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
- /* P1014 and it's derivatives support max 16bit DDR width */
- if (svr == SVR_P1014) {
- __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
- __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
- /* For CS0_BNDS we divide the start and end address by 2, so we can just
- * shift the entire register to achieve the desired result and the mask
- * the value so we don't write reserved fields */
- __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
- }
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
puts("\nNAND boot... ");
- /* Initialize the DDR3 */
- sdram_init();
-
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
void board_init_r(gd_t *gd, ulong dest_addr)
{
+ puts("\nSecond program loader running in sram...");
nand_boot();
}
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1)
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1)
#endif
};
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_T2080QDS) += t2080qds.o
-obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o
+obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o
+obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
obj-y += ddr.o
obj-y += law.o
#include <asm/fsl_serdes.h>
#include "../common/qixis.h"
#include "../common/fman.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
+#if defined(CONFIG_T2080QDS)
#define EMI1_SLOT2 6
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
-#define EMI2 7
+#elif defined(CONFIG_T2081QDS)
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT6 6
+#define EMI1_SLOT7 7
+#endif
+#define EMI2 8
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
+#if defined(CONFIG_T2080QDS)
"T2080QDS_MDIO_RGMII1",
"T2080QDS_MDIO_RGMII2",
"T2080QDS_MDIO_SLOT1",
"T2080QDS_MDIO_SLOT5",
"T2080QDS_MDIO_SLOT2",
"T2080QDS_MDIO_10GC",
+#elif defined(CONFIG_T2081QDS)
+ "T2081QDS_MDIO_RGMII1",
+ "T2081QDS_MDIO_RGMII2",
+ "T2081QDS_MDIO_SLOT1",
+ "T2081QDS_MDIO_SLOT2",
+ "T2081QDS_MDIO_SLOT3",
+ "T2081QDS_MDIO_SLOT5",
+ "T2081QDS_MDIO_SLOT6",
+ "T2081QDS_MDIO_SLOT7",
+ "T2081QDS_MDIO_10GC",
+#endif
};
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_T2080QDS)
static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#elif defined(CONFIG_T2081QDS)
+static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
+#endif
-static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
- const char *name = T2080qds_mdio_name_for_muxval(muxval);
+ const char *name = t208xqds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return bus;
}
-struct T2080qds_mdio {
+struct t208xqds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
-static void T2080qds_mux_mdio(u8 muxval)
+static void t208xqds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
- if (muxval < 7) {
+ if (muxval < 8) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
}
}
-static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval);
+ t208xqds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
-static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval);
+ t208xqds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
-static int T2080qds_mdio_reset(struct mii_dev *bus)
+static int t208xqds_mdio_reset(struct mii_dev *bus)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
-static int T2080qds_mdio_init(char *realbusname, u8 muxval)
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
{
- struct T2080qds_mdio *pmdio;
+ struct t208xqds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
- printf("Failed to allocate T2080QDS MDIO bus\n");
+ printf("Failed to allocate t208xqds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
- printf("Failed to allocate T2080QDS private data\n");
+ printf("Failed to allocate t208xqds private data\n");
free(bus);
return -1;
}
- bus->read = T2080qds_mdio_read;
- bus->write = T2080qds_mdio_write;
- bus->reset = T2080qds_mdio_reset;
- sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
+ bus->read = t208xqds_mdio_read;
+ bus->write = t208xqds_mdio_write;
+ bus->reset = t208xqds_mdio_reset;
+ sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
pmdio->muxval = muxval;
bus->priv = pmdio;
-
return mdio_register(bus);
}
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
switch (port) {
+#if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC9:
case FM1_DTSEC10:
- sprintf(alias, "phy_sgmii_s3_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ }
break;
case FM1_DTSEC5:
case FM1_DTSEC6:
fdt_status_okay_by_alias(fdt, "emi1_slot2");
}
break;
+#elif defined(CONFIG_T2081QDS)
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ } else if (mdio_mux[port] == EMI1_SLOT5) {
+ sprintf(alias, "phy_sgmii_s5_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot5");
+ } else if (mdio_mux[port] == EMI1_SLOT6) {
+ sprintf(alias, "phy_sgmii_s6_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot6");
+ } else if (mdio_mux[port] == EMI1_SLOT7) {
+ sprintf(alias, "phy_sgmii_s7_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot7");
+ }
+ break;
+#endif
default:
break;
}
}
/*
- * This function reads RCW to check if Serdes1{E,F,G,H} is configured
- * as slot 1/2/3 and update the lane_to_slot[] array accordingly
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
*/
static void initialize_lane_to_slot(void)
{
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) {
+#if defined(CONFIG_T2080QDS)
case 0x51:
case 0x5f:
case 0x65:
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x6b:
+ lane_to_slot[4] = 1;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xca:
+ case 0xcb:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xf2:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[5] = 4;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 7;
+ break;
+#endif
default:
break;
}
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_T2080QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+#if defined(CONFIG_T2081QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
case 0x95:
case 0xa2:
case 0x94:
- /* SGMII in Slot3 */
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x51:
case 0x5f:
case 0x65:
- /* XAUI/HiGig in Slot3 */
+ /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
fm_info_set_phy_address(FM1_10GEC2, 5);
fm_info_set_phy_address(FM1_10GEC3, 6);
fm_info_set_phy_address(FM1_10GEC4, 7);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
case 0x6d:
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
- /* SGMII in Slot3 */
+ /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
+#if defined(CONFIG_T2080QDS)
case 0xd9:
case 0xd3:
case 0xcb:
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0xca:
+ case 0xcb:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ /* SGMII in Slot5 */
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot6 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ break;
+#endif
+ case 0xf2:
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
default:
break;
}
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
+ mdio_mux[i]));
+ break;
+#if defined(CONFIG_T2081QDS)
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 6:
+ mdio_mux[i] = EMI1_SLOT6;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 7:
+ mdio_mux[i] = EMI1_SLOT7;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
break;
+#endif
}
break;
case PHY_INTERFACE_MODE_RGMII:
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
-#include "t2080qds.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
int brd_mux_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
+ u32 srds_prtcl_s1;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+#if defined(CONFIG_T2080QDS)
+ u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
switch (srds_prtcl_s1) {
case 0:
/* SerDes1 is not enabled */
break;
+#if defined(CONFIG_T2080QDS)
case 0x1c:
case 0xa2:
/* SD1(A:D) => SLOT3 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x51:
+ /* SD1(A:D) => SLOT2 XAUI
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6b:
+ /* SD1(A:D) => XFI SFP Module
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6c:
+ /* SD1(A:B) => XFI SFP Module
+ * SD1(C:D) => SLOT2 SGMII
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xe8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0x6d:
+ /* SD1(A:B) => XFI SFP Module
+ * SD1(C:D) => SLOT2 SGMII
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xe8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xaa:
+ case 0xab:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(F:H) => SLOT1 SGMI4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xf8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xca:
+ case 0xcb:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B) => SLOT7 SGMII
+ * SD1(C) => SLOT6 SGMII
+ * SD1(D) => SLOT5 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0xde:
+ case 0xdf:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x25);
+ break;
+ case 0xf2:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B:D) => SLOT7 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x81);
+ QIXIS_WRITE(brdcfg[13], 0xa5);
+ break;
+#endif
default:
printf("WARNING: unsupported for SerDes1 Protocol %d\n",
srds_prtcl_s1);
return -1;
}
+#ifdef CONFIG_T2080QDS
switch (srds_prtcl_s2) {
case 0:
/* SerDes2 is not enabled */
srds_prtcl_s2);
return -1;
}
+#endif
return 0;
}
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __T2080QDS_QIXIS_H__
-#define __T2080QDS_QIXIS_H__
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
-/* Definitions of QIXIS Registers for T2080QDS */
+/* Definitions of QIXIS Registers for T208xQDS */
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+#define BRDCFG9_SFP_TX_EN 0x10
+
#define BRDCFG12_SD3EN_MASK 0x20
#define BRDCFG12_SD3MX_MASK 0x08
#define BRDCFG12_SD3MX_SLOT5 0x08
Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
void env_relocate_spec(void)
{
- char buf[CONFIG_ENV_SIZE];
int ret;
+ char *buf = NULL;
+ buf = (char *)malloc(CONFIG_ENV_SIZE);
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!env_flash) {
set_default_env("!spi_flash_probe() failed");
+ if (buf)
+ free(buf);
return;
}
gd->env_valid = 1;
out:
spi_flash_free(env_flash);
+ if (buf)
+ free(buf);
env_flash = NULL;
}
#endif
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
+ phydev->supported = phydev->drv->features;
return 0;
}
#endif
}
- if (!strcmp(phy_type, "utmi")) {
+ if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
setbits_be32(&ehci->control, UTMI_PHY_EN);
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
#define CONFIG_SYS_NAND_U_BOOT_START \
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
- #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
- #define CONFIG_ENV_ADDR 0xfff80000
- #else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_NAND_FSL_IFC
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
+#ifdef CONFIG_SECURE_BOOT
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL
+#ifdef CONFIG_SECURE_BOOT
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#else
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xD0001000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
#endif
-
#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
#define CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
/*
* Environment
*/
-#if defined(CONFIG_RAMBOOT_SDCARD)
+#if defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#elif defined(CONFIG_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
#if defined(CONFIG_P1010RDB_PA)
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
#endif
-#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#define CONFIG_ENV_OFFSET (1024 * 1024)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
*/
/*
- * T2080 QDS board configuration file
+ * T2080/T2081 QDS board configuration file
*/
-#ifndef __T2080QDS_H
-#define __T2080QDS_H
+#ifndef __T208xQDS_H
+#define __T208xQDS_H
-#define CONFIG_T2080QDS
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
#define CONFIG_SPI_FLASH
#define CONFIG_USB_EHCI
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_T2080QDS
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_T2081QDS
+#endif
/* High Level Configuration Options */
#define CONFIG_PHYS_64BIT
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
+#endif
#endif
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_STMICRO
+#if defined(CONFIG_T2080QDS)
#define CONFIG_SPI_FLASH_SPANSION
+#elif defined(CONFIG_T2081QDS)
+#define CONFIG_SPI_FLASH_EON
+#endif
+
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_NET_MULTI
#define CONFIG_E1000
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_CMD_USB
#endif
-#endif /* __T2080QDS_H */
+#endif /* __T208xQDS_H */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
-#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
+#endif
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
projects / karo-tx-uboot.git / commitdiff