imx:mx6ul add clock support
authorPeng Fan <Peng.Fan@freescale.com>
Mon, 20 Jul 2015 11:28:27 +0000 (19:28 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Wed, 9 Sep 2015 18:08:23 +0000 (20:08 +0200)
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
   MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
   but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
   sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
   || defined....", only need one CONFIG_PCIE_IMX in header file.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h

index 259b315..c9f604e 100644 (file)
@@ -175,19 +175,32 @@ void enable_usboh3_clk(unsigned char enable)
 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 void enable_enet_clk(unsigned char enable)
 {
-       u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+       u32 mask, *addr;
+
+       if (is_cpu_type(MXC_CPU_MX6UL)) {
+               mask = MXC_CCM_CCGR3_ENET_MASK;
+               addr = &imx_ccm->CCGR3;
+       } else {
+               mask = MXC_CCM_CCGR1_ENET_MASK;
+               addr = &imx_ccm->CCGR1;
+       }
 
        if (enable)
-               setbits_le32(&imx_ccm->CCGR1, mask);
+               setbits_le32(addr, mask);
        else
-               clrbits_le32(&imx_ccm->CCGR1, mask);
+               clrbits_le32(addr, mask);
 }
 #endif
 
 #ifdef CONFIG_MXC_UART
 void enable_uart_clk(unsigned char enable)
 {
-       u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
+       u32 mask;
+
+       if (is_cpu_type(MXC_CPU_MX6UL))
+               mask = MXC_CCM_CCGR5_UART_MASK;
+       else
+               mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 
        if (enable)
                setbits_le32(&imx_ccm->CCGR5, mask);
@@ -235,7 +248,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
-               if (is_cpu_type(MXC_CPU_MX6SX)) {
+               if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
                        mask = MXC_CCM_CCGR6_I2C4_MASK;
                        addr = &imx_ccm->CCGR6;
                } else {
@@ -293,9 +306,9 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
                return infreq * (20 + div * 2);
        case PLL_USBOTG:
                div = __raw_readl(&anatop->usb1_pll_480_ctrl);
-               if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+               if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
                        return infreq;
-               div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+               div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 
                return infreq * (20 + div * 2);
        case PLL_AUDIO:
@@ -321,9 +334,9 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
                return 25000000 * (div + (div >> 1) + 1);
        case PLL_USB2:
                div = __raw_readl(&anatop->usb2_pll_480_ctrl);
-               if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+               if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
                        return infreq;
-               div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+               div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 
                return infreq * (20 + div * 2);
        case PLL_MLB:
@@ -343,9 +356,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
        switch (pll) {
        case PLL_528:
-               if (pfd_num == 3) {
-                       /* No PFD3 on PLL2 */
-                       return 0;
+               if (!is_cpu_type(MXC_CPU_MX6UL)) {
+                       if (pfd_num == 3) {
+                               /* No PFD3 on PPL2 */
+                               return 0;
+                       }
                }
                div = __raw_readl(&anatop->pfd_528);
                freq = (u64)decode_pll(PLL_528, MXC_HCLK);
@@ -377,10 +392,12 @@ static u32 get_mcu_main_clk(void)
 
 u32 get_periph_clk(void)
 {
-       u32 reg, freq = 0;
+       u32 reg, div = 0, freq = 0;
 
        reg = __raw_readl(&imx_ccm->cbcdr);
        if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+               div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
+                      MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
                reg = __raw_readl(&imx_ccm->cbcmr);
                reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
                reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
@@ -416,7 +433,7 @@ u32 get_periph_clk(void)
                }
        }
 
-       return freq;
+       return freq / (div + 1);
 }
 
 static u32 get_ipg_clk(void)
@@ -436,7 +453,7 @@ static u32 get_ipg_per_clk(void)
 
        reg = __raw_readl(&imx_ccm->cscmr1);
        if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-           is_mx6dqp()) {
+           is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
                if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
                        return MXC_HCLK; /* OSC 24Mhz */
        }
@@ -453,7 +470,7 @@ static u32 get_uart_clk(void)
        reg = __raw_readl(&imx_ccm->cscdr1);
 
        if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-           is_mx6dqp()) {
+           is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
                if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                        freq = MXC_HCLK;
        }
@@ -472,7 +489,8 @@ static u32 get_cspi_clk(void)
        cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
                     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-       if (is_mx6dqp()) {
+       if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
+           is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
                if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
                        return MXC_HCLK / (cspi_podf + 1);
        }
@@ -483,7 +501,7 @@ static u32 get_cspi_clk(void)
 static u32 get_axi_clk(void)
 {
        u32 root_freq, axi_podf;
-       u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
+       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 
        axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
        axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
@@ -493,9 +511,9 @@ static u32 get_axi_clk(void)
                        root_freq = mxc_get_pll_pfd(PLL_528, 2);
                else
                        root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
-       } else
+       } else {
                root_freq = get_periph_clk();
-
+       }
        return  root_freq / (axi_podf + 1);
 }
 
@@ -549,6 +567,8 @@ static u32 get_nfc_clk(void)
        case 3:
                root_freq = mxc_get_pll_pfd(PLL_528, 2);
                break;
+       default:
+               return 0;
        }
 
        return root_freq / (pred + 1) / (podf + 1);
@@ -625,47 +645,60 @@ static int set_nfc_clk(u32 ref, u32 freq_khz)
        return 0;
 }
 
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
        u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-       u32 freq, podf;
 
-       podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
-                       >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
-
-       switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
-               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
-       case 0:
-               freq = decode_pll(PLL_528, MXC_HCLK);
-               break;
-       case 1:
-               freq = mxc_get_pll_pfd(PLL_528, 2);
-               break;
-       case 2:
-               freq = mxc_get_pll_pfd(PLL_528, 0);
-               break;
-       case 3:
-               /* static / 2 divider */
-               freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
+       u32 freq, podf, per2_clk2_podf;
+
+       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+           is_cpu_type(MXC_CPU_MX6SL)) {
+               podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
+                       MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+               if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
+                       per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
+                               MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
+                       if (is_cpu_type(MXC_CPU_MX6SL)) {
+                               if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+                                       freq = MXC_HCLK;
+                               else
+                                       freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+                       } else {
+                               if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+                                       freq = decode_pll(PLL_528, MXC_HCLK);
+                               else
+                                       freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+                       }
+               } else {
+                       per2_clk2_podf = 0;
+                       switch ((cbcmr &
+                               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+                               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+                       case 0:
+                               freq = decode_pll(PLL_528, MXC_HCLK);
+                               break;
+                       case 1:
+                               freq = mxc_get_pll_pfd(PLL_528, 2);
+                               break;
+                       case 2:
+                               freq = mxc_get_pll_pfd(PLL_528, 0);
+                               break;
+                       case 3:
+                               /* static / 2 divider */
+                               freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
+                               break;
+                       }
+               }
+               return freq / (podf + 1) / (per2_clk2_podf + 1);
+       } else {
+               podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+                       MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+               return get_periph_clk() / (podf + 1);
        }
-
-       return freq / (podf + 1);
-
-}
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
-       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-       u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
-                               MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
-       return get_periph_clk() / (mmdc_ch0_podf + 1);
 }
-#endif
 
-#ifdef CONFIG_SOC_MX6SX
+#ifdef CONFIG_FSL_QSPI
 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
 {
@@ -826,6 +859,7 @@ u32 imx_get_fecclk(void)
        return mxc_get_clock(MXC_IPG_CLK);
 }
 
+#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 static int enable_enet_pll(uint32_t en)
 {
        u32 reg;
@@ -848,8 +882,9 @@ static int enable_enet_pll(uint32_t en)
        writel(reg, &anatop->pll_enet);
        return 0;
 }
+#endif
 
-#ifndef CONFIG_SOC_MX6SX
+#ifdef CONFIG_CMD_SATA
 static void ungate_sata_clock(void)
 {
        struct mxc_ccm_reg *const imx_ccm =
@@ -858,18 +893,7 @@ static void ungate_sata_clock(void)
        /* Enable SATA clock. */
        setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 }
-#endif
-
-static void ungate_pcie_clock(void)
-{
-       struct mxc_ccm_reg *const imx_ccm =
-               (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-       /* Enable PCIe clock. */
-       setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
-}
 
-#ifndef CONFIG_SOC_MX6SX
 int enable_sata_clock(void)
 {
        ungate_sata_clock();
@@ -885,6 +909,16 @@ void disable_sata_clock(void)
 }
 #endif
 
+#ifdef CONFIG_PCIE_IMX
+static void ungate_pcie_clock(void)
+{
+       struct mxc_ccm_reg *const imx_ccm =
+               (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       /* Enable PCIe clock. */
+       setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
 int enable_pcie_clock(void)
 {
        struct anatop_regs *anatop_regs =
@@ -924,7 +958,7 @@ int enable_pcie_clock(void)
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
        /* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_SOC_MX6SX
+#ifdef CONFIG_CMD_SATA
        ungate_sata_clock();
 #endif
        ungate_pcie_clock();
@@ -932,6 +966,7 @@ int enable_pcie_clock(void)
        return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
                               BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
+#endif
 
 #ifdef CONFIG_SECURE_BOOT
 void hab_caam_clock_enable(unsigned char enable)
@@ -967,20 +1002,20 @@ static void enable_pll3(void)
 
        /* make sure pll3 is enabled */
        if ((readl(&anatop->usb1_pll_480_ctrl) &
-                       BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
+                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
                /* enable pll's power */
-               writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
                       &anatop->usb1_pll_480_ctrl_set);
                writel(0x80, &anatop->ana_misc2_clr);
                /* wait for pll lock */
                while ((readl(&anatop->usb1_pll_480_ctrl) &
-                       BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
+                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
                        ;
                /* disable bypass */
-               writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
                       &anatop->usb1_pll_480_ctrl_clr);
                /* enable pll output */
-               writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
                       &anatop->usb1_pll_480_ctrl_set);
        }
 }
index aeb2e5e..1bebafe 100644 (file)
@@ -62,6 +62,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_RBC_EN                             (1 << 27)
 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                        (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET              21
+/* CCR_WB does not exist on i.MX6SX/UL */
 #define MXC_CCM_CCR_WB_COUNT_MASK                      (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
 #define MXC_CCM_CCR_WB_COUNT_OFFSET                    (1 << 16)
 #define MXC_CCM_CCR_COSC_EN                            (1 << 12)
@@ -102,12 +103,11 @@ struct mxc_ccm_reg {
 /* Define the bits in register CBCDR */
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK            (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET          27
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                 (1 << 26)
+#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL                  (1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                   (1 << 25)
-#ifndef CONFIG_SOC_MX6SX
+/* MMDC_CH0 not exists on i.MX6SX */
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK               (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET             19
-#endif
 #define MXC_CCM_CBCDR_AXI_PODF_MASK                    (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET                  16
 #define MXC_CCM_CBCDR_AHB_PODF_MASK                    (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
@@ -130,7 +130,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET           23
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK         (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET       21
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL             (1 << 20)
+#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL                 (1 << 20)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET                18
 #ifndef CONFIG_SOC_MX6SX
@@ -155,18 +155,19 @@ struct mxc_ccm_reg {
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET            29
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                 (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET               26
-#else
 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK                   (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET                 27
-#endif
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK         (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET       23
 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK              (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET            20
+/* CSCMR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCMR1_GPMI_CLK_SEL                    (1 << 19)
+#define MXC_CCM_CSCMR1_BCH_CLK_SEL                     (1 << 18)
 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL                  (1 << 19)
 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL                  (1 << 18)
 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL                  (1 << 17)
@@ -177,12 +178,11 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             12
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             10
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
-#endif
 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
-#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                        (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6
 
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        0x3F
@@ -197,10 +197,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)
 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              8
 
-#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK               (0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK               (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET             2
 
 /* Define the bits in register CSCDR1 */
@@ -208,6 +208,12 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK               (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET             25
 #endif
+/* CSCDR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCDR1_GPMI_PODF_MASK                  (0x7 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)
+#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET                        22
+#define MXC_CCM_CSCDR1_BCH_PODF_MASK                   (0x7 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET)
+#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET                 19
+
 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                        (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET              22
 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                        (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
@@ -222,7 +228,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 #endif
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              0x3F
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            0
 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << 6)
@@ -242,7 +248,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            0
 
 /* Define the bits in register CS2CDR */
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI2 on i.MX6SX */
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)               (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
@@ -252,7 +258,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK              (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET            15
 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                        (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
-#else
+
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK              (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET            21
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                        (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
@@ -260,14 +266,26 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET            18
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                        (((v) & 0x7) << 18)
 
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK       \
-       (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET     \
-       (is_mx6dqp() ? 15 : 16)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)         \
-       (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP           (0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP         15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v)             (((v) & 0x7) << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ            (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ          16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)              (((v) & 0x3) << 16)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK               \
+       ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
+        MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP :         \
+        MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET             \
+       ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
+        MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP :       \
+        MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)                 \
+       ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
+        MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :           \
+        MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
 
-#endif
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK            (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET          12
 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK            (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
@@ -496,10 +514,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_ECSPI4S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                   8
 #define MXC_CCM_CCGR1_ECSPI5S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
-#ifndef CONFIG_SOC_MX6SX
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET           10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK             (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
-#endif
+/* CCGR1_ENET does not exist on i.MX6SX/UL */
+#define MXC_CCM_CCGR1_ENET_OFFSET                      10
+#define MXC_CCM_CCGR1_ENET_MASK                                (3 << MXC_CCM_CCGR1_ENET_OFFSET)
 #define MXC_CCM_CCGR1_EPIT1S_OFFSET                    12
 #define MXC_CCM_CCGR1_EPIT1S_MASK                      (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
 #define MXC_CCM_CCGR1_EPIT2S_OFFSET                    14
@@ -570,21 +587,21 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 #endif
 
-#ifdef CONFIG_SOC_MX6SX
+/* Exist on i.MX6SX */
 #define MXC_CCM_CCGR3_M4_OFFSET                                        2
 #define MXC_CCM_CCGR3_M4_MASK                                  (3 << MXC_CCM_CCGR3_M4_OFFSET)
 #define MXC_CCM_CCGR3_ENET_OFFSET                              4
 #define MXC_CCM_CCGR3_ENET_MASK                                        (3 << MXC_CCM_CCGR3_ENET_OFFSET)
 #define MXC_CCM_CCGR3_QSPI_OFFSET                              14
 #define MXC_CCM_CCGR3_QSPI_MASK                                        (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
-#else
+
 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET                          0
 #define MXC_CCM_CCGR3_IPU1_IPU_MASK                            (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET                      2
 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK                                (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET                      4
 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK                                (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
-#endif
+
 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET                          6
 #define MXC_CCM_CCGR3_IPU2_IPU_MASK                            (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET                      8
@@ -593,15 +610,22 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                                (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                           12
 #define MXC_CCM_CCGR3_LDB_DI0_MASK                             (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
+
+/* QSPI1 exists on i.MX6SX/UL */
 #define MXC_CCM_CCGR3_QSPI1_OFFSET                             14
 #define MXC_CCM_CCGR3_QSPI1_MASK                               (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
-#else
+
 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET                           14
 #define MXC_CCM_CCGR3_LDB_DI1_MASK                             (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET                     16
 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK                       (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
-#endif
+
+/* A7_CLKDIV/WDOG1 on i.MX6UL */
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET                  16
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK                    (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET                   18
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK                     (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
+
 #define MXC_CCM_CCGR3_MLB_OFFSET                               18
 #define MXC_CCM_CCGR3_MLB_MASK                                 (3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET       20
@@ -614,22 +638,28 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK                        (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET              26
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                        (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+/* AXI on i.MX6UL */
+#define MXC_CCM_CCGR3_AXI_CLK_OFFSET                           28
+#define MXC_CCM_CCGR3_AXI_CLK_MASK                             (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
 #define MXC_CCM_CCGR3_OCRAM_OFFSET                             28
 #define MXC_CCM_CCGR3_OCRAM_MASK                               (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
-#ifndef CONFIG_SOC_MX6SX
+
+/* GPIO4 on i.MX6UL */
+#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET                         30
+#define MXC_CCM_CCGR3_GPIO4_CLK_MASK                           (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
+
+#ifndef CONFIG_MX6SX
 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                      30
 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 #endif
 
 #define MXC_CCM_CCGR4_PCIE_OFFSET                              0
 #define MXC_CCM_CCGR4_PCIE_MASK                                        (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI2 on i.MX6SX */
 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET                                10
 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK                          (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
-#else
 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET              8
 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK                        (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
-#endif
 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET                        12
 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK                  (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET     14
@@ -680,12 +710,22 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_SAI2_MASK                                        (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
 #endif
 
+/* PRG_CLK0 exists on i.MX6QP */
+#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET                          24
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK                            (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
+
 #define MXC_CCM_CCGR6_USBOH3_OFFSET                            0
 #define MXC_CCM_CCGR6_USBOH3_MASK                              (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC1_OFFSET                            2
 #define MXC_CCM_CCGR6_USDHC1_MASK                              (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
 #define MXC_CCM_CCGR6_USDHC2_OFFSET                            4
 #define MXC_CCM_CCGR6_USDHC2_MASK                              (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+/* GPMI/BCH on i.MX6UL */
+#define MXC_CCM_CCGR6_BCH_OFFSET                               6
+#define MXC_CCM_CCGR6_BCH_MASK                                 (3 << MXC_CCM_CCGR6_BCH_OFFSET)
+#define MXC_CCM_CCGR6_GPMI_OFFSET                              8
+#define MXC_CCM_CCGR6_GPMI_MASK                                        (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
+
 #define MXC_CCM_CCGR6_USDHC3_OFFSET                            6
 #define MXC_CCM_CCGR6_USDHC3_MASK                              (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC4_OFFSET                            8
@@ -711,35 +751,62 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET                         12
 #define MXC_CCM_CCGR6_VDOAXICLK_MASK                           (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
 
-#define BM_ANADIG_USB_PLL_480_CTRL_LOCK                                (1 << 31)
-#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS                      (1 << 16)
-#define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC              14
-#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC              (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v)           \
-       (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) &   \
-               BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M     0x0
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1    0x1
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2    0x2
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR         0x3
-#define BM_ANADIG_USB_PLL_480_CTRL_ENABLE                      (1 << 13)
-#define BM_ANADIG_USB_PLL_480_CTRL_POWER                       (1 << 12)
-#define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF               (1 << 11)
-#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP                   (1 << 10)
-#define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP                     (1 << 9)
-#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF                   (1 << 8)
-#define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF                     (1 << 7)
-#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS                 (1 << 6)
-#define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0                    2
-#define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0                    (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
-#define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v)         \
-       (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
-               BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT                  0
-#define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT                  (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
-#define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v)          \
-       (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
-               BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
+#define BM_ANADIG_PLL_ARM_LOCK                                 (1 << 31)
+#define BM_ANADIG_PLL_ARM_PLL_SEL                              (1 << 19)
+#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL                       (1 << 18)
+#define BM_ANADIG_PLL_ARM_LVDS_SEL                             (1 << 17)
+#define BM_ANADIG_PLL_ARM_BYPASS                               (1 << 16)
+#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC                       14
+#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC                       (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v)         \
+       (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
+               BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M              0x0
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1             0x1
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2             0x2
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR                  0x3
+#define BM_ANADIG_PLL_ARM_ENABLE                               (1 << 13)
+#define BM_ANADIG_PLL_ARM_POWERDOWN                            (1 << 12)
+#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF                                (1 << 11)
+#define BM_ANADIG_PLL_ARM_DOUBLE_CP                            (1 << 10)
+#define BM_ANADIG_PLL_ARM_HALF_CP                              (1 << 9)
+#define BM_ANADIG_PLL_ARM_DOUBLE_LF                            (1 << 8)
+#define BM_ANADIG_PLL_ARM_HALF_LF                              (1 << 7)
+#define BP_ANADIG_PLL_ARM_DIV_SELECT                           0
+#define BM_ANADIG_PLL_ARM_DIV_SELECT                           (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
+#define BF_ANADIG_PLL_ARM_DIV_SELECT(v)                 \
+       (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
+               BM_ANADIG_PLL_ARM_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK                               (1 << 31)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS                     (1 << 16)
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC             14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC             (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)          \
+       (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) &  \
+               BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M    0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1   0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2   0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR                0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE                     (1 << 13)
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER                      (1 << 12)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF              (1 << 11)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP                  (1 << 10)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP                    (1 << 9)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF                  (1 << 8)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF                    (1 << 7)
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS                        (1 << 6)
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0                   2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0                   (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)                \
+       (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
+               BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT                 0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT                 (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)         \
+       (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
+               BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
 
 #define BM_ANADIG_PLL_528_LOCK                                 (1 << 31)
 #define BM_ANADIG_PLL_528_PLL_SEL                              (1 << 19)
@@ -880,6 +947,35 @@ struct mxc_ccm_reg {
        (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
                BM_ANADIG_PLL_VIDEO_DENOM_B)
 
+#define BM_ANADIG_PLL_MLB_LOCK                                 (1 << 31)
+#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG                  26
+#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG                  (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v)         \
+       (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
+               BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG                       23
+#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG                       (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v)         \
+       (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
+               BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG                         20
+#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG                         (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v)         \
+       (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
+               BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG                         17
+#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG                         (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v)         \
+       (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
+               BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BM_ANADIG_PLL_MLB_BYPASS                               (1 << 16)
+#define BP_ANADIG_PLL_MLB_PHASE_SEL                            12
+#define BM_ANADIG_PLL_MLB_PHASE_SEL                            (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
+#define BF_ANADIG_PLL_MLB_PHASE_SEL(v)         \
+       (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
+               BM_ANADIG_PLL_MLB_PHASE_SEL)
+#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF                                (1 << 11)
+
 #define BM_ANADIG_PLL_ENET_LOCK                                        (1 << 31)
 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE                      (1 << 21)
 #define BM_ANADIG_PLL_ENET_ENABLE_SATA                         (1 << 20)
@@ -967,6 +1063,139 @@ struct mxc_ccm_reg {
        (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
                BM_ANADIG_PFD_528_PFD0_FRAC)
 
+#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY                      26
+#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY                      (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)         \
+       (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
+               BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL                       (1 << 25)
+#define BP_ANADIG_ANA_MISC0_ANAMUX                             21
+#define BM_ANADIG_ANA_MISC0_ANAMUX                             (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
+#define BF_ANADIG_ANA_MISC0_ANAMUX(v)         \
+       (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
+               BM_ANADIG_ANA_MISC0_ANAMUX)
+#define BM_ANADIG_ANA_MISC0_ANAMUX_EN                          (1 << 20)
+#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH                    18
+#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH                    (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v)         \
+       (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
+               BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN                      (1 << 17)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK                         (1 << 16)
+#define BP_ANADIG_ANA_MISC0_OSC_I                              14
+#define BM_ANADIG_ANA_MISC0_OSC_I                              (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
+#define BF_ANADIG_ANA_MISC0_OSC_I(v)         \
+       (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
+               BM_ANADIG_ANA_MISC0_OSC_I)
+#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN                     (1 << 13)
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG                   (1 << 12)
+#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST                    8
+#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST                    (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v)         \
+       (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
+               BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP                       (1 << 7)
+#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ                      4
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ                      (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
+#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v)         \
+       (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
+               BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF                  (1 << 3)
+#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER                    (1 << 2)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP                    (1 << 1)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWD                         (1 << 0)
+
+#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO                         (1 << 31)
+#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO                         (1 << 30)
+#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO                   (1 << 29)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN                      (1 << 13)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN                      (1 << 12)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN                      (1 << 11)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN                      (1 << 10)
+#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL                      5
+#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL                      (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v)         \
+       (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
+               BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL                      0
+#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL                      (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v)         \
+       (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
+               BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+
+#define BP_ANADIG_ANA_MISC2_CONTROL3                           30
+#define BM_ANADIG_ANA_MISC2_CONTROL3                           (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
+#define BF_ANADIG_ANA_MISC2_CONTROL3(v)                 \
+       (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
+               BM_ANADIG_ANA_MISC2_CONTROL3)
+#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME                     28
+#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME                     (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v)         \
+       (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
+               BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME                     26
+#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME                     (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v)         \
+       (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
+               BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME                     24
+#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME                     (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v)         \
+       (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
+               BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BM_ANADIG_ANA_MISC2_CONTROL2                           (1 << 23)
+#define BM_ANADIG_ANA_MISC2_REG2_OK                            (1 << 22)
+#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO                     (1 << 21)
+#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS                     (1 << 19)
+#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET                     16
+#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET                     (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v)         \
+       (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
+               BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL1                           (1 << 15)
+#define BM_ANADIG_ANA_MISC2_REG1_OK                            (1 << 14)
+#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO                     (1 << 13)
+#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS                     (1 << 11)
+#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET                     8
+#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET                     (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
+#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v)         \
+       (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
+               BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL0                           (1 << 7)
+#define BM_ANADIG_ANA_MISC2_REG0_OK                            (1 << 6)
+#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO                     (1 << 5)
+#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS                     (1 << 3)
+#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET                     0
+#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET                     (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v)         \
+       (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
+               BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+
+#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE                       20
+#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE                       (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v)         \
+       (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
+               BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE                                8
+#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE                                (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v)         \
+       (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
+               BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BM_ANADIG_TEMPSENSE0_TEST                              (1 << 6)
+#define BP_ANADIG_TEMPSENSE0_VBGADJ                            3
+#define BM_ANADIG_TEMPSENSE0_VBGADJ                            (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
+#define BF_ANADIG_TEMPSENSE0_VBGADJ(v)         \
+       (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
+               BM_ANADIG_TEMPSENSE0_VBGADJ)
+#define BM_ANADIG_TEMPSENSE0_FINISHED                          (1 << 2)
+#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP                      (1 << 1)
+#define BM_ANADIG_TEMPSENSE0_POWER_DOWN                                (1 << 0)
+
+#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ                      0
+#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ                      (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v)         \
+       (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
+               BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+
 
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
index 7d72156..c0f8f4a 100644 (file)
 #define CONFIG_SYS_CACHELINE_SIZE      32
 #endif
 
-#define ROMCP_ARB_BASE_ADDR             0x00000000
-#define ROMCP_ARB_END_ADDR              0x000FFFFF
+#define ROMCP_ARB_BASE_ADDR            0x00000000
+#define ROMCP_ARB_END_ADDR             0x000FFFFF
 
 #ifdef CONFIG_SOC_MX6SL
-#define GPU_2D_ARB_BASE_ADDR            0x02200000
-#define GPU_2D_ARB_END_ADDR             0x02203FFF
-#define OPENVG_ARB_BASE_ADDR            0x02204000
-#define OPENVG_ARB_END_ADDR             0x02207FFF
+#define GPU_2D_ARB_BASE_ADDR           0x02200000
+#define GPU_2D_ARB_END_ADDR            0x02203FFF
+#define OPENVG_ARB_BASE_ADDR           0x02204000
+#define OPENVG_ARB_END_ADDR            0x02207FFF
 #elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define CAAM_ARB_BASE_ADDR              0x00100000
-#define CAAM_ARB_END_ADDR               0x00107FFF
-#define GPU_ARB_BASE_ADDR               0x01800000
-#define GPU_ARB_END_ADDR                0x01803FFF
-#define APBH_DMA_ARB_BASE_ADDR          0x01804000
-#define APBH_DMA_ARB_END_ADDR           0x0180BFFF
+#define CAAM_ARB_BASE_ADDR             0x00100000
+#define CAAM_ARB_END_ADDR              0x00107FFF
+#define GPU_ARB_BASE_ADDR              0x01800000
+#define GPU_ARB_END_ADDR               0x01803FFF
+#define APBH_DMA_ARB_BASE_ADDR         0x01804000
+#define APBH_DMA_ARB_END_ADDR          0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR                   0x007F8000
 
 #else
@@ -55,7 +55,7 @@
 
 /* GPV - PL301 configuration ports */
 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define GPV2_BASE_ADDR                  0x00D00000
+#define GPV2_BASE_ADDR                 0x00D00000
 #else
 #define GPV2_BASE_ADDR                 0x00200000
 #endif
 #define PRIVATE_TIMERS_WD_BASE_ADDR    0x00A00600
 #define IC_DISTRIBUTOR_BASE_ADDR       0x00A01000
 #define L2_PL310_BASE                  0x00A02000
-#define GPV0_BASE_ADDR                  0x00B00000
-#define GPV1_BASE_ADDR                  0x00C00000
+#define GPV0_BASE_ADDR                 0x00B00000
+#define GPV1_BASE_ADDR                 0x00C00000
 
-#define AIPS1_ARB_BASE_ADDR             0x02000000
-#define AIPS1_ARB_END_ADDR              0x020FFFFF
-#define AIPS2_ARB_BASE_ADDR             0x02100000
-#define AIPS2_ARB_END_ADDR              0x021FFFFF
+#define AIPS1_ARB_BASE_ADDR            0x02000000
+#define AIPS1_ARB_END_ADDR             0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR            0x02100000
+#define AIPS2_ARB_END_ADDR             0x021FFFFF
 /* AIPS3 only on i.MX6SX */
-#define AIPS3_ARB_BASE_ADDR             0x02200000
-#define AIPS3_ARB_END_ADDR              0x022FFFFF
+#define AIPS3_ARB_BASE_ADDR            0x02200000
+#define AIPS3_ARB_END_ADDR             0x022FFFFF
 #ifdef CONFIG_SOC_MX6SX
-#define WEIM_ARB_BASE_ADDR              0x50000000
-#define WEIM_ARB_END_ADDR               0x57FFFFFF
-#define QSPI0_AMBA_BASE                0x60000000
-#define QSPI0_AMBA_END                 0x6FFFFFFF
-#define QSPI1_AMBA_BASE                0x70000000
-#define QSPI1_AMBA_END                 0x7FFFFFFF
+#define WEIM_ARB_BASE_ADDR             0x50000000
+#define WEIM_ARB_END_ADDR              0x57FFFFFF
+#define QSPI0_AMBA_BASE                        0x60000000
+#define QSPI0_AMBA_END                 0x6FFFFFFF
+#define QSPI1_AMBA_BASE                        0x70000000
+#define QSPI1_AMBA_END                 0x7FFFFFFF
 #elif defined(CONFIG_SOC_MX6UL)
-#define WEIM_ARB_BASE_ADDR              0x50000000
-#define WEIM_ARB_END_ADDR               0x57FFFFFF
-#define QSPI0_AMBA_BASE                 0x60000000
-#define QSPI0_AMBA_END                  0x6FFFFFFF
+#define WEIM_ARB_BASE_ADDR             0x50000000
+#define WEIM_ARB_END_ADDR              0x57FFFFFF
+#define QSPI0_AMBA_BASE                        0x60000000
+#define QSPI0_AMBA_END                 0x6FFFFFFF
 #else
 #define SATA_ARB_BASE_ADDR             0x02200000
 #define SATA_ARB_END_ADDR              0x02203FFF
 #endif
 
 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define MMDC0_ARB_BASE_ADDR             0x80000000
-#define MMDC0_ARB_END_ADDR              0xFFFFFFFF
-#define MMDC1_ARB_BASE_ADDR             0xC0000000
-#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#define MMDC0_ARB_BASE_ADDR            0x80000000
+#define MMDC0_ARB_END_ADDR             0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR            0xC0000000
+#define MMDC1_ARB_END_ADDR             0xFFFFFFFF
 #else
 #define MMDC0_ARB_BASE_ADDR            0x10000000
 #define MMDC0_ARB_END_ADDR             0x7FFFFFFF
 
 #define AIPS2_ON_BASE_ADDR             (ATZ2_BASE_ADDR + 0x7C000)
 #define AIPS2_OFF_BASE_ADDR            (ATZ2_BASE_ADDR + 0x80000)
-#define CAAM_BASE_ADDR                 (ATZ2_BASE_ADDR)
+#define CAAM_BASE_ADDR                 ATZ2_BASE_ADDR
 #define ARM_BASE_ADDR                  (ATZ2_BASE_ADDR + 0x40000)
 
 #define CONFIG_SYS_FSL_SEC_ADDR                CAAM_BASE_ADDR
 #define MLB_BASE_ADDR                  (AIPS2_OFF_BASE_ADDR + 0xC000)
 #endif
 
-#define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
-#define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
-#define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
-#define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
-#define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
-#define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
-#define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
-#define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
-#define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
+#define USDHC1_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x30000)
 /* i.MX6SL */
-#define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define RNGB_IPS_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
 #ifdef CONFIG_SOC_MX6UL
-#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#define ENET2_BASE_ADDR                        (AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
 /* i.MX6SX */
-#define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define ENET2_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x34000)
 #endif
 /* i.MX6DQ/SDL */
-#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define MMDC_P1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x34000)
 
 #define WEIM_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x3C000)
 #else
 #define IP2APB_PERFMON3_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
-#define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
+#define IP2APB_TZASC1_BASE_ADDR                (AIPS2_OFF_BASE_ADDR + 0x50000)
 #ifdef CONFIG_SOC_MX6UL
-#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI0_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x60000)
 #elif defined(CONFIG_SOC_MX6SX)
-#define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
-#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
-#define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define SAI1_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define AUDMUX_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define SAI2_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define QSPI0_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR                        (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
-#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
-#define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define IP2APB_TZASC2_BASE_ADDR                (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define MIPI_CSI2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x64000)
 #endif
-#define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
-#define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
-#define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
-#define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
-#define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
-#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
-#define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
-#define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
+#define MX6UL_WDOG3_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define UART2_BASE                     (AIPS2_OFF_BASE_ADDR + 0x68000)
+#define UART3_BASE                     (AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE                     (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE                     (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY1_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY2_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
 #ifdef CONFIG_SOC_MX6SX
-#define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
-#define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
-#define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
-#define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
-#define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
-#define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
-#define LCDIF1_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x20000)
-#define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
-#define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
-#define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
-#define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
-#define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
-#define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
-#define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
-#define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
-#define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
-#define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
-#define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
-#define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
-#define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
-#define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
-#define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
-#define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
-#define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#define GIS_BASE_ADDR                  (AIPS3_ARB_BASE_ADDR + 0x04000)
+#define DCIC1_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0x0C000)
+#define DCIC2_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0x10000)
+#define CSI1_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x14000)
+#define PXP_BASE_ADDR                  (AIPS3_ARB_BASE_ADDR + 0x18000)
+#define CSI2_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x1C000)
+#define LCDIF1_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x20000)
+#define LCDIF2_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define VADC_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x28000)
+#define VDEC_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x2C000)
+#define SPBA_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x3C000)
+#define AIPS3_CONFIG_BASE_ADDR         (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define ADC1_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define ADC2_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define ECSPI5_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define HS_BASE_ADDR                   (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define MU_MCU_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x94000)
+#define CANFD_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0x98000)
+#define MU_DSP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x9C000)
+#define UART6_BASE_ADDR                        (AIPS3_ARB_BASE_ADDR + 0xA0000)
+#define PWM5_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xA4000)
+#define PWM6_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xA8000)
+#define PWM7_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xAC000)
+#define PWM8_BASE_ADDR                 (AIPS3_ARB_BASE_ADDR + 0xB0000)
 #endif
-#define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define MX6SX_WDOG3_BASE_ADDR          (AIPS3_ARB_BASE_ADDR + 0x88000)
 
 /* only for i.MX6SX/UL */
 #define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?  \
-                        MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
+                               MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
 
-#define CHIP_REV_1_0                 0x10
-#define CHIP_REV_1_2                 0x12
-#define CHIP_REV_1_5                 0x15
-#define CHIP_REV_2_0                 0x20
+#define CHIP_REV_1_0                   0x10
+#define CHIP_REV_1_2                   0x12
+#define CHIP_REV_1_5                   0x15
+#define CHIP_REV_2_0                   0x20
 #if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define IRAM_SIZE                    0x00040000
+#define IRAM_SIZE                      0x00040000
 #else
 #define IRAM_SIZE                      0x00020000
 #endif
@@ -417,33 +417,33 @@ struct src {
 
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET             29
-#define IOMUXC_GPR3_GPU_DBG_MASK               (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_GPU_DBG_MASK               (3 << IOMUXC_GPR3_GPU_DBG_OFFSET)
 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET    28
-#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK      (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK      (1 << IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET    27
-#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK      (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK      (1 << IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
-#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK   (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK   (1 << IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
-#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK   (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK   (1 << IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET           21
-#define IOMUXC_GPR3_OCRAM_CTL_MASK             (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_MASK             (0xf << IOMUXC_GPR3_OCRAM_CTL_OFFSET)
 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET                17
-#define IOMUXC_GPR3_OCRAM_STATUS_MASK          (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK          (0xf << IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET    16
-#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK      (1 << IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET    15
-#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK      (1 << IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET    14
-#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK      (1 << IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET    13
-#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK      (1 << IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET    12
-#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK      (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK      (1 << IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET    11
-#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK      (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK      (1 << IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
 #define IOMUXC_GPR3_IPU_DIAG_OFFSET            10
-#define IOMUXC_GPR3_IPU_DIAG_MASK              (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_MASK              (1 << IOMUXC_GPR3_IPU_DIAG_OFFSET)
 
 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0   0
 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1   1
@@ -451,16 +451,16 @@ struct src {
 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1   3
 
 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET       8
-#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK         (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK         (3 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
 
 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET       6
-#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK         (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK         (3 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
 
 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET                4
-#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK          (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK          (3 << IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
 
 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET                2
-#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK          (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK          (3 << IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
 
 
 struct iomuxc {
@@ -484,71 +484,71 @@ struct gpc {
 };
 
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET           20
-#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK             (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK             (3 << IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET              16
-#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK                        (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK                        (7 << IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
 
 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET                        15
-#define IOMUXC_GPR2_BGREF_RRMODE_MASK                  (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
-#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES          (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
-#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES          (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK                  (1 << IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES          (1 << IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES          (0 << IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH  0
 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW   1
 
 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET             10
-#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK               (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH                (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW         (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK               (1 << IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH                (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH << IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW         (IOMUXC_GPR2_VSYNC_ACTIVE_LOW << IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 
 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET             9
-#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK               (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH                (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW         (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK               (1 << IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH                (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH << IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW         (IOMUXC_GPR2_VSYNC_ACTIVE_LOW << IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 
 #define IOMUXC_GPR2_BITMAP_SPWG        0
 #define IOMUXC_GPR2_BITMAP_JEIDA       1
 
 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET             8
-#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK               (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA              (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG               (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK               (1 << IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA              (IOMUXC_GPR2_BITMAP_JEIDA << IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG               (IOMUXC_GPR2_BITMAP_SPWG << IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 
 #define IOMUXC_GPR2_DATA_WIDTH_18      0
 #define IOMUXC_GPR2_DATA_WIDTH_24      1
 
 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET              7
-#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK                        (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT               (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT               (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK                        (1 << IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT               (IOMUXC_GPR2_DATA_WIDTH_18 << IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT               (IOMUXC_GPR2_DATA_WIDTH_24 << IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 
 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET             6
-#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK               (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA              (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG               (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK               (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA              (IOMUXC_GPR2_BITMAP_JEIDA << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG               (IOMUXC_GPR2_BITMAP_SPWG << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 
 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET              5
-#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK                        (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT               (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT               (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK                        (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT               (IOMUXC_GPR2_DATA_WIDTH_18 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT               (IOMUXC_GPR2_DATA_WIDTH_24 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 
 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET               4
-#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK                 (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK                 (1 << IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
 
 #define IOMUXC_GPR2_MODE_DISABLED      0
 #define IOMUXC_GPR2_MODE_ENABLED_DI0   1
 #define IOMUXC_GPR2_MODE_ENABLED_DI1   3
 
 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET               2
-#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                 (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED             (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0          (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1          (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                 (3 << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED             (IOMUXC_GPR2_MODE_DISABLED << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0          (IOMUXC_GPR2_MODE_ENABLED_DI0 << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1          (IOMUXC_GPR2_MODE_ENABLED_DI1 << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 
 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET               0
-#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK                 (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED             (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0          (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1          (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK                 (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED             (IOMUXC_GPR2_MODE_DISABLED << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0          (IOMUXC_GPR2_MODE_ENABLED_DI0 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1          (IOMUXC_GPR2_MODE_ENABLED_DI1 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 
 /* ECSPI registers */
 struct cspi_regs {