fpga: Remove all CONFIG_SYS_* fpga related options

All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>

diff --git a/include/altera.h b/include/altera.h
index 7a2bece03215604e65564e2ca3185c9a48824272..6aad5ee868d2796424c417986d9527dc5bf36727 100644 (file)
--- a/include/altera.h
+++ b/include/altera.h
@@ -27,23 +27,6 @@
 #ifndef _ALTERA_H_
 #define _ALTERA_H_
 
-/* Altera Model definitions
- *********************************************************************/
-#define CONFIG_SYS_ACEX1K              CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_CYCLON2             CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_STRATIX_II          CONFIG_SYS_FPGA_DEV( 0x4 )
-
-#define CONFIG_SYS_ALTERA_ACEX1K       (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
-#define CONFIG_SYS_ALTERA_CYCLON2      (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
-#define CONFIG_SYS_ALTERA_STRATIX_II   (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
-/* Add new models here */
-
-/* Altera Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_ALTERA_IF_PS        CONFIG_SYS_FPGA_IF( 0x1 )       /* passive serial */
-#define CONFIG_SYS_ALTERA_IF_FPP       CONFIG_SYS_FPGA_IF( 0x2 )       /* fast passive parallel */
-/* Add new interfaces here */
-
 typedef enum {                         /* typedef Altera_iface */
        min_altera_iface_type,          /* insert all new types after this */
        passive_serial,                 /* serial data and external clock */

diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 1bc2c5a0a4abb08bc6f03e8363ba12893f2103c3..536b7556fabb35eded2f7fbf874b8a0e12b9a538 100644 (file)
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -238,7 +238,7 @@
 
 /* FPGA - Spartan 2 */
 /* experiment
-#define CONFIG_FPGA            CONFIG_SYS_SPARTAN3
+#define CONFIG_FPGA
 #define CONFIG_FPGA_COUNT      1
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC

diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index c296e3cf069ea92551c233ad918a1bca79cda6ec..30fb6c2ffd0aa3aa25f177de7c7087237216f262 100644 (file)
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -606,7 +606,7 @@
  * FPGA
  */
 #define CONFIG_FPGA_COUNT      1
-#define CONFIG_FPGA            CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 

diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index 6850965fb38eb684064f36e04eceb87d127174c8..72714688eba0f00c4b3c5175f27238cd4164935a 100644 (file)
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -310,7 +310,7 @@
 
 #undef FPGA_DEBUG
 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA            CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA     1
 #define CONFIG_FPGA_CYCLON2    1
 #define CONFIG_FPGA_COUNT      1

diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index a99ad3c44b9e5c64534f0720665de5ff119c1164..a9c00acc9ad5d584cffdc920879e379c79690e74 100644 (file)
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -499,7 +499,7 @@
        ""
 
 #define CONFIG_FPGA_COUNT      1
-#define CONFIG_FPGA            CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 

diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
index bf2f44ec6e9915b4709645086e509f7a9278d20c..5d2ff1480542aa2a2abf4d93edf687cb8375c5a5 100644 (file)
--- a/include/configs/MVSMR.h
+++ b/include/configs/MVSMR.h
@@ -280,7 +280,7 @@
 
 #undef FPGA_DEBUG
 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA            CONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX     1
 #define CONFIG_FPGA_SPARTAN2   1
 #define CONFIG_FPGA_COUNT      1

diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index 376a3d031edc78fa7c12ce1ca77c3e1f0c8866f2..f9adc0170003381988e828242d0d420bbee98e3d 100644 (file)
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -273,7 +273,7 @@
 #endif /* (CONFIG_CMD_NET) */
 
 #define CONFIG_FPGA_COUNT      1
-#define CONFIG_FPGA          CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK

diff --git a/include/fpga.h b/include/fpga.h
index ebefba8d05f35bbcee663dfa8b7b6cc688c547ca..38e9018c939b4872b16e69493ffc00f1d1b85da3 100644 (file)
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -31,16 +31,6 @@
 #define CONFIG_MAX_FPGA_DEVICES                5
 #endif
 
-/* CONFIG_FPGA bit assignments */
-#define CONFIG_SYS_FPGA_MAN(x)         (x)
-#define CONFIG_SYS_FPGA_DEV(x)         ((x) << 8 )
-#define CONFIG_SYS_FPGA_IF(x)          ((x) << 16 )
-
-/* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CONFIG_SYS_FPGA_XILINX         CONFIG_SYS_FPGA_MAN( 0x1 )
-#define CONFIG_SYS_FPGA_ALTERA         CONFIG_SYS_FPGA_MAN( 0x2 )
-
-
 /* fpga_xxxx function return value definitions */
 #define FPGA_SUCCESS           0
 #define FPGA_FAIL              -1

diff --git a/include/lattice.h b/include/lattice.h
index 6a2cf93db123a43728c82d67ffe0dc3e7742d617..49871da22d97213b10d31aa0f27af9e421022251 100644 (file)
--- a/include/lattice.h
+++ b/include/lattice.h
@@ -278,9 +278,6 @@ typedef struct {
        char            *desc;  /* description string */
 } Lattice_desc;                        /* end, typedef Altera_desc */
 
-/* Lattice Model Type */
-#define CONFIG_SYS_XP2         CONFIG_SYS_FPGA_DEV(0x1)
-
 /* Board specific implementation specific function types */
 typedef void (*Lattice_jtag_init)(void);
 typedef void (*Lattice_jtag_set_tdi)(int v);

diff --git a/include/xilinx.h b/include/xilinx.h
index bcfe76d81ef07bf0050ed5b699e4d244dd3f5d30..9a64771c6051ca59ed377e685693cc86c7357c8b 100644 (file)
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -27,30 +27,6 @@
 #ifndef _XILINX_H_
 #define _XILINX_H_
 
-/* Xilinx Model definitions
- *********************************************************************/
-#define CONFIG_SYS_SPARTAN2                    CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_VIRTEX_E                    CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_VIRTEX2                     CONFIG_SYS_FPGA_DEV( 0x4 )
-#define CONFIG_SYS_SPARTAN3                    CONFIG_SYS_FPGA_DEV( 0x8 )
-#define CONFIG_SYS_ZYNQ                                CONFIG_SYS_FPGA_DEV(0x10)
-#define CONFIG_SYS_XILINX_SPARTAN2     (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
-#define CONFIG_SYS_XILINX_VIRTEX_E     (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
-#define CONFIG_SYS_XILINX_VIRTEX2      (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
-#define CONFIG_SYS_XILINX_SPARTAN3     (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
-#define CONFIG_SYS_XILINX_ZYNQ (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_ZYNQ)
-/* XXX - Add new models here */
-
-
-/* Xilinx Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_XILINX_IF_SS        CONFIG_SYS_FPGA_IF( 0x1 )       /* slave serial         */
-#define CONFIG_SYS_XILINX_IF_MS        CONFIG_SYS_FPGA_IF( 0x2 )       /* master serial        */
-#define CONFIG_SYS_XILINX_IF_SP        CONFIG_SYS_FPGA_IF( 0x4 )       /* slave parallel       */
-#define CONFIG_SYS_XILINX_IF_JTAG      CONFIG_SYS_FPGA_IF( 0x8 )       /* jtag                 */
-#define CONFIG_SYS_XILINX_IF_MSM       CONFIG_SYS_FPGA_IF( 0x10 )      /* master selectmap     */
-#define CONFIG_SYS_XILINX_IF_SSM       CONFIG_SYS_FPGA_IF( 0x20 )      /* slave selectmap      */
-
 /* Xilinx types
  *********************************************************************/
 typedef enum {                 /* typedef Xilinx_iface */