u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
$(call if_changed,pad_cat)
+MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
+u-boot-nand.gph: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+ @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
obj-y += init.o
obj-y += psc.o
obj-y += clock.o
+obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
-obj-y += keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
obj-y += msmc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += ddr3.o
+obj-y += keystone.o
--- /dev/null
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Keystone2: get clk rate for K2HK
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+ [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3A_PLL:
+ ret = external_clk[ddr3a_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ case DDR3B_PLL:
+ ret = external_clk[ddr3b_clk];
+ reg = KS2_DDR3BPLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
+ case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
+ case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+
+ return 0;
+}
*/
#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
}
}
-struct pll_regs {
- u32 reg0, reg1;
-};
-
-static const struct pll_regs pll_regs[] = {
- [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
- [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
- [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
- [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
- [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
-};
-
-/* Fout = Fref * NF(mult) / NR(prediv) / OD */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(K2HK_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = K2HK_PASSPLLCTL0;
- break;
- case TETRIS_PLL:
- ret = external_clk[tetris_clk];
- reg = K2HK_ARMPLLCTL0;
- break;
- case DDR3A_PLL:
- ret = external_clk[ddr3a_clk];
- reg = K2HK_DDR3APLLCTL0;
- break;
- case DDR3B_PLL:
- ret = external_clk[ddr3b_clk];
- reg = K2HK_DDR3BPLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
-
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
- case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
- case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
- return 0;
-}
-
void init_pll(const struct pll_init_data *data)
{
u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
tmp = pllctl_reg_read(data->pll, secctl);
if (tmp & (PLLCTL_BYPASS)) {
- setbits_le32(pll_regs[data->pll].reg1,
+ setbits_le32(keystone_pll_regs[data->pll].reg1,
BIT(MAIN_ENSAT_OFFSET));
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
- clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
- (pllm << 6));
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ PLLM_MULT_HI_SMASK, (pllm << 6));
/* Set the BWADJ (12 bit field) */
tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
- clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ PLL_BWADJ_LO_SMASK,
(tmp_ctl << PLL_BWADJ_LO_SHIFT));
- clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+ PLL_BWADJ_HI_MASK,
(tmp_ctl >> 8));
/*
* Set the pll divider (6 bit field) *
* PLLD[5:0] is located in MAINPLLCTL0
*/
- clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ PLL_DIV_MASK, plld);
/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+#ifndef CONFIG_SOC_K2E
} else if (data->pll == TETRIS_PLL) {
bwadj = pllm >> 1;
/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
- setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
* only applicable for Kepler
*/
- clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
- setbits_le32(pll_regs[data->pll].reg1 ,
+ setbits_le32(keystone_pll_regs[data->pll].reg1 ,
PLL_PLLRST | PLLCTL_ENSAT);
/*
(pllm << 6) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
- __raw_writel(tmp, pll_regs[data->pll].reg0);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
- tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
- __raw_writel(tmp, pll_regs[data->pll].reg1);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/*
* 5 Wait for at least 5 us based on the reference
* clock (PLL reset time)
sdelay(21000); /* Wait for a minimum of 7 us*/
/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
- clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+ clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
/*
* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
* (PLL lock time)
*/
sdelay(105000);
/* 8 disable bypass */
- clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
* only applicable for Kepler
*/
- setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
+#endif
} else {
- setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+ setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
/*
* process keeps state of Bypass bit while programming
* all other DDR PLL settings
*/
- tmp = __raw_readl(pll_regs[data->pll].reg0);
+ tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
/*
(pllm << PLL_MULT_SHIFT) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT);
- __raw_writel(tmp, pll_regs[data->pll].reg0);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
- tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
if (data->pll == PASS_PLL)
tmp |= PLLCTL_PAPLL;
- __raw_writel(tmp, pll_regs[data->pll].reg1);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
tmp = PLL_PLLRST;
/* Set RESET bit = 1 */
- setbits_le32(pll_regs[data->pll].reg1, tmp);
+ setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
/* Wait for a minimum of 7 us*/
sdelay(21000);
/* Clear RESET bit */
- clrbits_le32(pll_regs[data->pll].reg1, tmp);
+ clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
sdelay(105000);
/* clear BYPASS (Enable PLL Mode) */
- clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
sdelay(21000); /* Wait for a minimum of 7 us*/
}
#include <asm/arch/psc_defs.h>
struct pll_init_data cmd_pll_data = {
- .pll = MAIN_PLL,
- .pll_m = 16,
- .pll_d = 1,
- .pll_od = 2,
+ .pll = MAIN_PLL,
+ .pll_m = 16,
+ .pll_d = 1,
+ .pll_od = 2,
};
int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (strncmp(argv[1], "pa", 2) == 0)
cmd_pll_data.pll = PASS_PLL;
+#ifndef CONFIG_SOC_K2E
else if (strncmp(argv[1], "arm", 3) == 0)
cmd_pll_data.pll = TETRIS_PLL;
+#endif
+#ifdef CONFIG_SOC_K2HK
else if (strncmp(argv[1], "ddr3a", 5) == 0)
cmd_pll_data.pll = DDR3A_PLL;
else if (strncmp(argv[1], "ddr3b", 5) == 0)
cmd_pll_data.pll = DDR3B_PLL;
+#else
+ else if (strncmp(argv[1], "ddr3", 4) == 0)
+ cmd_pll_data.pll = DDR3_PLL;
+#endif
else
goto pll_cmd_usage;
return cmd_usage(cmdtp);
}
+#ifdef CONFIG_SOC_K2HK
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
);
+#endif
+#ifdef CONFIG_SOC_K2E
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ "set pll multiplier and pre divider",
+ "<pa|ddr3> <mult> <div> <OD>\n"
+);
+#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
- "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+#ifdef CONFIG_SOC_K2HK
+ "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
+#endif
+#ifdef CONFIG_SOC_K2E
+ "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
+#endif
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/arch/hardware.h>
#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/ddr3.h>
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
;
}
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
{
__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
+
+void ddr3_reset_ddrphy(void)
+{
+ u32 tmp;
+
+ /* Assert DDR3A PHY reset */
+ tmp = readl(KS2_DDR3APLLCTL1);
+ tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+ writel(tmp, KS2_DDR3APLLCTL1);
+
+ /* wait 10us to catch the reset */
+ udelay(10);
+
+ /* Release DDR3A PHY reset */
+ tmp = readl(KS2_DDR3APLLCTL1);
+ tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
+ __raw_writel(tmp, KS2_DDR3APLLCTL1);
+}
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
+#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
void chip_configuration_unlock(void)
{
- __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
- __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+ __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+ __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
int arch_cpu_init(void)
chip_configuration_unlock();
icache_enable();
-#ifdef CONFIG_SOC_K2HK
- share_all_segments(8);
- share_all_segments(9);
- share_all_segments(10); /* QM PDSP */
- share_all_segments(11); /* PCIE */
+ msmc_share_all_segments(8); /* TETRIS */
+ msmc_share_all_segments(9); /* NETCP */
+ msmc_share_all_segments(10); /* QM PDSP */
+ msmc_share_all_segments(11); /* PCIE 0 */
+#ifdef CONFIG_SOC_K2E
+ msmc_share_all_segments(13); /* PCIE 1 */
#endif
/*
--- /dev/null
+/*
+ * Keystone EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mon.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/hardware.h>
+
+/**
+ * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
+ * @ptr - array of data
+ * @length - lenght of data array
+ */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+ u32 i;
+
+ if (!(readl(KS2_DEVSTAT) & 0x1))
+ for (i = 0; i < length; i++, ptr++)
+ *ptr = cpu_to_be32(*ptr);
+
+ return 0;
+}
+
+static int turn_off_myself(void)
+{
+ printf("Turning off ourselves\r\n");
+ mon_power_off(0);
+
+ psc_disable_module(KS2_LPSC_TETRIS);
+ psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+ asm volatile ("isb\n"
+ "dsb\n"
+ "wfi\n");
+
+ printf("What! Should not see that\n");
+ return 0;
+}
+
+static void turn_off_all_dsps(int num_dsps)
+{
+ int i;
+
+ for (i = 0; i < num_dsps; i++) {
+ if (psc_disable_module(i + KS2_LPSC_GEM_0))
+ printf("Cannot disable module for #%d DSP", i);
+
+ if (psc_disable_domain(i + 8))
+ printf("Cannot disable domain for #%d DSP", i);
+ }
+}
+
+int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return turn_off_myself();
+}
+
+U_BOOT_CMD(
+ killme, 1, 0, do_killme_cmd,
+ "turn off main ARM core",
+ "turn off main ARM core. Should not live after that :(\n"
+);
+
+int misc_init_r(void)
+{
+ char *env;
+ long ks2_debug = 0;
+
+ env = getenv("ks2_debug");
+
+ if (env)
+ ks2_debug = simple_strtol(env, NULL, 0);
+
+ if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
+ turn_off_all_dsps(KS2_NUM_DSPS);
+
+ return 0;
+}
*/
#include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/msmc.h>
struct mpax {
u32 mpaxl;
};
-void share_all_segments(int priv_id)
+void msmc_share_all_segments(int priv_id)
{
- struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
int j;
for (j = 0; j < 8; j++) {
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASE K2HK_PSC_BASE
-#endif
-
int psc_delay(void)
{
udelay(10);
retry = 0;
do {
- ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+ ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat & (1 << domain_num);
} while ((ptstat != 0) && ((retry += psc_delay()) <
PSC_PTSTAT_TIMEOUT_LIMIT));
u32 domain_num;
/* Get the power domain associated with the module number */
- domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
- v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
- pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
}
/* Set the next state for the module to enabled/disabled */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
/* Trigger the enable */
- ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
/* Wait on the complete */
return psc_wait(domain_num);
u32 mdctl;
/* Set the bit to apply reset */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
u32 mdctl;
/* Set the bit to apply reset */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
u32 mdctl;
/* Set the reset isolation bit */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
- v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
return 0;
u32 pdctl;
u32 ptcmd;
- pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+ pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
- ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
return psc_wait(domain_num);
}
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_K2HK_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_500,
};
+#endif
+
+#ifdef CONFIG_K2E_EVM
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_800,
+};
+#endif
void spl_init_keystone_plls(void)
{
hw_data_init();
#ifdef CONFIG_SPL_BUILD
- if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+ if (warm_reset() &&
+ (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
force_emif_self_refresh();
#endif
watchdog_init();
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
- u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
-#elif defined(CONFIG_NAND)
+ u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
+ /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+ /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
+ /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
+ /* min 16MB */ GPMC_SIZE_16M)));
+#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG6,
0
};
- u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
+ u32 size = GPMC_SIZE_16M;
+
#elif defined(CONFIG_CMD_ONENAND)
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
ONENAND_GPMC_CONFIG6,
0
};
- u32 base = PISMO1_ONEN_BASE;
- u32 size = PISMO1_ONEN_SIZE;
+ u32 size = GPMC_SIZE_128M;
+ u32 base = CONFIG_SYS_ONENAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Initial Code from:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
- M_NAND_GPMC_CONFIG1,
- M_NAND_GPMC_CONFIG2,
- M_NAND_GPMC_CONFIG3,
- M_NAND_GPMC_CONFIG4,
- M_NAND_GPMC_CONFIG5,
- M_NAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_CMD_ONENAND)
-static const u32 gpmc_onenand[GPMC_MAX_REG] = {
- ONENAND_GPMC_CONFIG1,
- ONENAND_GPMC_CONFIG2,
- ONENAND_GPMC_CONFIG3,
- ONENAND_GPMC_CONFIG4,
- ONENAND_GPMC_CONFIG5,
- ONENAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_ONENAND */
-
-/********************************************************
- * mem_ok() - test used to see if timings are correct
- * for a part. Helps in guessing which part
- * we are currently using.
- *******************************************************/
-u32 mem_ok(u32 cs)
-{
- u32 val1, val2, addr;
- u32 pattern = 0x12345678;
-
- addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
- writel(0x0, addr + 0x400); /* clear pos A */
- writel(pattern, addr); /* pattern to pos B */
- writel(0x0, addr + 4); /* remove pattern off the bus */
- val1 = readl(addr + 0x400); /* get pos A value */
- val2 = readl(addr); /* get val2 */
- writel(0x0, addr + 0x400); /* clear pos A */
-
- if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
- return 0;
- else
- return 1;
-}
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
- u32 size)
-{
- writel(0, &cs->config7);
- sdelay(1000);
- /* Delay for settling */
- writel(gpmc_config[0], &cs->config1);
- writel(gpmc_config[1], &cs->config2);
- writel(gpmc_config[2], &cs->config3);
- writel(gpmc_config[3], &cs->config4);
- writel(gpmc_config[4], &cs->config5);
- writel(gpmc_config[5], &cs->config6);
-
- /*
- * Enable the config. size is the CS size and goes in
- * bits 11:8. We set bit 6 to enable this CS and the base
- * address goes into bits 5:0.
- */
- writel((size << 8) | (GPMC_CS_ENABLE << 6) |
- ((base >> 24) & GPMC_BASEADDR_MASK),
- &cs->config7);
- sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
- /* putting a blanket check on GPMC based on ZeBu for now */
- gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
- const u32 *gpmc_config = NULL;
- u32 base = 0;
- u32 size = 0;
-#endif
- u32 config = 0;
-
- /* global settings */
- writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
- writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
- config = readl(&gpmc_cfg->config);
- config &= (~0xf00);
- writel(config, &gpmc_cfg->config);
-
- /*
- * Disable the GPMC0 config set by ROM code
- * It conflicts with our MPDB (both at 0x08000000)
- */
- writel(0, &gpmc_cfg->cs[0].config7);
- sdelay(1000);
-
-#if defined(CONFIG_CMD_NAND) /* CS 0 */
- gpmc_config = gpmc_m_nand;
-
- base = PISMO1_NAND_BASE;
- size = PISMO1_NAND_SIZE;
- enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
- gpmc_config = gpmc_onenand;
- base = PISMO1_ONEN_BASE;
- size = PISMO1_ONEN_SIZE;
- enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-}
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_RATIO 0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
-#define MT47H128M16RT25E_WR_DQS 0x00
-#define MT47H128M16RT25E_PHY_WRLVL 0x00
-#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
-#define PISMO1_NOR 1
-#define PISMO1_NAND 2
-#define PISMO2_CS0 3
-#define PISMO2_CS1 4
-#define PISMO1_ONENAND 5
#define DBG_MPDB 6
-#define PISMO2_NAND_CS0 7
-#define PISMO2_NAND_CS1 8
#endif /* endif _MEM_H_ */
--- /dev/null
+/*
+ * K2E: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2E_H
+#define __ASM_ARCH_CLOCK_K2E_H
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ ddr3_clk,
+ mcm_clk,
+ pcie_clk,
+ sgmii_clk,
+ xgmii_clk,
+ usb_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+ core_pll_clk,
+ pass_pll_clk,
+ ddr3_pll_clk,
+ sys_clk0_clk,
+ sys_clk0_1_clk,
+ sys_clk0_2_clk,
+ sys_clk0_3_clk,
+ sys_clk0_4_clk,
+ sys_clk0_6_clk,
+ sys_clk0_8_clk,
+ sys_clk0_12_clk,
+ sys_clk0_24_clk,
+ sys_clk1_clk,
+ sys_clk1_3_clk,
+ sys_clk1_4_clk,
+ sys_clk1_6_clk,
+ sys_clk1_12_clk,
+ sys_clk2_clk,
+ sys_clk3_clk
+};
+
+#define KS2_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ DDR3_PLL,
+};
+
+#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
+#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
+#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
+#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
+#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+
+#endif
#ifndef __ASM_ARCH_CLOCK_K2HK_H
#define __ASM_ARCH_CLOCK_K2HK_H
-#include <asm/arch/hardware.h>
-
-#ifndef __ASSEMBLY__
-
enum ext_clk_e {
sys_clk,
alt_core_clk,
sys_clk3_clk
};
-#define K2HK_CLK1_6 sys_clk0_6_clk
+#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
DDR3A_PLL,
DDR3B_PLL,
};
-#define MAIN_PLL CORE_PLL
-
-/* PLL configuration data */
-struct pll_init_data {
- int pll;
- int pll_m; /* PLL Multiplier */
- int pll_d; /* PLL divider */
- int pll_od; /* PLL output divider */
-};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
-void init_plls(int num_pll, struct pll_init_data *config);
-void init_pll(const struct pll_init_data *data);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-#endif
-
#endif
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#ifndef __ASSEMBLY__
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/clock-k2hk.h>
#endif
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/clock-k2e.h>
+#endif
+
+#define MAIN_PLL CORE_PLL
+
+#include <asm/types.h>
+
+struct keystone_pll_regs {
+ u32 reg0;
+ u32 reg1;
+};
+
+/* PLL configuration data */
+struct pll_init_data {
+ int pll;
+ int pll_m; /* PLL Multiplier */
+ int pll_d; /* PLL divider */
+ int pll_od; /* PLL output divider */
+};
+
+extern const struct keystone_pll_regs keystone_pll_regs[];
+
+void init_plls(int num_pll, struct pll_init_data *config);
+void init_pll(const struct pll_init_data *data);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+#endif
#endif
};
static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x100)
+ (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
};
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
--- /dev/null
+/*
+ * DDR3
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DDR3_H_
+#define _DDR3_H_
+
+#include <asm/arch/hardware.h>
+
+struct ddr3_phy_config {
+ unsigned int pllcr;
+ unsigned int pgcr1_mask;
+ unsigned int pgcr1_val;
+ unsigned int ptr0;
+ unsigned int ptr1;
+ unsigned int ptr2;
+ unsigned int ptr3;
+ unsigned int ptr4;
+ unsigned int dcr_mask;
+ unsigned int dcr_val;
+ unsigned int dtpr0;
+ unsigned int dtpr1;
+ unsigned int dtpr2;
+ unsigned int mr0;
+ unsigned int mr1;
+ unsigned int mr2;
+ unsigned int dtcr;
+ unsigned int pgcr2;
+ unsigned int zq0cr1;
+ unsigned int zq1cr1;
+ unsigned int zq2cr1;
+ unsigned int pir_v1;
+ unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+ unsigned int sdcfg;
+ unsigned int sdtim1;
+ unsigned int sdtim2;
+ unsigned int sdtim3;
+ unsigned int sdtim4;
+ unsigned int zqcfg;
+ unsigned int sdrfc;
+};
+
+void ddr3_init(void);
+void ddr3_reset_ddrphy(void);
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+
+#endif
--- /dev/null
+/*
+ * K2E: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2E_H
+#define __ASM_ARCH_HARDWARE_K2E_H
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x24000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD_RST 0
+#define KS2_LPSC_USB_1 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE 10
+#define KS2_LPSC_VUSR0 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_PCIE_1 27
+#define KS2_LPSC_XGE 50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 1
+
+#endif
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define K2HK_PLL_CNTRL_BASE 0x02310000
-#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
-#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
-#define KS2_RSTCTRL_KEY 0x5a69
-#define KS2_RSTCTRL_MASK 0xffff0000
-#define KS2_RSTCTRL_SWRST 0xfffe0000
-
-#define K2HK_PSC_BASE 0x02350000
-#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
-#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
-#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
-
-#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
-#define ARM_PLL_EN BIT(13)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-#define K2HK_SPI0_BASE 0x21000400
-#define K2HK_SPI1_BASE 0x21000600
-#define K2HK_SPI2_BASE 0x21000800
-#define K2HK_SPI_BASE K2HK_SPI0_BASE
-
-/* Chip configuration unlock codes and registers */
-#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
-#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
-#define KEYSTONE_KICK0_MAGIC 0x83e70b13
-#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
+#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
-#define KS2_PASS_BASE 0x02000000
+#define KS2_PASS_BASE 0x02000000
/* PLL control registers */
-#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
-#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
-#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
-#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
-#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
-#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
-#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
-#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
/* Power and Sleep Controller (PSC) Domains */
-#define K2HK_LPSC_MOD 0
-#define K2HK_LPSC_DUMMY1 1
-#define K2HK_LPSC_USB 2
-#define K2HK_LPSC_EMIF25_SPI 3
-#define K2HK_LPSC_TSIP 4
-#define K2HK_LPSC_DEBUGSS_TRC 5
-#define K2HK_LPSC_TETB_TRC 6
-#define K2HK_LPSC_PKTPROC 7
-#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
-#define K2HK_LPSC_SGMII 8
-#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
-#define K2HK_LPSC_CRYPTO 9
-#define K2HK_LPSC_PCIE 10
-#define K2HK_LPSC_SRIO 11
-#define K2HK_LPSC_VUSR0 12
-#define K2HK_LPSC_CHIP_SRSS 13
-#define K2HK_LPSC_MSMC 14
-#define K2HK_LPSC_GEM_0 15
-#define K2HK_LPSC_GEM_1 16
-#define K2HK_LPSC_GEM_2 17
-#define K2HK_LPSC_GEM_3 18
-#define K2HK_LPSC_GEM_4 19
-#define K2HK_LPSC_GEM_5 20
-#define K2HK_LPSC_GEM_6 21
-#define K2HK_LPSC_GEM_7 22
-#define K2HK_LPSC_EMIF4F_DDR3A 23
-#define K2HK_LPSC_EMIF4F_DDR3B 24
-#define K2HK_LPSC_TAC 25
-#define K2HK_LPSC_RAC 26
-#define K2HK_LPSC_RAC_1 27
-#define K2HK_LPSC_FFTC_A 28
-#define K2HK_LPSC_FFTC_B 29
-#define K2HK_LPSC_FFTC_C 30
-#define K2HK_LPSC_FFTC_D 31
-#define K2HK_LPSC_FFTC_E 32
-#define K2HK_LPSC_FFTC_F 33
-#define K2HK_LPSC_AI2 34
-#define K2HK_LPSC_TCP3D_0 35
-#define K2HK_LPSC_TCP3D_1 36
-#define K2HK_LPSC_TCP3D_2 37
-#define K2HK_LPSC_TCP3D_3 38
-#define K2HK_LPSC_VCP2X4_A 39
-#define K2HK_LPSC_CP2X4_B 40
-#define K2HK_LPSC_VCP2X4_C 41
-#define K2HK_LPSC_VCP2X4_D 42
-#define K2HK_LPSC_VCP2X4_E 43
-#define K2HK_LPSC_VCP2X4_F 44
-#define K2HK_LPSC_VCP2X4_G 45
-#define K2HK_LPSC_VCP2X4_H 46
-#define K2HK_LPSC_BCP 47
-#define K2HK_LPSC_DXB 48
-#define K2HK_LPSC_VUSR1 49
-#define K2HK_LPSC_XGE 50
-#define K2HK_LPSC_ARM_SREFLEX 51
-#define K2HK_LPSC_TETRIS 52
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DUMMY1 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE 10
+#define KS2_LPSC_SRIO 11
+#define KS2_LPSC_VUSR0 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_GEM_4 19
+#define KS2_LPSC_GEM_5 20
+#define KS2_LPSC_GEM_6 21
+#define KS2_LPSC_GEM_7 22
+#define KS2_LPSC_EMIF4F_DDR3A 23
+#define KS2_LPSC_EMIF4F_DDR3B 24
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_RAC_1 27
+#define KS2_LPSC_FFTC_A 28
+#define KS2_LPSC_FFTC_B 29
+#define KS2_LPSC_FFTC_C 30
+#define KS2_LPSC_FFTC_D 31
+#define KS2_LPSC_FFTC_E 32
+#define KS2_LPSC_FFTC_F 33
+#define KS2_LPSC_AI2 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 36
+#define KS2_LPSC_TCP3D_2 37
+#define KS2_LPSC_TCP3D_3 38
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_CP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_VCP2X4_E 43
+#define KS2_LPSC_VCP2X4_F 44
+#define KS2_LPSC_VCP2X4_G 45
+#define KS2_LPSC_VCP2X4_H 46
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DXB 48
+#define KS2_LPSC_VUSR1 49
+#define KS2_LPSC_XGE 50
+#define KS2_LPSC_ARM_SREFLEX 51
-/* DDR3A definitions */
-#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
-#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
-#define K2HK_DDR3A_DDRPHYC 0x02329000
/* DDR3B definitions */
-#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
-#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
-#define K2HK_DDR3B_DDRPHYC 0x02328000
-
-/* Queue manager */
-#define DEVICE_QM_MANAGER_BASE 0x02a02000
-#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
-#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
-#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
-#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
-#define DEVICE_QM_NUM_LINKRAMS 2
-#define DEVICE_QM_NUM_MEMREGIONS 20
-
-#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
-#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
-#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
-#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
-
-#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
-#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
-#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
+#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
+#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
+#define KS2_DDR3B_DDRPHYC 0x02328000
-/* MSMC control */
-#define K2HK_MSMC_CTRL_BASE 0x0bc00000
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 8
#endif /* __ASM_ARCH_HARDWARE_H */
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
-struct ddr3_phy_config {
- unsigned int pllcr;
- unsigned int pgcr1_mask;
- unsigned int pgcr1_val;
- unsigned int ptr0;
- unsigned int ptr1;
- unsigned int ptr2;
- unsigned int ptr3;
- unsigned int ptr4;
- unsigned int dcr_mask;
- unsigned int dcr_val;
- unsigned int dtpr0;
- unsigned int dtpr1;
- unsigned int dtpr2;
- unsigned int mr0;
- unsigned int mr1;
- unsigned int mr2;
- unsigned int dtcr;
- unsigned int pgcr2;
- unsigned int zq0cr1;
- unsigned int zq1cr1;
- unsigned int zq2cr1;
- unsigned int pir_v1;
- unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
- unsigned int sdcfg;
- unsigned int sdtim1;
- unsigned int sdtim2;
- unsigned int sdtim3;
- unsigned int sdtim4;
- unsigned int zqcfg;
- unsigned int sdrfc;
-};
-
#endif
#define BIT(x) (1 << (x))
#define NOSRA_MASK 0x08000000
#define ECC_MASK 0x00000001
+/* DDR3 definitions */
+#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
+#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
+#define KS2_DDR3A_DDRPHYC 0x02329000
+
#define KS2_DDR3_MIDR_OFFSET 0x00
#define KS2_DDR3_STATUS_OFFSET 0x04
#define KS2_DDR3_SDCFG_OFFSET 0x08
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
+#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
+
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
+/* Boot Config */
+#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
+#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
+/* PSC */
+#define KS2_PSC_BASE 0x02350000
+#define KS2_LPSC_GEM_0 15
+#define KS2_LPSC_TETRIS 52
+#define KS2_TETRIS_PWR_DOMAIN 31
+
+/* Chip configuration unlock codes and registers */
+#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KS2_KICK0_MAGIC 0x83e70b13
+#define KS2_KICK1_MAGIC 0x95a4f1e0
+
+/* PLL control registers */
+#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+#define KS2_PLL_CNTRL_BASE 0x02310000
+#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
+#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
+#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY 0x5a69
+#define KS2_RSTCTRL_MASK 0xffff0000
+#define KS2_RSTCTRL_SWRST 0xfffe0000
+
+/* SPI */
+#define KS2_SPI0_BASE 0x21000400
+#define KS2_SPI1_BASE 0x21000600
+#define KS2_SPI2_BASE 0x21000800
+#define KS2_SPI_BASE KS2_SPI0_BASE
+
/* AEMIF */
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
+/* Flag from ks2_debug options to check if DSPs need to stay ON */
+#define DBG_LEAVE_DSPS_ON 0x1
+
+/* Queue manager */
+#define KS2_QM_MANAGER_BASE 0x02a02000
+#define KS2_QM_DESC_SETUP_BASE 0x02a03000
+#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
+#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
+#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
+
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE 0x0bc00000
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/hardware-k2e.h>
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
- unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int part_no = (jtag_id >> 12) & 0xffff;
return (part_no == 0xb981) ? 1 : 0;
}
+static inline int cpu_is_k2e(void)
+{
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb9a6) ? 1 : 0;
+}
+
static inline int cpu_revision(void)
{
- unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int rev = (jtag_id >> 28) & 0xf;
return rev;
}
-void share_all_segments(int priv_id);
int cpu_to_bus(u32 *ptr, u32 length);
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-void init_ddr3(void);
void sdelay(unsigned long);
#endif
--- /dev/null
+/*
+ * K2HK: secure kernel command header file
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MON_H_
+#define _MON_H_
+
+int mon_power_off(int core_id);
+
+#endif
--- /dev/null
+/*
+ * MSMC controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MSMC_H_
+#define _MSMC_H_
+
+#include <asm/arch/hardware.h>
+
+void msmc_share_all_segments(int priv_id);
+
+#endif
#define DEBUG_BASE 0x08000000 /* debug board */
#define NAND_BASE 0x30000000 /* NAND addr */
/* (actual size small port) */
-#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
#define ONENAND_MAP 0x20000000 /* OneNand addr */
/* (actual size small port) */
/* SMS */
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
-#define PISMO1_NOR 1
-#define PISMO1_NAND 2
-#define PISMO2_CS0 3
-#define PISMO2_CS1 4
-#define PISMO1_ONENAND 5
#define DBG_MPDB 6
-#define PISMO2_NAND_CS0 7
-#define PISMO2_NAND_CS1 8
-
-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE FLASH_BASE
-#define PISMO1_NAND_BASE NAND_BASE
-#define PISMO2_CS0_BASE PISMO2_MAP1
-#define PISMO1_ONEN_BASE ONENAND_MAP
#define DBG_MPDB_BASE DEBUG_BASE
#ifndef __ASSEMBLY__
return *omap_si_rev;
}
+#define OMAP44xx 0x44000000
+
+static inline u8 is_omap44xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFF000000) == OMAP44xx;
+};
+
#define OMAP54xx 0x54000000
static inline u8 is_omap54xx(void)
#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "board.h"
+#include <power/pmic.h>
#include <power/tps65218.h>
#include <miiphy.h>
#include <cpsw.h>
}
#endif
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ power_tps65218_init(I2C_PMIC);
+ p = pmic_get("TPS65218_PMIC");
+ if (p && !pmic_probe(p))
+ puts("PMIC: TPS65218\n");
+
+ return 0;
+}
+
int board_init(void)
{
struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+extern u32 *const omap_si_rev;
+
static void cpsw_control(int enabled)
{
/* VTP can be added here */
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
- .slaves = 1,
+ .slaves = 2,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
+ if (*omap_si_rev == DRA722_ES1_0)
+ cpsw_data.active_slave = 1;
+
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+ {VIN2A_D12, (M3) },
+ {VIN2A_D13, (M3) },
+ {VIN2A_D14, (M3) },
+ {VIN2A_D15, (M3) },
+ {VIN2A_D16, (M3) },
+ {VIN2A_D17, (M3) },
+ {VIN2A_D18, (IEN | M3)},
+ {VIN2A_D19, (IEN | M3)},
+ {VIN2A_D20, (IEN | M3)},
+ {VIN2A_D21, (IEN | M3)},
+ {VIN2A_D22, (IEN | M3)},
+ {VIN2A_D23, (IEN | M3)},
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
+++ /dev/null
-#
-# K2HK-EVM: board Makefile
-# (C) Copyright 2012-2014
-# Texas Instruments Incorporated, <www.ti.com>
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += board.o
-obj-y += ddr3.o
+++ /dev/null
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1600_64A = {
- .pllcr = 0x0001C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0D861A80ul,
- .ptr4 = 0x0C827100ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0xA19DBB66ul,
- .dtpr1 = 0x12868300ul,
- .dtpr2 = 0x50035200ul,
- .mr0 = 0x00001C70ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
- .dtcr = 0x730035C7ul,
- .pgcr2 = 0x00F07A12ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_64 = {
- .sdcfg = 0x6200CE6aul,
- .sdtim1 = 0x16709C55ul,
- .sdtim2 = 0x00001D4Aul,
- .sdtim3 = 0x435DFF54ul,
- .sdtim4 = 0x553F0CFFul,
- .zqcfg = 0xF0073200ul,
- .sdrfc = 0x00001869ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1600_32 = {
- .pllcr = 0x0001C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0D861A80ul,
- .ptr4 = 0x0C827100ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0xA19DBB66ul,
- .dtpr1 = 0x12868300ul,
- .dtpr2 = 0x50035200ul,
- .mr0 = 0x00001C70ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
- .dtcr = 0x730035C7ul,
- .pgcr2 = 0x00F07A12ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_32 = {
- .sdcfg = 0x6200DE6aul,
- .sdtim1 = 0x16709C55ul,
- .sdtim2 = 0x00001D4Aul,
- .sdtim3 = 0x435DFF54ul,
- .sdtim4 = 0x553F0CFFul,
- .zqcfg = 0x70073200ul,
- .sdrfc = 0x00001869ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64A = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
- NOSRA_MASK | UDIMM_MASK),
- .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_64 = {
- .sdcfg = 0x62008C62ul,
- .sdtim1 = 0x125C8044ul,
- .sdtim2 = 0x00001D29ul,
- .sdtim3 = 0x32CDFF43ul,
- .sdtim4 = 0x543F0ADFul,
- .zqcfg = 0xF0073200ul,
- .sdrfc = 0x00001457ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1333_32 = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
- NOSRA_MASK | UDIMM_MASK),
- .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_32 = {
- .sdcfg = 0x62009C62ul,
- .sdtim1 = 0x125C8044ul,
- .sdtim2 = 0x00001D29ul,
- .sdtim3 = 0x32CDFF43ul,
- .sdtim4 = 0x543F0ADFul,
- .zqcfg = 0xf0073200ul,
- .sdrfc = 0x00001457ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64 = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-/******************************************************/
-int get_dimm_params(char *dimm_name)
-{
- u8 spd_params[256];
- int ret;
- int old_bus;
-
- i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
- old_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
- i2c_set_bus_num(old_bus);
-
- dimm_name[0] = '\0';
-
- if (ret) {
- puts("Cannot read DIMM params\n");
- return 1;
- }
-
- /*
- * We need to convert spd data to dimm parameters
- * and to DDR3 EMIF and PHY regirsters values.
- * For now we just return DIMM type string value.
- * Caller may use this value to choose appropriate
- * a pre-set DDR3 configuration
- */
-
- strncpy(dimm_name, (char *)&spd_params[0x80], 18);
- dimm_name[18] = '\0';
-
- return 0;
-}
-
-struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
-struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
-struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
-struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
-
-void init_ddr3(void)
-{
- char dimm_name[32];
-
- get_dimm_params(dimm_name);
-
- printf("Detected SO-DIMM [%s]\n", dimm_name);
-
- if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
- init_pll(&ddr3a_400);
- if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
- printf("DRAM: Capacity 8 GiB (includes reported below)\n");
- } else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
- printf("DRAM: Capacity 4 GiB (includes reported below)\n");
- }
- } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
- init_pll(&ddr3a_333);
- if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
- } else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
- }
- } else {
- printf("Unknown SO-DIMM. Cannot configure DDR3\n");
- while (1)
- ;
- }
-
- init_pll(&ddr3b_333);
- init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
- init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
-}
--- /dev/null
+#
+# KS2-EVM: board Makefile
+# (C) Copyright 2012-2014
+# Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += ddr3_cfg.o
+obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
Supported boot modes:
- SPI NOR boot
+ - AEMIF NAND boot
Supported image formats:-
- u-boot.bin: for loading and running u-boot.bin through Texas instruments
code composure studio (CCS)
- u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+ - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
Build instructions:
===================
>make k2hk_evm_config
>make u-boot-spi.gph
+To build u-boot-nand.gph
+ >make k2hk_evm_config
+ >make u-boot-nand.gph
+
Load and Run U-Boot on K2HK EVM using CCS
=========================================
5. At the U-Boot console type following to setup u-boot environment variables.
setenv addr_uboot 0x87000000
setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
- run burn_uboot
+ run burn_uboot_spi
Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
to "SPI Little Endian Boot mode" as per instruction at
http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
+
+AEMIF NAND Flash programming instructions
+======================================
+U-Boot image can be flashed to first 1024KB of the NAND flash using following
+instructions:-
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+ CortexA15_1 (Free Running)"
+3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+ using CCS", but using address 0x87000000.
+4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+ setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
+ run burn_uboot_nand
+ Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+ to "ARM NAND Boot mode" as per instruction at
+ http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
/*
- * K2HK EVM : Board initialization
+ * Keystone : Board initialization
*
- * (C) Copyright 2012-2014
+ * (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "board.h"
#include <common.h>
#include <exports.h>
#include <fdt_support.h>
-#include <libfdt.h>
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
+#include <asm/arch/ddr3.h>
#include <asm/arch/emac_defs.h>
-#include <asm/arch/psc_defs.h>
#include <asm/ti-common/ti-aemif.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 device_big_endian;
-
-unsigned int external_clk[ext_clk_count] = {
- [sys_clk] = 122880000,
- [alt_core_clk] = 125000000,
- [pa_clk] = 122880000,
- [tetris_clk] = 125000000,
- [ddr3a_clk] = 100000000,
- [ddr3b_clk] = 100000000,
- [mcm_clk] = 312500000,
- [pcie_clk] = 100000000,
- [sgmii_srio_clk] = 156250000,
- [xgmii_clk] = 156250000,
- [usb_clk] = 100000000,
- [rp1_clk] = 123456789 /* TODO: cannot find
- what is that */
-};
-
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = AEMIF_MODE_NAND,
.turn_around = 3,
.width = AEMIF_WIDTH_8,
},
-
-};
-
-static struct pll_init_data pll_config[] = {
- CORE_PLL_1228,
- PASS_PLL_983,
- TETRIS_PLL_1200,
};
int dram_init(void)
{
- init_ddr3();
+ ddr3_init();
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
- {
- .int_name = "K2HK_EMAC",
- .rx_flow = 22,
- .phy_addr = 0,
- .slave_port = 1,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- },
- {
- .int_name = "K2HK_EMAC1",
- .rx_flow = 23,
- .phy_addr = 1,
- .slave_port = 2,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- },
- {
- .int_name = "K2HK_EMAC2",
- .rx_flow = 24,
- .phy_addr = 2,
- .slave_port = 3,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- },
- {
- .int_name = "K2HK_EMAC3",
- .rx_flow = 25,
- .phy_addr = 3,
- .slave_port = 4,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- },
-};
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
int get_eth_env_param(char *env_name)
{
char *env;
- int res = -1;
+ int res = -1;
env = getenv(env_name);
if (env)
int board_eth_init(bd_t *bis)
{
- int j;
- int res;
- char link_type_name[32];
+ int j;
+ int res;
+ int port_num;
+ char link_type_name[32];
- for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
- j++) {
+ port_num = get_num_eth_ports();
+
+ for (j = 0; j < port_num; j++) {
sprintf(link_type_name, "sgmii%d_link_type", j);
res = get_eth_env_param(link_type_name);
if (res >= 0)
}
#endif
-/* Byte swap the 32-bit data if the device is BE */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
- u32 i;
-
- if (device_big_endian)
- for (i = 0; i < length; i++, ptr++)
- *ptr = __swab32(*ptr);
-
- return 0;
-}
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void)
-{
- init_plls(ARRAY_SIZE(pll_config), pll_config);
- return 0;
-}
-#endif
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-#define K2_DDR3_START_ADDR 0x80000000
void ft_board_setup(void *blob, bd_t *bd)
{
- u64 start[2];
+ int lpae;
+ char *env;
+ char *endp;
+ int nbanks;
u64 size[2];
- char name[32], *env, *endp;
- int lpae, nodeoffset;
+ u64 start[2];
+ char name[32];
+ int nodeoffset;
u32 ddr3a_size;
- int nbanks;
+ int unitrd_fixup = 0;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
+ env = getenv("uinitrd_fixup");
+ unitrd_fixup = env && simple_strtol(env, NULL, 0);
ddr3a_size = 0;
if (lpae) {
/* adjust memory start address for LPAE */
if (lpae) {
- start[0] -= K2_DDR3_START_ADDR;
+ start[0] -= CONFIG_SYS_SDRAM_BASE;
start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
}
fdt_fixup_memory_banks(blob, start, size, nbanks);
/* Fix up the initrd */
- if (lpae) {
- u64 initrd_start, initrd_end;
- u32 *prop1, *prop2;
+ if (lpae && unitrd_fixup) {
int err;
+ u32 *prop1, *prop2;
+ u64 initrd_start, initrd_end;
+
nodeoffset = fdt_path_offset(blob, "/chosen");
if (nodeoffset >= 0) {
prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
"linux,initrd-end", NULL);
if (prop1 && prop2) {
initrd_start = __be32_to_cpu(*prop1);
- initrd_start -= K2_DDR3_START_ADDR;
+ initrd_start -= CONFIG_SYS_SDRAM_BASE;
initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be32_to_cpu(*prop2);
- initrd_end -= K2_DDR3_START_ADDR;
+ initrd_end -= CONFIG_SYS_SDRAM_BASE;
initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
void ft_board_setup_ex(void *blob, bd_t *bd)
{
- int lpae;
- char *env;
- u64 *reserve_start, size;
+ int lpae;
+ u64 size;
+ char *env;
+ u64 *reserve_start;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
*reserve_start = __cpu_to_be64(*reserve_start);
size = __cpu_to_be64(*(reserve_start + 1));
if (size) {
- *reserve_start -= K2_DDR3_START_ADDR;
+ *reserve_start -= CONFIG_SYS_SDRAM_BASE;
*reserve_start +=
CONFIG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
--- /dev/null
+/*
+ * K2HK EVM : Board common header
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KS2_BOARD
+#define _KS2_BOARD
+
+#include <asm/arch/emac_defs.h>
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int get_num_eth_ports(void);
+
+#endif
--- /dev/null
+/*
+ * K2E EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 100000000,
+ [alt_core_clk] = 100000000,
+ [pa_clk] = 100000000,
+ [ddr3_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+};
+
+static struct pll_init_data pll_config[] = {
+ CORE_PLL_1200,
+ PASS_PLL_1000,
+};
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ init_plls(ARRAY_SIZE(pll_config), pll_config);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 125000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 125000000,
+ [ddr3a_clk] = 100000000,
+ [ddr3b_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_srio_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+ [rp1_clk] = 123456789
+};
+
+static struct pll_init_data pll_config[] = {
+ CORE_PLL_1228,
+ PASS_PLL_983,
+ TETRIS_PLL_1200,
+};
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2HK_EMAC",
+ .rx_flow = 22,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC1",
+ .rx_flow = 23,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC2",
+ .rx_flow = 24,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2HK_EMAC3",
+ .rx_flow = 25,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ init_plls(ARRAY_SIZE(pll_config), pll_config);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <i2c.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR3 PHY configuration data with 1600M rate, 8GB size */
+struct ddr3_phy_config ddr3phy_1600_8g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0xA19DBB66ul,
+ .dtpr1 = 0x32868300ul,
+ .dtpr2 = 0x50035200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x730035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
+struct ddr3_emif_config ddr3_1600_8g = {
+ .sdcfg = 0x6200CE6Aul,
+ .sdtim1 = 0x16709C55ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF54ul,
+ .sdtim4 = 0x553F0CFFul,
+ .zqcfg = 0xF0073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+#ifdef CONFIG_K2HK_EVM
+/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
+struct ddr3_phy_config ddr3phy_1333_2g = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x32857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
+struct ddr3_emif_config ddr3_1333_2g = {
+ .sdcfg = 0x62008C62ul,
+ .sdtim1 = 0x125C8044ul,
+ .sdtim2 = 0x00001D29ul,
+ .sdtim3 = 0x32CDFF43ul,
+ .sdtim4 = 0x543F0ADFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001457ul,
+};
+#endif
+
+#ifdef CONFIG_K2E_EVM
+/* DDR3 PHY configuration data with 1600M rate, and 4GB size */
+struct ddr3_phy_config ddr3phy_1600_4g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x08861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x9D9CBB66ul,
+ .dtpr1 = 0x12840300ul,
+ .dtpr2 = 0x5002D200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */
+struct ddr3_emif_config ddr3_1600_4g = {
+ .sdcfg = 0x6200CE62ul,
+ .sdtim1 = 0x166C9855ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x421DFF53ul,
+ .sdtim4 = 0x543F07FFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+#endif
+
+int ddr3_get_dimm_params(char *dimm_name)
+{
+ int ret;
+ int old_bus;
+ u8 spd_params[256];
+
+ i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+ old_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+ i2c_set_bus_num(old_bus);
+
+ dimm_name[0] = '\0';
+
+ if (ret) {
+ puts("Cannot read DIMM params\n");
+ return 1;
+ }
+
+ /*
+ * We need to convert spd data to dimm parameters
+ * and to DDR3 EMIF and PHY regirsters values.
+ * For now we just return DIMM type string value.
+ * Caller may use this value to choose appropriate
+ * a pre-set DDR3 configuration
+ */
+
+ strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+ dimm_name[18] = '\0';
+
+ return 0;
+}
--- /dev/null
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR3_CFG_H
+#define __DDR3_CFG_H
+
+extern struct ddr3_phy_config ddr3phy_1600_8g;
+extern struct ddr3_emif_config ddr3_1600_8g;
+
+extern struct ddr3_phy_config ddr3phy_1333_2g;
+extern struct ddr3_emif_config ddr3_1333_2g;
+
+extern struct ddr3_phy_config ddr3phy_1600_4g;
+extern struct ddr3_emif_config ddr3_1600_4g;
+
+int ddr3_get_dimm_params(char *dimm_name);
+
+#endif /* __DDR3_CFG_H */
--- /dev/null
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+ char dimm_name[32];
+
+ if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
+ init_pll(&ddr3_400);
+
+ ddr3_get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ /* 8G SO-DIMM */
+ ddr3_size = 8;
+ printf("DRAM: 8 GiB\n");
+ ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
+ } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
+ /* 4G SO-DIMM */
+ ddr3_size = 4;
+ printf("DRAM: 4 GiB\n");
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
+ }
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
--- /dev/null
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+
+void ddr3_init(void)
+{
+ char dimm_name[32];
+
+ ddr3_get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ init_pll(&ddr3a_400);
+ if (cpu_revision() > 0) {
+ if (cpu_revision() > 1) {
+ /* PG 2.0 */
+ /* Reset DDR3A PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+ ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1600_8g);
+ } else {
+ /* PG 1.1 */
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1600_8g);
+ }
+
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_8g);
+ printf("DRAM: Capacity 8 GiB (includes reported below)\n");
+ } else {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+ ddr3_1600_8g.sdcfg |= 0x1000;
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_8g);
+ printf("DRAM: Capacity 4 GiB (includes reported below)\n");
+ }
+ } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
+ init_pll(&ddr3a_333);
+ if (cpu_revision() > 0) {
+ if (cpu_revision() > 1) {
+ /* PG 2.0 */
+ /* Reset DDR3A PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+ ddr3phy_1333_2g.zq0cr1 |= 0x10000;
+ ddr3phy_1333_2g.zq1cr1 |= 0x10000;
+ ddr3phy_1333_2g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1333_2g);
+ } else {
+ /* PG 1.1 */
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1333_2g);
+ }
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_2g);
+ } else {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
+ ddr3_1333_2g.sdcfg |= 0x1000;
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_2g);
+ }
+ } else {
+ printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+ while (1)
+ ;
+ }
+}
Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 highbank - highbank highbank - Rob Herring <robh@kernel.org>
-Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
+Active arm armv7 keystone ti ks2_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
+Active arm armv7 keystone ti ks2_evm k2e_evm - Vitaly Andrianov <vitalya@ti.com>
Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
if (!ft_verify_fdt(blob))
return -1;
-#ifdef CONFIG_SOC_K2HK
+#if defined(CONFIG_SOC_KEYSTONE)
if (IMAGE_OF_BOARD_SETUP)
ft_board_setup_ex(blob, gd->bd);
#endif
Configuration Options:
+ CONFIG_SYS_NAND_U_BOOT_OFFS
+ NAND Offset from where SPL will read u-boot image. This is the starting
+ address of u-boot MTD partition in NAND.
+
CONFIG_CMD_NAND
Enables NAND support and commmands.
detection. However ECC calculation on such plaforms would still be
done by GPMC controller.
+ CONFIG_SPL_NAND_AM33XX_BCH
+ Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
+ hardware ECC correction. This is useful for platforms which have ELM
+ hardware engine and use NAND boot mode.
+ Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+ so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
+ SPL-NAND driver with software ECC correction support.
+
CONFIG_NAND_OMAP_ECCSCHEME
On OMAP platforms, this CONFIG specifies NAND ECC scheme.
It can take following values:
#endif
};
+#if defined CONFIG_KEYSTONE_RBL_NAND
+#if defined(CONFIG_SYS_NAND_PAGE_2K)
+static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
+ .eccbytes = 40,
+ .eccpos = {
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4, },
+ {.offset = 16, .length = 6, },
+ {.offset = 32, .length = 6, },
+ {.offset = 48, .length = 6, },
+ },
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+ .eccbytes = 80,
+ .eccpos = {
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+ 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
+ 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
+ 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4, },
+ {.offset = 16, .length = 6, },
+ {.offset = 32, .length = 6, },
+ {.offset = 48, .length = 6, },
+ {.offset = 64, .length = 6, },
+ {.offset = 80, .length = 6, },
+ {.offset = 96, .length = 6, },
+ {.offset = 112, .length = 6, },
+ },
+#endif
+};
+
+#ifdef CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
+#endif
+
+/**
+ * nand_davinci_write_page - write one page
+ * @mtd: MTD device structure
+ * @chip: NAND chip descriptor
+ * @buf: the data to write
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
+ * @cached: cached programming
+ * @raw: use _raw version of write_page
+ */
+static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required,
+ int page, int cached, int raw)
+{
+ int status;
+ int ret = 0;
+ struct nand_ecclayout *saved_ecc_layout;
+
+ /* save current ECC layout and assign Keystone RBL ECC layout */
+ if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ saved_ecc_layout = chip->ecc.layout;
+ chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
+ mtd->oobavail = chip->ecc.layout->oobavail;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+
+ if (unlikely(raw))
+ status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
+ else
+ status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+
+ if (status < 0) {
+ ret = status;
+ goto err;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
+
+ /*
+ * See if operation failed and additional status checks are
+ * available.
+ */
+ if ((status & NAND_STATUS_FAIL) && (chip->errstat))
+ status = chip->errstat(mtd, chip, FL_WRITING, status, page);
+
+ if (status & NAND_STATUS_FAIL) {
+ ret = -EIO;
+ goto err;
+ }
+
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+ /* Send command to read back the data */
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+ if (chip->verify_buf(mtd, buf, mtd->writesize)) {
+ ret = -EIO;
+ goto err;
+ }
+
+ /* Make sure the next page prog is preceded by a status read */
+ chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+#endif
+err:
+ /* restore ECC layout */
+ if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ chip->ecc.layout = saved_ecc_layout;
+ mtd->oobavail = saved_ecc_layout->oobavail;
+ }
+
+ return ret;
+}
+
+/**
+ * nand_davinci_read_page_hwecc - hardware ECC based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
+ *
+ * Not for syndrome calculating ECC controllers which need a special oob layout.
+ */
+static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint32_t *eccpos;
+ uint8_t *p = buf;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
+
+ /* save current ECC layout and assign Keystone RBL ECC layout */
+ if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
+ mtd->oobavail = chip->ecc.layout->oobavail;
+ }
+
+ eccpos = chip->ecc.layout->eccpos;
+
+ /* Read the OOB area first */
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+
+ /* restore ECC layout */
+ if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ chip->ecc.layout = saved_ecc_layout;
+ mtd->oobavail = saved_ecc_layout->oobavail;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_KEYSTONE_RBL_NAND */
+
static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
u32 val;
void davinci_nand_init(struct nand_chip *nand)
{
+#if defined CONFIG_KEYSTONE_RBL_NAND
+ int i;
+ struct nand_ecclayout *layout;
+
+ layout = &nand_keystone_rbl_4bit_layout_oobfirst;
+ layout->oobavail = 0;
+ for (i = 0; layout->oobfree[i].length &&
+ i < ARRAY_SIZE(layout->oobfree); i++)
+ layout->oobavail += layout->oobfree[i].length;
+
+ nand->write_page = nand_davinci_write_page;
+ nand->ecc.read_page = nand_davinci_read_page_hwecc;
+#endif
nand->chip_delay = 0;
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
nand->bbt_options |= NAND_BBT_USE_FLASH;
#define chan_read(chan, fld) __raw_readl((chan)->fld)
#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
+#define for_active_slave(slave, priv) \
+ slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
#define for_each_slave(slave, priv) \
for (slave = (priv)->slaves; slave != (priv)->slaves + \
(priv)->data.slaves; slave++)
int link = 0;
struct cpsw_slave *slave;
- for_each_slave(slave, priv)
+ for_active_slave(slave, priv)
cpsw_slave_update_link(slave, priv, &link);
priv->mdio_link = readl(&mdio_regs->link);
return link;
ALE_SECURE);
cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
- for_each_slave(slave, priv)
+ for_active_slave(slave, priv)
cpsw_slave_init(slave, priv);
cpsw_update_link(priv);
cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
priv->bus = miiphy_get_dev_by_name(dev->name);
- for_each_slave(slave, priv)
+ for_active_slave(slave, priv)
cpsw_phy_init(dev, slave);
return 1;
#include <common.h>
#include <i2c.h>
+#include <asm/errno.h>
+#include <power/pmic.h>
#include <power/tps65218.h>
/**
return 0;
}
+
+int power_tps65218_init(unsigned char bus)
+{
+ static const char name[] = "TPS65218_PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = TPS65218_PMIC_NUM_OF_REGS;
+ p->hw.i2c.addr = TPS65218_CHIP_PM;
+ p->hw.i2c.tx_num = 1;
+ p->bus = bus;
+
+ return 0;
+}
#define serial_in(y) readb(y)
#endif
-#if defined(CONFIG_K2HK_EVM)
+#if defined(CONFIG_SOC_KEYSTONE)
#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
#undef UART_MCRVAL
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, &com_port->mdr1);
#endif /* CONFIG_OMAP */
-#if defined(CONFIG_K2HK_EVM)
+#if defined(CONFIG_SOC_KEYSTONE)
serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
#endif
}
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#endif
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
#ifdef CONFIG_NOR_BOOT
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* Power */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
#define CONFIG_POWER_TPS65218
/* SPL defines. */
#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_NAND_ONFI_DETECTION
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
/* GPIO pin + bank to pin ID mapping */
#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
*/
/* **** PISMO SUPPORT *** */
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* NAND and environment organization */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_ENV_IS_IN_NAND 1
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
--- /dev/null
+/*
+ * Configuration header file for TI's k2e-evm
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_K2E_EVM_H
+#define __CONFIG_K2E_EVM_H
+
+/* Platform type */
+#define CONFIG_SOC_K2E
+#define CONFIG_K2E_EVM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT "K2E EVM # "
+
+#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
+
+#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0"
+#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
+#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0"
+#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0"
+#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0"
+
+#include <configs/ks2_evm.h>
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE 0x0c100000
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#endif /* __CONFIG_K2E_EVM_H */
#define CONFIG_SOC_K2HK
#define CONFIG_K2HK_EVM
-/* U-Boot Build Configuration */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_THUMB_BUILD
-
-/* SoC Configuration */
-#define CONFIG_ARMV7
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_TEXT_BASE 0x0c001000
-#define CONFIG_SPL_TARGET "u-boot-spi.gph"
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Memory Configuration */
-#define CONFIG_NR_DRAM_BANKS 2
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
-#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
-#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
- GENERATED_GBL_DATA_SIZE)
-
-/* SPL SPI Loader Configuration */
-#define CONFIG_SPL_TEXT_BASE 0x0c200000
-#define CONFIG_SPL_PAD_TO 65536
-#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
-#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
- CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
-#define CONFIG_SPL_STACK_SIZE (8 * 1024)
-#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
- CONFIG_SYS_SPL_MALLOC_SIZE + \
- CONFIG_SPL_STACK_SIZE - 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
-#define CONFIG_SPL_FRAMEWORK
-
-/* UART Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6)
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* SPI Configuration */
-#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI0
-#define CONFIG_SYS_SPI_BASE K2HK_SPI_BASE
-#define CONFIG_SYS_SPI0_NUM_CS 4
-#define CONFIG_SYS_SPI1
-#define CONFIG_SYS_SPI1_BASE K2HK_SPI1_BASE
-#define CONFIG_SYS_SPI1_NUM_CS 4
-#define CONFIG_SYS_SPI2
-#define CONFIG_SYS_SPI2_NUM_CS 4
-#define CONFIG_SYS_SPI2_BASE K2HK_SPI2_BASE
-#define CONFIG_CMD_SPI
-#define CONFIG_SYS_SPI_CLK clk_get_rate(K2HK_LPSC_EMIF25_SPI)
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT "K2HK EVM # "
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
-#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
-#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
-#define I2C_BUS_MAX 3
+#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
-/* EEPROM definitions */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0"
+#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0"
+#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0"
+#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0"
+#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0"
-/* Network Configuration */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 32
-#define CONFIG_NET_MULTI
-#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
-#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
-#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
-#define CONFIG_SYS_SGMII_RATESCALE 2
+#include <configs/ks2_evm.h>
-/* AEMIF */
-#define CONFIG_TI_AEMIF
-#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE 0x0c200000
/* NAND Configuration */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_NAND_ECCLAYOUT
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_MASK_CLE 0x4000
-#define CONFIG_SYS_NAND_MASK_ALE 0x2000
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
- "1024k(bootloader)ro,512k(params)ro," \
- "-(ubifs)"
-/* U-Boot command configuration */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_EEPROM
-
-/* U-Boot general configuration */
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_SYS_PROMPT "K2HK EVM # "
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_PBSIZE 2048
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "boot=ramfs\0" \
- "tftp_root=/\0" \
- "nfs_root=/export\0" \
- "mem_lpae=1\0" \
- "mem_reserve=512M\0" \
- "addr_fdt=0x87000000\0" \
- "addr_kern=0x88000000\0" \
- "addr_mon=0x0c5f0000\0" \
- "addr_uboot=0x87000000\0" \
- "addr_fs=0x82000000\0" \
- "addr_ubi=0x82000000\0" \
- "fdt_high=0xffffffff\0" \
- "name_fdt=uImage-k2hk-evm.dtb\0" \
- "name_fs=arago-console-image.cpio.gz\0" \
- "name_kern=uImage-keystone-evm.bin\0" \
- "name_mon=skern-keystone-evm.bin\0" \
- "name_uboot=u-boot-spi-keystone-evm.gph\0" \
- "name_ubi=keystone-evm-ubifs.ubi\0" \
- "run_mon=mon_install ${addr_mon}\0" \
- "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
- "init_net=run args_all args_net\0" \
- "init_ubi=run args_all args_ubi; " \
- "ubi part ubifs; ubifsmount boot\0" \
- "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
- "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
- "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
- "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
- "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
- "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
- "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
- "burn_uboot=sf probe; sf erase 0 0x100000; " \
- "sf write ${addr_uboot} 0 ${filesize}\0" \
- "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
- "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
- "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
- "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
- "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
- "${nfs_options} ip=dhcp\0" \
- "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
- "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
- "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
- "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
- "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
- "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
- "burn_ubi=nand erase.part ubifs; " \
- "nand write ${addr_ubi} ubifs ${filesize}\0" \
- "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
- "args_ramfs=setenv bootargs ${bootargs} earlyprintk " \
- "rdinit=/sbin/init rw root=/dev/ram0 " \
- "initrd=0x802000000,9M\0" \
- "no_post=1\0" \
- "mtdparts=mtdparts=davinci_nand.0:" \
- "1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0"
-#define CONFIG_BOOTCOMMAND \
- "run init_${boot} get_fdt_${boot} get_mon_${boot} " \
- "get_kern_${boot} run_mon run_kern"
-#define CONFIG_BOOTARGS \
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_SYS_BARGSIZE 1024
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
-
-#define CONFIG_SUPPORT_RAW_INITRD
-
-/* we may include files below only after all above definitions */
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#define CONFIG_SYS_HZ_CLOCK clk_get_rate(K2HK_CLK1_6)
+/* Network */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
#endif /* __CONFIG_K2HK_EVM_H */
--- /dev/null
+/*
+ * Common configuration header file for all Keystone II EVM platforms
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_KS2_EVM_H
+#define __CONFIG_KS2_EVM_H
+
+#define CONFIG_SOC_KEYSTONE
+
+/* U-Boot Build Configuration */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
+#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_THUMB_BUILD
+
+/* SoC Configuration */
+#define CONFIG_ARMV7
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_TEXT_BASE 0x0c001000
+#define CONFIG_SPL_TARGET "u-boot-spi.gph"
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory Configuration */
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
+#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
+#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_PAD_TO 65536
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
+#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
+#define CONFIG_SPL_STACK_SIZE (8 * 1024)
+#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
+ CONFIG_SYS_SPL_MALLOC_SIZE + \
+ CONFIG_SPL_STACK_SIZE - 4)
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SPL_FRAMEWORK
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
+#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* SPI Configuration */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SYS_SPI0
+#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
+#define CONFIG_SYS_SPI0_NUM_CS 4
+#define CONFIG_SYS_SPI1
+#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
+#define CONFIG_SYS_SPI1_NUM_CS 4
+#define CONFIG_SYS_SPI2
+#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
+#define CONFIG_SYS_SPI2_NUM_CS 4
+
+/* Network Configuration */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 32
+#define CONFIG_NET_MULTI
+#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
+#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
+#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
+#define CONFIG_SYS_SGMII_RATESCALE 2
+
+/* AEMIF */
+#define CONFIG_TI_AEMIF
+#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
+#define I2C_BUS_MAX 3
+
+/* EEPROM definitions */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/* NAND Configuration */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_KEYSTONE_RBL_NAND
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
+#define CONFIG_SYS_NAND_MASK_CLE 0x4000
+#define CONFIG_SYS_NAND_MASK_ALE 0x2000
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
+ "1024k(bootloader)ro,512k(params)ro," \
+ "-(ubifs)"
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_EEPROM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE 2048
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* EDMA3 */
+#define CONFIG_TI_EDMA3
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "boot=ramfs\0" \
+ "tftp_root=/\0" \
+ "nfs_root=/export\0" \
+ "mem_lpae=1\0" \
+ "mem_reserve=512M\0" \
+ "addr_fdt=0x87000000\0" \
+ "addr_kern=0x88000000\0" \
+ KS2_ADDR_MON \
+ "addr_uboot=0x87000000\0" \
+ "addr_fs=0x82000000\0" \
+ "addr_ubi=0x82000000\0" \
+ "addr_secdb_key=0xc000000\0" \
+ "fdt_high=0xffffffff\0" \
+ KS2_FDT_NAME \
+ "name_fs=arago-console-image.cpio.gz\0" \
+ "name_kern=uImage\0" \
+ KS2_NAME_MON \
+ NAME_UBOOT \
+ NAME_UBI \
+ "run_mon=mon_install ${addr_mon}\0" \
+ "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
+ "init_net=run args_all args_net\0" \
+ "init_ubi=run args_all args_ubi; " \
+ "ubi part ubifs; ubifsmount boot;" \
+ "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
+ "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
+ "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
+ "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
+ "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
+ "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
+ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
+ "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
+ "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
+ "sf write ${addr_uboot} 0 ${filesize}\0" \
+ "burn_uboot_nand=nand erase 0 0x100000; " \
+ "nand write ${addr_uboot} 0 ${filesize}\0" \
+ "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
+ KS2_ARGS_UBI \
+ "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
+ "${nfs_options} ip=dhcp\0" \
+ "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
+ "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
+ "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
+ "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
+ "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
+ "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
+ "burn_ubi=nand erase.part ubifs; " \
+ "nand write ${addr_ubi} ubifs ${filesize}\0" \
+ "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
+ "args_ramfs=setenv bootargs ${bootargs} " \
+ "rdinit=/sbin/init rw root=/dev/ram0 " \
+ "initrd=0x802000000,9M\0" \
+ "no_post=1\0" \
+ "mtdparts=mtdparts=davinci_nand.0:" \
+ "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run init_${boot} get_fdt_${boot} get_mon_${boot} " \
+ "get_kern_${boot} run_mon run_kern"
+
+#define CONFIG_BOOTARGS \
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_SYS_BARGSIZE 1024
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
+#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* we may include files below only after all above definitions */
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
+
+/* Maximum memory size for relocated U-boot at the end of the DDR3 memory
+ which is NOT applicable for DDR ECC test */
+#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */
+
+#endif /* __CONFIG_KS2_EVM_H */
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
#ifdef ONENAND_SUPPORT
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#endif /* __CONFIG_H */
/*
* PISMO support
*/
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
/* Monitor at start of flash - Reserve 2 sectors */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
* NAND / OneNAND
*/
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#endif
*/
#ifdef CONFIG_BOOT_ONENAND
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
-
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#endif
#ifdef CONFIG_NAND
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#endif
#endif /* __IGEP00X0_H */
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
#endif
/* Monitor at start of flash */
0x01F00000) /* 31MB */
/* FLASH and environment organization */
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
#if defined(CONFIG_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#endif /* __CONFIG_H */
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
"4m(kernel),-(fs)"
#if defined(CONFIG_CMD_NAND)
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
#endif
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* un-assigned */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
/*
* USB configuration. We enable MUSB support, both for host and for
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
#define MACH_TYPE_OMAP3_TAO3530 2836
*/
/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-/* NAND */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
-#endif
-
/* spl export command */
#define CONFIG_CMD_SPL
#endif
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_MTD_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
#endif /* !CONFIG_NOR_BOOT */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* NAND and environment organization */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
struct cpsw_slave_data *slave_data;
void (*control)(int enabled);
u32 host_port_num;
+ u32 active_slave;
u8 version;
};
};
int pmic_init(unsigned char bus);
+int power_init_board(void);
int pmic_dialog_init(unsigned char bus);
int check_reg(struct pmic *p, u32 reg);
struct pmic *pmic_alloc(void);
int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
uchar mask);
int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+int power_tps65218_init(unsigned char bus);
#endif /* __POWER_TPS65218_H__ */
projects / karo-tx-uboot.git / commitdiff