ARM: cache: implement a default weak flush_cache() function

Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu <josh.wu@atmel.com>

diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 06dee0fc1b9c7b0073be63e0d89f6e79a4d0e2d7..1e4c2142b1317cea432c950af40486b35876fe53 100644 (file)
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -110,11 +110,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
        asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
        asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 

-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}
-

 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {


@@ -123,10 +118,6 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
 void flush_dcache_all(void)
 {
 }

-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}

 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 99d1a139b0dc4e5b8b6e1bb5494bcce29bd8ba0b..e5c1a6ae6c92965e20144094a4d9af1a3fd13c9c 100644 (file)
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -69,11 +69,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 
        asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
 
        asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }

-
-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}

 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {


@@ -82,10 +77,6 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
 void flush_dcache_all(void)
 {
 }

-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}

 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 /*
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 /*

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 1dcceb846ffbdb65a0507d746bb51a01d5fbb292..4a6207a74064e3f7b3febb0c40249604378414b0 100644 (file)
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -288,15 +288,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
        flush_dcache_range(start, stop);
        v7_inval_tlb();
 }
        flush_dcache_range(start, stop);
        v7_inval_tlb();
 }

-
-/*
- * Flush range from all levels of d-cache/unified-cache used:
- * Affects the range [start, start + size - 1]
- */
-void  flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}

 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {


@@ -310,10 +301,6 @@ void arm_init_before_mmu(void)
 {
 }
 
 {
 }
 

-void  flush_cache(unsigned long start, unsigned long size)
-{
-}
-

 void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 }
 void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 }

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index cd160c4b633b94ef33efc2221bd1411497a9bac2..835f6a6525ea08e8c3a1473d78fa7dbf1428c681 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -253,11 +253,3 @@ void __weak enable_caches(void)
        icache_enable();
        dcache_enable();
 }
        icache_enable();
        dcache_enable();
 }

-
-/*
- * Flush range from all levels of d-cache/unified-cache
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index a690e0b53cbaeacc1fda19fea1cb4a7922122f05..cd13db3440ddf783e0cb8089e4cd5724a90e7831 100644 (file)
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,31 +10,13 @@
 #include <common.h>
 #include <malloc.h>
 
 #include <common.h>
 #include <malloc.h>
 

+/*
+ * Flush range from all levels of d-cache/unified-cache.
+ * Affects the range [start, start + size - 1].
+ */

 __weak void flush_cache(unsigned long start, unsigned long size)
 {
 __weak void flush_cache(unsigned long start, unsigned long size)
 {

-#if defined(CONFIG_CPU_ARM1136)
-
-#if !defined(CONFIG_SYS_ICACHE_OFF)
-       asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
-#endif
-
-#if !defined(CONFIG_SYS_DCACHE_OFF)
-       asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
-#endif
-
-#endif /* CONFIG_CPU_ARM1136 */
-
-#ifdef CONFIG_CPU_ARM926EJS
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-       asm(
-               /* test and clean, page 2-23 of arm926ejs manual */
-               "0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n"
-               /* flush write buffer as well (page 2-22) */
-               "mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory"
-               );
-#endif
-#endif /* CONFIG_CPU_ARM926EJS */
-       return;
+       flush_dcache_range(start, start + size);

 }
 
 /*
 }
 
 /*