VERSION = 2015
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
rom: u-boot.rom FORCE
IFDTOOL=$(objtree)/tools/ifdtool
-IFDTOOL_FLAGS = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin
+IFDTOOL_FLAGS = -f 0:$(objtree)/u-boot.dtb
+IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
+IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin
IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
ifneq ($(CONFIG_HAVE_INTEL_ME),)
endif
ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
+endif
+
+ifneq ($(CONFIG_HAVE_FSP),)
+IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_CMC),)
+IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
endif
ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
endif
quiet_cmd_ifdtool = IFDTOOL $@
regarding the non-volatile storage device. Define this to
the eMMC device that fastboot should use to store the image.
+ CONFIG_FASTBOOT_GPT_NAME
+ The fastboot "flash" command supports writing the downloaded
+ image to the Protective MBR and the Primary GUID Partition
+ Table. (Additionally, this downloaded image is post-processed
+ to generate and write the Backup GUID Partition Table.)
+ This occurs when the specified "partition name" on the
+ "fastboot flash" command line matches this value.
+ Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
+
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
CONFIG_JFFS2_NAND_DEV
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC_START).
+- CONFIG_SYS_NONCACHED_MEMORY:
+ Size of non-cached memory area. This area of memory will be
+ typically located right below the malloc() area and mapped
+ uncached in the MMU. This is useful for drivers that would
+ otherwise require a lot of explicit cache maintenance. For
+ some drivers it's also impossible to properly maintain the
+ cache. For example if the regions that need to be flushed
+ are not a multiple of the cache-line size, *and* padding
+ cannot be allocated between the regions to align them (i.e.
+ if the HW requires a contiguous array of regions, and the
+ size of each region is not cache-aligned), then a flush of
+ one region may result in overwriting data that hardware has
+ written to another region in the same cache-line. This can
+ happen for example in network drivers where descriptors for
+ buffers are typically smaller than the CPU cache-line (e.g.
+ 16 bytes vs. 32 or 64 bytes).
+
+ Non-cached memory is only supported on 32-bit ARM at present.
+
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
bool "Panasonic UniPhier platform"
select CPU_V7
select SUPPORT_SPL
+ select SPL
select OF_CONTROL if !SPL_BUILD
endchoice
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y += clk-usb-otg.o
.gate = SW_ONLY_GATE(0x0360, 20, 4),
};
+static struct bus_clk_data usb_otg_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
static struct bus_clk_data sdio1_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
};
*/
/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+ .clk = {
+ .name = "usb_otg_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &usb_otg_ahb_data,
+};
+
static struct bus_clock sdio1_ahb_clk = {
.clk = {
.name = "sdio1_ahb_clk",
CLK_LK(bsc2),
CLK_LK(bsc3),
/* Bus clocks */
+ CLK_LK(usb_otg_ahb),
CLK_LK(sdio1_ahb),
CLK_LK(sdio2_ahb),
CLK_LK(sdio3_ahb),
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case HSOTG_BASE_ADDR:
+ ahbstr = "usb_otg_ahb_clk";
+ break;
+ default:
+ printf("%s: base 0x%p not found\n", __func__, base);
+ return -EINVAL;
+ }
+
+ return clk_get_and_enable(ahbstr);
+}
config TARGET_ODROID
bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3
+ bool "Exynos5422 Odroid board"
+ select OF_CONTROL
+
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
select CPU_V7_HAS_NONSEC
if (sel == 0x3)
sclk = get_pll_clk(MPLL);
+ else if (sel == 0x4)
+ sclk = get_pll_clk(SPLL);
else if (sel == 0x6)
sclk = get_pll_clk(EPLL);
else
{
return 0;
}
+
+int __weak clk_usb_otg_enable(void *base)
+{
+ return 0;
+}
case MXC_SATA_CLK:
return get_ahb_clk();
default:
+ printf("Unsupported MXC CLK: %d\n", clk);
break;
}
- return -1;
+ return 0;
}
/*
#include <altera.h>
#include <miiphy.h>
#include <netdev.h>
+#include <watchdog.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/dwmmc.h>
int arch_cpu_init(void)
{
+#ifdef CONFIG_HW_WATCHDOG
+ /*
+ * In case the watchdog is enabled, make sure to (re-)configure it
+ * so that the defined timeout is valid. Otherwise the SPL (Perloader)
+ * timeout value is still active which might too short for Linux
+ * booting.
+ */
+ hw_watchdog_init();
+#else
/*
* If the HW watchdog is NOT enabled, make sure it is not running,
* for example because it was enabled in the preloader. This might
* trigger a watchdog-triggered reboot of Linux kernel later.
*/
-#ifndef CONFIG_HW_WATCHDOG
socfpga_watchdog_reset();
#endif
+
return 0;
}
bool
default SPL_BUILD
+config CMD_DDRPHY_DUMP
+ bool "Enable dump command of DDR PHY parameters"
+ depends on !SPL_BUILD
+ help
+ The command "ddrphy" shows the resulting parameters of DDR PHY
+ training; it is useful for the evaluation of DDR PHY training.
+
choice
prompt "DDR3 Frequency select"
depends on DRAM_INIT
obj-y += cache_uniphier.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
obj-y += dram_init.o
+obj-$(CONFIG_DRAM_INIT) += ddrphy_training.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
+obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
obj-y += board_common.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
+{
+ return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
+}
+
+static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
+{
+ int ch, p, dx;
+ struct ddrphy __iomem *phy;
+
+ for (ch = 0; ch < NR_DDRCH; ch++) {
+ for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+ phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ printf("CH%dP%dDX%d:", ch, p, dx);
+ (*callback)(&phy->dx[dx]);
+ printf("\n");
+ }
+ }
+ }
+}
+
+static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+
+ for (i = 0; i < 10; i++)
+ printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+ printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
+}
+
+void wbdl_dump(void)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+
+ for (i = 15; i < 24; i++)
+ printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+ printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
+}
+
+void rbdl_dump(void)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
+
+ dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int rank;
+ u32 lcdlr0 = readl(&dx->lcdlr[0]);
+ u32 gtr = readl(&dx->gtr);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+void wld_dump(void)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int rank;
+ u32 lcdlr2 = readl(&dx->lcdlr[2]);
+ u32 gtr = readl(&dx->gtr);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+void dqsgd_dump(void)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+ u32 mdl = readl(&dx->mdlr);
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+void mdl_dump(void)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
+ p - (u32 *)phy, #x, p, readl(p)); }
+
+void reg_dump(void)
+{
+ int ch, p;
+ struct ddrphy __iomem *phy;
+
+ printf("\n--- DDR PHY registers ---\n");
+
+ for (ch = 0; ch < NR_DDRCH; ch++) {
+ for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+ printf("== Ch%d, PHY%d ==\n", ch, p);
+ printf(" No: Name : Address : Data\n");
+
+ phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+ REG_DUMP(ridr);
+ REG_DUMP(pir);
+ REG_DUMP(pgcr[0]);
+ REG_DUMP(pgcr[1]);
+ REG_DUMP(pgsr[0]);
+ REG_DUMP(pgsr[1]);
+ REG_DUMP(pllcr);
+ REG_DUMP(ptr[0]);
+ REG_DUMP(ptr[1]);
+ REG_DUMP(ptr[2]);
+ REG_DUMP(ptr[3]);
+ REG_DUMP(ptr[4]);
+ REG_DUMP(acmdlr);
+ REG_DUMP(acbdlr);
+ REG_DUMP(dxccr);
+ REG_DUMP(dsgcr);
+ REG_DUMP(dcr);
+ REG_DUMP(dtpr[0]);
+ REG_DUMP(dtpr[1]);
+ REG_DUMP(dtpr[2]);
+ REG_DUMP(mr0);
+ REG_DUMP(mr1);
+ REG_DUMP(mr2);
+ REG_DUMP(mr3);
+ REG_DUMP(dx[0].gcr);
+ REG_DUMP(dx[0].gtr);
+ REG_DUMP(dx[1].gcr);
+ REG_DUMP(dx[1].gtr);
+ }
+ }
+}
+
+static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *cmd = argv[1];
+
+ if (argc == 1)
+ cmd = "all";
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump();
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump();
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump();
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump();
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump();
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddr, 2, 1, do_ddr,
+ "UniPhier DDR PHY parameters dumper",
+ "- dump all of the followings\n"
+ "ddr wbdl - dump Write Bit Delay\n"
+ "ddr rbdl - dump Read Bit Delay\n"
+ "ddr wld - dump Write Leveling\n"
+ "ddr dqsgd - dump DQS Gating Delay\n"
+ "ddr mdl - dump Master Delay Line\n"
+ "ddr reg - dump registers\n"
+);
#include <common.h>
#include <asm/arch/boot-device.h>
+#include <asm/arch/sbc-regs.h>
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
mode_sel = get_boot_mode_sel();
+ printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
+
puts("Boot Mode Pin:\n");
for (table = boot_device_table; strlen(table->info); table++) {
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
+{
+ int dx;
+ u32 __iomem tmp, *p;
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ p = &phy->dx[dx].gcr;
+
+ tmp = readl(p);
+ /* Specify the rank that should be write leveled */
+ tmp &= ~DXGCR_WLRKEN_MASK;
+ tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
+ writel(tmp, p);
+ }
+
+ p = &phy->dtcr;
+
+ tmp = readl(p);
+ /* Specify the rank used during data bit deskew and eye centering */
+ tmp &= ~DTCR_DTRANK_MASK;
+ tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
+ /* Use Multi-Purpose Register for DQS gate training */
+ tmp |= DTCR_DTMPR;
+ /* Specify the rank enabled for data-training */
+ tmp &= ~DTCR_RNKEN_MASK;
+ tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+ writel(tmp, p);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static struct ddrphy_init_sequence init_sequence[] = {
+ {
+ "DRAM Initialization",
+ PIR_DRAMRST | PIR_DRAMINIT,
+ PGSR0_DIDONE,
+ PGSR0_DIERR
+ },
+ {
+ "Write Leveling",
+ PIR_WL,
+ PGSR0_WLDONE,
+ PGSR0_WLERR
+ },
+ {
+ "Read DQS Gate Training",
+ PIR_QSGATE,
+ PGSR0_QSGDONE,
+ PGSR0_QSGERR
+ },
+ {
+ "Write Leveling Adjustment",
+ PIR_WLADJ,
+ PGSR0_WLADONE,
+ PGSR0_WLAERR
+ },
+ {
+ "Read Bit Deskew",
+ PIR_RDDSKW,
+ PGSR0_RDDONE,
+ PGSR0_RDERR
+ },
+ {
+ "Write Bit Deskew",
+ PIR_WRDSKW,
+ PGSR0_WDDONE,
+ PGSR0_WDERR
+ },
+ {
+ "Read Eye Training",
+ PIR_RDEYE,
+ PGSR0_REDONE,
+ PGSR0_REERR
+ },
+ {
+ "Write Eye Training",
+ PIR_WREYE,
+ PGSR0_WEDONE,
+ PGSR0_WEERR
+ }
+};
+
+int ddrphy_training(struct ddrphy __iomem *phy)
+{
+ int i;
+ u32 pgsr0;
+ u32 init_flag = PIR_INIT;
+ u32 done_flag = PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ init_flag |= init_sequence[i].init_flag;
+ done_flag |= init_sequence[i].done_flag;
+ }
+
+ writel(init_flag, &phy->pir);
+
+ do {
+ if (--timeout < 0) {
+#ifndef CONFIG_SPL_BUILD
+ printf("%s: error: timeout during DDR training\n",
+ __func__);
+#endif
+ return -1;
+ }
+ udelay(1);
+ pgsr0 = readl(&phy->pgsr[0]);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ if (pgsr0 & init_sequence[i].err_flag) {
+#ifndef CONFIG_SPL_BUILD
+ printf("%s: error: %s failed\n", __func__,
+ init_sequence[i].description);
+#endif
+ return -1;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
#define REG DEVICE /* IO Register: Device */
#define DDR DEVICE /* DDR SDRAM: Device */
-#ifdef CONFIG_SPL_BUILD
#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20))
-#else
-#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SYS_TEXT_BASE) >> 20))
-#endif
#define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20))
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8253c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a82dbc0, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000800, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+}
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
+#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+ ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+ ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000000, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+}
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
+#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+ void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+ ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
+ ddrphy_init(phy0_1, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_1, 1);
+ ddrphy_training(phy0_1);
+
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+ ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 0);
+ ddrphy_training(phy1_0);
+
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
+ ddrphy_init(phy1_1, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_1, 1);
+ ddrphy_training(phy1_1);
+
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x00000000, &phy->mr3);
+#else
+ writel(0x00000800, &phy->mr3);
+#endif
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+}
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
+#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+ ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+ ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
obj-y += clock.o
obj-y += lowlevel_init.o
obj-y += pinmux-common.o
+obj-y += powergate.o
+obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
obj-$(CONFIG_TEGRA124) += vpr.o
--- /dev/null
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/io.h>
+#include <asm/types.h>
+
+#include <asm/arch/powergate.h>
+#include <asm/arch/tegra.h>
+
+#define PWRGATE_TOGGLE 0x30
+#define PWRGATE_TOGGLE_START (1 << 8)
+
+#define REMOVE_CLAMPING 0x34
+
+#define PWRGATE_STATUS 0x38
+
+static int tegra_powergate_set(enum tegra_powergate id, bool state)
+{
+ u32 value, mask = state ? (1 << id) : 0, old_mask;
+ unsigned long start, timeout = 25;
+
+ value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ old_mask = value & (1 << id);
+
+ if (mask == old_mask)
+ return 0;
+
+ writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
+
+ start = get_timer(0);
+
+ while (get_timer(start) < timeout) {
+ value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ if ((value & (1 << id)) == mask)
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int tegra_powergate_power_on(enum tegra_powergate id)
+{
+ return tegra_powergate_set(id, true);
+}
+
+int tegra_powergate_power_off(enum tegra_powergate id)
+{
+ return tegra_powergate_set(id, false);
+}
+
+static int tegra_powergate_remove_clamping(enum tegra_powergate id)
+{
+ unsigned long value;
+
+ /*
+ * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
+ * partitions reversed. This was originally introduced on Tegra20 but
+ * has since been carried forward for backwards-compatibility.
+ */
+ if (id == TEGRA_POWERGATE_VDEC)
+ value = 1 << TEGRA_POWERGATE_PCIE;
+ else if (id == TEGRA_POWERGATE_PCIE)
+ value = 1 << TEGRA_POWERGATE_VDEC;
+ else
+ value = 1 << id;
+
+ writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
+
+ return 0;
+}
+
+int tegra_powergate_sequence_power_up(enum tegra_powergate id,
+ enum periph_id periph)
+{
+ int err;
+
+ reset_set_enable(periph, 1);
+
+ err = tegra_powergate_power_on(id);
+ if (err < 0)
+ return err;
+
+ clock_enable(periph);
+
+ udelay(10);
+
+ err = tegra_powergate_remove_clamping(id);
+ if (err < 0)
+ return err;
+
+ udelay(10);
+
+ reset_set_enable(periph, 0);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/arch-tegra/xusb-padctl.h>
+
+struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type)
+{
+ return NULL;
+}
+
+int __weak tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
+{
+ return -ENOSYS;
+}
+
+int __weak tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
+{
+ return -ENOSYS;
+}
+
+int __weak tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
+{
+ return -ENOSYS;
+}
+
+int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
+{
+ return -ENOSYS;
+}
+
+void __weak tegra_xusb_padctl_init(const void *fdt)
+{
+}
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
+obj-y += xusb-padctl.o
writel(val, &sysctr->cntcr);
debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
}
+
+#define PLLE_SS_CNTL 0x68
+#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
+#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
+#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
+#define PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define PLLE_BASE_ENABLE (1 << 30)
+#define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
+#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
+#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
+#define PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define PLLE_MISC_PTS (1 << 8)
+#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
+#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
+
+#define PLLE_AUX 0x48c
+#define PLLE_AUX_SEQ_ENABLE (1 << 24)
+#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
+
+int tegra_plle_enable(void)
+{
+ unsigned int m = 1, n = 200, cpcon = 13;
+ u32 value;
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value &= ~PLLE_BASE_LOCK_OVERRIDE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
+ value |= PLLE_AUX_ENABLE_SWCTL;
+ value &= ~PLLE_AUX_SEQ_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
+
+ udelay(1);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ value |= PLLE_MISC_IDDQ_SWCTL;
+ value &= ~PLLE_MISC_IDDQ_OVERRIDE;
+ value |= PLLE_MISC_LOCK_ENABLE;
+ value |= PLLE_MISC_PTS;
+ value |= PLLE_MISC_VREG_BG_CTRL(3);
+ value |= PLLE_MISC_VREG_CTRL(2);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+ udelay(5);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+ PLLE_SS_CNTL_BYPASS_SS;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value &= ~PLLE_BASE_PLDIV_CML(0xf);
+ value &= ~PLLE_BASE_NDIV(0xff);
+ value &= ~PLLE_BASE_MDIV(0xff);
+ value |= PLLE_BASE_PLDIV_CML(cpcon);
+ value |= PLLE_BASE_NDIV(n);
+ value |= PLLE_BASE_MDIV(m);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ udelay(1);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value |= PLLE_BASE_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ /* wait for lock */
+ udelay(300);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_SSCINVERT;
+ value &= ~PLLE_SS_CNTL_SSCCENTER;
+
+ value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
+ value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+ value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+
+ value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
+ value |= PLLE_SS_CNTL_SSCINC(0x01);
+ value |= PLLE_SS_CNTL_SSCMAX(0x25);
+
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_SSCBYP;
+ value &= ~PLLE_SS_CNTL_BYPASS_SS;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ udelay(1);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_INTERP_RESET;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ udelay(1);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/xusb-padctl.h>
+
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
+#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
+
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
+
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
+
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
+
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
+
+enum tegra124_function {
+ TEGRA124_FUNC_SNPS,
+ TEGRA124_FUNC_XUSB,
+ TEGRA124_FUNC_UART,
+ TEGRA124_FUNC_PCIE,
+ TEGRA124_FUNC_USB3,
+ TEGRA124_FUNC_SATA,
+ TEGRA124_FUNC_RSVD,
+};
+
+static const char *const tegra124_functions[] = {
+ "snps",
+ "xusb",
+ "uart",
+ "pcie",
+ "usb3",
+ "sata",
+ "rsvd",
+};
+
+static const unsigned int tegra124_otg_functions[] = {
+ TEGRA124_FUNC_SNPS,
+ TEGRA124_FUNC_XUSB,
+ TEGRA124_FUNC_UART,
+ TEGRA124_FUNC_RSVD,
+};
+
+static const unsigned int tegra124_usb_functions[] = {
+ TEGRA124_FUNC_SNPS,
+ TEGRA124_FUNC_XUSB,
+};
+
+static const unsigned int tegra124_pci_functions[] = {
+ TEGRA124_FUNC_PCIE,
+ TEGRA124_FUNC_USB3,
+ TEGRA124_FUNC_SATA,
+ TEGRA124_FUNC_RSVD,
+};
+
+struct tegra_xusb_padctl_lane {
+ const char *name;
+
+ unsigned int offset;
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int iddq;
+
+ const unsigned int *funcs;
+ unsigned int num_funcs;
+};
+
+#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
+ { \
+ .name = _name, \
+ .offset = _offset, \
+ .shift = _shift, \
+ .mask = _mask, \
+ .iddq = _iddq, \
+ .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
+ .funcs = tegra124_##_funcs##_functions, \
+ }
+
+static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
+ TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
+ TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
+ TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
+ TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
+ TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
+ TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
+ TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
+ TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
+ TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
+ TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
+ TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
+ TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
+};
+
+struct tegra_xusb_phy_ops {
+ int (*prepare)(struct tegra_xusb_phy *phy);
+ int (*enable)(struct tegra_xusb_phy *phy);
+ int (*disable)(struct tegra_xusb_phy *phy);
+ int (*unprepare)(struct tegra_xusb_phy *phy);
+};
+
+struct tegra_xusb_phy {
+ const struct tegra_xusb_phy_ops *ops;
+
+ struct tegra_xusb_padctl *padctl;
+};
+
+struct tegra_xusb_padctl_pin {
+ const struct tegra_xusb_padctl_lane *lane;
+
+ unsigned int func;
+ int iddq;
+};
+
+#define MAX_GROUPS 3
+#define MAX_PINS 6
+
+struct tegra_xusb_padctl_group {
+ const char *name;
+
+ const char *pins[MAX_PINS];
+ unsigned int num_pins;
+
+ const char *func;
+ int iddq;
+};
+
+struct tegra_xusb_padctl_config {
+ const char *name;
+
+ struct tegra_xusb_padctl_group groups[MAX_GROUPS];
+ unsigned int num_groups;
+};
+
+struct tegra_xusb_padctl {
+ struct fdt_resource regs;
+
+ unsigned int enable;
+
+ struct tegra_xusb_phy phys[2];
+
+ const struct tegra_xusb_padctl_lane *lanes;
+ unsigned int num_lanes;
+
+ const char *const *functions;
+ unsigned int num_functions;
+
+ struct tegra_xusb_padctl_config config;
+};
+
+static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
+ unsigned long offset)
+{
+ return readl(padctl->regs.start + offset);
+}
+
+static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
+ u32 value, unsigned long offset)
+{
+ writel(value, padctl->regs.start + offset);
+}
+
+static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
+{
+ u32 value;
+
+ if (padctl->enable++ > 0)
+ return 0;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ return 0;
+}
+
+static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
+{
+ u32 value;
+
+ if (padctl->enable == 0) {
+ error("tegra-xusb-padctl: unbalanced enable/disable");
+ return 0;
+ }
+
+ if (--padctl->enable > 0)
+ return 0;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ return 0;
+}
+
+static int phy_prepare(struct tegra_xusb_phy *phy)
+{
+ return tegra_xusb_padctl_enable(phy->padctl);
+}
+
+static int phy_unprepare(struct tegra_xusb_phy *phy)
+{
+ return tegra_xusb_padctl_disable(phy->padctl);
+}
+
+static int pcie_phy_enable(struct tegra_xusb_phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy->padctl;
+ int err = -ETIMEDOUT;
+ unsigned long start;
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
+ value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
+ XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
+ XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+ start = get_timer(0);
+
+ while (get_timer(start) < 50) {
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
+ err = 0;
+ break;
+ }
+ }
+
+ return err;
+}
+
+static int pcie_phy_disable(struct tegra_xusb_phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy->padctl;
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+ return 0;
+}
+
+static int sata_phy_enable(struct tegra_xusb_phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy->padctl;
+ int err = -ETIMEDOUT;
+ unsigned long start;
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
+ value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ start = get_timer(0);
+
+ while (get_timer(start) < 50) {
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
+ err = 0;
+ break;
+ }
+ }
+
+ return err;
+}
+
+static int sata_phy_disable(struct tegra_xusb_phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy->padctl;
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+ value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
+ value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+
+ return 0;
+}
+
+static const struct tegra_xusb_phy_ops pcie_phy_ops = {
+ .prepare = phy_prepare,
+ .enable = pcie_phy_enable,
+ .disable = pcie_phy_disable,
+ .unprepare = phy_unprepare,
+};
+
+static const struct tegra_xusb_phy_ops sata_phy_ops = {
+ .prepare = phy_prepare,
+ .enable = sata_phy_enable,
+ .disable = sata_phy_disable,
+ .unprepare = phy_unprepare,
+};
+
+static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
+ .phys = {
+ [0] = {
+ .ops = &pcie_phy_ops,
+ },
+ [1] = {
+ .ops = &sata_phy_ops,
+ },
+ },
+};
+
+static const struct tegra_xusb_padctl_lane *
+tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
+{
+ unsigned int i;
+
+ for (i = 0; i < padctl->num_lanes; i++)
+ if (strcmp(name, padctl->lanes[i].name) == 0)
+ return &padctl->lanes[i];
+
+ return NULL;
+}
+
+static int
+tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
+ struct tegra_xusb_padctl_group *group,
+ const void *fdt, int node)
+{
+ unsigned int i;
+ int len, err;
+
+ group->name = fdt_get_name(fdt, node, &len);
+
+ len = fdt_count_strings(fdt, node, "nvidia,lanes");
+ if (len < 0) {
+ error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property");
+ return -EINVAL;
+ }
+
+ group->num_pins = len;
+
+ for (i = 0; i < group->num_pins; i++) {
+ err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
+ &group->pins[i]);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property");
+ return -EINVAL;
+ }
+ }
+
+ group->num_pins = len;
+
+ err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property");
+ return -EINVAL;
+ }
+
+ group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
+
+ return 0;
+}
+
+static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
+ const char *name)
+{
+ unsigned int i;
+
+ for (i = 0; i < padctl->num_functions; i++)
+ if (strcmp(name, padctl->functions[i]) == 0)
+ return i;
+
+ return -ENOENT;
+}
+
+static int
+tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
+ const struct tegra_xusb_padctl_lane *lane,
+ const char *name)
+{
+ unsigned int i;
+ int func;
+
+ func = tegra_xusb_padctl_find_function(padctl, name);
+ if (func < 0)
+ return func;
+
+ for (i = 0; i < lane->num_funcs; i++)
+ if (lane->funcs[i] == func)
+ return i;
+
+ return -ENOENT;
+}
+
+static int
+tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
+ const struct tegra_xusb_padctl_group *group)
+{
+ unsigned int i;
+
+ for (i = 0; i < group->num_pins; i++) {
+ const struct tegra_xusb_padctl_lane *lane;
+ unsigned int func;
+ u32 value;
+
+ lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
+ if (!lane) {
+ error("tegra-xusb-padctl: no lane for pin %s",
+ group->pins[i]);
+ continue;
+ }
+
+ func = tegra_xusb_padctl_lane_find_function(padctl, lane,
+ group->func);
+ if (func < 0) {
+ error("tegra-xusb-padctl: function %s invalid for lane %s: %d",
+ group->func, lane->name, func);
+ continue;
+ }
+
+ value = padctl_readl(padctl, lane->offset);
+
+ /* set pin function */
+ value &= ~(lane->mask << lane->shift);
+ value |= func << lane->shift;
+
+ /*
+ * Set IDDQ if supported on the lane and specified in the
+ * configuration.
+ */
+ if (lane->iddq > 0 && group->iddq >= 0) {
+ if (group->iddq != 0)
+ value &= ~(1 << lane->iddq);
+ else
+ value |= 1 << lane->iddq;
+ }
+
+ padctl_writel(padctl, value, lane->offset);
+ }
+
+ return 0;
+}
+
+static int
+tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
+ struct tegra_xusb_padctl_config *config)
+{
+ unsigned int i;
+
+ for (i = 0; i < config->num_groups; i++) {
+ const struct tegra_xusb_padctl_group *group;
+ int err;
+
+ group = &config->groups[i];
+
+ err = tegra_xusb_padctl_group_apply(padctl, group);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to apply group %s: %d",
+ group->name, err);
+ continue;
+ }
+ }
+
+ return 0;
+}
+
+static int
+tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
+ struct tegra_xusb_padctl_config *config,
+ const void *fdt, int node)
+{
+ int subnode;
+
+ config->name = fdt_get_name(fdt, node, NULL);
+
+ fdt_for_each_subnode(fdt, subnode, node) {
+ struct tegra_xusb_padctl_group *group;
+ int err;
+
+ group = &config->groups[config->num_groups];
+
+ err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
+ subnode);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to parse group %s",
+ group->name);
+ return err;
+ }
+
+ config->num_groups++;
+ }
+
+ return 0;
+}
+
+static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
+ const void *fdt, int node)
+{
+ int subnode, err;
+
+ err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
+ if (err < 0) {
+ error("tegra-xusb-padctl: registers not found");
+ return err;
+ }
+
+ fdt_for_each_subnode(fdt, subnode, node) {
+ struct tegra_xusb_padctl_config *config = &padctl->config;
+
+ err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
+ subnode);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to parse entry %s: %d",
+ config->name, err);
+ continue;
+ }
+ }
+
+ return 0;
+}
+
+static int process_nodes(const void *fdt, int nodes[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++) {
+ enum fdt_compat_id id;
+ int err;
+
+ if (!fdtdec_get_is_enabled(fdt, nodes[i]))
+ continue;
+
+ id = fdtdec_lookup(fdt, nodes[i]);
+ switch (id) {
+ case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
+ break;
+
+ default:
+ error("tegra-xusb-padctl: unsupported compatible: %s",
+ fdtdec_get_compatible(id));
+ continue;
+ }
+
+ padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
+ padctl->lanes = tegra124_lanes;
+
+ padctl->num_functions = ARRAY_SIZE(tegra124_functions);
+ padctl->functions = tegra124_functions;
+
+ err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to parse DT: %d",
+ err);
+ continue;
+ }
+
+ /* deassert XUSB padctl reset */
+ reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
+
+ err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to apply pinmux: %d",
+ err);
+ continue;
+ }
+
+ /* only a single instance is supported */
+ break;
+ }
+
+ return 0;
+}
+
+struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
+{
+ struct tegra_xusb_phy *phy = NULL;
+
+ switch (type) {
+ case TEGRA_XUSB_PADCTL_PCIE:
+ phy = &padctl->phys[0];
+ phy->padctl = padctl;
+ break;
+
+ case TEGRA_XUSB_PADCTL_SATA:
+ phy = &padctl->phys[1];
+ phy->padctl = padctl;
+ break;
+ }
+
+ return phy;
+}
+
+int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->prepare)
+ return phy->ops->prepare(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->enable)
+ return phy->ops->enable(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->disable)
+ return phy->ops->disable(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->unprepare)
+ return phy->ops->unprepare(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+void tegra_xusb_padctl_init(const void *fdt)
+{
+ int count, nodes[1];
+
+ count = fdtdec_find_aliases_for_id(fdt, "padctl",
+ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+ nodes, ARRAY_SIZE(nodes));
+ if (process_nodes(fdt, nodes, count))
+ return;
+}
/* Tegra20 Clock control functions */
#include <common.h>
+#include <errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
/* 0x48 */
NONE(AFI),
NONE(CORESIGHT),
- NONE(RESERVED74),
+ NONE(PCIEXCLK),
NONE(AVPUCQ),
NONE(RESERVED76),
NONE(RESERVED77),
case PERIPH_ID_RESERVED30:
case PERIPH_ID_RESERVED35:
case PERIPH_ID_RESERVED56:
- case PERIPH_ID_RESERVED74:
+ case PERIPH_ID_PCIEXCLK:
case PERIPH_ID_RESERVED76:
case PERIPH_ID_RESERVED77:
case PERIPH_ID_RESERVED78:
void arch_timer_init(void)
{
}
+
+#define PMC_SATA_PWRGT 0x1ac
+#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
+#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
+
+#define PLLE_SS_CNTL 0x68
+#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
+#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define PLLE_BASE_ENABLE_CML (1 << 31)
+#define PLLE_BASE_ENABLE (1 << 30)
+#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
+#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
+#define PLLE_MISC_PLL_READY (1 << 15)
+#define PLLE_MISC_LOCK (1 << 11)
+#define PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
+
+static int tegra_plle_train(void)
+{
+ unsigned int timeout = 2000;
+ unsigned long value;
+
+ value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+ value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+ writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+ value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+ value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
+ writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+ value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+ value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+ writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+ do {
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ if (value & PLLE_MISC_PLL_READY)
+ break;
+
+ udelay(100);
+ } while (--timeout);
+
+ if (timeout == 0) {
+ error("timeout waiting for PLLE to become ready");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+int tegra_plle_enable(void)
+{
+ unsigned int timeout = 1000;
+ u32 value;
+ int err;
+
+ /* disable PLLE clock */
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value &= ~PLLE_BASE_ENABLE_CML;
+ value &= ~PLLE_BASE_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ /* clear lock enable and setup field */
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ value &= ~PLLE_MISC_LOCK_ENABLE;
+ value &= ~PLLE_MISC_SETUP_BASE(0xffff);
+ value &= ~PLLE_MISC_SETUP_EXT(0x3);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ if ((value & PLLE_MISC_PLL_READY) == 0) {
+ err = tegra_plle_train();
+ if (err < 0) {
+ error("failed to train PLLE: %d", err);
+ return err;
+ }
+ }
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ value |= PLLE_MISC_SETUP_BASE(0x7);
+ value |= PLLE_MISC_LOCK_ENABLE;
+ value |= PLLE_MISC_SETUP_EXT(0);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+ PLLE_SS_CNTL_BYPASS_SS;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ do {
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ if (value & PLLE_MISC_LOCK)
+ break;
+
+ udelay(2);
+ } while (--timeout);
+
+ if (timeout == 0) {
+ error("timeout waiting for PLLE to lock");
+ return -ETIMEDOUT;
+ }
+
+ udelay(50);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
+ value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
+
+ value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+ value |= PLLE_SS_CNTL_SSCINC(0x01);
+
+ value &= ~PLLE_SS_CNTL_SSCBYP;
+ value &= ~PLLE_SS_CNTL_INTERP_RESET;
+ value &= ~PLLE_SS_CNTL_BYPASS_SS;
+
+ value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+ value |= PLLE_SS_CNTL_SSCMAX(0x24);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ return 0;
+}
/* Tegra30 Clock control functions */
#include <common.h>
+#include <errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
case PERIPH_ID_RESERVED43:
case PERIPH_ID_RESERVED45:
case PERIPH_ID_RESERVED56:
+ case PERIPH_ID_PCIEXCLK:
case PERIPH_ID_RESERVED76:
case PERIPH_ID_RESERVED77:
case PERIPH_ID_RESERVED78:
void arch_timer_init(void)
{
}
+
+#define PMC_SATA_PWRGT 0x1ac
+#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
+#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
+
+#define PLLE_SS_CNTL 0x68
+#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
+#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define PLLE_BASE_ENABLE_CML (1 << 31)
+#define PLLE_BASE_ENABLE (1 << 30)
+#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
+#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
+#define PLLE_MISC_PLL_READY (1 << 15)
+#define PLLE_MISC_LOCK (1 << 11)
+#define PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
+
+static int tegra_plle_train(void)
+{
+ unsigned int timeout = 2000;
+ unsigned long value;
+
+ value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+ value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+ writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+ value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+ value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
+ writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+ value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+ value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+ writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+ do {
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ if (value & PLLE_MISC_PLL_READY)
+ break;
+
+ udelay(100);
+ } while (--timeout);
+
+ if (timeout == 0) {
+ error("timeout waiting for PLLE to become ready");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+int tegra_plle_enable(void)
+{
+ unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
+ u32 value;
+ int err;
+
+ /* disable PLLE clock */
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value &= ~PLLE_BASE_ENABLE_CML;
+ value &= ~PLLE_BASE_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ /* clear lock enable and setup field */
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ value &= ~PLLE_MISC_LOCK_ENABLE;
+ value &= ~PLLE_MISC_SETUP_BASE(0xffff);
+ value &= ~PLLE_MISC_SETUP_EXT(0x3);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ if ((value & PLLE_MISC_PLL_READY) == 0) {
+ err = tegra_plle_train();
+ if (err < 0) {
+ error("failed to train PLLE: %d", err);
+ return err;
+ }
+ }
+
+ /* configure PLLE */
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ value &= ~PLLE_BASE_PLDIV_CML(0x0f);
+ value |= PLLE_BASE_PLDIV_CML(cpcon);
+
+ value &= ~PLLE_BASE_PLDIV(0x3f);
+ value |= PLLE_BASE_PLDIV(p);
+
+ value &= ~PLLE_BASE_NDIV(0xff);
+ value |= PLLE_BASE_NDIV(n);
+
+ value &= ~PLLE_BASE_MDIV(0xff);
+ value |= PLLE_BASE_MDIV(m);
+
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ value |= PLLE_MISC_SETUP_BASE(0x7);
+ value |= PLLE_MISC_LOCK_ENABLE;
+ value |= PLLE_MISC_SETUP_EXT(0);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+ PLLE_SS_CNTL_BYPASS_SS;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ do {
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ if (value & PLLE_MISC_LOCK)
+ break;
+
+ udelay(2);
+ } while (--timeout);
+
+ if (timeout == 0) {
+ error("timeout waiting for PLLE to lock");
+ return -ETIMEDOUT;
+ }
+
+ udelay(50);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
+ value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
+
+ value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+ value |= PLLE_SS_CNTL_SSCINC(0x01);
+
+ value &= ~PLLE_SS_CNTL_SSCBYP;
+ value &= ~PLLE_SS_CNTL_INTERP_RESET;
+ value &= ~PLLE_SS_CNTL_BYPASS_SS;
+
+ value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+ value |= PLLE_SS_CNTL_SSCMAX(0x24);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ return 0;
+}
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
+ exynos5800-peach-pi.dtb \
+ exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
--- /dev/null
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "exynos54xx.dtsi"
+
+/ {
+ model = "Odroid XU3 based on EXYNOS5422";
+ compatible = "samsung,odroidxu3", "samsung,exynos5";
+
+ aliases {
+ serial0 = "/serial@12C00000";
+ console = "/serial@12C20000";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000
+ 0x50000000 0x10000000
+ 0x60000000 0x10000000
+ 0x70000000 0x10000000
+ 0x80000000 0x10000000
+ 0x90000000 0x10000000
+ 0xa0000000 0x10000000
+ 0xb0000000 0xea00000>;
+ };
+
+ ehci@12110000 {
+ samsung,vbus-gpio = <&gpio 0x66 0>; /* X26 */
+ };
+
+ serial@12C20000 {
+ status="okay";
+ };
+
+ mmc@12200000 {
+ fifoth_val = <0x201f0020>;
+ };
+
+ mmc@12220000 {
+ fifoth_val = <0x201f0020>;
+ };
+};
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
-
- edp-lvds-bridge@48 {
- compatible = "parade,ps8625";
- reg = <0x48>;
- };
};
sound@3830000 {
reg = <0x80000000 0x80000000>;
};
+ pcie-controller@01003000 {
+ status = "okay";
+
+ avddio-pex-supply = <&vdd_1v05_run>;
+ dvddio-pex-supply = <&vdd_1v05_run>;
+ avdd-pex-pll-supply = <&vdd_1v05_run>;
+ hvdd-pex-supply = <&vdd_3v3_lp0>;
+ hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+ vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
+ avdd-pll-erefe-supply = <&avdd_1v05_run>;
+
+ pci@1,0 {
+ status = "okay";
+ };
+
+ pci@2,0 {
+ status = "okay";
+ };
+ };
+
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <100000>;
};
+ /* Expansion PWR_I2C_*, on-board components */
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
+
+ pmic: pmic@40 {
+ compatible = "ams,as3722";
+ reg = <0x40>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ ams,system-power-controller;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&as3722_default>;
+
+ as3722_default: pinmux {
+ gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ gpio1_2_4_7 {
+ pins = "gpio1", "gpio2", "gpio4", "gpio7";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio3_5_6 {
+ pins = "gpio3", "gpio5", "gpio6";
+ bias-high-impedance;
+ };
+ };
+
+ regulators {
+ vsup-sd2-supply = <&vdd_5v0_sys>;
+ vsup-sd3-supply = <&vdd_5v0_sys>;
+ vsup-sd4-supply = <&vdd_5v0_sys>;
+ vsup-sd5-supply = <&vdd_5v0_sys>;
+ vin-ldo0-supply = <&vdd_1v35_lp0>;
+ vin-ldo1-6-supply = <&vdd_3v3_run>;
+ vin-ldo2-5-7-supply = <&vddio_1v8>;
+ vin-ldo3-4-supply = <&vdd_3v3_sys>;
+ vin-ldo9-10-supply = <&vdd_5v0_sys>;
+ vin-ldo11-supply = <&vdd_3v3_run>;
+
+ sd0 {
+ regulator-name = "+VDD_CPU_AP";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <2>;
+ };
+
+ sd1 {
+ regulator-name = "+VDD_CORE";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microamp = <2500000>;
+ regulator-max-microamp = <2500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <1>;
+ };
+
+ vdd_1v35_lp0: sd2 {
+ regulator-name = "+1.35V_LP0(sd2)";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sd3 {
+ regulator-name = "+1.35V_LP0(sd3)";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v05_run: sd4 {
+ regulator-name = "+1.05V_RUN";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vddio_1v8: sd5 {
+ regulator-name = "+1.8V_VDDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_gpu: sd6 {
+ regulator-name = "+VDD_GPU_AP";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ avdd_1v05_run: ldo0 {
+ regulator-name = "+1.05V_RUN_AVDD";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,ext-control = <1>;
+ };
+
+ ldo1 {
+ regulator-name = "+1.8V_RUN_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo2 {
+ regulator-name = "+1.2V_GEN_AVDD";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3 {
+ regulator-name = "+1.05V_LP0_VDD_RTC";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,enable-tracking;
+ };
+
+ ldo4 {
+ regulator-name = "+2.8V_RUN_CAM";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo5 {
+ regulator-name = "+1.2V_RUN_CAM_FRONT";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vddio_sdmmc3: ldo6 {
+ regulator-name = "+VDDIO_SDMMC3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo7 {
+ regulator-name = "+1.05V_RUN_CAM_REAR";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo9 {
+ regulator-name = "+3.3V_RUN_TOUCH";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo10 {
+ regulator-name = "+2.8V_RUN_CAM_AF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo11 {
+ regulator-name = "+1.8V_RUN_VPP_FUSE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
};
i2c@7000d100 {
spi-max-frequency = <25000000>;
};
+ padctl@7009f000 {
+ pinctrl-0 = <&padctl_default>;
+ pinctrl-names = "default";
+
+ padctl_default: pinmux {
+ usb3 {
+ nvidia,lanes = "pcie-0", "pcie-1";
+ nvidia,function = "usb3";
+ nvidia,iddq = <0>;
+ };
+
+ pcie {
+ nvidia,lanes = "pcie-2", "pcie-3",
+ "pcie-4";
+ nvidia,function = "pcie";
+ nvidia,iddq = <0>;
+ };
+
+ sata {
+ nvidia,lanes = "sata-0";
+ nvidia,function = "sata";
+ nvidia,iddq = <0>;
+ };
+ };
+ };
+
sdhci@700b0400 {
status = "okay";
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
};
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_mux: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+VDD_MUX";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "+5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
+
+ vdd_3v3_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "+3.3V_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
+
+ vdd_3v3_run: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "+3.3V_RUN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_3v3_hdmi: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3_run>;
+ };
+
+ vdd_usb1_vbus: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "+USB0_VBUS_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_usb3_vbus: regulator@8 {
+ compatible = "regulator-fixed";
+ reg = <8>;
+ regulator-name = "+5V_USB_HS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_3v3_lp0: regulator@10 {
+ compatible = "regulator-fixed";
+ reg = <10>;
+ regulator-name = "+3.3V_LP0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_hdmi_pll: regulator@11 {
+ compatible = "regulator-fixed";
+ reg = <11>;
+ regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ vin-supply = <&vdd_1v05_run>;
+ };
+
+ vdd_5v0_hdmi: regulator@12 {
+ compatible = "regulator-fixed";
+ reg = <12>;
+ regulator-name = "+5V_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ /* Molex power connector */
+ vdd_5v0_sata: regulator@13 {
+ compatible = "regulator-fixed";
+ reg = <13>;
+ regulator-name = "+5V_SATA";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_12v0_sata: regulator@14 {
+ compatible = "regulator-fixed";
+ reg = <14>;
+ regulator-name = "+12V_SATA";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_mux>;
+ };
+ };
};
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra124";
+ interrupt-parent = <&gic>;
+
+ pcie-controller@01003000 {
+ compatible = "nvidia,tegra124-pcie";
+ device_type = "pci";
+ reg = <0x01003000 0x00000800 /* PADS registers */
+ 0x01003800 0x00000800 /* AFI registers */
+ 0x02000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
+ 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
+ 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
+ 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
+ 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+
+ clocks = <&tegra_car TEGRA124_CLK_PCIE>,
+ <&tegra_car TEGRA124_CLK_AFI>,
+ <&tegra_car TEGRA124_CLK_PLL_E>,
+ <&tegra_car TEGRA124_CLK_CML0>;
+ clock-names = "pex", "afi", "pll_e", "cml";
+ resets = <&tegra_car 70>,
+ <&tegra_car 72>,
+ <&tegra_car 74>;
+ reset-names = "pex", "afi", "pcie_x";
+ status = "disabled";
+
+ phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
+ phy-names = "pcie";
+
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <1>;
+ };
+ };
+
+ gic: interrupt-controller@50041000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x50041000 0x1000>,
+ <0x50042000 0x2000>,
+ <0x50044000 0x2000>,
+ <0x50046000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
tegra_car: clock@60006000 {
compatible = "nvidia,tegra124-car";
clocks = <&tegra_car 105>;
};
+ padctl: padctl@7009f000 {
+ compatible = "nvidia,tegra124-xusb-padctl";
+ reg = <0x7009f000 0x1000>;
+ resets = <&tegra_car 142>;
+ reset-names = "padctl";
+
+ #phy-cells = <1>;
+ };
+
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0000 0x200>;
status = "disabled";
};
+ pcie-controller@80003000 {
+ status = "okay";
+
+ avdd-pex-supply = <&pci_vdd_reg>;
+ vdd-pex-supply = <&pci_vdd_reg>;
+ avdd-pex-pll-supply = <&pci_vdd_reg>;
+ avdd-plle-supply = <&pci_vdd_reg>;
+ vddio-pex-clk-supply = <&pci_clk_reg>;
+
+ pci@1,0 {
+ status = "okay";
+ };
+ };
+
usb@c5000000 {
nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
};
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
bus-width = <4>;
};
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_vdd_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ hdmi_pll_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vbus_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pci_clk_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "pci_clk";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ pci_vdd_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "pci_vdd";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ };
+ };
+
};
reg = <0x7000f400 0x200>;
};
+ pcie-controller@80003000 {
+ compatible = "nvidia,tegra20-pcie";
+ device_type = "pci";
+ reg = <0x80003000 0x00000800 /* PADS registers */
+ 0x80003800 0x00000200 /* AFI registers */
+ 0x90000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
+ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
+ 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
+ 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
+ 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
+
+ clocks = <&tegra_car TEGRA20_CLK_PEX>,
+ <&tegra_car TEGRA20_CLK_AFI>,
+ <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
+ <&tegra_car TEGRA20_CLK_PLL_E>;
+ clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+ status = "disabled";
+
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+ };
+
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
reg = <0x80000000 0x7ff00000>;
};
+ pcie-controller@00003000 {
+ status = "okay";
+
+ avdd-pexa-supply = <&ldo1_reg>;
+ vdd-pexa-supply = <&ldo1_reg>;
+ avdd-pexb-supply = <&ldo1_reg>;
+ vdd-pexb-supply = <&ldo1_reg>;
+ avdd-pex-pll-supply = <&ldo1_reg>;
+ avdd-plle-supply = <&ldo1_reg>;
+ vddio-pex-ctl-supply = <&sys_3v3_reg>;
+ hvdd-pex-supply = <&sys_3v3_pexs_reg>;
+
+ pci@1,0 {
+ status = "okay";
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@2,0 {
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@3,0 {
+ status = "okay";
+ nvidia,num-lanes = <2>;
+ };
+ };
+
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
+
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_5v_in_reg>;
+ vcc2-supply = <&vdd_5v_in_reg>;
+ vcc3-supply = <&vio_reg>;
+ vcc4-supply = <&vdd_5v_in_reg>;
+ vcc5-supply = <&vdd_5v_in_reg>;
+ vcc6-supply = <&vdd2_reg>;
+ vcc7-supply = <&vdd_5v_in_reg>;
+ vccio-supply = <&vdd_5v_in_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd1_reg: vdd1 {
+ regulator-name = "vddio_ddr_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd2_reg: vdd2 {
+ regulator-name = "vdd_1v5_gen";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vddctrl_reg: vddctrl {
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ vio_reg: vio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "vdd_pexa,vdd_pexb";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "vdd_sata,avdd_plle";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ /* LDO3 is not connected to anything */
+
+ ldo4_reg: ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "vddio_sdmmc,avdd_vdac";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+ };
+ };
};
spi@7000da00 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
status = "okay";
};
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v_in_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v_in";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ chargepump_5v_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "chargepump_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ ddr_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ vdd_5v_sata_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd_5v_sata";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ usb1_vbus_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ usb3_vbus_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ sys_3v3_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "sys_3v3,vdd_3v3_alw";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
+
+ sys_3v3_pexs_reg: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "sys_3v3_pexs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_5v0_hdmi: regulator@8 {
+ compatible = "regulator-fixed";
+ reg = <8>;
+ regulator-name = "+VDD_5V_HDMI";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&sys_3v3_reg>;
+ };
+ };
};
reg = <0x80000000 0x40000000>;
};
+ pcie-controller@00003000 {
+ status = "okay";
+
+ /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
+ avdd-pexb-supply = <&ldo1_reg>;
+ vdd-pexb-supply = <&ldo1_reg>;
+ avdd-pex-pll-supply = <&ldo1_reg>;
+ hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
+ vddio-pex-ctl-supply = <&sys_3v3_reg>;
+ avdd-plle-supply = <&ldo2_reg>;
+
+ pci@1,0 {
+ nvidia,num-lanes = <4>;
+ };
+
+ pci@2,0 {
+ nvidia,num-lanes = <1>;
+ };
+
+ pci@3,0 {
+ status = "okay";
+ nvidia,num-lanes = <1>;
+ };
+ };
+
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
+
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_ac_bat_reg>;
+ vcc2-supply = <&vdd_ac_bat_reg>;
+ vcc3-supply = <&vio_reg>;
+ vcc4-supply = <&vdd_5v0_reg>;
+ vcc5-supply = <&vdd_ac_bat_reg>;
+ vcc6-supply = <&vdd2_reg>;
+ vcc7-supply = <&vdd_ac_bat_reg>;
+ vccio-supply = <&vdd_ac_bat_reg>;
+
+ regulators {
+ vdd1_reg: vdd1 {
+ regulator-name = "vddio_ddr_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd2_reg: vdd2 {
+ regulator-name = "vdd_1v5_gen";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vddctrl_reg: vddctrl {
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ vio_reg: vio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "vdd_pexa,vdd_pexb";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "vdd_sata,avdd_plle";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ /* LDO3 is not connected to anything */
+
+ ldo4_reg: ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "vddio_sdmmc,avdd_vdac";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+ };
+ };
};
spi@7000da00 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
status = "okay";
};
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_ac_bat_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_ac_bat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ cam_1v8_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "cam_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vio_reg>;
+ };
+
+ cp_5v_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "cp_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ emmc_3v3_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "emmc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ modem_3v3_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "modem_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
+ };
+
+ pex_hvdd_3v3_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "pex_hvdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam1_ldo_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "vdd_cam1_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam2_ldo_reg: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "vdd_cam2_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam3_ldo_reg: regulator@8 {
+ compatible = "regulator-fixed";
+ reg = <8>;
+ regulator-name = "vdd_cam3_ldo";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_com_reg: regulator@9 {
+ compatible = "regulator-fixed";
+ reg = <9>;
+ regulator-name = "vdd_com";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_fuse_3v3_reg: regulator@10 {
+ compatible = "regulator-fixed";
+ reg = <10>;
+ regulator-name = "vdd_fuse_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_pnl1_reg: regulator@11 {
+ compatible = "regulator-fixed";
+ reg = <11>;
+ regulator-name = "vdd_pnl1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_vid_reg: regulator@12 {
+ compatible = "regulator-fixed";
+ reg = <12>;
+ regulator-name = "vddio_vid";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ ddr_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "ddr";
+ reg = <100>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ sys_3v3_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ reg = <101>;
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb1_vbus_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ reg = <102>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ usb3_vbus_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ reg = <103>;
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ vdd_5v0_reg: regulator@104 {
+ compatible = "regulator-fixed";
+ reg = <104>;
+ regulator-name = "5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_bl_reg: regulator@105 {
+ compatible = "regulator-fixed";
+ reg = <105>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_bl2_reg: regulator@106 {
+ compatible = "regulator-fixed";
+ reg = <106>;
+ regulator-name = "vdd_bl2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
};
reg = <0x80000000 0x40000000>;
};
- /* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
- board) */
+ /*
+ * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+ * board)
+ */
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <100000>;
};
- /* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
- touch screen controller */
+ /*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
/ {
compatible = "nvidia,tegra30";
+ interrupt-parent = <&intc>;
+
+ intc: interrupt-controller@50041000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x50041000 0x1000
+ 0x50040100 0x0100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ pcie-controller@00003000 {
+ compatible = "nvidia,tegra30-pcie";
+ device_type = "pci";
+ reg = <0x00003000 0x00000800 /* PADS registers */
+ 0x00003800 0x00000200 /* AFI registers */
+ 0x10000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
+ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
+ 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
+ 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
+ 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */
+ 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
+
+ clocks = <&tegra_car TEGRA30_CLK_PCIE>,
+ <&tegra_car TEGRA30_CLK_AFI>,
+ <&tegra_car TEGRA30_CLK_PCIEX>,
+ <&tegra_car TEGRA30_CLK_PLL_E>,
+ <&tegra_car TEGRA30_CLK_CML0>;
+ clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+ status = "disabled";
+
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
+ reg = <0x001800 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+ };
tegra_car: clock {
compatible = "nvidia,tegra30-car";
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
- uart3 = &uart3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
- uart3 = &uart3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
- uart3 = &uart3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p)
{
- char *name1, *name2;
+ char name[9];
int ret;
if (i2c_index >= ARRAY_SIZE(i2c_bases))
return -EINVAL;
- name1 = malloc(9);
- name2 = malloc(9);
- if (!name1 || !name2)
- return -ENOMEM;
-
- sprintf(name1, "i2c_sda%d", i2c_index);
- sprintf(name2, "i2c_scl%d", i2c_index);
- ret = gpio_request(p->sda.gp, name1);
+ snprintf(name, sizeof(name), "i2c_sda%01d", i2c_index);
+ ret = gpio_request(p->sda.gp, name);
if (ret)
- goto err_req1;
+ return ret;
- ret = gpio_request(p->scl.gp, name2);
+ snprintf(name, sizeof(name), "i2c_scl%01d", i2c_index);
+ ret = gpio_request(p->scl.gp, name);
if (ret)
- goto err_req2;
+ goto err_req;
/* Enable i2c clock */
ret = enable_i2c_clk(1, i2c_index);
err_idle:
err_clk:
gpio_free(p->scl.gp);
-err_req2:
+err_req:
gpio_free(p->sda.gp);
-err_req1:
- free(name1);
- free(name2);
return ret;
}
/* for MMC return either RAW or FAT mode */
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
-#ifdef CONFIG_SPL_FAT_SUPPORT
+#if defined(CONFIG_SPL_FAT_SUPPORT)
return MMCSD_MODE_FS;
+#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
+ return MMCSD_MODE_EMMCBOOT;
#else
return MMCSD_MODE_RAW;
#endif
#define ESUB_CLK_BASE_ADDR 0x38000000
#define ESW_CONTRL_BASE_ADDR 0x38200000
#define GPIO2_BASE_ADDR 0x35003000
+#define HSOTG_BASE_ADDR 0x3f120000
+#define HSOTG_CTRL_BASE_ADDR 0x3f130000
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR 0x3500d000
#define BCM2835_BOARD_REV_B_REV2_f 0xf
#define BCM2835_BOARD_REV_B_PLUS 0x10
#define BCM2835_BOARD_REV_CM 0x11
+#define BCM2835_BOARD_REV_A_PLUS 0x12
struct bcm2835_mbox_tag_get_board_rev {
struct bcm2835_mbox_tag_hdr tag_hdr;
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
-/* Initialize the Parade dP<->LVDS bridge if present */
-int parade_init(const void *blob);
-
#endif /* _EXYNOS4_SYSTEM_H */
--- /dev/null
+#ifndef _TEGRA_POWERGATE_H_
+#define _TEGRA_POWERGATE_H_
+
+#include <asm/arch/clock.h>
+
+enum tegra_powergate {
+ TEGRA_POWERGATE_CPU,
+ TEGRA_POWERGATE_3D,
+ TEGRA_POWERGATE_VENC,
+ TEGRA_POWERGATE_PCIE,
+ TEGRA_POWERGATE_VDEC,
+ TEGRA_POWERGATE_L2,
+ TEGRA_POWERGATE_MPE,
+ TEGRA_POWERGATE_HEG,
+ TEGRA_POWERGATE_SATA,
+ TEGRA_POWERGATE_CPU1,
+ TEGRA_POWERGATE_CPU2,
+ TEGRA_POWERGATE_CPU3,
+ TEGRA_POWERGATE_CELP,
+ TEGRA_POWERGATE_3D1,
+ TEGRA_POWERGATE_CPU0,
+ TEGRA_POWERGATE_C0NC,
+ TEGRA_POWERGATE_C1NC,
+ TEGRA_POWERGATE_SOR,
+ TEGRA_POWERGATE_DIS,
+ TEGRA_POWERGATE_DISB,
+ TEGRA_POWERGATE_XUSBA,
+ TEGRA_POWERGATE_XUSBB,
+ TEGRA_POWERGATE_XUSBC,
+ TEGRA_POWERGATE_VIC,
+ TEGRA_POWERGATE_IRAM,
+};
+
+int tegra_powergate_sequence_power_up(enum tegra_powergate id,
+ enum periph_id periph);
+int tegra_powergate_power_off(enum tegra_powergate id);
+
+#endif
--- /dev/null
+#ifndef _TEGRA_XUSB_PADCTL_H_
+#define _TEGRA_XUSB_PADCTL_H_
+
+struct tegra_xusb_phy;
+
+/**
+ * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
+ * @type: the type of PHY to obtain
+ *
+ * The type of PHY varies between SoC generations. Typically there are XUSB,
+ * PCIe and SATA PHYs, though not all generations support all of them. The
+ * value of type can usually be directly parsed from a device tree.
+ *
+ * Return: a pointer to the PHY or NULL if no such PHY exists
+ */
+struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
+
+void tegra_xusb_padctl_init(const void *fdt);
+int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
+
+#endif
--- /dev/null
+#ifndef _TEGRA114_POWERGATE_H_
+#define _TEGRA114_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA114_POWERGATE_H_ */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+int tegra_plle_enable(void);
+
#endif /* _TEGRA124_CLOCK_H_ */
--- /dev/null
+#ifndef _TEGRA124_POWERGATE_H_
+#define _TEGRA124_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA124_POWERGATE_H_ */
/* 72 */
PERIPH_ID_AFI,
PERIPH_ID_CORESIGHT,
- PERIPH_ID_RESERVED74,
+ PERIPH_ID_PCIEXCLK,
PERIPH_ID_AVPUCQ,
PERIPH_ID_RESERVED76,
PERIPH_ID_RESERVED77,
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
+int tegra_plle_enable(void);
+
#endif /* _TEGRA20_CLOCK_H */
--- /dev/null
+#ifndef _TEGRA20_POWERGATE_H_
+#define _TEGRA20_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA20_POWERGATE_H_ */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+int tegra_plle_enable(void);
+
#endif /* _TEGRA30_CLOCK_H_ */
--- /dev/null
+#ifndef _TEGRA30_POWERGATE_H_
+#define _TEGRA30_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA30_POWERGATE_H_ */
--- /dev/null
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+ u32 ridr; /* Revision Identification Register */
+ u32 pir; /* PHY Initialixation Register */
+ u32 pgcr[2]; /* PHY General Configuration Register */
+ u32 pgsr[2]; /* PHY General Status Register */
+ u32 pllcr; /* PLL Control Register */
+ u32 ptr[5]; /* PHY Timing Register */
+ u32 acmdlr; /* AC Master Delay Line Register */
+ u32 acbdlr; /* AC Bit Delay Line Register */
+ u32 aciocr; /* AC I/O Configuration Register */
+ u32 dxccr; /* DATX8 Common Configuration Register */
+ u32 dsgcr; /* DDR System General Configuration Register */
+ u32 dcr; /* DRAM Configuration Register */
+ u32 dtpr[3]; /* DRAM Timing Parameters Register */
+ u32 mr0; /* Mode Register 0 */
+ u32 mr1; /* Mode Register 1 */
+ u32 mr2; /* Mode Register 2 */
+ u32 mr3; /* Mode Register 3 */
+ u32 odtcr; /* ODT Configuration Register */
+ u32 dtcr; /* Data Training Configuration Register */
+ u32 dtar[4]; /* Data Training Address Register */
+ u32 dtdr[2]; /* Data Training Data Register */
+ u32 dtedr[2]; /* Data Training Eye Data Register */
+ u32 rsv0[13]; /* Reserved */
+ u32 dcuar; /* DCU Address Register */
+ u32 dcudr; /* DCU Data Register */
+ u32 dcurr; /* DCU Run Register */
+ u32 dculr; /* DCU Loop Register */
+ u32 dcugcr; /* DCU General Configuration Register */
+ u32 dcutpr; /* DCU Timing Parameters Register */
+ u32 dcusr[2]; /* DCU Status Register */
+ u32 rsv1[8]; /* Reserved */
+ u32 bistrr; /* BIST Run Register */
+ u32 bistwcr; /* BIST Word Count Register */
+ u32 bistmskr[3]; /* BIST Mask Register */
+ u32 bistlsr; /* BIST LFSR Sed Register */
+ u32 bistar[3]; /* BIST Address Register */
+ u32 bistudpr; /* BIST User Data Pattern Register */
+ u32 bistgsr; /* BIST General Status Register */
+ u32 bistwer; /* BIST Word Error Register */
+ u32 bistber[4]; /* BIST Bit Error Register */
+ u32 bistwcsr; /* BIST Word Count Status Register */
+ u32 bistfwr[3]; /* BIST Fail Word Register */
+ u32 rsv2[10]; /* Reserved */
+ u32 gpr[2]; /* General Purpose Register */
+ struct ddrphy_zq { /* ZQ */
+ u32 cr[2]; /* Impedance Control Register */
+ u32 sr[2]; /* Impedance Status Register */
+ } zq[4];
+ struct ddrphy_datx8 { /* DATX8 */
+ u32 gcr; /* General Configuration Register */
+ u32 gsr[2]; /* General Status Register */
+ u32 bdlr[5]; /* Bit Delay Line Register */
+ u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
+ u32 mdlr; /* Master Delay Line Register */
+ u32 gtr; /* General Timing Register */
+ u32 rsv[3]; /* Reserved */
+ } dx[9];
+} __packed;
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT (1 << 0) /* Initialization Trigger */
+#define PIR_ZCAL (1 << 1) /* Impedance Calibration */
+#define PIR_PLLINIT (1 << 4) /* PLL Initialization */
+#define PIR_DCAL (1 << 5) /* DDL Calibration */
+#define PIR_PHYRST (1 << 6) /* PHY Reset */
+#define PIR_DRAMRST (1 << 7) /* DRAM Reset */
+#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */
+#define PIR_WL (1 << 9) /* Write Leveling */
+#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */
+#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */
+#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */
+#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */
+#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */
+#define PIR_WREYE (1 << 15) /* Write Data Eye Training */
+#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */
+#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */
+#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */
+#define PIR_INITBYP (1 << 31) /* Initialization Bypass */
+
+#define PGSR0_IDONE (1 << 0) /* Initialization Done */
+#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */
+#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */
+#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */
+#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */
+#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */
+#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */
+#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */
+#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */
+#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */
+#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */
+#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */
+#define PGSR0_IERR (1 << 16) /* Initialization Error */
+#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */
+#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */
+#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */
+#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */
+#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */
+#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */
+#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */
+#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */
+#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */
+#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */
+#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN (0 << 5)
+#define DXCCR_DQSRES_688_OHM (1 << 5)
+#define DXCCR_DQSRES_611_OHM (2 << 5)
+#define DXCCR_DQSRES_550_OHM (3 << 5)
+#define DXCCR_DQSRES_500_OHM (4 << 5)
+#define DXCCR_DQSRES_458_OHM (5 << 5)
+#define DXCCR_DQSRES_393_OHM (6 << 5)
+#define DXCCR_DQSRES_344_OHM (7 << 5)
+
+#define DXCCR_DQSNRES_OPEN (0 << 9)
+#define DXCCR_DQSNRES_688_OHM (1 << 9)
+#define DXCCR_DQSNRES_611_OHM (2 << 9)
+#define DXCCR_DQSNRES_550_OHM (3 << 9)
+#define DXCCR_DQSNRES_500_OHM (4 << 9)
+#define DXCCR_DQSNRES_458_OHM (5 << 9)
+#define DXCCR_DQSNRES_393_OHM (6 << 9)
+#define DXCCR_DQSNRES_344_OHM (7 << 9)
+
+#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */
+#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */
+#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY 2
+
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define NR_DDRPHY_PER_CH 1
+#else
+#define NR_DDRPHY_PER_CH 2
+#endif
+
+#define NR_DDRCH 2
+
+#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */
struct clk *clk_get_parent(struct clk *clk);
int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
#endif
* code for more information.
*/
int smh_load(const char *fname, void *memp, int avail, int verbose);
-int smh_read(int fd, void *memp, int len);
-int smh_open(const char *fname, char *modestr);
-int smh_close(int fd);
-int smh_len_fd(int fd);
-int smh_len(const char *fname);
+long smh_len(const char *fname);
#endif /* __SEMIHOSTING_H__ */
*/
void mmu_page_table_flush(unsigned long start, unsigned long stop);
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
#endif /* __ASSEMBLY__ */
#define arch_align_stack(x) (x)
/* for now: just dummy functions to satisfy the linker */
#include <common.h>
+#include <malloc.h>
__weak void flush_cache(unsigned long start, unsigned long size)
{
{
puts("WARNING: Caches not enabled\n");
}
+
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+/*
+ * Reserve one MMU section worth of address space below the malloc() area that
+ * will be mapped uncached.
+ */
+static unsigned long noncached_start;
+static unsigned long noncached_end;
+static unsigned long noncached_next;
+
+void noncached_init(void)
+{
+ phys_addr_t start, end;
+ size_t size;
+
+ end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
+ size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
+ start = end - size;
+
+ debug("mapping memory %pa-%pa non-cached\n", &start, &end);
+
+ noncached_start = start;
+ noncached_end = end;
+ noncached_next = start;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+ mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
+#endif
+}
+
+phys_addr_t noncached_alloc(size_t size, size_t align)
+{
+ phys_addr_t next = ALIGN(noncached_next, align);
+
+ if (next >= noncached_end || (noncached_end - next) < size)
+ return 0;
+
+ debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
+ noncached_next = next + size;
+
+ return next;
+}
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
/*
* Call the handler
*/
-static int smh_trap(unsigned int sysnum, void *addr)
+static long smh_trap(unsigned int sysnum, void *addr)
{
- register int result asm("r0");
+ register long result asm("r0");
#if defined(CONFIG_ARM64)
asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
#else
}
/*
- * Open, load a file into memory, and close it. Check that the available space
- * is sufficient to store the entire file. Return the bytes actually read from
- * the file as seen by the read function. The verbose flag enables some extra
- * printing of successful read status.
+ * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
+ * descriptor or -1 on error.
*/
-int smh_load(const char *fname, void *memp, int avail, int verbose)
+static long smh_open(const char *fname, char *modestr)
{
- int ret, fd, len;
-
- ret = -1;
-
- debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
- avail, memp);
-
- /* Open the file */
- fd = smh_open(fname, "rb");
- if (fd == -1)
- return ret;
+ long fd;
+ unsigned long mode;
+ struct smh_open_s {
+ const char *fname;
+ unsigned long mode;
+ size_t len;
+ } open;
- /* Get the file length */
- ret = smh_len_fd(fd);
- if (ret == -1) {
- smh_close(fd);
- return ret;
- }
+ debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
- /* Check that the file will fit in the supplied buffer */
- if (ret > avail) {
- printf("%s: ERROR ret %d, avail %u\n", __func__, ret,
- avail);
- smh_close(fd);
- return ret;
+ /* Check the file mode */
+ if (!(strcmp(modestr, "r"))) {
+ mode = MODE_READ;
+ } else if (!(strcmp(modestr, "rb"))) {
+ mode = MODE_READBIN;
+ } else {
+ printf("%s: ERROR mode \'%s\' not supported\n", __func__,
+ modestr);
+ return -1;
}
- len = ret;
-
- /* Read the file into the buffer */
- ret = smh_read(fd, memp, len);
- if (ret == 0) {
- /* Print successful load information if requested */
- if (verbose) {
- printf("\n%s\n", fname);
- printf(" 0x%8p dest\n", memp);
- printf(" 0x%08x size\n", len);
- printf(" 0x%08x avail\n", avail);
- }
- }
+ open.fname = fname;
+ open.len = strlen(fname);
+ open.mode = mode;
- /* Close the file */
- smh_close(fd);
+ /* Open the file on the host */
+ fd = smh_trap(SYSOPEN, &open);
+ if (fd == -1)
+ printf("%s: ERROR fd %ld for file \'%s\'\n", __func__, fd,
+ fname);
- return ret;
+ return fd;
}
/*
* Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure
*/
-int smh_read(int fd, void *memp, int len)
+static long smh_read(long fd, void *memp, size_t len)
{
- int ret;
+ long ret;
struct smh_read_s {
- int fd;
+ long fd;
void *memp;
- int len;
+ size_t len;
} read;
- debug("%s: fd %d, memp %p, len %d\n", __func__, fd, memp, len);
+ debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
read.fd = fd;
read.memp = memp;
read.len = len;
ret = smh_trap(SYSREAD, &read);
- if (ret == 0) {
- return 0;
- } else {
+ if (ret < 0) {
/*
* The ARM handler allows for returning partial lengths,
* but in practice this never happens so rather than create
* hard to maintain partial read loops and such, just fail
* with an error message.
*/
- printf("%s: ERROR ret %d, fd %d, len %u memp %p\n",
+ printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
__func__, ret, fd, len, memp);
+ return -1;
}
- return ret;
+
+ return 0;
}
/*
- * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
- * descriptor or -1 on error.
+ * Close the file using the file descriptor
*/
-int smh_open(const char *fname, char *modestr)
+static long smh_close(long fd)
{
- int ret, fd, mode;
- struct smh_open_s {
- const char *fname;
- unsigned int mode;
- unsigned int len;
- } open;
+ long ret;
- debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
-
- ret = -1;
+ debug("%s: fd %ld\n", __func__, fd);
- /* Check the file mode */
- if (!(strcmp(modestr, "r"))) {
- mode = MODE_READ;
- } else if (!(strcmp(modestr, "rb"))) {
- mode = MODE_READBIN;
- } else {
- printf("%s: ERROR mode \'%s\' not supported\n", __func__,
- modestr);
- return ret;
- }
-
- open.fname = fname;
- open.len = strlen(fname);
- open.mode = mode;
-
- /* Open the file on the host */
- fd = smh_trap(SYSOPEN, &open);
- if (fd == -1)
- printf("%s: ERROR fd %d for file \'%s\'\n", __func__, fd,
- fname);
+ ret = smh_trap(SYSCLOSE, &fd);
+ if (ret == -1)
+ printf("%s: ERROR fd %ld\n", __func__, fd);
- return fd;
+ return ret;
}
/*
- * Close the file using the file descriptor
+ * Get the file length from the file descriptor
*/
-int smh_close(int fd)
+static long smh_len_fd(long fd)
{
- int ret;
- long fdlong;
+ long ret;
- debug("%s: fd %d\n", __func__, fd);
+ debug("%s: fd %ld\n", __func__, fd);
- fdlong = (long)fd;
- ret = smh_trap(SYSCLOSE, &fdlong);
+ ret = smh_trap(SYSFLEN, &fd);
if (ret == -1)
- printf("%s: ERROR fd %d\n", __func__, fd);
+ printf("%s: ERROR ret %ld, fd %ld\n", __func__, ret, fd);
return ret;
}
/*
- * Get the file length from the file descriptor
+ * Open, load a file into memory, and close it. Check that the available space
+ * is sufficient to store the entire file. Return the bytes actually read from
+ * the file as seen by the read function. The verbose flag enables some extra
+ * printing of successful read status.
*/
-int smh_len_fd(int fd)
+int smh_load(const char *fname, void *memp, int avail, int verbose)
{
- int ret;
- long fdlong;
+ long ret;
+ long fd;
+ size_t len;
- debug("%s: fd %d\n", __func__, fd);
+ ret = -1;
- fdlong = (long)fd;
- ret = smh_trap(SYSFLEN, &fdlong);
- if (ret == -1)
- printf("%s: ERROR ret %d\n", __func__, ret);
+ debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
+ avail, memp);
+
+ /* Open the file */
+ fd = smh_open(fname, "rb");
+ if (fd == -1)
+ return -1;
+
+ /* Get the file length */
+ ret = smh_len_fd(fd);
+ if (ret == -1) {
+ smh_close(fd);
+ return -1;
+ }
+
+ /* Check that the file will fit in the supplied buffer */
+ if (ret > avail) {
+ printf("%s: ERROR ret %ld, avail %u\n", __func__, ret,
+ avail);
+ smh_close(fd);
+ return -1;
+ }
+
+ len = ret;
+
+ /* Read the file into the buffer */
+ ret = smh_read(fd, memp, len);
+ if (ret == 0) {
+ /* Print successful load information if requested */
+ if (verbose) {
+ printf("\n%s\n", fname);
+ printf(" 0x%8p dest\n", memp);
+ printf(" 0x%08lx size\n", len);
+ printf(" 0x%08x avail\n", avail);
+ }
+ }
+
+ /* Close the file */
+ smh_close(fd);
return ret;
}
/*
* Get the file length from the filename
*/
-int smh_len(const char *fname)
+long smh_len(const char *fname)
{
- int ret, fd, len;
+ long ret;
+ long fd;
+ long len;
debug("%s: file \'%s\'\n", __func__, fname);
/* Open the file */
fd = smh_open(fname, "rb");
- if (fd == -1)
+ if (fd < 0)
return fd;
/* Get the file length */
len = smh_len_fd(fd);
+ if (len < 0) {
+ smh_close(fd);
+ return len;
+ }
/* Close the file */
ret = smh_close(fd);
- if (ret == -1)
+ if (ret < 0)
return ret;
- debug("%s: returning len %d\n", __func__, len);
+ debug("%s: returning len %ld\n", __func__, len);
/* Return the file length (or -1 error indication) */
return len;
and it provides a 2560x1700 high resolution touch-enabled LCD
display.
+config TARGET_CROWNBAY
+ bool "Support Intel Crown Bay CRB"
+ help
+ This is the Intel Crown Bay Customer Reference Board. It contains
+ the Intel Atom Processor E6xx populated on the COM Express module
+ with 1GB DDR2 soldered down memory and a carrier board with the
+ Intel Platform Controller Hub EG20T, other system components and
+ peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
endchoice
config RAMBASE
source "arch/x86/cpu/ivybridge/Kconfig"
+source "arch/x86/cpu/queensbay/Kconfig"
+
source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/intel/crownbay/Kconfig"
+
endmenu
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
+obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-y += lapic.o
obj-$(CONFIG_PCI) += pci.o
obj-y += turbo.o
update->data = fdt_getprop(blob, node, "data", &update->size);
if (!update->data)
return -EINVAL;
+ update->data += 48;
+ update->size -= 48;
update->header_version = fdtdec_get_int(blob, node,
"intel,header-version", 0);
update->date_code = fdtdec_get_int(blob, node,
"intel,date-code", 0);
update->processor_signature = fdtdec_get_int(blob, node,
- "intel.processor-signature", 0);
+ "intel,processor-signature", 0);
update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
update->loader_revision = fdtdec_get_int(blob, node,
- "loader-revision", 0);
+ "intel,loader-revision", 0);
update->processor_flags = fdtdec_get_int(blob, node,
- "processor-flags", 0);
+ "intel,processor-flags", 0);
return 0;
}
-static uint32_t microcode_read_rev(void)
+static inline uint32_t microcode_read_rev(void)
{
/*
* Some Intel CPUs can be very finicky about the CPUID sequence used.
{
struct microcode_update cpu, update;
const void *blob = gd->fdt_blob;
+ int skipped;
int count;
int node;
int ret;
microcode_read_cpu(&cpu);
node = 0;
count = 0;
+ skipped = 0;
do {
node = fdtdec_next_compatible(blob, node,
COMPAT_INTEL_MICROCODE);
if (node < 0) {
debug("%s: Found %d updates\n", __func__, count);
- return count ? 0 : -ENOENT;
+ return count ? 0 : skipped ? -EEXIST : -ENOENT;
}
ret = microcode_decode_node(blob, node, &update);
ret);
return ret;
}
- if (update.processor_signature == cpu.processor_signature &&
- (update.processor_flags & cpu.processor_flags)) {
- debug("%s: Update already exists\n", __func__);
- return -EEXIST;
+ if (!(update.processor_signature == cpu.processor_signature &&
+ (update.processor_flags & cpu.processor_flags))) {
+ debug("%s: Skipping non-matching update, sig=%x, pf=%x\n",
+ __func__, update.processor_signature,
+ update.processor_flags);
+ skipped++;
+ continue;
}
-
+ ret = microcode_read_rev();
wrmsr(0x79, (ulong)update.data, 0);
debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
microcode_read_rev(), update.date_code & 0xffff,
debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
- data = (char *)CONFIG_X86_MRC_START;
+ data = (char *)CONFIG_X86_MRC_ADDR;
if (data) {
int rv;
int (*func)(struct pei_data *);
--- /dev/null
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_QUEENSBAY
+ bool
+ select HAVE_FSP
+ select HAVE_CMC
+
+if INTEL_QUEENSBAY
+
+config HAVE_FSP
+ bool "Add an Firmware Support Package binary"
+ help
+ Select this option to add an Firmware Support Package binary to
+ the resulting U-Boot image. It is a binary blob which U-Boot uses
+ to set up SDRAM and other chipset specific initialization.
+
+ Note: Without this binary U-Boot will not be able to set up its
+ SDRAM so will not boot.
+
+config FSP_FILE
+ string "Firmware Support Package binary filename"
+ depends on HAVE_FSP
+ default "fsp.bin"
+ help
+ The filename of the file to use as Firmware Support Package binary
+ in the board directory.
+
+config FSP_ADDR
+ hex "Firmware Support Package binary location"
+ depends on HAVE_FSP
+ default 0xfffc0000
+ help
+ FSP is not Position Independent Code (PIC) and the whole FSP has to
+ be rebased if it is placed at a location which is different from the
+ perferred base address specified during the FSP build. Use Intel's
+ Binary Configuration Tool (BCT) to do the rebase.
+
+ The default base address of 0xfffc0000 indicates that the binary must
+ be located at offset 0xc0000 from the beginning of a 1MB flash device.
+
+config FSP_TEMP_RAM_ADDR
+ hex
+ default 0x2000000
+ help
+ Stack top address which is used in FspInit after DRAM is ready and
+ CAR is disabled.
+
+config HAVE_CMC
+ bool "Add a Chipset Micro Code state machine binary"
+ help
+ Select this option to add a Chipset Micro Code state machine binary
+ to the resulting U-Boot image. It is a 64K data block of machine
+ specific code which must be put in the flash for the processor to
+ access when powered up before system BIOS is executed.
+
+config CMC_FILE
+ string "Chipset Micro Code state machine filename"
+ depends on HAVE_CMC
+ default "cmc.bin"
+ help
+ The filename of the file to use as Chipset Micro Code state machine
+ binary in the board directory.
+
+config CMC_ADDR
+ hex "Chipset Micro Code state machine binary location"
+ depends on HAVE_CMC
+ default 0xfffb0000
+ help
+ The location of the CMC binary is determined by a strap. It must be
+ put in flash at a location matching the strap-determined base address.
+
+ The default base address of 0xfffb0000 indicates that the binary must
+ be located at offset 0xb0000 from the beginning of a 1MB flash device.
+
+endif
--- /dev/null
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
+obj-y += fsp_configs.o fsp_support.o
+obj-$(CONFIG_PCI) += tnc_pci.o
#include <common.h>
#include <asm/arch/fsp/fsp_support.h>
-void update_fsp_upd(struct upd_region_t *fsp_upd)
+void update_fsp_upd(struct upd_region *fsp_upd)
{
/* Override any UPD setting if required */
#include <asm/arch/fsp/fsp_support.h>
#include <asm/post.h>
-/**
- * Reads a 64-bit value from memory that may be unaligned.
- *
- * This function returns the 64-bit value pointed to by buf. The function
- * guarantees that the read operation does not produce an alignment fault.
- *
- * If the buf is NULL, then ASSERT().
- *
- * @buf: Pointer to a 64-bit value that may be unaligned.
- *
- * @return: The 64-bit value read from buf.
- */
-static u64 read_unaligned64(const u64 *buf)
-{
- ASSERT(buf != NULL);
-
- return *buf;
-}
-
/**
* Compares two GUIDs
*
- * If the GUIDs are identical then TRUE is returned.
- * If there are any bit differences in the two GUIDs, then FALSE is returned.
- *
- * If guid1 is NULL, then ASSERT().
- * If guid2 is NULL, then ASSERT().
+ * If the GUIDs are identical then true is returned.
+ * If there are any bit differences in the two GUIDs, then false is returned.
*
* @guid1: A pointer to a 128 bit GUID.
* @guid2: A pointer to a 128 bit GUID.
*
- * @retval TRUE: guid1 and guid2 are identical.
- * @retval FALSE: guid1 and guid2 are not identical.
+ * @retval true: guid1 and guid2 are identical.
+ * @retval false: guid1 and guid2 are not identical.
*/
-static unsigned char compare_guid(const struct efi_guid_t *guid1,
- const struct efi_guid_t *guid2)
+static bool compare_guid(const struct efi_guid *guid1,
+ const struct efi_guid *guid2)
{
- u64 guid1_low;
- u64 guid2_low;
- u64 guid1_high;
- u64 guid2_high;
-
- guid1_low = read_unaligned64((const u64 *)guid1);
- guid2_low = read_unaligned64((const u64 *)guid2);
- guid1_high = read_unaligned64((const u64 *)guid1 + 1);
- guid2_high = read_unaligned64((const u64 *)guid2 + 1);
-
- return (unsigned char)(guid1_low == guid2_low && guid1_high == guid2_high);
+ if (memcmp(guid1, guid2, sizeof(struct efi_guid)) == 0)
+ return true;
+ else
+ return false;
}
u32 __attribute__((optimize("O0"))) find_fsp_header(void)
{
+ /*
+ * This function may be called before the a stack is established,
+ * so special care must be taken. First, it cannot declare any local
+ * variable using stack. Only register variable can be used here.
+ * Secondly, some compiler version will add prolog or epilog code
+ * for the C function. If so the function call may not work before
+ * stack is ready.
+ *
+ * GCC 4.8.1 has been verified to be working for the following codes.
+ */
volatile register u8 *fsp asm("eax");
/* Initalize the FSP base */
- fsp = (u8 *)CONFIG_FSP_LOCATION;
+ fsp = (u8 *)CONFIG_FSP_ADDR;
/* Check the FV signature, _FVH */
- if (((struct fv_header_t *)fsp)->sign == 0x4856465F) {
+ if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) {
/* Go to the end of the FV header and align the address */
- fsp += ((struct fv_header_t *)fsp)->ext_hdr_off;
- fsp += ((struct fv_ext_header_t *)fsp)->ext_hdr_size;
+ fsp += ((struct fv_header *)fsp)->ext_hdr_off;
+ fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size;
fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8);
} else {
fsp = 0;
/* Check the FFS GUID */
if (fsp &&
- (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[0] == 0x912740BE) &&
- (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[1] == 0x47342284) &&
- (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[2] == 0xB08471B9) &&
- (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[3] == 0x0C3F3527)) {
+ ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 &&
+ ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 &&
+ ((struct ffs_file_header *)fsp)->name.data3 == FSP_GUID_DATA3 &&
+ ((struct ffs_file_header *)fsp)->name.data4[0] == FSP_GUID_DATA4_0 &&
+ ((struct ffs_file_header *)fsp)->name.data4[1] == FSP_GUID_DATA4_1 &&
+ ((struct ffs_file_header *)fsp)->name.data4[2] == FSP_GUID_DATA4_2 &&
+ ((struct ffs_file_header *)fsp)->name.data4[3] == FSP_GUID_DATA4_3 &&
+ ((struct ffs_file_header *)fsp)->name.data4[4] == FSP_GUID_DATA4_4 &&
+ ((struct ffs_file_header *)fsp)->name.data4[5] == FSP_GUID_DATA4_5 &&
+ ((struct ffs_file_header *)fsp)->name.data4[6] == FSP_GUID_DATA4_6 &&
+ ((struct ffs_file_header *)fsp)->name.data4[7] == FSP_GUID_DATA4_7) {
/* Add the FFS header size to find the raw section header */
- fsp += sizeof(struct ffs_file_header_t);
+ fsp += sizeof(struct ffs_file_header);
} else {
fsp = 0;
}
if (fsp &&
- ((struct raw_section_t *)fsp)->type == EFI_SECTION_RAW) {
+ ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) {
/* Add the raw section header size to find the FSP header */
- fsp += sizeof(struct raw_section_t);
+ fsp += sizeof(struct raw_section);
} else {
fsp = 0;
}
return (u32)fsp;
}
-void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list)
+void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
{
u32 stack_len;
u32 stack_base;
post_code(POST_MRC);
- ASSERT(status == 0);
+ assert(status == 0);
/* Get the migrated stack in normal memory */
- stack_base = (u32)get_bootloader_tmp_mem(hob_list, &stack_len);
- ASSERT(stack_base != 0);
+ stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len);
+ assert(stack_base != 0);
stack_top = stack_base + stack_len - sizeof(u32);
/*
* Old stack base is stored at the very end of the stack top,
* use it to calculate the migrated shared data base
*/
- shared_data = (struct shared_data_t *)(stack_base +
+ shared_data = (struct shared_data *)(stack_base +
((u32)shared_data - *(u32 *)stack_top));
/* The boot loader main function entry */
void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
{
- struct shared_data_t shared_data;
+ struct shared_data shared_data;
fsp_init_f init;
- struct fsp_init_params_t params;
- struct fspinit_rtbuf_t rt_buf;
- struct vpd_region_t *fsp_vpd;
- struct fsp_header_t *fsp_hdr;
- struct fsp_init_params_t *params_ptr;
- struct upd_region_t *fsp_upd;
-
- fsp_hdr = (struct fsp_header_t *)find_fsp_header();
+ struct fsp_init_params params;
+ struct fspinit_rtbuf rt_buf;
+ struct vpd_region *fsp_vpd;
+ struct fsp_header *fsp_hdr;
+ struct fsp_init_params *params_ptr;
+ struct upd_region *fsp_upd;
+
+ fsp_hdr = (struct fsp_header *)find_fsp_header();
if (fsp_hdr == NULL) {
/* No valid FSP info header was found */
- ASSERT(FALSE);
+ panic("Invalid FSP header");
}
- fsp_upd = (struct upd_region_t *)&shared_data.fsp_upd;
- memset((void *)&rt_buf, 0, sizeof(struct fspinit_rtbuf_t));
+ fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
+ memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
/* Reserve a gap in stack top */
rt_buf.common.stack_top = (u32 *)stack_top - 32;
rt_buf.common.boot_mode = boot_mode;
- rt_buf.common.upd_data = (struct upd_region_t *)fsp_upd;
+ rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
/* Get VPD region start */
- fsp_vpd = (struct vpd_region_t *)(fsp_hdr->img_base +
+ fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
fsp_hdr->cfg_region_off);
/* Verifify the VPD data region is valid */
- ASSERT((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
+ assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
(fsp_vpd->sign == VPD_IMAGE_ID));
/* Copy default data from Flash */
memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
- sizeof(struct upd_region_t));
+ sizeof(struct upd_region));
/* Verifify the UPD data region is valid */
- ASSERT(fsp_upd->terminator == 0x55AA);
+ assert(fsp_upd->terminator == UPD_TERMINATOR);
/* Override any UPD setting if required */
update_fsp_upd(fsp_upd);
- memset((void *)¶ms, 0, sizeof(struct fsp_init_params_t));
+ memset(¶ms, 0, sizeof(struct fsp_init_params));
params.nvs_buf = nvs_buf;
- params.rt_buf = (struct fspinit_rtbuf_t *)&rt_buf;
+ params.rt_buf = (struct fspinit_rtbuf *)&rt_buf;
params.continuation = (fsp_continuation_f)asm_continuation;
init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
/*
* Should never get here.
- * Control will continue from romstage_main_continue_asm.
+ * Control will continue from fsp_continue.
* This line below is to prevent the compiler from optimizing
* structure intialization.
+ *
+ * DO NOT REMOVE!
*/
init(¶ms);
-
- /*
- * Should never return.
- * Control will continue from ContinuationFunc
- */
- ASSERT(FALSE);
}
-u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase)
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
{
fsp_notify_f notify;
- struct fsp_notify_params_t params;
- struct fsp_notify_params_t *params_ptr;
+ struct fsp_notify_params params;
+ struct fsp_notify_params *params_ptr;
u32 status;
if (!fsp_hdr)
- fsp_hdr = (struct fsp_header_t *)find_fsp_header();
+ fsp_hdr = (struct fsp_header *)find_fsp_header();
if (fsp_hdr == NULL) {
/* No valid FSP info header */
- ASSERT(FALSE);
+ panic("Invalid FSP header");
}
notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
return status;
}
-u32 get_usable_lowmem_top(const void *hob_list)
+u32 fsp_get_usable_lowmem_top(const void *hob_list)
{
- union hob_pointers_t hob;
+ union hob_pointers hob;
phys_addr_t phys_start;
u32 top;
hob.raw = (void *)hob_list;
/* * Collect memory ranges */
- top = 0x100000;
- while (!END_OF_HOB(hob)) {
- if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+ top = FSP_LOWMEM_BASE;
+ while (!end_of_hob(hob)) {
+ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
if (hob.res_desc->type == RES_SYS_MEM) {
phys_start = hob.res_desc->phys_start;
/* Need memory above 1MB to be collected here */
- if (phys_start >= 0x100000 &&
- phys_start < (phys_addr_t)0x100000000)
+ if (phys_start >= FSP_LOWMEM_BASE &&
+ phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
top += (u32)(hob.res_desc->len);
}
}
- hob.raw = GET_NEXT_HOB(hob);
+ hob.raw = get_next_hob(hob);
}
return top;
}
-u64 get_usable_highmem_top(const void *hob_list)
+u64 fsp_get_usable_highmem_top(const void *hob_list)
{
- union hob_pointers_t hob;
+ union hob_pointers hob;
phys_addr_t phys_start;
u64 top;
hob.raw = (void *)hob_list;
/* Collect memory ranges */
- top = 0x100000000;
- while (!END_OF_HOB(hob)) {
- if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+ top = FSP_HIGHMEM_BASE;
+ while (!end_of_hob(hob)) {
+ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
if (hob.res_desc->type == RES_SYS_MEM) {
phys_start = hob.res_desc->phys_start;
/* Need memory above 1MB to be collected here */
- if (phys_start >= (phys_addr_t)0x100000000)
+ if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
top += (u32)(hob.res_desc->len);
}
}
- hob.raw = GET_NEXT_HOB(hob);
+ hob.raw = get_next_hob(hob);
}
return top;
}
-u64 get_fsp_reserved_mem_from_guid(const void *hob_list, u64 *len,
- struct efi_guid_t *guid)
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
+ struct efi_guid *guid)
{
- union hob_pointers_t hob;
+ union hob_pointers hob;
/* Get the HOB list for processing */
hob.raw = (void *)hob_list;
/* Collect memory ranges */
- while (!END_OF_HOB(hob)) {
- if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+ while (!end_of_hob(hob)) {
+ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
if (hob.res_desc->type == RES_MEM_RESERVED) {
if (compare_guid(&hob.res_desc->owner, guid)) {
if (len)
}
}
}
- hob.raw = GET_NEXT_HOB(hob);
+ hob.raw = get_next_hob(hob);
}
return 0;
}
-u32 get_fsp_reserved_mem(const void *hob_list, u32 *len)
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
{
- const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
+ const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
u64 length;
u32 base;
- base = (u32)get_fsp_reserved_mem_from_guid(hob_list,
- &length, (struct efi_guid_t *)&guid);
+ base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+ &length, (struct efi_guid *)&guid);
if ((len != 0) && (base != 0))
*len = (u32)length;
return base;
}
-u32 get_tseg_reserved_mem(const void *hob_list, u32 *len)
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
{
- const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
+ const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
u64 length;
u32 base;
- base = (u32)get_fsp_reserved_mem_from_guid(hob_list,
- &length, (struct efi_guid_t *)&guid);
+ base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+ &length, (struct efi_guid *)&guid);
if ((len != 0) && (base != 0))
*len = (u32)length;
return base;
}
-void *get_next_hob(u16 type, const void *hob_list)
+void *fsp_get_next_hob(u16 type, const void *hob_list)
{
- union hob_pointers_t hob;
+ union hob_pointers hob;
- ASSERT(hob_list != NULL);
+ assert(hob_list != NULL);
hob.raw = (u8 *)hob_list;
/* Parse the HOB list until end of list or matching type is found */
- while (!END_OF_HOB(hob)) {
- if (hob.hdr->type == type)
+ while (!end_of_hob(hob)) {
+ if (get_hob_type(hob) == type)
return hob.raw;
- hob.raw = GET_NEXT_HOB(hob);
+ hob.raw = get_next_hob(hob);
}
return NULL;
}
-void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list)
+void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list)
{
- union hob_pointers_t hob;
+ union hob_pointers hob;
hob.raw = (u8 *)hob_list;
- while ((hob.raw = get_next_hob(HOB_TYPE_GUID_EXT,
+ while ((hob.raw = fsp_get_next_hob(HOB_TYPE_GUID_EXT,
hob.raw)) != NULL) {
if (compare_guid(guid, &hob.guid->name))
break;
- hob.raw = GET_NEXT_HOB(hob);
+ hob.raw = get_next_hob(hob);
}
return hob.raw;
}
-void *get_guid_hob_data(const void *hob_list, u32 *len, struct efi_guid_t *guid)
+void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
+ struct efi_guid *guid)
{
u8 *guid_hob;
- guid_hob = get_next_guid_hob(guid, hob_list);
+ guid_hob = fsp_get_next_guid_hob(guid, hob_list);
if (guid_hob == NULL) {
return NULL;
} else {
if (len)
- *len = GET_GUID_HOB_DATA_SIZE(guid_hob);
+ *len = get_guid_hob_data_size(guid_hob);
- return GET_GUID_HOB_DATA(guid_hob);
+ return get_guid_hob_data(guid_hob);
}
}
-void *get_fsp_nvs_data(const void *hob_list, u32 *len)
+void *fsp_get_nvs_data(const void *hob_list, u32 *len)
{
- const struct efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+ const struct efi_guid guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
- return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid);
+ return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
}
-void *get_bootloader_tmp_mem(const void *hob_list, u32 *len)
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
{
- const struct efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
+ const struct efi_guid guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
- return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid);
+ return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
}
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/arch/tnc.h>
+#include <asm/arch/fsp/fsp_support.h>
+#include <asm/processor.h>
+
+static void unprotect_spi_flash(void)
+{
+ u32 bc;
+
+ bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
+ bc |= 0x1; /* unprotect the flash */
+ pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+}
+
+int arch_cpu_init(void)
+{
+ struct pci_controller *hose;
+ int ret;
+
+ post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ timer_set_base(rdtsc());
+#endif
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ ret = pci_early_init_hose(&hose);
+ if (ret)
+ return ret;
+
+ unprotect_spi_flash();
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ post_code(POST_CPU_INFO);
+ return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+ /* cold reset */
+ outb(0x06, PORT_RESET);
+}
+
+void board_final_cleanup(void)
+{
+ u32 status;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
+ status = fsp_notify(NULL, INIT_PHASE_BOOT);
+ if (status != FSP_SUCCESS)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+
+ return;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/post.h>
+
+.globl car_init
+car_init:
+ /*
+ * Note: ebp holds the BIST value (built-in self test) so far, but ebp
+ * will be destroyed through the FSP call, thus we have to test the
+ * BIST value here before we call into FSP.
+ */
+ test %ebp, %ebp
+ jz car_init_start
+ post_code(POST_BIST_FAILURE)
+ jmp die
+
+car_init_start:
+ post_code(POST_CAR_START)
+ lea find_fsp_header_romstack, %esp
+ jmp find_fsp_header
+
+find_fsp_header_ret:
+ /* EAX points to FSP_INFO_HEADER */
+ mov %eax, %ebp
+
+ /* sanity test */
+ cmp $CONFIG_FSP_ADDR, %eax
+ jb die
+
+ /* calculate TempRamInitEntry address */
+ mov 0x30(%ebp), %eax
+ add 0x1c(%ebp), %eax
+
+ /* call FSP TempRamInitEntry to setup temporary stack */
+ lea temp_ram_init_romstack, %esp
+ jmp *%eax
+
+temp_ram_init_ret:
+ addl $4, %esp
+ cmp $0, %eax
+ jnz car_init_fail
+
+ post_code(POST_CAR_CPU_CACHE)
+
+ /*
+ * The FSP TempRamInit initializes the ecx and edx registers to
+ * point to a temporary but writable memory range (Cache-As-RAM).
+ * ecx: the start of this temporary memory range,
+ * edx: the end of this range.
+ */
+
+ /* stack grows down from top of CAR */
+ movl %edx, %esp
+
+ /*
+ * TODO:
+ *
+ * According to FSP architecture spec, the fsp_init() will not return
+ * to its caller, instead it requires the bootloader to provide a
+ * so-called continuation function to pass into the FSP as a parameter
+ * of fsp_init, and fsp_init() will call that continuation function
+ * directly.
+ *
+ * The call to fsp_init() may need to be moved out of the car_init()
+ * to cpu_init_f() with the help of some inline assembly codes.
+ * Note there is another issue that fsp_init() will setup another stack
+ * using the fsp_init parameter stack_top after DRAM is initialized,
+ * which means any data on the previous stack (on the CAR) gets lost
+ * (ie: U-Boot global_data). FSP is supposed to support such scenario,
+ * however it does not work. This should be revisited in the future.
+ */
+ movl $CONFIG_FSP_TEMP_RAM_ADDR, %eax
+ xorl %edx, %edx
+ xorl %ecx, %ecx
+ call fsp_init
+
+.global fsp_init_done
+fsp_init_done:
+ /*
+ * We come here from FspInit with eax pointing to the HOB list.
+ * Save eax to esi temporarily.
+ */
+ movl %eax, %esi
+ /*
+ * Re-initialize the ebp (BIST) to zero, as we already reach here
+ * which means we passed BIST testing before.
+ */
+ xorl %ebp, %ebp
+ jmp car_init_ret
+
+car_init_fail:
+ post_code(POST_CAR_FAILURE)
+
+die:
+ hlt
+ jmp die
+ hlt
+
+ /*
+ * The function call before CAR initialization is tricky. It cannot
+ * be called using the 'call' instruction but only the 'jmp' with
+ * the help of a handcrafted stack in the ROM. The stack needs to
+ * contain the function return address as well as the parameters.
+ */
+ .balign 4
+find_fsp_header_romstack:
+ .long find_fsp_header_ret
+
+ .balign 4
+temp_ram_init_romstack:
+ .long temp_ram_init_ret
+ .long temp_ram_init_params
+temp_ram_init_params:
+_dt_ucode_base_size:
+ /* These next two fields are filled in by ifdtool */
+ .long 0 /* microcode base */
+ .long 0 /* microcode size */
+ .long CONFIG_SYS_MONITOR_BASE /* code region base */
+ .long CONFIG_SYS_MONITOR_LEN /* code region size */
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/fsp_support.h>
+#include <asm/e820.h>
+#include <asm/post.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ phys_size_t ram_size = 0;
+ union hob_pointers hob;
+
+ hob.raw = gd->arch.hob_list;
+ while (!end_of_hob(hob)) {
+ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
+ if (hob.res_desc->type == RES_SYS_MEM ||
+ hob.res_desc->type == RES_MEM_RESERVED) {
+ ram_size += hob.res_desc->len;
+ }
+ }
+ hob.raw = get_next_hob(hob);
+ }
+
+ gd->ram_size = ram_size;
+ post_code(POST_DRAM);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return fsp_get_usable_lowmem_top(gd->arch.hob_list);
+}
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+ unsigned num_entries = 0;
+
+ union hob_pointers hob;
+
+ hob.raw = gd->arch.hob_list;
+
+ while (!end_of_hob(hob)) {
+ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
+ entries[num_entries].addr = hob.res_desc->phys_start;
+ entries[num_entries].size = hob.res_desc->len;
+
+ if (hob.res_desc->type == RES_SYS_MEM)
+ entries[num_entries].type = E820_RAM;
+ else if (hob.res_desc->type == RES_MEM_RESERVED)
+ entries[num_entries].type = E820_RESERVED;
+ }
+ hob.raw = get_next_hob(hob);
+ num_entries++;
+ }
+
+ return num_entries;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/arch/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
+
+ pci_set_region(hose->regions + 3,
+ 0,
+ 0,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 4;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ u32 status;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+ status = fsp_notify(NULL, INIT_PHASE_PCI);
+ if (status != FSP_SUCCESS)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <sdhci.h>
+
+static struct pci_device_id mmc_supported[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
+ { }
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+ struct sdhci_host *mmc_host;
+ pci_dev_t devbusfn;
+ u32 iobase;
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
+ devbusfn = pci_find_devices(mmc_supported, i);
+ if (devbusfn == -1)
+ return -ENODEV;
+
+ mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+ if (!mmc_host)
+ return -ENOMEM;
+
+ mmc_host->name = "Topcliff SDHCI";
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+ mmc_host->ioaddr = (void *)iobase;
+ mmc_host->quirks = 0;
+ ret = add_sdhci(mmc_host, 0, 0);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
};
serial {
- compatible = "coreboot-uart";
+ compatible = "x86-uart";
reg = <0x3f8 0x10>;
reg-shift = <0>;
io-mapped = <1>;
memory-map = <0xffe00000 0x00200000>;
};
};
+
+ microcode {
+ update@0 {
+#include "microcode/m0220661105_cv.dtsi"
+ };
+ };
+
};
microcode {
update@0 {
-#include "m12206a7_00000028.dtsi"
+#include "microcode/m12206a7_00000029.dtsi"
};
update@1 {
-#include "m12306a9_00000017.dtsi"
+#include "microcode/m12306a9_0000001b.dtsi"
};
};
+++ /dev/null
-/*
- * Copyright (c) <1995-2013>, Intel Corporation.
- * All rights reserved.
- *
- * Redistribution. Redistribution and use in binary form, without modification, are
- * permitted provided that the following conditions are met:
- * .Redistributions must reproduce the above copyright notice and the following
- * disclaimer in the documentation and/or other materials provided with the
- * distribution.
- * Neither the name of Intel Corporation nor the names of its suppliers may be used
- * to endorse or promote products derived from this software without specific prior
- * written permission.
- * .No reverse engineering, decompilation, or disassembly of this software is
- * permitted.
- * ."Binary form" includes any format commonly used for electronic conveyance
- * which is a reversible, bit-exact translation of binary representation to ASCII or
- * ISO text, for example, "uuencode."
- *
- * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x28>;
-intel,date-code = <0x04242012>;
-intel,processor-signature = <0x000206a7>;
-intel,checksum = <0xf3e9935d>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x12>;
-
-/* The 48-byte public header is omitted. */
-data = <
- 0x00000000 0x000000a1 0x00020001 0x00000028
- 0x00000000 0x00000000 0x20120423 0x000008f1
- 0x00000001 0x000206a7 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x00000000 0x000008f1 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x52b813ac 0xdb8994c7 0x70e9f6bb 0x9d6db2ff
- 0xf4d70f5d 0x5b1eccf6 0xac59106f 0x0ae2e2c1
- 0x1a7bbeb1 0x355a1d62 0x2e7eb594 0x09f8dea9
- 0x432a49e4 0xbf520253 0xdafa4010 0x893a858a
- 0x766e0efb 0xd91e196d 0x838bd2ef 0xe5146494
- 0xd515f413 0x29704828 0xe85598b6 0xdcbe6c51
- 0x88eabbfa 0xa1e8909f 0xd8931721 0x35386554
- 0x089a78a7 0xd9914775 0xd4644748 0x1556a4dc
- 0xf44448f6 0xd054d7db 0xf30f2b7d 0x5ae223d0
- 0xcbbb48b0 0x5c8b0383 0x177de157 0x9c1e5f73
- 0x2ec28289 0xd72a7b6c 0x823b6eb2 0x35e02171
- 0xba8deae4 0x06f4d468 0x13dbafaa 0x72b419f1
- 0x033385b5 0x05806920 0x4c6034cf 0x9bd117dc
- 0x976e2d04 0x250330f0 0x7250b5e1 0x184980c2
- 0x12a9d7d6 0x1bc808f9 0xae79994f 0xc6f87901
- 0xc0e3132f 0x671491c5 0x236cad39 0x37889d9c
- 0x67f7c3f3 0x964a6be5 0xbcced7da 0x57eeaa6e
- 0x7bca1522 0x654fee4c 0x2a1ca5d9 0xa1803cf3
- 0x00000011 0x8c316d2c 0x17603b7e 0x32e42981
- 0xc26c1400 0xf0fbccb6 0xeab6b43a 0x11d456a5
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- 0x183356af 0xb6e98608 0x987b43c2 0xa8a3cfd2
- 0xc2c5fce0 0xcc3af64a 0xd6d3a291 0xe59ad1f5
- 0x124ca513 0x9522b50a 0x25150477 0xa2eb5797
- 0x7fc63626 0x648c48e3 0x9f5797ff 0x2307b84d
- 0x980625a4 0xabc05983 0x24980807 0x773c4f99
- 0x3407b872 0x07c3657a 0xa2cd9e48 0x49c1e6a8
- 0xa881b84c 0xf804d72c 0xb5319d2a 0x3e39780f
- 0x97518822 0x0acd54c2 0x0721a9ff 0x10e1d2fd
- 0xa7b6db77 0x845b1a56 0xef00160e 0x6b41bfd5
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- 0x84d3e1b5 0xcc6d9201 0x95046196 0x276b527b
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- 0xe7cc826c 0xf87bafc7 0xeecaec10 0x8e60919c
- 0xbf14c996 0xd3dcaee3 0xb8fa0b7e 0x81563c6e
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- 0xb7e6872d 0xaf828cd6 0xc28d3316 0x2a91f6d0
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- 0xaf4f03c0 0xb4f4ee64 0x169e64e5 0x04653ac0
- 0xed51cb70 0xfeaff0e5 0x51dbf346 0x072a2407
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- 0xcd0a697e 0x5023db4b 0x33e6d8e7 0x44bbe6b4
- 0x827e859f 0x6ca4cc81 0x661bb2c3 0x71209ee8
- 0xb8c3ffaf 0xd1075f51 0xba1eae10 0x728b0a6a
- 0xe4af7a2f 0xca9bcf2e 0xb249a631 0xdce6be47
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- 0xea594a23 0x41b75c2c 0x3a401a95 0xd33cd88a
- 0xc295cad0 0x67f48045 0x1dc9ad4c 0x4bc48864
- 0x53991b6e 0x7aadde5f 0x2b0bf775 0x06ba5380
- 0x9eb874be 0x2c4b967a 0x1bcc342f 0xe875001b
- 0x15b5642d 0x5be99c9d 0xcb210ace 0x1b4924ad
- 0x3793ed81 0x8b983114 0x3ec33981 0x75ec71e7
- 0x8b5b7df3 0x834756f4 0x100fad01 0x70037fdf
- 0x0cef9a36 0x3d9e3a2d 0x38b48efd 0xfc4034b6
- 0xa32e29dd 0x388944bc 0xc1c15614 0x3877e9c7
- 0xa5e733fa 0xa621bd53 0x4b651df6 0xce082970
- 0x85f30d6f 0x729a5c87 0x31dd7ba9 0xdb495828
- 0x7b12c698 0x953495c9 0x6b5f99e7 0x2cc42fa8
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- 0xe3986de9 0x923a5c76 0x2ee9abca 0x1a9fedbe
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- 0x0f345c40 0x667517e6 0x860838ba 0x6dae933b
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- 0x64b413f2 0xd2c4145a 0x0b2c11f3 0xfdfe9f93
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- 0xf8a95268 0x9ed1ef87 0x9ae33cfb 0x3b21f1ef
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- 0x8393bfba 0x37438788 0x1724194d 0x8e77a045
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- 0xcb2959b8 0x10307e19 0xf71fbbfd 0xdda641e1
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- 0x5593c249 0x94561f51 0x534cc654 0xca7c8814
- 0xb59a578c 0x40b2b614 0xeaf3437a 0x198d5b4e
- 0xf245fa53 0xfb75e0b0 0xa363c46d 0xc43b5468
- 0xdf036413 0xc59f5a36 0xd8ff4381 0xa3af3e36
- 0x7af63462 0x414526d7 0x7bdc41c5 0xa416f1e7
- 0x6987d9ad 0x472c5499 0x4f10ee37 0x47bb7ff7
- 0xc7f2e621 0x820008f7 0x33a475db 0x91ff5d72
- 0x0517401c 0x73d067c8 0xe417b69d 0xb86d9903
- 0x1ac9a032 0x74bbf582 0x8b65596e 0x883be34c
- 0x95dcc26f 0xe232c646 0xfae9c19f 0x35cb5273
- 0x6a94d095 0xfff6ca91 0xb9c40eb5 0xd351dcac
- 0xc90d464f 0x9b609642 0x15663b56 0x15f7f88d
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- 0x6cff0416 0x343466f4 0xd121a7a6 0x6caa3942
- 0xe4f365a2 0xd832eb0c 0x616728e5 0xcca4c71a
- 0x4010cdc2 0xd0f1d1cb 0x5e695f89 0x27719206
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- 0xdde7aa5c 0x8f1a077f 0x110a4a5a 0xb3a5ad31
- 0xaacebf8f 0x66ff7f33 0xa2340971 0xfb4c7e82
- 0x8dd536d7 0xafd2021a 0x72aa9c6e 0x22df6952
- 0x83c4b4fb 0xba515555 0x93eee8f0 0x22d0ed5a
- 0xbec05586 0x83828f28 0xe0d7f930 0xac0f0199
- 0xef6d76f9 0xf56ebdf8 0xf67323c9 0x8b805745
- 0xce5902c0 0xfa2ce3da 0x10f836dd 0xe1ac6d97
- 0xa0e415ea 0xbb7c32ad 0xc421f3b0 0x8166e898
- 0x74e7a73c 0xf454b82a 0x631369b1 0xe30ed23f
- 0xdaa1c75b 0xe7c9c6a7 0x5f33c375 0x99c05187
- 0xf2d6e6ae 0xcd2045b8 0x92ff3009 0x15082015
- 0xd1a1580e 0xdce25f9b 0x21984a75 0xa9be5388
- 0x099a5372 0x3ab9bcfa 0xdb9069aa 0x49a99be6
- 0x42a9ee0b 0xfe32d832 0x24e11ad3 0xd16f596b
- 0xb95982cc 0x754ab1c8 0x42ffa128 0x539e823d
- 0x28e0f976 0x262ddfc0 0x2a16e7ad 0x49b5acd9
- 0x931f3def 0xdc419b84 0x8412cc3c 0x81056cd9
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- 0xcdd6d59f 0x24b984d8 0x8f1c5bcf 0x25bcef1d
- 0x00dc603a 0x76fd94c2 0xa267a7dc 0xa6e90a6a
- 0x5c5916d6 0x065a52cf 0xa28d3263 0x9b17b72d
- 0xb8436b48 0x1b1c2391 0x1fda3395 0xa6cecbcb
- 0xbc4ec502 0x1766b590 0x5945fbd6 0x6a124405
- 0xf92d06f2 0xe24694b7 0xf6befd08 0x8266cf5c
- 0x03ed670a 0x5f98be62 0xf27b7e2e 0x598cf22c
- 0x2e855591 0x879815fb 0x153799c6 0x3820faf6
- 0x3d3a2cc6 0xdbb6dece 0x1a3c46b2 0x5031bdda
- 0x47894c03 0xe43661fe 0x7a6ee548 0xa5ca9779
- 0x6aa9e105 0xbc8505a3 0xa03b860a 0x448faeb9
- 0x367de4a9 0xc9779c7d 0x6535ad8c 0x4b7fcacc
- 0xb2db5c10 0x0ab41ec6 0xe528ab90 0x5e6f03da
- 0x98bc76d3 0xf38df42e 0xea59b039 0x1c2eaa28
- 0xca30dac5 0xdb0eb8c6 0x60063860 0x18823f8d
- 0x164e2f28 0x7cbbe080 0x70a12315 0xb08f44d9
- 0x5fbb9453 0x4bc62738 0x9fa15ffc 0xe4033ca1
- 0xc9dfbc13 0x58245d7d 0x588113aa 0x8f5a6ac8
- 0x92588a60 0x26330c74 0xb2aaf0e3 0x24ada1ea
- 0xa9e973ae 0x624b73e7 0x4ef961db 0x95ede155
- 0xf2bb86ff 0x96bc79d9 0x95cd646b 0x1c3af453
- 0xf60fa711 0x10905115 0x0e24b740 0x169bb227
- 0x34cee6f0 0x990980db 0x18d8ace5 0xd4c87504
- 0x29515d32 0x2e5d9c04 0x87dffa60 0x12e815d1
- 0x021db8e9 0x2c5a42fd 0x6e3a1a13 0x88889ab5
- 0x3bc915a6 0x608919c5 0xd310a970 0xea8f3218
- 0x949f55bc 0x9ed7aadd 0x6d990157 0x181f1c2f
- 0xa940df64 0xf3be8c39 0x7ca2e699 0x7b4f07f9
- 0x89e83fee 0xe66b9493 0x54fc3d17 0xa63d2d46
- 0xd5e835d5 0x910e0144 0xecf67025 0x1fa6a93a
- 0xe692dbca 0x466af681 0xc2bc808c 0xbb4ebd60
- 0x74d5c729 0xa283ad25 0x1e66fa23 0x6d372988
- 0x753c9fcb 0x1742efdb 0x5b68cf15 0x372a0e33
- 0xaa3a7ebd 0xa0e944d5 0x95d5cbb4 0x4fb6020b
- 0xced927b0 0xb2afea78 0xd0646b72 0x1622fad4
- 0x4672c6b6 0x736ae4f8 0x8d46a4db 0x0e6a432e
- 0xe0a30a98 0x4c2bcf4f 0xd87acedd 0x19682d7a
- 0xf97c025c 0x55d8feb3 0xbcd4d2ff 0x236c6f9f
- 0x8ba0246d 0x42812f73 0x327636f5 0xc92cd30a
- 0x08a69d9d 0xc735a946 0x82eca01f 0xda0753a0
- 0x7077b1d1 0x17b05834 0xfa24bc02 0xf49f4473
- 0x8f9ac6b4 0xa880c630 0xf7457b4d 0xd5f829e4
- 0x25c49a99 0x1176a997 0xbb2d2009 0x61d35764
- 0xa322c752 0x6ef3ae02 0x5faae6f8 0x9a52acf1
- 0x19176f43 0x43843b07 0x14efc471 0xee474403
- 0x319c4857 0xa19adcf0 0xc0a466e1 0x02db14ad
- 0xb7f211f3 0x72aa6ca6 0x0eb9bffe 0x48a6d284
- 0x9a93a2ee 0xac09fc5f 0x92a62c4f 0xd34f0271
- 0xffb348c7 0xf229b6e2 0xc68ec1ca 0x19577dbc
- 0x069a10bf 0xf64ac347 0xf7c3c848 0x81975294
- 0x6376e550 0x93b53440 0x8bb17daa 0xc4c64c07
- 0xcaeff293 0xd51497b0 0x33da3565 0xa73d5def
- 0x4bf4dcde 0xfb470fcd 0xca7db864 0x7ef17022
- 0x47567363 0xd8fb8d74 0xa68c3c72 0x8202e4f3
- 0x75bf1798 0x16a70fd2 0xcc3b697f 0xab9a1075
- 0x13f56ef3 0x269d0302 0xcb655a43 0xc9a4de88
- 0xfb8363de 0xff40f36d 0xd2555489 0x647a7995
- 0xfd8eda6e 0xa3958c9a 0x20e029b4 0xbed3e225
- 0xa7df5f17 0x63bc3c1a 0x337ecc9d 0x6c329508
- 0x786aa47e 0x1db5b093 0xc0acd73b 0xf9587237
- 0x243e5d40 0xd3623c3a 0x338c4740 0xb672140e
- 0x43640a9b 0xb7ef3f6a 0x44151074 0x749bcc46
- 0xfa1f103b 0x0fefb19e 0x58855538 0x138ad276
- 0x2641fd80 0x297d99d0 0xfaa63ba2 0x00b6f11a
- 0x3793fb6b 0x124763a1 0x8b9419ac 0x56abf9eb
- 0xdbf83419 0x43570571 0x37299cd8 0x8b201e62
- 0xa4058fa5 0xb320e91b 0xbe7d40b7 0x4eca3b2d
- 0x8519c155 0xf4b17021 0x9e4c572a 0xdc1f9e16
- 0x39a589a3 0xa6cfc7a8 0x5b986910 0x64e150e7
- 0x60b6f2c1 0x02bacd3f 0x2f3b5a5c 0xc6f453a8
- 0x15a87a7e 0x76104a14 0xafa2ef63 0x2cd48dbe
- 0x3c7abddc 0xd786ea5a 0x4f65867a 0x355cda38
- 0x2ae03d9e 0x4f11f6be 0xfc0a0034 0xde4ea602
- 0x21ff83ea 0x0f12d913 0xedf4da28 0xc96d8fd1
- 0xd7e82c3c 0xfec63bdc 0x37a456d7 0x3007e18c
- 0x091a47b6 0x82f1c641 0x82219cce 0x3e7e6993
- 0x7b3a2115 0x0b8e1a02 0x40f88213 0xfa2f9c21
- >;
+++ /dev/null
-/*
- * Copyright (c) <1995-2013>, Intel Corporation.
- * All rights reserved.
- *
- * Redistribution. Redistribution and use in binary form, without modification, are
- * permitted provided that the following conditions are met:
- * .Redistributions must reproduce the above copyright notice and the following
- * disclaimer in the documentation and/or other materials provided with the
- * distribution.
- * Neither the name of Intel Corporation nor the names of its suppliers may be used
- * to endorse or promote products derived from this software without specific prior
- * written permission.
- * .No reverse engineering, decompilation, or disassembly of this software is
- * permitted.
- * ."Binary form" includes any format commonly used for electronic conveyance
- * which is a reversible, bit-exact translation of binary representation to ASCII or
- * ISO text, for example, "uuencode."
- *
- * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x17>;
-intel,date-code = <0x01092013>;
-intel,processor-signature = <0x000306a9>;
-intel,checksum = <0x3546450b>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x12>;
-
-/* The 48-byte public header is omitted. */
-data = <
- 0x00000000 0x000000a1 0x00020001 0x00000017
- 0x00000000 0x00000000 0x20130107 0x00000a61
- 0x00000001 0x000306a9 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x86c5b0d4 0xf6978804 0x7f4f5870 0x6319dc3c
- 0xbb3b7d61 0x33cf9075 0xe8424658 0xf611a357
- 0x5a3401db 0x42caecce 0xb4d8e75e 0xe6dbaf24
- 0x7861b35f 0x6bd717bc 0x23b9b731 0x82ec1ac8
- 0x20337b64 0x5396dbf1 0x59973bff 0x724bc7e9
- 0x5237193b 0x0b8647c1 0x6a0d0e16 0xbf9ddb5b
- 0xace2cc1c 0xad707638 0x056f102f 0xa37e60f8
- 0x76255642 0xfb86e030 0xb8069a40 0x367795f1
- 0x653fb05e 0xab7f14ad 0xb6e8a8e1 0xd2598d20
- 0x2eba3f68 0x78b372f1 0xba8d13f8 0x1f1de861
- 0x97f951d5 0x8097c728 0x27dbf904 0xb97906a8
- 0xffe7a4ac 0x4b947668 0xc1dbd726 0x2adcf777
- 0x63b1bcf0 0x818e2a1b 0x49aa907b 0x2faf5e8d
- 0xae842352 0x82707fae 0x0aa12b41 0xa0bae11c
- 0xb4298c47 0xd2b4099c 0x4ff625f2 0xcd2630d4
- 0x79850981 0x05dbf57d 0xb05b81a5 0x56e73ec7
- 0x95cb3897 0xe262bda5 0xb2c6e288 0xcb7f8e77
- 0x72b8bdd3 0x3f400494 0x63ade65b 0xbc4adc71
- 0x00000011 0x06c0f8ff 0x0eb63d77 0xc54cdabf
- 0x76bc8860 0xdd142643 0xe7bfc220 0x17aa0a91
- 0x4fd676ba 0x4b6b1a15 0x2a1a1c16 0x4fed6de0
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- 0xb830a38b 0xec25bc6b 0x61c8a8a9 0x49a21dba
- 0xfcf8bad0 0x7372f29c 0x1f7fbcdd 0xc2ff42f4
- 0x780878f0 0xc967068e 0xe19cc3c9 0x155e6646
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- 0xec34444a 0xb0594770 0xd7180f9f 0xa510a168
- 0x460563b0 0x5d4f34f4 0x21dfc16b 0x051de344
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- 0x1bf6a96b 0x77dd859a 0xda35335f 0x22fab458
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- 0x1bb2a34e 0x642c7653 0x0f536213 0x1f7ab4eb
- 0xaa5ef677 0xe6ac9581 0xd7a2fe73 0xd417dc79
- 0x455a6877 0xae825a40 0xe0c98bec 0xac39ba49
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- 0x1b005ce7 0xddb742ce 0x6c5f3ffc 0x24f74d2c
- 0xf4ace044 0xb21bc7ba 0x338002dc 0x240effa1
- 0xd208ae00 0xfe8c2b5c 0x9a457293 0xd9365ac4
- 0x98f24244 0xf6d1aaea 0x7b874350 0x1ba4086b
- 0x1d3bf168 0x2bb6f4fa 0xb27f8477 0x8da836f6
- 0xa8762693 0xc377fa64 0x74cfd979 0x90435c25
- 0x29d80e17 0xc3503c9c 0xaacd2178 0x232c748d
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- 0xfdd8c80d 0x01b0591b 0xf70bc4ce 0xb278c496
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- 0x2a4d5b8a 0xf7624bea 0x3fdcbc90 0xb5a66e35
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- 0x8e3653c7 0x34496b0c 0x6b2aeebc 0x2fbab601
- 0x105613a2 0x7babd55d 0xa01af846 0x248be690
- 0xed27917c 0x26ee6e13 0xa1dac5fe 0x852ed91a
- 0xfc83fcca 0xdf479c33 0xfd6efe96 0xdc62521b
- 0xa37d2a8c 0x1d2bad9e 0x4287614f 0xc4f7b62c
- 0x2aab0562 0xec6d4226 0x52853fb4 0x264e3507
- 0x1c3af366 0x33269776 0x81b8529d 0x115530dc
- 0xe035f98f 0x433d1b6c 0x1ea6daea 0xecfd2ad2
- 0xa57a0c22 0x1dbe3e12 0x6fafe41b 0x8e579e35
- 0x6c493fbb 0x034dd4f9 0xd17cd6f2 0x05c5cfa8
- 0xd9bffa39 0x0fc16e9c 0x831b88c8 0x7e7dce3e
- 0x3320bc7f 0xd5abafaa 0x217ab526 0xade2597d
- 0xf01b00f2 0xc9e34b72 0x00a4cb0b 0xdc198512
- 0xdc7cc8a1 0x89db07b5 0x6c2153ea 0xb8bdb8aa
- 0xdf8a1ae8 0xa517f6b1 0xd32569d9 0x37e79008
- 0x3c7527c3 0x7d5b2d3b 0xb31cb907 0x35db7f6c
- 0x0ab0cd65 0x75feaded 0x7c8260a9 0x5bc04f56
- 0x2fac9f60 0xd7b3a2c0 0x2b393634 0xc2df7f43
- 0x1ff2fa9f 0xc81af169 0x188b1f4e 0x08bf6f86
- 0x5ab2f188 0x0a71eb64 0x03b57501 0xa684fc23
- 0xa729ffef 0xe3b4a709 0xf9eb97d2 0x01506c95
- 0x0d9285f5 0x8e1ee93c 0x7d15a0d8 0xd9390673
- 0xf116ebd8 0x7e68798b 0x3dc8412e 0x5a9a04b4
- 0xe3805f51 0x00493bb1 0x4ec65ca2 0x2aedd69a
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- 0x422e7c15 0xb1732663 0x1ff404f0 0x2d5052b0
- 0x6e45356c 0x7e2201e8 0x7c5ebcd1 0x1cb4425a
- 0xb1539a64 0xa2e4459f 0xcf1ade8a 0xfc476473
- 0xf4147deb 0x2afbdd77 0xff01fabc 0x6597408a
- 0x0951220b 0x6750f3ec 0x0a242763 0xf3d71c05
- 0x84cb1c26 0xdb7a81bd 0x7aea1a5d 0x7e719a48
- 0xc5c12fe1 0x0ce2e988 0x29ecc6f0 0x5ede901a
- 0xda8399b1 0x31c05d6b 0xe1956aff 0x59ed7c3d
- 0x60832637 0x9bcb7cac 0x63c530d1 0x14c677de
- 0x9225ed18 0x065327c9 0xd1ff6a0e 0x5516517e
- 0x53c6f5c2 0xed5983cf 0xaa1d18b9 0xbe300d7f
- 0xadc525a7 0x07ea81b6 0xfc517a09 0x4ead3f86
- 0x45435f41 0x2efa58df 0x02348ebc 0x30ed6783
- 0x190b4fb9 0x85c55d6e 0xc9ed8896 0x416ee113
- 0x9b3536d9 0x30577cc0 0xbc4b88c8 0xcda59612
- 0xdfe2bd89 0xd60cde71 0x98843881 0xcc1f32f2
- 0x18b3f643 0x671a14ca 0xd6482a47 0xac6a7d38
- 0x1897da16 0x91b6fcb3 0xf199bb35 0xd38c00ba
- 0xa8c946b6 0x52a1ad37 0xd38ed2d4 0xa1d6f81d
- 0x5af6865b 0xebdb858f 0xb844b110 0x53201ea2
- 0x08870945 0x10c869de 0x19849613 0xdb35d3ed
- 0xd68ebd6e 0x1056fd48 0xf1a0e305 0xe3982ebd
- 0x6f7cc391 0x5956374a 0xf414a5a2 0x325119ab
- 0x99ee1f96 0x6f044bd9 0x8374805b 0xb55c366c
- 0xa2c77051 0x68f199e5 0xd36a9714 0x878f847b
- 0xec0394ae 0x86d0584b 0xf4df66b9 0x451cd039
- 0xf4de06ae 0x35dd0554 0x818a342f 0xeefdbfc9
- 0x5b4e9edd 0x22d9313a 0x3b710d60 0x6deaeb4c
- 0xa9e26512 0x98d31867 0x3c2c2d61 0x7eb5ce41
- 0x40890db6 0x7a3aa660 0x3ef4f306 0x7322881f
- 0x49dac4d5 0x96efe685 0x27bb7f49 0xbb955283
- 0x79c5f2b7 0xff599c28 0x28ee7f5e 0x9f324b73
- 0x45edb7cf 0x39a8b79c 0xd0919c6e 0xe149b29d
- 0x62f5f82e 0xebcfa23e 0xd4d68937 0x54270090
- 0x958af0d4 0xa1e4e799 0xaf68ac19 0x82a84f4e
- 0x50f67b84 0xd5e59629 0xf5fdf24c 0xab1d63c5
- 0x30835807 0x431fce5f 0xe5f96f4d 0x3f6b4802
- 0x14010be8 0xdca45ae5 0xc82709af 0xff76ce2c
- 0x8b222c22 0x73a2d948 0xa8d59cea 0x8c31849e
- 0x469c2e5f 0x3777ee84 0x5fdfa5da 0x02ef9bb2
- 0x792d3194 0xbed63f21 0x0b6dc5f1 0xc9d7fe08
- 0x6df7883d 0x366566cf 0xef772769 0x37826465
- 0x1cdc3086 0xa69ff7b6 0x235012ea 0x292f7e75
- 0x30bdd0fd 0xffdc9df1 0x95c6d570 0xec206204
- 0xc6cd42cb 0xc0d6dfd9 0xb7a16b71 0x17fa527e
- 0x295f2c79 0x990f9820 0x8b8f447d 0x193f9ad1
- 0xebddb2af 0x5dd532eb 0xf1bbd8e8 0x3444a3f4
- 0x18ccce93 0x05edeb4f 0xc4a6b935 0xba37aab0
- 0x96076ba4 0x250dc2f7 0xc4093548 0x030e777d
- 0x7ea40933 0x8da7b1dd 0x59c0b79f 0x807d437c
- 0xf5233ddf 0x54c1983f 0xfc18771b 0xe74b85f0
- 0xdbd725b5 0x70cdd153 0x4ffe300c 0xfda4bdae
- 0xf4ac75d2 0x91c4e15a 0x34d92b97 0x16356a79
- >;
--- /dev/null
+/*
+ * Copyright (c) <1995-2014>, Intel Corporation.
+ * All rights reserved.
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * .Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date: Sat Sep 13 22:51:38 CST 2014
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x105>;
+intel,date-code = <0x7182011>;
+intel,processor-signature = <0x20661>;
+intel,checksum = <0x52558795>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x2>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x05010000 0x11201807 0x61060200
+ 0x95875552 0x01000000 0x02000000 0xd0130000
+ 0x00140000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x05010000
+ 0x19000000 0x00010500 0x15071120 0x01040000
+ 0x01000000 0x61060200 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x9557a557 0x7d7a0fe3 0x8e2fbe53 0x0db9e346
+ 0xd35c00d6 0x21bb34b7 0x662b6406 0xa0425035
+ 0x3d028208 0xcb843695 0xee06be0a 0x9817efa7
+ 0xb86c0d16 0x45f70c93 0x79fdc3af 0xd5f30da7
+ 0x460f62b0 0x238a0470 0xf0ec95bf 0x97b9c176
+ 0x6d612851 0x69b9b4b6 0x1df769cc 0xe11674df
+ 0x1b579adf 0xc8bcc050 0xcdb3e285 0x327592c1
+ 0xbeb6047a 0x977f6be5 0xc4854052 0x27f38b66
+ 0x4ca5eab3 0xf806decc 0x2be4b409 0x460a3b03
+ 0xde2f6e0f 0x53ce08b3 0x3ef0ef93 0x4e013088
+ 0x226f8a5c 0x57f7d291 0x8d640bf7 0x8a998907
+ 0x40464dd8 0x804ef3e5 0x647e35f3 0xeabee2d1
+ 0x3a5ce9c7 0x4d7ee530 0x564321ec 0x9e85107e
+ 0xd595581d 0xcbf6efde 0xed3010ed 0x3d607e82
+ 0xe32d4b6b 0xd06fec83 0xf39240a6 0xe487988d
+ 0xddbefcbe 0xefaf1121 0x96bf9acb 0xacce795c
+ 0x7fa5f89b 0xbe440e5d 0xb6d3a3dc 0xcad17290
+ 0x503ae748 0x04c80b8d 0xd394ea6a 0x3e4072c3
+ 0x11000000 0x0b0ae65d 0xc6c53cbd 0xd52a6c2d
+ 0x84cc192f 0x89498e7d 0x89270686 0xe68105e0
+ 0x4073a570 0xd3338d8e 0x51193152 0x7266182f
+ 0x980553fa 0x51b89c90 0xd13b6151 0xe6e40a91
+ 0x0ab997d8 0x2d0a443b 0x9d3d566d 0x820402d1
+ 0xdbe79fcc 0x7c5e0b45 0xaf94216d 0xbf717950
+ 0x520b3dd4 0x566a3396 0x0b6f794f 0xc5dfeda5
+ 0x71ba0f02 0x4839a5ed 0x39a4e4a6 0xe567c652
+ 0x0e044997 0x84a0effd 0x09c67178 0x89a815c8
+ 0xac821555 0xd6719303 0x582b964e 0xfe3a53f6
+ 0x241b9b8b 0xc6e65457 0x623a4e0a 0x590d7d03
+ 0xe50e7ce1 0x4bca4700 0xf24f5eff 0x1f1b20d9
+ 0x77e3227e 0x699b5e5d 0x9aa5f621 0xff08bba0
+ 0xf17ce716 0x0f5336f5 0xbce055a7 0x8cea9dac
+ 0x8e09d26c 0x66c3ddf0 0xbec71660 0x75248cd2
+ 0x29afcf8d 0xa5ade5ce 0xf68bace5 0x63b513cd
+ 0x4736a842 0x4dbf80df 0x4e85fbdf 0x4dce3d56
+ 0xf2150fdc 0xc4232709 0xffdc3e3a 0x92b72a3d
+ 0x9ffce715 0x682959d1 0x091ba33c 0x0f1dc729
+ 0x2f29a924 0x1df72429 0x19b0365d 0x2d5a3cd8
+ 0x20617351 0x109074f9 0xf232874a 0x40d79569
+ 0x97dbe4c6 0xa3b66845 0xa04d2faa 0x6dce9a96
+ 0xd4963c67 0xd4516f76 0x64a0b04d 0x0b87ddfe
+ 0xd8a5305d 0x717ecf67 0x77189035 0x40542ed4
+ 0x5a180ff1 0xb2042e2c 0x6639819b 0x0f0756c3
+ 0xf939bd70 0x25efe0d6 0x3eb65ae9 0x39a057d2
+ 0xb2595655 0xf808b4fd 0xe22d0593 0x76256500
+ 0x0eeee6ee 0x6895d1cf 0x9fc117a7 0xd19e5f15
+ 0xf677f085 0x1ecdb30d 0x704d0975 0x9099f42e
+ 0x421be0b2 0xd02548bd 0x3a16e675 0x7d8b051d
+ 0x9d24480f 0xbc006432 0x184da9ec 0xbad7abef
+ 0x299f58aa 0xc1a249fa 0x8d9d31f3 0xe73cda17
+ 0xf41ac993 0x7b88d3bb 0xf349c676 0xb8341361
+ 0x1b69bc01 0x98e0bfd2 0xf31db8d9 0xeb49b275
+ 0xabc40133 0xfb7d0701 0xcd5ff353 0x4eaceb8d
+ 0x67aac555 0x6d81693b 0xe81c555d 0x5d7f3688
+ 0xd4347083 0xcd861b1d 0xd332f2cb 0x43130028
+ 0x7f1a1c51 0xe2ce3af2 0xdff5076e 0x6ef21237
+ 0xf65fc8c4 0xbd28ff14 0xd70f49a3 0x4f559249
+ 0xd6fe7530 0x1fe89b4a 0xc1cc8975 0x2fd705c5
+ 0xf2993d77 0x60f2e3da 0xe3ca3c44 0xbd0f70b1
+ 0x0d333d10 0xa29a6aa1 0x43b5a6d4 0x30d15a08
+ 0x6df9564a 0xea09045d 0x54ca3f5a 0xfbcfa037
+ 0x6dd64d1b 0xa4a8995c 0x1f4298f0 0x3f4d9a86
+ 0x924ee146 0xc2e3f464 0xc247747f 0x8bf5c7d7
+ 0xf8f0b05d 0xf65a115f 0x4b1ae4e5 0xe131e187
+ 0xfaf713c1 0x5ff88660 0xcd4916b0 0x448028e0
+ 0x140711ca 0xffe77575 0x8b7740bd 0x82b6ed95
+ 0xd94d9647 0x2623c011 0xd54fba11 0x30a7050b
+ 0x28fe4069 0x70b8bf7d 0xf786eb6d 0xe39db734
+ 0xa3290669 0x8747e1d6 0x35804a42 0x1c26ed60
+ 0x30a8880f 0x8170a277 0xa1d97657 0x6ebcb3ed
+ 0x3bb6ce89 0xff808c1b 0xc919fd1e 0x911d8b14
+ 0xcbf41a24 0x82abc738 0xfb5e988e 0x328aa123
+ 0xf19146e3 0x587baa80 0xd105e811 0x83b09389
+ 0xa29fc554 0xe3831a28 0x183f8de7 0x4ef5656e
+ 0xcc940baf 0x938bf4b4 0x90627bae 0x14fc3cdb
+ 0x75e45681 0xf912c1b3 0x7a5b8a0f 0x3b970524
+ 0x6a74d34a 0xb3da9fe6 0x847a3bd8 0xfc4f7dd6
+ 0x88fd7f3b 0xbcd74a15 0x3afed836 0x17e31cd0
+ 0x5d866dcb 0x0ab69608 0xe334f0fb 0x7181d4a3
+ 0x8dc87560 0xd9c94d6f 0x491c2c91 0xca295ed6
+ 0xfb8dcd79 0xeb4d3f89 0xec581071 0x0457ebc6
+ 0x6b63590b 0x9dde4b79 0x3dc0a0aa 0x41ec8a1e
+ 0xfb2ab80e 0x07adc629 0xb8534a4f 0xd0d23901
+ 0xcfd024da 0x47c4163a 0xc89d26bb 0xe5cac48c
+ 0x17c7fbba 0xd992f42e 0x466f5e35 0xce48304e
+ 0x394683c8 0xef6e6b7a 0xb9d1242d 0xb961debd
+ 0x432a3dff 0xa4931ea7 0xd9f03907 0xc29e9ce6
+ 0x4fccf4c9 0xbf234555 0x0b6a6771 0xb29f29ef
+ 0x7edc4bfd 0x781dcf74 0x4ae31020 0x1ab72d9b
+ 0x0ac457e2 0xf9291e09 0xd4084918 0xa540d999
+ 0x223408d3 0x0bd039aa 0xaf0dd904 0x9cfd6a01
+ 0x826c6bca 0x8e41a96d 0xa56fc4ee 0x6a7509fb
+ 0x5cd2e6fc 0xb89aa158 0xb1e5d3f5 0x92ccd05e
+ 0x995d5acb 0x5ed1dc08 0x75038dac 0x4377c835
+ 0x265d66d8 0x3692096f 0xcd69ee59 0x310df351
+ 0x087e3133 0xe89e2d58 0x137fd054 0x00f3562b
+ 0x2ae304e5 0x9db0316d 0x6868cec6 0xb249ccec
+ 0x9f602c90 0xd3715e7c 0x3fcc8a62 0xa1c1e065
+ 0x5b4281d4 0x124dfd7e 0xe9d21462 0x77cbc940
+ 0xf915f2a5 0x66df82fc 0xa8c67c56 0xac4d461b
+ 0x836deb52 0x95fbb48d 0x3454b6bd 0xd87d7a64
+ 0xe64d32b8 0xc44c2aa0 0x3e213c1f 0x4d31b94d
+ 0x4640be5e 0xe127234b 0x9ca54856 0xac7d093f
+ 0x03d0508b 0x30f5121d 0x6e347d91 0x47772312
+ 0x318ea26e 0xad3f6902 0xb5598746 0x8be3b65b
+ 0xc8bbd31d 0x24691564 0xee77d2e8 0x3581944e
+ 0xeff8eed5 0xa29ea86c 0xc2597492 0x23c1c118
+ 0x7810c079 0xb966ee47 0x823e9954 0x9e558c0a
+ 0x74759c12 0x193c6b4e 0x7544597d 0x65c9bf8a
+ 0x68f5e263 0x718c679b 0xc8dc50ba 0x5f5ab841
+ 0xc3eaf579 0xc2072358 0x62481939 0xffe7e686
+ 0x201f3215 0x1d88dc8e 0x28fb4002 0x40c56ec5
+ 0xb7bcce00 0xd52f5042 0x84498e04 0xcc97fb7d
+ 0x64035e93 0xcd3478a4 0x15d63309 0xa9e47b85
+ 0xe835e45f 0x9de598b7 0x94f569f7 0x56689b0c
+ 0x381f9173 0x708b3e52 0xc81f0649 0x12113041
+ 0x4694aae2 0x69040fc0 0xe4ba7bf4 0xfadc5729
+ 0xc168381f 0x1985f118 0xab0ca720 0xf0150799
+ 0x42690e4a 0x71af3be9 0x9325f3b8 0x36575996
+ 0x4dc1dca7 0x7e534c37 0x01830a21 0x221eef4f
+ 0x18698322 0x57a80837 0x483ae2d8 0xef905b54
+ 0xe01827de 0xae9a8ff1 0x0058be7b 0x052632ad
+ 0x9df5c90b 0xb763fc7a 0x5535c95c 0x8eb5916a
+ 0x75fde5cc 0x57d8eeab 0x0dcc35c6 0xbf11c88f
+ 0x69142118 0x4f35c928 0x7966066c 0xb2d13b4b
+ 0xdad06d34 0xb5d8f5c7 0xe0bb11e6 0x8a36325d
+ 0xc1122d64 0xcf07a1a5 0xfe7ce9b1 0x176b624b
+ 0x4de883fd 0x00a9024b 0x3d3f7271 0x5072895d
+ 0x2634e158 0x2f3c9a35 0x95e374d1 0x65e66528
+ 0x47766433 0x4cb805ff 0xbc8f0319 0x6d5055a5
+ 0x4932e8c2 0xa93fbb4d 0x87f08bd9 0xf5e5706e
+ 0x409af40e 0x017edf5c 0xc5394c71 0x6fb97b6d
+ 0x7b5ddb6b 0x0256adfe 0x76d337e2 0xa3327113
+ 0xfbb4cb29 0xea68ca27 0xa76a865e 0x8cdb2dd3
+ 0x902642bd 0x16772269 0xb2341eaf 0x858fa943
+ 0xb087fac9 0xd17de85b 0x3d9c248a 0x0bdcf2d0
+ 0x874fc03c 0xf19f2591 0x190c06a9 0xc6b5c3ea
+ 0x472b6245 0xdb9f8201 0x46d27a0d 0x52218ffe
+ 0xece78c44 0x3ef6e38a 0xfcf19b65 0x536c840c
+ 0x86d363e8 0xaa852826 0xde17e3ec 0xa9c3b45b
+ 0xd322302a 0x48f03728 0x2f60d01a 0x3b356752
+ 0x8a869fd4 0x055d04f4 0x765074fb 0xb0b5c2d1
+ 0x865ad360 0x0cb6c6e8 0x5de9cf99 0x863938d3
+ 0xd4d9aeea 0x0babfa86 0x172cfb57 0x972d8f4f
+ 0xe9aeeb95 0x6acbe297 0xf2459e42 0x415fdd12
+ 0x84b2e67b 0x47d2d466 0x44bc85a4 0x1a55b957
+ 0xe4d01142 0xbf4ea387 0x5651e1a2 0x19124703
+ 0x8aaed1b2 0x841f3ecd 0xc6d6cc4f 0x1f2d8565
+ 0xba08e74a 0x68e5ecf4 0x07af5ef4 0xdd5a43a9
+ 0x6086c705 0x37ced045 0x0fb05ca6 0x35f39f3b
+ 0xda1ecbef 0x1daf6d76 0x5481d7ed 0xc51e8385
+ 0xa705e11e 0x127d2a7f 0x654d4710 0x1a34370e
+ 0xf8496ea4 0x4392b6ec 0x2f209933 0x9c5ab017
+ 0xa4f7b837 0x33e0a7d0 0x98fb0635 0xdefc042a
+ 0xc7a1f6b5 0x47107766 0xd06acfba 0xb8ac2a93
+ 0xe21cca44 0xf0150492 0xd4de2e01 0xe0d6e9a5
+ 0xa758b5df 0x2e1c31c0 0xc4794495 0x3d9cc157
+ 0xf94aa4f7 0xc2325855 0xcf9ddd12 0xaa70e611
+ 0x2b2404b8 0x75d87f38 0xa2a6f772 0x61abfa04
+ 0x23b61fb0 0x87f4067f 0x355abf99 0x2c4e6c48
+ 0x2dc8a3b2 0x119b08b5 0x3f1f6d09 0x374372f0
+ 0x24d79d32 0xef2b58be 0x461ab91c 0x1d31267e
+ 0x8b1b2c7e 0x27a4f103 0x1686c7c3 0x55af0d87
+ 0x61c2503b 0x9ffcca7f 0xc3cbdd07 0xd49a4f3c
+ 0x9ddc2ac9 0x335e1b2a 0xd8dcfc08 0x6e83f11c
+ 0x53de9e30 0x7b774670 0x15a97571 0x1ecacf66
+ 0x26581520 0xeee3496b 0x1fdf8174 0x4ddd3c61
+ 0xaa504fc2 0x0b09792e 0x9b81d1c7 0x10765c95
+ 0xd3e7b9d1 0xefdb38f9 0x4c44d38e 0xaaf8fd08
+ 0xceb22e7c 0x5ac74242 0x6baee02d 0x5c7eaa5b
+ 0x27265dca 0x614c3b5e 0x2994874d 0x486d48a3
+ 0x5945c4f9 0xe465f343 0x934e55de 0x633199a2
+ 0x147222cc 0x9bbb0c16 0x6a7e7ef1 0xb7bce9b5
+ 0x13413d18 0x628231af 0x0fd2d58c 0x4cbafba0
+ 0xa930fae6 0x91733823 0xe06f99c3 0xda3b57b7
+ 0x04b8a9dd 0x53451e33 0x11fde5fd 0x0e35bcb8
+ 0x3a5799d4 0x3893f9c0 0x6b9d0e1d 0xf8d948ce
+ 0xa33a6628 0x7d09792d 0xd74b3719 0x0afb4de0
+ 0xfaa5a685 0xecf7f8ac 0xcf34b855 0x89453b4d
+ 0x12f028c3 0x45edc3fd 0x792c43fc 0x2b054962
+ 0xb8799a92 0x0ab38d61 0xa6c6a76d 0x7670cdbd
+ 0xf878b511 0x9a3474ba 0x478673f0 0x7398bba8
+ 0x4fa10ff5 0xf0a1931c 0xd5938e03 0xe9a23c28
+ 0x7bea2a5b 0xf7a8db22 0xb94ae0e3 0x2abe6385
+ 0x0ef2cc36 0x6b997544 0x1e8cc4f1 0x69a5b182
+ 0x54f9b7c7 0x8fe56cba 0xc7c12fcc 0x8d689865
+ 0x2d6ef011 0xc6a1b740 0x66af0a76 0x76018cdd
+ 0x30661377 0xcf1fcf93 0x08046423 0xdf9371c8
+ 0x1795ec3e 0xf5ea09c6 0xe462de69 0xd7da78a1
+ 0xd8bda1eb 0x1179f53a 0x2b394767 0x3ba153a7
+ 0xf9c85bd7 0x5700c827 0x8478ac99 0x080a2f52
+ 0xdd1c18f1 0x579cea67 0x345c56ce 0x4563f16a
+ 0xfa1a5b74 0x0b6e233e 0xadc7bd9a 0xbee6d2f0
+ 0xa249f3ef 0xcdea9b77 0xeaaed82e 0xcc4448a7
+ 0x34f7cafb 0x7621bb44 0x4965b0eb 0xe6d6b8bf
+ 0x3c683b25 0x33bcb5fe 0x3f376249 0x5b40dc67
+ 0x658bf6aa 0x7f0c5d0d 0x61514591 0xeb3bb83f
+ 0xc2e208dd 0xe82f08f2 0x6ef75ae5 0x9c11bc0d
+ 0x289c0553 0x1578ce5d 0xb7f05c0e 0x818c5ebd
+ 0xe566ec9b 0xc6995b3f 0x0c02aac3 0x2b4264b3
+ 0xf9cad304 0x5b0479fb 0xf8ce8d6f 0xb7d80d8b
+ 0x41a0d223 0x71ec8a7a 0xc9d74d41 0x245c5988
+ 0xf607fc59 0xf1c7b6ab 0x142ef712 0xbf607800
+ 0x281e5911 0xad9a3e63 0x87b59384 0x7ebdc04c
+ 0x6f47867b 0xb6a304ac 0x289f65e7 0x335fc866
+ 0x77eb11b3 0xb70c25b2 0x70b43d52 0x684d46c0
+ 0x0940459b 0xde739ede 0x0b438a29 0xb713e77e
+ 0x71f539b7 0x8b2f0f7b 0x8d8ab95d 0x42cde8c9
+ 0x08c259d1 0x021eda69 0x2af81ddc 0xc7d13028
+ 0x05abfa20 0x6a61008b 0xfc62557f 0xd6d731b2
+ 0xb080aca3 0x6acae4a3 0xab33d2bc 0x7983c177
+ 0xdf0c357d 0xb8dcb956 0x9c214460 0xfeb75d75
+ 0x9b3d468b 0xd2c3106c 0xb1bd118e 0xf26df6a8
+ 0x11b9c4d2 0x031357f9 0xf7af8a12 0x70fef26c
+ 0xe5d8b8d5 0xf6746fd8 0xd6cc3266 0x4158e59f
+ 0xa38fbfcb 0x01c61ff6 0x44c7c4e6 0xf26db3aa
+ 0x46bb6d84 0x0a794535 0x1d5eab72 0x42345de7
+ 0x0c7e6d47 0x8bacc223 0xb7334b8d 0x3d9d951b
+ 0x18f4afc4 0x9c0cb708 0x53b71b82 0x603e8350
+ 0x6f2df978 0x0c6f3f0f 0x661ebca9 0x30788bd0
+ 0x982959c0 0x50aa1351 0x672297c1 0xa490a756
+ 0x21c9e911 0x977e172e 0x0446db50 0x49b711c1
+ 0xbc6d54c7 0x0fe0adb4 0xc4ec0fe4 0xae6d09b6
+ 0x316cfa53 0xba68cc8b 0x104bdbe9 0xc31639a3
+ 0x812a97fb 0xa1c6884b 0xc884d473 0xe3057c15
+ 0x5ee879a3 0x5abe8262 0xb906bbde 0xfd98fcbd
+ 0x6ae15c96 0x44a17e0e 0x28acfa15 0xb345122c
+ 0x6ddc4244 0x005eb369 0x22d038bc 0x0d226e4f
+ 0x64c7ed6c 0x7964b8d9 0xbc5d668d 0x99155e56
+ 0x9979151c 0x65312a00 0x0271d338 0x64867293
+ 0xed0d26fb 0xe69c5f02 0x93fd6871 0xf5702656
+ 0x4fad1c2b 0x20f8c272 0x438b964a 0x87ff3fa2
+ 0x6706537a 0x437b5709 0x6fb797dd 0x85679fab
+ 0x00da6b51 0xeecc5540 0x2998791c 0xc36d40ef
+ 0xb545e334 0x9ace5e06 0x8a9e6c54 0xc341d0cd
+ 0x1478a2d4 0xb81413bd 0x80601f72 0xa1b250b9
+ 0x1cb7f5ce 0xefad630c 0x32325fcc 0x29e3474d
+ 0x6a7ae043 0x879ee630 0xdc1e8a55 0x7ae794a8
+ 0x4ee38039 0x2ff4947a 0x53bb84b1 0x8f0b077d
+ 0xaa4c543b 0x9aa88443 0xeb31a017 0xf3485983
+ 0xe53b855c 0x6e17aec6 0x726458a6 0x5acf4345
+ 0xa1b95c5a 0x30668c67 0x47fb5dc7 0x8aafbff4
+ 0x4b94ef01 0x07bd6231 0x544afcf3 0xfdffca2f
+ 0xce847471 0xe90abc6e 0xf05e3cc1 0xf602a9c8
+ 0x8f104b51 0x1ae3da07 0xd07dfc04 0x561d9373
+ 0x6f6cc833 0xac982489 0x3c0f8afd 0xfab974d0
+ 0x397e135e 0x8edb3eb4 0x452b9509 0x3972829d
+ 0x639e3981 0x1c758ec1 0x11428fa5 0xe8308fa7
+ 0x571d71b9 0x94e40c2b 0x1aaaa397 0xce9283ae
+ 0x599bbb93 0x51c04bf7 0x556bc74f 0xf6e6e799
+ 0xc34191e0 0x5f06bce6 0x9f63ecd1 0x54437905
+ 0xf8f9bd50 0xde82cbf6 0xe11a9949 0x9d312bfa
+ 0xe712e3db 0xb57eabc9 0x57682068 0xc91c2e3c
+ 0x681e4fbd 0x0ecd3452 0xcc893248 0xf13f0600
+ 0x9a8a9194 0xb4c1cd29 0xd504d8f2 0xee6c5b8a
+ 0x211c9958 0x7a4f9c30 0x32775708 0xda97bf03
+ 0xf7035e57 0xbe77d547 0x37accd1e 0x6c537775
+ 0x8d63b752 0x7fec4a3c 0x94211d9e 0x60bfeb2a
+ 0xebd47130 0x747d52fc 0x8434f487 0xac9091cc
+ 0x8f8b228f 0xb77f96a1 0xc21fede9 0xa9e2678a
+ 0xbc815194 0x54d677ac 0x66c11faf 0xfb666595
+ 0x01e5e973 0x5c990d0c 0xf2cea425 0x5b516ff8
+ 0x8c932784 0xd18feb32 0xb5acd3d3 0x1703b89a
+ 0x34fb512c 0x0ac83386 0xd58c5728 0x5c018ed6
+ 0xbe0908a0 0xd490b0e9 0x0ec94527 0x2f281499
+ 0x471df723 0x03eddc08 0x9b99d975 0x11535b70
+ 0x5802288c 0xb3512d42 0x415a9c0d 0x52dbd146
+ 0x8b0c59bf 0xd8160cc7 0xe37dee6e 0xfd5211cc
+ 0x5635ff4d 0x8d783398 0xc11f5d62 0x54ca73b4
+ 0xc3ebdf96 0x835e7883 0x9cd03137 0xe4b4f709
+ 0xdbde6d86 0x2b562b2d 0xfecc0df5 0x172a5ec2
+ 0x568b52b9 0xf542957c 0xd738b325 0x49c49aaf
+ 0x6eb4c9ad 0x363f4978 0xac4b0cb3 0x4ec8dca8
+ 0x7a2ec2ba 0x10ff39bc 0x8b8748d5 0x6a86e67b
+ 0x0d81e2b6 0xf4bde138 0x02249333 0xab0c7acf
+ 0x4ce5e894 0x1656dad7 0x46c59329 0xa849fea0
+ 0x3d0400be 0x6898c4f7 0xd866ff9a 0x84a5b170
+ 0xc997009e 0x80524f6e 0xc80fb5dd 0x5bde0181
+ 0x0bb0c8a8 0xe5a6b9e4 0xd4753f0a 0xda9bf0c6
+ 0xd6dd041b 0x4c7338f0 0xa223bd71 0x23b58f4a
+ 0xf6e127dc 0x1777033d 0x5b057a0f 0xe08af0bf
+ 0x17c07032 0xbbc3f27f 0xac6dc98b 0x921e2f12
+ 0xcf32236d 0x6cb700a8 0xa3b4e5cc 0xe9b65d73
+ 0xca7d6f44 0x7b5917f6 0x7b80dd21 0x5ee87e45
+ 0x86799f71 0x0667e036 0x8f97dcca 0xc4bfd5d9
+ 0x90737eed 0x41b5a457 0xc6c96301 0xf8933e95
+ 0xe51c2456 0x00c661f4 0x8a0e1aaa 0x92aa4181
+ 0x1e3f8638 0xd481a14a 0xaf637189 0x91622fb3
+ 0x4450865d 0x4202b431 0x5248342b 0x01ff713b
+ 0xe33b5ec5 0x912d6856 0x10deb2ac 0x9072c180
+ 0x24d792af 0xa39c5dfd 0xb4c94140 0xfeb32004
+ 0xa174dae8 0x49da7dfc 0xa4db1090 0x7d2a998b
+ 0xb7eba69b 0x9b824871 0x3557bd1d 0xd3a73d9b
+ 0xf225310b 0xad1ffcf6 0x2d5f075b 0x592de6f4
+ 0x69e438f4 0x4ed8cac4 0xa79c947f 0xb95f9590
+ 0xb8ede5c9 0x0b1c9229 0x85a4b30e 0x65149920
+ 0x433461a8 0x186fda4f 0xbaee7097 0xd3cac1bd
+ 0x8bc32ca2 0x914f1512 0x9b619478 0x582a53c9
+ 0x4e624a00 0x77e445ec 0x6f823159 0xa9c4766b
+ 0x0dd6ad28 0xfabdadc5 0x704bfd95 0x08645056
+ 0xe1939821 0x76650b62 0x8876941a 0xf812239f
+ 0x2869ce13 0xa4d292c7 0xecba40fd 0x83d2fd8f
+ 0xdd45ccc0 0x7c12b7cb 0xdc0a20bb 0x0d9be34d
+ 0x4dd16a9d 0x25835446 0xb94d8c21 0x97ca8010
+ 0xddd09324 0x95ffe31f 0xa86136c9 0x828ac571
+ 0x9aa7fc00 0x382cc48c 0x015f7186 0xc3fd040d
+ 0x505408e0 0x21cdc34c 0xbd266059 0x6e2f673e
+ 0xe4523c1b 0x3ba56bb3 0x1c343938 0xabc0df54
+ 0x8ba4f1e8 0xfbd4c592 0xb678c884 0xff3be2f1
+ 0xca013570 0xfb0598df 0x3cb9cc1d 0xe3ba8ca3
+ 0xc3d7ecee 0x0ae84a0b 0x0d70f0c3 0x963110ff
+ >;
--- /dev/null
+/*
+ * Copyright (c) <1995-2014>, Intel Corporation.
+ * All rights reserved.
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * .Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x29>;
+intel,date-code = <0x6122013>;
+intel,processor-signature = <0x206a7>;
+intel,checksum = <0xc9c91df0>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x29000000 0x13201206 0xa7060200
+ 0xf01dc9c9 0x01000000 0x12000000 0xd0270000
+ 0x00280000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x29000000
+ 0x00000000 0x00000000 0x11061320 0xd1090000
+ 0x01000000 0xa7060200 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xd1090000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xfd2a2f68 0x82ac7ebb 0xa4916328 0x7480b81b
+ 0xd329a777 0x25750339 0x9a8f7a9b 0xf1da9cb8
+ 0xb1be7b1a 0x621d5a35 0x94b57e2e 0xa9def809
+ 0xe4492a43 0x530252bf 0x1040fada 0x8a853a89
+ 0xfb0e6e76 0x6d191ed9 0xefd28b83 0x946414e5
+ 0x13f415d5 0x28487029 0xb69855e8 0x516cbedc
+ 0xfabbea88 0x9f90e8a1 0x211793d8 0x54653835
+ 0xa7789a08 0x754791d9 0x484764d4 0xdca45615
+ 0xf64844f4 0xdbd754d0 0x7d2b0ff3 0xd023e25a
+ 0xb048bbcb 0x83038b5c 0x57e17d17 0x735f1e9c
+ 0x8982c22e 0x6c7b2ad7 0xb26e3b82 0x7121e035
+ 0xe4ea8dba 0x68d4f406 0xaaafdb13 0xf119b472
+ 0xb5853303 0x20698005 0xcf34604c 0xdc17d19b
+ 0x042d6e97 0xf0300325 0xe1b55072 0xc2804918
+ 0xd6d7a912 0xf908c81b 0x4f9979ae 0x0179f8c6
+ 0x2f13e3c0 0xc5911467 0x39ad6c23 0x9c9d8837
+ 0xf3c3f767 0xe56b4a96 0xdad7cebc 0x6eaaee57
+ 0x2215ca7b 0x4cee4f65 0xd9a51c2a 0xf33c80a1
+ 0x11000000 0x0b468bda 0x0b57c7cb 0x885fad4b
+ 0x8a37307a 0x68cc7d5b 0xb6395b55 0x583626b8
+ 0x21efe98d 0xa516cc42 0xf5b978b1 0x585d8a11
+ 0xdd5f2ee4 0x17b1c7eb 0xb6f005ea 0x9ecc6ac6
+ 0x82c0f1b2 0x25a114fb 0xa6086296 0x93da75f4
+ 0x0695ff88 0xd413dd65 0xccf7609e 0xb7718aa8
+ 0x334406dd 0x28de253f 0xfb43ca83 0xa4674656
+ 0x7392e05f 0x9b062c62 0x17571892 0xb5811cbf
+ 0x9d64666b 0xa01c1500 0x5893e418 0x07ba6ed1
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+ 0x167c42e3 0x0c0cd705 0x82756ce5 0xe81ba860
+ 0x536c357c 0xc27433fa 0x41c8078f 0x1ff779d0
+ 0x73ddd76d 0xe606c66c 0xe0ad45bf 0xfebdc310
+ 0xcb2aa836 0x39903a79 0xe53d5dc1 0x0cb6a1ff
+ 0xe6091d08 0xcb2961d8 0xd38987ff 0x2bd624fd
+ 0xfb4e484a 0x8c60efbb 0x0ed088b5 0x5a142b04
+ 0xa737bab1 0x44da29a2 0xc046ecb1 0xe7ccefdc
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+ 0xdb4927f7 0xa229106d 0x6a7db273 0x8ac6a901
+ 0x00a87e4d 0x14fd1e2a 0x63a5fa87 0x5ca223c5
+ 0xc0c980c1 0x42c447ef 0x5b274187 0x75bd6279
+ 0xdb44dae2 0x60856af1 0x777caf5f 0x298e810a
+ 0x93f4f418 0x9e1ddf3f 0x6f589046 0x18ea149c
+ 0x4a5ce4b0 0x529db285 0x3c2dde59 0x1d680e51
+ 0x3a62d819 0xdf4c01d2 0x432a8f06 0x70a37043
+ 0x4a0d4baf 0x0d3395be 0xfce0391f 0x5228aac2
+ 0x9dd9b00e 0x6149f393 0x6fee1d85 0x1d3628cb
+ 0x107076de 0xd99fe940 0xa227eec2 0xc97d8119
+ 0xcf2fa8b2 0x821dac93 0x518875f2 0xd18d1d47
+ 0x3e27fdcb 0x47823f98 0x20d42c1e 0x9a58812b
+ 0xe0987435 0x1426f12f 0x61d6f627 0x5c58d415
+ 0xe5ca80de 0x9e11e526 0xbccc0f94 0xb49cec4d
+ 0x357f947c 0xbef0e2f2 0x5b9b2596 0xddc87ff7
+ 0x5f2705f8 0xa25f2be7 0xbb45a165 0xe49ef6d5
+ 0xe76e250a 0x75584c7d 0x7900da7b 0xee0e3360
+ 0x6988740c 0x4aa56944 0x2d485383 0xef45f5d5
+ 0x0df4b0f7 0x48199182 0x5b33c21c 0x8f2483c1
+ 0x8aae6c50 0xaf406ccb 0xb7522bda 0xeafb64de
+ 0x9a9b1fd7 0x3ab46c34 0x0ec5f025 0xe5bc9668
+ 0xdb108e78 0xd6152ac8 0xc382ec93 0x5abc2565
+ 0x4f256030 0x856f6eb5 0xb589dc96 0x3de80942
+ 0x49d20a05 0x8e3ac21b 0x0262ecc7 0x5f1bce89
+ 0xec50198c 0x0115b078 0xf67d94e3 0x1cc3682b
+ 0xfb2d4ab0 0x4d6ce252 0x1d7aace9 0xf7e99257
+ 0xc1235e85 0x8129ee72 0xb6cfbb13 0x6b851ab5
+ 0x430633d1 0xe9ed33e9 0xfe85a42a 0xb4583c0a
+ 0x35a65f5e 0x5fb0bc81 0xe16db440 0x7d022cf2
+ 0x8f832920 0x20ed9ad4 0x6a4ace8b 0xf4c85869
+ 0xf17dd57b 0x277ae0d5 0xb5f59c50 0x35d099a5
+ 0x9ce955ae 0xcb200000 0xcedc4073 0x2a2ba8b2
+ 0xa1b53439 0x46ced775 0x59069604 0x6488f5d8
+ 0x2bc0af55 0x643178a2 0x36f62be3 0x2606f0a1
+ 0x3057cf8a 0xc28f4a3d 0x708e8020 0xb3fccf9a
+ 0x29b79fa7 0x35622d93 0x85eb0e68 0x80fa3b59
+ 0x143f340f 0x20e17166 0x169fe55d 0x698f3655
+ 0x0bc8b45b 0xde3aaf6c 0xbd597266 0x75505401
+ 0x44d0095d 0x4c00f346 0xfb9ef2c6 0xee70ef96
+ 0xae807621 0xfbbe7490 0x9c0a283e 0x01a8058d
+ 0x1be53568 0x0b8dc8a8 0x45afb745 0x3ee1ff58
+ 0xe772e14e 0x3ca4e729 0x6973e751 0x764f244e
+ 0xca8d1621 0x6c4fb15c 0xae972e6d 0x3d26c6d3
+ 0x5ca8f450 0x6328d65c 0x2e7cd88c 0x87dddcc1
+ 0xcbbdefc6 0x1ab8c0cc 0xd21e503a 0x20c11d27
+ 0x2f0adc1d 0xc24240d2 0xc73aa069 0x99afc53e
+ 0xcab27e40 0xbe107ccb 0x8ad5f0ae 0x9024c188
+ 0xe02bb39d 0xdb784309 0xf91acb54 0x4d15b75d
+ 0xd339c237 0x3b556619 0xf69f91f6 0xca6fcfd4
+ 0xb5ddf471 0x0698490e 0xb0855c30 0xe2b34b13
+ 0x3c979248 0xc0484a59 0xb4cf9f4f 0x7975f2ac
+ 0x602259d3 0x89364c24 0x37f29913 0x0b4c88a0
+ 0x23f0b663 0x309c13d2 0x80a3d12c 0x4c866e87
+ 0xea7e29c0 0xbc33db6e 0x3c3af584 0x63da0de7
+ 0x9bc6bf5f 0x3b948269 0x4d41b09b 0x5724dd20
+ 0x4e16618b 0x5917781f 0x4bdec762 0x562cc3fd
+ 0x50e59d92 0xb3edea05 0xa6ceaa68 0x60af473d
+ 0x78a99aca 0xd60ba313 0xe502992c 0x0c25c2ba
+ 0x476eebd4 0xe7e23958 0xc4ac2757 0x0d6695ec
+ 0x7664b4f0 0xb87ed0a5 0xdcf23b2a 0x76d38802
+ 0x21699284 0x87b80e7c 0xf0e34f45 0x4bb84bc8
+ 0x0316744a 0x26de0ed4 0xb25ff5e3 0x31445bb1
+ 0xaccc5b87 0x271b976a 0xcdf5663b 0xe142d271
+ 0x1af28339 0x7d304ca4 0x11ee6243 0xdf70fbc3
+ 0xb8d88f25 0x4c2d9626 0x8eb72c77 0xceee1817
+ 0x4e1b35f7 0x6c261f67 0xa32a2801 0x67ace2af
+ 0x7c87f8c1 0xca6f2505 0x982269dc 0x137080a9
+ 0xe40fa78a 0x3897a66a 0xdc5d0ff7 0x58016e44
+ 0x21bcc988 0xf2a4df15 0x9fb021d4 0xca59e882
+ 0x3673d08e 0x7cf5d500 0xd41ab9df 0xc17b4a58
+ 0x2cb85aa3 0x01103427 0x5a8fac5b 0x7ac856b2
+ 0xb1532563 0x1b94b518 0xadea3bfa 0x597109a9
+ 0xf28df608 0xc2bf64bf 0xf517bb53 0x61b7d5ad
+ 0xa4a38e9d 0xa9fdc597 0xf990f2f1 0x00466640
+ 0xcecd06a7 0x5eef09d3 0xb67a08ae 0xd780d8a0
+ 0x07641a71 0x9dc9f7b9 0x5f0b5a44 0x94dfe40f
+ 0x6db0cf7c 0x3fe72d11 0xb2443ea3 0xe051f336
+ 0x4ec8a6a4 0x11201430 0xb44e2b28 0x5bd018b0
+ 0x444ba2bf 0xa63031eb 0x147f9826 0x3fc56ac1
+ 0xd3a75ad3 0xc3f71815 0x340bd72b 0x3e5a488d
+ 0x0cd8fb05 0x17791534 0x68e7321c 0x1489c701
+ 0xa39f2d71 0x7cbbd9f9 0x42cba365 0x024f7d9a
+ 0x29ef2da1 0x1eb9c4e6 0xc8b24985 0x9c33412c
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+ 0xfef28251 0x41e36ee6 0xd91e2c20 0x7698357b
+ 0xb3684b1a 0x272311be 0x32860f75 0x44a6cc61
+ 0x63e3f66f 0x5a1497b7 0xeddf5a57 0xcdd4577c
+ 0x3cc63cd3 0xf7e72773 0x3fc9bb40 0x97ce4118
+ 0x1438da68 0x7a32210b 0x2aa07598 0x04e858ca
+ 0x850e0082 0x0b0f78d1 0xb178c391 0x9a2e231e
+ 0xa8f3b67b 0x2a08ea99 0x340d101b 0x42973ffa
+ 0x755ae5cf 0x201213c4 0x445e44f7 0x15a872c8
+ 0x857b94f3 0x24c023ab 0xb203df2a 0xc4711de8
+ 0xd1faaeea 0x1eb857b6 0x8c1b712b 0x11ad0f2a
+ 0xc64cf474 0xff6c128c 0xff13eac3 0xc4952e8f
+ 0xacdac9d1 0xb8c2f092 0x38d50a33 0xaeec4534
+ 0xa661a7ee 0x4d19a2bd 0x0f2d95e4 0x9a221827
+ 0xc9fe071f 0xe53486d7 0x1dc5426c 0x848eea4c
+ 0x607f616b 0x41a301f6 0xeadc389c 0x1f109048
+ 0x249f14da 0x2a20d362 0x7c93cd00 0x7ca633e8
+ 0xe50fb5a4 0xace8f92f 0x49638c89 0x478b4371
+ 0x60d70e8b 0x0bfb8bfb 0x6cac803d 0x702996e4
+ 0x15a35d2c 0xd68a2d93 0xe025d5ee 0xd8ca8c86
+ 0x295393d3 0xce1be3f8 0x0ee6bd15 0xd6735f38
+ 0x311495e6 0x7eb8bc83 0xea53551f 0x4fa9a90d
+ 0xe16a9ea0 0x651eb233 0x95f0afec 0xc687ed29
+ 0x0cd3abc8 0x132bb8b4 0xd70dadd3 0x538e630a
+ 0x98481e4c 0x0d7e6f1b 0x3986b2de 0xbe0924dd
+ 0x1d14608e 0x189f553e 0x7a6b7786 0x48bae520
+ 0xed56a3cf 0x795b4c6f 0x8670597a 0x40eb02ab
+ 0xf9b0b287 0xec9f86c3 0xe9a8c3a1 0xe6860542
+ 0x387ad930 0x8676e402 0x633f0709 0xd661d134
+ 0x011c1396 0xabf1f3f5 0x3fd76128 0x7be75289
+ 0xa6046e69 0xf3713680 0xa2ed30c5 0x893df28d
+ 0x197b8543 0x9860bef6 0xf6930c5c 0x6c0c379b
+ 0x0b0026e1 0x3ca86896 0xa7ea0bdc 0xca94413f
+ 0x6cbe8d16 0xd3e4edf9 0xb06efcef 0x3a8934c6
+ 0x00195592 0xa978bf0c 0x7435b0d1 0x3b17d97c
+ 0x0438684e 0x576ced8e 0x648683fc 0x362a8a87
+ 0x493fd86f 0x6bbe0476 0x16f74de4 0xbfeaaba8
+ 0xe6b90728 0xdc252878 0xe0b72eac 0x0872f52c
+ 0x2bab1521 0xa6c0d894 0x9f2b3726 0xd392e334
+ 0x785f82ce 0x15bba4af 0xb55cd743 0x6e8e9cf8
+ 0x047fd2e7 0x1fdfe424 0x8d4820e5 0xce7dd8c3
+ 0x88c82282 0x31ef9a76 0x1881fc38 0x3932a9da
+ 0x65bbfefb 0xe00f33b6 0xdd0754aa 0x1f596051
+ 0x704dfd7b 0x2604be1b 0x08b6c4f5 0x3f244085
+ 0xd89c65e3 0xcc4cdb71 0x143a2681 0x1bd3d004
+ 0x009460ff 0x86e314a5 0xb1aff86f 0xaa2599df
+ 0xbf68de69 0x355c8267 0x9588dbed 0xe47edd9b
+ 0x266b2ddd 0x129b0b01 0x6e6622a6 0xb3ea4a00
+ 0x802abd6b 0x7a268c1d 0x9f5a7b41 0x6f4aba0e
+ 0xe279b988 0x660ef08f 0xf4207beb 0xfa0168f6
+ 0x93266ea0 0xedfef092 0x302b5e5f 0x7278d2be
+ 0x58a494ab 0x8f53a302 0xf5e766de 0x1ef717bf
+ 0x45e2d6fd 0xf593b066 0xaea0f1e1 0x1bd1e027
+ 0xf853ba21 0x1127c5c4 0x8aa43b18 0xf1fba0b8
+ 0xe1cfb0b8 0xa9f9fef6 0x1320f1ab 0x5f7dfc74
+ 0x30f11ab4 0xaf47a3cc 0x9c190830 0xac085edb
+ 0x8b4db7c8 0x771ec065 0x6d5f3c3f 0xb8815437
+ 0x20d3c99c 0x00823c74 0x24d63cae 0x7587e453
+ 0x1a3fd67b 0xa5b361cd 0x789d168b 0x98a93943
+ 0xd7505c0a 0xa923b38d 0x46097a4f 0x814e41dc
+ 0x0f50f2de 0xbb548368 0xc48273d4 0xf27b6798
+ 0x9a6b5231 0x68491e7b 0x3f482179 0x89ea3b35
+ 0xa7525ffd 0xf8f1f616 0x07859572 0x738cb4b3
+ 0x8937c6dd 0xf5988c71 0x4874905e 0x677a8c17
+ 0xd58df987 0xc4210078 0xe6b1c480 0x7a91e14d
+ 0xa1228a7a 0x09057467 0x6cd59ec7 0x6ba93248
+ 0xb8e263cb 0xd3305730 0xaec36ee6 0xc773d0b5
+ 0x2895f8ec 0x6c9f5fb5 0xd32a21a5 0xcea9d058
+ 0xfa97282f 0x5559ceb4 0x5a0bf57c 0xf3cd99b5
+ 0x2771f6c4 0xfcc9a35d 0x5143417e 0x7c6f9db7
+ 0xb47cb7df 0xe7dde37b 0x70a07531 0xe25e06a2
+ 0x3bbb7d30 0xaf41b085 0xe664f973 0xee2c7ab7
+ 0xef8eb1b5 0xfba67f7d 0xd71568dc 0xbbff3339
+ 0xdf49725d 0xbc0e7edc 0x5361e6d3 0xb0978c73
+ 0x1320540a 0xa9843a06 0x34099c74 0x4bdddd23
+ 0x18680496 0x44f9cc19 0x6de71a34 0xe4eae858
+ 0x3349a819 0x28400571 0x10a55fe9 0x05672399
+ 0xb376eadd 0xed4b1a35 0xe79d0a4f 0xca8d0601
+ 0x78a7b066 0x8ea59a40 0x7be112a2 0xe99ea438
+ 0x44bd9efa 0x6e5227a1 0x70325aef 0x777282e9
+ 0xb579c189 0x4ee92bc9 0x0d0236dd 0xb57cf232
+ 0xb815e184 0xd05823e4 0x0c9490b8 0x70a5fa56
+ 0xdf0f178a 0x99d27374 0x1aba9e05 0x18378c3d
+ 0x86991118 0x3a199a70 0x90b2a2cf 0x67a6923b
+ 0x0975e5f2 0xf50fb0a3 0xbffbd67a 0xce6371e7
+ 0x203564ef 0xb1d7a395 0x201cb1c4 0x30085e3c
+ 0xfb2c66b4 0xf80ae969 0x1d407625 0x0bca1a0f
+ 0xb62c078f 0x83efbf38 0xbd7b0a69 0x7d9bb66a
+ 0x46b5c885 0xb256d753 0x0b5d008e 0x1756d5bf
+ 0xa9ffdaf6 0x01231fcb 0x8c69e461 0xbb2ad661
+ 0x29dee8f7 0xf1f23d56 0xd5e90ffa 0x48d9d93e
+ 0x77b26e95 0x49c47953 0x7565da8e 0x41a6124a
+ 0xfce69643 0x55f99554 0xa5501d6e 0x5738b726
+ 0x4c989c96 0x93cbe27e 0x20ff3d38 0xf4787a09
+ 0xfa3520e4 0x26b2dc11 0xb701c94b 0xcd8857ee
+ 0xb4b07229 0x0bbcf1a7 0x3d31cd32 0x08ced413
+ 0x3da04c1d 0x7bdf1787 0x344f510d 0x53a02e8e
+ 0x7e295418 0xa5ed24b3 0x3a5a2c98 0x34947e44
+ 0xb398bfcb 0x7c0ea498 0x18db3289 0xec646beb
+ 0x2e8ed766 0x5aff9ee3 0x497dc7fa 0xa70c3be4
+ 0xfc9306c4 0x729f532c 0xd87d61d0 0x635fadbd
+ 0x1efb1234 0x66fdb543 0xf5b86d07 0x3a4836fd
+ 0x9caf7dd3 0x8a9d9e5b 0x179529ac 0xa9a3fee8
+ 0x4cfa4495 0x791b8b7a 0xc503fc2b 0x1e07d0e5
+ 0x0561cfae 0xb5e7c403 0x0809744a 0xea84c654
+ 0x23614fd6 0x23ae773f 0x545be2c5 0x3585b8b4
+ 0xcad8b6ed 0x088a56c0 0x81054caf 0xecb13d9f
+ 0x44bd49f7 0x90a3da4a 0xf4b04300 0x32a2b69f
+ 0x44bed501 0x85cb54ef 0x85dde589 0xe410132b
+ 0x1c2e41c7 0x3d28cc9b 0x4df948de 0xaa058c37
+ 0xb82cf615 0xfa0574f8 0xd0391f5d 0xfb2b98b3
+ 0x3ce5585d 0x80ca4d6a 0x4b138f75 0x721ccc65
+ 0x496a3e37 0x4a8dd025 0x2d77b3db 0x65800ff3
+ 0x1d2df03e 0xb4b12a59 0x4c6a5b9b 0x17413fda
+ 0x4e938a09 0x7e3aa03a 0xf86cc8f3 0x972cd7b7
+ 0x871849b1 0x0c0879d2 0xc7c652a9 0xe9531ae1
+ 0x541142d9 0x4f731afa 0x9c43e538 0x866b695d
+ 0x4a4c4076 0x1e8aa293 0x51bc1eaa 0x5f57d28a
+ 0x142eb7f5 0x14096954 0xae0e9eb3 0xef732983
+ 0x70187474 0x3569b88a 0xfd3a3c61 0x54f0e2d0
+ 0x7afff032 0xa89cd23d 0x658114ec 0x434ccbc9
+ 0xc25f33c7 0x1b6e9a7a 0xd97bd017 0x3b7489d7
+ 0x67129c97 0x333ee180 0x04bf73ae 0x4731105f
+ 0x09d589f9 0x7d5a67a3 0x3e8fcb8c 0x2090c536
+ 0x14a623c0 0x21a247fb 0xe117bbe6 0xe98bbd1c
+ 0x09e23674 0x02f09f22 0xba7f9f45 0xd18573b6
+ 0xa6eb18fb 0xe01a7904 0xa8869f58 0x82ec81ee
+ 0xf4549f1a 0xfa0f6085 0x1cf809e9 0xe603d078
+ 0x13525306 0xd5611c7a 0x2c92b32b 0x5fdc0c0a
+ 0x0b3aaced 0xa40059b7 0x27c42499 0xcc619db5
+ 0x9f9b7841 0xfdca5eb2 0x2d3e833a 0x2830a6a0
+ 0x4c81f3b0 0x3ec8a8bd 0x50b95605 0x33a9d515
+ 0x7fe14795 0x4ff1d83d 0xef92fbfe 0x87f4faed
+ 0x35d5fc69 0xd8764a49 0xec81abfe 0x634a2ed8
+ 0x9635825a 0x0943624c 0x5eea8464 0x578e2344
+ 0x551bd5af 0xca02915b 0xea419d8c 0x9d0fa00e
+ 0xf3633f48 0xc6ad62ae 0x1eeef6ab 0x21ab106a
+ 0xe325954d 0x60457916 0x6ac9168c 0xea8a9d6f
+ 0x14772361 0x7630452f 0x8795e1de 0x21144d8d
+ 0xe7996dd2 0x45aff64a 0xfa62c37f 0x3f5a04cf
+ 0x250f988b 0x7985d243 0x1f717008 0x7908d22f
+ 0x4fc0d5d5 0x856d9819 0xccfab84e 0x3fec2a74
+ 0xe75c1af6 0xe2682ac3 0x2f08e560 0x7133d2a0
+ 0x63e5fcca 0x3a17438f 0x9cb826c8 0x06a2f3cd
+ 0x4bac2001 0x50596ba4 0xe74758d4 0x64d17e0a
+ 0x08fc5b67 0xb0d62f6e 0x95eb8e15 0xd51bfa64
+ 0x421c68b9 0xdd1526a8 0xfb7ea10e 0xab21193a
+ 0x4b1186dc 0x77bbfd82 0x1ab08e9f 0x871659a5
+ 0x1658fd5f 0xa04f322d 0xf50ed273 0xb8d411a7
+ 0x8056489c 0xfbd858ae 0xd70f7d88 0x3c5cbc78
+ 0xf53ec2be 0x1d2228e2 0x8b53aace 0x212454d9
+ 0x76ea1d2e 0x9ca66373 0x9f6679c2 0x51c48b56
+ 0x47348811 0x8abc0a27 0x60050980 0x5d290483
+ 0x7ea8504f 0xde186466 0x91219d4c 0xa73144ed
+ 0xb5f36fa4 0xa37912b8 0x02625bd3 0x3bc2d9ed
+ 0x2e623844 0xa9a751af 0xf0ba18af 0x4433e06e
+ 0xca7cda24 0x686c9163 0x86a437c1 0xf8c17120
+ 0xed50542e 0x62b61fa1 0x600e47b6 0xdff86df8
+ 0x77502dd5 0xea5d75ac 0x095a06e4 0xa18efafd
+ 0xfbd01eaa 0x27a1cb0a 0x3dfcab8e 0x07be7250
+ 0x086cb680 0x2c1ddcf4 0x6fa79784 0xcd874edb
+ 0xa383d520 0xa5c0d1cd 0x2e09cd9a 0x34d645c4
+ 0xf6b9b98d 0xe8e80ab0 0x39b78c60 0x6098b6f2
+ 0xc3c13e53 0x88c9fd83 0x60c9e766 0xf49c4c2d
+ 0x79e3d3d3 0xbfade7d5 0x6ba57dc1 0x3069e3ad
+ 0x59632e2b 0xb86e871e 0x2dd63287 0x9704b283
+ 0x343a6cb3 0x37d7950d 0x283f262d 0xd49d5f75
+ 0xdacc49b7 0x5952e045 0xc0fefa19 0x69effce3
+ 0x5b2a3c0b 0x3757339f 0x18584f8a 0x77a80760
+ 0x5fcdadc0 0xc9b4df80 0xfa521be0 0xbcfc8ecb
+ 0xfd3f8eb8 0xbee4739a 0x139caf94 0xbdea1cd7
+ 0xab158240 0x233fd8dc 0x8ec63274 0x34eee6d8
+ 0x4603b2f8 0xae544fc5 0xcd444551 0x2b2b349a
+ 0x0a562524 0xb2e02518 0x577b1125 0x8b3c1ff9
+ 0xfd27d88c 0x2ad77d04 0x1f82a54e 0x20254fdc
+ 0xee8e63cf 0x8df3fa2f 0x9ffc7c43 0x421ae12f
+ 0x9b166441 0xb74a5a4f 0xdad0511e 0x0a8ee5e9
+ 0x8fe86041 0x37ef90ea 0x3fcf8380 0x87288691
+ 0x384b8b8a 0x98d8a45f 0x995443d7 0x6c617236
+ 0x9a40f76f 0x9f30733f 0xfdbf3927 0x7b4c0281
+ 0x9e87e64f 0x9802938c 0x65f9de31 0x829c3eda
+ 0x0a1d2f4a 0x22e0e854 0x30045b70 0xbf84a44f
+ 0xc2c30b57 0x47c5ff90 0xaea87e93 0x99c69ae5
+ 0x1080e89f 0xc2896e80 0x09ba0cb2 0xd16ee263
+ 0xe05337b0 0xef1d8359 0xc1d4b102 0x08620117
+ 0x2e4ab2bf 0x05dc3af8 0xc7ab866b 0xeee05983
+ 0xd0a00c19 0x96996791 0x75ac6042 0x29001ada
+ 0x13440a23 0x2b1eca42 0x4cddfd68 0x81a98384
+ 0x6bcda226 0xa8594443 0x92f26e53 0x434de4ec
+ 0x07596ee2 0x4c8ea6ed 0x5596054d 0xaffe0ef4
+ 0x6dc1ab64 0x20bc006b 0xad4e3933 0xe6df0d3f
+ 0xfb3ca9ee 0xc2895a4e 0x8fed0d43 0xa5ed7985
+ 0xc364f083 0xc397a806 0x7b651ff9 0x1d7e22e5
+ 0xfd02f57d 0x5f16a429 0x8612177a 0xd36b8983
+ 0xd87b0303 0xeaa632b0 0x57dff2b2 0x19772dd0
+ 0x51317bfc 0x28404b1f 0x9e35d818 0x9c771bb7
+ 0x6d42a5c1 0xa6030578 0x9c844d5f 0x95d5eb7f
+ 0xdf15f5ec 0xf0f8c86e 0xf8ebfd20 0xae32d9b5
+ 0x4ce2b066 0x776f0149 0xda8a429f 0x0e895a79
+ 0xbe62c881 0xf9c051d8 0xcaa48f97 0x9e8dcb1b
+ 0x69cafc21 0x411f1bff 0x4f4d71dd 0x102cf709
+ 0x974ebe53 0x7373aea6 0xef2a7ec1 0xedabaccc
+ 0xdac969c4 0xe010b562 0xb6880570 0xa7a7f5d4
+ 0x3c6464f2 0x96dea774 0x1614a588 0x06074080
+ 0xb37304f0 0x99da7dda 0xd3e36214 0xb27b7cae
+ 0xb4cef0b3 0xa435dc77 0x9d1c1a15 0x616993f4
+ 0xb8a5ec8f 0xdce1ff5a 0xaaea14c4 0xa5d2172f
+ 0x90c8c636 0x49c0b81e 0xff9db895 0x4252b336
+ 0xd420b5ce 0x87b35be4 0xae32bda2 0x441092d9
+ 0x321e8583 0x7d863719 0x3c888147 0x3f2bb9f6
+ 0xd1daf5f1 0x682f2ffe 0xae62e280 0xcf8f928a
+ 0x4a7237f5 0x6f3a55af 0xb91dba98 0x9b83b723
+ 0x0e857ed8 0xd5ac567d 0xaf8bf791 0x23f8269a
+ 0xe369638f 0x6a88edb1 0x5ff0be07 0x5c02b513
+ 0x7d22f89e 0x2f865c08 0x9cc0d56e 0x31c87205
+ 0x420508f2 0x95a21602 0x04d838e3 0x353353e8
+ 0x7ca1feb6 0x61c6f7dc 0xf78a68eb 0x918f2ac1
+ 0x413037a4 0x09692d1c 0xc8eceb54 0xb1bf975a
+ 0x2ab63552 0x467bceeb 0x408bf024 0xeaed2b31
+ 0x3255158b 0x8d9c6617 0xe450350f 0x615cf5f3
+ 0x1a7fd744 0x27a0da59 0x43298211 0x77392298
+ 0x9511e81a 0x08a2c2dc 0x3d6f1113 0x967e6586
+ 0xd1726b35 0xb9292da6 0xaa6f8ad4 0x0f13b47f
+ 0x34b96cea 0xebd9487d 0xfe533d60 0x41bcdc60
+ 0x364c8c79 0x32be8bb8 0x1395ead9 0x9e85e474
+ 0x146b6fbc 0xc93267cf 0xcdda98d4 0xccfb2835
+ 0xe779dbd5 0xf9288237 0x2073e129 0x16fe4ab8
+ 0x34ca576d 0xac313eb7 0x5deb3b4d 0x1727510b
+ 0xc168a414 0x332cd921 0xe38e8123 0x9a2c1aef
+ 0x80f5d1d9 0x7c88c923 0x8af17577 0x59ae1408
+ 0xffa5e565 0xb418ab13 0xdd6376aa 0x45cd70d9
+ 0x3c3a06a2 0xbc555669 0x34d1fc08 0xc2aa934a
+ 0x385416e2 0x91ceeadb 0xe06c9cef 0x0394dbd4
+ 0x43e7c657 0x296d7621 0x55dafcba 0x808b836b
+ 0x61c41f0c 0xd9689bc5 0x3a531ffd 0x8417ed30
+ 0x3f3f8616 0x641eb4a9 0x24964006 0xe8d2612a
+ 0x3b916d7c 0x5603319f 0x29007523 0xc9c7dc1c
+ 0xd1f7212e 0x22ac1932 0x05c39a5a 0xd55081ce
+ 0x589ae996 0xa998fcbe 0xd8df5512 0xef7d7a01
+ >;
--- /dev/null
+/*
+ * Copyright (c) <1995-2014>, Intel Corporation.
+ * All rights reserved.
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * .Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x1b>;
+intel,date-code = <0x5292014>;
+intel,processor-signature = <0x306a9>;
+intel,checksum = <0x579ae07a>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x1b000000 0x14202905 0xa9060300
+ 0x7ae09a57 0x01000000 0x12000000 0xd02f0000
+ 0x00300000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x1b000000
+ 0x00000000 0x00000000 0x16051420 0x610b0000
+ 0x01000000 0xa9060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xc2b13ad8 0x6ce74fea 0xd364ad12 0xf6404a69
+ 0xc89041e4 0x217fa2f6 0x6ff6e43f 0x79cde4eb
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
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+ 0x9f4e950c 0xb9a1546f 0xe718f140 0xc75d5d02
+ 0xabe66af2 0xecc54d7b 0xb4373489 0x22254496
+ 0x4b4b7f7c 0x40dde60e 0xfe621a3e 0xa6605c67
+ 0x5cf6a3a2 0x75df88a3 0xbf0749b0 0x705a0a04
+ 0xf3cae078 0x392bdebd 0x98878e65 0x0f5a2be5
+ 0xec172835 0xf610cc90 0xac6ff369 0x0a71c173
+ 0x8eae2d62 0x2ccbb630 0xd3b702ea 0x1626bfff
+ 0xdb4a6975 0xd2a936f7 0x0bb63194 0x5d9120dd
+ 0x5860e04e 0x3baeca91 0x95a621db 0xa6d23aaf
+ 0xfebcfa2d 0xa5ed89cf 0x2192280a 0x72322cb8
+ 0xd79e14d2 0x0528ce06 0x1c6a8f9c 0x6703407c
+ 0x93819694 0x6c554390 0x7875452a 0xf45d2757
+ 0xe0458d1d 0x335f6179 0x48989cc9 0xdc16cec8
+ 0x9e2c0ee5 0x78daabe2 0x2069e8eb 0x0e87f238
+ 0x0a928dda 0xc66e14b3 0x2a6c4031 0x73821630
+ 0x8b8c4a40 0x243702b7 0xded80901 0x5de34802
+ 0xea029b73 0x59a47771 0xe747d796 0xe80aea8d
+ 0x0bd01815 0x76fe1f68 0xa345fc34 0x73737383
+ 0x76753b6c 0x57dcba56 0xb11d6b21 0x81dc371e
+ 0x311f4ea0 0x3b4b2522 0xe8a66ef4 0x1932df0c
+ 0x9f3790d6 0x0d0478a3 0x7dd0a24b 0xeb581381
+ 0x6fe8ff06 0xe34c2d69 0x26842e15 0xe9a39562
+ 0x78f2d7d1 0x79ab33f5 0x197df69c 0x38a9a004
+ 0x9391dba9 0xfbb4b7c5 0xa97bb70f 0x0720b57b
+ 0xd9b26325 0x3ed1a3fc 0x11f5aba0 0x6e6a53ef
+ 0xe2ce236e 0x30994468 0x9d4369cd 0xcb6b5b5c
+ 0x61a0945c 0x090e7dea 0x5d9b676a 0xd474cb52
+ 0x8ebf1af3 0x35f2a70b 0x417d48a0 0x45062dcc
+ 0x841d8d90 0x30f8e590 0x1c935ad3 0x29313e0c
+ 0x46ecf673 0x4998b596 0x95f23529 0xf31bd581
+ 0x1b32045a 0x90432d28 0xa2a6c268 0xbf40fcae
+ 0x4104b314 0x02677221 0xa99231ac 0xe28abada
+ 0xd7d72a73 0xf1b2ce4c 0xf753f8be 0x9d7fc1c7
+ 0x9a0e7a7a 0xf04ccf32 0x58433f5f 0xab9a6d51
+ 0x71262b1c 0x48f84d91 0x897670bb 0x47dd10cb
+ 0xac7ef74d 0x78dc3e54 0x30b17eaa 0xc8f46618
+ 0xc636fe3b 0x86ac06e3 0xfb8edd16 0xed357170
+ 0xbfd34bf8 0xaeb9571a 0x4eec6a50 0xe881a1b7
+ 0x8a1cbbde 0xc6c077b6 0xaeda1441 0xf990296a
+ 0xc91e87d6 0xad0ca921 0x855537b6 0xfc0da57d
+ 0xf8427d87 0x9ece7413 0xc5d4b4c9 0x2fca7822
+ 0xa1888443 0xd3bf617e 0xab21ce7d 0xe63b5f53
+ 0x828501c5 0x81a39da9 0xb8cfb4c6 0x6b23b8dc
+ 0x853fe425 0xba262321 0x34f11b05 0x8044aea4
+ 0x67a3f99d 0x51e8afb7 0x04efcf27 0x7773f9ff
+ 0x8abceec1 0xd75d87a2 0x7e30d774 0xdd7a42f2
+ 0x2ca6ad73 0x27d4e62f 0xbc228d26 0x035a7713
+ 0x5dbcc13a 0x792a97da 0x56cf9fc2 0x5906fa3e
+ 0x97a3147c 0x85e59863 0x19ad1f49 0x1af659a8
+ 0xddc6a273 0xd254a195 0x44d83a00 0x3b7c5fa7
+ 0xcaf756aa 0x68ad08b9 0xfc57da12 0x3b278f24
+ 0xbd165574 0x3cf597ca 0xdeb872ba 0x543eb2f5
+ 0xfabc0d4f 0x0799c544 0x3d71181d 0x22c8a598
+ 0xb82840fc 0x1a198d19 0xf529a0ea 0x2f65bc24
+ 0xe979f99d 0xff8617b4 0x376e5abb 0xb095a03e
+ 0xa36b1107 0x2dacf004 0xe4c565e1 0xc96463cd
+ 0x3b495e2d 0x4a2c2cd7 0xa0053fc2 0x6c82a085
+ 0x6b801c45 0xc1481d77 0x6d95dc15 0x44dc8bf6
+ 0x3eed7d25 0x901a6b49 0x2797e953 0x502ad2c3
+ 0x8491c3f2 0x3ce059eb 0x992c1a76 0x6c56d2a2
+ 0xcf1878a7 0x10574487 0x5a2f85e6 0xf94e418e
+ 0x4c149aed 0x9381b5a3 0x79c90da4 0x635e696e
+ 0x243073ba 0x67504105 0xe82ac957 0xaccda7b3
+ 0x29bdd624 0xd0c1533c 0xbc080065 0x8d617329
+ 0x27e6f74a 0x31e87692 0x50a3857d 0xc5b1ec3f
+ 0x4f03be5f 0xa35fde17 0x537a59bb 0x793d1eb5
+ 0xc11a0588 0x067e5593 0x102532c3 0x4024b312
+ 0x32504cf4 0x4ddc0e9a 0xad5b1d24 0x41081874
+ 0xf94fced4 0x16f39da6 0x9bdfbe58 0xc5615db4
+ 0x1fdd769d 0x4278b52e 0x4525b8b6 0x7feed258
+ 0xe0b4348b 0xb4925ccc 0x5547cc88 0x3f7f5443
+ 0x5b8cc6d3 0xbe6a15cf 0x7308c088 0xde4219df
+ 0x4685593c 0xc4ae83a3 0xaea72ff0 0x403b0c08
+ 0xe533a9aa 0xed46be76 0x4390bcd0 0x683a9f3f
+ 0x338b5cd3 0x7cd59689 0x2eb11aec 0x74e91cfd
+ 0x7ae588aa 0x0eadf94e 0x30a6b42f 0x1965f165
+ 0xd96de54b 0x06c85abf 0x1bbc0ab8 0x79f3ddd0
+ 0x871fd58d 0x498dd69d 0x9197dd0e 0x6cbb3a4f
+ 0x8a1f2a01 0x0d9cf747 0x80e66655 0x770d2b25
+ 0x567bd3eb 0x59583c5a 0x58afeddd 0x9296d0e3
+ 0xcf5af62c 0xf48b4c78 0x746f657e 0xe543b903
+ 0x24603809 0xd1bceeea 0x16d04950 0x2a7c754b
+ 0x4ea8bb99 0x9daecb97 0x3045b9a9 0x4a3e84d9
+ 0x5487e79f 0xd6145e57 0xc3b17f6f 0x14448bb6
+ 0x8e8529f5 0xf895acb9 0x6605c0f0 0x52d00ca9
+ 0xabf6e3e9 0x8f36e307 0xa7a15442 0x55144801
+ 0x69b028b2 0x8ab3b912 0xb493f80e 0x2dc9fdfa
+ 0x1b091fbf 0x1bce6b31 0x79eb414e 0xe5f86ea0
+ 0x39ef7dbd 0x2f86faf0 0xec366923 0xe770c7be
+ 0x74e4aa61 0xef3b9da0 0xd77bd8be 0xfd13d3cb
+ 0x4e8023c6 0x3d993904 0xfcb2f700 0xa14b753b
+ 0xde16c1c3 0x983c5a86 0x52ba5e61 0x1d67b044
+ 0x0f9a302d 0x2f13b653 0x769cbb97 0xea3e1cbd
+ 0x5791778c 0x540fcff1 0x5e6c53f2 0xc9cbac0f
+ 0x40ceadf0 0x648713d3 0xb5347ada 0xfe280079
+ 0xb8389f3f 0x5a6be26a 0x8e683d28 0x6a3e8e3a
+ 0x97ecac7a 0x70b648f1 0xe4eca20e 0x088cd0b4
+ 0xbad30405 0x0f77e382 0x673cdf65 0x438af1f0
+ 0x0b4f4eea 0xf0cc34e9 0x374a3c04 0x4370d27d
+ 0xc3e1e84d 0x141205c2 0xfa831e8d 0x32f2f10a
+ 0x77899366 0xc9d07590 0x9b6f2286 0xcac96a03
+ 0xf822808b 0x265606cd 0xbeef275d 0x73415b15
+ 0x4c87250e 0xf95a8c8a 0xdc8d6166 0x68522e63
+ 0xb9becc14 0x7b5f20be 0x3d158dab 0xa73b1716
+ 0x3b2cac15 0xf0498939 0xb60653bf 0x33fafc0e
+ 0x3b416955 0x3addca50 0x16ab21cf 0xd18cbdb6
+ 0x3b29b87b 0xa6fb7e4b 0x6634147f 0x44283b1e
+ 0x430ae726 0xa907ab82 0x2baa6706 0x621d2390
+ 0x15944559 0x2516c807 0x7d1eeb61 0xe2714121
+ 0x288d3998 0x47713cbb 0xa1ce3c1e 0x0c29b6dd
+ 0x9923131c 0x2dd19cfa 0x83d0ece5 0x78474c7b
+ 0x92dee4f0 0xba5cb0f7 0x780c1d41 0x50da5a89
+ 0xe303cebb 0xe8d5a2bd 0x7d6269a9 0xb75484f1
+ 0x33ee8186 0x085b7657 0x7b1c7863 0xdb1a43ce
+ 0x3d0c4bf0 0x302c1292 0x81e42216 0xee1f2c9d
+ 0x822451ab 0xcefd8067 0x8330dc41 0x14492542
+ 0xf038f54d 0x90a1abf9 0xc3067a77 0x40d9a42c
+ 0x127285c1 0x80ad15ff 0xaf4854e2 0xa47874f4
+ 0x2ed59760 0x67252c6a 0xe2830f38 0x8150c00c
+ 0x16f61cca 0x1331f815 0x2d832d17 0x163c6010
+ 0x69464e2f 0x99940411 0xbce5e85f 0x43d39ef2
+ 0x9b7224dc 0x28652b6d 0x331a7632 0x127f669e
+ 0x44a034ad 0xe95d2cec 0x3d83fefb 0xfa6d40a2
+ 0x9b535bf4 0xc83411ce 0xd661655b 0x64bcd8d2
+ 0xd99e1570 0x7dc4d877 0x9756b210 0x7623dc0d
+ 0x484dd33f 0xe7bca204 0xa06efbc5 0xa358c03f
+ 0x362cb282 0xe40e6d04 0x17ab9f5e 0x79a71a09
+ 0x804bf1a9 0x6bca7d73 0x5504a4ff 0xd3946f75
+ 0x18b0b9d4 0xd85993cc 0x94d000a5 0x8dda1609
+ 0x30afb8f6 0xb3c99c3c 0x7686d59d 0x68b719db
+ 0xdc7b3edb 0xedb76012 0xbfa0ba3b 0x280b829d
+ 0x72fcf1aa 0xe3d8f83c 0x088a57cf 0x95156217
+ 0x3306eb47 0x1d09cf54 0x1391876f 0x5b15ecde
+ 0xb46104e1 0x8d8f2593 0x90ee50cc 0x78dad4b2
+ 0xfd96daee 0xdbf15e95 0xfc859faa 0xdb4422a5
+ 0xa00eeab6 0x525232c6 0x9b665668 0x8a70518b
+ 0xbb27f7ac 0xb066b096 0x25754db6 0xe8c7d748
+ 0xd4e8d361 0x380dd246 0x9bdf15e6 0x6823c660
+ 0x5d408fe7 0xe59a5a89 0x1eb7523b 0x4997158e
+ 0xfa6214d2 0x03b35025 0x9aeff33c 0x20a38aad
+ 0x522f79cd 0x4141f19c 0xc58cd2bd 0xc816da37
+ 0x62c6f8d9 0xc15ea9f4 0x138d1f45 0xd36cef03
+ 0x88183bd6 0xe0de9036 0xefcbe8fc 0x5ebdce26
+ 0x9e83b01b 0xd35f6747 0x552951f1 0x4e20dd66
+ 0x419702b1 0x45446e7c 0x7ce5616b 0x6152e3a8
+ 0xffd572e1 0x4fab25b0 0x07563b80 0x98720ee7
+ 0x176d29bf 0x21cbd730 0xbde74431 0x09a8cce2
+ 0xc15e548e 0xe6a92b4b 0x14f17e74 0x75f7817b
+ 0x592143e8 0x113dbd25 0x5f7d7160 0xbdd8b1e0
+ 0x6ce045e5 0x53b27b2d 0x371c8aa8 0xa4da8be0
+ 0xf1f6df4e 0x9519bac4 0x6d6169cf 0x7846253f
+ 0xccb95d95 0x6ad11a98 0x4a3bd21d 0x5389f44c
+ 0x7c07ef3a 0xb983ca57 0xcf7f290d 0x4ec516f1
+ 0xa7711e70 0x818d45a9 0x49db6441 0xd032fc2a
+ 0x657df4d3 0xe37e6809 0x459a22da 0x41df8aa5
+ 0x462108a6 0x65177d27 0x1ddffa9f 0x7fa6631b
+ 0xdd7a414c 0x6351f0d1 0x1b38a419 0x6b529c8e
+ 0x167745e4 0xcac35897 0x3d7bf419 0xd59ed67a
+ 0x6486b2c9 0x9ae4fc90 0x8f608920 0xd35335c0
+ 0x8f113cba 0x0fcc11a1 0xdc180fbf 0x57a99319
+ 0x2c54185f 0x764c18d0 0x4f84b111 0x30a11040
+ 0xd15620af 0x496af145 0x263b2de2 0x3ff103dd
+ 0x38484dac 0xf143a3bc 0xb62c0de6 0xb122c545
+ 0x72f10466 0x63728442 0xee0117c9 0x2309f14b
+ 0x4ccdd5de 0x37ae022d 0x2ee7f050 0xf2aa9af6
+ 0xcd314a20 0x86954941 0x97215303 0xcd7e1687
+ 0x1dab6672 0x1c920209 0x41102dae 0x8b21c8ab
+ 0x6f70b04b 0x2988b209 0x86e6f033 0x5eb91718
+ 0x925b3c40 0xdcad0288 0x0ee98331 0xc3096ceb
+ 0x9fa04740 0x3ce3fb23 0x90d75cbd 0xeab21768
+ 0xaca5db0a 0x1c440578 0x762cb728 0x315a699f
+ 0xcd2b6490 0x11e3e267 0xa10d1bbc 0x23ac26d3
+ 0xc0c7c268 0x37ecf7ac 0x28de6fe5 0x6fb8e3e8
+ 0x583d1131 0x8370812a 0x3afd5d58 0x4569a06e
+ 0xf27ad86f 0x0db6a631 0x9add5128 0x1748c9fd
+ 0xc46e3c57 0x4c0df93e 0xc595c544 0x397f7e7e
+ 0x241f4086 0x7d7ed51b 0x56027473 0x656a6110
+ 0x970a8011 0xf9c7beb5 0xc6cb9957 0xb7426461
+ 0x62d3d89d 0xf99d48ca 0x3e4d4a88 0x9f751b71
+ 0xfa020205 0xa3124337 0x59935869 0x98c58314
+ 0xff7c4385 0x69191265 0xaf85ebb9 0xe434cda2
+ 0xb1ad3e0e 0x221d32e1 0x022d73a0 0xd676ce06
+ 0xab7f0c21 0x915c2444 0xf5bdaba2 0x74e4e789
+ 0x11ff0d95 0x58c53feb 0xa54eb847 0x9af982ae
+ 0x8d721596 0x73510fe4 0x95e3bd19 0xd82f8359
+ 0xc09cdd5b 0xc07f57a4 0xbece605b 0xa8a43c5b
+ 0x0acbeb6d 0x3c5cd8ce 0xb631050d 0xd558c921
+ 0xcb5054c2 0xefb06252 0x40d2e2cc 0x14ffe6ff
+ 0x761001a9 0xad64e7a5 0xb55618b4 0x2a40a1fc
+ 0x2cbe6d40 0x2bc18fc1 0x196e7092 0x3c137791
+ 0xa799eb23 0x1156feb9 0xd55d7ed1 0x0149c315
+ 0xae77081f 0xfe724690 0x55ed2fd7 0x04b18cd7
+ 0x691583f4 0xb1be4fde 0x19ae1cf7 0x3250140b
+ 0x35daeeb2 0xc9459a84 0xea2c19e1 0x57f8c9cb
+ 0xe05e07a4 0xcc77a363 0x43afd702 0x48305862
+ 0x6c4b459f 0x66ed6178 0x26be9f81 0xeac41ee5
+ 0xbe5e2e6b 0x177f9068 0xede56c48 0x438b3811
+ 0xd5bd7ee4 0xc027d1a8 0xc1c0f725 0x48d4d4eb
+ 0x6ffa28d5 0xbd6ac9eb 0xd497781d 0x24d3a154
+ 0x409bb5c0 0x8079bf76 0x90a522dc 0x19bf7033
+ 0x1a529b6e 0xe5207e4d 0x3d49b7bc 0x3eca6d54
+ 0xa37681a6 0xaa9a62e4 0xe54aa1e1 0xb91e7157
+ 0x8cce8f65 0xbcbbd62c 0x7fa477b5 0x44f46b50
+ 0x54263fcf 0x529cbb5d 0x8923e390 0x0778d6d7
+ 0x0cc0503f 0x02c374ce 0xb89c3e5c 0x25b1b353
+ 0xb227cb2d 0x44108698 0x5e5968c2 0x82c48632
+ 0x0b8f4209 0x1a241879 0x9edca6f1 0xa1fa51ab
+ 0x206db0c6 0xbfbbbe98 0xa71c91f6 0xa1b28056
+ 0xb8bfaaa9 0xa5914f75 0x77d26574 0xacfd459d
+ 0x77f7cab2 0x249ebf26 0xef902bdd 0x77f6e48d
+ 0x82497035 0x93333a9d 0x34ea9953 0x8f08d41c
+ >;
*/
typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
-#pragma pack(1)
-
-struct fsp_init_params_t {
+struct fsp_init_params {
/* Non-volatile storage buffer pointer */
void *nvs_buf;
/* Runtime buffer pointer */
fsp_continuation_f continuation;
};
-struct common_buf_t {
+struct common_buf {
/*
* Stack top pointer used by the bootloader. The new stack frame will be
* set up at this location after FspInit API call.
u32 reserved[7]; /* Reserved */
};
-enum fsp_phase_t {
+enum fsp_phase {
/* Notification code for post PCI enuermation */
INIT_PHASE_PCI = 0x20,
/* Notification code before transfering control to the payload */
INIT_PHASE_BOOT = 0x40
};
-struct fsp_notify_params_t {
+struct fsp_notify_params {
/* Notification phase used for NotifyPhase API */
- enum fsp_phase_t phase;
+ enum fsp_phase phase;
};
-#pragma pack()
-
/* FspInit API function prototype */
-typedef u32 (*fsp_init_f)(struct fsp_init_params_t *param);
+typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
/* FspNotify API function prototype */
-typedef u32 (*fsp_notify_f)(struct fsp_notify_params_t *param);
+typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
#endif
#ifndef __FSP_FFS_H__
#define __FSP_FFS_H__
-#pragma pack(1)
-
/* Used to verify the integrity of the file */
-union ffs_integrity_t {
+union __packed ffs_integrity {
struct {
/*
* The IntegrityCheck.checksum.header field is an 8-bit
* Each file begins with the header that describe the
* contents and state of the files.
*/
-struct ffs_file_header_t {
+struct __packed ffs_file_header {
/*
* This GUID is the file name.
* It is used to uniquely identify the file.
*/
- struct efi_guid_t name;
+ struct efi_guid name;
/* Used to verify the integrity of the file */
- union ffs_integrity_t integrity;
+ union ffs_integrity integrity;
/* Identifies the type of file */
u8 type;
/* Declares various file attribute bits */
u8 state;
};
-struct ffs_file_header2_t {
+struct __packed ffs_file_header2 {
/*
* This GUID is the file name. It is used to uniquely identify the file.
* There may be only one instance of a file with the file name GUID of
* Name in any given firmware volume, except if the file type is
* EFI_FV_FILE_TYPE_FFS_PAD.
*/
- struct efi_guid_t name;
+ struct efi_guid name;
/* Used to verify the integrity of the file */
- union ffs_integrity_t integrity;
+ union ffs_integrity integrity;
/* Identifies the type of file */
u8 type;
/* Declares various file attribute bits */
/*
* The length of the file in bytes, including the FFS header.
* The length of the file data is either
- * (size - sizeof(struct ffs_file_header_t)). This calculation means a
+ * (size - sizeof(struct ffs_file_header)). This calculation means a
* zero-length file has a size of 24 bytes, which is
- * sizeof(struct ffs_file_header_t). Size is not required to be a
+ * sizeof(struct ffs_file_header). Size is not required to be a
* multiple of 8 bytes. Given a file F, the next file header is located
* at the next 8-byte aligned firmware volume offset following the last
* byte of the file F.
* If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
* and size must be set to zero.
* If FFS_ATTRIB_LARGE_FILE is not set then
- * struct ffs_file_header_t is used.
+ * struct ffs_file_header is used.
*/
u32 ext_size;
};
#define EFI_SECTION_SMM_DEPEX 0x1C
/* Common section header */
-struct raw_section_t {
+struct __packed raw_section {
/*
* A 24-bit unsigned integer that contains the total size of
* the section in bytes, including the EFI_COMMON_SECTION_HEADER.
u8 type;
};
-struct raw_section2_t {
+struct __packed raw_section2 {
/*
* A 24-bit unsigned integer that contains the total size of
* the section in bytes, including the EFI_COMMON_SECTION_HEADER.
u32 ext_size;
};
-#pragma pack()
-
#endif
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
-struct fv_blkmap_entry_t {
+struct fv_blkmap_entry {
/* The number of sequential blocks which are of the same size */
u32 num_blocks;
/* The size of the blocks */
};
/* Describes the features and layout of the firmware volume */
-struct fv_header_t {
+struct fv_header {
/*
* The first 16 bytes are reserved to allow for the reset vector of
* processors whose reset vector is at address 0.
* Declares the file system with which the firmware volume
* is formatted.
*/
- struct efi_guid_t fs_guid;
+ struct efi_guid fs_guid;
/*
* Length in bytes of the complete firmware volume, including
* the header.
* An array of run-length encoded FvBlockMapEntry structures.
* The array is terminated with an entry of {0,0}.
*/
- struct fv_blkmap_entry_t block_map[1];
+ struct fv_blkmap_entry block_map[1];
};
-#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
+#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
/* Firmware Volume Header Revision definition */
#define EFI_FVH_REVISION 0x02
/* Extension header pointed by ExtHeaderOffset of volume header */
-struct fv_ext_header_t {
+struct fv_ext_header {
/* firmware volume name */
- struct efi_guid_t fv_name;
+ struct efi_guid fv_name;
/* Size of the rest of the extension header including this structure */
u32 ext_hdr_size;
};
* Describes the format and size of the data inside the HOB.
* All HOBs must contain this generic HOB header.
*/
-struct hob_header_t {
+struct hob_header {
u16 type; /* HOB type */
u16 len; /* HOB length */
u32 reserved; /* always zero */
};
/* Enumeration of memory types introduced in UEFI */
-enum efi_mem_type_t {
+enum efi_mem_type {
EFI_RESERVED_MEMORY_TYPE,
/*
* The code portions of a loaded application.
* exist outside the HOB list. This HOB type describes how memory is used,
* not the physical attributes of memory.
*/
-struct hob_mem_alloc_t {
- struct hob_header_t hdr;
+struct hob_mem_alloc {
+ struct hob_header hdr;
/*
* A GUID that defines the memory allocation region's type and purpose,
* as well as other fields within the memory allocation HOB. This GUID
* is used to define the additional data within the HOB that may be
- * present for the memory allocation HOB. Type efi_guid_t is defined in
+ * present for the memory allocation HOB. Type efi_guid is defined in
* InstallProtocolInterface() in the UEFI 2.0 specification.
*/
- struct efi_guid_t name;
+ struct efi_guid name;
/*
* The base address of memory allocated by this HOB.
* Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
* Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
* specification.
*/
- enum efi_mem_type_t mem_type;
+ enum efi_mem_type mem_type;
/* padding */
u8 reserved[4];
};
* Describes the resource properties of all fixed, nonrelocatable resource
* ranges found on the processor host bus during the HOB producer phase.
*/
-struct hob_res_desc_t {
- struct hob_header_t hdr;
+struct hob_res_desc {
+ struct hob_header hdr;
/*
* A GUID representing the owner of the resource. This GUID is
* used by HOB consumer phase components to correlate device
* ownership of a resource.
*/
- struct efi_guid_t owner;
+ struct efi_guid owner;
u32 type;
u32 attr;
/* The physical start address of the resource region */
* Allows writers of executable content in the HOB producer phase to
* maintain and manage HOBs with specific GUID.
*/
-struct hob_guid_t {
- struct hob_header_t hdr;
+struct hob_guid {
+ struct hob_header hdr;
/* A GUID that defines the contents of this HOB */
- struct efi_guid_t name;
+ struct efi_guid name;
/* GUID specific data goes here */
};
/* Union of all the possible HOB Types */
-union hob_pointers_t {
- struct hob_header_t *hdr;
- struct hob_mem_alloc_t *mem_alloc;
- struct hob_res_desc_t *res_desc;
- struct hob_guid_t *guid;
+union hob_pointers {
+ struct hob_header *hdr;
+ struct hob_mem_alloc *mem_alloc;
+ struct hob_res_desc *res_desc;
+ struct hob_guid *guid;
u8 *raw;
};
/**
- * Returns the type of a HOB.
+ * get_hob_type() - return the type of a HOB
*
* This macro returns the type field from the HOB header for the
* HOB specified by hob.
*
* @return: HOB type.
*/
-#define GET_HOB_TYPE(hob) \
- ((*(struct hob_header_t **)&(hob))->type)
+static inline u16 get_hob_type(union hob_pointers hob)
+{
+ return hob.hdr->type;
+}
/**
- * Returns the length, in bytes, of a HOB.
+ * get_hob_length() - return the length, in bytes, of a HOB
*
* This macro returns the len field from the HOB header for the
* HOB specified by hob.
*
* @return: HOB length.
*/
-#define GET_HOB_LENGTH(hob) \
- ((*(struct hob_header_t **)&(hob))->len)
+static inline u16 get_hob_length(union hob_pointers hob)
+{
+ return hob.hdr->len;
+}
/**
- * Returns a pointer to the next HOB in the HOB list.
+ * get_next_hob() - return a pointer to the next HOB in the HOB list
*
* This macro returns a pointer to HOB that follows the HOB specified by hob
* in the HOB List.
*
* @return: A pointer to the next HOB in the HOB list.
*/
-#define GET_NEXT_HOB(hob) \
- (void *)(*(u8 **)&(hob) + GET_HOB_LENGTH(hob))
+static inline void *get_next_hob(union hob_pointers hob)
+{
+ return (void *)(*(u8 **)&(hob) + get_hob_length(hob));
+}
/**
- * Determines if a HOB is the last HOB in the HOB list.
+ * end_of_hob() - determine if a HOB is the last HOB in the HOB list
*
* This macro determine if the HOB specified by hob is the last HOB in the
- * HOB list. If hob is last HOB in the HOB list, then TRUE is returned.
- * Otherwise, FALSE is returned.
+ * HOB list. If hob is last HOB in the HOB list, then true is returned.
+ * Otherwise, false is returned.
*
* @hob: A pointer to a HOB.
*
- * @retval TRUE: The HOB specified by hob is the last HOB in the HOB list.
- * @retval FALSE: The HOB specified by hob is not the last HOB in the HOB list.
+ * @retval true: The HOB specified by hob is the last HOB in the HOB list.
+ * @retval false: The HOB specified by hob is not the last HOB in the HOB list.
*/
-#define END_OF_HOB(hob) (GET_HOB_TYPE(hob) == (u16)HOB_TYPE_EOH)
+static inline bool end_of_hob(union hob_pointers hob)
+{
+ return get_hob_type(hob) == HOB_TYPE_EOH;
+}
/**
- * Returns a pointer to data buffer from a HOB of type HOB_TYPE_GUID_EXT.
+ * get_guid_hob_data() - return a pointer to data buffer from a HOB of
+ * type HOB_TYPE_GUID_EXT
*
* This macro returns a pointer to the data buffer in a HOB specified by hob.
* hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
*
* @return: A pointer to the data buffer in a HOB.
*/
-#define GET_GUID_HOB_DATA(hob) \
- (void *)(*(u8 **)&(hob) + sizeof(struct hob_guid_t))
+static inline void *get_guid_hob_data(u8 *hob)
+{
+ return (void *)(hob + sizeof(struct hob_guid));
+}
/**
- * Returns the size of the data buffer from a HOB of type HOB_TYPE_GUID_EXT.
+ * get_guid_hob_data_size() - return the size of the data buffer from a HOB
+ * of type HOB_TYPE_GUID_EXT
*
* This macro returns the size, in bytes, of the data buffer in a HOB
* specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
*
* @return: The size of the data buffer.
*/
-#define GET_GUID_HOB_DATA_SIZE(hob) \
- (u16)(GET_HOB_LENGTH(hob) - sizeof(struct hob_guid_t))
+static inline u16 get_guid_hob_data_size(u8 *hob)
+{
+ union hob_pointers hob_p = *(union hob_pointers *)hob;
+ return get_hob_length(hob_p) - sizeof(struct hob_guid);
+}
/* FSP specific GUID HOB definitions */
+#define FSP_GUID_DATA1 0x912740be
+#define FSP_GUID_DATA2 0x2284
+#define FSP_GUID_DATA3 0x4734
+#define FSP_GUID_DATA4_0 0xb9
+#define FSP_GUID_DATA4_1 0x71
+#define FSP_GUID_DATA4_2 0x84
+#define FSP_GUID_DATA4_3 0xb0
+#define FSP_GUID_DATA4_4 0x27
+#define FSP_GUID_DATA4_5 0x35
+#define FSP_GUID_DATA4_6 0x3f
+#define FSP_GUID_DATA4_7 0x0c
+
#define FSP_HEADER_GUID \
{ \
- 0x912740be, 0x2284, 0x4734, \
- {0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c} \
+ FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
+ { FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
+ FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
+ FSP_GUID_DATA4_6, FSP_GUID_DATA4_7 } \
}
#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
-#pragma pack(1)
-
-struct fsp_header_t {
+struct __packed fsp_header {
u32 sign; /* 'FSPH' */
u32 hdr_len; /* header length */
u8 reserved1[3];
u32 reserved2;
};
-#pragma pack()
-
#endif
#ifndef __FSP_PLATFORM_H__
#define __FSP_PLATFORM_H__
-#pragma pack(1)
-
-struct fspinit_rtbuf_t {
- struct common_buf_t common; /* FSP common runtime data structure */
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
};
-#pragma pack()
-
#endif
#include "fsp_bootmode.h"
#include "fsp_vpd.h"
-struct shared_data_t {
- struct fsp_header_t *fsp_hdr;
+struct shared_data {
+ struct fsp_header *fsp_hdr;
u32 *stack_top;
- struct upd_region_t fsp_upd;
+ struct upd_region fsp_upd;
};
+#define FSP_LOWMEM_BASE 0x100000UL
+#define FSP_HIGHMEM_BASE 0x100000000ULL
+
+/**
+ * FSP Continuation assembly helper routine
+ *
+ * This routine jumps to the C version of FSP continuation function
+ */
void asm_continuation(void);
+/**
+ * FSP initialization complete
+ *
+ * This is the function that indicates FSP initialization is complete and jumps
+ * back to the bootloader with HOB list pointer as the parameter.
+ *
+ * @hob_list: HOB list pointer
+ */
void fsp_init_done(void *hob_list);
/**
*
* @retval: Never returns
*/
-void fsp_continue(struct shared_data_t *shared_data, u32 status,
+void fsp_continue(struct shared_data *shared_data, u32 status,
void *hob_list);
/**
* Find FSP header offset in FSP image
*
- * If this function is called before the a stack is established, special care
- * must be taken. First, it cannot declare any local variable using stack.
- * Only register variable can be used here. Secondly, some compiler version
- * will add prolog or epilog code for the C function. If so the function call
- * may not work before stack is ready. GCC 4.8.1 has been verified to be
- * working for the following code.
- *
* @retval: the offset of FSP header. If signature is invalid, returns 0.
*/
u32 find_fsp_header(void);
* FSP notification wrapper function
*
* @fsp_hdr: Pointer to FSP information header
- * @phase: FSP initialization phase defined in enum fsp_phase_t
+ * @phase: FSP initialization phase defined in enum fsp_phase
*
* @retval: compatible status code with EFI_STATUS defined in PI spec
*/
-u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase);
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
/**
* This function retrieves the top of usable low memory.
*
* @retval: Usable low memory top.
*/
-u32 get_usable_lowmem_top(const void *hob_list);
+u32 fsp_get_usable_lowmem_top(const void *hob_list);
/**
* This function retrieves the top of usable high memory.
*
* @retval: Usable high memory top.
*/
-u64 get_usable_highmem_top(const void *hob_list);
+u64 fsp_get_usable_highmem_top(const void *hob_list);
/**
* This function retrieves a special reserved memory region.
* @retval: Reserved region start address.
* 0 if this region does not exist.
*/
-u64 get_fsp_reserved_mem_from_guid(const void *hob_list,
- u64 *len, struct efi_guid_t *guid);
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
+ u64 *len, struct efi_guid *guid);
/**
* This function retrieves the FSP reserved normal memory.
* @retval: FSP reserved memory base
* 0 if this region does not exist.
*/
-u32 get_fsp_reserved_mem(const void *hob_list, u32 *len);
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);
/**
* This function retrieves the TSEG reserved normal memory.
* @retval NULL: Failed to find the TSEG reserved memory.
* @retval others: TSEG reserved memory base.
*/
-u32 get_tseg_reserved_mem(const void *hob_list, u32 *len);
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
/**
* Returns the next instance of a HOB type from the starting HOB.
*
* @retval: A HOB object with matching type; Otherwise NULL.
*/
-void *get_next_hob(u16 type, const void *hob_list);
+void *fsp_get_next_hob(u16 type, const void *hob_list);
/**
* Returns the next instance of the matched GUID HOB from the starting HOB.
*
* @retval: A HOB object with matching GUID; Otherwise NULL.
*/
-void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list);
+void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list);
/**
* This function retrieves a GUID HOB data buffer and size.
* @retval NULL: Failed to find the GUID HOB.
* @retval others: GUID HOB data buffer pointer.
*/
-void *get_guid_hob_data(const void *hob_list, u32 *len,
- struct efi_guid_t *guid);
+void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
+ struct efi_guid *guid);
/**
* This function retrieves FSP Non-volatile Storage HOB buffer and size.
* @retval NULL: Failed to find the NVS HOB.
* @retval others: FSP NVS data buffer pointer.
*/
-void *get_fsp_nvs_data(const void *hob_list, u32 *len);
+void *fsp_get_nvs_data(const void *hob_list, u32 *len);
/**
* This function retrieves Bootloader temporary stack buffer and size.
* @retval NULL: Failed to find the bootloader temporary stack HOB.
* @retval others: Bootloader temporary stackbuffer pointer.
*/
-void *get_bootloader_tmp_mem(const void *hob_list, u32 *len);
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
/**
* This function overrides the default configurations in the UPD data region.
*
- * @fsp_upd: A pointer to the upd_region_t data strcture
+ * @fsp_upd: A pointer to the upd_region data strcture
*
* @return: None
*/
-void update_fsp_upd(struct upd_region_t *fsp_upd);
+void update_fsp_upd(struct upd_region *fsp_upd);
#endif
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
-/*
- * Boolean true value. UEFI Specification defines this value to be 1,
- * but this form is more portable.
- */
-#define TRUE ((unsigned char)(1 == 1))
-
-/*
- * Boolean false value. UEFI Specification defines this value to be 0,
- * but this form is more portable.
- */
-#define FALSE ((unsigned char)(0 == 1))
-
/* 128 bit buffer containing a unique identifier value */
-struct efi_guid_t {
+struct efi_guid {
u32 data1;
u16 data2;
u16 data3;
#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
(SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
-/* Assertion for debug */
-#define ASSERT(exp) do { if (!(exp)) for (;;); } while (FALSE)
-
/*
* Define FSP API return status code.
* Compatiable with EFI_STATUS defined in PI Spec.
#ifndef __VPDHEADER_H__
#define __VPDHEADER_H__
-#pragma pack(1)
+#define UPD_TERMINATOR 0x55AA
-struct upd_region_t {
+struct __packed upd_region {
u64 sign; /* Offset 0x0000 */
u64 reserved; /* Offset 0x0008 */
u8 dummy[240]; /* Offset 0x0010 */
#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */
#define VPD_IMAGE_REV 0x00000301
-struct vpd_region_t {
+struct __packed vpd_region {
u64 sign; /* Offset 0x0000 */
u32 img_rev; /* Offset 0x0008 */
u32 upd_offset; /* Offset 0x000C */
u8 pcie_port_ioh; /* Offset 0x0029 */
};
-#pragma pack()
-
#endif
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+#include <pci.h>
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+
+#endif /* _X86_ARCH_TNC_H_ */
#include <asm-generic/gpio.h>
struct ich6_bank_platdata {
- uint32_t base_addr;
+ uint16_t base_addr;
const char *bank_name;
};
} set3;
};
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
#endif /* _X86_GPIO_H_ */
#define SYSCTLA 0x92
#define SLAVE_PIC 0xa0
+#define UART0_BASE 0x3f8
+#define UART1_BASE 0x2f8
+
#endif
"Memory Allocation",
"Resource Descriptor",
"GUID Extension",
- "Firmware Volumn",
+ "Firmware Volume",
"CPU",
"Memory Pool",
"reserved",
- "Firmware Volumn 2",
+ "Firmware Volume 2",
"Load PEIM Unused",
"UEFI Capsule",
};
int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- union hob_pointers_t hob;
+ union hob_pointers hob;
u16 type;
char *desc;
int i = 0;
printf("No. | Address | Type | Length in Bytes\n");
printf("----|----------|---------------------|----------------\n");
- while (!END_OF_HOB(hob)) {
+ while (!end_of_hob(hob)) {
printf("%-3d | %08x | ", i, (unsigned int)hob.raw);
- type = hob.hdr->type;
+ type = get_hob_type(hob);
if (type == HOB_TYPE_UNUSED)
desc = "*Unused*";
else if (type == HOB_TYPE_EOH)
- desc = "**END OF HOB**";
+ desc = "*END OF HOB*";
else if (type >= 0 && type <= ARRAY_SIZE(hob_type))
desc = hob_type[type];
else
- desc = "!!!Invalid Type!!!";
- printf("%-19s | %-15d\n", desc, hob.hdr->len);
- hob.raw = GET_NEXT_HOB(hob);
+ desc = "*Invalid Type*";
+ printf("%-19s | %-15d\n", desc, get_hob_length(hob));
+ hob.raw = get_next_hob(hob);
i++;
}
return 0;
}
-/* -------------------------------------------------------------------- */
-
U_BOOT_CMD(
hob, 1, 1, do_hob,
- "print FSP Hand-Off Block information",
+ "print Firmware Support Package (FSP) Hand-Off Block information",
""
);
F: configs/vexpress_aemv8a_defconfig
VEXPRESS_AEMV8A_SEMI BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
F: configs/vexpress_aemv8a_semi_defconfig
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#include <i2c.h>
+#include <netdev.h>
void pin_mux_usb(void)
{
/* For CD GPIO PP1 */
pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}
+
+#ifdef CONFIG_PCI
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif
return 0;
}
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}
#ifdef CONFIG_USB_EHCI_MX5
#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
-#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 2)
+#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
static void setup_usb_h1(void)
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 1);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 0)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
int board_early_init_f(void)
{
setup_iomux_uart();
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <asm/arch/mx6-ddr.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
return cpu_eth_init(bis);
}
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_hc1_pads[] = {
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+
+ imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+ ARRAY_SIZE(usb_hc1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ break;
+ case 1:
+ if (on)
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+ else
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
int board_early_init_f(void)
{
setup_iomux_uart();
#endif
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
return 0;
}
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
-
int checkboard(void)
{
puts("Board: MX6SLEVK\n");
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
+ writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
return 0;
}
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
/* GPIO Set 1 */
if (gpio->set1.level)
--- /dev/null
+if TARGET_CROWNBAY
+
+config SYS_BOARD
+ default "crownbay"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "queensbay"
+
+config SYS_CONFIG_NAME
+ default "crownbay"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select INTEL_QUEENSBAY
+ select BOARD_ROMSIZE_KB_1024
+
+endif
--- /dev/null
+INTEL CROWNBAY BOARD
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: board/intel/crownbay/
+F: include/configs/crownbay.h
+F: configs/crownbay_defconfig
--- /dev/null
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += crownbay.o start.o
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+#include <netdev.h>
+#include <smsc_lpc47m.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 4)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+
+ return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ jmp early_board_init_ret
obj-y := novena_spl.o
else
obj-y := novena.o
+obj-$(CONFIG_VIDEO_IPUV3) += video.o
endif
#include <power/pfuze100_pmic.h>
#include <stdio_dev.h>
-DECLARE_GLOBAL_DATA_PTR;
+#include "novena.h"
-#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14)
-#define NOVENA_SD_WP IMX_GPIO_NR(1, 2)
-#define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
+DECLARE_GLOBAL_DATA_PTR;
/*
* GPIO button
}
#endif
-/*
- * Video over HDMI
- */
-#if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {
- {
- /* HDMI Output */
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
- }
- }
-};
-
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* Turn on LDB0,IPU,IPU DI0 clocks */
- setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-
- /* set LDB0, LDB1 clk select to 011/011 */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
- MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
- (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
- (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
-
- setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-
- setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
- MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-
- writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
- IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
- IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
- IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
- IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
- IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
- IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
- &iomux->gpr[2]);
-
- clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
- IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
- IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-}
-#endif
-
int board_early_init_f(void)
{
#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
+ setup_display_clock();
#endif
return 0;
return 0;
}
+int board_late_init(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display_lvds();
+#endif
+ return 0;
+}
+
int checkboard(void)
{
puts("Board: Novena 4x\n");
--- /dev/null
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__
+#define __BOARD_KOSAGI_NOVENA_NOVENA_H__
+
+#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17)
+#define NOVENA_BACKLIGHT_PWM_GPIO IMX_GPIO_NR(4, 29)
+#define NOVENA_BACKLIGHT_PWR_GPIO IMX_GPIO_NR(4, 15)
+#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14)
+#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7)
+#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4)
+#define NOVENA_ITE6251_PWR_GPIO IMX_GPIO_NR(5, 28)
+#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16)
+#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12)
+#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29)
+#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22)
+#define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
+#define NOVENA_SD_WP IMX_GPIO_NR(1, 2)
+
+#define NOVENA_IT6251_I2C_BUS 2
+#define NOVENA_IT6251_CHIPADDR 0x5c
+#define NOVENA_IT6251_LVDSADDR 0x5e
+
+void setup_display_clock(void);
+void setup_display_lvds(void);
+
+#endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */
#include <asm/arch/mx6-ddr.h>
+#include "novena.h"
+
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL \
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17)
-#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7)
-#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4)
-#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29)
-#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12)
-#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22)
-#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16)
-
/*
* Audio
*/
static iomux_v3_cfg_t hdmi_pads[] = {
/* "Ghost HPD" pin */
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* LCD_PWR_CTL */
+ MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LCD_BL_ON */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* GPIO_PWM1 */
+ MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void novena_spl_setup_iomux_video(void)
--- /dev/null
+/*
+ * Novena video output support
+ *
+ * IT6251 code based on code Copyright (C) 2014 Sean Cross
+ * from https://github.com/xobs/novena-linux.git commit
+ * 3d85836ee1377d445531928361809612aa0a18db
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+
+#include "novena.h"
+
+#define IT6251_VENDOR_ID_LOW 0x00
+#define IT6251_VENDOR_ID_HIGH 0x01
+#define IT6251_DEVICE_ID_LOW 0x02
+#define IT6251_DEVICE_ID_HIGH 0x03
+#define IT6251_SYSTEM_STATUS 0x0d
+#define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0)
+#define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1)
+#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2)
+#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3)
+#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4)
+#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5)
+#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6)
+#define IT6251_REF_STATE 0x0e
+#define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0)
+#define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1)
+#define IT6251_REF_STATE_CR_PATTERN (1 << 2)
+#define IT6251_REF_STATE_EQ_PATTERN (1 << 3)
+#define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4)
+#define IT6251_REF_STATE_MUTED (1 << 5)
+
+#define IT6251_REG_PCLK_CNT_LOW 0x57
+#define IT6251_REG_PCLK_CNT_HIGH 0x58
+
+#define IT6521_RETRY_MAX 20
+
+static int it6251_is_stable(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+ const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+ int status;
+ int clkcnt;
+ int rpclkcnt;
+ int refstate;
+
+ rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
+ ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
+ debug("RPCLKCnt: %d\n", rpclkcnt);
+
+ status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
+ debug("System status: 0x%02x\n", status);
+
+ clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
+ ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
+ 0x0f00);
+ debug("Clock: 0x%02x\n", clkcnt);
+
+ refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
+ debug("Ref Link State: 0x%02x\n", refstate);
+
+ if ((refstate & 0x1f) != 0)
+ return 0;
+
+ /* If video is muted, that's a failure */
+ if (refstate & IT6251_REF_STATE_MUTED)
+ return 0;
+
+ if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
+ return 0;
+
+ return 1;
+}
+
+static int it6251_ready(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+
+ /* Test if the IT6251 came out of reset by reading ID regs. */
+ if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
+ return 0;
+ if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
+ return 0;
+ if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
+ return 0;
+ if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
+ return 0;
+
+ return 1;
+}
+
+static void it6251_program_regs(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+ const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+
+ i2c_reg_write(caddr, 0x05, 0x00);
+ mdelay(1);
+
+ /* set LVDSRX address, and enable */
+ i2c_reg_write(caddr, 0xfd, 0xbc);
+ i2c_reg_write(caddr, 0xfe, 0x01);
+
+ /*
+ * LVDSRX
+ */
+ /* This write always fails, because the chip goes into reset */
+ /* reset LVDSRX */
+ i2c_reg_write(laddr, 0x05, 0xff);
+ i2c_reg_write(laddr, 0x05, 0x00);
+
+ /* reset LVDSRX PLL */
+ i2c_reg_write(laddr, 0x3b, 0x42);
+ i2c_reg_write(laddr, 0x3b, 0x43);
+
+ /* something with SSC PLL */
+ i2c_reg_write(laddr, 0x3c, 0x08);
+ /* don't swap links, but writing reserved registers */
+ i2c_reg_write(laddr, 0x0b, 0x88);
+
+ /* JEIDA, 8-bit depth 0x11, orig 0x42 */
+ i2c_reg_write(laddr, 0x2c, 0x01);
+ /* "reserved" */
+ i2c_reg_write(laddr, 0x32, 0x04);
+ /* "reserved" */
+ i2c_reg_write(laddr, 0x35, 0xe0);
+ /* "reserved" + clock delay */
+ i2c_reg_write(laddr, 0x2b, 0x24);
+
+ /* reset LVDSRX pix clock */
+ i2c_reg_write(laddr, 0x05, 0x02);
+ i2c_reg_write(laddr, 0x05, 0x00);
+
+ /*
+ * DPTX
+ */
+ /* set for two lane mode, normal op, no swapping, no downspread */
+ i2c_reg_write(caddr, 0x16, 0x02);
+
+ /* some AUX channel EDID magic */
+ i2c_reg_write(caddr, 0x23, 0x40);
+
+ /* power down lanes 3-0 */
+ i2c_reg_write(caddr, 0x5c, 0xf3);
+
+ /* enable DP scrambling, change EQ CR phase */
+ i2c_reg_write(caddr, 0x5f, 0x06);
+
+ /* color mode RGB, pclk/2 */
+ i2c_reg_write(caddr, 0x60, 0x02);
+ /* dual pixel input mode, no EO swap, no RGB swap */
+ i2c_reg_write(caddr, 0x61, 0x04);
+ /* M444B24 video format */
+ i2c_reg_write(caddr, 0x62, 0x01);
+
+ /* vesa range / not interlace / vsync high / hsync high */
+ i2c_reg_write(caddr, 0xa0, 0x0F);
+
+ /* hpd event timer set to 1.6-ish ms */
+ i2c_reg_write(caddr, 0xc9, 0xf5);
+
+ /* more reserved magic */
+ i2c_reg_write(caddr, 0xca, 0x4d);
+ i2c_reg_write(caddr, 0xcb, 0x37);
+
+ /* enhanced framing mode, auto video fifo reset, video mute disable */
+ i2c_reg_write(caddr, 0xd3, 0x03);
+
+ /* "vidstmp" and some reserved stuff */
+ i2c_reg_write(caddr, 0xd4, 0x45);
+
+ /* queue number -- reserved */
+ i2c_reg_write(caddr, 0xe7, 0xa0);
+ /* info frame packets and reserved */
+ i2c_reg_write(caddr, 0xe8, 0x33);
+ /* more AVI stuff */
+ i2c_reg_write(caddr, 0xec, 0x00);
+
+ /* select PC master reg for aux channel? */
+ i2c_reg_write(caddr, 0x23, 0x42);
+
+ /* send PC request commands */
+ i2c_reg_write(caddr, 0x24, 0x00);
+ i2c_reg_write(caddr, 0x25, 0x00);
+ i2c_reg_write(caddr, 0x26, 0x00);
+
+ /* native aux read */
+ i2c_reg_write(caddr, 0x2b, 0x00);
+ /* back to internal */
+ i2c_reg_write(caddr, 0x23, 0x40);
+
+ /* voltage swing level 3 */
+ i2c_reg_write(caddr, 0x19, 0xff);
+ /* pre-emphasis level 3 */
+ i2c_reg_write(caddr, 0x1a, 0xff);
+
+ /* start link training */
+ i2c_reg_write(caddr, 0x17, 0x01);
+}
+
+static int it6251_init(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+ int reg;
+ int tries, retries = 0;
+
+ for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
+ /* Program the chip. */
+ it6251_program_regs();
+
+ /* Wait for video stable. */
+ for (tries = 0; tries < 100; tries++) {
+ reg = i2c_reg_read(caddr, 0x17);
+ /* Test Link CFG, STS, LCS read done. */
+ if ((reg & 0xe0) != 0xe0) {
+ /* Not yet, wait a bit more. */
+ mdelay(2);
+ continue;
+ }
+
+ /* Test if the video input is stable. */
+ if (it6251_is_stable())
+ return 0;
+ }
+ /*
+ * If we couldn't stabilize, requeue and try again,
+ * because it means that the LVDS channel isn't
+ * stable yet.
+ */
+ printf("Display didn't stabilize.\n");
+ printf("This may be because the LVDS port is still in powersave mode.\n");
+ mdelay(50);
+ }
+
+ return -EINVAL;
+}
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int lvds_enabled;
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ if (lvds_enabled)
+ return;
+
+ /* ITE IT6251 power enable. */
+ gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
+ mdelay(10);
+ gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
+ mdelay(20);
+ lvds_enabled = 1;
+}
+
+static int detect_lvds(struct display_info_t const *dev)
+{
+ int ret, loops = 250;
+
+ enable_lvds(dev);
+
+ ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+ if (ret) {
+ puts("Cannot select IT6251 I2C bus.\n");
+ return 0;
+ }
+
+ /* Wait up-to ~250 mS for the LVDS to come up. */
+ while (--loops) {
+ ret = it6251_ready();
+ if (ret)
+ return ret;
+
+ mdelay(1);
+ }
+
+ return 0;
+}
+
+struct display_info_t const displays[] = {
+ {
+ /* HDMI Output */
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15384,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ }, {
+ /* LVDS Output: N133HSE-EA1 Rev. C1 */
+ .bus = -1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_lvds,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Chimei-FHD",
+ .refresh = 60,
+ .xres = 1920,
+ .yres = 1080,
+ .pixclock = 15384,
+ .left_margin = 148,
+ .right_margin = 88,
+ .upper_margin = 36,
+ .lower_margin = 4,
+ .hsync_len = 44,
+ .vsync_len = 5,
+ .sync = FB_SYNC_HOR_HIGH_ACT |
+ FB_SYNC_VERT_HIGH_ACT |
+ FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ },
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_vpll(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int timeout = 100000;
+
+ setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+ BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+ clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_BYPASS,
+ BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+void setup_display_clock(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ enable_ipu_clock();
+ enable_vpll();
+ imx_setup_hdmi();
+
+ /* Turn on IPU LDB DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ /* Switch LDB DI0 to PLL5 (Video PLL) */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+ (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+ /* LDB clock div by 3.5 */
+ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ /* DI0 clock derived from ldb_di0_clk */
+ clrsetbits_le32(&mxc_ccm->chsccdr,
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+ );
+
+ /* Enable both LVDS channels, both connected to DI0. */
+ writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+ IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+ );
+}
+
+void setup_display_lvds(void)
+{
+ int ret;
+
+ ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+ if (ret) {
+ puts("Cannot select LVDS-to-eDP I2C bus.\n");
+ return;
+ }
+
+ /* The IT6251 should be ready now, if it's not, it's not connected. */
+ ret = it6251_ready();
+ if (!ret)
+ return;
+
+ /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
+ ret = it6251_init();
+ if (!ret) {
+ /* Backlight power enable. */
+ gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
+ /* PWM backlight pin, always on for full brightness. */
+ gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
+ }
+}
#include <dm.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include "pinmux-config-cardhu.h"
#include <i2c.h>
+#include <netdev.h>
#define PMU_I2C_ADDRESS 0x2D
#define MAX_I2C_RETRY 3
board_sdmmc_voltage_init();
}
#endif /* MMC */
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ u8 addr, data[1];
+ int err;
+
+ err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
+ if (err) {
+ debug("failed to find PMU bus\n");
+ return err;
+ }
+
+ /* TPS659110: LDO1_REG = 1.05V, ACTIVE */
+ data[0] = 0x15;
+ addr = 0x30;
+
+ err = i2c_write(dev, addr, data, 1);
+ if (err) {
+ debug("failed to set VDD supply\n");
+ return err;
+ }
+
+ /* GPIO: PEX = 3.3V */
+ err = gpio_request(GPIO_PL7, "PEX");
+ if (err < 0)
+ return err;
+
+ gpio_direction_output(GPIO_PL7, 1);
+
+ /* TPS659110: LDO2_REG = 1.05V, ACTIVE */
+ data[0] = 0x15;
+ addr = 0x31;
+
+ err = i2c_write(dev, addr, data, 1);
+ if (err) {
+ debug("failed to set AVDD supply\n");
+ return err;
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif /* PCI */
#include <asm/arch-tegra/tegra_mmc.h>
#include <asm/arch-tegra/mmc.h>
#endif
+#include <asm/arch-tegra/xusb-padctl.h>
#include <i2c.h>
#include <spi.h>
#include "emc.h"
pin_mux_nand();
#endif
+ tegra_xusb_padctl_init(gd->fdt_blob);
+
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
*/
#include <common.h>
+#include <netdev.h>
+#include <power/as3722.h>
+
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
+
#include "pinmux-config-jetson-tk1.h"
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
ARRAY_SIZE(jetson_tk1_drvgrps));
}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *pmic;
+ int err;
+
+ err = as3722_init(&pmic);
+ if (err) {
+ error("failed to initialize AS3722 PMIC: %d\n", err);
+ return err;
+ }
+
+ err = as3722_sd_enable(pmic, 4);
+ if (err < 0) {
+ error("failed to enable SD4: %d\n", err);
+ return err;
+ }
+
+ err = as3722_sd_set_voltage(pmic, 4, 0x24);
+ if (err < 0) {
+ error("failed to set SD4 voltage: %d\n", err);
+ return err;
+ }
+
+ err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH |
+ AS3722_GPIO_INVERT);
+ if (err < 0) {
+ error("failed to configure GPIO#1 as output: %d\n", err);
+ return err;
+ }
+
+ err = as3722_gpio_direction_output(pmic, 2, 1);
+ if (err < 0) {
+ error("failed to set GPIO#2 high: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif /* PCI */
return 0;
}
-
-/* Fine-tune the DRAM configuration. */
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-{
- /* Enable Auto Precharge. */
- dram_vals[3] |= 1 << 8;
- /* Enable Fast Writes. */
- dram_vals[5] |= 1 << 8;
- /* tEMRS = 3*tCK */
- dram_vals[10] &= ~(0x3 << 8);
- dram_vals[10] |= (0x3 << 8);
- /* CASLAT = 3*tCK */
- dram_vals[11] &= ~(0x3 << 0);
- dram_vals[11] |= (0x3 << 0);
- /* tCKE = 1*tCK */
- dram_vals[12] &= ~(0x7 << 0);
- dram_vals[12] |= (0x1 << 0);
- /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
- dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
- dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
- /* tDAL = 6*tCK */
- dram_vals[15] &= ~(0xf << 16);
- dram_vals[15] |= (0x6 << 16);
- /* tREF = 1040*tCK */
- dram_vals[26] &= ~0xffff;
- dram_vals[26] |= 0x0410;
- /* tRAS_MAX = 9334*tCK */
- dram_vals[32] &= ~0xffff;
- dram_vals[32] |= 0x2475;
-}
{
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
}
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /* Enable Auto Precharge. */
+ dram_vals[3] |= 1 << 8;
+ /* Enable Fast Writes. */
+ dram_vals[5] |= 1 << 8;
+ /* tEMRS = 3*tCK */
+ dram_vals[10] &= ~(0x3 << 8);
+ dram_vals[10] |= (0x3 << 8);
+ /* CASLAT = 3*tCK */
+ dram_vals[11] &= ~(0x3 << 0);
+ dram_vals[11] |= (0x3 << 0);
+ /* tCKE = 1*tCK */
+ dram_vals[12] &= ~(0x7 << 0);
+ dram_vals[12] |= (0x1 << 0);
+ /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+ dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+ dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+ /* tDAL = 6*tCK */
+ dram_vals[15] &= ~(0xf << 16);
+ dram_vals[15] |= (0x6 << 16);
+ /* tREF = 1040*tCK */
+ dram_vals[26] &= ~0xffff;
+ dram_vals[26] |= 0x0410;
+ /* tRAS_MAX = 9334*tCK */
+ dram_vals[32] &= ~0xffff;
+ dram_vals[32] |= 0x2475;
+}
static const struct {
const char *name;
const char *fdtfile;
+ bool has_onboard_eth;
} models[] = {
+ [0] = {
+ "Unknown model",
+ "bcm2835-rpi-other.dtb",
+ false,
+ },
[BCM2835_BOARD_REV_B_I2C0_2] = {
"Model B (no P5)",
"bcm2835-rpi-b-i2c0.dtb",
+ true,
},
[BCM2835_BOARD_REV_B_I2C0_3] = {
"Model B (no P5)",
"bcm2835-rpi-b-i2c0.dtb",
+ true,
},
[BCM2835_BOARD_REV_B_I2C1_4] = {
"Model B",
"bcm2835-rpi-b.dtb",
+ true,
},
[BCM2835_BOARD_REV_B_I2C1_5] = {
"Model B",
"bcm2835-rpi-b.dtb",
+ true,
},
[BCM2835_BOARD_REV_B_I2C1_6] = {
"Model B",
"bcm2835-rpi-b.dtb",
+ true,
},
[BCM2835_BOARD_REV_A_7] = {
"Model A",
"bcm2835-rpi-a.dtb",
+ false,
},
[BCM2835_BOARD_REV_A_8] = {
"Model A",
"bcm2835-rpi-a.dtb",
+ false,
},
[BCM2835_BOARD_REV_A_9] = {
"Model A",
"bcm2835-rpi-a.dtb",
+ false,
},
[BCM2835_BOARD_REV_B_REV2_d] = {
"Model B rev2",
"bcm2835-rpi-b-rev2.dtb",
+ true,
},
[BCM2835_BOARD_REV_B_REV2_e] = {
"Model B rev2",
"bcm2835-rpi-b-rev2.dtb",
+ true,
},
[BCM2835_BOARD_REV_B_REV2_f] = {
"Model B rev2",
"bcm2835-rpi-b-rev2.dtb",
+ true,
},
[BCM2835_BOARD_REV_B_PLUS] = {
"Model B+",
"bcm2835-rpi-b-plus.dtb",
+ true,
},
[BCM2835_BOARD_REV_CM] = {
"Compute Module",
"bcm2835-rpi-cm.dtb",
+ false,
+ },
+ [BCM2835_BOARD_REV_A_PLUS] = {
+ "Model A+",
+ "bcm2835-rpi-a-plus.dtb",
+ false,
},
};
return;
fdtfile = models[rpi_board_rev].fdtfile;
- if (!fdtfile)
- fdtfile = "bcm2835-rpi-other.dtb";
-
setenv("fdtfile", fdtfile);
}
ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
int ret;
+ if (!models[rpi_board_rev].has_onboard_eth)
+ return;
+
if (getenv("usbethaddr"))
return;
}
rpi_board_rev = msg->get_board_rev.body.resp.rev;
- if (rpi_board_rev >= ARRAY_SIZE(models))
+ if (rpi_board_rev >= ARRAY_SIZE(models)) {
+ printf("RPI: Board rev %u outside known range\n",
+ rpi_board_rev);
+ rpi_board_rev = 0;
+ }
+ if (!models[rpi_board_rev].name) {
+ printf("RPI: Board rev %u unknown\n", rpi_board_rev);
rpi_board_rev = 0;
+ }
name = models[rpi_board_rev].name;
- if (!name)
- name = "Unknown model";
printf("RPI model: %s\n", name);
}
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+ default "smdk5420"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "odroid_xu3"
+
+endif
+
if TARGET_PEACH_PI
config SYS_BOARD
#include <asm/io.h>
#include <i2c.h>
#include <lcd.h>
+#include <parade.h>
#include <spi.h>
#include <errno.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_USB_EHCI_EXYNOS
-static int board_usb_vbus_init(void)
-{
- /* Enable VBUS power switch */
- gpio_direction_output(EXYNOS5420_GPIO_X26, 1);
-
- /* VBUS turn ON time */
- mdelay(3);
-
- return 0;
-}
-#endif
-
int exynos_init(void)
{
-#ifdef CONFIG_USB_EHCI_EXYNOS
- board_usb_vbus_init();
-#endif
return 0;
}
#endif
setup_mon_len,
setup_fdt,
+#ifdef CONFIG_TRACE
trace_early_init,
+#endif
initf_malloc,
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* TODO: can this go into arch_cpu_init()? */
return 0;
}
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+static int initr_noncached(void)
+{
+ noncached_init();
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DM
static int initr_dm(void)
{
#endif
initr_barrier,
initr_malloc,
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ initr_noncached,
+#endif
bootstage_relocate,
#ifdef CONFIG_DM
initr_dm,
int controller_index = simple_strtoul(usb_controller, NULL, 0);
board_usb_init(controller_index, USB_INIT_DEVICE);
- dfu_clear_detach();
+ g_dnl_clear_detach();
g_dnl_register("usb_dnl_dfu");
while (1) {
- if (dfu_detach()) {
+ if (g_dnl_detach()) {
/*
* Check if USB bus reset is performed after detach,
* which indicates that -R switch has been passed to
if (dfu_reset)
run_command("reset", 0);
- dfu_clear_detach();
+ g_dnl_clear_detach();
return ret;
}
{
int ret;
+ g_dnl_clear_detach();
ret = g_dnl_register("usb_dnl_fastboot");
if (ret)
return ret;
while (1) {
+ if (g_dnl_detach())
+ break;
if (ctrlc())
break;
usb_gadget_handle_interrupts();
}
g_dnl_unregister();
+ g_dnl_clear_detach();
return CMD_RET_SUCCESS;
}
static int do_hash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *s;
-#ifdef CONFIG_HASH_VERIFY
int flags = HASH_FLAG_ENV;
+#ifdef CONFIG_HASH_VERIFY
if (argc < 4)
return CMD_RET_USAGE;
if (!strcmp(argv[1], "-v")) {
argc--;
argv++;
}
-#else
- const int flags = HASH_FLAG_ENV;
#endif
/* Move forward to 'algorithm' parameter */
argc--;
}
#ifdef CONFIG_HASH_VERIFY
-U_BOOT_CMD(
- hash, 6, 1, do_hash,
- "compute hash message digest",
- "algorithm address count [[*]sum_dest]\n"
- " - compute message digest [save to env var / *address]\n"
- "hash -v algorithm address count [*]sum\n"
- " - verify hash of memory area with env var / *address"
-);
+#define HARGS 6
#else
+#define HARGS 5
+#endif
+
U_BOOT_CMD(
- hash, 5, 1, do_hash,
- "compute message digest",
- "algorithm address count [[*]sum_dest]\n"
+ hash, HARGS, 1, do_hash,
+ "compute hash message digest",
+ "algorithm address count [[*]hash_dest]\n"
" - compute message digest [save to env var / *address]"
-);
+#ifdef CONFIG_HASH_VERIFY
+ "\nhash -v algorithm address count [*]hash\n"
+ " - verify message digest of memory area to immediate value, \n"
+ " env var or *address"
#endif
+);
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <config.h>
#include <common.h>
#include <fb_mmc.h>
#include <part.h>
#include <aboot.h>
#include <sparse_format.h>
+#ifndef CONFIG_FASTBOOT_GPT_NAME
+#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
+#endif
+
/* The 64 defined bytes plus the '\0' */
#define RESPONSE_LEN (64 + 1)
void fb_mmc_flash_write(const char *cmd, void *download_buffer,
unsigned int download_bytes, char *response)
{
- int ret;
block_dev_desc_t *dev_desc;
disk_partition_t info;
return;
}
- ret = get_partition_info_efi_by_name(dev_desc, cmd, &info);
- if (ret) {
+ if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
+ printf("%s: updating MBR, Primary and Backup GPT(s)\n",
+ __func__);
+ if (is_valid_gpt_buf(dev_desc, download_buffer)) {
+ printf("%s: invalid GPT - refusing to write to flash\n",
+ __func__);
+ fastboot_fail("invalid GPT partition");
+ return;
+ }
+ if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) {
+ printf("%s: writing GPT partitions failed\n", __func__);
+ fastboot_fail("writing GPT partitions failed");
+ return;
+ }
+ printf("........ success\n");
+ fastboot_okay("");
+ return;
+ } else if (get_partition_info_efi_by_name(dev_desc, cmd, &info)) {
error("cannot find partition: '%s'\n", cmd);
fastboot_fail("cannot find partition");
return;
env_var = 1;
}
- if (env_var) {
+ if (!env_var) {
ulong addr;
void *buf;
{
ulong addr, len;
- if (argc < 2)
+ if ((argc < 2) || ((flags & HASH_FLAG_VERIFY) && (argc < 3)))
return CMD_RET_USAGE;
addr = simple_strtoul(*argv++, NULL, 16);
#else
if (0) {
#endif
- if (!argc)
- return CMD_RET_USAGE;
if (parse_verify_sum(algo, *argv, vsum,
flags & HASH_FLAG_ENV)) {
printf("ERROR: %s does not contain a valid "
CONFIG_ARM=y
-+S:CONFIG_RMOBILE=y
+CONFIG_RMOBILE=y
CONFIG_TARGET_ARMADILLO_800EVA=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_CROWNBAY=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_ARM=y
-+S:CONFIG_RMOBILE=y
+CONFIG_RMOBILE=y
CONFIG_TARGET_KZM9G=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_ODROID_XU3=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
sizeof(efi_guid_t));
}
+static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba,
+ lbaint_t lastlba)
+{
+ uint32_t crc32_backup = 0;
+ uint32_t calc_crc32;
+
+ /* Check the GPT header signature */
+ if (le64_to_cpu(gpt_h->signature) != GPT_HEADER_SIGNATURE) {
+ printf("%s signature is wrong: 0x%llX != 0x%llX\n",
+ "GUID Partition Table Header",
+ le64_to_cpu(gpt_h->signature),
+ GPT_HEADER_SIGNATURE);
+ return -1;
+ }
+
+ /* Check the GUID Partition Table CRC */
+ memcpy(&crc32_backup, &gpt_h->header_crc32, sizeof(crc32_backup));
+ memset(&gpt_h->header_crc32, 0, sizeof(gpt_h->header_crc32));
+
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
+ le32_to_cpu(gpt_h->header_size));
+
+ memcpy(&gpt_h->header_crc32, &crc32_backup, sizeof(crc32_backup));
+
+ if (calc_crc32 != le32_to_cpu(crc32_backup)) {
+ printf("%s CRC is wrong: 0x%x != 0x%x\n",
+ "GUID Partition Table Header",
+ le32_to_cpu(crc32_backup), calc_crc32);
+ return -1;
+ }
+
+ /*
+ * Check that the my_lba entry points to the LBA that contains the GPT
+ */
+ if (le64_to_cpu(gpt_h->my_lba) != lba) {
+ printf("GPT: my_lba incorrect: %llX != " LBAF "\n",
+ le64_to_cpu(gpt_h->my_lba),
+ lba);
+ return -1;
+ }
+
+ /*
+ * Check that the first_usable_lba and that the last_usable_lba are
+ * within the disk.
+ */
+ if (le64_to_cpu(gpt_h->first_usable_lba) > lastlba) {
+ printf("GPT: first_usable_lba incorrect: %llX > " LBAF "\n",
+ le64_to_cpu(gpt_h->first_usable_lba), lastlba);
+ return -1;
+ }
+ if (le64_to_cpu(gpt_h->last_usable_lba) > lastlba) {
+ printf("GPT: last_usable_lba incorrect: %llX > " LBAF "\n",
+ le64_to_cpu(gpt_h->last_usable_lba), lastlba);
+ return -1;
+ }
+
+ debug("GPT: first_usable_lba: %llX last_usable_lba: %llX last lba: "
+ LBAF "\n", le64_to_cpu(gpt_h->first_usable_lba),
+ le64_to_cpu(gpt_h->last_usable_lba), lastlba);
+
+ return 0;
+}
+
+static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e)
+{
+ uint32_t calc_crc32;
+
+ /* Check the GUID Partition Table Entry Array CRC */
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_e,
+ le32_to_cpu(gpt_h->num_partition_entries) *
+ le32_to_cpu(gpt_h->sizeof_partition_entry));
+
+ if (calc_crc32 != le32_to_cpu(gpt_h->partition_entry_array_crc32)) {
+ printf("%s: 0x%x != 0x%x\n",
+ "GUID Partition Table Entry Array CRC is wrong",
+ le32_to_cpu(gpt_h->partition_entry_array_crc32),
+ calc_crc32);
+ return -1;
+ }
+
+ return 0;
+}
+
+static void prepare_backup_gpt_header(gpt_header *gpt_h)
+{
+ uint32_t calc_crc32;
+ uint64_t val;
+
+ /* recalculate the values for the Backup GPT Header */
+ val = le64_to_cpu(gpt_h->my_lba);
+ gpt_h->my_lba = gpt_h->alternate_lba;
+ gpt_h->alternate_lba = cpu_to_le64(val);
+ gpt_h->partition_entry_lba =
+ cpu_to_le64(le64_to_cpu(gpt_h->last_usable_lba) + 1);
+ gpt_h->header_crc32 = 0;
+
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
+ le32_to_cpu(gpt_h->header_size));
+ gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
+}
+
#ifdef CONFIG_EFI_PARTITION
/*
* Public Functions (include/part.h)
const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
* sizeof(gpt_entry)), dev_desc);
u32 calc_crc32;
- u64 val;
debug("max lba: %x\n", (u32) dev_desc->lba);
/* Setup the Protective MBR */
!= pte_blk_cnt)
goto err;
- /* recalculate the values for the Backup GPT Header */
- val = le64_to_cpu(gpt_h->my_lba);
- gpt_h->my_lba = gpt_h->alternate_lba;
- gpt_h->alternate_lba = cpu_to_le64(val);
- gpt_h->header_crc32 = 0;
-
- calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
- le32_to_cpu(gpt_h->header_size));
- gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
+ prepare_backup_gpt_header(gpt_h);
if (dev_desc->block_write(dev_desc->dev,
(lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
free(gpt_h);
return ret;
}
+
+int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf)
+{
+ gpt_header *gpt_h;
+ gpt_entry *gpt_e;
+
+ /* determine start of GPT Header in the buffer */
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
+ dev_desc->blksz);
+ if (validate_gpt_header(gpt_h, GPT_PRIMARY_PARTITION_TABLE_LBA,
+ dev_desc->lba))
+ return -1;
+
+ /* determine start of GPT Entries in the buffer */
+ gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
+ dev_desc->blksz);
+ if (validate_gpt_entries(gpt_h, gpt_e))
+ return -1;
+
+ return 0;
+}
+
+int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf)
+{
+ gpt_header *gpt_h;
+ gpt_entry *gpt_e;
+ int gpt_e_blk_cnt;
+ lbaint_t lba;
+ int cnt;
+
+ if (is_valid_gpt_buf(dev_desc, buf))
+ return -1;
+
+ /* determine start of GPT Header in the buffer */
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
+ dev_desc->blksz);
+
+ /* determine start of GPT Entries in the buffer */
+ gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
+ dev_desc->blksz);
+ gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) *
+ le32_to_cpu(gpt_h->sizeof_partition_entry)),
+ dev_desc);
+
+ /* write MBR */
+ lba = 0; /* MBR is always at 0 */
+ cnt = 1; /* MBR (1 block) */
+ if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) {
+ printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "MBR", cnt, lba);
+ return 1;
+ }
+
+ /* write Primary GPT */
+ lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
+ cnt = 1; /* GPT Header (1 block) */
+ if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Primary GPT Header", cnt, lba);
+ return 1;
+ }
+
+ lba = le64_to_cpu(gpt_h->partition_entry_lba);
+ cnt = gpt_e_blk_cnt;
+ if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Primary GPT Entries", cnt, lba);
+ return 1;
+ }
+
+ prepare_backup_gpt_header(gpt_h);
+
+ /* write Backup GPT */
+ lba = le64_to_cpu(gpt_h->partition_entry_lba);
+ cnt = gpt_e_blk_cnt;
+ if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Backup GPT Entries", cnt, lba);
+ return 1;
+ }
+
+ lba = le64_to_cpu(gpt_h->my_lba);
+ cnt = 1; /* GPT Header (1 block) */
+ if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Backup GPT Header", cnt, lba);
+ return 1;
+ }
+
+ return 0;
+}
#endif
/*
static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
gpt_header *pgpt_head, gpt_entry **pgpt_pte)
{
- u32 crc32_backup = 0;
- u32 calc_crc32;
- u64 lastlba;
-
if (!dev_desc || !pgpt_head) {
printf("%s: Invalid Argument(s)\n", __func__);
return 0;
return 0;
}
- /* Check the GPT header signature */
- if (le64_to_cpu(pgpt_head->signature) != GPT_HEADER_SIGNATURE) {
- printf("GUID Partition Table Header signature is wrong:"
- "0x%llX != 0x%llX\n",
- le64_to_cpu(pgpt_head->signature),
- GPT_HEADER_SIGNATURE);
- return 0;
- }
-
- /* Check the GUID Partition Table CRC */
- memcpy(&crc32_backup, &pgpt_head->header_crc32, sizeof(crc32_backup));
- memset(&pgpt_head->header_crc32, 0, sizeof(pgpt_head->header_crc32));
-
- calc_crc32 = efi_crc32((const unsigned char *)pgpt_head,
- le32_to_cpu(pgpt_head->header_size));
-
- memcpy(&pgpt_head->header_crc32, &crc32_backup, sizeof(crc32_backup));
-
- if (calc_crc32 != le32_to_cpu(crc32_backup)) {
- printf("GUID Partition Table Header CRC is wrong:"
- "0x%x != 0x%x\n",
- le32_to_cpu(crc32_backup), calc_crc32);
- return 0;
- }
-
- /* Check that the my_lba entry points to the LBA that contains the GPT */
- if (le64_to_cpu(pgpt_head->my_lba) != lba) {
- printf("GPT: my_lba incorrect: %llX != %" PRIX64 "\n",
- le64_to_cpu(pgpt_head->my_lba),
- lba);
+ if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
return 0;
- }
-
- /* Check the first_usable_lba and last_usable_lba are within the disk. */
- lastlba = (u64)dev_desc->lba;
- if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) {
- printf("GPT: first_usable_lba incorrect: %llX > %" PRIX64 "\n",
- le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
- return 0;
- }
- if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) {
- printf("GPT: last_usable_lba incorrect: %llX > %" PRIX64 "\n",
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
- return 0;
- }
-
- debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %"
- PRIX64 "\n", le64_to_cpu(pgpt_head->first_usable_lba),
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
/* Read and allocate Partition Table Entries */
*pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
return 0;
}
- /* Check the GUID Partition Table Entry Array CRC */
- calc_crc32 = efi_crc32((const unsigned char *)*pgpt_pte,
- le32_to_cpu(pgpt_head->num_partition_entries) *
- le32_to_cpu(pgpt_head->sizeof_partition_entry));
-
- if (calc_crc32 != le32_to_cpu(pgpt_head->partition_entry_array_crc32)) {
- printf("GUID Partition Table Entry Array CRC is wrong:"
- "0x%x != 0x%x\n",
- le32_to_cpu(pgpt_head->partition_entry_array_crc32),
- calc_crc32);
-
+ if (validate_gpt_entries(pgpt_head, *pgpt_pte)) {
free(*pgpt_pte);
return 0;
}
- U-boot for Odroid X2/U3
+ U-boot for Odroid X2/U3/XU3
========================
1. Summary
==========
-This is a quick instruction for setup Odroid boards based on Exynos4412.
-Board config: odroid_config
+This is a quick instruction for setup Odroid boards.
+Board config: odroid_config for X2/U3
+Board config: odroid-xu3_config for XU3
2. Supported devices
====================
-This U-BOOT config can be used on two boards:
+This U-BOOT config can be used on three boards:
- Odroid U3
- Odroid X2
with CPU Exynos 4412 rev 2.0 and 2GB of RAM
+- Odroid XU3
+with CPU Exynos5422 and 2GB of RAM
3. Boot sequence
================
iROM->BL1->(BL2 + TrustZone)->U-BOOT
-This version of U-BOOT doesn't implement SPL but it is required(BL2)
-and can be found in "boot.tar.gz" from here:
+This version of U-BOOT doesn't implement SPL. So, BL1, BL2, and TrustZone
+binaries are needed to boot up.
+
+<< X2/U3 >>
+It can be found in "boot.tar.gz" from here:
http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&value=boot.tar.gz
or here:
http://odroid.in/guides/ubuntu-lfs/boot.tar.gz
+<< XU3 >>
+It can be downloaded from:
+https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel
+
+
4. Boot media layout
====================
The table below shows SD/eMMC cards layout for U-boot.
| Bl2 | 31 | 30 | 1 (boot) |
| U-boot | 63 | 62 | 1 (boot) |
| Tzsw | 2111 | 2110 | 1 (boot) |
-| Uboot Env | 2500 | 2500 | 0 (user) |
+| Uboot Env | 2560 | 2560 | 0 (user) |
-------------------------------------
5. Prepare the SD boot card - with SD card reader
=================================================
To prepare bootable media you need boot binaries provided by hardkernel.
-File "boot.tar.gz" (link in point 3.) contains:
-- E4412_S.bl1.HardKernel.bin
-- E4412_S.tzsw.signed.bin
-- bl2.signed.bin
+From the downloaded files, You can find:
+- bl1.bin
+- tzsw.bin
+- bl2.bin
- sd_fusing.sh
- u-boot.bin
+(The file names can be slightly different, but you can distinguish what they are
+without problem)
This is all you need to boot this board. But if you want to use your custom
u-boot then you need to change u-boot.bin with your own u-boot binary*
The proper binary file of current U-boot is u-boot-dtb.bin.
quick steps for Linux:
-- extract boot.tar.gz
+- Download all files from the link at point 3 and extract it if needed.
- put any SD card into the SD reader
- check the device with "dmesg"
- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition)
with a eMMC card reader (boot from eMMC card slot)
=====================================================
To boot the device from the eMMC slot you should use a special card reader
-which supports eMMC partiion switch. All of the boot binaries are stored
+which supports eMMC partition switch. All of the boot binaries are stored
on the eMMC boot partition which is normally hidden.
The "sd_fusing.sh" script can be used after updating offsets of binaries
8. Prepare the boot media using Hardkernel U-boot
=================================================
-You can update the U-boot to the custom one if you have an working bootloader
-delivered with the board on a eMMC/SD card. Then follow the steps:
+You can update the U-boot to the custom one if you have a working bootloader
+delivered with the board on the eMMC/SD card. Then follow the steps:
- install the android fastboot tool
- connect a micro usb cable to the board
- on the U-boot prompt, run command: fastboot (as a root)
9. Partition layout
====================
-Default U-boot environment is setup for fixed partiion layout.
+Default U-boot environment is setup for fixed partition layout.
Partition table: MSDOS. Disk layout and files as listed in the table below.
----- ------ ------ ------ -------- ---------------------------------
Supported fdt files are:
- exynos4412-odroidx2.dtb
- exynos4412-odroidu3.dtb
+- exynos5422-odroidxu3.dtb
Supported kernel files are:
- Image.itb
11. USB host support
====================
+NOTE: This section is only for Odroid X2/U3.
The ethernet can be accessed after starting the USB subsystem in U-Boot.
The adapter does not come with a preconfigured MAC address, and hence it needs
--- /dev/null
+#
+# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+U-Boot on x86
+=============
+
+This document describes the information about U-Boot running on x86 targets,
+including supported boards, build instructions, todo list, etc.
+
+Status
+------
+U-Boot supports running as a coreboot [1] payload on x86. So far only Link
+(Chromebook Pixel) has been tested, but it should work with minimal adjustments
+on other x86 boards since coreboot deals with most of the low-level details.
+
+U-Boot also supports booting directly from x86 reset vector without coreboot,
+aka raw support or bare support. Currently Link and Intel Crown Bay board
+support running U-Boot 'bare metal'.
+
+As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
+kernel as part of a FIT image. It also supports a compressed zImage.
+
+Build Instructions
+------------------
+Building U-Boot as a coreboot payload is just like building U-Boot for targets
+on other architectures, like below:
+
+$ make coreboot-x86_defconfig
+$ make all
+
+Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
+little bit tricky, as generally it requires several binary blobs which are not
+shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
+not turned on by default in the U-Boot source tree. Firstly, you need turn it
+on by uncommenting the following line in the main U-Boot Makefile:
+
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
+Link-specific instructions:
+
+First, you need the following binary blobs:
+
+* descriptor.bin - Intel flash descriptor
+* me.bin - Intel Management Engine
+* mrc.bin - Memory Reference Code, which sets up SDRAM
+* video ROM - sets up the display
+
+You can get these binary blobs by:
+
+$ git clone http://review.coreboot.org/p/blobs.git
+$ cd blobs
+
+Find the following files:
+
+* ./mainboard/google/link/descriptor.bin
+* ./mainboard/google/link/me.bin
+* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
+
+The 3rd one should be renamed to mrc.bin.
+As for the video ROM, you can get it here [2].
+Make sure all these binary blobs are put in the board directory.
+
+Now you can build U-Boot and obtain u-boot.rom:
+
+$ make chromebook_link_defconfig
+$ make all
+
+Intel Crown Bay specific instructions:
+
+U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
+Firmware Support Package [4] to perform all the necessary initialization steps
+as documented in the BIOS Writer Guide, including initialization of the CPU,
+memory controller, chipset and certain bus interfaces.
+
+Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
+install it on your host and locate the FSP binary blob. Note this platform
+also requires a Chipset Micro Code (CMC) state machine binary to be present in
+the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
+in this FSP package too.
+
+* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
+* ./Microcode/C0_22211.BIN
+
+Rename the first one to fsp.bin and second one to cmc.bin and put them in the
+board directory.
+
+Now you can build U-Boot and obtaim u-boot.rom
+
+$ make crownbay_defconfig
+$ make all
+
+CPU Microcode
+-------------
+Modern CPU usually requires a special bit stream called microcode [5] to be
+loaded on the processor after power up in order to function properly. U-Boot
+has already integrated these as hex dumps in the source tree.
+
+Driver Model
+------------
+x86 has been converted to use driver model for serial and GPIO.
+
+Device Tree
+-----------
+x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
+be turned on. Not every device on the board is configured via devie tree, but
+more and more devices will be added as time goes by. Check out the directory
+arch/x86/dts/ for these device tree source files.
+
+TODO List
+---------
+- MTRR support (for performance)
+- Audio
+- Chrome OS verified boot
+- SMI and ACPI support, to provide platform info and facilities to Linux
+
+References
+----------
+[1] http://www.coreboot.org
+[2] http://www.coreboot.org/~stepan/pci8086,0166.rom
+[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
+[4] http://www.intel.com/fsp
+[5] http://en.wikipedia.org/wiki/Microcode
#include <linux/list.h>
#include <linux/compiler.h>
-static bool dfu_detach_request;
static LIST_HEAD(dfu_list);
static int dfu_alt_num;
static int alt_num_cnt;
return true;
}
-bool dfu_detach(void)
-{
- return dfu_detach_request;
-}
-
-void dfu_trigger_detach(void)
-{
- dfu_detach_request = true;
-}
-
-void dfu_clear_detach(void)
-{
- dfu_detach_request = false;
-}
-
static int dfu_find_alt_num(const char *s)
{
int i = 0;
return dfu_buf;
s = getenv("dfu_bufsiz");
- dfu_buf_size = s ? (unsigned long)simple_strtol(s, NULL, 16) :
- CONFIG_SYS_DFU_DATA_BUF_SIZE;
+ if (s)
+ dfu_buf_size = (unsigned long)simple_strtol(s, NULL, 0);
+
+ if (!s || !dfu_buf_size)
+ dfu_buf_size = CONFIG_SYS_DFU_DATA_BUF_SIZE;
+
if (dfu->max_buf_size && dfu_buf_size > dfu->max_buf_size)
dfu_buf_size = dfu->max_buf_size;
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
u64 offset, void *buf, long *len)
{
- struct mmc *mmc = find_mmc_device(dfu->data.mmc.dev_num);
+ struct mmc *mmc;
u32 blk_start, blk_count, n = 0;
int ret, part_num_bkp = 0;
+ mmc = find_mmc_device(dfu->data.mmc.dev_num);
+ if (!mmc) {
+ error("Device MMC %d - not found!", dfu->data.mmc.dev_num);
+ return -ENODEV;
+ }
+
/*
* We must ensure that we work in lba_blk_size chunks, so ALIGN
* this value.
struct ich6_bank_priv {
/* These are I/O addresses */
- uint32_t use_sel;
- uint32_t io_sel;
- uint32_t lvl;
+ uint16_t use_sel;
+ uint16_t io_sel;
+ uint16_t lvl;
};
/* TODO: Move this to device tree, or platform data */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u32 gpiobase;
+ u16 gpiobase;
int offset;
/* Where should it be? */
/*
* GPIOBASE moved to its current offset with ICH6, but prior to
* that it was unused (or undocumented). Check that it looks
- * okay: not all ones or zeros, and mapped to I/O space (bit 0).
+ * okay: not all ones or zeros.
+ *
+ * Note we don't need check bit0 here, because the Tunnel Creek
+ * GPIO base address register bit0 is reserved (read returns 0),
+ * while on the Ivybridge the bit0 is used to indicate it is an
+ * I/O space.
*/
tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
- if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
- !(tmplong & 0x00000001)) {
+ if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
debug("%s: unexpected GPIOBASE value\n", __func__);
return -ENODEV;
}
* at the offset that we just read. Bit 0 indicates that it's
* an I/O address, not a memory address, so mask that off.
*/
- gpiobase = tmplong & 0xfffffffe;
+ gpiobase = tmplong & 0xfffe;
offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
if (offset == -1) {
debug("%s: Invalid register offset %d\n", __func__, offset);
* Modified to use le32_to_cpu and cpu_to_le32 properly
*/
#include <common.h>
+#include <errno.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
-#define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
+#ifdef CONFIG_SYS_RX_ETH_BUFFER
+ #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
+#else
+ #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
+#endif
#define RX_BUF_SIZE 1536 /* Rx Buffer size */
#define RX_BUF_LEN 8192
{"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
{"RTL-8168d/8111d", 0x28, 0xff7e1880,},
{"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
+ {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
{"RTL-8101e", 0x34, 0xff7e1880,},
{"RTL-8100e", 0x32, 0xff7e1880,},
};
u32 buf_Haddr;
};
-/* Define the TX Descriptor */
-static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
-/* __attribute__ ((aligned(256))); */
+#define RTL8169_DESC_SIZE 16
-/* Create a static buffer of size RX_BUF_SZ for each
-TX Descriptor. All descriptors point to a
-part of this buffer */
-static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
+#if ARCH_DMA_MINALIGN > 256
+# define RTL8169_ALIGN ARCH_DMA_MINALIGN
+#else
+# define RTL8169_ALIGN 256
+#endif
-/* Define the RX Descriptor */
-static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
- /* __attribute__ ((aligned(256))); */
+/*
+ * Warn if the cache-line size is larger than the descriptor size. In such
+ * cases the driver will likely fail because the CPU needs to flush the cache
+ * when requeuing RX buffers, therefore descriptors written by the hardware
+ * may be discarded.
+ *
+ * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
+ * the driver to allocate descriptors from a pool of non-cached memory.
+ */
+#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
+#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && !defined(CONFIG_SYS_DCACHE_OFF)
+#warning cache-line size is larger than descriptor size
+#endif
+#endif
-/* Create a static buffer of size RX_BUF_SZ for each
-RX Descriptor All descriptors point to a
-part of this buffer */
-static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
+/*
+ * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
+ * descriptors point to a part of this buffer.
+ */
+DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
+
+/*
+ * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
+ * descriptors point to a part of this buffer.
+ */
+DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
struct rtl8169_private {
void *mmio_addr; /* memory map physical address */
unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
unsigned long dirty_tx;
- unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
- unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
unsigned char *RxBufferRings; /* Index of Rx Buffer */
return 0;
}
+/*
+ * TX and RX descriptors are 16 bytes. This causes problems with the cache
+ * maintenance on CPUs where the cache-line size exceeds the size of these
+ * descriptors. What will happen is that when the driver receives a packet
+ * it will be immediately requeued for the hardware to reuse. The CPU will
+ * therefore need to flush the cache-line containing the descriptor, which
+ * will cause all other descriptors in the same cache-line to be flushed
+ * along with it. If one of those descriptors had been written to by the
+ * device those changes (and the associated packet) will be lost.
+ *
+ * To work around this, we make use of non-cached memory if available. If
+ * descriptors are mapped uncached there's no need to manually flush them
+ * or invalidate them.
+ *
+ * Note that this only applies to descriptors. The packet data buffers do
+ * not have the same constraints since they are 1536 bytes large, so they
+ * are unlikely to share cache-lines.
+ */
+static void *rtl_alloc_descs(unsigned int num)
+{
+ size_t size = num * RTL8169_DESC_SIZE;
+
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ return (void *)noncached_alloc(size, RTL8169_ALIGN);
+#else
+ return memalign(RTL8169_ALIGN, size);
+#endif
+}
+
/*
* Cache maintenance functions. These are simple wrappers around the more
* general purpose flush_cache() and invalidate_dcache_range() functions.
static void rtl_inval_rx_desc(struct RxDesc *desc)
{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
+#endif
}
static void rtl_flush_rx_desc(struct RxDesc *desc)
{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
flush_cache((unsigned long)desc, sizeof(*desc));
+#endif
}
static void rtl_inval_tx_desc(struct TxDesc *desc)
{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
+#endif
}
static void rtl_flush_tx_desc(struct TxDesc *desc)
{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
flush_cache((unsigned long)desc, sizeof(*desc));
+#endif
}
static void rtl_inval_buffer(void *buf, size_t size)
printf ("%s\n", __FUNCTION__);
#endif
- tpc->TxDescArrays = tx_ring;
- /* Tx Desscriptor needs 256 bytes alignment; */
- tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
- 255) & ~255);
-
- tpc->RxDescArrays = rx_ring;
- /* Rx Desscriptor needs 256 bytes alignment; */
- tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
- 255) & ~255);
-
rtl8169_init_ring(dev);
rtl8169_hw_start(dev);
/* Construct a perfect filter frame with the mac address as first match
RTL_W32(RxMissed, 0);
- tpc->TxDescArrays = NULL;
- tpc->RxDescArrays = NULL;
- tpc->TxDescArray = NULL;
- tpc->RxDescArray = NULL;
for (i = 0; i < NUM_RX_DESC; i++) {
tpc->RxBufferRing[i] = NULL;
}
#endif
}
- return 1;
+
+ tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
+ if (!tpc->RxDescArray)
+ return -ENOMEM;
+
+ tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
+ if (!tpc->TxDescArray)
+ return -ENOMEM;
+
+ return 0;
}
int rtl8169_initialize(bd_t *bis)
while(1){
unsigned int region;
u16 device;
+ int err;
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
dev->send = rtl_send;
dev->recv = rtl_recv;
- eth_register (dev);
+ err = rtl_init(dev, bis);
+ if (err < 0) {
+ printf(pr_fmt("failed to initialize card: %d\n"), err);
+ free(dev);
+ continue;
+ }
- rtl_init(dev, bis);
+ eth_register (dev);
card_number++;
}
obj-$(CONFIG_SH4_PCI) += pci_sh4.o
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
+obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
--- /dev/null
+/*
+ * Copyright (c) 2010, CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on NVIDIA PCIe driver
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * Copyright (c) 2013-2014, NVIDIA Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#define DEBUG
+#define pr_fmt(fmt) "tegra-pcie: " fmt
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <pci.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/powergate.h>
+#include <asm/arch-tegra/xusb-padctl.h>
+
+#include <linux/list.h>
+
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AFI_AXI_BAR0_SZ 0x00
+#define AFI_AXI_BAR1_SZ 0x04
+#define AFI_AXI_BAR2_SZ 0x08
+#define AFI_AXI_BAR3_SZ 0x0c
+#define AFI_AXI_BAR4_SZ 0x10
+#define AFI_AXI_BAR5_SZ 0x14
+
+#define AFI_AXI_BAR0_START 0x18
+#define AFI_AXI_BAR1_START 0x1c
+#define AFI_AXI_BAR2_START 0x20
+#define AFI_AXI_BAR3_START 0x24
+#define AFI_AXI_BAR4_START 0x28
+#define AFI_AXI_BAR5_START 0x2c
+
+#define AFI_FPCI_BAR0 0x30
+#define AFI_FPCI_BAR1 0x34
+#define AFI_FPCI_BAR2 0x38
+#define AFI_FPCI_BAR3 0x3c
+#define AFI_FPCI_BAR4 0x40
+#define AFI_FPCI_BAR5 0x44
+
+#define AFI_CACHE_BAR0_SZ 0x48
+#define AFI_CACHE_BAR0_ST 0x4c
+#define AFI_CACHE_BAR1_SZ 0x50
+#define AFI_CACHE_BAR1_ST 0x54
+
+#define AFI_MSI_BAR_SZ 0x60
+#define AFI_MSI_FPCI_BAR_ST 0x64
+#define AFI_MSI_AXI_BAR_ST 0x68
+
+#define AFI_CONFIGURATION 0xac
+#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
+
+#define AFI_FPCI_ERROR_MASKS 0xb0
+
+#define AFI_INTR_MASK 0xb4
+#define AFI_INTR_MASK_INT_MASK (1 << 0)
+#define AFI_INTR_MASK_MSI_MASK (1 << 8)
+
+#define AFI_SM_INTR_ENABLE 0xc4
+#define AFI_SM_INTR_INTA_ASSERT (1 << 0)
+#define AFI_SM_INTR_INTB_ASSERT (1 << 1)
+#define AFI_SM_INTR_INTC_ASSERT (1 << 2)
+#define AFI_SM_INTR_INTD_ASSERT (1 << 3)
+#define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
+#define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
+#define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
+#define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
+
+#define AFI_AFI_INTR_ENABLE 0xc8
+#define AFI_INTR_EN_INI_SLVERR (1 << 0)
+#define AFI_INTR_EN_INI_DECERR (1 << 1)
+#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
+#define AFI_INTR_EN_TGT_DECERR (1 << 3)
+#define AFI_INTR_EN_TGT_WRERR (1 << 4)
+#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
+#define AFI_INTR_EN_AXI_DECERR (1 << 6)
+#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
+#define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
+
+#define AFI_PCIE_CONFIG 0x0f8
+#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
+#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
+
+#define AFI_FUSE 0x104
+#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
+
+#define AFI_PEX0_CTRL 0x110
+#define AFI_PEX1_CTRL 0x118
+#define AFI_PEX2_CTRL 0x128
+#define AFI_PEX_CTRL_RST (1 << 0)
+#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
+#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
+#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
+
+#define AFI_PLLE_CONTROL 0x160
+#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
+#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
+
+#define AFI_PEXBIAS_CTRL_0 0x168
+
+#define PADS_CTL_SEL 0x0000009C
+
+#define PADS_CTL 0x000000A0
+#define PADS_CTL_IDDQ_1L (1 << 0)
+#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
+#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
+
+#define PADS_PLL_CTL_TEGRA20 0x000000B8
+#define PADS_PLL_CTL_TEGRA30 0x000000B4
+#define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
+#define PADS_PLL_CTL_LOCKDET (0x1 << 8)
+#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
+#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
+#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
+#define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
+#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
+#define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
+#define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
+#define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
+
+#define PADS_REFCLK_CFG0 0x000000C8
+#define PADS_REFCLK_CFG1 0x000000CC
+
+/*
+ * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
+ * entries, one entry per PCIe port. These field definitions and desired
+ * values aren't in the TRM, but do come from NVIDIA.
+ */
+#define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
+#define PADS_REFCLK_CFG_E_TERM_SHIFT 7
+#define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
+#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
+
+/* Default value provided by HW engineering is 0xfa5c */
+#define PADS_REFCLK_CFG_VALUE \
+ ( \
+ (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
+ (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
+ (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
+ (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
+ )
+
+#define RP_VEND_XP 0x00000F00
+#define RP_VEND_XP_DL_UP (1 << 30)
+
+#define RP_PRIV_MISC 0x00000FE0
+#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
+#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
+
+#define RP_LINK_CONTROL_STATUS 0x00000090
+#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
+#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
+
+struct tegra_pcie;
+
+struct tegra_pcie_port {
+ struct tegra_pcie *pcie;
+
+ struct fdt_resource regs;
+ unsigned int num_lanes;
+ unsigned int index;
+
+ struct list_head list;
+};
+
+struct tegra_pcie_soc {
+ unsigned int num_ports;
+ unsigned long pads_pll_ctl;
+ unsigned long tx_ref_sel;
+ bool has_pex_clkreq_en;
+ bool has_pex_bias_ctrl;
+ bool has_cml_clk;
+ bool has_gen2;
+};
+
+struct tegra_pcie {
+ struct pci_controller hose;
+
+ struct fdt_resource pads;
+ struct fdt_resource afi;
+ struct fdt_resource cs;
+
+ struct fdt_resource prefetch;
+ struct fdt_resource mem;
+ struct fdt_resource io;
+
+ struct list_head ports;
+ unsigned long xbar;
+
+ const struct tegra_pcie_soc *soc;
+ struct tegra_xusb_phy *phy;
+};
+
+static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose)
+{
+ return container_of(hose, struct tegra_pcie, hose);
+}
+
+static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
+ unsigned long offset)
+{
+ writel(value, pcie->afi.start + offset);
+}
+
+static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
+{
+ return readl(pcie->afi.start + offset);
+}
+
+static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
+ unsigned long offset)
+{
+ writel(value, pcie->pads.start + offset);
+}
+
+static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
+{
+ return readl(pcie->pads.start + offset);
+}
+
+static unsigned long rp_readl(struct tegra_pcie_port *port,
+ unsigned long offset)
+{
+ return readl(port->regs.start + offset);
+}
+
+static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
+ unsigned long offset)
+{
+ writel(value, port->regs.start + offset);
+}
+
+static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
+{
+ return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
+ (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
+ (where & 0xfc);
+}
+
+static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
+ int where, unsigned long *address)
+{
+ unsigned int bus = PCI_BUS(bdf);
+
+ if (bus == 0) {
+ unsigned int dev = PCI_DEV(bdf);
+ struct tegra_pcie_port *port;
+
+ list_for_each_entry(port, &pcie->ports, list) {
+ if (port->index + 1 == dev) {
+ *address = port->regs.start + (where & ~3);
+ return 0;
+ }
+ }
+ } else {
+ *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
+ return 0;
+ }
+
+ return -1;
+}
+
+static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf,
+ int where, u32 *value)
+{
+ struct tegra_pcie *pcie = to_tegra_pcie(hose);
+ unsigned long address;
+ int err;
+
+ err = tegra_pcie_conf_address(pcie, bdf, where, &address);
+ if (err < 0) {
+ *value = 0xffffffff;
+ return 1;
+ }
+
+ *value = readl(address);
+
+ /* fixup root port class */
+ if (PCI_BUS(bdf) == 0) {
+ if (where == PCI_CLASS_REVISION) {
+ *value &= ~0x00ff0000;
+ *value |= PCI_CLASS_BRIDGE_PCI << 16;
+ }
+ }
+
+ return 0;
+}
+
+static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf,
+ int where, u32 value)
+{
+ struct tegra_pcie *pcie = to_tegra_pcie(hose);
+ unsigned long address;
+ int err;
+
+ err = tegra_pcie_conf_address(pcie, bdf, where, &address);
+ if (err < 0)
+ return 1;
+
+ writel(value, address);
+
+ return 0;
+}
+
+static int tegra_pcie_port_parse_dt(const void *fdt, int node,
+ struct tegra_pcie_port *port)
+{
+ const u32 *addr;
+ int len;
+
+ addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
+ if (!addr) {
+ error("property \"assigned-addresses\" not found");
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ port->regs.start = fdt32_to_cpu(addr[2]);
+ port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
+
+ return 0;
+}
+
+static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
+ unsigned long *xbar)
+{
+ enum fdt_compat_id id = fdtdec_lookup(fdt, node);
+
+ switch (id) {
+ case COMPAT_NVIDIA_TEGRA20_PCIE:
+ switch (lanes) {
+ case 0x00000004:
+ debug("single-mode configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
+ return 0;
+
+ case 0x00000202:
+ debug("dual-mode configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
+ return 0;
+ }
+ break;
+
+ case COMPAT_NVIDIA_TEGRA30_PCIE:
+ switch (lanes) {
+ case 0x00000204:
+ debug("4x1, 2x1 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
+ return 0;
+
+ case 0x00020202:
+ debug("2x3 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
+ return 0;
+
+ case 0x00010104:
+ debug("4x1, 1x2 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
+ return 0;
+ }
+ break;
+
+ case COMPAT_NVIDIA_TEGRA124_PCIE:
+ switch (lanes) {
+ case 0x0000104:
+ debug("4x1, 1x1 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
+ return 0;
+
+ case 0x0000102:
+ debug("2x1, 1x1 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
+ return 0;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return -FDT_ERR_NOTFOUND;
+}
+
+static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
+ struct tegra_pcie *pcie)
+{
+ const u32 *ptr, *end;
+ int len;
+
+ ptr = fdt_getprop(fdt, node, "ranges", &len);
+ if (!ptr) {
+ error("missing \"ranges\" property");
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ end = ptr + len / 4;
+
+ while (ptr < end) {
+ struct fdt_resource *res = NULL;
+ u32 space = fdt32_to_cpu(*ptr);
+
+ switch ((space >> 24) & 0x3) {
+ case 0x01:
+ res = &pcie->io;
+ break;
+
+ case 0x02: /* 32 bit */
+ case 0x03: /* 64 bit */
+ if (space & (1 << 30))
+ res = &pcie->prefetch;
+ else
+ res = &pcie->mem;
+
+ break;
+ }
+
+ if (res) {
+ res->start = fdt32_to_cpu(ptr[3]);
+ res->end = res->start + fdt32_to_cpu(ptr[5]);
+ }
+
+ ptr += 3 + 1 + 2;
+ }
+
+ debug("PCI regions:\n");
+ debug(" I/O: %#x-%#x\n", pcie->io.start, pcie->io.end);
+ debug(" non-prefetchable memory: %#x-%#x\n", pcie->mem.start,
+ pcie->mem.end);
+ debug(" prefetchable memory: %#x-%#x\n", pcie->prefetch.start,
+ pcie->prefetch.end);
+
+ return 0;
+}
+
+static int tegra_pcie_parse_port_info(const void *fdt, int node,
+ unsigned int *index,
+ unsigned int *lanes)
+{
+ pci_dev_t bdf;
+ int err;
+
+ err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
+ if (err < 0) {
+ error("failed to parse \"nvidia,num-lanes\" property");
+ return err;
+ }
+
+ *lanes = err;
+
+ err = fdtdec_pci_get_bdf(fdt, node, &bdf);
+ if (err < 0) {
+ error("failed to parse \"reg\" property");
+ return err;
+ }
+
+ *index = PCI_DEV(bdf) - 1;
+
+ return 0;
+}
+
+static int tegra_pcie_parse_dt(const void *fdt, int node,
+ struct tegra_pcie *pcie)
+{
+ int err, subnode;
+ u32 lanes = 0;
+
+ err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
+ &pcie->pads);
+ if (err < 0) {
+ error("resource \"pads\" not found");
+ return err;
+ }
+
+ err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
+ &pcie->afi);
+ if (err < 0) {
+ error("resource \"afi\" not found");
+ return err;
+ }
+
+ err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
+ &pcie->cs);
+ if (err < 0) {
+ error("resource \"cs\" not found");
+ return err;
+ }
+
+ pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
+ if (pcie->phy) {
+ err = tegra_xusb_phy_prepare(pcie->phy);
+ if (err < 0) {
+ error("failed to prepare PHY: %d", err);
+ return err;
+ }
+ }
+
+ err = tegra_pcie_parse_dt_ranges(fdt, node, pcie);
+ if (err < 0) {
+ error("failed to parse \"ranges\" property");
+ return err;
+ }
+
+ fdt_for_each_subnode(fdt, subnode, node) {
+ unsigned int index = 0, num_lanes = 0;
+ struct tegra_pcie_port *port;
+
+ err = tegra_pcie_parse_port_info(fdt, subnode, &index,
+ &num_lanes);
+ if (err < 0) {
+ error("failed to obtain root port info");
+ continue;
+ }
+
+ lanes |= num_lanes << (index << 3);
+
+ if (!fdtdec_get_is_enabled(fdt, subnode))
+ continue;
+
+ port = malloc(sizeof(*port));
+ if (!port)
+ continue;
+
+ memset(port, 0, sizeof(*port));
+ port->num_lanes = num_lanes;
+ port->index = index;
+
+ err = tegra_pcie_port_parse_dt(fdt, subnode, port);
+ if (err < 0) {
+ free(port);
+ continue;
+ }
+
+ list_add_tail(&port->list, &pcie->ports);
+ port->pcie = pcie;
+ }
+
+ err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar);
+ if (err < 0) {
+ error("invalid lane configuration");
+ return err;
+ }
+
+ return 0;
+}
+
+int __weak tegra_pcie_board_init(void)
+{
+ return 0;
+}
+
+static int tegra_pcie_power_on(struct tegra_pcie *pcie)
+{
+ const struct tegra_pcie_soc *soc = pcie->soc;
+ unsigned long value;
+ int err;
+
+ /* reset PCIEXCLK logic, AFI controller and PCIe controller */
+ reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
+ reset_set_enable(PERIPH_ID_AFI, 1);
+ reset_set_enable(PERIPH_ID_PCIE, 1);
+
+ err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
+ if (err < 0) {
+ error("failed to power off PCIe partition: %d", err);
+ return err;
+ }
+
+ tegra_pcie_board_init();
+
+ err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
+ PERIPH_ID_PCIE);
+ if (err < 0) {
+ error("failed to power up PCIe partition: %d", err);
+ return err;
+ }
+
+ /* take AFI controller out of reset */
+ reset_set_enable(PERIPH_ID_AFI, 0);
+
+ /* enable AFI clock */
+ clock_enable(PERIPH_ID_AFI);
+
+ if (soc->has_cml_clk) {
+ /* enable CML clock */
+ value = readl(NV_PA_CLK_RST_BASE + 0x48c);
+ value |= (1 << 0);
+ value &= ~(1 << 1);
+ writel(value, NV_PA_CLK_RST_BASE + 0x48c);
+ }
+
+ err = tegra_plle_enable();
+ if (err < 0) {
+ error("failed to enable PLLE: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
+{
+ const struct tegra_pcie_soc *soc = pcie->soc;
+ unsigned long start = get_timer(0);
+ u32 value;
+
+ while (get_timer(start) < timeout) {
+ value = pads_readl(pcie, soc->pads_pll_ctl);
+ if (value & PADS_PLL_CTL_LOCKDET)
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
+{
+ const struct tegra_pcie_soc *soc = pcie->soc;
+ u32 value;
+ int err;
+
+ /* initialize internal PHY, enable up to 16 PCIe lanes */
+ pads_writel(pcie, 0, PADS_CTL_SEL);
+
+ /* override IDDQ to 1 on all 4 lanes */
+ value = pads_readl(pcie, PADS_CTL);
+ value |= PADS_CTL_IDDQ_1L;
+ pads_writel(pcie, value, PADS_CTL);
+
+ /*
+ * Set up PHY PLL inputs select PLLE output as refclock, set TX
+ * ref sel to div10 (not div5).
+ */
+ value = pads_readl(pcie, soc->pads_pll_ctl);
+ value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
+ value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
+ pads_writel(pcie, value, soc->pads_pll_ctl);
+
+ /* reset PLL */
+ value = pads_readl(pcie, soc->pads_pll_ctl);
+ value &= ~PADS_PLL_CTL_RST_B4SM;
+ pads_writel(pcie, value, soc->pads_pll_ctl);
+
+ udelay(20);
+
+ /* take PLL out of reset */
+ value = pads_readl(pcie, soc->pads_pll_ctl);
+ value |= PADS_PLL_CTL_RST_B4SM;
+ pads_writel(pcie, value, soc->pads_pll_ctl);
+
+ /* configure the reference clock driver */
+ value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
+ pads_writel(pcie, value, PADS_REFCLK_CFG0);
+
+ if (soc->num_ports > 2)
+ pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
+
+ /* wait for the PLL to lock */
+ err = tegra_pcie_pll_wait(pcie, 500);
+ if (err < 0) {
+ error("PLL failed to lock: %d", err);
+ return err;
+ }
+
+ /* turn off IDDQ override */
+ value = pads_readl(pcie, PADS_CTL);
+ value &= ~PADS_CTL_IDDQ_1L;
+ pads_writel(pcie, value, PADS_CTL);
+
+ /* enable TX/RX data */
+ value = pads_readl(pcie, PADS_CTL);
+ value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
+ pads_writel(pcie, value, PADS_CTL);
+
+ return 0;
+}
+
+static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
+{
+ const struct tegra_pcie_soc *soc = pcie->soc;
+ struct tegra_pcie_port *port;
+ u32 value;
+ int err;
+
+ if (pcie->phy) {
+ value = afi_readl(pcie, AFI_PLLE_CONTROL);
+ value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
+ value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
+ afi_writel(pcie, value, AFI_PLLE_CONTROL);
+ }
+
+ if (soc->has_pex_bias_ctrl)
+ afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
+
+ value = afi_readl(pcie, AFI_PCIE_CONFIG);
+ value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
+ value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
+
+ list_for_each_entry(port, &pcie->ports, list)
+ value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
+
+ afi_writel(pcie, value, AFI_PCIE_CONFIG);
+
+ value = afi_readl(pcie, AFI_FUSE);
+
+ if (soc->has_gen2)
+ value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
+ else
+ value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
+
+ afi_writel(pcie, value, AFI_FUSE);
+
+ if (pcie->phy)
+ err = tegra_xusb_phy_enable(pcie->phy);
+ else
+ err = tegra_pcie_phy_enable(pcie);
+
+ if (err < 0) {
+ error("failed to power on PHY: %d\n", err);
+ return err;
+ }
+
+ /* take the PCIEXCLK logic out of reset */
+ reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
+
+ /* finally enable PCIe */
+ value = afi_readl(pcie, AFI_CONFIGURATION);
+ value |= AFI_CONFIGURATION_EN_FPCI;
+ afi_writel(pcie, value, AFI_CONFIGURATION);
+
+ /* disable all interrupts */
+ afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
+ afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
+ afi_writel(pcie, 0, AFI_INTR_MASK);
+ afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
+
+ return 0;
+}
+
+static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
+{
+ unsigned long fpci, axi, size;
+
+ /* BAR 0: type 1 extended configuration space */
+ fpci = 0xfe100000;
+ size = fdt_resource_size(&pcie->cs);
+ axi = pcie->cs.start;
+
+ afi_writel(pcie, axi, AFI_AXI_BAR0_START);
+ afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
+ afi_writel(pcie, fpci, AFI_FPCI_BAR0);
+
+ /* BAR 1: downstream I/O */
+ fpci = 0xfdfc0000;
+ size = fdt_resource_size(&pcie->io);
+ axi = pcie->io.start;
+
+ afi_writel(pcie, axi, AFI_AXI_BAR1_START);
+ afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
+ afi_writel(pcie, fpci, AFI_FPCI_BAR1);
+
+ /* BAR 2: prefetchable memory */
+ fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
+ size = fdt_resource_size(&pcie->prefetch);
+ axi = pcie->prefetch.start;
+
+ afi_writel(pcie, axi, AFI_AXI_BAR2_START);
+ afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
+ afi_writel(pcie, fpci, AFI_FPCI_BAR2);
+
+ /* BAR 3: non-prefetchable memory */
+ fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
+ size = fdt_resource_size(&pcie->mem);
+ axi = pcie->mem.start;
+
+ afi_writel(pcie, axi, AFI_AXI_BAR3_START);
+ afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
+ afi_writel(pcie, fpci, AFI_FPCI_BAR3);
+
+ /* NULL out the remaining BARs as they are not used */
+ afi_writel(pcie, 0, AFI_AXI_BAR4_START);
+ afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
+ afi_writel(pcie, 0, AFI_FPCI_BAR4);
+
+ afi_writel(pcie, 0, AFI_AXI_BAR5_START);
+ afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
+ afi_writel(pcie, 0, AFI_FPCI_BAR5);
+
+ /* map all upstream transactions as uncached */
+ afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
+ afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
+ afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
+ afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
+
+ /* MSI translations are setup only when needed */
+ afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
+ afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
+ afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
+ afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
+}
+
+static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
+{
+ unsigned long ret = 0;
+
+ switch (port->index) {
+ case 0:
+ ret = AFI_PEX0_CTRL;
+ break;
+
+ case 1:
+ ret = AFI_PEX1_CTRL;
+ break;
+
+ case 2:
+ ret = AFI_PEX2_CTRL;
+ break;
+ }
+
+ return ret;
+}
+
+static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
+{
+ unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
+ unsigned long value;
+
+ /* pulse reset signel */
+ value = afi_readl(port->pcie, ctrl);
+ value &= ~AFI_PEX_CTRL_RST;
+ afi_writel(port->pcie, value, ctrl);
+
+ udelay(2000);
+
+ value = afi_readl(port->pcie, ctrl);
+ value |= AFI_PEX_CTRL_RST;
+ afi_writel(port->pcie, value, ctrl);
+}
+
+static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
+{
+ unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
+ unsigned long value;
+
+ /* enable reference clock */
+ value = afi_readl(port->pcie, ctrl);
+ value |= AFI_PEX_CTRL_REFCLK_EN;
+
+ if (port->pcie->soc->has_pex_clkreq_en)
+ value |= AFI_PEX_CTRL_CLKREQ_EN;
+
+ value |= AFI_PEX_CTRL_OVERRIDE_EN;
+
+ afi_writel(port->pcie, value, ctrl);
+
+ tegra_pcie_port_reset(port);
+}
+
+static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
+{
+ unsigned int retries = 3;
+ unsigned long value;
+
+ value = rp_readl(port, RP_PRIV_MISC);
+ value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
+ value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
+ rp_writel(port, value, RP_PRIV_MISC);
+
+ do {
+ unsigned int timeout = 200;
+
+ do {
+ value = rp_readl(port, RP_VEND_XP);
+ if (value & RP_VEND_XP_DL_UP)
+ break;
+
+ udelay(2000);
+ } while (--timeout);
+
+ if (!timeout) {
+ debug("link %u down, retrying\n", port->index);
+ goto retry;
+ }
+
+ timeout = 200;
+
+ do {
+ value = rp_readl(port, RP_LINK_CONTROL_STATUS);
+ if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
+ return true;
+
+ udelay(2000);
+ } while (--timeout);
+
+retry:
+ tegra_pcie_port_reset(port);
+ } while (--retries);
+
+ return false;
+}
+
+static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
+{
+ unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
+ unsigned long value;
+
+ /* assert port reset */
+ value = afi_readl(port->pcie, ctrl);
+ value &= ~AFI_PEX_CTRL_RST;
+ afi_writel(port->pcie, value, ctrl);
+
+ /* disable reference clock */
+ value = afi_readl(port->pcie, ctrl);
+ value &= ~AFI_PEX_CTRL_REFCLK_EN;
+ afi_writel(port->pcie, value, ctrl);
+}
+
+static void tegra_pcie_port_free(struct tegra_pcie_port *port)
+{
+ list_del(&port->list);
+ free(port);
+}
+
+static int tegra_pcie_enable(struct tegra_pcie *pcie)
+{
+ struct tegra_pcie_port *port, *tmp;
+
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+ debug("probing port %u, using %u lanes\n", port->index,
+ port->num_lanes);
+
+ tegra_pcie_port_enable(port);
+
+ if (tegra_pcie_port_check_link(port))
+ continue;
+
+ debug("link %u down, ignoring\n", port->index);
+
+ tegra_pcie_port_disable(port);
+ tegra_pcie_port_free(port);
+ }
+
+ return 0;
+}
+
+static const struct tegra_pcie_soc tegra20_pcie_soc = {
+ .num_ports = 2,
+ .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
+ .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
+ .has_pex_clkreq_en = false,
+ .has_pex_bias_ctrl = false,
+ .has_cml_clk = false,
+ .has_gen2 = false,
+};
+
+static const struct tegra_pcie_soc tegra30_pcie_soc = {
+ .num_ports = 3,
+ .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
+ .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+ .has_pex_clkreq_en = true,
+ .has_pex_bias_ctrl = true,
+ .has_cml_clk = true,
+ .has_gen2 = false,
+};
+
+static const struct tegra_pcie_soc tegra124_pcie_soc = {
+ .num_ports = 2,
+ .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
+ .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+ .has_pex_clkreq_en = true,
+ .has_pex_bias_ctrl = true,
+ .has_cml_clk = true,
+ .has_gen2 = true,
+};
+
+static int process_nodes(const void *fdt, int nodes[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++) {
+ const struct tegra_pcie_soc *soc;
+ struct tegra_pcie *pcie;
+ enum fdt_compat_id id;
+ int err;
+
+ if (!fdtdec_get_is_enabled(fdt, nodes[i]))
+ continue;
+
+ id = fdtdec_lookup(fdt, nodes[i]);
+ switch (id) {
+ case COMPAT_NVIDIA_TEGRA20_PCIE:
+ soc = &tegra20_pcie_soc;
+ break;
+
+ case COMPAT_NVIDIA_TEGRA30_PCIE:
+ soc = &tegra30_pcie_soc;
+ break;
+
+ case COMPAT_NVIDIA_TEGRA124_PCIE:
+ soc = &tegra124_pcie_soc;
+ break;
+
+ default:
+ error("unsupported compatible: %s",
+ fdtdec_get_compatible(id));
+ continue;
+ }
+
+ pcie = malloc(sizeof(*pcie));
+ if (!pcie) {
+ error("failed to allocate controller");
+ continue;
+ }
+
+ memset(pcie, 0, sizeof(*pcie));
+ pcie->soc = soc;
+
+ INIT_LIST_HEAD(&pcie->ports);
+
+ err = tegra_pcie_parse_dt(fdt, nodes[i], pcie);
+ if (err < 0) {
+ free(pcie);
+ continue;
+ }
+
+ err = tegra_pcie_power_on(pcie);
+ if (err < 0) {
+ error("failed to power on");
+ continue;
+ }
+
+ err = tegra_pcie_enable_controller(pcie);
+ if (err < 0) {
+ error("failed to enable controller");
+ continue;
+ }
+
+ tegra_pcie_setup_translations(pcie);
+
+ err = tegra_pcie_enable(pcie);
+ if (err < 0) {
+ error("failed to enable PCIe");
+ continue;
+ }
+
+ pcie->hose.first_busno = 0;
+ pcie->hose.current_busno = 0;
+ pcie->hose.last_busno = 0;
+
+ pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE,
+ NV_PA_SDRAM_BASE, gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ pci_set_region(&pcie->hose.regions[1], pcie->io.start,
+ pcie->io.start, fdt_resource_size(&pcie->io),
+ PCI_REGION_IO);
+
+ pci_set_region(&pcie->hose.regions[2], pcie->mem.start,
+ pcie->mem.start, fdt_resource_size(&pcie->mem),
+ PCI_REGION_MEM);
+
+ pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start,
+ pcie->prefetch.start,
+ fdt_resource_size(&pcie->prefetch),
+ PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+ pcie->hose.region_count = 4;
+
+ pci_set_ops(&pcie->hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ tegra_pcie_read_conf,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ tegra_pcie_write_conf);
+
+ pci_register_hose(&pcie->hose);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Enumerating devices...\n");
+ printf("---------------------------------------\n");
+ printf(" Device ID Description\n");
+ printf(" ------ -- -----------\n");
+#endif
+
+ pcie->hose.last_busno = pci_hose_scan(&pcie->hose);
+ }
+
+ return 0;
+}
+
+void pci_init_board(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int count, nodes[1];
+
+ count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
+ COMPAT_NVIDIA_TEGRA124_PCIE,
+ nodes, ARRAY_SIZE(nodes));
+ if (process_nodes(fdt, nodes, count))
+ return;
+
+ count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
+ COMPAT_NVIDIA_TEGRA30_PCIE,
+ nodes, ARRAY_SIZE(nodes));
+ if (process_nodes(fdt, nodes, count))
+ return;
+
+ count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
+ COMPAT_NVIDIA_TEGRA20_PCIE,
+ nodes, ARRAY_SIZE(nodes));
+ if (process_nodes(fdt, nodes, count))
+ return;
+}
+
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+ if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0)
+ return 1;
+
+ return 0;
+}
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_AS3722_POWER) += as3722.o
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP221_POWER) += axp221.o
--- /dev/null
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define pr_fmt(fmt) "as3722: " fmt
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <i2c.h>
+
+#include <power/as3722.h>
+
+#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
+#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
+#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
+#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
+#define AS3722_GPIO_SIGNAL_OUT 0x20
+#define AS3722_SD_CONTROL 0x4d
+#define AS3722_LDO_CONTROL 0x4e
+#define AS3722_ASIC_ID1 0x90
+#define AS3722_DEVICE_ID 0x0c
+#define AS3722_ASIC_ID2 0x91
+
+static int as3722_read(struct udevice *pmic, u8 reg, u8 *value)
+{
+ int err;
+
+ err = i2c_read(pmic, reg, value, 1);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+static int as3722_write(struct udevice *pmic, u8 reg, u8 value)
+{
+ int err;
+
+ err = i2c_write(pmic, reg, &value, 1);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+static int as3722_read_id(struct udevice *pmic, u8 *id, u8 *revision)
+{
+ int err;
+
+ err = as3722_read(pmic, AS3722_ASIC_ID1, id);
+ if (err) {
+ error("failed to read ID1 register: %d", err);
+ return err;
+ }
+
+ err = as3722_read(pmic, AS3722_ASIC_ID2, revision);
+ if (err) {
+ error("failed to read ID2 register: %d", err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
+{
+ u8 value;
+ int err;
+
+ if (sd > 6)
+ return -EINVAL;
+
+ err = as3722_read(pmic, AS3722_SD_CONTROL, &value);
+ if (err) {
+ error("failed to read SD control register: %d", err);
+ return err;
+ }
+
+ value |= 1 << sd;
+
+ err = as3722_write(pmic, AS3722_SD_CONTROL, value);
+ if (err < 0) {
+ error("failed to write SD control register: %d", err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value)
+{
+ int err;
+
+ if (sd > 6)
+ return -EINVAL;
+
+ err = as3722_write(pmic, AS3722_SD_VOLTAGE(sd), value);
+ if (err < 0) {
+ error("failed to write SD%u voltage register: %d", sd, err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
+{
+ u8 value;
+ int err;
+
+ if (ldo > 11)
+ return -EINVAL;
+
+ err = as3722_read(pmic, AS3722_LDO_CONTROL, &value);
+ if (err) {
+ error("failed to read LDO control register: %d", err);
+ return err;
+ }
+
+ value |= 1 << ldo;
+
+ err = as3722_write(pmic, AS3722_LDO_CONTROL, value);
+ if (err < 0) {
+ error("failed to write LDO control register: %d", err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value)
+{
+ int err;
+
+ if (ldo > 11)
+ return -EINVAL;
+
+ err = as3722_write(pmic, AS3722_LDO_VOLTAGE(ldo), value);
+ if (err < 0) {
+ error("failed to write LDO%u voltage register: %d", ldo,
+ err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
+ unsigned long flags)
+{
+ u8 value = 0;
+ int err;
+
+ if (flags & AS3722_GPIO_OUTPUT_VDDH)
+ value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ if (flags & AS3722_GPIO_INVERT)
+ value |= AS3722_GPIO_CONTROL_INVERT;
+
+ err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int as3722_gpio_set(struct udevice *pmic, unsigned int gpio,
+ unsigned int level)
+{
+ const char *l;
+ u8 value;
+ int err;
+
+ if (gpio > 7)
+ return -EINVAL;
+
+ err = as3722_read(pmic, AS3722_GPIO_SIGNAL_OUT, &value);
+ if (err < 0) {
+ error("failed to read GPIO signal out register: %d", err);
+ return err;
+ }
+
+ if (level == 0) {
+ value &= ~(1 << gpio);
+ l = "low";
+ } else {
+ value |= 1 << gpio;
+ l = "high";
+ }
+
+ err = as3722_write(pmic, AS3722_GPIO_SIGNAL_OUT, value);
+ if (err) {
+ error("failed to set GPIO#%u %s: %d", gpio, l, err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
+ unsigned int level)
+{
+ u8 value;
+ int err;
+
+ if (gpio > 7)
+ return -EINVAL;
+
+ if (level == 0)
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
+ else
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u as output: %d", gpio, err);
+ return err;
+ }
+
+ err = as3722_gpio_set(pmic, gpio, level);
+ if (err < 0) {
+ error("failed to set GPIO#%u high: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_init(struct udevice **devp)
+{
+ struct udevice *pmic;
+ u8 id, revision;
+ const unsigned int bus = 0;
+ const unsigned int address = 0x40;
+ int err;
+
+ err = i2c_get_chip_for_busnum(bus, address, &pmic);
+ if (err)
+ return err;
+ err = as3722_read_id(pmic, &id, &revision);
+ if (err < 0) {
+ error("failed to read ID: %d", err);
+ return err;
+ }
+
+ if (id != AS3722_DEVICE_ID) {
+ error("unknown device");
+ return -ENOENT;
+ }
+
+ debug("AS3722 revision %#x found on I2C bus %u, address %#x\n",
+ revision, bus, address);
+ *devp = pmic;
+
+ return 0;
+}
obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
-obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
+obj-$(CONFIG_X86_SERIAL) += serial_x86.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
#include <ns16550.h>
#include <serial.h>
-static const struct udevice_id coreboot_serial_ids[] = {
- { .compatible = "coreboot-uart" },
+static const struct udevice_id x86_serial_ids[] = {
+ { .compatible = "x86-uart" },
{ }
};
-static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
+static int x86_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev_get_platdata(dev);
int ret;
return 0;
}
U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_coreboot",
+ .name = "serial_x86",
.id = UCLASS_SERIAL,
- .of_match = coreboot_serial_ids,
- .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
+ .of_match = x86_serial_ids,
+ .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
.priv_auto_alloc_size = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
# new USB host ethernet layer dependencies
obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
+obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o
obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
--- /dev/null
+/*
+ * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
+ * based on the U-Boot Asix driver as well as information
+ * from the Linux AX88179_178a driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <net.h>
+#include <linux/mii.h>
+#include "usb_ether.h"
+#include <malloc.h>
+#include <errno.h>
+
+/* ASIX AX88179 based USB 3.0 Ethernet Devices */
+#define AX88179_PHY_ID 0x03
+#define AX_EEPROM_LEN 0x100
+#define AX88179_EEPROM_MAGIC 0x17900b95
+#define AX_MCAST_FLTSIZE 8
+#define AX_MAX_MCAST 64
+#define AX_INT_PPLS_LINK (1 << 16)
+#define AX_RXHDR_L4_TYPE_MASK 0x1c
+#define AX_RXHDR_L4_TYPE_UDP 4
+#define AX_RXHDR_L4_TYPE_TCP 16
+#define AX_RXHDR_L3CSUM_ERR 2
+#define AX_RXHDR_L4CSUM_ERR 1
+#define AX_RXHDR_CRC_ERR (1 << 29)
+#define AX_RXHDR_DROP_ERR (1 << 31)
+#define AX_ENDPOINT_INT 0x01
+#define AX_ENDPOINT_IN 0x02
+#define AX_ENDPOINT_OUT 0x03
+#define AX_ACCESS_MAC 0x01
+#define AX_ACCESS_PHY 0x02
+#define AX_ACCESS_EEPROM 0x04
+#define AX_ACCESS_EFUS 0x05
+#define AX_PAUSE_WATERLVL_HIGH 0x54
+#define AX_PAUSE_WATERLVL_LOW 0x55
+
+#define PHYSICAL_LINK_STATUS 0x02
+ #define AX_USB_SS (1 << 2)
+ #define AX_USB_HS (1 << 1)
+
+#define GENERAL_STATUS 0x03
+ #define AX_SECLD (1 << 2)
+
+#define AX_SROM_ADDR 0x07
+#define AX_SROM_CMD 0x0a
+ #define EEP_RD (1 << 2)
+ #define EEP_BUSY (1 << 4)
+
+#define AX_SROM_DATA_LOW 0x08
+#define AX_SROM_DATA_HIGH 0x09
+
+#define AX_RX_CTL 0x0b
+ #define AX_RX_CTL_DROPCRCERR (1 << 8)
+ #define AX_RX_CTL_IPE (1 << 9)
+ #define AX_RX_CTL_START (1 << 7)
+ #define AX_RX_CTL_AP (1 << 5)
+ #define AX_RX_CTL_AM (1 << 4)
+ #define AX_RX_CTL_AB (1 << 3)
+ #define AX_RX_CTL_AMALL (1 << 1)
+ #define AX_RX_CTL_PRO (1 << 0)
+ #define AX_RX_CTL_STOP 0
+
+#define AX_NODE_ID 0x10
+#define AX_MULFLTARY 0x16
+
+#define AX_MEDIUM_STATUS_MODE 0x22
+ #define AX_MEDIUM_GIGAMODE (1 << 0)
+ #define AX_MEDIUM_FULL_DUPLEX (1 << 1)
+ #define AX_MEDIUM_EN_125MHZ (1 << 3)
+ #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4)
+ #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5)
+ #define AX_MEDIUM_RECEIVE_EN (1 << 8)
+ #define AX_MEDIUM_PS (1 << 9)
+ #define AX_MEDIUM_JUMBO_EN 0x8040
+
+#define AX_MONITOR_MOD 0x24
+ #define AX_MONITOR_MODE_RWLC (1 << 1)
+ #define AX_MONITOR_MODE_RWMP (1 << 2)
+ #define AX_MONITOR_MODE_PMEPOL (1 << 5)
+ #define AX_MONITOR_MODE_PMETYPE (1 << 6)
+
+#define AX_GPIO_CTRL 0x25
+ #define AX_GPIO_CTRL_GPIO3EN (1 << 7)
+ #define AX_GPIO_CTRL_GPIO2EN (1 << 6)
+ #define AX_GPIO_CTRL_GPIO1EN (1 << 5)
+
+#define AX_PHYPWR_RSTCTL 0x26
+ #define AX_PHYPWR_RSTCTL_BZ (1 << 4)
+ #define AX_PHYPWR_RSTCTL_IPRL (1 << 5)
+ #define AX_PHYPWR_RSTCTL_AT (1 << 12)
+
+#define AX_RX_BULKIN_QCTRL 0x2e
+#define AX_CLK_SELECT 0x33
+ #define AX_CLK_SELECT_BCS (1 << 0)
+ #define AX_CLK_SELECT_ACS (1 << 1)
+ #define AX_CLK_SELECT_ULR (1 << 3)
+
+#define AX_RXCOE_CTL 0x34
+ #define AX_RXCOE_IP (1 << 0)
+ #define AX_RXCOE_TCP (1 << 1)
+ #define AX_RXCOE_UDP (1 << 2)
+ #define AX_RXCOE_TCPV6 (1 << 5)
+ #define AX_RXCOE_UDPV6 (1 << 6)
+
+#define AX_TXCOE_CTL 0x35
+ #define AX_TXCOE_IP (1 << 0)
+ #define AX_TXCOE_TCP (1 << 1)
+ #define AX_TXCOE_UDP (1 << 2)
+ #define AX_TXCOE_TCPV6 (1 << 5)
+ #define AX_TXCOE_UDPV6 (1 << 6)
+
+#define AX_LEDCTRL 0x73
+
+#define GMII_PHY_PHYSR 0x11
+ #define GMII_PHY_PHYSR_SMASK 0xc000
+ #define GMII_PHY_PHYSR_GIGA (1 << 15)
+ #define GMII_PHY_PHYSR_100 (1 << 14)
+ #define GMII_PHY_PHYSR_FULL (1 << 13)
+ #define GMII_PHY_PHYSR_LINK (1 << 10)
+
+#define GMII_LED_ACT 0x1a
+ #define GMII_LED_ACTIVE_MASK 0xff8f
+ #define GMII_LED0_ACTIVE (1 << 4)
+ #define GMII_LED1_ACTIVE (1 << 5)
+ #define GMII_LED2_ACTIVE (1 << 6)
+
+#define GMII_LED_LINK 0x1c
+ #define GMII_LED_LINK_MASK 0xf888
+ #define GMII_LED0_LINK_10 (1 << 0)
+ #define GMII_LED0_LINK_100 (1 << 1)
+ #define GMII_LED0_LINK_1000 (1 << 2)
+ #define GMII_LED1_LINK_10 (1 << 4)
+ #define GMII_LED1_LINK_100 (1 << 5)
+ #define GMII_LED1_LINK_1000 (1 << 6)
+ #define GMII_LED2_LINK_10 (1 << 8)
+ #define GMII_LED2_LINK_100 (1 << 9)
+ #define GMII_LED2_LINK_1000 (1 << 10)
+ #define LED0_ACTIVE (1 << 0)
+ #define LED0_LINK_10 (1 << 1)
+ #define LED0_LINK_100 (1 << 2)
+ #define LED0_LINK_1000 (1 << 3)
+ #define LED0_FD (1 << 4)
+ #define LED0_USB3_MASK 0x001f
+ #define LED1_ACTIVE (1 << 5)
+ #define LED1_LINK_10 (1 << 6)
+ #define LED1_LINK_100 (1 << 7)
+ #define LED1_LINK_1000 (1 << 8)
+ #define LED1_FD (1 << 9)
+ #define LED1_USB3_MASK 0x03e0
+ #define LED2_ACTIVE (1 << 10)
+ #define LED2_LINK_1000 (1 << 13)
+ #define LED2_LINK_100 (1 << 12)
+ #define LED2_LINK_10 (1 << 11)
+ #define LED2_FD (1 << 14)
+ #define LED_VALID (1 << 15)
+ #define LED2_USB3_MASK 0x7c00
+
+#define GMII_PHYPAGE 0x1e
+#define GMII_PHY_PAGE_SELECT 0x1f
+ #define GMII_PHY_PGSEL_EXT 0x0007
+ #define GMII_PHY_PGSEL_PAGE0 0x0000
+
+/* local defines */
+#define ASIX_BASE_NAME "axg"
+#define USB_CTRL_SET_TIMEOUT 5000
+#define USB_CTRL_GET_TIMEOUT 5000
+#define USB_BULK_SEND_TIMEOUT 5000
+#define USB_BULK_RECV_TIMEOUT 5000
+
+#define AX_RX_URB_SIZE 1024 * 0x12
+#define BLK_FRAME_SIZE 0x200
+#define PHY_CONNECT_TIMEOUT 5000
+
+#define TIMEOUT_RESOLUTION 50 /* ms */
+
+#define FLAG_NONE 0
+#define FLAG_TYPE_AX88179 (1U << 0)
+#define FLAG_TYPE_AX88178a (1U << 1)
+#define FLAG_TYPE_DLINK_DUB1312 (1U << 2)
+#define FLAG_TYPE_SITECOM (1U << 3)
+#define FLAG_TYPE_SAMSUNG (1U << 4)
+#define FLAG_TYPE_LENOVO (1U << 5)
+
+/* local vars */
+static const struct {
+ unsigned char ctrl, timer_l, timer_h, size, ifg;
+} AX88179_BULKIN_SIZE[] = {
+ {7, 0x4f, 0, 0x02, 0xff},
+ {7, 0x20, 3, 0x03, 0xff},
+ {7, 0xae, 7, 0x04, 0xff},
+ {7, 0xcc, 0x4c, 0x04, 8},
+};
+
+static int curr_eth_dev; /* index for name of next device detected */
+
+/* driver private */
+struct asix_private {
+ int flags;
+ int rx_urb_size;
+ int maxpacketsize;
+};
+
+/*
+ * Asix infrastructure commands
+ */
+static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
+ u16 size, void *data)
+{
+ int len;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
+
+ debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
+ cmd, value, index, size);
+
+ memcpy(buf, data, size);
+
+ len = usb_control_msg(
+ dev->pusb_dev,
+ usb_sndctrlpipe(dev->pusb_dev, 0),
+ cmd,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ value,
+ index,
+ buf,
+ size,
+ USB_CTRL_SET_TIMEOUT);
+
+ return len == size ? 0 : ECOMM;
+}
+
+static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
+ u16 size, void *data)
+{
+ int len;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
+
+ debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
+ cmd, value, index, size);
+
+ len = usb_control_msg(
+ dev->pusb_dev,
+ usb_rcvctrlpipe(dev->pusb_dev, 0),
+ cmd,
+ USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ value,
+ index,
+ buf,
+ size,
+ USB_CTRL_GET_TIMEOUT);
+
+ memcpy(data, buf, size);
+
+ return len == size ? 0 : ECOMM;
+}
+
+static int asix_read_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ u8 buf[ETH_ALEN];
+
+ asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf);
+ debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n",
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+
+ memcpy(eth->enetaddr, buf, ETH_ALEN);
+
+ return 0;
+}
+
+static int asix_basic_reset(struct ueth_data *dev)
+{
+ struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
+ u8 buf[5];
+ u16 *tmp16;
+ u8 *tmp;
+
+ tmp16 = (u16 *)buf;
+ tmp = (u8 *)buf;
+
+ /* Power up ethernet PHY */
+ *tmp16 = 0;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
+
+ *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
+ mdelay(200);
+
+ *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
+ mdelay(200);
+
+ /* RX bulk configuration */
+ memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
+
+ dev_priv->rx_urb_size = 128 * 20;
+
+ /* Water Level configuration */
+ *tmp = 0x34;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
+
+ *tmp = 0x52;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
+
+ /* Enable checksum offload */
+ *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
+ AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
+
+ *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
+ AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
+
+ /* Configure RX control register => start operation */
+ *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
+ AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
+
+ *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
+ AX_MONITOR_MODE_RWMP;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
+
+ /* Configure default medium type => giga */
+ *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
+ AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
+ AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
+
+ u16 adv = 0;
+ adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
+ ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
+ asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
+
+ adv = ADVERTISE_1000FULL;
+ asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
+
+ return 0;
+}
+
+static int asix_wait_link(struct ueth_data *dev)
+{
+ int timeout = 0;
+ int link_detected;
+ u8 buf[2];
+ u16 *tmp16;
+
+ tmp16 = (u16 *)buf;
+
+ do {
+ asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
+ MII_BMSR, 2, buf);
+ link_detected = *tmp16 & BMSR_LSTATUS;
+ if (!link_detected) {
+ if (timeout == 0)
+ printf("Waiting for Ethernet connection... ");
+ mdelay(TIMEOUT_RESOLUTION);
+ timeout += TIMEOUT_RESOLUTION;
+ }
+ } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
+
+ if (link_detected) {
+ if (timeout > 0)
+ printf("done.\n");
+ return 0;
+ } else {
+ printf("unable to connect.\n");
+ return -ENETUNREACH;
+ }
+}
+
+/*
+ * Asix callbacks
+ */
+static int asix_init(struct eth_device *eth, bd_t *bd)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
+ u8 buf[2], tmp[5], link_sts;
+ u16 *tmp16, mode;
+
+
+ tmp16 = (u16 *)buf;
+
+ debug("** %s()\n", __func__);
+
+ /* Configure RX control register => start operation */
+ *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
+ AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
+ if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
+ goto out_err;
+
+ if (asix_wait_link(dev) != 0) {
+ /*reset device and try again*/
+ printf("Reset Ethernet Device\n");
+ asix_basic_reset(dev);
+ if (asix_wait_link(dev) != 0)
+ goto out_err;
+ }
+
+ /* Configure link */
+ mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
+ AX_MEDIUM_RXFLOW_CTRLEN;
+
+ asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
+ 1, 1, &link_sts);
+
+ asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
+ GMII_PHY_PHYSR, 2, tmp16);
+
+ if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
+ return 0;
+ } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
+ mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
+ AX_MEDIUM_JUMBO_EN;
+
+ if (link_sts & AX_USB_SS)
+ memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
+ else if (link_sts & AX_USB_HS)
+ memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
+ else
+ memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
+ } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
+ mode |= AX_MEDIUM_PS;
+
+ if (link_sts & (AX_USB_SS | AX_USB_HS))
+ memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
+ else
+ memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
+ } else {
+ memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
+ }
+
+ /* RX bulk configuration */
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
+
+ dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
+ if (*tmp16 & GMII_PHY_PHYSR_FULL)
+ mode |= AX_MEDIUM_FULL_DUPLEX;
+ asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
+ 2, 2, &mode);
+
+ return 0;
+out_err:
+ return -1;
+}
+
+static int asix_send(struct eth_device *eth, void *packet, int length)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
+
+ int err;
+ u32 packet_len, tx_hdr2;
+ int actual_len, framesize;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
+ PKTSIZE + (2 * sizeof(packet_len)));
+
+ debug("** %s(), len %d\n", __func__, length);
+
+ packet_len = length;
+ cpu_to_le32s(&packet_len);
+
+ memcpy(msg, &packet_len, sizeof(packet_len));
+ framesize = dev_priv->maxpacketsize;
+ tx_hdr2 = 0;
+ if (((length + 8) % framesize) == 0)
+ tx_hdr2 |= 0x80008000; /* Enable padding */
+
+ cpu_to_le32s(&tx_hdr2);
+
+ memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
+
+ memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
+ (void *)packet, length);
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ (void *)msg,
+ length + sizeof(packet_len) + sizeof(tx_hdr2),
+ &actual_len,
+ USB_BULK_SEND_TIMEOUT);
+ debug("Tx: len = %u, actual = %u, err = %d\n",
+ length + sizeof(packet_len), actual_len, err);
+
+ return err;
+}
+
+static int asix_recv(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
+
+ u16 frame_pos;
+ int err;
+ int actual_len;
+
+ int pkt_cnt;
+ u32 rx_hdr;
+ u16 hdr_off;
+ u32 *pkt_hdr;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
+
+ actual_len = -1;
+
+ debug("** %s()\n", __func__);
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ (void *)recv_buf,
+ dev_priv->rx_urb_size,
+ &actual_len,
+ USB_BULK_RECV_TIMEOUT);
+ debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
+ actual_len, err);
+
+ if (err != 0) {
+ debug("Rx: failed to receive\n");
+ return -ECOMM;
+ }
+ if (actual_len > dev_priv->rx_urb_size) {
+ debug("Rx: received too many bytes %d\n", actual_len);
+ return -EMSGSIZE;
+ }
+
+
+ rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
+ le32_to_cpus(&pkt_hdr);
+
+ pkt_cnt = (u16)rx_hdr;
+ hdr_off = (u16)(rx_hdr >> 16);
+ pkt_hdr = (u32 *)(recv_buf + hdr_off);
+
+
+ frame_pos = 0;
+
+ while (pkt_cnt--) {
+ u16 pkt_len;
+
+ le32_to_cpus(pkt_hdr);
+ pkt_len = (*pkt_hdr >> 16) & 0x1fff;
+
+ frame_pos += 2;
+
+ NetReceive(recv_buf + frame_pos, pkt_len);
+
+ pkt_hdr++;
+ frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
+
+ if (pkt_cnt == 0)
+ return 0;
+ }
+ return err;
+}
+
+static void asix_halt(struct eth_device *eth)
+{
+ debug("** %s()\n", __func__);
+}
+
+/*
+ * Asix probing functions
+ */
+void ax88179_eth_before_probe(void)
+{
+ curr_eth_dev = 0;
+}
+
+struct asix_dongle {
+ unsigned short vendor;
+ unsigned short product;
+ int flags;
+};
+
+static const struct asix_dongle asix_dongles[] = {
+ { 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
+ { 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
+ { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
+ { 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
+ { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
+ { 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
+ { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
+};
+
+/* Probe to see if a new device is actually an asix device */
+int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss)
+{
+ struct usb_interface *iface;
+ struct usb_interface_descriptor *iface_desc;
+ struct asix_private *dev_priv;
+ int ep_in_found = 0, ep_out_found = 0;
+ int i;
+
+ /* let's examine the device now */
+ iface = &dev->config.if_desc[ifnum];
+ iface_desc = &dev->config.if_desc[ifnum].desc;
+
+ for (i = 0; asix_dongles[i].vendor != 0; i++) {
+ if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
+ dev->descriptor.idProduct == asix_dongles[i].product)
+ /* Found a supported dongle */
+ break;
+ }
+
+ if (asix_dongles[i].vendor == 0)
+ return 0;
+
+ memset(ss, 0, sizeof(struct ueth_data));
+
+ /* At this point, we know we've got a live one */
+ debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+
+ /* Initialize the ueth_data structure with some useful info */
+ ss->ifnum = ifnum;
+ ss->pusb_dev = dev;
+ ss->subclass = iface_desc->bInterfaceSubClass;
+ ss->protocol = iface_desc->bInterfaceProtocol;
+
+ /* alloc driver private */
+ ss->dev_priv = calloc(1, sizeof(struct asix_private));
+ if (!ss->dev_priv)
+ return 0;
+ dev_priv = ss->dev_priv;
+ dev_priv->flags = asix_dongles[i].flags;
+
+ /*
+ * We are expecting a minimum of 3 endpoints - in, out (bulk), and
+ * int. We will ignore any others.
+ */
+ for (i = 0; i < iface_desc->bNumEndpoints; i++) {
+ /* is it an interrupt endpoint? */
+ if ((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
+ ss->ep_int = iface->ep_desc[i].bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK;
+ ss->irqinterval = iface->ep_desc[i].bInterval;
+ continue;
+ }
+
+ /* is it an BULK endpoint? */
+ if (!((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
+ continue;
+
+ u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
+ if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
+ ss->ep_in = ep_addr &
+ USB_ENDPOINT_NUMBER_MASK;
+ ep_in_found = 1;
+ }
+ if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
+ ss->ep_out = ep_addr &
+ USB_ENDPOINT_NUMBER_MASK;
+ dev_priv->maxpacketsize =
+ dev->epmaxpacketout[AX_ENDPOINT_OUT];
+ ep_out_found = 1;
+ }
+ }
+ debug("Endpoints In %d Out %d Int %d\n",
+ ss->ep_in, ss->ep_out, ss->ep_int);
+
+ /* Do some basic sanity checks, and bail if we find a problem */
+ if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
+ !ss->ep_in || !ss->ep_out || !ss->ep_int) {
+ debug("Problems with device\n");
+ return 0;
+ }
+ dev->privptr = (void *)ss;
+ return 1;
+}
+
+int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth)
+{
+ if (!eth) {
+ debug("%s: missing parameter.\n", __func__);
+ return 0;
+ }
+ sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
+ eth->init = asix_init;
+ eth->send = asix_send;
+ eth->recv = asix_recv;
+ eth->halt = asix_halt;
+ eth->priv = ss;
+
+ if (asix_basic_reset(ss))
+ return 0;
+
+ /* Get the MAC address */
+ if (asix_read_mac(eth))
+ return 0;
+ debug("MAC %pM\n", eth->enetaddr);
+
+ return 1;
+}
.get_info = asix_eth_get_info,
},
#endif
+#ifdef CONFIG_USB_ETHER_ASIX88179
+ {
+ .before_probe = ax88179_eth_before_probe,
+ .probe = ax88179_eth_probe,
+ .get_info = ax88179_eth_get_info,
+ },
+#endif
#ifdef CONFIG_USB_ETHER_MCS7830
{
.before_probe = mcs7830_eth_before_probe,
if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
receive_data(ep);
- usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
}
}
to_runtime_mode(f_dfu);
f_dfu->dfu_state = DFU_STATE_appIDLE;
- dfu_trigger_detach();
+ g_dnl_trigger_detach();
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
fastboot_tx_write_str("OKAY");
}
+static void do_exit_on_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ g_dnl_trigger_detach();
+}
+
+static void cb_continue(struct usb_ep *ep, struct usb_request *req)
+{
+ fastboot_func->in_req->complete = do_exit_on_complete;
+ fastboot_tx_write_str("OKAY");
+}
+
#ifdef CONFIG_FASTBOOT_FLASH
static void cb_flash(struct usb_ep *ep, struct usb_request *req)
{
}, {
.cmd = "boot",
.cb = cb_boot,
+ }, {
+ .cmd = "continue",
+ .cb = cb_continue,
},
#ifdef CONFIG_FASTBOOT_FLASH
{
static int download_tail(long long int left, int cnt)
{
- struct dfu_entity *dfu_entity = dfu_get_entity(alt_setting_num);
- void *transfer_buffer = dfu_get_buf(dfu_entity);
+ struct dfu_entity *dfu_entity;
+ void *transfer_buffer;
int ret;
debug("%s: left: %llu cnt: %d\n", __func__, left, cnt);
+ dfu_entity = dfu_get_entity(alt_setting_num);
+ if (!dfu_entity) {
+ error("Alt setting: %d entity not found!\n", alt_setting_num);
+ return -ENOENT;
+ }
+
+ transfer_buffer = dfu_get_buf(dfu_entity);
+ if (!transfer_buffer) {
+ error("Transfer buffer not allocated!");
+ return -ENXIO;
+ }
+
if (left) {
ret = dfu_write(dfu_entity, transfer_buffer, left, cnt++);
if (ret) {
return -EOPNOTSUPP;
}
+static bool g_dnl_detach_request;
+
+bool g_dnl_detach(void)
+{
+ return g_dnl_detach_request;
+}
+
+void g_dnl_trigger_detach(void)
+{
+ g_dnl_detach_request = true;
+}
+
+void g_dnl_clear_detach(void)
+{
+ g_dnl_detach_request = false;
+}
+
static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev)
{
struct usb_gadget *gadget = cdev->gadget;
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_ASIX88179
/* MMC SPL */
#define CONFIG_EXYNOS_SPL
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+/* PCI host support */
+#define CONFIG_PCI
+#define CONFIG_PCI_TEGRA
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+
+/* PCI networking support */
+#define CONFIG_RTL8169
+
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+/* PCI host support */
+#define CONFIG_PCI
+#define CONFIG_PCI_TEGRA
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+
+/* PCI networking support */
+#define CONFIG_RTL8169
+
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 8
-#define CONFIG_X86_MRC_START 0xfffa0000
+#define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_CACHE_MRC_SIZE_KB 512
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
#define CONFIG_VIDEO_X86
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial,cbmem\0" \
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_SYS_X86_START16 0xfffff800
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_X86_RESET_VECTOR
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_X86_SERIAL
+#define CONFIG_SMSC_LPC47M
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x80000000
+
+#define CONFIG_PCI_PREF_BUS 0xc0000000
+#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE 0x20000000
+
+#define CONFIG_PCI_IO_BUS 0x2000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0xe000
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define CONFIG_SCSI_DEV_LIST \
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
+
+#define CONFIG_SPI_FLASH_SST
+
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
+/* Video is not supported */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+#endif /* __CONFIG_H */
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
+
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
/* Command definition */
#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_SETEXPR
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 1
-
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
-#define EMMC_ENV \
- "emmcdev=2\0" \
- "update_emmc_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "if mmc dev ${emmcdev}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0"
-#else
-#define EMMC_ENV ""
-#endif
-
-#ifdef CONFIG_CMD_SF
-#define SF_ENV \
- "update_spi_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if ${get_cmd} ${update_spi_firmware_filename}; then " \
- "if sf probe; then " \
- "sf erase 0 0xc0000; " \
- "sf write ${loadaddr} 0x400 ${filesize}; " \
- "fi; " \
- "fi\0"
-#else
-#define SF_ENV ""
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_addr=0x18000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- EMMC_ENV \
- SF_ENV \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${image}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
#if defined(CONFIG_ENV_IS_IN_MMC)
/* RiOTboard */
-#define CONFIG_DEFAULT_FDT_FILE "imx6dl-riotboard.dtb"
+#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
/* MarSBoard */
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-marsboard.dtb"
+#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (8 * 1024)
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
-#define CONFIG_OF_LIBFDT
-
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
+#include <config_distro_defaults.h>
+
+/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
+ "kernel_addr_r=0x12000000\0" \
+ "fdt_addr_r=0x13000000\0" \
+ "scriptaddr=0x13100000\0" \
+ "pxefile_addr_r=0x13200000\0" \
+ "ramdisk_addr_r=0x13300000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONSOLE_STDIN_SETTINGS \
+ "stdin=serial\0"
+
+#define CONSOLE_STDOUT_SETTINGS \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define CONSOLE_ENV_SETTINGS \
+ CONSOLE_STDIN_SETTINGS \
+ CONSOLE_STDOUT_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONSOLE_ENV_SETTINGS \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
+ BOOTENV
+
#endif /* __RIOTBOARD_CONFIG_H */
#define CONFIG_CMD_GPIO
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+
/* USB boot mode */
#define CONFIG_USB_BOOTING
#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
-/* USB */
-#define CONFIG_CMD_USB
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-
#define CONFIG_SPL_TEXT_BASE 0x02023400
#define CONFIG_IRAM_STACK 0x02050000
/* A variant of Exynos5420 (Exynos5 Family) */
#define CONFIG_EXYNOS5800
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-#define CONFIG_ENV_SPI_BASE 0x12D30000
-#define FLASH_SIZE (0x4 << 20)
-#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
-#define CONFIG_SPI_BOOTING
-
#include <configs/exynos5-common.h>
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_VAR_SIZE_SPL
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_TEXT_BASE 0x23E00000
#ifdef CONFIG_VAR_SIZE_SPL
#define CONFIG_SPL_TEXT_BASE 0x02024410
#else
#define CONFIG_BOARD_REV_GPIO_COUNT 2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-
-/*
- * Put the initial stack pointer 1KB below this to allow room for the
- * SPL marker. This value is arbitrary, but gd_t is placed starting here.
- */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
-
-/* Miscellaneous configurable options */
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-
#endif /* __CONFIG_EXYNOS5420_H */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
/* Init Functions */
#define CONFIG_BOARD_EARLY_INIT_F
#include <linux/sizes.h>
+/* enable PMIC */
+#define CONFIG_AS3722_POWER
+
#include "tegra124-common.h"
/* High-level configuration options */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+/* PCI host support */
+#define CONFIG_PCI
+#define CONFIG_PCI_TEGRA
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+
+/* PCI networking support */
+#define CONFIG_RTL8169
+
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
#endif /* __CONFIG_H */
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
+#endif
+
#endif /* __MX6QSABRESD_CONFIG_H */
/* System configurations */
#define CONFIG_MX6
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MISC_INIT_R
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
/* SPL */
#define CONFIG_SPL_FAT_SUPPORT
/* Video output */
#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
--- /dev/null
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Hyungwon Hwang <human.hwang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ODROID_XU3_H
+#define __CONFIG_ODROID_XU3_H
+
+#include "exynos5420-common.h"
+
+#define CONFIG_SYS_PROMPT "ODROID-XU3 # "
+#define CONFIG_IDENT_STRING " for ODROID-XU3"
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2 /* use SERIAL 2 */
+
+#define TZPC_BASE_OFFSET 0x10000
+
+#define CONFIG_CMD_MMC
+
+/*
+ * FIXME: The number of bank is actually 8. But there is no way to reserve the
+ * last 16 Mib in the last bank now. So I just excluded the last bank
+ * temporally.
+ */
+#define CONFIG_NR_DRAM_BANKS 7
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+
+/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */
+#undef CONFIG_EXYNOS_TMU
+#undef CONFIG_TMU_CMD_DTT
+
+#endif /* __CONFIG_H */
/* USB Configs */
#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_CMD_EXT4
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_LIB_UUID
+#define CONFIG_CMD_FS_UUID
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTFILE
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
+#define CONFIG_SPI_BOOTING
#include <configs/exynos5420-common.h>
#include <configs/exynos5-dt-common.h>
#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_TEXT_BASE 0x23E00000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
+
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#define CONFIG_SYS_PROMPT "Peach-Pi # "
#define CONFIG_IDENT_STRING " for Peach-Pi"
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
+#define CONFIG_SPI_BOOTING
#include <configs/exynos5420-common.h>
#include <configs/exynos5-dt-common.h>
#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_TEXT_BASE 0x23E00000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
+
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#define CONFIG_SYS_PROMPT "Peach-Pit # "
#define CONFIG_IDENT_STRING " for Peach-Pit"
#ifndef __CONFIG_SMDK5420_H
#define __CONFIG_SMDK5420_H
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE 0x12D30000
+#define FLASH_SIZE (0x4 << 20)
+#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
+#define CONFIG_SPI_BOOTING
+
#include <configs/exynos5420-common.h>
#define CONFIG_BOARD_COMMON
#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_TEXT_BASE 0x23E00000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#define CONFIG_SYS_PROMPT "SMDK5420 # "
#define CONFIG_IDENT_STRING " for SMDK5420"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+/* USB */
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 7
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
#endif
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
-#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
/*
* NS16550 Configuration
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+/* PCI host support */
+#define CONFIG_PCI
+#define CONFIG_PCI_TEGRA
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+
+/* PCI networking support */
+#define CONFIG_RTL8169
+
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_DM
+
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000)
+#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SUPPORT
#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H
+/* We use generic board for v8 Versatile Express */
+#define CONFIG_SYS_GENERIC_BOARD
+
#ifdef CONFIG_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
-/*#define CONFIG_SYS_GENERIC_BOARD*/
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SUPPORT_RAW_INITRD
char *dfu_extract_token(char** e, int *n);
void dfu_trigger_reset(void);
int dfu_get_alt(char *name);
-bool dfu_detach(void);
-void dfu_trigger_detach(void);
-void dfu_clear_detach(void);
int dfu_init_env_entities(char *interface, char *devstr);
unsigned char *dfu_get_buf(struct dfu_entity *dfu);
unsigned char *dfu_free_buf(void);
#define TEGRA20_CLK_OWR 71
#define TEGRA20_CLK_AFI 72
#define TEGRA20_CLK_CSITE 73
-/* 74 */
+#define TEGRA20_CLK_PCIE_XCLK 74
#define TEGRA20_CLK_AVPUCQ 75
#define TEGRA20_CLK_LA 76
/* 77 */
#define TEGRA30_CLK_OWR 71
#define TEGRA30_CLK_AFI 72
#define TEGRA30_CLK_CSITE 73
-/* 74 */
+#define TEGRA30_CLK_PCIEX 74
#define TEGRA30_CLK_AVPUCQ 75
#define TEGRA30_CLK_LA 76
/* 77 */
--- /dev/null
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
+
+#define TEGRA_XUSB_PADCTL_PCIE 0
+#define TEGRA_XUSB_PADCTL_SATA 1
+
+#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */
COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */
+ COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */
+ COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */
+ COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */
+ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+ /* Tegra124 XUSB pad controller */
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */
COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */
COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */
+ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_COUNT,
};
void g_dnl_unregister(void);
void g_dnl_set_serialnumber(char *);
+bool g_dnl_detach(void);
+void g_dnl_trigger_detach(void);
+void g_dnl_clear_detach(void);
+
#endif /* __G_DOWNLOAD_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PARADE_H__
+#define __PARADE_H__
+
+/* Initialize the Parade dP<->LVDS bridge if present */
+#ifdef CONFIG_VIDEO_PARADE
+int parade_init(const void *blob);
+#else
+static inline int parade_init(const void *blob) { return -1; }
+#endif
+
+#endif /* __PARADE_H__ */
*/
int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid,
disk_partition_t *partitions, const int parts_count);
+
+/**
+ * is_valid_gpt_buf() - Ensure that the Primary GPT information is valid
+ *
+ * @param dev_desc - block device descriptor
+ * @param buf - buffer which contains the MBR and Primary GPT info
+ *
+ * @return - '0' on success, otherwise error
+ */
+int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf);
+
+/**
+ * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
+ *
+ * @param dev_desc - block device descriptor
+ * @param buf - buffer which contains the MBR and Primary GPT info
+ *
+ * @return - '0' on success, otherwise error
+ */
+int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf);
#endif
#endif /* _PART_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __POWER_AS3722_H__
+#define __POWER_AS3722_H__
+
+#include <asm/types.h>
+
+#define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_INVERT (1 << 1)
+
+struct udevice;
+
+int as3722_init(struct udevice **devp);
+int as3722_sd_enable(struct udevice *pmic, unsigned int sd);
+int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value);
+int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo);
+int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value);
+int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
+ unsigned long flags);
+int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
+ unsigned int level);
+
+#endif /* __POWER_AS3722_H__ */
int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth);
+void ax88179_eth_before_probe(void);
+int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss);
+int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth);
+
void mcs7830_eth_before_probe(void);
int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss);
COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
COMPAT(NVIDIA_TEGRA114_SPI, "nvidia,tegra114-spi"),
+ COMPAT(NVIDIA_TEGRA124_PCIE, "nvidia,tegra124-pcie"),
+ COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"),
+ COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"),
+ COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
COMPAT(INTEL_GMA, "intel,gma"),
+ COMPAT(AMS_AS3722, "ams,as3722"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
if (gd->flags & GD_FLG_RELOC)
reloc_ofs = gd->reloc_off;
- debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs);
+ debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs);
+ if (gd->flags & GD_FLG_RELOC)
+ debug(" (relocated to %p)\n", (char *)*init_fnc_ptr);
+ else
+ debug("\n");
ret = (*init_fnc_ptr)();
if (ret) {
printf("initcall sequence %p failed at call %p (err=%d)\n",
exit 1
fi
-MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1)
-MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2)
+version_string=$($gas --version | head -1 | sed -e 's/.*) *\([0-9.]*\).*/\1/' )
+
+MAJOR=$(echo $version_string | cut -d . -f 1)
+MINOR=$(echo $version_string | cut -d . -f 2)
printf "%02d%02d\\n" $MAJOR $MINOR
hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
HOSTCFLAGS_mkexynosspl.o := -pedantic
+ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o
hostprogs-$(CONFIG_X86) += ifdtool
hostprogs-$(CONFIG_MX23) += mxsboot
Buildman is a builder. It is not make, although it runs make. It does not
produce any useful output on the terminal while building, except for
progress information (except with -v, see below). All the output (errors,
-warnings and binaries if you are ask for them) is stored in output
+warnings and binaries if you ask for them) is stored in output
directories, which you can look at while the build is progressing, or when
it is finished.
means to build all arm boards except nvidia, freescale and anything ending
with 'ball'.
-It is convenient to use the -n option to see whaat will be built based on
+It is convenient to use the -n option to see what will be built based on
the subset given.
Buildman does not store intermediate object files. It optionally copies
To find out how the build went, ask for a summary with -s. You can do this
-either before the build completes (presumably in another terminal) or or
+either before the build completes (presumably in another terminal) or
afterwards. Let's work through an example of how this is used:
$ ./tools/buildman/buildman -b lcd9b -s
At commit 16, the error moves - you can see that the old error at line 120
is fixed, but there is a new one at line 126. This is probably only because
-we added some code and moved the broken line father down the file.
+we added some code and moved the broken line further down the file.
If many boards have the same error, then -e will display the error only
once. This makes the output as concise as possible. To see which boards have
board was built) and by 96 bytes for powerpc. This increase was offset in both
cases by reductions in rodata and data/bss.
-Shown below the summary lines is the sizes for each board. Below each board
-is the sizes for each function. This information starts with:
+Shown below the summary lines are the sizes for each board. Below each board
+are the sizes for each function. This information starts with:
add - number of functions added / removed
grow - number of functions which grew / shrunk
This has mostly be written in my spare time as a response to my difficulties
in testing large series of patches. Apart from tidying up there is quite a
bit of scope for improvement. Things like better error diffs and easier
-access to log files. Also it would be nice it buildman could 'hunt' for
+access to log files. Also it would be nice if buildman could 'hunt' for
problems, perhaps by building a few boards for each arch, or checking
commits for changed files and building only boards which use those files.
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
+#include <libfdt.h>
#include "ifdtool.h"
#undef DEBUG
#define FLREG_BASE(reg) ((reg & 0x00000fff) << 12);
#define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff);
+enum input_file_type_t {
+ IF_normal,
+ IF_fdt,
+ IF_uboot,
+};
+
+struct input_file {
+ char *fname;
+ unsigned int addr;
+ enum input_file_type_t type;
+};
+
/**
* find_fd() - Find the flash description in the ROM image
*
return NULL;
}
- debug("Found Flash Descriptor signature at 0x%08x\n", i);
+ debug("Found Flash Descriptor signature at 0x%08lx\n",
+ (char *)ptr - image);
return (struct fdbar_t *)ptr;
}
return ret;
}
+static int perror_fname(const char *fmt, const char *fname)
+{
+ char msg[strlen(fmt) + strlen(fname) + 1];
+
+ sprintf(msg, fmt, fname);
+ perror(msg);
+
+ return -1;
+}
+
/**
* write_image() - Write the image to a file
*
new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR |
S_IWUSR | S_IRGRP | S_IROTH);
- if (write(new_fd, image, size) != size) {
- perror("Error while writing");
- return -1;
- }
+ if (new_fd < 0)
+ return perror_fname("Could not open file '%s'", filename);
+ if (write(new_fd, image, size) != size)
+ return perror_fname("Could not write file '%s'", filename);
close(new_fd);
return 0;
int fd = open(fname, O_RDONLY);
struct stat buf;
- if (fd == -1) {
- perror("Could not open file");
- return -1;
- }
- if (fstat(fd, &buf) == -1) {
- perror("Could not stat file");
- return -1;
- }
+ if (fd == -1)
+ return perror_fname("Could not open file '%s'", fname);
+ if (fstat(fd, &buf) == -1)
+ return perror_fname("Could not stat file '%s'", fname);
*sizep = buf.st_size;
debug("File %s is %d bytes\n", fname, *sizep);
* 0xffffffff so use an address relative to that. For an
* 8MB ROM the start address is 0xfff80000.
* @write_fname: Filename to add to the image
- * @return 0 if OK, -ve on error
+ * @return number of bytes written if OK, -ve on error
*/
static int write_data(char *image, int size, unsigned int addr,
const char *write_fname)
if (write_fd < 0)
return write_fd;
- offset = addr + size;
+ offset = (uint32_t)(addr + size);
debug("Writing %s to offset %#x\n", write_fname, offset);
if (offset < 0 || offset + write_size > size) {
close(write_fd);
+ return write_size;
+}
+
+/**
+ * write_uboot() - Write U-Boot, device tree and microcode pointer
+ *
+ * This writes U-Boot into a place in the flash, followed by its device tree.
+ * The microcode pointer is written so that U-Boot can find the microcode in
+ * the device tree very early in boot.
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @uboot: Input file information for u-boot.bin
+ * @fdt: Input file information for u-boot.dtb
+ * @ucode_ptr: Address in U-Boot where the microcode pointer should be placed
+ * @return 0 if OK, -ve on error
+ */
+static int write_uboot(char *image, int size, struct input_file *uboot,
+ struct input_file *fdt, unsigned int ucode_ptr)
+{
+ const void *blob;
+ const char *data;
+ int uboot_size;
+ uint32_t *ptr;
+ int data_size;
+ int offset;
+ int node;
+ int ret;
+
+ uboot_size = write_data(image, size, uboot->addr, uboot->fname);
+ if (uboot_size < 0)
+ return uboot_size;
+ fdt->addr = uboot->addr + uboot_size;
+ debug("U-Boot size %#x, FDT at %#x\n", uboot_size, fdt->addr);
+ ret = write_data(image, size, fdt->addr, fdt->fname);
+ if (ret < 0)
+ return ret;
+
+ if (ucode_ptr) {
+ blob = (void *)image + (uint32_t)(fdt->addr + size);
+ debug("DTB at %lx\n", (char *)blob - image);
+ node = fdt_node_offset_by_compatible(blob, 0,
+ "intel,microcode");
+ if (node < 0) {
+ debug("No microcode found in FDT: %s\n",
+ fdt_strerror(node));
+ return -ENOENT;
+ }
+ data = fdt_getprop(blob, node, "data", &data_size);
+ if (!data) {
+ debug("No microcode data found in FDT: %s\n",
+ fdt_strerror(data_size));
+ return -ENOENT;
+ }
+ offset = ucode_ptr - uboot->addr;
+ ptr = (void *)image + offset;
+ ptr[0] = uboot->addr + (data - image);
+ ptr[1] = data_size;
+ debug("Wrote microcode pointer at %x: addr=%x, size=%x\n",
+ ucode_ptr, ptr[0], ptr[1]);
+ }
+
return 0;
}
char *desc_fname = NULL, *addr_str = NULL;
int region_type = -1, inputfreq = 0;
enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
- unsigned int addr[WRITE_MAX];
- char *wr_fname[WRITE_MAX];
+ struct input_file input_file[WRITE_MAX], *ifile, *fdt = NULL;
unsigned char wr_idx, wr_num = 0;
int rom_size = -1;
bool write_it;
char *outfile = NULL;
struct stat buf;
int size = 0;
+ unsigned int ucode_ptr = 0;
+ bool have_uboot = false;
int bios_fd;
char *image;
int ret;
{"descriptor", 1, NULL, 'D'},
{"em100", 0, NULL, 'e'},
{"extract", 0, NULL, 'x'},
+ {"fdt", 1, NULL, 'f'},
{"inject", 1, NULL, 'i'},
{"lock", 0, NULL, 'l'},
+ {"microcode", 1, NULL, 'm'},
{"romsize", 1, NULL, 'r'},
{"spifreq", 1, NULL, 's'},
{"unlock", 0, NULL, 'u'},
+ {"uboot", 1, NULL, 'U'},
{"write", 1, NULL, 'w'},
{"version", 0, NULL, 'v'},
{"help", 0, NULL, 'h'},
{0, 0, 0, 0}
};
- while ((opt = getopt_long(argc, argv, "cdD:ehi:lr:s:uvw:x?",
+ while ((opt = getopt_long(argc, argv, "cdD:ef:hi:lm:r:s:uU:vw:x?",
long_options, &option_index)) != EOF) {
switch (opt) {
case 'c':
case 'l':
mode_locked = 1;
break;
+ case 'm':
+ ucode_ptr = strtoul(optarg, NULL, 0);
+ break;
case 'r':
rom_size = strtol(optarg, NULL, 0);
debug("ROM size %d\n", rom_size);
exit(EXIT_SUCCESS);
break;
case 'w':
+ case 'U':
+ case 'f':
+ ifile = &input_file[wr_num];
mode_write = 1;
if (wr_num < WRITE_MAX) {
if (get_two_words(optarg, &addr_str,
- &wr_fname[wr_num])) {
+ &ifile->fname)) {
print_usage(argv[0]);
exit(EXIT_FAILURE);
}
- addr[wr_num] = strtol(optarg, NULL, 0);
+ ifile->addr = strtol(optarg, NULL, 0);
+ ifile->type = opt == 'f' ? IF_fdt :
+ opt == 'U' ? IF_uboot : IF_normal;
+ if (ifile->type == IF_fdt)
+ fdt = ifile;
+ else if (ifile->type == IF_uboot)
+ have_uboot = true;
wr_num++;
} else {
fprintf(stderr,
exit(EXIT_FAILURE);
}
+ if (have_uboot && !fdt) {
+ fprintf(stderr,
+ "You must supply a device tree file for U-Boot\n\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
filename = argv[optind];
if (optind + 2 != argc)
outfile = argv[optind + 1];
if (mode_write) {
for (wr_idx = 0; wr_idx < wr_num; wr_idx++) {
- ret = write_data(image, size,
- addr[wr_idx], wr_fname[wr_idx]);
- if (ret)
+ ifile = &input_file[wr_idx];
+ if (ifile->type == IF_fdt) {
+ continue;
+ } else if (ifile->type == IF_uboot) {
+ ret = write_uboot(image, size, ifile, fdt,
+ ucode_ptr);
+ } else {
+ ret = write_data(image, size, ifile->addr,
+ ifile->fname);
+ }
+ if (ret < 0)
break;
}
}
free(image);
close(bios_fd);
- return ret ? 1 : 0;
+ return ret < 0 ? 1 : 0;
}
--- /dev/null
+microcode-tool.py
\ No newline at end of file
--- /dev/null
+#!/usr/bin/env python
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Intel microcode update tool
+
+from optparse import OptionParser
+import os
+import re
+import struct
+import sys
+
+MICROCODE_DIR = 'arch/x86/dts/microcode'
+
+class Microcode:
+ """Holds information about the microcode for a particular model of CPU.
+
+ Attributes:
+ name: Name of the CPU this microcode is for, including any version
+ information (e.g. 'm12206a7_00000029')
+ model: Model code string (this is cpuid(1).eax, e.g. '206a7')
+ words: List of hex words containing the microcode. The first 16 words
+ are the public header.
+ """
+ def __init__(self, name, data):
+ self.name = name
+ # Convert data into a list of hex words
+ self.words = []
+ for value in ''.join(data).split(','):
+ hexval = value.strip()
+ if hexval:
+ self.words.append(int(hexval, 0))
+
+ # The model is in the 4rd hex word
+ self.model = '%x' % self.words[3]
+
+def ParseFile(fname):
+ """Parse a micrcode.dat file and return the component parts
+
+ Args:
+ fname: Filename to parse
+ Returns:
+ 3-Tuple:
+ date: String containing date from the file's header
+ license_text: List of text lines for the license file
+ microcodes: List of Microcode objects from the file
+ """
+ re_date = re.compile('/\* *(.* [0-9]{4}) *\*/$')
+ re_license = re.compile('/[^-*+] *(.*)$')
+ re_name = re.compile('/\* *(.*)\.inc *\*/', re.IGNORECASE)
+ microcodes = {}
+ license_text = []
+ date = ''
+ data = []
+ name = None
+ with open(fname) as fd:
+ for line in fd:
+ line = line.rstrip()
+ m_date = re_date.match(line)
+ m_license = re_license.match(line)
+ m_name = re_name.match(line)
+ if m_name:
+ if name:
+ microcodes[name] = Microcode(name, data)
+ name = m_name.group(1).lower()
+ data = []
+ elif m_license:
+ license_text.append(m_license.group(1))
+ elif m_date:
+ date = m_date.group(1)
+ else:
+ data.append(line)
+ if name:
+ microcodes[name] = Microcode(name, data)
+ return date, license_text, microcodes
+
+def List(date, microcodes, model):
+ """List the available microcode chunks
+
+ Args:
+ date: Date of the microcode file
+ microcodes: Dict of Microcode objects indexed by name
+ model: Model string to search for, or None
+ """
+ print 'Date: %s' % date
+ if model:
+ mcode_list, tried = FindMicrocode(microcodes, model.lower())
+ print 'Matching models %s:' % (', '.join(tried))
+ else:
+ print 'All models:'
+ mcode_list = [microcodes[m] for m in microcodes.keys()]
+ for mcode in mcode_list:
+ print '%-20s: model %s' % (mcode.name, mcode.model)
+
+def FindMicrocode(microcodes, model):
+ """Find all the microcode chunks which match the given model.
+
+ This model is something like 306a9 (the value returned in eax from
+ cpuid(1) when running on Intel CPUs). But we allow a partial match,
+ omitting the last 1 or two characters to allow many families to have the
+ same microcode.
+
+ If the model name is ambiguous we return a list of matches.
+
+ Args:
+ microcodes: Dict of Microcode objects indexed by name
+ model: String containing model name to find
+ Returns:
+ Tuple:
+ List of matching Microcode objects
+ List of abbreviations we tried
+ """
+ # Allow a full name to be used
+ mcode = microcodes.get(model)
+ if mcode:
+ return [mcode], []
+
+ tried = []
+ found = []
+ for i in range(3):
+ abbrev = model[:-i] if i else model
+ tried.append(abbrev)
+ for mcode in microcodes.values():
+ if mcode.model.startswith(abbrev):
+ found.append(mcode)
+ if found:
+ break
+ return found, tried
+
+def CreateFile(date, license_text, mcode, outfile):
+ """Create a microcode file in U-Boot's .dtsi format
+
+ Args:
+ date: String containing date of original microcode file
+ license: List of text lines for the license file
+ mcode: Microcode object to write
+ outfile: Filename to write to ('-' for stdout)
+ """
+ out = '''/*%s
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date: %s
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <%d>;
+intel,update-revision = <%#x>;
+intel,date-code = <%#x>;
+intel,processor-signature = <%#x>;
+intel,checksum = <%#x>;
+intel,loader-revision = <%d>;
+intel,processor-flags = <%#x>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <%s
+\t>;'''
+ words = ''
+ for i in range(len(mcode.words)):
+ if not (i & 3):
+ words += '\n'
+ val = mcode.words[i]
+ # Change each word so it will be little-endian in the FDT
+ # This data is needed before RAM is available on some platforms so we
+ # cannot do an endianness swap on boot.
+ val = struct.unpack("<I", struct.pack(">I", val))[0]
+ words += '\t%#010x' % val
+
+ # Take care to avoid adding a space before a tab
+ text = ''
+ for line in license_text:
+ if line[0] == '\t':
+ text += '\n *' + line
+ else:
+ text += '\n * ' + line
+ args = [text, date]
+ args += [mcode.words[i] for i in range(7)]
+ args.append(words)
+ if outfile == '-':
+ print out % tuple(args)
+ else:
+ if not outfile:
+ if not os.path.exists(MICROCODE_DIR):
+ print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
+ os.makedirs(MICROCODE_DIR)
+ outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
+ print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
+ mcode.name, outfile)
+ with open(outfile, 'w') as fd:
+ print >> fd, out % tuple(args)
+
+def MicrocodeTool():
+ """Run the microcode tool"""
+ commands = 'create,license,list'.split(',')
+ parser = OptionParser()
+ parser.add_option('-d', '--mcfile', type='string', action='store',
+ help='Name of microcode.dat file')
+ parser.add_option('-m', '--model', type='string', action='store',
+ help='Model name to extract')
+ parser.add_option('-o', '--outfile', type='string', action='store',
+ help='Filename to use for output (- for stdout), default is'
+ ' %s/<name>.dtsi' % MICROCODE_DIR)
+ parser.usage += """ command
+
+ Process an Intel microcode file (use -h for help). Commands:
+
+ create Create microcode .dtsi file for a model
+ list List available models in microcode file
+ license Print the license
+
+ Typical usage:
+
+ ./tools/microcode-tool -d microcode.dat -m 306a create
+
+ This will find the appropriate file and write it to %s.""" % MICROCODE_DIR
+
+ (options, args) = parser.parse_args()
+ if not args:
+ parser.error('Please specify a command')
+ cmd = args[0]
+ if cmd not in commands:
+ parser.error("Unknown command '%s'" % cmd)
+
+ if not options.mcfile:
+ parser.error('You must specify a microcode file')
+ date, license_text, microcodes = ParseFile(options.mcfile)
+
+ if cmd == 'list':
+ List(date, microcodes, options.model)
+ elif cmd == 'license':
+ print '\n'.join(license_text)
+ elif cmd == 'create':
+ if not options.model:
+ parser.error('You must specify a model to create')
+ model = options.model.lower()
+ mcode_list, tried = FindMicrocode(microcodes, model)
+ if not mcode_list:
+ parser.error("Unknown model '%s' (%s) - try 'list' to list" %
+ (model, ', '.join(tried)))
+ if len(mcode_list) > 1:
+ parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' "
+ "to list or specify a particular file" %
+ (model, ', '.join(tried),
+ ', '.join([m.name for m in mcode_list])))
+ CreateFile(date, license_text, mcode_list[0], options.outfile)
+ else:
+ parser.error("Unknown command '%s'" % cmd)
+
+if __name__ == "__main__":
+ MicrocodeTool()
projects / karo-tx-uboot.git / commitdiff