arm:mx6sx add QSPI support

Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 93a02adcec4d843e68196903f891cccaddb566ab..a05dca33af0c7792220f92e9d5eaad2bff65cf89 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -434,6 +434,56 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
 }
 #endif
 

+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+       u32 reg = 0;
+       /* Enable QuadSPI clock */
+       switch (qspi_num) {
+       case 0:
+               /* disable the clock gate */
+               clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+               /* set 50M  : (50 = 396 / 2 / 4) */
+               reg = readl(&imx_ccm->cscmr1);
+               reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+                        MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+               reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+                       (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+               writel(reg, &imx_ccm->cscmr1);
+
+               /* enable the clock gate */
+               setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+               break;
+       case 1:
+               /*
+                * disable the clock gate
+                * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+                * disable both of them.
+                */
+               clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+                            MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+               /* set 50M  : (50 = 396 / 2 / 4) */
+               reg = readl(&imx_ccm->cs2cdr);
+               reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+                        MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+                        MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+               reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+                       MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+               writel(reg, &imx_ccm->cs2cdr);
+
+               /*enable the clock gate*/
+               setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+                            MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+               break;
+       default:
+               break;
+       }
+}
+#endif
+

 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {

diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 226a4cde17e0c9b3b528f155ca786f27c7110ec1..a6de5ee4bc12623a769b96a8f9bc86dde7b9e47f 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);

+void enable_qspi_clk(int qspi_num);

 void enable_thermal_clk(void);
 #endif /* __ASM_ARCH_CLOCK_H */
 void enable_thermal_clk(void);
 #endif /* __ASM_ARCH_CLOCK_H */

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5314298a1dd6a801f34ba680dd433ad2ed5b081d..c968600b770f397972722e655221a0f834d49d6c 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -92,10 +92,10 @@
 #define AIPS3_END_ADDR                 0x022FFFFF
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define AIPS3_END_ADDR                 0x022FFFFF
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF

-#define QSPI1_ARB_BASE_ADDR             0x60000000
-#define QSPI1_ARB_END_ADDR              0x6FFFFFFF
-#define QSPI2_ARB_BASE_ADDR             0x70000000
-#define QSPI2_ARB_END_ADDR              0x7FFFFFFF
+#define QSPI0_AMBA_BASE                0x60000000
+#define QSPI0_AMBA_END                 0x6FFFFFFF
+#define QSPI1_AMBA_BASE                0x70000000
+#define QSPI1_AMBA_END                 0x7FFFFFFF

 #else
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF
 #else
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF


@@ -262,8 +262,8 @@
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 #ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 #ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)

-#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define QSPI2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)

 #else
 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
 #else
 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index eae2f3acc67879b313d09ddc9c83dcada79bf729..e9c45de06dbd77d226eeed1e9bbeda7c6a261a94 100644 (file)
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,11 @@
 #include "fsl_qspi.h"
 
 #define RX_BUFFER_SIZE         0x80
 #include "fsl_qspi.h"
 
 #define RX_BUFFER_SIZE         0x80

+#ifdef CONFIG_MX6SX
+#define TX_BUFFER_SIZE         0x200
+#else

 #define TX_BUFFER_SIZE         0x40
 #define TX_BUFFER_SIZE         0x40

+#endif

 
 #define OFFSET_BITS_MASK       0x00ffffff
 
 
 #define OFFSET_BITS_MASK       0x00ffffff
 


@@ -53,10 +57,16 @@
 
 static unsigned long spi_bases[] = {
        QSPI0_BASE_ADDR,
 
 static unsigned long spi_bases[] = {
        QSPI0_BASE_ADDR,

+#ifdef CONFIG_MX6SX
+       QSPI1_BASE_ADDR,
+#endif

 };
 
 static unsigned long amba_bases[] = {
        QSPI0_AMBA_BASE,
 };
 
 static unsigned long amba_bases[] = {
        QSPI0_AMBA_BASE,

+#ifdef CONFIG_MX6SX
+       QSPI1_AMBA_BASE,
+#endif

 };
 
 struct fsl_qspi {
 };
 
 struct fsl_qspi {


@@ -159,8 +169,17 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
                qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
                        PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
                        PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
                qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
                        PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
                        PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));

+#ifdef CONFIG_MX6SX
+       /*
+        * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
+        * So, Use IDATSZ in IPCR to determine the size and here set 0.
+        */
+       qspi_write32(&regs->lut[lut_base + 1], OPRND0(0) |
+                    PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#else

        qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
                PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
        qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
                PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));

+#endif

        qspi_write32(&regs->lut[lut_base + 2], 0);
        qspi_write32(&regs->lut[lut_base + 3], 0);
 
        qspi_write32(&regs->lut[lut_base + 2], 0);
        qspi_write32(&regs->lut[lut_base + 3], 0);