]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
am33xx: Move the call to ddr_pll_config, make it take the frequency
authorTom Rini <trini@ti.com>
Tue, 3 Jul 2012 16:20:06 +0000 (09:20 -0700)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 1 Sep 2012 12:58:12 +0000 (14:58 +0200)
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value.  This call can be delayed
slightly to the point where we know which type of memory we have.

Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/include/asm/arch-am33xx/sys_proto.h

index f06882472ea4b153783970db061ef32bf55bdfb0..1071f925cc171c76c8f6d972d64bf6b4fed89510 100644 (file)
@@ -246,7 +246,7 @@ static void per_pll_config(void)
                ;
 }
 
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
 {
        u32 clkmode, clksel, div_m2;
 
@@ -264,7 +264,7 @@ static void ddr_pll_config(void)
                ;
 
        clksel = clksel & (~CLK_SEL_MASK);
-       clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+       clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
        writel(clksel, &cmwkup->clkseldpllddr);
 
        div_m2 = div_m2 & CLK_DIV_SEL;
@@ -298,7 +298,6 @@ void pll_init()
        mpu_pll_config();
        core_pll_config();
        per_pll_config();
-       ddr_pll_config();
 
        /* Enable the required interconnect clocks */
        enable_interface_clocks();
index 9b1a80c0245f33dad6c8830ae68b7b7fc2d2c9f9..12f270a2d46401a8cdc312d209dc71346b0e40fc 100644 (file)
@@ -21,6 +21,7 @@
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 
@@ -150,6 +151,7 @@ void config_ddr(short ddr_type)
        enable_emif_clocks();
 
        if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+               ddr_pll_config(266);
                config_vtp();
 
                config_cmd_ctrl(&ddr2_cmd_ctrl_data);
index 6c58f1b30fd6fac7e57e50f8b052fcd01d6375bd..eef55732a859ca17616b00d7fda2c63ce892ec86 100644 (file)
@@ -30,4 +30,5 @@ int print_cpuinfo(void);
 
 u32 get_device_type(void);
 void setup_clocks_for_console(void);
+void ddr_pll_config(unsigned int ddrpll_M);
 #endif