+commit 17a41e4492121ccf9fa2c10c2cb1a6d1c18d74f7
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Jan 9 16:56:54 2008 -0600
+
+ Add QE brg freq and correct qe bus freq fdt update code
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 890dfef06c2d169a3356359596890754dfb8ee1c
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Jan 9 16:34:51 2008 -0600
+
+ Remove cache config from ATUM8548 and sbc8548 configs
+
+ These boards weren't updated by Kumar's config patch because they
+ weren't in the tree, yet.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit b8ec2385038c094b07ec5b49336289a46b6e9cc6
+Author: Timur Tabi <timur@freescale.com>
+Date: Mon Jan 7 13:31:19 2008 -0600
+
+ 85xx: add ability to upload QE firmware
+
+ Define the layout of a binary blob that contains a QE firmware and instructions
+ on how to upload it. Add function qe_upload_firmware() to parse the blob and
+ perform the actual upload. Add command-line command "qe fw" to take a firmware
+ blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the
+ 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define
+ 'struct rsp' in immap_qe.h to include the actual RISC Special Registers.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Jan 8 01:22:21 2008 -0600
+
+ 85xx: Remove cache config from configs.h
+
+ Either use the standard defines in asm/cache.h or grab the information
+ at runtime from the L1CFG SPR.
+
+ Also, minor cleanup in cache.h to make the code a bit more readable.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b964e9368f45372aaf1da0c13fe56f6d81ae8e96
+Author: robert lazarski <robertlazarski@gmail.com>
+Date: Fri Dec 21 10:39:27 2007 -0500
+
+ mpc85xx: Add support for ATUM8548 (updated)
+
+ Add support for Instituto Atlantico's ATUM8548 board
+
+ Signed-off-by: robert lazarski <robertlazarski@gmail.com>
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 7bd6104b71de9bca80ac8e0936003443bb42f2fc
+Author: robert lazarski <robertlazarski@gmail.com>
+Date: Fri Dec 21 10:36:37 2007 -0500
+
+ mpc85xx: Add support for ATUM8548 (updated)
+
+ Add support for Instituto Atlantico's ATUM8548 board
+
+ Signed-off-by: robert lazarski <robertlazarski@gmail.com>
+
+commit 9e3ed392d2c8965e24c942b58796c31c644c2f70
+Author: Joe Hamman <joe.hamman@embeddedspecialties.com>
+Date: Thu Dec 13 06:45:14 2007 -0600
+
+ mpc85xx: Add support for SBC8548 (updated)
+
+ Add support for Wind River's SBC8548 reference board.
+
+ Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
+
+commit 11c45ebd46d6517b51b7a92dd52a618b2f4e5586
+Author: Joe Hamman <joe.hamman@embeddedspecialties.com>
+Date: Thu Dec 13 06:45:08 2007 -0600
+
+ mpc85xx: Add support for SBC8548 (updated)
+
+ Add support for Wind River's SBC8548 reference board.
+
+ Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
+ Signed-off by: Andy Fleming <afleming@freescale.com>
+
+commit 64d4bcb087c2ece1c4d0de8efe85e0075e5b1594
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Oct 22 19:58:19 2007 +0400
+
+ MPC8568E-MDS: set up QE pario for UART1
+
+ To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should
+ be set up appropriately.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit ad162249cb371e9e38971676f09be791e5f3cf4a
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Oct 22 18:12:46 2007 +0400
+
+ MPC8568E-MDS: reset UCCs to use them reliably
+
+ In order to use GETH1 and GETH2 on the MPC8568E-MDS, we should reset
+ UCCs.
+
+ p.s Similar code exists in the Linux kernel board file (for capability
+ reasons with older U-Boots), but should be removed some day.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 2146cf56821c3364786ca94a7306008c5824b238
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Dec 19 01:18:15 2007 -0600
+
+ Reworked FSL Book-E TLB macros to be more readable
+
+ The old macros made it difficult to know what WIMGE and perm bits
+ were set for a TLB entry. Actually use the bit masks for these items
+ since they are only a single bit.
+
+ Also moved the macros into mmu.h out of e500.h since they aren't specific
+ to e500.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1d47273d46925929f8f2c1913cd96d7257aade88
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Dec 18 23:21:51 2007 -0600
+
+ Use FSL Book-E MMU macros from Linux Kernel
+
+ Grab the FSL Book-E MAS register macros from Linux. Also added
+ defines for page sizes up to 4TB and removed SHAREN since it doesnt
+ really exist.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 02df4a270f817ef6ec39047a01b55fecdc5f3b37
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Jan 9 13:51:32 2008 -0600
+
+ Fix my own merge stupidity
+
+ Way back in August I merged Heiko's patch:
+ 566a494f592: [PCS440EP] upgrade the PCS440EP board
+
+ with Jon's CONFIG_COMMANDS patches.
+
+ This was done in commit: 6bf6f114dcdd97ec3f80c2761ed40e31229d6b78
+
+ However, in the process, I left out some of Heiko's good changes.
+
+ Now Heiko's and Jon's patches are properly merged in fat_register_device()
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 6636b62a6efc7f14e6e788788631ae7a7fca4537
+Author: James Yang <James.Yang@freescale.com>
+Date: Wed Jan 9 11:17:49 2008 -0600
+
+ Expose parse_line() globally.
+
+ Add new function readline_into_buffer() that allows the
+ output of readline to be put into a pointer to char buffer.
+
+ This refactoring allows other functions besides the
+ main command loop to also use the same input mechanism.
+
+ Signed-off-by: James Yang <James.Yang@freescale.com>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 7ca90513486abd4ae50bd1b7403f47cc58c5ad25
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Wed Jan 9 01:15:25 2008 +0100
+
+ trivial: fix consequences of a bad merge
+
+ Fix what looks like a merge artifact.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 4785a694c0045996ccf0ac5b8edf531efc1b730e
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Thu Jan 3 10:51:15 2008 +0800
+
+ Add Ctrl combo key support to usb keyboard driver.
+
+ Ctrl combo key support is added, which is very useful to input Ctrl-C
+ for interrupt current job.
+ Also add usb_event_poll() calling to usb_kbd_testc(), which can get
+ key input when tstc() is called.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+
+commit 10c7382bc5d5e64c47f94ac2ca78cc574442e82d
+Author: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Sun Dec 30 03:30:56 2007 +0100
+
+ fix various comments
+
+ Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
+
+commit 7817cb2083d982923752fe0f12b67c0e7c09a027
+Author: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Sun Dec 30 03:30:46 2007 +0100
+
+ fix comments with new drivers organization
+
+ Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
+
+commit a9b410dc7d2a4721c408b13abfc037988150f145
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Fri Dec 28 12:50:59 2007 +0900
+
+ Remove the obsolete terse version of do_mii()
+
+ We now have more useful version of do_mii() and everybody use it.
+ Gerald Van Baren says:
+
+ > When I originally wrote the mii command 6(!) years ago, I wrote a
+ > verbose version that printed human readable decomposition of the flags,
+ > etc., and a terse one that didn't print as much stuff and thus had a
+ > smaller memory footprint.
+ >
+ > It sounds like the terse version has withered and died, apparently
+ > people are only using the verbose version (which is very understandable,
+ > I do myself).
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+ Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 01c687aa6e065bd4faf80f723361e798941dd6b0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Dec 27 13:42:56 2007 -0500
+
+ Do not reference sha1.c when building mkimage.
+
+ remove sha1.o from mkimage linking since it isn't actually used.
+
+ Signed-Off-By: Mike Frysinger <vapier@gentoo.org>
+
+commit b9173af73e524d37c812f210173cf83385c5171a
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Thu Dec 27 15:39:54 2007 +0900
+
+ common/cmd_mii.c: Add sanity argc check
+
+ If type mii command without arguments, we suffer from uninitialized argv[]
+ entries; for example we MIPS get stuck by TLB error.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 500856eb1707ed17d9204baa61dd59948d3b2899
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Wed Jan 9 19:39:36 2008 +0100
+
+ API for external applications.
+
+ This is an API for external (standalone) applications running on top of
+ U-Boot, and is meant to be more extensible and robust than the existing
+ jumptable mechanism. It is similar to UNIX syscall approach. See api/README
+ for more details.
+
+ Included is the demo application using this new framework (api_examples).
+
+ Please note this is still an experimental feature, and is turned off by
+ default.
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 26a41790f8eba19ad450e18ae91351daf485b3e2
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Wed Jan 9 18:05:27 2008 +0100
+
+ Globalize envmatch()
+
+ The newly introduced API (routines related to env vars) will need to call
+ it.
+
+ Signed-off-by: Rafal Zabdyr <armo@semihalf.com>
+
+commit 6007f3251c0967adc13f2ed8be1b924ddc30124d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jan 9 15:14:46 2008 +0100
+
+ Coding Style cleanup, update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit fc6414eca55f1fc108fb12fc8cdc43bd8b4463f9
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Dec 18 04:29:55 2007 -0500
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+commit 58694f9709c0c3e3178e349ae748d98cfb0c639a
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Thu Jan 3 10:51:15 2008 +0800
+
+ Add Ctrl combo key support to usb keyboard driver.
+
+ Ctrl combo key support is added, which is very useful to input Ctrl-C
+ for interrupt current job.
+ Also add usb_event_poll() calling to usb_kbd_testc(), which can get
+ key input when tstc() is called.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+ Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
commit 07eb02687f008721974a2fb54cd7fdc28033ab3c
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jan 9 13:43:38 2008 +0100
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+commit c83d7ca4dadd44ae430235077f63b64a11f36f6e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Jan 8 22:58:27 2008 +0100
+
+ Fix compile problem with new env code.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6de66b35426312a21174a9bf0576a094e2904bea
+Author: Markus Klotzbücher <mk@denx.de>
+Date: Tue Nov 27 10:23:20 2007 +0100
+
+ tools: fix fw_printenv tool to compile again
+
+ This patch updates the fw_printenv/fw_setenv userspace tool to include
+ the correct MTD header in order to compile against current kernel
+ headers. Backward compatibility is preserved by introducing an option
+ MTD_VERSION which can be set to "old" for compilation using the old MTD
+ headers. Along with this a number of warnings are fixed.
+
+ Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
commit ad3006fe7e84667021753b74247b0bafd97ba35f
Author: Gerald Van Baren <vanbaren@cideas.com>
Date: Mon Jan 7 23:47:32 2008 -0500
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 245a362ad3c0c1b84fccc9fec7b623eb14f6e502
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Wed Oct 24 01:37:36 2007 +0200
+
+ TQM5200: Call usb_cpu_init() during board init
+
+ usb_cpu_init() configures GPS USB pins, clocks, etc. and
+ is required for proper operation of kernel USB subsystem.
+ This setup was previously done in the kernel by the fixup
+ code which is being removed, thus low level init must be
+ done by U-boot now.
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+ Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit b5af773f8d92677e06f3295b45557c9d0a487c24
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Thu Oct 25 17:51:27 2007 +0800
+
+ Fix the issue of usb_kbd driver missing the scan code of key 'z'.
+
+ The scan code of the key 'z' is 0x1d, which should be handled.
+
+ The change has be tested on NOVATEK USB keyboard and ULI PCI OHCI
+ controller.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+ Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 85ac988e86f9414fa645b0148dc66c3520a1eb84
+Author: Rodolfo Giometti <giometti@enneenne.com>
+Date: Mon Oct 15 11:59:17 2007 +0200
+
+ PXA USB OHCI: "usb stop" implementation.
+
+ Some USB keys need to be switched off before loading the kernel
+ otherwise they can remain in an undefined status which prevents them
+ to be correctly recognized by the kernel.
+
+ Signed-off-by: Rodolfo Giometti <giometti@linux.it>
+ Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
commit 31548249decf18a6b877a18436b6139dd483fe4a
Author: Justin Flammia <jflammia@savantav.com>
Date: Mon Oct 29 17:40:35 2007 -0400
Joe Hamman <joe.hamman@embeddedspecialties.com>
+ sbc8548 MPC8548
sbc8641d MPC8641D
Klaus Heydeck <heydeck@kieback-peter.de>
GTH MPC860
+Robert Lazarski <robertlazarski@gmail.com>
+
+ ATUM8548 MPC8548
+
The LEOX team <team@leox.org>
ELPT860 MPC860T
#########################################################################
LIST_85xx=" \
+ ATUM8548 \
MPC8540ADS \
MPC8540EVAL \
MPC8541CDS \
PM854 \
PM856 \
sbc8540 \
+ sbc8548 \
sbc8560 \
stxgp3 \
stxssa \
"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
LIBS += common/libcommon.a
LIBS += libfdt/libfdt.a
+ifeq ($(CONFIG_API),y)
+LIBS += api/libapi.a
+endif
LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS)
SUBDIRS = tools \
examples
+ifeq ($(CONFIG_API),y)
+SUBDIRS += api_examples
+endif
+
.PHONY : $(SUBDIRS)
ifeq ($(CONFIG_NAND_U_BOOT),y)
## MPC85xx Systems
#########################################################################
+ATUM8548_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+
MPC8540ADS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
fi
@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
+sbc8548_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
+
sbc8560_config \
sbc8560_33_config \
sbc8560_66_config: unconfig
rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
rm -f $(obj)include/bmp_logo.h
rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
+ rm -f $(obj)api_examples/demo
clobber: clean
find $(OBJTREE) -type f \( -name .depend \
rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
[ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
+ find $(obj)api_examples -lname "*" -print | xargs rm -f
+ rm -f $(obj)api_examples/demo
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
(i.e. setenv videomode 317; saveenv; reset;)
- "videomode=bootargs" all the video parameters are parsed
- from the bootargs. (See drivers/videomodes.c)
+ from the bootargs. (See drivers/video/videomodes.c)
CONFIG_VIDEO_SED13806
CONFIG_FSL_I2C
Define this option if you want to use Freescale's I2C driver in
- drivers/fsl_i2c.c.
+ drivers/i2c/fsl_i2c.c.
- SPI Support: CONFIG_SPI
--- /dev/null
+#
+# (C) Copyright 2007 Semihalf
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libapi.a
+
+COBJS = api.o api_net.o api_storage.o api_platform-$(ARCH).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+U-Boot machine/arch independent API for external apps
+=====================================================
+
+1. Main assumptions
+
+ - there is a single entry point (syscall) to the API
+
+ - per current design the syscall is a C-callable function in the U-Boot
+ text, which might evolve into a real syscall using machine exception trap
+ once this initial version proves functional
+
+ - the consumer app is responsible for producing appropriate context (call
+ number and arguments)
+
+ - upon entry, the syscall dispatches the call to other (existing) U-Boot
+ functional areas like networking or storage operations
+
+ - consumer application will recognize the API is available by searching
+ a specified (assumed by convention) range of address space for the
+ signature
+
+ - the U-Boot integral part of the API is meant to be thin and non-intrusive,
+ leaving as much processing as possible on the consumer application side,
+ for example it doesn't keep states, but relies on hints from the app and
+ so on
+
+ - optional (CONFIG_API)
+
+
+2. Calls
+
+ - console related (getc, putc, tstc etc.)
+ - system (reset, platform info)
+ - time (delay, current)
+ - env vars (enumerate all, get, set)
+ - devices (enumerate all, open, close, read, write); currently two classes
+ of devices are recognized and supported: network and storage (ide, scsi,
+ usb etc.)
+
+
+3. Structure overview
+
+ - core API, integral part of U-Boot, mandatory
+ - implements the single entry point (mimics UNIX syscall)
+
+ - glue
+ - entry point at the consumer side, allows to make syscall, mandatory
+ part
+
+ - helper conveniency wrappers so that consumer app does not have to use
+ the syscall directly, but in a more friendly manner (a la libc calls),
+ optional part
+
+ - consumer application
+ - calls directly, or leverages the provided glue mid-layer
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_API)
+
+#include <command.h>
+#include <common.h>
+#include <malloc.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include "api_private.h"
+
+#define DEBUG
+#undef DEBUG
+
+/* U-Boot routines needed */
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern uchar (*env_get_char)(int);
+extern uchar *env_get_addr(int);
+
+/*****************************************************************************
+ *
+ * This is the API core.
+ *
+ * API_ functions are part of U-Boot code and constitute the lowest level
+ * calls:
+ *
+ * - they know what values they need as arguments
+ * - their direct return value pertains to the API_ "shell" itself (0 on
+ * success, some error code otherwise)
+ * - if the call returns a value it is buried within arguments
+ *
+ ****************************************************************************/
+
+#ifdef DEBUG
+#define debugf(fmt, args...) do { printf("%s(): ", __func__); printf(fmt, ##args); } while (0)
+#else
+#define debugf(fmt, args...)
+#endif
+
+typedef int (*cfp_t)(va_list argp);
+
+static int calls_no;
+
+/*
+ * pseudo signature:
+ *
+ * int API_getc(int *c)
+ */
+static int API_getc(va_list ap)
+{
+ int *c;
+
+ if ((c = (int *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ *c = getc();
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_tstc(int *c)
+ */
+static int API_tstc(va_list ap)
+{
+ int *t;
+
+ if ((t = (int *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ *t = tstc();
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_putc(char *ch)
+ */
+static int API_putc(va_list ap)
+{
+ char *c;
+
+ if ((c = (char *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ putc(*c);
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_puts(char **s)
+ */
+static int API_puts(va_list ap)
+{
+ char *s;
+
+ if ((s = (char *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ puts(s);
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_reset(void)
+ */
+static int API_reset(va_list ap)
+{
+ do_reset(NULL, 0, 0, NULL);
+
+ /* NOT REACHED */
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_get_sys_info(struct sys_info *si)
+ *
+ * fill out the sys_info struct containing selected parameters about the
+ * machine
+ */
+static int API_get_sys_info(va_list ap)
+{
+ struct sys_info *si;
+
+ si = (struct sys_info *)va_arg(ap, u_int32_t);
+ if (si == NULL)
+ return API_ENOMEM;
+
+ return (platform_sys_info(si)) ? 0 : API_ENODEV;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_udelay(unsigned long *udelay)
+ */
+static int API_udelay(va_list ap)
+{
+ unsigned long *d;
+
+ if ((d = (unsigned long *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ udelay(*d);
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_get_timer(unsigned long *current, unsigned long *base)
+ */
+static int API_get_timer(va_list ap)
+{
+ unsigned long *base, *cur;
+
+ cur = (unsigned long *)va_arg(ap, u_int32_t);
+ if (cur == NULL)
+ return API_EINVAL;
+
+ base = (unsigned long *)va_arg(ap, u_int32_t);
+ if (base == NULL)
+ return API_EINVAL;
+
+ *cur = get_timer(*base);
+ return 0;
+}
+
+
+/*****************************************************************************
+ *
+ * pseudo signature:
+ *
+ * int API_dev_enum(struct device_info *)
+ *
+ *
+ * cookies uniqely identify the previously enumerated device instance and
+ * provide a hint for what to inspect in current enum iteration:
+ *
+ * - net: ð_device struct address from list pointed to by eth_devices
+ *
+ * - storage: block_dev_desc_t struct address from &ide_dev_desc[n],
+ * &scsi_dev_desc[n] and similar tables
+ *
+ ****************************************************************************/
+
+static int API_dev_enum(va_list ap)
+{
+ struct device_info *di;
+
+ /* arg is ptr to the device_info struct we are going to fill out */
+ di = (struct device_info *)va_arg(ap, u_int32_t);
+ if (di == NULL)
+ return API_EINVAL;
+
+ if (di->cookie == NULL) {
+ /* start over - clean up enumeration */
+ dev_enum_reset(); /* XXX shouldn't the name contain 'stor'? */
+ debugf("RESTART ENUM\n");
+
+ /* net device enumeration first */
+ if (dev_enum_net(di))
+ return 0;
+ }
+
+ /*
+ * The hidden assumption is there can only be one active network
+ * device and it is identified upon enumeration (re)start, so there's
+ * no point in trying to find network devices in other cases than the
+ * (re)start and hence the 'next' device can only be storage
+ */
+ if (!dev_enum_storage(di))
+ /* make sure we mark there are no more devices */
+ di->cookie = NULL;
+
+ return 0;
+}
+
+
+static int API_dev_open(va_list ap)
+{
+ struct device_info *di;
+ int err = 0;
+
+ /* arg is ptr to the device_info struct */
+ di = (struct device_info *)va_arg(ap, u_int32_t);
+ if (di == NULL)
+ return API_EINVAL;
+
+ /* Allow only one consumer of the device at a time */
+ if (di->state == DEV_STA_OPEN)
+ return API_EBUSY;
+
+ if (di->cookie == NULL)
+ return API_ENODEV;
+
+ if (di->type & DEV_TYP_STOR)
+ err = dev_open_stor(di->cookie);
+
+ else if (di->type & DEV_TYP_NET)
+ err = dev_open_net(di->cookie);
+ else
+ err = API_ENODEV;
+
+ if (!err)
+ di->state = DEV_STA_OPEN;
+
+ return err;
+}
+
+
+static int API_dev_close(va_list ap)
+{
+ struct device_info *di;
+ int err = 0;
+
+ /* arg is ptr to the device_info struct */
+ di = (struct device_info *)va_arg(ap, u_int32_t);
+ if (di == NULL)
+ return API_EINVAL;
+
+ if (di->state == DEV_STA_CLOSED)
+ return 0;
+
+ if (di->cookie == NULL)
+ return API_ENODEV;
+
+ if (di->type & DEV_TYP_STOR)
+ err = dev_close_stor(di->cookie);
+
+ else if (di->type & DEV_TYP_NET)
+ err = dev_close_net(di->cookie);
+ else
+ /*
+ * In case of unknown device we cannot change its state, so
+ * only return error code
+ */
+ err = API_ENODEV;
+
+ if (!err)
+ di->state = DEV_STA_CLOSED;
+
+ return err;
+}
+
+
+/*
+ * Notice: this is for sending network packets only, as U-Boot does not
+ * support writing to storage at the moment (12.2007)
+ *
+ * pseudo signature:
+ *
+ * int API_dev_write(
+ * struct device_info *di,
+ * void *buf,
+ * int *len
+ * )
+ *
+ * buf: ptr to buffer from where to get the data to send
+ *
+ * len: length of packet to be sent (in bytes)
+ *
+ */
+static int API_dev_write(va_list ap)
+{
+ struct device_info *di;
+ void *buf;
+ int *len;
+ int err = 0;
+
+ /* 1. arg is ptr to the device_info struct */
+ di = (struct device_info *)va_arg(ap, u_int32_t);
+ if (di == NULL)
+ return API_EINVAL;
+
+ /* XXX should we check if device is open? i.e. the ->state ? */
+
+ if (di->cookie == NULL)
+ return API_ENODEV;
+
+ /* 2. arg is ptr to buffer from where to get data to write */
+ buf = (void *)va_arg(ap, u_int32_t);
+ if (buf == NULL)
+ return API_EINVAL;
+
+ /* 3. arg is length of buffer */
+ len = (int *)va_arg(ap, u_int32_t);
+ if (len == NULL)
+ return API_EINVAL;
+ if (*len <= 0)
+ return API_EINVAL;
+
+ if (di->type & DEV_TYP_STOR)
+ /*
+ * write to storage is currently not supported by U-Boot:
+ * no storage device implements block_write() method
+ */
+ return API_ENODEV;
+
+ else if (di->type & DEV_TYP_NET)
+ err = dev_write_net(di->cookie, buf, *len);
+ else
+ err = API_ENODEV;
+
+ return err;
+}
+
+
+/*
+ * pseudo signature:
+ *
+ * int API_dev_read(
+ * struct device_info *di,
+ * void *buf,
+ * size_t *len,
+ * unsigned long *start
+ * size_t *act_len
+ * )
+ *
+ * buf: ptr to buffer where to put the read data
+ *
+ * len: ptr to length to be read
+ * - network: len of packet to read (in bytes)
+ * - storage: # of blocks to read (can vary in size depending on define)
+ *
+ * start: ptr to start block (only used for storage devices, ignored for
+ * network)
+ *
+ * act_len: ptr to where to put the len actually read
+ */
+static int API_dev_read(va_list ap)
+{
+ struct device_info *di;
+ void *buf;
+ lbasize_t *len_stor, *act_len_stor;
+ lbastart_t *start;
+ int *len_net, *act_len_net;
+
+ /* 1. arg is ptr to the device_info struct */
+ di = (struct device_info *)va_arg(ap, u_int32_t);
+ if (di == NULL)
+ return API_EINVAL;
+
+ /* XXX should we check if device is open? i.e. the ->state ? */
+
+ if (di->cookie == NULL)
+ return API_ENODEV;
+
+ /* 2. arg is ptr to buffer from where to put the read data */
+ buf = (void *)va_arg(ap, u_int32_t);
+ if (buf == NULL)
+ return API_EINVAL;
+
+ if (di->type & DEV_TYP_STOR) {
+ /* 3. arg - ptr to var with # of blocks to read */
+ len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+ if (!len_stor)
+ return API_EINVAL;
+ if (*len_stor <= 0)
+ return API_EINVAL;
+
+ /* 4. arg - ptr to var with start block */
+ start = (lbastart_t *)va_arg(ap, u_int32_t);
+
+ /* 5. arg - ptr to var where to put the len actually read */
+ act_len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+ if (!act_len_stor)
+ return API_EINVAL;
+
+ *act_len_stor = dev_read_stor(di->cookie, buf, *len_stor, *start);
+
+ } else if (di->type & DEV_TYP_NET) {
+
+ /* 3. arg points to the var with length of packet to read */
+ len_net = (int *)va_arg(ap, u_int32_t);
+ if (!len_net)
+ return API_EINVAL;
+ if (*len_net <= 0)
+ return API_EINVAL;
+
+ /* 4. - ptr to var where to put the len actually read */
+ act_len_net = (int *)va_arg(ap, u_int32_t);
+ if (!act_len_net)
+ return API_EINVAL;
+
+ *act_len_net = dev_read_net(di->cookie, buf, *len_net);
+
+ } else
+ return API_ENODEV;
+
+ return 0;
+}
+
+
+/*
+ * pseudo signature:
+ *
+ * int API_env_get(const char *name, char **value)
+ *
+ * name: ptr to name of env var
+ */
+static int API_env_get(va_list ap)
+{
+ char *name, **value;
+
+ if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+ if ((value = (char **)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ *value = getenv(name);
+
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_env_set(const char *name, const char *value)
+ *
+ * name: ptr to name of env var
+ *
+ * value: ptr to value to be set
+ */
+static int API_env_set(va_list ap)
+{
+ char *name, *value;
+
+ if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+ if ((value = (char *)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ setenv(name, value);
+
+ return 0;
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_env_enum(const char *last, char **next)
+ *
+ * last: ptr to name of env var found in last iteration
+ */
+static int API_env_enum(va_list ap)
+{
+ int i, n;
+ char *last, **next;
+
+ last = (char *)va_arg(ap, u_int32_t);
+
+ if ((next = (char **)va_arg(ap, u_int32_t)) == NULL)
+ return API_EINVAL;
+
+ if (last == NULL)
+ /* start over */
+ *next = ((char *)env_get_addr(0));
+ else {
+ *next = last;
+
+ for (i = 0; env_get_char(i) != '\0'; i = n + 1) {
+ for (n = i; env_get_char(n) != '\0'; ++n) {
+ if (n >= CFG_ENV_SIZE) {
+ /* XXX shouldn't we set *next = NULL?? */
+ return 0;
+ }
+ }
+
+ if (envmatch((uchar *)last, i) < 0)
+ continue;
+
+ /* try to get next name */
+ i = n + 1;
+ if (env_get_char(i) == '\0') {
+ /* no more left */
+ *next = NULL;
+ return 0;
+ }
+
+ *next = ((char *)env_get_addr(i));
+ return 0;
+ }
+ }
+
+ return 0;
+}
+
+static cfp_t calls_table[API_MAXCALL] = { NULL, };
+
+/*
+ * The main syscall entry point - this is not reentrant, only one call is
+ * serviced until finished.
+ *
+ * e.g. syscall(1, int *, u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+ *
+ * call: syscall number
+ *
+ * retval: points to the return value placeholder, this is the place the
+ * syscall puts its return value, if NULL the caller does not
+ * expect a return value
+ *
+ * ... syscall arguments (variable number)
+ *
+ * returns: 0 if the call not found, 1 if serviced
+ */
+int syscall(int call, int *retval, ...)
+{
+ va_list ap;
+ int rv;
+
+ if (call < 0 || call >= calls_no || calls_table[call] == NULL) {
+ debugf("invalid call #%d\n", call);
+ return 0;
+ }
+
+ if (calls_table[call] == NULL) {
+ debugf("syscall #%d does not have a handler\n", call);
+ return 0;
+ }
+
+ va_start(ap, retval);
+ rv = calls_table[call](ap);
+ if (retval != NULL)
+ *retval = rv;
+
+ return 1;
+}
+
+void api_init(void)
+{
+ struct api_signature *sig = NULL;
+
+ /* TODO put this into linker set one day... */
+ calls_table[API_RSVD] = NULL;
+ calls_table[API_GETC] = &API_getc;
+ calls_table[API_PUTC] = &API_putc;
+ calls_table[API_TSTC] = &API_tstc;
+ calls_table[API_PUTS] = &API_puts;
+ calls_table[API_RESET] = &API_reset;
+ calls_table[API_GET_SYS_INFO] = &API_get_sys_info;
+ calls_table[API_UDELAY] = &API_udelay;
+ calls_table[API_GET_TIMER] = &API_get_timer;
+ calls_table[API_DEV_ENUM] = &API_dev_enum;
+ calls_table[API_DEV_OPEN] = &API_dev_open;
+ calls_table[API_DEV_CLOSE] = &API_dev_close;
+ calls_table[API_DEV_READ] = &API_dev_read;
+ calls_table[API_DEV_WRITE] = &API_dev_write;
+ calls_table[API_ENV_GET] = &API_env_get;
+ calls_table[API_ENV_SET] = &API_env_set;
+ calls_table[API_ENV_ENUM] = &API_env_enum;
+ calls_no = API_MAXCALL;
+
+ debugf("API initialized with %d calls\n", calls_no);
+
+ dev_stor_init();
+
+ /*
+ * Produce the signature so the API consumers can find it
+ */
+ sig = malloc(sizeof(struct api_signature));
+ if (sig == NULL) {
+ printf("API: could not allocate memory for the signature!\n");
+ return;
+ }
+
+ debugf("API sig @ 0x%08x\n", sig);
+ memcpy(sig->magic, API_SIG_MAGIC, 8);
+ sig->version = API_SIG_VERSION;
+ sig->syscall = &syscall;
+ sig->checksum = 0;
+ sig->checksum = crc32(0, (unsigned char *)sig,
+ sizeof(struct api_signature));
+ debugf("syscall entry: 0x%08x\n", sig->syscall);
+}
+
+void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long size,
+ int flags)
+{
+ int i;
+
+ if (!si->mr || !size || (flags == 0))
+ return;
+
+ /* find free slot */
+ for (i = 0; i < si->mr_no; i++)
+ if (si->mr[i].flags == 0) {
+ /* insert new mem region */
+ si->mr[i].start = start;
+ si->mr[i].size = size;
+ si->mr[i].flags = flags;
+ return;
+ }
+}
+
+#endif /* CONFIG_API */
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_API)
+
+#include <common.h>
+#include <net.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DEBUG
+#undef DEBUG
+
+#if !defined(CONFIG_NET_MULTI)
+#error "API/net is currently only available for platforms with CONFIG_NET_MULTI"
+#endif
+
+#ifdef DEBUG
+#define debugf(fmt, args...) do { printf("%s(): ", __func__); printf(fmt, ##args); } while (0)
+#else
+#define debugf(fmt, args...)
+#endif
+
+#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
+
+
+static int dev_valid_net(void *cookie)
+{
+ return ((void *)eth_get_dev() == cookie) ? 1 : 0;
+}
+
+int dev_open_net(void *cookie)
+{
+ if (!dev_valid_net(cookie))
+ return API_ENODEV;
+
+ if (eth_init(gd->bd) < 0)
+ return API_EIO;
+
+ return 0;
+}
+
+int dev_close_net(void *cookie)
+{
+ if (!dev_valid_net(cookie))
+ return API_ENODEV;
+
+ eth_halt();
+ return 0;
+}
+
+/*
+ * There can only be one active eth interface at a time - use what is
+ * currently set to eth_current
+ */
+int dev_enum_net(struct device_info *di)
+{
+ struct eth_device *eth_current = eth_get_dev();
+
+ di->type = DEV_TYP_NET;
+ di->cookie = (void *)eth_current;
+ if (di->cookie == NULL)
+ return 0;
+
+ memcpy(di->di_net.hwaddr, eth_current->enetaddr, 6);
+
+ debugf("device found, returning cookie 0x%08x\n",
+ (u_int32_t)di->cookie);
+
+ return 1;
+}
+
+int dev_write_net(void *cookie, void *buf, int len)
+{
+ /* XXX verify that cookie points to a valid net device??? */
+
+ return eth_send(buf, len);
+}
+
+int dev_read_net(void *cookie, void *buf, int len)
+{
+ /* XXX verify that cookie points to a valid net device??? */
+
+ return eth_receive(buf, len);
+}
+
+#endif /* CONFIG_API */
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * This file contains routines that fetch data from ARM-dependent sources
+ * (bd_info etc.)
+ *
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_API)
+
+#include <linux/types.h>
+#include <api_public.h>
+
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+
+#include "api_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Important notice: handling of individual fields MUST be kept in sync with
+ * include/asm-arm/u-boot.h and include/asm-arm/global_data.h, so any changes
+ * need to reflect their current state and layout of structures involved!
+ */
+int platform_sys_info(struct sys_info *si)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ platform_set_mr(si, gd->bd->bi_dram[i].start,
+ gd->bd->bi_dram[i].size, MR_ATTR_DRAM);
+
+ return 1;
+}
+
+#endif /* CONFIG_API */
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * This file contains routines that fetch data from PowerPC-dependent sources
+ * (bd_info etc.)
+ *
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_API)
+
+#include <linux/types.h>
+#include <api_public.h>
+
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+
+#include "api_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Important notice: handling of individual fields MUST be kept in sync with
+ * include/asm-ppc/u-boot.h and include/asm-ppc/global_data.h, so any changes
+ * need to reflect their current state and layout of structures involved!
+ */
+int platform_sys_info(struct sys_info *si)
+{
+ si->clk_bus = gd->bus_clk;
+ si->clk_cpu = gd->cpu_clk;
+
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \
+ defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#define bi_bar bi_immr_base
+#elif defined(CONFIG_MPC5xxx)
+#define bi_bar bi_mbar_base
+#elif defined(CONFIG_MPC83XX)
+#define bi_bar bi_immrbar
+#elif defined(CONFIG_MPC8220)
+#define bi_bar bi_mbar_base
+#endif
+
+#if defined(bi_bar)
+ si->bar = gd->bd->bi_bar;
+#undef bi_bar
+#else
+ si->bar = NULL;
+#endif
+
+ platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
+ platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
+ platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
+
+ return 1;
+}
+
+#endif /* CONFIG_API */
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _API_PRIVATE_H_
+#define _API_PRIVATE_H_
+
+void api_init(void);
+void platform_set_mr(struct sys_info *, unsigned long, unsigned long, int);
+int platform_sys_info(struct sys_info *);
+
+void dev_enum_reset(void);
+int dev_enum_storage(struct device_info *);
+int dev_enum_net(struct device_info *);
+
+int dev_open_stor(void *);
+int dev_open_net(void *);
+int dev_close_stor(void *);
+int dev_close_net(void *);
+
+lbasize_t dev_read_stor(void *, void *, lbasize_t, lbastart_t);
+int dev_read_net(void *, void *, int);
+int dev_write_net(void *, void *, int);
+
+void dev_stor_init(void);
+
+#endif /* _API_PRIVATE_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_API)
+
+#include <common.h>
+#include <api_public.h>
+
+#define DEBUG
+#undef DEBUG
+
+#ifdef DEBUG
+#define debugf(fmt, args...) do { printf("%s(): ", __func__); printf(fmt, ##args); } while (0)
+#else
+#define debugf(fmt, args...)
+#endif
+
+#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
+
+
+#define ENUM_IDE 0
+#define ENUM_USB 1
+#define ENUM_SCSI 2
+#define ENUM_MMC 3
+#define ENUM_MAX 4
+
+struct stor_spec {
+ int max_dev;
+ int enum_started;
+ int enum_ended;
+ int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
+ char name[4];
+};
+
+static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
+
+
+void dev_stor_init(void)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+ specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
+ specs[ENUM_IDE].enum_started = 0;
+ specs[ENUM_IDE].enum_ended = 0;
+ specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
+ specs[ENUM_IDE].name = "ide";
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_USB)
+ specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
+ specs[ENUM_USB].enum_started = 0;
+ specs[ENUM_USB].enum_ended = 0;
+ specs[ENUM_USB].type = DEV_TYP_STOR | DT_STOR_USB;
+ specs[ENUM_USB].name = "usb";
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
+ specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
+ specs[ENUM_SCSI].enum_started = 0;
+ specs[ENUM_SCSI].enum_ended = 0;
+ specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
+ specs[ENUM_SCSI].name = "scsi";
+#endif
+}
+
+/*
+ * Finds next available device in the storage group
+ *
+ * type: storage group type - ENUM_IDE, ENUM_SCSI etc.
+ *
+ * first: if 1 the first device in the storage group is returned (if
+ * exists), if 0 the next available device is searched
+ *
+ * more: returns 0/1 depending if there are more devices in this group
+ * available (for future iterations)
+ *
+ * returns: 0/1 depending if device found in this iteration
+ */
+static int dev_stor_get(int type, int first, int *more, struct device_info *di)
+{
+ int found = 0;
+ *more = 0;
+
+ int i;
+
+ block_dev_desc_t *dd;
+
+ if (first) {
+ di->cookie = (void *)get_dev(specs[type].name, 0);
+ found = 1;
+
+ } else {
+ for (i = 0; i < specs[type].max_dev; i++)
+ if (di->cookie == (void *)get_dev(specs[type].name, i)) {
+ /* previous cookie found -- advance to the
+ * next device, if possible */
+
+ if (++i >= specs[type].max_dev) {
+ /* out of range, no more to enum */
+ di->cookie = NULL;
+ break;
+ }
+
+ di->cookie = (void *)get_dev(specs[type].name, i);
+ found = 1;
+
+ /* provide hint if there are more devices in
+ * this group to enumerate */
+ if ((i + 1) < specs[type].max_dev)
+ *more = 1;
+
+ break;
+ }
+ }
+
+ if (found) {
+ di->type = specs[type].type;
+
+ if (di->cookie != NULL) {
+ dd = (block_dev_desc_t *)di->cookie;
+ if (dd->type == DEV_TYPE_UNKNOWN) {
+ debugf("device instance exists, but is not active..");
+ found = 0;
+ } else {
+ di->di_stor.block_count = dd->lba;
+ di->di_stor.block_size = dd->blksz;
+ }
+ }
+
+ } else
+ di->cookie = NULL;
+
+ return found;
+}
+
+
+/*
+ * returns: ENUM_IDE, ENUM_USB etc. based on block_dev_desc_t
+ */
+static int dev_stor_type(block_dev_desc_t *dd)
+{
+ int i, j;
+
+ for (i = ENUM_IDE; i < ENUM_MAX; i++)
+ for (j = 0; j < specs[i].max_dev; j++)
+ if (dd == get_dev(specs[i].name, j))
+ return i;
+
+ return ENUM_MAX;
+}
+
+
+/*
+ * returns: 0/1 whether cookie points to some device in this group
+ */
+static int dev_is_stor(int type, struct device_info *di)
+{
+ return (dev_stor_type(di->cookie) == type) ? 1 : 0;
+}
+
+
+static int dev_enum_stor(int type, struct device_info *di)
+{
+ int found = 0, more = 0;
+
+ debugf("called, type %d\n", type);
+
+ /*
+ * Formulae for enumerating storage devices:
+ * 1. if cookie (hint from previous enum call) is NULL we start again
+ * with enumeration, so return the first available device, done.
+ *
+ * 2. if cookie is not NULL, check if it identifies some device in
+ * this group:
+ *
+ * 2a. if cookie is a storage device from our group (IDE, USB etc.),
+ * return next available (if exists) in this group
+ *
+ * 2b. if it isn't device from our group, check if such devices were
+ * ever enumerated before:
+ * - if not, return the first available device from this group
+ * - else return 0
+ */
+
+ if (di->cookie == NULL) {
+
+ debugf("group%d - enum restart\n", type);
+
+ /*
+ * 1. Enumeration (re-)started: take the first available
+ * device, if exists
+ */
+ found = dev_stor_get(type, 1, &more, di);
+ specs[type].enum_started = 1;
+
+ } else if (dev_is_stor(type, di)) {
+
+ debugf("group%d - enum continued for the next device\n", type);
+
+ if (specs[type].enum_ended) {
+ debugf("group%d - nothing more to enum!\n", type);
+ return 0;
+ }
+
+ /* 2a. Attempt to take a next available device in the group */
+ found = dev_stor_get(type, 0, &more, di);
+
+ } else {
+
+ if (specs[type].enum_ended) {
+ debugf("group %d - already enumerated, skipping\n", type);
+ return 0;
+ }
+
+ debugf("group%d - first time enum\n", type);
+
+ if (specs[type].enum_started == 0) {
+ /*
+ * 2b. If enumerating devices in this group did not
+ * happen before, it means the cookie pointed to a
+ * device frome some other group (another storage
+ * group, or network); in this case try to take the
+ * first available device from our group
+ */
+ specs[type].enum_started = 1;
+
+ /*
+ * Attempt to take the first device in this group:
+ *'first element' flag is set
+ */
+ found = dev_stor_get(type, 1, &more, di);
+
+ } else {
+ errf("group%d - out of order iteration\n", type);
+ found = 0;
+ more = 0;
+ }
+ }
+
+ /*
+ * If there are no more devices in this group, consider its
+ * enumeration finished
+ */
+ specs[type].enum_ended = (!more) ? 1 : 0;
+
+ if (found)
+ debugf("device found, returning cookie 0x%08x\n",
+ (u_int32_t)di->cookie);
+ else
+ debugf("no device found\n");
+
+ return found;
+}
+
+void dev_enum_reset(void)
+{
+ int i;
+
+ for (i = 0; i < ENUM_MAX; i ++) {
+ specs[i].enum_started = 0;
+ specs[i].enum_ended = 0;
+ }
+}
+
+int dev_enum_storage(struct device_info *di)
+{
+ int i;
+
+ /*
+ * check: ide, usb, scsi, mmc
+ */
+ for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
+ if (dev_enum_stor(i, di))
+ return 1;
+ }
+
+ return 0;
+}
+
+static int dev_stor_is_valid(int type, block_dev_desc_t *dd)
+{
+ int i;
+
+ for (i = 0; i < specs[type].max_dev; i++)
+ if (dd == get_dev(specs[type].name, i))
+ if (dd->type != DEV_TYPE_UNKNOWN)
+ return 1;
+
+ return 0;
+}
+
+
+int dev_open_stor(void *cookie)
+{
+ int type = dev_stor_type(cookie);
+
+ if (type == ENUM_MAX)
+ return API_ENODEV;
+
+ if (dev_stor_is_valid(type, (block_dev_desc_t *)cookie))
+ return 0;
+
+ return API_ENODEV;
+}
+
+
+int dev_close_stor(void *cookie)
+{
+ /*
+ * Not much to do as we actually do not alter storage devices upon
+ * close
+ */
+ return 0;
+}
+
+
+static int dev_stor_index(block_dev_desc_t *dd)
+{
+ int i, type;
+
+ type = dev_stor_type(dd);
+ for (i = 0; i < specs[type].max_dev; i++)
+ if (dd == get_dev(specs[type].name, i))
+ return i;
+
+ return (specs[type].max_dev);
+}
+
+
+lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
+{
+ int type;
+ block_dev_desc_t *dd = (block_dev_desc_t *)cookie;
+
+ if ((type = dev_stor_type(dd)) == ENUM_MAX)
+ return 0;
+
+ if (!dev_stor_is_valid(type, dd))
+ return 0;
+
+ if ((dd->block_read) == NULL) {
+ debugf("no block_read() for device 0x%08x\n");
+ return 0;
+ }
+
+ return (dd->block_read(dev_stor_index(dd), start, len, buf));
+}
+
+#endif /* CONFIG_API */
--- /dev/null
+#
+# (C) Copyright 2007 Semihalf
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(ARCH),ppc)
+LOAD_ADDR = 0x40000
+endif
+
+#ifeq ($(ARCH),arm)
+#LOAD_ADDR = 0xc100000
+#endif
+
+include $(TOPDIR)/config.mk
+
+ELF += demo
+BIN += demo.bin
+
+#CFLAGS += -v
+
+COBJS := $(ELF:=.o)
+SOBJS := crt0.o
+ifeq ($(ARCH),ppc)
+SOBJS += ppcstring.o
+endif
+
+LIB = $(obj)libglue.a
+LIBCOBJS= glue.o crc32.o ctype.o string.o vsprintf.o libgenwrap.o
+
+LIBOBJS = $(addprefix $(obj),$(SOBJS) $(LIBCOBJS))
+
+SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(SOBJS:.o=.S)
+OBJS := $(addprefix $(obj),$(COBJS))
+ELF := $(addprefix $(obj),$(ELF))
+BIN := $(addprefix $(obj),$(BIN))
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+CPPFLAGS += -I..
+
+all: $(obj).depend $(OBJS) $(LIB) $(BIN) $(ELF)
+
+#########################################################################
+$(LIB): $(obj).depend $(LIBOBJS)
+ $(AR) $(ARFLAGS) $@ $(LIBOBJS)
+
+$(ELF):
+$(obj)%: $(obj)%.o $(LIB)
+ $(LD) $(obj)crt0.o -Ttext $(LOAD_ADDR) \
+ -o $@ $< $(LIB) \
+ -L$(gcclibdir) -lgcc
+
+$(BIN):
+$(obj)%.bin: $(obj)%
+ $(OBJCOPY) -O binary $< $@ 2>/dev/null
+
+$(obj)crc32.c:
+ @rm -f $(obj)crc32.c
+ ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
+
+$(obj)ctype.c:
+ @rm -f $(obj)ctype.c
+ ln -s $(src)../lib_generic/ctype.c $(obj)ctype.c
+
+$(obj)string.c:
+ @rm -f $(obj)string.c
+ ln -s $(src)../lib_generic/string.c $(obj)string.c
+
+$(obj)vsprintf.c:
+ @rm -f $(obj)vsprintf.c
+ ln -s $(src)../lib_generic/vsprintf.c $(obj)vsprintf.c
+
+ifeq ($(ARCH),ppc)
+$(obj)ppcstring.S:
+ @rm -f $(obj)ppcstring.S
+ ln -s $(src)../lib_ppc/ppcstring.S $(obj)ppcstring.S
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#if defined(CONFIG_PPC)
+
+ .text
+
+ .globl _start
+_start:
+ b main
+
+
+ .globl syscall
+syscall:
+ lis %r11, syscall_ptr@ha
+ addi %r11, %r11, syscall_ptr@l
+ lwz %r11, 0(%r11)
+ mtctr %r11
+ bctr
+
+
+ .globl syscall_ptr
+syscall_ptr:
+ .align 4
+ .long 0
+#else
+#error No support for this arch!
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include "glue.h"
+
+#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
+
+void test_dump_si(struct sys_info *);
+void test_dump_di(int);
+void test_dump_sig(struct api_signature *);
+
+char buf[2048];
+
+#define WAIT_SECS 5
+
+int main(int argc, char *argv[])
+{
+ int rv = 0;
+ int h, i, j;
+ int devs_no;
+ struct api_signature *sig = NULL;
+ ulong start, now;
+ struct device_info *di;
+
+ if (!api_search_sig(&sig))
+ return -1;
+
+ syscall_ptr = sig->syscall;
+ if (syscall_ptr == NULL)
+ return -2;
+
+ if (sig->version > API_SIG_VERSION)
+ return -3;
+
+ printf("API signature found @%x\n", sig);
+ test_dump_sig(sig);
+
+ printf("\n*** Consumer API test ***\n");
+ printf("syscall ptr 0x%08x@%08x\n", syscall_ptr, &syscall_ptr);
+
+ /* console activities */
+ ub_putc('B');
+
+ printf("*** Press any key to continue ***\n");
+ printf("got char 0x%x\n", ub_getc());
+
+ /* system info */
+ test_dump_si(ub_get_sys_info());
+
+ /* timing */
+ printf("\n*** Timing - wait a couple of secs ***\n");
+ start = ub_get_timer(0);
+ printf("\ntime: start %lu\n\n", start);
+ for (i = 0; i < WAIT_SECS; i++)
+ for (j = 0; j < 1000; j++)
+ ub_udelay(1000); /* wait 1 ms */
+
+ /* this is the number of milliseconds that passed from ub_get_timer(0) */
+ now = ub_get_timer(start);
+ printf("\ntime: now %lu\n\n", now);
+
+ /* enumerate devices */
+ printf("\n*** Enumerate devices ***\n");
+ devs_no = ub_dev_enum();
+
+ printf("Number of devices found: %d\n", devs_no);
+ if (devs_no == 0)
+ return -1;
+
+
+ printf("\n*** Show devices ***\n");
+ for (i = 0; i < devs_no; i++) {
+ test_dump_di(i);
+ printf("\n");
+ }
+
+ printf("\n*** Operations on devices ***\n");
+
+ /* test opening a device already opened */
+ h = 0;
+ if ((rv = ub_dev_open(h)) != 0) {
+ errf("open device %d error %d\n", h, rv);
+ return -1;
+ }
+ if ((rv = ub_dev_open(h)) != 0)
+ errf("open device %d error %d\n", h, rv);
+
+ ub_dev_close(h);
+
+ /* test storage */
+ printf("Trying storage devices...\n");
+ for (i = 0; i < devs_no; i++) {
+ di = ub_dev_get(i);
+
+ if (di->type & DEV_TYP_STOR)
+ break;
+
+ }
+ if (i == devs_no)
+ printf("No storage devices available\n");
+ else {
+ if ((rv = ub_dev_open(i)) != 0)
+ errf("open device %d error %d\n", i, rv);
+ else if ((rv = ub_dev_read(i, &buf, 200, 20)) != 0)
+ errf("could not read from device %d, error %d\n", i, rv);
+
+ ub_dev_close(i);
+ }
+
+ /* test networking */
+ printf("Trying network devices...\n");
+ for (i = 0; i < devs_no; i++) {
+ di = ub_dev_get(i);
+
+ if (di->type == DEV_TYP_NET)
+ break;
+
+ }
+ if (i == devs_no)
+ printf("No network devices available\n");
+ else {
+ if ((rv = ub_dev_open(i)) != 0)
+ errf("open device %d error %d\n", i, rv);
+ else if ((rv = ub_dev_send(i, &buf, 2048)) != 0)
+ errf("could not send to device %d, error %d\n", i, rv);
+
+ ub_dev_close(i);
+ }
+
+ if (ub_dev_close(h) != 0)
+ errf("could not close device %d\n", h);
+
+ printf("\n*** Env vars ***\n");
+
+ printf("ethact = %s\n", ub_env_get("ethact"));
+ printf("old fileaddr = %s\n", ub_env_get("fileaddr"));
+ ub_env_set("fileaddr", "deadbeef");
+ printf("new fileaddr = %s\n", ub_env_get("fileaddr"));
+
+ const char *env = NULL;
+
+ while ((env = ub_env_enum(env)) != NULL)
+ printf("%s = %s\n", env, ub_env_get(env));
+
+ /* reset */
+ ub_reset();
+ printf("\nHmm, reset returned...?!\n");
+
+ return rv;
+}
+
+void test_dump_sig(struct api_signature *sig)
+{
+ printf("signature:\n");
+ printf(" version\t= %d\n", sig->version);
+ printf(" checksum\t= 0x%08x\n", sig->checksum);
+ printf(" sc entry\t= 0x%08x\n", sig->syscall);
+}
+
+void test_dump_si(struct sys_info *si)
+{
+ int i;
+
+ printf("sys info:\n");
+ printf(" clkbus\t= 0x%08x\n", si->clk_bus);
+ printf(" clkcpu\t= 0x%08x\n", si->clk_cpu);
+ printf(" bar\t\t= 0x%08x\n", si->bar);
+
+ printf("---\n");
+ for (i = 0; i < si->mr_no; i++) {
+ if (si->mr[i].flags == 0)
+ break;
+
+ printf(" start\t= 0x%08lx\n", si->mr[i].start);
+ printf(" size\t= 0x%08lx\n", si->mr[i].size);
+
+ switch(si->mr[i].flags & 0x000F) {
+ case MR_ATTR_FLASH:
+ printf(" type FLASH\n");
+ break;
+ case MR_ATTR_DRAM:
+ printf(" type DRAM\n");
+ break;
+ case MR_ATTR_SRAM:
+ printf(" type SRAM\n");
+ break;
+ default:
+ printf(" type UNKNOWN\n");
+ }
+ printf("---\n");
+ }
+}
+
+static char * test_stor_typ(int type)
+{
+ if (type & DT_STOR_IDE)
+ return "IDE";
+
+ if (type & DT_STOR_SCSI)
+ return "SCSI";
+
+ if (type & DT_STOR_USB)
+ return "USB";
+
+ if (type & DT_STOR_MMC);
+ return "MMC";
+
+ return "Unknown";
+}
+
+void test_dump_di(int handle)
+{
+ int i;
+ struct device_info *di = ub_dev_get(handle);
+
+ printf("device info (%d):\n", handle);
+ printf(" cookie\t= 0x%08x\n", (uint32_t)di->cookie);
+ printf(" type\t\t= 0x%08x\n", di->type);
+
+ if (di->type == DEV_TYP_NET) {
+ printf(" hwaddr\t= ");
+ for (i = 0; i < 6; i++)
+ printf("%02x ", di->di_net.hwaddr[i]);
+
+ printf("\n");
+
+ } else if (di->type & DEV_TYP_STOR) {
+ printf(" type\t\t= %s\n", test_stor_typ(di->type));
+ printf(" blk size\t\t= %d\n", di->di_stor.block_size);
+ printf(" blk count\t\t= %d\n", di->di_stor.block_count);
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include "glue.h"
+
+static int valid_sig(struct api_signature *sig)
+{
+ uint32_t checksum;
+ struct api_signature s;
+
+ if (sig == NULL)
+ return 0;
+ /*
+ * Clear the checksum field (in the local copy) so as to calculate the
+ * CRC with the same initial contents as at the time when the sig was
+ * produced
+ */
+ s = *sig;
+ s.checksum = 0;
+
+ checksum = crc32(0, (unsigned char *)&s, sizeof(struct api_signature));
+
+ if (checksum != sig->checksum)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Searches for the U-Boot API signature
+ *
+ * returns 1/0 depending on found/not found result
+ */
+int api_search_sig(struct api_signature **sig) {
+
+ unsigned char *sp;
+
+ if (sig == NULL)
+ return 0;
+
+ sp = (unsigned char *)API_SEARCH_START;
+
+ while ((sp + (int)API_SIG_MAGLEN) < (unsigned char *)API_SEARCH_END) {
+ if (!memcmp(sp, API_SIG_MAGIC, API_SIG_MAGLEN)) {
+ *sig = (struct api_signature *)sp;
+ if (valid_sig(*sig))
+ return 1;
+ }
+ sp += API_SIG_MAGLEN;
+ }
+
+ *sig = NULL;
+ return 0;
+}
+
+/****************************************
+ *
+ * console
+ *
+ ****************************************/
+
+int ub_getc(void)
+{
+ int c;
+
+ if (!syscall(API_GETC, NULL, (uint32_t)&c))
+ return -1;
+
+ return c;
+}
+
+int ub_tstc(void)
+{
+ int t;
+
+ if (!syscall(API_TSTC, NULL, (uint32_t)&t))
+ return -1;
+
+ return t;
+}
+
+void ub_putc(char c)
+{
+ syscall(API_PUTC, NULL, (uint32_t)&c);
+}
+
+void ub_puts(const char *s)
+{
+ syscall(API_PUTS, NULL, (uint32_t)s);
+}
+
+/****************************************
+ *
+ * system
+ *
+ ****************************************/
+
+void ub_reset(void)
+{
+ syscall(API_RESET, NULL);
+}
+
+#define MR_MAX 5
+static struct mem_region mr[MR_MAX];
+static struct sys_info si;
+
+struct sys_info * ub_get_sys_info(void)
+{
+ int err = 0;
+
+ memset(&si, 0, sizeof(struct sys_info));
+ si.mr = mr;
+ si.mr_no = MR_MAX;
+ memset(&mr, 0, sizeof(mr));
+
+ if (!syscall(API_GET_SYS_INFO, &err, (u_int32_t)&si))
+ return NULL;
+
+ return ((err) ? NULL : &si);
+}
+
+/****************************************
+ *
+ * timing
+ *
+ ****************************************/
+
+void ub_udelay(unsigned long usec)
+{
+ syscall(API_UDELAY, NULL, &usec);
+}
+
+unsigned long ub_get_timer(unsigned long base)
+{
+ unsigned long cur;
+
+ if (!syscall(API_GET_TIMER, NULL, &cur, &base))
+ return 0;
+
+ return cur;
+}
+
+
+/****************************************************************************
+ *
+ * devices
+ *
+ * Devices are identified by handles: numbers 0, 1, 2, ..., MAX_DEVS-1
+ *
+ ***************************************************************************/
+
+#define MAX_DEVS 6
+
+static struct device_info devices[MAX_DEVS];
+
+struct device_info * ub_dev_get(int i)
+{
+ return ((i < 0 || i >= MAX_DEVS) ? NULL : &devices[i]);
+}
+
+/*
+ * Enumerates the devices: fills out device_info elements in the devices[]
+ * array.
+ *
+ * returns: number of devices found
+ */
+int ub_dev_enum(void)
+{
+ struct device_info *di;
+ int n = 0;
+
+ memset(&devices, 0, sizeof(struct device_info) * MAX_DEVS);
+ di = &devices[0];
+
+ if (!syscall(API_DEV_ENUM, NULL, di))
+ return 0;
+
+ while (di->cookie != NULL) {
+
+ if (++n >= MAX_DEVS)
+ break;
+
+ /* take another device_info */
+ di++;
+
+ /* pass on the previous cookie */
+ di->cookie = devices[n - 1].cookie;
+
+ if (!syscall(API_DEV_ENUM, NULL, di))
+ return 0;
+ }
+
+ return n;
+}
+
+/*
+ * handle: 0-based id of the device
+ *
+ * returns: 0 when OK, err otherwise
+ */
+int ub_dev_open(int handle)
+{
+ struct device_info *di;
+ int err = 0;
+
+ if (handle < 0 || handle >= MAX_DEVS)
+ return API_EINVAL;
+
+ di = &devices[handle];
+
+ if (!syscall(API_DEV_OPEN, &err, di))
+ return -1;
+
+ return err;
+}
+
+int ub_dev_close(int handle)
+{
+ struct device_info *di;
+
+ if (handle < 0 || handle >= MAX_DEVS)
+ return API_EINVAL;
+
+ di = &devices[handle];
+ if (!syscall(API_DEV_CLOSE, NULL, di))
+ return -1;
+
+ return 0;
+}
+
+/*
+ *
+ * Validates device for read/write, it has to:
+ *
+ * - have sane handle
+ * - be opened
+ *
+ * returns: 0/1 accordingly
+ */
+static int dev_valid(int handle)
+{
+ if (handle < 0 || handle >= MAX_DEVS)
+ return 0;
+
+ if (devices[handle].state != DEV_STA_OPEN)
+ return 0;
+
+ return 1;
+}
+
+static int dev_stor_valid(int handle)
+{
+ if (!dev_valid(handle))
+ return 0;
+
+ if (!(devices[handle].type & DEV_TYP_STOR))
+ return 0;
+
+ return 1;
+}
+
+int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start)
+{
+ struct device_info *di;
+ lbasize_t act_len;
+ int err = 0;
+
+ if (!dev_stor_valid(handle))
+ return API_ENODEV;
+
+ di = &devices[handle];
+ if (!syscall(API_DEV_READ, &err, di, buf, &len, &start, &act_len))
+ return -1;
+
+ if (err)
+ return err;
+
+ if (act_len != len)
+ return API_EIO;
+
+ return 0;
+}
+
+static int dev_net_valid(int handle)
+{
+ if (!dev_valid(handle))
+ return 0;
+
+ if (devices[handle].type != DEV_TYP_NET)
+ return 0;
+
+ return 1;
+}
+
+int ub_dev_recv(int handle, void *buf, int len)
+{
+ struct device_info *di;
+ int err = 0, act_len;
+
+ if (!dev_net_valid(handle))
+ return API_ENODEV;
+
+ di = &devices[handle];
+ if (!syscall(API_DEV_READ, &err, di, buf, &len, &act_len))
+ return -1;
+
+ if (err)
+ return -1;
+
+ return act_len;
+}
+
+int ub_dev_send(int handle, void *buf, int len)
+{
+ struct device_info *di;
+ int err = 0;
+
+ if (!dev_net_valid(handle))
+ return API_ENODEV;
+
+ di = &devices[handle];
+ if (!syscall(API_DEV_WRITE, &err, di, buf, &len))
+ return -1;
+
+ return err;
+}
+
+/****************************************
+ *
+ * env vars
+ *
+ ****************************************/
+
+char * ub_env_get(const char *name)
+{
+ char *value;
+
+ if (!syscall(API_ENV_GET, NULL, (uint32_t)name, (uint32_t)&value))
+ return NULL;
+
+ return value;
+}
+
+void ub_env_set(const char *name, char *value)
+{
+ syscall(API_ENV_SET, NULL, (uint32_t)name, (uint32_t)value);
+}
+
+
+static char env_name[256];
+
+const char * ub_env_enum(const char *last)
+{
+ const char *env, *str;
+ int i;
+
+ env = NULL;
+
+ /*
+ * It's OK to pass only the name piece as last (and not the whole
+ * 'name=val' string), since the API_ENUM_ENV call uses envmatch()
+ * internally, which handles such case
+ */
+ if (!syscall(API_ENV_ENUM, NULL, (uint32_t)last, (uint32_t)&env))
+ return NULL;
+
+ if (!env)
+ /* no more env. variables to enumerate */
+ return NULL;
+
+ /* next enumerated env var */
+ memset(env_name, 0, 256);
+ for (i = 0, str = env; *str != '=' && *str != '\0';)
+ env_name[i++] = *str++;
+
+ env_name[i] = '\0';
+
+ return env_name;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * This is the header file for conveniency wrapper routines (API glue)
+ */
+
+#ifndef _API_GLUE_H_
+#define _API_GLUE_H_
+
+#define API_SEARCH_START (255 * 1024 * 1024) /* start at 1MB below top RAM */
+#define API_SEARCH_END (256 * 1024 * 1024 - 1) /* ...and search to the end */
+
+int syscall(int, int *, ...);
+void * syscall_ptr;
+
+int api_search_sig(struct api_signature **sig);
+
+/*
+ * ub_ library calls are part of the application, not U-Boot code! They are
+ * front-end wrappers that are used by the consumer application: they prepare
+ * arguments for particular syscall and jump to the low level syscall()
+ */
+
+/* console */
+int ub_getc(void);
+int ub_tstc(void);
+void ub_putc(char c);
+void ub_puts(const char *s);
+
+/* system */
+void ub_reset(void);
+struct sys_info * ub_get_sys_info(void);
+
+/* time */
+void ub_udelay(unsigned long);
+unsigned long ub_get_timer(unsigned long);
+
+/* env vars */
+char * ub_env_get(const char *name);
+void ub_env_set(const char *name, char *value);
+const char * ub_env_enum(const char *last);
+
+/* devices */
+int ub_dev_enum(void);
+int ub_dev_open(int handle);
+int ub_dev_close(int handle);
+int ub_dev_read(int handle, void *buf,
+ lbasize_t len, lbastart_t start);
+int ub_dev_send(int handle, void *buf, int len);
+int ub_dev_recv(int handle, void *buf, int len);
+struct device_info * ub_dev_get(int);
+
+#endif /* _API_GLUE_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * This is is a set of wrappers/stubs that allow to use certain routines from
+ * U-Boot's lib_generic in the standalone app. This way way we can re-use
+ * existing code e.g. operations on strings and similar.
+ *
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include "glue.h"
+
+/*
+ * printf() and vprintf() are stolen from u-boot/common/console.c
+ */
+void printf (const char *fmt, ...)
+{
+ va_list args;
+ uint i;
+ char printbuffer[256];
+
+ va_start (args, fmt);
+
+ /* For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vsprintf (printbuffer, fmt, args);
+ va_end (args);
+
+ /* Print the string */
+ ub_puts (printbuffer);
+}
+
+void vprintf (const char *fmt, va_list args)
+{
+ uint i;
+ char printbuffer[256];
+
+ /* For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vsprintf (printbuffer, fmt, args);
+
+ /* Print the string */
+ ub_puts (printbuffer);
+}
+
+void putc (const char c)
+{
+ ub_putc(c);
+}
+
+void udelay(unsigned long usec)
+{
+ ub_udelay(usec);
+}
+
+void do_reset (void)
+{
+ ub_reset();
+}
+
+void *malloc(size_t len)
+{
+ return NULL;
+}
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright 2007
+ * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+long int fixed_sdram(void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+
+ if ((uint)&gur->porpllsr != 0xe00e0000) {
+ printf("immap size error %x\n",&gur->porpllsr);
+ }
+ printf ("Board: ATUM8548\n");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+ ecm->eedr = 0xffffffff; /* Clear ecm errors */
+ ecm->eeer = 0xffffffff; /* Enable ecm errors */
+
+ return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_SPD_EEPROM)
+ puts("spd_sdram\n");
+ dram_size = spd_sdram ();
+#else
+ puts("fixed_sdram\n");
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ puts(" DDR: ");
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++) {
+ printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
+ *p = 0xaaaaaaaa;
+ }
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+int first_free_busno=0;
+
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+ devdisr, io_sel, host_agent);
+
+ /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
+ gur->clkocr |= MPC85xx_ATUM_CLKOCR;
+
+ if (io_sel & 1) {
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ printf (" eTSEC1 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ printf (" eTSEC2 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ printf (" eTSEC3 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
+ printf (" eTSEC4 is in sgmii mode.\n");
+ }
+
+#ifdef CONFIG_PCIE1
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 5);
+ int pcie_configured = io_sel & 6;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE1 connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+#ifdef CFG_PCIE1_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE1_MEM_BASE2,
+ CFG_PCIE1_MEM_PHYS2,
+ CFG_PCIE1_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf(" PCIE1 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE1: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+
+ uint pci_agent = (host_agent == 6);
+ uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ (uint)pci
+ );
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI1 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+ } else {
+ printf (" PCI1: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci2_hose;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ pci_set_region(hose->regions + 1,
+ CFG_PCI2_MEM_BASE,
+ CFG_PCI2_MEM_PHYS,
+ CFG_PCI2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ pci_set_region(hose->regions + 2,
+ CFG_PCI2_IO_BASE,
+ CFG_PCI2_IO_PHYS,
+ CFG_PCI2_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI2 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI2;
+#endif
+}
+
+
+int last_stage_init(void)
+{
+ int ic = icache_status ();
+ printf ("icache_status: %d\n", ic);
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci2", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
--- /dev/null
+#
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# atum8548 board
+# TEXT_BASE = 0xfff80000
+# TEXT_BASE = 0xfffff000
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
--- /dev/null
+/*
+ * Copyright 2007
+ * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define LAWAR_TRGT_PCI1 0x00000000
+#define LAWAR_TRGT_PCI2 0x00100000
+#define LAWAR_TRGT_PCIE 0x00200000
+#define LAWAR_TRGT_DDR 0x00f00000
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long (2f-1f)/16
+
+1:
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, guarded
+ * Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, MAS2_G)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, MAS2_G)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, MAS2_G)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, MAS2_G)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /* TLB 1 Initializations */
+ /*
+ * TLB 0, 1: 128M Non-cacheable, guarded
+ * 0xf8000000 128M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x4000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x4000000, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 2: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCI1/PCIE 8,9,a,b
+ */
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 3, 4: 512M Non-cacheable, guarded
+ * 0xc0000000 1G PCI2
+ */
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 1M PCI1 IO
+ * 0xe210_0000 1M PCI2 IO
+ * 0xe300_0000 1M PCIe IO
+ */
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+2:
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
+ * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
+ * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+
+ .long (4f-3f)/8
+3:
+ .long 0
+ .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN
+
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+
+ .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+
+ .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+4:
+ entry_end
--- /dev/null
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/atum8548/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/atum8548/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4*1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8*1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12*1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 0: 16M Non-cacheable, guarded
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+ .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM)
/*
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1, 9, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 8, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1, 9, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe200_0000 16M PCI1 IO
* 0xe300_0000 16M PCI2 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 7: 1M Non-cacheable, guarded
* 0xf8000000 1M CADMUS registers
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB0 16K Cacheable, guarded
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCIE 8,9,a,b
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe100_0000 255M PCI IO range
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#ifdef CFG_LBC_CACHE_BASE
/*
* TLB 5: 64M Cacheable, non-guarded
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
2:
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCI1/PCIE 8,9,a,b
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#ifdef CFG_RIO_MEM_PHYS
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe210_0000 1M PCI2 IO
* 0xe300_0000 1M PCIe IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 7: 64M Non-cacheable, guarded
* 0xf8000000 64M CADMUS registers, relocated L2SRAM
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
2:
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe200_0000 16M PCI1 IO
* 0xe300_0000 16M PCI2 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 7: 1M Non-cacheable, guarded
* 0xf8000000 1M CADMUS registers
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+ .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM)
/*
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1, 9, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 8, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1, 9, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end
*/
#include <common.h>
+#include <asm/io.h>
+
#include "bcsr.h"
void enable_8568mds_duart()
bcsr[7] |= 0x01;
}
+
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void)
+{
+ volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ /* Turn off UCC1 & UCC2 */
+ out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
+ out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
+
+ /* Mode is RGMII, all bits clear */
+ out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
+ BCSR_UCC2_MODE_MSK));
+
+ /* Turn UCC1 & UCC2 on */
+ out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
+ out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
+}
+#endif
7 Flash write protect
*/
+#define BCSR_UCC1_GETH_EN (0x1 << 7)
+#define BCSR_UCC2_GETH_EN (0x1 << 7)
+#define BCSR_UCC1_MODE_MSK (0x3 << 4)
+#define BCSR_UCC2_MODE_MSK (0x3 << 0)
+
/*BCSR Utils functions*/
void enable_8568mds_duart(void);
void disable_8568mds_flash_write(void);
void enable_8568mds_qe_mdio(void);
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void);
+#endif
+
#endif /* __BCSR_H_ */
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
#define entry_start \
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* TLB 1 Initializations */
/*
* 0xff000000 16M FLASH (upper half)
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x1000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x1000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x1000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x1000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLBe 1: 16M Non-cacheable, guarded
* 0xfe000000 16M FLASH (lower half)
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLBe 2: 1G Non-cacheable, guarded
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLBe 3: 64M Non-cacheable, guarded
* 0xe200_0000 8M PCI1 IO
* 0xe280_0000 8M PCIe IO
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLBe 4: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLBe 5: 256K Non-cacheable, guarded
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
+ .long FSL_BOOKE_MAS2(CFG_BCSR_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_BCSR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
2:
entry_end
{1, 31, 2, 0, 3}, /* GTX125 */
{4, 6, 3, 0, 2}, /* MDIO */
{4, 5, 1, 0, 2}, /* MDC */
+
+ /* UART1 */
+ {2, 0, 1, 0, 2}, /* UART_SOUT1 */
+ {2, 1, 1, 0, 2}, /* UART_RTS1 */
+ {2, 2, 2, 0, 2}, /* UART_CTS1 */
+ {2, 3, 2, 0, 2}, /* UART_SIN1 */
+
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};
enable_8568mds_duart();
enable_8568mds_flash_write();
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+ reset_8568mds_uccs();
+#endif
#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
enable_8568mds_qe_mdio();
#endif
.long 0x0a /* the following data table uses a few of 16 TLB entries */
- .long TLB1_MAS0(1,1,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,1,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#if defined(CFG_FLASH_PORT_WIDTH_16)
- .long TLB1_MAS0(1,2,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
- .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1,3,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
- .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,2,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1,3,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x400000,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x400000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#else
- .long TLB1_MAS0(1,2,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1,3,0)
- .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,2,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1,3,0)
+ .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(0,0)
+ .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#endif
#if !defined(CONFIG_SPD_EEPROM)
- .long TLB1_MAS0(1,4,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1,5,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
- .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
- .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,4,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1,5,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x4000000,0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x4000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#else
- .long TLB1_MAS0(1,4,0)
- .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1,5,0)
- .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,4,0)
+ .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(0,0)
+ .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1,5,0)
+ .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(0,0)
+ .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#endif
- .long TLB1_MAS0(1,6,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS0(1,6,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
- .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,(MAS2_I|MAS2_G))
#else
- .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,0)
#endif
- .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(1,7,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long FSL_BOOKE_MAS0(1,7,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
- .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
#else
- .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
#endif
- .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(1,8,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,8,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(1,9,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
- .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,9,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long FSL_BOOKE_MAS2(CFG_BCSR,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_BCSR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- .long TLB1_MAS0(1,15,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,15,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#else
- .long TLB1_MAS0(1,15,0)
- .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,15,0)
+ .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(0,0)
+ .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xfc000000 64M FLASH (8,16,32 or 64 MB)
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM)
/*
* Likely it needs to be increased by two for these entries.
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xfc000000 64M FLASH (8,16,32 or 64 MB)
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM)
/*
* Likely it needs to be increased by two for these entries.
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end
--- /dev/null
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8560 board
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := init.o
+#SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# sbc8548 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
--- /dev/null
+/*
+ * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xe4010000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff800000 16M TLB for 8MB FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 3: 256M Cacheable, non-guarded
+ * 0x0 256M DDR SDRAM
+ */
+ #if !defined(CONFIG_SPD_EEPROM)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+ #endif
+
+ /*
+ * TLB 4: 64M Non-cacheable, guarded
+ * 0xe0000000 1M CCSRBAR
+ * 0xe2000000 16M PCI1 IO
+ */
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 5: 64M Cacheable, non-guarded
+ * 0xf0000000 64M LBC SDRAM
+ */
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ /*
+ * TLB 6: 16M Cacheable, non-guarded
+ * 0xf8000000 1M 7-segment LED display
+ * 0xf8100000 1M User switches
+ * 0xf8300000 1M Board revision
+ * 0xf8b00000 1M EEPROM
+ */
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x0fff_ffff DDR 256M
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
+ * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+ #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+ #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+ #define LAWBAR0 0
+ #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long 4
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ entry_end
--- /dev/null
+/*
+ * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram (void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+
+ printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
+ (volatile)(*(u_char *)CFG_BD_REV) >> 4);
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ /*
+ * Fix CPU2 errata: A core hang possible while executing a
+ * msync instruction and a snoopable transaction from an I/O
+ * master tagged to make quick forward progress is present.
+ */
+ ecm->eebpcr |= (1 << 16);
+
+ /*
+ * Hack TSEC 3 and 4 IO voltages.
+ */
+ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
+
+ ecm->eedr = 0xffffffff; /* clear ecm errors */
+ ecm->eeer = 0xffffffff; /* enable ecm errors */
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & 0x0f) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or3 = CFG_OR3_PRELIM;
+ asm("msync");
+
+ lbc->br3 = CFG_BR3_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8548 uses "new" 15-16 style addressing.
+ */
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed_sdram init -- doesn't use serial presence detect.
+ * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #define CFG_DDR_CONTROL 0xc300c000
+
+ volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+
+ ddr->cs0_bnds = 0x0000007f;
+ ddr->cs1_bnds = 0x008000ff;
+ ddr->cs2_bnds = 0x00000000;
+ ddr->cs3_bnds = 0x00000000;
+ ddr->cs0_config = 0x80010101;
+ ddr->cs1_config = 0x80010101;
+ ddr->cs2_config = 0x00000000;
+ ddr->cs3_config = 0x00000000;
+ ddr->ext_refrec = 0x00000000;
+ ddr->timing_cfg_0 = 0x00220802;
+ ddr->timing_cfg_1 = 0x38377322;
+ ddr->timing_cfg_2 = 0x0fa044C7;
+ ddr->sdram_cfg = 0x4300C000;
+ ddr->sdram_cfg_2 = 0x24401000;
+ ddr->sdram_mode = 0x23C00542;
+ ddr->sdram_mode_2 = 0x00000000;
+ ddr->sdram_interval = 0x05080100;
+ ddr->sdram_md_cntl = 0x00000000;
+ ddr->sdram_data_init = 0x00000000;
+ ddr->sdram_clk_cntl = 0x03800000;
+ asm("sync;isync;msync");
+ udelay(500);
+
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
+
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_sbc8548_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+static struct pci_controller pci1_hose = {
+ config_table: pci_sbc8548_config_table};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno=0;
+
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+ struct pci_config_table *table;
+
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+
+ /* relocate config table pointers */
+ hose->config_table = \
+ (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
+ for (table = hose->config_table; table && table->vendor; table++)
+ table->config_device += gd->reloc_off;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+#ifdef CONFIG_PCIX_CHECK
+ if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+ }
+#endif
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
+}
+
+int last_stage_init(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/sbc8548/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/sbc8548/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ drivers/net/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
/* TLB for CCSRBAR (IMMR) */
- .long TLB1_MAS0(1,1,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,1,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
/* TLB for Local Bus stuff, just map the whole 512M */
/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
- .long TLB1_MAS0(1,2,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,2,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(1,3,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,3,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM)
- .long TLB1_MAS0(1,4,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1,5,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
- .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
- .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,4,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1,5,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#else
- .long TLB1_MAS0(1,4,0)
- .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1,5,0)
- .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,4,0)
+ .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(0,0)
+ .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1,5,0)
+ .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(0,0)
+ .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#endif
- .long TLB1_MAS0(1,6,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long FSL_BOOKE_MAS0(1,6,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
- .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
#else
- .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
#endif
- .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(1,7,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,7,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- .long TLB1_MAS0(1,15,0)
- .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,15,0)
+ .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#else
- .long TLB1_MAS0(1,15,0)
- .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1,15,0)
+ .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long FSL_BOOKE_MAS2(0,0)
+ .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end
};
/*-------------------------------------------------------------------------+
- | pci_init_board (Called from pci_init() in drivers/pci.c)
+ | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
|
| Init the PCI part of the SolidCard III
|
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* !!!!! !!!!!
* !!!!! Next type definition was coming from original !!!!!
- * !!!!! status LED driver drivers/status_led.c and !!!!!
- * !!!!! should exported for using here. !!!!!
+ * !!!!! status LED driver drivers/misc/status_led.c !!!!!
+ * !!!!! and should be exported for using it here. !!!!!
* !!!!! !!!!!
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 7: 16K Non-cacheable, guarded
* 0xfc000000 16K Configuration Latch register
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
+ .long FSL_BOOKE_MAS2(CFG_LBC_LCLDEVS_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_LBC_LCLDEVS_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM)
/*
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1, 9, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 8, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(1, 9, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xfc000000 6M4 FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), \
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), \
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe200_0000 16M PCI1 IO
* 0xe300_0000 16M PCI2 IO
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 256M Non-cacheable, guarded
* 0xfb000000 Configuration Latch register (one word)
* 0xfc000000 Up to 64M flash
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_OPTION_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_OPTION_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end
/*
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
+
extern int usb_cpu_init(void);
#ifdef CONFIG_PS2MULT
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+ .long FSL_BOOKE_MAS0(0, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+ .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+ .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 1, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+ .long FSL_BOOKE_MAS0(1, 0, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x4000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 2, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 3, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 4, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 5, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 6, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
+ .long FSL_BOOKE_MAS0(1, 7, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+ .long FSL_BOOKE_MAS0(1, 8, 0)
+ .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end
#include <command.h>
#include <miiphy.h>
-#ifdef CONFIG_TERSE_MII
-/*
- * Display values from last command.
- */
-uint last_op;
-uint last_addr;
-uint last_data;
-uint last_reg;
-
-/*
- * MII device/info/read/write
- *
- * Syntax:
- * mii device {devname}
- * mii info {addr}
- * mii read {addr} {reg}
- * mii write {addr} {reg} {data}
- */
-int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- char op;
- unsigned char addr, reg;
- unsigned short data;
- int rcode = 0;
- char *devname;
-
- if (argc < 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
-#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
- mii_init ();
-#endif
-
- /*
- * We use the last specified parameters, unless new ones are
- * entered.
- */
- op = last_op;
- addr = last_addr;
- data = last_data;
- reg = last_reg;
-
- if ((flag & CMD_FLAG_REPEAT) == 0) {
- op = argv[1][0];
- if (argc >= 3)
- addr = simple_strtoul (argv[2], NULL, 16);
- if (argc >= 4)
- reg = simple_strtoul (argv[3], NULL, 16);
- if (argc >= 5)
- data = simple_strtoul (argv[4], NULL, 16);
- }
-
- /* use current device */
- devname = miiphy_get_current_dev();
-
- /*
- * check device/read/write/list.
- */
- if (op == 'i') {
- unsigned char j, start, end;
- unsigned int oui;
- unsigned char model;
- unsigned char rev;
-
- /*
- * Look for any and all PHYs. Valid addresses are 0..31.
- */
- if (argc >= 3) {
- start = addr; end = addr + 1;
- } else {
- start = 0; end = 31;
- }
-
- for (j = start; j < end; j++) {
- if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
- printf ("PHY 0x%02X: "
- "OUI = 0x%04X, "
- "Model = 0x%02X, "
- "Rev = 0x%02X, "
- "%3dbase%s, %s\n",
- j, oui, model, rev,
- miiphy_speed (devname, j),
- miiphy_is_1000base_x (devname, j)
- ? "X" : "T",
- (miiphy_duplex (devname, j) == FULL)
- ? "FDX" : "HDX");
- }
- }
- } else if (op == 'r') {
- if (miiphy_read (devname, addr, reg, &data) != 0) {
- puts ("Error reading from the PHY\n");
- rcode = 1;
- } else {
- printf ("%04X\n", data & 0x0000FFFF);
- }
- } else if (op == 'w') {
- if (miiphy_write (devname, addr, reg, data) != 0) {
- puts ("Error writing to the PHY\n");
- rcode = 1;
- }
- } else if (op == 'd') {
- if (argc == 2)
- miiphy_listdev ();
- else
- miiphy_set_current_dev (argv[2]);
- } else {
- printf ("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
- /*
- * Save the parameters for repeats.
- */
- last_op = op;
- last_addr = addr;
- last_data = data;
- last_reg = reg;
-
- return rcode;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- mii, 5, 1, do_mii,
- "mii - MII utility commands\n",
- "device - list available devices\n"
- "mii device <devname> - set current device\n"
- "mii info <addr> - display MII PHY info\n"
- "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
- "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
-);
-
-#else /* ! CONFIG_TERSE_MII ================================================= */
-
typedef struct _MII_reg_desc_t {
ushort regno;
char * name;
int rcode = 0;
char *devname;
+ if (argc < 2) {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x)
mii_init ();
#endif
"mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
"Addr and/or reg may be ranges, e.g. 2-7.\n"
);
-
-#endif /* CONFIG_TERSE_MII */
/************************************************************************
************************************************************************/
-static int envmatch (uchar *, int);
-
/*
* Table with supported baudrates (defined in config_xyz.h)
*/
* If the names match, return the index for the value2, else NULL.
*/
-static int
-envmatch (uchar *s1, int i2)
+int envmatch (uchar *s1, int i2)
{
while (*s1 == env_get_char(i2++))
size_t start, size_t len,
size_t * retlen, u_char * buf);
-/* info for NAND chips, defined in drivers/nand/nand.c */
+/* info for NAND chips, defined in drivers/mtd/nand/nand.c */
extern nand_info_t nand_info[];
/* references to names in env_common.c */
#include <fdt_support.h>
#include <exports.h>
+#ifdef CONFIG_QE
+#include "../drivers/qe/qe.h"
+#endif
/*
* Global data (for the gd->bd)
*/
#endif
}
}
+
+#ifdef CONFIG_QE
+/*
+ * If a QE firmware has been uploaded, then add the 'firmware' node under
+ * the 'qe' node.
+ */
+void fdt_fixup_qe_firmware(void *fdt)
+{
+ struct qe_firmware_info *qe_fw_info;
+ int node, ret;
+
+ qe_fw_info = qe_get_firmware_info();
+ if (!qe_fw_info)
+ return;
+
+ node = fdt_path_offset(fdt, "/qe");
+ if (node < 0)
+ return;
+
+ /* We assume the node doesn't exist yet */
+ node = fdt_add_subnode(fdt, node, "firmware");
+ if (node < 0)
+ return;
+
+ ret = fdt_setprop(fdt, node, "extended-modes",
+ &qe_fw_info->extended_modes, sizeof(u64));
+ if (ret < 0)
+ goto error;
+
+ ret = fdt_setprop_string(fdt, node, "id", qe_fw_info->id);
+ if (ret < 0)
+ goto error;
+
+ ret = fdt_setprop(fdt, node, "virtual-traps", qe_fw_info->vtraps,
+ sizeof(qe_fw_info->vtraps));
+ if (ret < 0)
+ goto error;
+
+ return;
+
+error:
+ fdt_del_node(fdt, node);
+}
+#endif
+
#endif
#define MAX_DELAY_STOP_STR 32
-static int parse_line (char *, char *[]);
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
static int abortboot(int);
#endif
*/
int readline (const char *const prompt)
{
+ return readline_into_buffer(prompt, console_buffer);
+}
+
+
+int readline_into_buffer (const char *const prompt, char * buffer)
+{
+ char *p = buffer;
+ char * p_buf = p;
#ifdef CONFIG_CMDLINE_EDITING
- char *p = console_buffer;
unsigned int len=MAX_CMDBUF_SIZE;
int rc;
static int initted = 0;
rc = cread_line(prompt, p, &len);
return rc < 0 ? rc : len;
#else
- char *p = console_buffer;
int n = 0; /* buffer index */
int plen = 0; /* prompt length */
int col; /* output column cnt */
case '\n':
*p = '\0';
puts ("\r\n");
- return (p - console_buffer);
+ return (p - p_buf);
case '\0': /* nul */
continue;
case 0x03: /* ^C - break */
- console_buffer[0] = '\0'; /* discard input */
+ p_buf[0] = '\0'; /* discard input */
return (-1);
case 0x15: /* ^U - erase line */
puts (erase_seq);
--col;
}
- p = console_buffer;
+ p = p_buf;
n = 0;
continue;
case 0x17: /* ^W - erase word */
- p=delete_char(console_buffer, p, &col, &n, plen);
+ p=delete_char(p_buf, p, &col, &n, plen);
while ((n > 0) && (*p != ' ')) {
- p=delete_char(console_buffer, p, &col, &n, plen);
+ p=delete_char(p_buf, p, &col, &n, plen);
}
continue;
case 0x08: /* ^H - backspace */
case 0x7F: /* DEL - backspace */
- p=delete_char(console_buffer, p, &col, &n, plen);
+ p=delete_char(p_buf, p, &col, &n, plen);
continue;
default:
/* if auto completion triggered just continue */
*p = '\0';
if (cmd_auto_complete(prompt, console_buffer, &n, &col)) {
- p = console_buffer + n; /* reset */
+ p = p_buf + n; /* reset */
continue;
}
#endif
static unsigned char num_lock = 0;
static unsigned char caps_lock = 0;
static unsigned char scroll_lock = 0;
+static unsigned char ctrl = 0;
static unsigned char leds __attribute__ ((aligned (0x4)));
/* test if a character is in the queue */
static int usb_kbd_testc(void)
{
+#ifdef CFG_USB_EVENT_POLL
+ usb_event_poll();
+#endif
if(usb_in_pointer==usb_out_pointer)
return(0); /* no data */
else
else /* non shifted */
keycode=usb_kbd_numkey[scancode-0x1e];
}
+
+ if (ctrl)
+ keycode = scancode - 0x3;
+
if(pressed==1) {
if(scancode==NUM_LOCK) {
num_lock=~num_lock;
return 1;
}
res=0;
+
+ switch (new[0]) {
+ case 0x0: /* No combo key pressed */
+ ctrl = 0;
+ break;
+ case 0x01: /* Left Ctrl pressed */
+ case 0x10: /* Right Ctrl pressed */
+ ctrl = 1;
+ break;
+ }
+
for (i = 2; i < 8; i++) {
if (old[i] > 3 && memscan(&new[2], old[i], 6) == &new[8]) {
res|=usb_kbd_translate(old[i],new[0],0);
if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback,
(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
printf("can't register RX callback!\n");
- return 0;
+ return -1;
}
if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback,
(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
printf("can't register TX callback!\n");
- return 0;
+ return -1;
}
npe_set_mac_address(dev);
if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
printf("can't enable port!\n");
- return 0;
+ return -1;
}
p_npe->active = 1;
- return 1;
+ return 0;
}
#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
#ifdef CONFIG_QE
- do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
"bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
+ "brg-frequency", bd->bi_busfreq / 2, 1);
+ fdt_fixup_qe_firmware(blob);
#endif
#ifdef CFG_NS16550
ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize * 1024 * 1024)
&& ram_tlb_index < 16) {
- mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
- mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
- mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 0, 0, 0));
- mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+ mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+ mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+ mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
+ mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR)));
asm volatile("isync;msync;tlbwe;isync");
- debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
- debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
- debug("DDR: MAS2=0x%08x\n",
- TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 0, 0, 0));
+ debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+ debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+ debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
debug("DDR: MAS3=0x%08x\n",
- TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+ FSL_BOOKE_MAS3(ram_tlb_address, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR)));
ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
ram_tlb_index++;
*/
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
- li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r2, L1CFG0
+ andi. r2, r2, 0x1ff
+ /* cache size * 1024 / (2 * L1 line size) */
+ slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
mtctr r2
li r0,0
1:
/* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
- li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r4,L1CFG0
+ andi. r4,r4,0x1ff
+ slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: icbi r0,r3
dcbi r0,r3
if (efis->actual_phy_addr == -1) {
printf ("Unable to discover phy!\n");
- return 0;
+ return -1;
}
#else
efis->actual_phy_addr = -1;
efis->initialized = 1;
- return 1;
+ return 0;
}
}
/*
- * drivers/pci.c skips every host bridge but the 405GP since it could
+ * drivers/pci/pci.c skips every host bridge but the 405GP since it could
* be set as an Adapter.
*
* I (Andrew May) don't know what we should do here, but I don't want
* Startup Code (reset vector)
*
* do important init only if we don't start from RAM!
- * - relocate armboot to ram
+ * - relocate armboot to RAM
* - setup stack
* - jump to second stage
*/
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
-#endif
+#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
/****************************************************************************/
reset:
- mrs r0,cpsr /* set the cpu to SVC32 mode */
+ mrs r0,cpsr /* set the CPU to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
orr r0,r0,#0x13
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
- * not when booting from ram!
+ * not when booting from RAM!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit /* we do sys-critical inits */
-#endif
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
+#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
+#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
#undef OSCR
#undef OWER
#undef OIER
-#endif
+#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */
#ifdef CONFIG_PXA250
#undef RCSR
#undef CCCR
-#endif
+#endif /* CONFIG_PXA250 */
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
#ifdef CONFIG_CPU_MONAHANS
# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif
+# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */
# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif
-#else /* ! CONFIG_CPU_MONAHANS */
+# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */
+#else /* !CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
cpuspeed: .word CFG_CPUSPEED
-#else
+#else /* !CFG_CPUSPEED */
#error "You have to define CFG_CPUSPEED!!"
-#endif
+#endif /* CFG_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/* takes care the CP15 update has taken place */
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
-#else
+#else /* CONFIG_CPU_MONAHANS */
/* Step 1 - Enable CP6 permission */
mrc p15, 0, r1, c15, c1, 0 @ read CPAR
orr r1, r1, #0x40
ldr r1, =CKENB
ldr r2, =(CKENB_6_IRQ)
str r2, [r1]
-#endif
+#endif /* !CONFIG_CPU_MONAHANS */
/* set clock speed */
#ifdef CONFIG_CPU_MONAHANS
ldr r0, =ACCR
ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
str r1, [r0]
-#else /* ! CONFIG_CPU_MONAHANS */
+#else /* !CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
ldr r0, CC_BASE
ldr r1, cpuspeed
bl do_fiq /* effiction fiq_save_user_regs */
irq_restore_user_regs
-#else
+#else /* !CONFIG_USE_IRQ */
.align 5
irq:
bad_save_user_regs
bl do_fiq
-#endif
+#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
/* */
int usb_cpu_init_fail(void)
{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS)
+ UHCHR |= UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+ UHCHR |= UHCHR_SSEP2;
+#endif
+ UHCHR |= UHCHR_SSEP1;
+ UHCHR |= UHCHR_SSE;
+
return 0;
}
--- /dev/null
+Building U-Boot
+---------------
+
+The ATUM8548 code is known to build using ELDK 4.1.
+
+$ make ATUM8548_config
+Configuring for ATUM8548 board...
+$ make
+
+Using Flash
+-----------
+
+The ATUM8548 board has one flash bank, of 128MB in size (2^23 = 0x08000000).
+
+The BDI2000 commands for copying u-boot into flash are
+as follows:
+
+ erase 0xFFF80000 0x4000 0x20
+ prog 0xfff80000 uboot.bin bin
+
+Booting Linux
+-------------
+
+U-boot/kermit commands for booting linux via NFS - assumming the proper
+bootargs are set - are as follows:
+
+ tftp 1000000 uImage.atum
+ tftp c00000 mpc8548atum.dtb
+ bootm 1000000 - c00000
Notes on the the generic USB-OHCI driver
========================================
-This driver (drivers/usb_ohci.[ch]) is the result of the merge of
+This driver (drivers/usb/usb_ohci.[ch]) is the result of the merge of
various existing OHCI drivers that were basically identical beside
cpu/board dependant initalization. This initalization has been moved
into cpu/board directories and are called via the hooks below.
board/modnet50/flash.c .. flash routines
board/modnet50/modnet50.c .. some board init stuff
-drivers/netarm_eth.c .. ethernet driver for the NET+50 CPU
-drivers/netarm_eth.h .. header for ethernet driver
+drivers/net/netarm_eth.c .. ethernet driver for the NET+50 CPU
+drivers/net/netarm_eth.h .. header for ethernet driver
include/configs/modnet50.h .. configuration file for ModNET50
nand write.jffs2 addr ofs|partition size
Like `write', but blocks that are marked bad are skipped and the
- is written to the next block instead. This allows writing writing
+ data is written to the next block instead. This allows writing
a JFFS2 image, as long as the image is short enough to fit even
after skipping the bad blocks. Compact images, such as those
produced by mkfs.jffs2 should work well, but loading an image copied
--- /dev/null
+Wind River SBC8548 reference board
+===========================
+
+Copyright 2007, Embedded Specialties, Inc.
+Copyright 2007 Wind River Systemes, Inc.
+-----------------------------
+
+1. Building U-Boot
+------------------
+The SBC8548 code is known to build using ELDK 4.1.
+
+ $ make sbc8548_config
+ Configuring for sbc8548 board...
+
+ $ make
+
+
+2. Switch and Jumper Settings
+-----------------------------
+All Jumpers & Switches are in their default positions. Please refer to
+the board documentation for details. Some settings control CPU voltages
+and settings may change with board revisions.
+
+3. Known limitations
+--------------------
+PCI:
+ The code to support PCI is currently disabled and has not been verified.
/*
- * drivers/nand/nand_util.c
+ * drivers/mtd/nand/nand_util.c
*
* Copyright (C) 2006 by Weiss-Electronic GmbH.
* All rights reserved.
if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
printf("Error: Cannot reset ethernet controller.\n");
- return 0;
+ return -1;
}
#ifdef CONFIG_TULIP_SELECT_MEDIA
send_setup_frame(dev, bis);
- return 1;
+ return 0;
}
static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
static int eepro100_init (struct eth_device *dev, bd_t * bis)
{
- int i, status = 0;
+ int i, status = -1;
int tx_cur;
struct descriptor *ias_cmd, *cfg_cmd;
goto Done;
}
- status = 1;
+ status = 0;
Done:
return status;
#endif
if (!macb_phy_init(macb))
- return 0;
+ return -1;
/* Enable TX and RX */
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
- return 1;
+ return 0;
}
static void macb_halt(struct eth_device *netdev)
}
dp83902a_recv(&pbuf[0], len);
- /*Just pass it to the upper layer*/
+ /* Just pass it to the upper layer */
NetReceive(&pbuf[0], len);
}
}
void eth_halt() {
-
PRINTK("### eth_halt\n");
if(initialized)
dp83902a_stop();
}
int eth_rx() {
-dp83902a_poll();
-return 1;
+ dp83902a_poll();
+ return 1;
}
int eth_send(volatile void *packet, int length) {
if (i <= 0) {
printf("%s: TIMEOUT: controller init failed\n", dev->name);
pcnet_reset (dev);
- return 0;
+ return -1;
}
/*
*/
pcnet_write_csr (dev, 0, 0x0002);
- return 1;
+ return 0;
}
static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len)
if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
printf("Cable not connected or other link failure\n");
- return(0);
+ return -1 ;
}
- return 1;
+ return 0;
}
/* Serial EEPROM section. */
/**************************************************************************
RESET - Finish setting up the ethernet interface
***************************************************************************/
-static void rtl_reset(struct eth_device *dev, bd_t *bis)
+static int rtl_reset(struct eth_device *dev, bd_t *bis)
{
int i;
#ifdef DEBUG_RTL8169
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
#endif
+ return 0;
}
/**************************************************************************
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# File: drivers/sk98lin/Makefile
+# File: drivers/net/sk98lin/Makefile
#
# Makefile for the SysKonnect SK-98xx device driver.
#
startup_tsec(dev);
/* If there's no link, fail */
- return priv->link;
+ return (priv->link ? 0 : -1);
}
(dev->enetaddr[0] << 16);
if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
- return 0;
+ return -1;
value =
MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
/* enable TX queue */
reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
- return 1;
+ return 0;
}
/*
db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
if (db->desc_pool_ptr == NULL)
- return 0;
+ return -1;
db->buf_pool_ptr = &buf_pool[0];
db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
if (db->buf_pool_ptr == NULL)
- return 0;
+ return -1;
db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
db->first_tx_desc_dma = db->desc_pool_dma_ptr;
db->cr6_data |= ULI526X_TXTH_256;
db->cr0_data = CR0_DEFAULT;
uli526x_init(dev);
- return 1;
+ return 0;
}
static void uli526x_disable(struct eth_device *dev)
*/
#include "common.h"
+#include <command.h>
#include "asm/errno.h"
#include "asm/io.h"
#include "asm/immap_qe.h"
void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
{
- u32 cecr;
+ u32 cecr;
if (cmd == QE_RESET) {
out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
return 0;
}
+/* The maximum number of RISCs we support */
+#define MAX_QE_RISC 2
+
+/* Firmware information stored here for qe_get_firmware_info() */
+static struct qe_firmware_info qe_firmware_info;
+
+/*
+ * Set to 1 if QE firmware has been uploaded, and therefore
+ * qe_firmware_info contains valid data.
+ */
+static int qe_firmware_uploaded;
+
+/*
+ * Upload a QE microcode
+ *
+ * This function is a worker function for qe_upload_firmware(). It does
+ * the actual uploading of the microcode.
+ */
+static void qe_upload_microcode(const void *base,
+ const struct qe_microcode *ucode)
+{
+ const u32 *code = base + be32_to_cpu(ucode->code_offset);
+ unsigned int i;
+
+ if (ucode->major || ucode->minor || ucode->revision)
+ printf("QE: uploading microcode '%s' version %u.%u.%u\n",
+ ucode->id, ucode->major, ucode->minor, ucode->revision);
+ else
+ printf("QE: uploading microcode '%s'\n", ucode->id);
+
+ /* Use auto-increment */
+ out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
+ QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
+
+ for (i = 0; i < be32_to_cpu(ucode->count); i++)
+ out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
+}
+
+/*
+ * Upload a microcode to the I-RAM at a specific address.
+ *
+ * See docs/README.qe_firmware for information on QE microcode uploading.
+ *
+ * Currently, only version 1 is supported, so the 'version' field must be
+ * set to 1.
+ *
+ * The SOC model and revision are not validated, they are only displayed for
+ * informational purposes.
+ *
+ * 'calc_size' is the calculated size, in bytes, of the firmware structure and
+ * all of the microcode structures, minus the CRC.
+ *
+ * 'length' is the size that the structure says it is, including the CRC.
+ */
+int qe_upload_firmware(const struct qe_firmware *firmware)
+{
+ unsigned int i;
+ unsigned int j;
+ u32 crc;
+ size_t calc_size = sizeof(struct qe_firmware);
+ size_t length;
+ const struct qe_header *hdr;
+
+ if (!firmware) {
+ printf("Invalid address\n");
+ return -EINVAL;
+ }
+
+ hdr = &firmware->header;
+ length = be32_to_cpu(hdr->length);
+
+ /* Check the magic */
+ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+ (hdr->magic[2] != 'F')) {
+ printf("Not a microcode\n");
+ return -EPERM;
+ }
+
+ /* Check the version */
+ if (hdr->version != 1) {
+ printf("Unsupported version\n");
+ return -EPERM;
+ }
+
+ /* Validate some of the fields */
+ if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) {
+ printf("Invalid data\n");
+ return -EINVAL;
+ }
+
+ /* Validate the length and check if there's a CRC */
+ calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
+
+ for (i = 0; i < firmware->count; i++)
+ /*
+ * For situations where the second RISC uses the same microcode
+ * as the first, the 'code_offset' and 'count' fields will be
+ * zero, so it's okay to add those.
+ */
+ calc_size += sizeof(u32) *
+ be32_to_cpu(firmware->microcode[i].count);
+
+ /* Validate the length */
+ if (length != calc_size + sizeof(u32)) {
+ printf("Invalid length\n");
+ return -EPERM;
+ }
+
+ /*
+ * Validate the CRC. We would normally call crc32_no_comp(), but that
+ * function isn't available unless you turn on JFFS support.
+ */
+ crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
+ if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
+ printf("Firmware CRC is invalid\n");
+ return -EIO;
+ }
+
+ /*
+ * If the microcode calls for it, split the I-RAM.
+ */
+ if (!firmware->split) {
+ out_be16(&qe_immr->cp.cercr,
+ in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
+ }
+
+ if (firmware->soc.model)
+ printf("Firmware '%s' for %u V%u.%u\n",
+ firmware->id, be16_to_cpu(firmware->soc.model),
+ firmware->soc.major, firmware->soc.minor);
+ else
+ printf("Firmware '%s'\n", firmware->id);
+
+ /*
+ * The QE only supports one microcode per RISC, so clear out all the
+ * saved microcode information and put in the new.
+ */
+ memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
+ strcpy(qe_firmware_info.id, firmware->id);
+ qe_firmware_info.extended_modes = firmware->extended_modes;
+ memcpy(qe_firmware_info.vtraps, firmware->vtraps,
+ sizeof(firmware->vtraps));
+ qe_firmware_uploaded = 1;
+
+ /* Loop through each microcode. */
+ for (i = 0; i < firmware->count; i++) {
+ const struct qe_microcode *ucode = &firmware->microcode[i];
+
+ /* Upload a microcode if it's present */
+ if (ucode->code_offset)
+ qe_upload_microcode(firmware, ucode);
+
+ /* Program the traps for this processor */
+ for (j = 0; j < 16; j++) {
+ u32 trap = be32_to_cpu(ucode->traps[j]);
+
+ if (trap)
+ out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+ }
+
+ /* Enable traps */
+ out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+ }
+
+ return 0;
+}
+
+struct qe_firmware_info *qe_get_firmware_info(void)
+{
+ return qe_firmware_uploaded ? &qe_firmware_info : NULL;
+}
+
+static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong addr;
+
+ if (argc < 3) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (strcmp(argv[1], "fw") == 0) {
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ if (!addr) {
+ printf("Invalid address\n");
+ return -EINVAL;
+ }
+
+ /*
+ * If a length was supplied, compare that with the 'length'
+ * field.
+ */
+
+ if (argc > 3) {
+ ulong length = simple_strtoul(argv[3], NULL, 16);
+ struct qe_firmware *firmware = (void *) addr;
+
+ if (length != be32_to_cpu(firmware->header.length)) {
+ printf("Length mismatch\n");
+ return -EINVAL;
+ }
+ }
+
+ return qe_upload_firmware((const struct qe_firmware *) addr);
+ }
+
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ qe, 4, 0, qe_cmd,
+ "qe - QUICC Engine commands\n",
+ "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
+ "the QE,\n\twith optional length <length> verification.\n"
+ );
+
#endif /* CONFIG_QE */
#define QE_SDEBCR_BA_MASK 0x01FFFFFF
+/* Communication Processor */
+#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
+#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
+#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
+
+/* I-RAM */
+#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
+#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
+
+/* Structure that defines QE firmware binary files.
+ *
+ * See doc/README.qe_firmware for a description of these fields.
+ */
+struct qe_firmware {
+ struct qe_header {
+ u32 length; /* Length of the entire structure, in bytes */
+ u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
+ u8 version; /* Version of this layout. First ver is '1' */
+ } header;
+ u8 id[62]; /* Null-terminated identifier string */
+ u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
+ u8 count; /* Number of microcode[] structures */
+ struct {
+ u16 model; /* The SOC model */
+ u8 major; /* The SOC revision major */
+ u8 minor; /* The SOC revision minor */
+ } __attribute__ ((packed)) soc;
+ u8 padding[4]; /* Reserved, for alignment */
+ u64 extended_modes; /* Extended modes */
+ u32 vtraps[8]; /* Virtual trap addresses */
+ u8 reserved[4]; /* Reserved, for future expansion */
+ struct qe_microcode {
+ u8 id[32]; /* Null-terminated identifier */
+ u32 traps[16]; /* Trap addresses, 0 == ignore */
+ u32 eccr; /* The value for the ECCR register */
+ u32 iram_offset; /* Offset into I-RAM for the code */
+ u32 count; /* Number of 32-bit words of the code */
+ u32 code_offset; /* Offset of the actual microcode */
+ u8 major; /* The microcode version major */
+ u8 minor; /* The microcode version minor */
+ u8 revision; /* The microcode version revision */
+ u8 padding; /* Reserved, for alignment */
+ u8 reserved[4]; /* Reserved, for future expansion */
+ } __attribute__ ((packed)) microcode[1];
+ /* All microcode binaries should be located here */
+ /* CRC32 should be located here, after the microcode binaries */
+} __attribute__ ((packed));
+
+struct qe_firmware_info {
+ char id[64]; /* Firmware name */
+ u32 vtraps[8]; /* Virtual trap addresses */
+ u64 extended_modes; /* Extended modes */
+};
+
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
uint qe_muram_alloc(uint size, uint align);
void qe_assign_page(uint snum, uint para_ram_base);
int qe_set_brg(uint brg, uint rate);
int qe_set_mii_clk_src(int ucc_num);
+int qe_upload_firmware(const struct qe_firmware *firmware);
+struct qe_firmware_info *qe_get_firmware_info(void);
#endif /* __QE_H__ */
if (dev->enetaddr[0] & 0x01) {
printf("%s: MacAddress is multcast address\n",
__FUNCTION__);
- return 0;
+ return -1;
}
uec_set_mac_address(uec, dev->enetaddr);
uec->the_first_run = 1;
err = uec_open(uec, COMM_DIR_RX_AND_TX);
if (err) {
printf("%s: cannot enable UEC device\n", dev->name);
- return 0;
+ return -1;
}
- return uec->mii_info->link;
+ return (uec->mii_info->link ? 0 : -1);
}
static void uec_halt(struct eth_device* dev)
* MA 02111-1307 USA
*
*
- * Derived in part from the SL811 HCD driver "u-boot/drivers/sl811_usb.c"
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
* (original copyright message follows):
*
* (C) Copyright 2004
* bodonoghue@CodeHermit.ie
*
* References
- * DasUBoot/drivers/usbdcore_omap1510.c, for design and implementation ideas.
+ * DasUBoot/drivers/usb/usbdcore_omap1510.c, for design and implementation
+ * ideas.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
/*****************************************************************************/
/* Cursor definition: */
-/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/i8042.c) to */
-/* let the cursor blink. Uses the macros CURSOR_OFF */
-/* and CURSOR_ON. */
+/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) */
+/* to let the cursor blink. Uses the macros */
+/* CURSOR_OFF and CURSOR_ON. */
/* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */
/* blinking is provided. Uses the macros CURSOR_SET */
/* and CURSOR_OFF. */
#define CURSOR_OFF console_cursor(0);
#define CURSOR_SET
#ifndef CONFIG_I8042_KBD
-#warning Cursor drawing on/off needs timer function s.a. drivers/i8042.c
+#warning Cursor drawing on/off needs timer function s.a. drivers/input/i8042.c
#endif
#else
#ifdef CONFIG_CONSOLE_TIME
/* no signature found */
return -1;
}
- if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
- /* ok, we assume we are on a PBR only */
- cur_part = 1;
- part_offset=0;
- } else {
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
- (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
- defined(CONFIG_SYSTEMACE) )
- /* First we assume, there is a MBR */
- if (!get_partition_info (dev_desc, part_no, &info)) {
- part_offset = info.start;
- cur_part = part_no;
- } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) {
- /* ok, we assume we are on a PBR only */
- cur_part = 1;
- part_offset = 0;
- } else {
- printf ("** Partition %d not valid on device %d **\n",
+ defined(CONFIG_MMC) || \
+ defined(CONFIG_SYSTEMACE) )
+ /* First we assume, there is a MBR */
+ if (!get_partition_info (dev_desc, part_no, &info)) {
+ part_offset = info.start;
+ cur_part = part_no;
+ } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) {
+ /* ok, we assume we are on a PBR only */
+ cur_part = 1;
+ part_offset = 0;
+ } else {
+ printf ("** Partition %d not valid on device %d **\n",
part_no, dev_desc->dev);
- return -1;
- }
+ return -1;
+ }
+
#else
- if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
- /* ok, we assume we are on a PBR only */
- cur_part = 1;
- part_offset = 0;
- info.start = part_offset;
- } else {
- /* FIXME we need to determine the start block of the
- * partition where the DOS FS resides. This can be done
- * by using the get_partition_info routine. For this
- * purpose the libpart must be included.
- */
- part_offset = 32;
- cur_part = 1;
- }
-#endif
+ if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
+ /* ok, we assume we are on a PBR only */
+ cur_part = 1;
+ part_offset = 0;
+ info.start = part_offset;
+ } else {
+ /* FIXME we need to determine the start block of the
+ * partition where the DOS FS resides. This can be done
+ * by using the get_partition_info routine. For this
+ * purpose the libpart must be included.
+ */
+ part_offset = 32;
+ cur_part = 1;
}
+#endif
return 0;
}
int read_jffs2_nand(size_t start, size_t len,
size_t * retlen, u_char * buf, int nanddev);
#else
-/* info for NAND chips, defined in drivers/nand/nand.c */
+/* info for NAND chips, defined in drivers/mtd/nand/nand.c */
extern nand_info_t nand_info[];
#endif
--- /dev/null
+#ifndef _API_PUBLIC_H_
+#define _API_PUBLIC_H_
+
+#define API_EINVAL 1 /* invalid argument(s) */
+#define API_ENODEV 2 /* no device */
+#define API_ENOMEM 3 /* no memory */
+#define API_EBUSY 4 /* busy, occupied etc. */
+#define API_EIO 5 /* I/O error */
+
+typedef int (*scp_t)(int, int *, ...);
+
+#define API_SIG_VERSION 1
+#define API_SIG_MAGIC "UBootAPI"
+#define API_SIG_MAGLEN 8
+
+struct api_signature {
+ char magic[API_SIG_MAGLEN]; /* magic string */
+ uint16_t version; /* API version */
+ uint32_t checksum; /* checksum of this sig struct */
+ scp_t syscall; /* entry point to the API */
+};
+
+enum {
+ API_RSVD = 0,
+ API_GETC,
+ API_PUTC,
+ API_TSTC,
+ API_PUTS,
+ API_RESET,
+ API_GET_SYS_INFO,
+ API_UDELAY,
+ API_GET_TIMER,
+ API_DEV_ENUM,
+ API_DEV_OPEN,
+ API_DEV_CLOSE,
+ API_DEV_READ,
+ API_DEV_WRITE,
+ API_ENV_ENUM,
+ API_ENV_GET,
+ API_ENV_SET,
+ API_MAXCALL
+};
+
+#define MR_ATTR_FLASH 0x0001
+#define MR_ATTR_DRAM 0x0002
+#define MR_ATTR_SRAM 0x0003
+
+struct mem_region {
+ unsigned long start;
+ unsigned long size;
+ int flags;
+};
+
+struct sys_info {
+ unsigned long clk_bus;
+ unsigned long clk_cpu;
+ unsigned long bar;
+ struct mem_region *mr;
+ int mr_no; /* number of memory regions */
+};
+
+#undef CFG_64BIT_LBA
+#ifdef CFG_64BIT_LBA
+typedef u_int64_t lbasize_t;
+#else
+typedef unsigned long lbasize_t;
+#endif
+typedef unsigned long lbastart_t;
+
+#define DEV_TYP_NONE 0x0000
+#define DEV_TYP_NET 0x0001
+
+#define DEV_TYP_STOR 0x0002
+#define DT_STOR_IDE 0x0010
+#define DT_STOR_SCSI 0x0020
+#define DT_STOR_USB 0x0040
+#define DT_STOR_MMC 0x0080
+
+#define DEV_STA_CLOSED 0x0000 /* invalid, closed */
+#define DEV_STA_OPEN 0x0001 /* open i.e. active */
+
+struct device_info {
+ int type;
+ void *cookie;
+
+ union {
+ struct {
+ lbasize_t block_count; /* no of blocks */
+ unsigned long block_size; /* size of one block */
+ } storage;
+
+ struct {
+ unsigned char hwaddr[6];
+ } net;
+ } info;
+#define di_stor info.storage
+#define di_net info.net
+
+ int state;
+};
+
+#endif /* _API_PUBLIC_H_ */
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480))
-#if defined(CONFIG_PPC64BRIDGE)
+#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
+#define L1_CACHE_SHIFT 4
+#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
#else
#define L1_CACHE_SHIFT 5
-#endif /* PPC64 */
-#else
-#define L1_CACHE_SHIFT 4
-#endif /* !(8xx || IOP480) */
+#endif
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
u8 res2[0x48];
} __attribute__ ((packed)) dbg_t;
-/* RISC Special Registers (Trap and Breakpoint)
+/*
+ * RISC Special Registers (Trap and Breakpoint). These are described in
+ * the QE Developer's Handbook.
*/
typedef struct rsp {
- u8 fixme[0x100];
+ u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
+ u8 res0[64];
+ u32 ibcr0;
+ u32 ibs0;
+ u32 ibcnr0;
+ u8 res1[4];
+ u32 ibcr1;
+ u32 ibs1;
+ u32 ibcnr1;
+ u32 npcr;
+ u32 dbcr;
+ u32 dbar;
+ u32 dbamr;
+ u32 dbsr;
+ u32 dbcnr;
+ u8 res2[12];
+ u32 dbdr_h;
+ u32 dbdr_l;
+ u32 dbdmr_h;
+ u32 dbdmr_l;
+ u32 bsr;
+ u32 bor;
+ u32 bior;
+ u8 res3[4];
+ u32 iatr[4];
+ u32 eccr; /* Exception control configuration register */
+ u32 eicr;
+ u8 res4[0x100-0xf8];
} __attribute__ ((packed)) rsp_t;
typedef struct qe_immap {
*/
/*
- * e500 support
+ * FSL Book-E support
*/
-#define MAS0_TLBSEL 0x10000000
-#define MAS0_ESEL 0x000F0000
-#define MAS0_NV 0x00000001
-
-#define MAS1_VALID 0x80000000
-#define MAS1_IPROT 0x40000000
-#define MAS1_TID 0x00FF0000
-#define MAS1_TS 0x00001000
-#define MAS1_TSIZE 0x00000F00
-
-#define MAS2_EPN 0xFFFFF000
-#define MAS2_SHAREN 0x00000200
-#define MAS2_X0 0x00000040
-#define MAS2_X1 0x00000020
-#define MAS2_W 0x00000010
-#define MAS2_I 0x00000008
-#define MAS2_M 0x00000004
-#define MAS2_G 0x00000002
-#define MAS2_E 0x00000001
-
-#define MAS3_RPN 0xFFFFF000
-#define MAS3_U0 0x00000200
-#define MAS3_U1 0x00000100
-#define MAS3_U2 0x00000080
-#define MAS3_U3 0x00000040
-#define MAS3_UX 0x00000020
-#define MAS3_SX 0x00000010
-#define MAS3_UW 0x00000008
-#define MAS3_SW 0x00000004
-#define MAS3_UR 0x00000002
-#define MAS3_SR 0x00000001
-
-#define MAS4_TLBSELD 0x10000000
-#define MAS4_TIDDSEL 0x00030000
-#define MAS4_DSHAREN 0x00001000
-#define MAS4_TSIZED(x) (x << 8)
-#define MAS4_X0D 0x00000040
-#define MAS4_X1D 0x00000020
-#define MAS4_WD 0x00000010
-#define MAS4_ID 0x00000008
-#define MAS4_MD 0x00000004
-#define MAS4_GD 0x00000002
-#define MAS4_ED 0x00000001
-
-#define MAS6_SPID 0x00FF0000
-#define MAS6_SAS 0x00000001
+#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
+#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
+#define MAS0_NV(x) ((x) & 0x00000FFF)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
+#define MAS1_TS 0x00001000
+#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
+
+#define MAS2_EPN 0xFFFFF000
+#define MAS2_X0 0x00000040
+#define MAS2_X1 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN 0xFFFFF000
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+
+#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
+#define MAS4_TIDDSEL 0x000F0000
+#define MAS4_TSIZED(x) MAS1_TSIZE(x)
+#define MAS4_X0D 0x00000040
+#define MAS4_X1D 0x00000020
+#define MAS4_WD 0x00000010
+#define MAS4_ID 0x00000008
+#define MAS4_MD 0x00000004
+#define MAS4_GD 0x00000002
+#define MAS4_ED 0x00000001
+
+#define MAS6_SPID0 0x3FFF0000
+#define MAS6_SPID1 0x00007FFE
+#define MAS6_SAS 0x00000001
+#define MAS6_SPID MAS6_SPID0
+
+#define MAS7_RPN 0xFFFFFFFF
+
+#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
+ (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
+#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
+ ((((v) << 31) & MAS1_VALID) |\
+ (((iprot) << 30) & MAS1_IPROT) |\
+ (MAS1_TID(tid)) |\
+ (((ts) << 12) & MAS1_TS) |\
+ (MAS1_TSIZE(tsize)))
+#define FSL_BOOKE_MAS2(epn, wimge) \
+ (((epn) & MAS3_RPN) | (wimge))
+#define FSL_BOOKE_MAS3(rpn, user, perms) \
+ (((rpn) & MAS3_RPN) | (user) | (perms))
#define BOOKE_PAGESZ_1K 0
#define BOOKE_PAGESZ_4K 1
#define BOOKE_PAGESZ_256M 9
#define BOOKE_PAGESZ_1G 10
#define BOOKE_PAGESZ_4G 11
+#define BOOKE_PAGESZ_16GB 12
+#define BOOKE_PAGESZ_64GB 13
+#define BOOKE_PAGESZ_256GB 14
+#define BOOKE_PAGESZ_1TB 15
#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR 0x00FFFFFF
#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
/* e500 definitions */
+#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
+#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define MCSRR1 SPRN_MCSRR1
#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
+#define L1CFG0 SPRN_L1CFG0
+#define L1CFG1 SPRN_L1CFG1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
#define BUCSR SPRN_BUCSR
void main_loop (void);
int run_command (const char *cmd, int flag);
int readline (const char *const prompt);
+int readline_into_buffer (const char *const prompt, char * buffer);
+int parse_line (char *, char *[]);
void init_cmd_timeout(void);
void reset_cmd_timeout(void);
/* common/cmd_nvedit.c */
int env_init (void);
void env_relocate (void);
+int envmatch (uchar *, int);
char *getenv (char *);
int getenv_r (char *name, char *buf, unsigned len);
int saveenv (void);
/* common/exports.c */
void jumptable_init(void);
+/* api/api.c */
+void api_init (void);
+
/* common/memsize.c */
long get_ram_size (volatile long *, long);
--- /dev/null
+/*
+ * Copyright 2007
+ * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * atum8548 board configuration file
+ *
+ * Please refer to doc/README.atum8548 for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Debug Options, Disable in production
+#define ET_DEBUG 1
+#define CONFIG_PANIC_HANG 1
+#define DEBUG 1
+*/
+
+/* CPLD Configuration Options */
+#define MPC85xx_ATUM_CLKOCR 0x80000002
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548 1 /* MPC8548 specific */
+
+#define CONFIG_PCI 1 /* enable any pci type devices */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCI2 1 /* PCI controller 2 */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
+
+#define CONFIG_SYS_CLK_FREQ 33000000
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+#undef CFG_DRAM_TEST
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR parameters
+ */
+ #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
+ #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
+ #define CFG_DDR_CS0_CONFIG 0x80000102
+ #define CFG_DDR_TIMING_0 0x00260802
+ #define CFG_DDR_TIMING_1 0x38355322
+ #define CFG_DDR_TIMING_2 0x039048c7
+ #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+ #define CFG_DDR_MODE 0x00000432
+ #define CFG_DDR_INTERVAL 0x05150100
+ #define DDR_SDRAM_CFG 0x43000000
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * based on flash chip S29GL01GP
+ * One bank, 128M, using the CFI driver.
+ * Boot from BR0 bank at 0xf800_0000
+ *
+ * BR0:
+ * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
+ * Port Size = 16 bits = BRx[19:20] = 10
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
+ *
+ * OR0:
+ * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
+ * Reserved ORx[17:18] = 00
+ * CSNT = ORx[20] = 1
+ * ACS = half cycle delay = ORx[21:22] = 11
+ * SCY = 6 = ORx[24:27] = 0110
+ * TRLX = use relaxed timing = ORx[29] = 1
+ * EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
+ */
+
+#define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */
+#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */
+
+#define CFG_BR0_PRELIM 0xf8001001
+
+#define CFG_OR0_PRELIM 0xf8000E65
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
+
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_EMPTY_INFO
+
+/*
+ * Flash on the LocalBus
+ */
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+
+/* Memory */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE 0xC0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2800000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#endif
+
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe3000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC3_PHY_ADDR 2
+#define TSEC4_PHY_ADDR 3
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS TSEC_GIGABIT
+#define TSEC4_FLAGS TSEC_GIGABIT
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME "eTSEC2"
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_IPADDR 10.101.43.142
+
+#define CONFIG_HOSTNAME atum
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE /tftpboot/uImage.atum
+#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
+
+#define CONFIG_SERVERIP 10.101.43.10
+#define CONFIG_GATEWAYIP 10.101.45.1
+#define CONFIG_NETMASK 255.255.248.0
+
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CFG_ISA_IO 0xE8000000
-/* see also drivers/videomodes.c */
+/* see also drivers/video/videomodes.c */
#define CFG_DEFAULT_VIDEO_MODE 0x303
#endif
# define CFG_ENV_SECT_SIZE 0x20000
#endif
-/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
keep reset. */
#undef CFG_FLASH_CFI
#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
-/* drivers/nand/nand.c */
+/* drivers/mtd/nand/nand.c */
#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
- #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CFG_ISA_IO 0xE8000000
-/* see also drivers/videomodes.c */
+/* see also drivers/video/videomodes.c */
#define CFG_DEFAULT_VIDEO_MODE 0x303
#endif
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
- #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
/*
* Move up the U-Boot & monitor area if more flash is fitted.
* If this U-Boot is to be run on Integrators with varying flash sizes,
- * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
* register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
* - CFG_MONITOR_BASE is set to indicate that the environment is not
* embedded in the boot monitor(s) area
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
* CFI FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
--- /dev/null
+/*
+ * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * sbc8548 board configuration file
+ *
+ * Please refer to doc/README.sbc85xx for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548 1 /* MPC8548 specific */
+#define CONFIG_SBC8548 1 /* SBC8548 board specific */
+
+#undef CONFIG_PCI /* enable any pci type devices */
+#undef CONFIG_PCI1 /* PCI controller 1 */
+#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#undef CONFIG_RIO
+#undef CONFIG_PCI2
+#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
+
+#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+ #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, one 8MB the other 64MB, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff80_0000
+ * Alternate BR6/OR6 bank at 0xfb80_0000
+ *
+ * BR0:
+ * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
+ * Port Size = 8 bits = BRx[19:20] = 01
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0
+ *
+ * BR6:
+ * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
+ * Port Size = 32 bits = BRx[19:20] = 11
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6
+ *
+ * OR0:
+ * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
+ * XAM = OR0[17:18] = 11
+ * CSNT = OR0[20] = 1
+ * ACS = half cycle delay = OR0[21:22] = 11
+ * SCY = 6 = OR0[24:27] = 0110
+ * TRLX = use relaxed timing = OR0[29] = 1
+ * EAD = use external address latch delay = OR0[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0
+ *
+ * OR6:
+ * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ * XAM = OR6[17:18] = 11
+ * CSNT = OR6[20] = 1
+ * ACS = half cycle delay = OR6[21:22] = 11
+ * SCY = 6 = OR6[24:27] = 0110
+ * TRLX = use relaxed timing = OR6[29] = 1
+ * EAD = use external address latch delay = OR6[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6
+ */
+
+#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
+#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
+
+#define CFG_BR0_PRELIM 0xff800801
+#define CFG_BR6_PRELIM 0xfb801801
+
+#define CFG_OR0_PRELIM 0xff806e65
+#define CFG_OR6_PRELIM 0xfc006e65
+
+#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+/* CS5 = Local bus peripherals controlled by the EPLD */
+
+#define CFG_BR5_PRELIM 0xf8000801
+#define CFG_OR5_PRELIM 0xff006e65
+#define CFG_EPLD_BASE 0xf8000000
+#define CFG_LED_DISP_BASE 0xf8000000
+#define CFG_USER_SWITCHES_BASE 0xf8100000
+#define CFG_BD_REV 0xf8300000
+#define CFG_EEPROM_BASE 0xf8b00000
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 3 and Option Register 3 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR3, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ */
+
+#define CFG_BR3_PRELIM 0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR3, need:
+ * 64MB mask for AM, OR3[0:7] = 1111 1100
+ * XAM, OR3[17:18] = 11
+ * 10 columns OR3[19-21] = 011
+ * 12 rows OR3[23-25] = 011
+ * EAD set for extra time OR[31] = 0
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
+ */
+
+#define CFG_OR3_PRELIM 0xfc006cc0
+
+#define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
+#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ * or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
+ | CFG_LBC_LSDMR_PRETOACT7 \
+ | CFG_LBC_LSDMR_ACTTORW7 \
+ | CFG_LBC_LSDMR_BL8 \
+ | CFG_LBC_LSDMR_WRC4 \
+ | CFG_LBC_LSDMR_CL3 \
+ | CFG_LBC_LSDMR_RFEN \
+ )
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2800000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#endif
+
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe3000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+
+#ifdef CONFIG_RIO
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xC0000000
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4
+#define CONFIG_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC3_PHY_ADDR 2
+#define TSEC4_PHY_ADDR 3
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME "eTSEC0"
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_IPADDR 192.168.0.55
+
+#define CONFIG_HOSTNAME sbc8548
+#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
+#define CONFIG_BOOTFILE /uImage
+#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
+
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=uRamdisk\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=sbc8548.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
- #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
#endif /* _ASMLANGUAGE */
-/* Motorola E500 core provides 16 TLB1 entries; they can be used for
- * initial memory mapping like legacy BAT registers do. Usually we
- * use four MAS registers(MAS0-3) to operate on TLB1 entries.
- *
- * While there are 16 Entries with variable Page Sizes in TLB1,
- * there are also 256 Entries with fixed 4K pages in TLB0.
- *
- * We also need LAWs(Local Access Window) to associate a range of
- * the local 32-bit address space with a particular target interface
- * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
- *
- * We put TLB1/LAW code here because memory mapping is board-specific
- * instead of cpu-specific.
- *
- * While these macros are all nominally for TLB1 by name, they can
- * also be used for TLB0 as well.
- */
-
-
-/*
- * Convert addresses to Effective and Real Page Numbers.
- * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
- */
-#define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff)
-#define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff)
-
-
-/* MAS0
- * tlbsel(TLB Select):0,1
- * esel(Entry Select): 0,1,2,...,15 for TLB1
- * nv(Next victim):0,1
- */
-#define TLB1_MAS0(tlbsel,esel,nv) \
- ((((tlbsel) << 28) & MAS0_TLBSEL) |\
- (((esel) << 16) & MAS0_ESEL ) |\
- (nv) )
-
-
-/* MAS1
- * v(TLB valid bit):0,1
- * iprot(invalidate protect):0,1
- * tid(translation identity):8bit to match process IDs
- * ts(translation space,comparing with MSR[IS,DS]): 0,1
- * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
- */
-#define TLB1_MAS1(v,iprot,tid,ts,tsize) \
- ((((v) << 31) & MAS1_VALID) |\
- (((iprot) << 30) & MAS1_IPROT) |\
- (((tid) << 16) & MAS1_TID) |\
- (((ts) << 12) & MAS1_TS) |\
- (((tsize) << 8) & MAS1_TSIZE) )
-
-
-/* MAS2
- * epn(effective page number):20bits
- * sharen(Shared cache state):0,1
- * x0,x1(implementation specific page attribute):0,1
- * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
- * endianness):0,1
- */
-#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
- ((((epn) << 12) & MAS2_EPN) |\
- (((sharen) << 9) & MAS2_SHAREN) |\
- (((x0) << 6) & MAS2_X0) |\
- (((x1) << 5) & MAS2_X1) |\
- (((w) << 4) & MAS2_W) |\
- (((i) << 3) & MAS2_I) |\
- (((m) << 2) & MAS2_M) |\
- (((g) << 1) & MAS2_G) |\
- (e) )
-
-
-/* MAS3
- * rpn(real page number):20bits
- * u0-u3(user bits, useful for page table management in OS):0,1
- * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
- * write,execute permission).
- */
-#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
- ((((rpn) << 12) & MAS3_RPN) |\
- (((u0) << 9) & MAS3_U0) |\
- (((u1) << 8) & MAS3_U1) |\
- (((u2) << 7) & MAS3_U2) |\
- (((u3) << 6) & MAS3_U3) |\
- (((ux) << 5) & MAS3_UX) |\
- (((sx) << 4) & MAS3_SX) |\
- (((uw) << 3) & MAS3_UW) |\
- (((sw) << 2) & MAS3_SW) |\
- (((ur) << 1) & MAS3_UR) |\
- (sr) )
-
-
#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
- line aligned data. */
#endif /* __E500_H__ */
void fdt_fixup_ethernet(void *fdt, bd_t *bd);
int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
const void *val, int len, int create);
+void fdt_fixup_qe_firmware(void *fdt);
#ifdef CONFIG_OF_HAS_UBOOT_ENV
int fdt_env(void *fdt);
#define NAND_ECC_HW3_256 2
/* Hardware ECC 3 byte ECC per 512 Byte data */
#define NAND_ECC_HW3_512 3
-/* Hardware ECC 3 byte ECC per 512 Byte data */
+/* Hardware ECC 6 byte ECC per 512 Byte data */
#define NAND_ECC_HW6_512 4
/* Hardware ECC 8 byte ECC per 512 Byte data */
#define NAND_ECC_HW8_512 6
/* Initialize the jump table for applications */
jumptable_init ();
+#if defined(CONFIG_API)
+ /* Initialize API */
+ api_init ();
+#endif
+
/* Initialize the console (after the relocation and devices init) */
console_init_r ();
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-# from drivers/nand directory
+# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-# from drivers/nand directory
+# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-# from drivers/nand directory
+# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
/*
- * Read on byte
+ * Read one byte
*/
if (this->read_byte(mtd) != 0xff)
return 1;
do {
debug ("Trying %s\n", eth_current->name);
- if (!eth_current->init(eth_current,bis)) {
+ if (eth_current->init(eth_current,bis) >= 0) {
eth_current->state = ETH_STATE_ACTIVE;
return 0;
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o $(obj)sha1.o
+$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
projects / karo-tx-uboot.git / commitdiff