on those systems that support this (optional)
feature, like the TQM8xxL modules.
-- I2C Support: CONFIG_HARD_I2C | CONFIG_SOFT_I2C
-
- These enable I2C serial bus commands. Defining either of
- (but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will
- include the appropriate I2C driver for the selected CPU.
+- I2C Support: CONFIG_SYS_I2C
+
+ This enable the NEW i2c subsystem, and will allow you to use
+ i2c commands at the u-boot command line (as long as you set
+ CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
+ based realtime clock chips or other i2c devices. See
+ common/cmd_i2c.c for a description of the command line
+ interface.
+
+ ported i2c driver to the new framework:
+ - drivers/i2c/soft_i2c.c:
+ - activate first bus with CONFIG_SYS_I2C_SOFT define
+ CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
+ for defining speed and slave address
+ - activate second bus with I2C_SOFT_DECLARATIONS2 define
+ CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
+ for defining speed and slave address
+ - activate third bus with I2C_SOFT_DECLARATIONS3 define
+ CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
+ for defining speed and slave address
+ - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
+ CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
+ for defining speed and slave address
+
+ - drivers/i2c/fsl_i2c.c:
+ - activate i2c driver with CONFIG_SYS_I2C_FSL
+ define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
+ offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
+ CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
+ bus.
+ - If your board supports a second fsl i2c bus, define
+ CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
+ CONFIG_SYS_FSL_I2C2_SPEED for the speed and
+ CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
+ second bus.
+
+ - drivers/i2c/tegra_i2c.c:
+ - activate this driver with CONFIG_SYS_I2C_TEGRA
+ - This driver adds 4 i2c buses with a fix speed from
+ 100000 and the slave addr 0!
+
+ - drivers/i2c/ppc4xx_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_PPC4XX
+ - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
+ - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
+
+ additional defines:
+
+ CONFIG_SYS_NUM_I2C_BUSES
+ Hold the number of i2c busses you want to use. If you
+ don't use/have i2c muxes on your i2c bus, this
+ is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
+ omit this define.
+
+ CONFIG_SYS_I2C_DIRECT_BUS
+ define this, if you don't use i2c muxes on your hardware.
+ if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+ omit this define.
+
+ CONFIG_SYS_I2C_MAX_HOPS
+ define how many muxes are maximal consecutively connected
+ on one i2c bus. If you not use i2c muxes, omit this
+ define.
+
+ CONFIG_SYS_I2C_BUSES
+ hold a list of busses you want to use, only used if
+ CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
+ a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
+ CONFIG_SYS_NUM_I2C_BUSES = 9:
+
+ CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \
+ {1, {I2C_NULL_HOP}}, \
+ {1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \
+ {1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \
+ }
+
+ which defines
+ bus 0 on adapter 0 without a mux
+ bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1
+ bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2
+ bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3
+ bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4
+ bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5
+ bus 6 on adapter 1 without a mux
+ bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1
+ bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2
+
+ If you do not have i2c muxes on your board, omit this define.
+
+- Legacy I2C Support: CONFIG_HARD_I2C
+
+ NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
+ provides the following compelling advantages:
+
+ - more than one i2c adapter is usable
+ - approved multibus support
+ - better i2c mux support
+
+ ** Please consider updating your I2C driver now. **
+
+ These enable legacy I2C serial bus commands. Defining
+ CONFIG_HARD_I2C will include the appropriate I2C driver
+ for the selected CPU.
This will allow you to use i2c commands at the u-boot
command line (as long as you set CONFIG_CMD_I2C in
CONFIG_HARD_I2C selects a hardware I2C controller.
- CONFIG_SOFT_I2C configures u-boot to use a software (aka
- bit-banging) driver instead of CPM or similar hardware
- support for I2C.
-
There are several other quantities that must also be
- defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
+ defined when you define CONFIG_HARD_I2C.
In both cases you will need to define CONFIG_SYS_I2C_SPEED
to be the frequency (in Hz) at which you wish your i2c bus
That's all that's required for CONFIG_HARD_I2C.
- If you use the software i2c interface (CONFIG_SOFT_I2C)
+ If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
then the following macros need to be defined (examples are
from include/configs/lwmon.h):
If not defined, then U-Boot uses predefined value for
specified DTT device.
- CONFIG_FSL_I2C
-
- Define this option if you want to use Freescale's I2C driver in
- drivers/i2c/fsl_i2c.c.
-
- CONFIG_I2C_MUX
-
- Define this option if you have I2C devices reached over 1 .. n
- I2C Muxes like the pca9544a. This option addes a new I2C
- Command "i2c bus [muxtype:muxaddr:muxchannel]" which adds a
- new I2C Bus to the existing I2C Busses. If you select the
- new Bus with "i2c dev", u-bbot sends first the commandos for
- the muxes to activate this new "bus".
-
- CONFIG_I2C_MULTI_BUS must be also defined, to use this
- feature!
-
- Example:
- Adding a new I2C Bus reached over 2 pca9544a muxes
- The First mux with address 70 and channel 6
- The Second mux with address 71 and channel 4
-
- => i2c bus pca9544a:70:6:pca9544a:71:4
-
- Use the "i2c bus" command without parameter, to get a list
- of I2C Busses with muxes:
-
- => i2c bus
- Busses reached over muxes:
- Bus ID: 2
- reached over Mux(es):
- pca9544a@70 ch: 4
- Bus ID: 3
- reached over Mux(es):
- pca9544a@70 ch: 6
- pca9544a@71 ch: 4
- =>
-
- If you now switch to the new I2C Bus 3 with "i2c dev 3"
- u-boot first sends the command to the mux@70 to enable
- channel 6, and then the command to the mux@71 to enable
- the channel 4.
-
- After that, you can use the "normal" i2c commands as
- usual to communicate with your I2C devices behind
- the 2 muxes.
-
- This option is actually implemented for the bitbanging
- algorithm in common/soft_i2c.c and for the Hardware I2C
- Bus on the MPC8260. But it should be not so difficult
- to add this option to other architectures.
-
CONFIG_SOFT_I2C_READ_REPEATED_START
defining this will force the i2c_read() function in
I2C muxes, you can define here, how to reach this
EEPROM. For example:
- #define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
+ #define CONFIG_I2C_ENV_EEPROM_BUS 1
EEPROM which holds the environment, is reached over
a pca9547 i2c mux with address 0x70, channel 3.
return freq;
}
+static u32 get_i2c_clk(void)
+{
+ return get_ipg_clk();
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
return get_sdhc_clk();
case MXC_FEC_CLK:
return get_fec_clk();
+ case MXC_I2C_CLK:
+ return get_i2c_clk();
default:
break;
}
* I2C related stuff
*/
#ifdef CONFIG_CMD_I2C
-#ifndef CONFIG_SOFT_I2C
+#ifndef CONFIG_SYS_I2C_SOFT
#define CONFIG_I2C_MVTWSI
#endif
#define CONFIG_SYS_I2C_SLAVE 0x0
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_FEC_CLK,
+ MXC_I2C_CLK,
};
void enable_ocotp_clk(unsigned char enable);
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
#define CONFIG_IOMUX_SHARE_CONF_REG
#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
/* MSCM interrupt rounter */
#define MSCM_IRSPRC_CP0_EN 1
#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_OBE_IBE_ENABLE)
#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
+#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
#endif
#if defined(CONFIG_HARD_I2C) || \
- defined(CONFIG_SOFT_I2C)
+ defined(CONFIG_SYS_I2C)
#include <i2c.h>
#endif
return (0);
}
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
static int init_func_i2c(void)
{
puts("I2C: ");
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
puts("ready\n");
return (0);
}
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
init_func_i2c,
#endif
dram_init, /* configure available RAM banks */
int post_flag;
#endif
+#if defined(CONFIG_SYS_I2C)
+#include <i2c.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
__attribute__((always_inline))
mmc_initialize(bd);
#endif
+#if defined(CONFIG_SYS_I2C)
+ i2c_reloc_fixup();
+#endif
/* relocate environment function pointers etc. */
env_relocate();
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
#endif
gd->bus_clk = gd->arch.flb_clk;
}
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
/* FlexBus Chipselect */
init_fbcs();
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG =
CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
init_fbcs();
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
gd->bus_clk = gd->cpu_clk;
#endif
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
-#ifdef CONFIG_SYS_I2C2_OFFSET
+#ifdef CONFIG_SYS_I2C2_FSL_OFFSET
gd->arch.i2c2_clk = gd->bus_clk;
#endif
#endif
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
#endif
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
#endif
}
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
}
setup_5445x_clocks();
#endif
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_FSL_I2C
gd->arch.i2c1_clk = gd->bus_clk;
#endif
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
out_be16(&gpio->par_feci2cirq,
GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
#endif
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
/* Architecture-specific global data */
struct arch_global_data {
-#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_SYS_I2C_FSL
unsigned long i2c1_clk;
unsigned long i2c2_clk;
#endif
#include <version.h>
#if defined(CONFIG_HARD_I2C) || \
- defined(CONFIG_SOFT_I2C)
+ defined(CONFIG_SYS_I2C)
#include <i2c.h>
#endif
/***********************************************************************/
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
static int init_func_i2c (void)
{
puts ("I2C: ");
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
puts ("ready\n");
return (0);
}
display_options,
checkcpu,
checkboard,
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
init_func_i2c,
#endif
#if defined(CONFIG_HARD_SPI)
spi_init_r ();
#endif
+#if defined(CONFIG_SYS_I2C)
+ /* Adjust I2C subsystem pointers after relocation */
+ i2c_reloc_fixup();
+#endif
+
/* relocate environment function pointers etc. */
env_relocate ();
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_SYS_I2C)
+#include <i2c.h>
+#endif
+
ulong monitor_flash_len;
/*
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
init_func_i2c,
#endif
dram_init, /* configure available RAM banks */
mmc_initialize(gd->bd);
#endif
+#if defined(CONFIG_SYS_I2C_ADAPTERS)
+ i2c_reloc_fixup();
+#endif
+
/* initialize environment */
env_relocate();
int i2c_set_bus_num(unsigned int bus)
{
-#if defined(CONFIG_I2C_MUX)
- if (bus < CONFIG_SYS_MAX_I2C_BUS) {
- i2c_bus_num = bus;
- } else {
- int ret;
-
- ret = i2x_mux_select_mux(bus);
- if (ret == 0)
- i2c_bus_num = bus;
- else
- return ret;
- }
-#else
if (bus >= CONFIG_SYS_MAX_I2C_BUS)
return -1;
i2c_bus_num = bus;
-#endif
return 0;
}
/* Initialize the I2C */
debug ("[VIDEO ENCODER] Initializing I2C bus...\n");
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
#ifdef CONFIG_FADS
/* Reset ADV7176 chip */
/*
* Set default values
*/
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 50000
-#endif
-
#define ONE_BILLION 1000000000
#define SDRAM0_CFG_DCE 0x80000000
* Make sure I2C controller is initialized
* before continuing.
*/
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
}
/* Make shure we are using SDRAM */
/*
* Set default values
*/
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 50000
-#endif
-
#define ONE_BILLION 1000000000
/*
* Make sure I2C controller is initialized
* before continuing.
*/
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
/*
* Read the SPD information using I2C interface. Check to see if the
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
* First switch to correct I2C bus. This is I2C bus 0
* for all currently available 4xx derivats.
*/
- I2C_SET_BUS(0);
+ i2c_set_bus_num(0);
#ifdef CONFIG_CMD_EEPROM
ret = eeprom_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
* before continuing.
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
#define IIC_TIMEOUT 1 /* 1 second */
-#if defined(CONFIG_I2C_MULTI_BUS)
-#define I2C_BUS_OFFS (i2c_bus_num * 0x100)
-#else
-#define I2C_BUS_OFFS (0x000)
-#endif /* CONFIG_I2C_MULTI_BUS */
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
-#elif defined(CONFIG_440) || defined(CONFIG_405EX)
-/* all remaining 440 variants */
-#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
-#else
-/* all 405 variants */
-#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
-#endif
-
struct ppc4xx_i2c {
u8 mdbuf;
u8 res1;
#if defined(CONFIG_CMD_DOC)
void doc_init(void);
#endif
-#if defined(CONFIG_HARD_I2C) || \
- defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
#include <i2c.h>
#endif
#include <spi.h>
/***********************************************************************/
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
static int init_func_i2c(void)
{
puts("I2C: ");
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
puts("ready\n");
return 0;
}
misc_init_f,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
init_func_i2c,
#endif
#if defined(CONFIG_HARD_SPI)
}
#endif
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
void i2c_init_board(void)
{
return rc;
}
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
void i2c_init_board(void)
{
u32 pin;
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
/* Initialise peripherals */
at91_seriald_hw_init();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
nand_hw_init();
macb_hw_init();
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
uchar buf[6];
char str[18];
char hostname[MODULE_NAME_MAXLEN];
" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
CONFIG_MAC_OFFSET);
}
-#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
+#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) */
if (!getenv("ethaddr"))
printf(LOG_PREFIX "MAC address not set, networking is not "
"operational\n");
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
*/
int pll_init(void)
{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
* However i2c_get_bus_num() cannot be called before
* relocation.
*/
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
void iic_init(void)
{
/* ports are now initialized in board_early_init_f() */
int iic_read(void)
{
- switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+ switch (I2C_ADAP_HWNR) {
case 0:
return at91_get_pio_value(I2C0_PORT, SDA0_PIN);
case 1:
void iic_sda(int bit)
{
- switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+ switch (I2C_ADAP_HWNR) {
case 0:
at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit);
break;
void iic_scl(int bit)
{
- switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+ switch (I2C_ADAP_HWNR) {
case 0:
at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit);
break;
return 0;
}
-#if defined(CONFIG_I2C_MULTI_BUS)
/*
* read field strength from I2C ADC
*/
"Initialize USB hub",
""
);
-#endif /* CONFIG_I2C_MULTI_BUS */
#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
int boot_eeprom_write (unsigned dev_addr,
int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
- int old_bus = I2C_GET_BUS();
+ int old_bus = i2c_get_bus_num();
unsigned int l, sum;
int valid = 0;
- I2C_SET_BUS(0);
+ i2c_set_bus_num(0);
if (i2c_read(chip, addr, alen, buffer, len) == 0)
if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
buffer[63] = sum;
}
- I2C_SET_BUS(old_bus);
+ i2c_set_bus_num(old_bus);
return 0;
}
}
#endif
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
void i2c_init_board(void)
{
u32 pin;
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
-CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
-CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
-CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
-CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
-CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
-CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
-CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
-CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_SLTTMR -- define to use SLT timer
-CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
-CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
{
int rc = 0;
-#ifdef CONFIG_HARD_I2C
-
+#if defined(CONFIG_SYS_I2C)
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
#endif
u8 reg8;
-#ifdef CONFIG_HARD_I2C
+#if defined(CONFIG_SYS_I2C)
i2c_set_bus_num(1);
/* Read the PCI_M66EN jumper setting */
if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
in_8(&cpld_data->pcba_rev) & 0x0F);
/* Initialize i2c early for rom_loc and flash bank information */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
+#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
}
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c0_pads[] = {
+ VF610_PAD_PTB14__I2C0_SCL,
+ VF610_PAD_PTB15__I2C0_SDA,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
CCM_CCGR3_ANADIG_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
- CCM_CCGR4_GPC_CTRL_MASK);
+ CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
setup_iomux_uart();
setup_iomux_enet();
+ setup_iomux_i2c();
return 0;
}
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
/* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
#else /* normal I/O port pins */
int ivm_read_eeprom(void)
{
-#if defined(CONFIG_I2C_MUX)
- I2C_MUX_DEVICE *dev = NULL;
-#endif
uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
- uchar *buf;
- unsigned long dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
int ret;
-#if defined(CONFIG_I2C_MUX)
- /* First init the Bus, select the Bus */
- buf = (unsigned char *) getenv("EEprom_ivm");
- if (buf != NULL)
- dev = i2c_mux_ident_muxstring(buf);
- if (dev == NULL) {
- printf("Error couldnt add Bus for IVM\n");
- return -1;
- }
- i2c_set_bus_num(dev->busid);
-#endif
+ i2c_set_bus_num(CONFIG_KM_IVM_BUS);
/* add deblocking here */
i2c_make_abort();
- ret = i2c_read(dev_addr, 0, 1, i2c_buffer,
+ ret = i2c_read(CONFIG_SYS_IVM_EEPROM_ADR, 0, 1, i2c_buffer,
CONFIG_SYS_IVM_EEPROM_MAX_LEN);
if (ret != 0) {
printf("Error reading EEprom\n");
{0, 0, 0, 0, QE_IOP_TAB_END},
};
-static int board_init_i2c_busses(void)
-{
- I2C_MUX_DEVICE *dev = NULL;
- uchar *dtt_bus = (uchar *)"pca9547:70:a";
-
- /* Set up the Bus for the DTTs */
- dev = i2c_mux_ident_muxstring(dtt_bus);
- if (dev == NULL)
- printf("Error couldn't add Bus for DTT\n");
-
- return 0;
-}
-
#if defined(CONFIG_SUVD3)
const uint upma_table[] = {
0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
int misc_init_r(void)
{
- /* add board specific i2c busses */
- board_init_i2c_busses();
return 0;
}
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_PEX_RST_OUTn,
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
MPP8_GPIO, /* SDA */
MPP9_GPIO, /* SCL */
#endif
int board_early_init_f(void)
{
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
u32 tmp;
/* set the 2 bitbang i2c pins as output gpios */
kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/*
* Reinit the GPIO for I2C Bitbang driver so that the now
* available gpio framework is consistent. The calls to
}
#endif
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
void set_sda(int state)
{
I2C_ACTIVE;
uchar val, errcd;
int i;
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
gd->arch.kbd_status = 0;
/* switch VCC on */
val |= MAX1604_OP_SUS | MAX1604_VCCBON;
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
udelay(500000);
*/
debug ("PCMCIA power OFF\n");
val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
val = 0;
uchar val, errcd;
int i;
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
gd->arch.kbd_status = 0;
#endif
/* Read Serial Presence Detect Information */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
for (i = 0; i < 128; i++)
datain[i] = 127;
i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
power_det_init();
-#ifdef CONFIG_TEGRA_I2C
+#ifdef CONFIG_SYS_I2C_TEGRA
#ifndef CONFIG_SYS_I2C_INIT_BOARD
#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
#endif
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
-#endif /* CONFIG_TEGRA_I2C */
+#endif /* CONFIG_SYS_I2C_TEGRA */
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_usb();
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
/* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */
/* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */
#endif
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */
/* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */
#else
+++ /dev/null
-/*
- * Copyright (C) 2005 Sandburst Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Ported from arch/powerpc/cpu/ppc4xx/i2c.c by AS HARNOIS by
- * Travis B. Sawyer
- * Sandburst Corporation.
- */
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-i2c.h>
-#include <i2c.h>
-#include <command.h>
-#include "ppc440gx_i2c.h"
-#include <asm/io.h>
-
-#ifdef CONFIG_I2C_BUS1
-
-#define IIC_OK 0
-#define IIC_NOK 1
-#define IIC_NOK_LA 2 /* Lost arbitration */
-#define IIC_NOK_ICT 3 /* Incomplete transfer */
-#define IIC_NOK_XFRA 4 /* Transfer aborted */
-#define IIC_NOK_DATA 5 /* No data in buffer */
-#define IIC_NOK_TOUT 6 /* Transfer timeout */
-
-#define IIC_TIMEOUT 1 /* 1 second */
-#if defined(CONFIG_SYS_I2C_NOPROBES)
-static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
-#endif
-
-static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS;
-
-static void _i2c_bus1_reset (void)
-{
- int i, status;
-
- /* Reset status register */
- /* write 1 in SCMP and IRQA to clear these fields */
- out_8 (IIC_STS1, 0x0A);
-
- /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
- out_8 (IIC_EXTSTS1, 0x8F);
- __asm__ volatile ("eieio");
-
- /*
- * Get current state, reset bus
- * only if no transfers are pending.
- */
- i = 10;
- do {
- /* Get status */
- status = in_8 (IIC_STS1);
- udelay (500); /* 500us */
- i--;
- } while ((status & IIC_STS_PT) && (i > 0));
- /* Soft reset controller */
- status = in_8 (IIC_XTCNTLSS1);
- out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
- __asm__ volatile ("eieio");
-
- /* make sure where in initial state, data hi, clock hi */
- out_8 (IIC_DIRECTCNTL1, 0xC);
- for (i = 0; i < 10; i++) {
- if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
- /* clock until we get to known state */
- out_8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
- udelay (100); /* 100us */
- out_8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
- udelay (100); /* 100us */
- } else {
- break;
- }
- }
- /* send start condition */
- out_8 (IIC_DIRECTCNTL1, 0x4);
- udelay (1000); /* 1ms */
- /* send stop condition */
- out_8 (IIC_DIRECTCNTL1, 0xC);
- udelay (1000); /* 1ms */
- /* Unreset controller */
- out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
- udelay (1000); /* 1ms */
-}
-
-void i2c1_init (int speed, int slaveadd)
-{
- sys_info_t sysInfo;
- unsigned long freqOPB;
- int val, divisor;
-
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* call board specific i2c bus reset routine before accessing the */
- /* environment, which might be in a chip on that bus. For details */
- /* about this problem see doc/I2C_Edge_Conditions. */
- i2c_init_board();
-#endif
-
- /* Handle possible failed I2C state */
- /* FIXME: put this into i2c_init_board()? */
- _i2c_bus1_reset ();
-
- /* clear lo master address */
- out_8 (IIC_LMADR1, 0);
-
- /* clear hi master address */
- out_8 (IIC_HMADR1, 0);
-
- /* clear lo slave address */
- out_8 (IIC_LSADR1, 0);
-
- /* clear hi slave address */
- out_8 (IIC_HSADR1, 0);
-
- /* Clock divide Register */
- /* get OPB frequency */
- get_sys_info (&sysInfo);
- freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
- /* set divisor according to freqOPB */
- divisor = (freqOPB - 1) / 10000000;
- if (divisor == 0)
- divisor = 1;
- out_8 (IIC_CLKDIV1, divisor);
-
- /* no interrupts */
- out_8 (IIC_INTRMSK1, 0);
-
- /* clear transfer count */
- out_8 (IIC_XFRCNT1, 0);
-
- /* clear extended control & stat */
- /* write 1 in SRC SRS SWC SWS to clear these fields */
- out_8 (IIC_XTCNTLSS1, 0xF0);
-
- /* Mode Control Register
- Flush Slave/Master data buffer */
- out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
- __asm__ volatile ("eieio");
-
-
- val = in_8(IIC_MDCNTL1);
- __asm__ volatile ("eieio");
-
- /* Ignore General Call, slave transfers are ignored,
- disable interrupts, exit unknown bus state, enable hold
- SCL
- 100kHz normaly or FastMode for 400kHz and above
- */
-
- val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
- if( speed >= 400000 ){
- val |= IIC_MDCNTL_FSM;
- }
- out_8 (IIC_MDCNTL1, val);
-
- /* clear control reg */
- out_8 (IIC_CNTL1, 0x00);
- __asm__ volatile ("eieio");
-
-}
-
-/*
- This code tries to use the features of the 405GP i2c
- controller. It will transfer up to 4 bytes in one pass
- on the loop. It only does out_8(lbz) to the buffer when it
- is possible to do out16(lhz) transfers.
-
- cmd_type is 0 for write 1 for read.
-
- addr_len can take any value from 0-255, it is only limited
- by the char, we could make it larger if needed. If it is
- 0 we skip the address write cycle.
-
- Typical case is a Write of an addr followd by a Read. The
- IBM FAQ does not cover this. On the last byte of the write
- we don't set the creg CHT bit, and on the first bytes of the
- read we set the RPST bit.
-
- It does not support address only transfers, there must be
- a data part. If you want to write the address yourself, put
- it in the data pointer.
-
- It does not support transfer to/from address 0.
-
- It does not check XFRCNT.
-*/
-static
-int i2c_transfer1(unsigned char cmd_type,
- unsigned char chip,
- unsigned char addr[],
- unsigned char addr_len,
- unsigned char data[],
- unsigned short data_len )
-{
- unsigned char* ptr;
- int reading;
- int tran,cnt;
- int result;
- int status;
- int i;
- uchar creg;
-
- if( data == 0 || data_len == 0 ){
- /*Don't support data transfer of no length or to address 0*/
- printf( "i2c_transfer: bad call\n" );
- return IIC_NOK;
- }
- if( addr && addr_len ){
- ptr = addr;
- cnt = addr_len;
- reading = 0;
- }else{
- ptr = data;
- cnt = data_len;
- reading = cmd_type;
- }
-
- /*Clear Stop Complete Bit*/
- out_8(IIC_STS1,IIC_STS_SCMP);
- /* Check init */
- i=10;
- do {
- /* Get status */
- status = in_8(IIC_STS1);
- __asm__ volatile("eieio");
- i--;
- } while ((status & IIC_STS_PT) && (i>0));
-
- if (status & IIC_STS_PT) {
- result = IIC_NOK_TOUT;
- return(result);
- }
- /*flush the Master/Slave Databuffers*/
- out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
- /*need to wait 4 OPB clocks? code below should take that long*/
-
- /* 7-bit adressing */
- out_8(IIC_HMADR1,0);
- out_8(IIC_LMADR1, chip);
- __asm__ volatile("eieio");
-
- tran = 0;
- result = IIC_OK;
- creg = 0;
-
- while ( tran != cnt && (result == IIC_OK)) {
- int bc,j;
-
- /* Control register =
- Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
- Transfer is a sequence of transfers
- */
- creg |= IIC_CNTL_PT;
-
- bc = (cnt - tran) > 4 ? 4 :
- cnt - tran;
- creg |= (bc-1)<<4;
- /* if the real cmd type is write continue trans*/
- if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
- creg |= IIC_CNTL_CHT;
-
- if (reading)
- creg |= IIC_CNTL_READ;
- else {
- for(j=0; j<bc; j++) {
- /* Set buffer */
- out_8(IIC_MDBUF1,ptr[tran+j]);
- __asm__ volatile("eieio");
- }
- }
- out_8(IIC_CNTL1, creg );
- __asm__ volatile("eieio");
-
- /* Transfer is in progress
- we have to wait for upto 5 bytes of data
- 1 byte chip address+r/w bit then bc bytes
- of data.
- udelay(10) is 1 bit time at 100khz
- Doubled for slop. 20 is too small.
- */
- i=2*5*8;
- do {
- /* Get status */
- status = in_8(IIC_STS1);
- __asm__ volatile("eieio");
- udelay (10);
- i--;
- } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
- && (i>0));
-
- if (status & IIC_STS_ERR) {
- result = IIC_NOK;
- status = in_8 (IIC_EXTSTS1);
- /* Lost arbitration? */
- if (status & IIC_EXTSTS_LA)
- result = IIC_NOK_LA;
- /* Incomplete transfer? */
- if (status & IIC_EXTSTS_ICT)
- result = IIC_NOK_ICT;
- /* Transfer aborted? */
- if (status & IIC_EXTSTS_XFRA)
- result = IIC_NOK_XFRA;
- } else if ( status & IIC_STS_PT) {
- result = IIC_NOK_TOUT;
- }
- /* Command is reading => get buffer */
- if ((reading) && (result == IIC_OK)) {
- /* Are there data in buffer */
- if (status & IIC_STS_MDBS) {
- /*
- even if we have data we have to wait 4OPB clocks
- for it to hit the front of the FIFO, after that
- we can just read. We should check XFCNT here and
- if the FIFO is full there is no need to wait.
- */
- udelay (1);
- for(j=0;j<bc;j++) {
- ptr[tran+j] = in_8(IIC_MDBUF1);
- __asm__ volatile("eieio");
- }
- } else
- result = IIC_NOK_DATA;
- }
- creg = 0;
- tran+=bc;
- if( ptr == addr && tran == cnt ) {
- ptr = data;
- cnt = data_len;
- tran = 0;
- reading = cmd_type;
- if( reading )
- creg = IIC_CNTL_RPST;
- }
- }
- return (result);
-}
-
-int i2c_probe1 (uchar chip)
-{
- uchar buf[1];
-
- buf[0] = 0;
-
- /*
- * What is needed is to send the chip address and verify that the
- * address was <ACK>ed (i.e. there was a chip at that address which
- * drove the data line low).
- */
- return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
-}
-
-
-int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- uchar xaddr[4];
- int ret;
-
- if ( alen > 4 ) {
- printf ("I2C read: addr len %d not supported\n", alen);
- return 1;
- }
-
- if ( alen > 0 ) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
-
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
- *
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
- */
- if( alen > 0 )
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-#endif
- if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
- printf( "I2c read: failed %d\n", ret);
- return 1;
- }
- return 0;
-}
-
-int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- uchar xaddr[4];
-
- if ( alen > 4 ) {
- printf ("I2C write: addr len %d not supported\n", alen);
- return 1;
-
- }
- if ( alen > 0 ) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
- *
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
- */
- if( alen > 0 )
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-#endif
-
- return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
-}
-
-/*-----------------------------------------------------------------------
- * Read a register
- */
-uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
-{
- uchar buf;
-
- i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
-
- return(buf);
-}
-
-/*-----------------------------------------------------------------------
- * Write a register
- */
-void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
-{
- i2c_write1(i2c_addr, reg, 1, &val, 1);
-}
-
-
-int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int j;
-#if defined(CONFIG_SYS_I2C_NOPROBES)
- int k, skip;
-#endif
-
- puts ("Valid chip addresses:");
- for(j = 0; j < 128; j++) {
-#if defined(CONFIG_SYS_I2C_NOPROBES)
- skip = 0;
- for (k = 0; k < sizeof(i2c_no_probes); k++){
- if (j == i2c_no_probes[k]){
- skip = 1;
- break;
- }
- }
- if (skip)
- continue;
-#endif
- if(i2c_probe1(j) == 0) {
- printf(" %02X", j);
- }
- }
- putc ('\n');
-
-#if defined(CONFIG_SYS_I2C_NOPROBES)
- puts ("Excluded chip addresses:");
- for( k = 0; k < sizeof(i2c_no_probes); k++ )
- printf(" %02X", i2c_no_probes[k] );
- putc ('\n');
-#endif
-
- return 0;
-}
-
-U_BOOT_CMD(
- iprobe1, 1, 1, do_i2c1_probe,
- "probe to discover valid I2C chip addresses",
- ""
-);
-
-#endif /* CONFIG_I2C_BUS1 */
+++ /dev/null
-/*
- * Copyright (C) 2005 Sandburst Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Ported from i2c driver for ppc4xx by AS HARNOIS by
- * Travis B. Sawyer
- * Sandburst Corporation
- */
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-i2c.h>
-#include <i2c.h>
-
-#ifdef CONFIG_HARD_I2C
-
-#define I2C_BUS1_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
-#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
-#define IIC_MDBUF1 (&i2c->mdbuf)
-#define IIC_SDBUF1 (&i2c->sdbuf)
-#define IIC_LMADR1 (&i2c->lmadr)
-#define IIC_HMADR1 (&i2c->hmadr)
-#define IIC_CNTL1 (&i2c->cntl)
-#define IIC_MDCNTL1 (&i2c->mdcntl)
-#define IIC_STS1 (&i2c->sts)
-#define IIC_EXTSTS1 (&i2c->extsts)
-#define IIC_LSADR1 (&i2c->lsadr)
-#define IIC_HSADR1 (&i2c->hsadr)
-#define IIC_CLKDIV1 (&i2c->clkdiv)
-#define IIC_INTRMSK1 (&i2c->intrmsk)
-#define IIC_XFRCNT1 (&i2c->xfrcnt)
-#define IIC_XTCNTLSS1 (&i2c->xtcntlss)
-#define IIC_DIRECTCNTL1 (&i2c->directcntl)
-
-void i2c1_init (int speed, int slaveadd);
-int i2c_probe1 (uchar chip);
-int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
-int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
-uchar i2c_reg_read1(uchar i2c_addr, uchar reg);
-void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val);
-
-#endif /* CONFIG_HARD_I2C */
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
-#include "ppc440gx_i2c.h"
#include "sb_common.h"
DECLARE_GLOBAL_DATA_PTR;
/* Get the board serial number from eeprom */
/* Initialize I2C */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
/* Read 256 bytes in EEPROM */
i2c_read (0x50, 0, 1, buff, 0x100);
* Attempt to turn on 2 of the fans...
* Need to go through the bridge
*/
+ i2c_set_bus_num(1);
puts ("FANS: ");
/* select fan4 through the bridge */
- i2c_reg_write1(0x73, /* addr */
- 0x00, /* reg */
- 0x08); /* val = bus 4 */
+ i2c_reg_write(0x73, /* addr */
+ 0x00, /* reg */
+ 0x08); /* val = bus 4 */
/* Turn on FAN 4 */
- i2c_reg_write1(0x2e,
- 1,
- 0x80);
+ i2c_reg_write(0x2e,
+ 1,
+ 0x80);
- i2c_reg_write1(0x2e,
- 0,
- 0x19);
+ i2c_reg_write(0x2e,
+ 0,
+ 0x19);
/* Deselect bus 4 on the bridge */
- i2c_reg_write1(0x73,
- 0x00,
- 0x00);
+ i2c_reg_write(0x73,
+ 0x00,
+ 0x00);
/* select fan3 through the bridge */
- i2c_reg_write1(0x73, /* addr */
- 0x00, /* reg */
- 0x04); /* val = bus 3 */
+ i2c_reg_write(0x73, /* addr */
+ 0x00, /* reg */
+ 0x04); /* val = bus 3 */
/* Turn on FAN 3 */
- i2c_reg_write1(0x2e,
- 1,
- 0x80);
+ i2c_reg_write(0x2e,
+ 1,
+ 0x80);
- i2c_reg_write1(0x2e,
- 0,
- 0x19);
+ i2c_reg_write(0x2e,
+ 0,
+ 0x19);
/* Deselect bus 3 on the bridge */
- i2c_reg_write1(0x73,
- 0x00,
- 0x00);
+ i2c_reg_write(0x73,
+ 0x00,
+ 0x00);
/* select fan2 through the bridge */
- i2c_reg_write1(0x73, /* addr */
- 0x00, /* reg */
- 0x02); /* val = bus 4 */
+ i2c_reg_write(0x73, /* addr */
+ 0x00, /* reg */
+ 0x02); /* val = bus 4 */
/* Turn on FAN 2 */
- i2c_reg_write1(0x2e,
- 1,
- 0x80);
+ i2c_reg_write(0x2e,
+ 1,
+ 0x80);
- i2c_reg_write1(0x2e,
- 0,
- 0x19);
+ i2c_reg_write(0x2e,
+ 0,
+ 0x19);
/* Deselect bus 2 on the bridge */
- i2c_reg_write1(0x73,
- 0x00,
- 0x00);
+ i2c_reg_write(0x73,
+ 0x00,
+ 0x00);
/* select fan1 through the bridge */
- i2c_reg_write1(0x73, /* addr */
- 0x00, /* reg */
- 0x01); /* val = bus 0 */
+ i2c_reg_write(0x73, /* addr */
+ 0x00, /* reg */
+ 0x01); /* val = bus 0 */
/* Turn on FAN 1 */
- i2c_reg_write1(0x2e,
- 1,
- 0x80);
+ i2c_reg_write(0x2e,
+ 1,
+ 0x80);
- i2c_reg_write1(0x2e,
- 0,
- 0x19);
+ i2c_reg_write(0x2e,
+ 0,
+ 0x19);
/* Deselect bus 1 on the bridge */
- i2c_reg_write1(0x73,
- 0x00,
- 0x00);
+ i2c_reg_write(0x73,
+ 0x00,
+ 0x00);
puts ("on\n");
+ i2c_set_bus_num(0);
return;
if (0 == macaddr_idx) {
/* Initialize I2C */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
/* Read 256 bytes in EEPROM */
i2c_read (0x50, 0, 1, buff, 0x100);
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
-#include "ppc440gx_i2c.h"
/*
* GPIO Settings
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
- ../common/sb_common.o
+COBJS = $(BOARD).o ../common/flash.o ../common/sb_common.o
SOBJS = init.o
#include <spd_sdram.h>
#include <i2c.h>
#include "../common/sb_common.h"
-#include "../common/ppc440gx_i2c.h"
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
#include <net.h>
************************************************************************/
int misc_init_f (void)
{
- /* Turn on i2c bus 1 */
- puts ("I2C1: ");
- i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- puts ("ready\n");
-
/* Turn on fans 3 & 4 */
sbcommon_fans();
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
- ../common/sb_common.o
+COBJS = $(BOARD).o ../common/flash.o ../common/sb_common.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
-#include "../common/ppc440gx_i2c.h"
#include "../common/sb_common.h"
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
************************************************************************/
int misc_init_f (void)
{
- /* Turn on i2c bus 1 */
- puts ("I2C1: ");
- i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- puts ("ready\n");
-
/* Turn on fans */
sbcommon_fans();
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
0, 0, 0, 0, 0, 0};
-#endif
+#endif /* __CONFIG_H */
void dram_init_banksize(void)
__attribute__((weak, alias("__dram_init_banksize")));
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
static int init_func_i2c(void)
{
puts("I2C: ");
misc_init_f,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
init_func_i2c,
#endif
#if defined(CONFIG_HARD_SPI)
int old_bus;
/* switch to correct I2C bus */
+#ifdef CONFIG_SYS_I2C
+ old_bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
+#else
old_bus = I2C_GET_BUS();
I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
+#endif
switch (argc) {
case 2: /* set date & time */
}
/* switch back to original I2C bus */
+#ifdef CONFIG_SYS_I2C
+ i2c_set_bus_num(old_bus);
+#else
I2C_SET_BUS(old_bus);
+#endif
return rcode;
}
/* Force a compilation error, if there are more then 32 sensors */
BUILD_BUG_ON(sizeof(sensors) > 32);
/* switch to correct I2C bus */
+#ifdef CONFIG_SYS_I2C
+ old_bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_DTT_BUS_NUM);
+#else
old_bus = I2C_GET_BUS();
I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM);
+#endif
_initialize_dtt();
printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i]));
/* switch back to original I2C bus */
+#ifdef CONFIG_SYS_I2C
+ i2c_set_bus_num(old_bus);
+#else
I2C_SET_BUS(old_bus);
+#endif
#endif
return 0;
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_init_f ();
#endif
-#if defined(CONFIG_HARD_I2C) || \
- defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
/*
+ * (C) Copyright 2009
+ * Sergey Kubushyn, himself, ksi@koi8.net
+ *
+ * Changes for unified multibus/multiadapter I2C support.
+ *
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
#include <asm/byteorder.h>
#include <linux/compiler.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* Display values from last command.
* Memory modify remembered values are different from display memory.
*/
* pairs. The following macros take care of this */
#if defined(CONFIG_SYS_I2C_NOPROBES)
-#if defined(CONFIG_I2C_MULTI_BUS)
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
static struct
{
uchar bus;
#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
-#endif /* CONFIG_MULTI_BUS */
-
-#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
-#endif
-
-#if defined(CONFIG_I2C_MUX)
-static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
-static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
-
-DECLARE_GLOBAL_DATA_PTR;
-
+#endif /* defined(CONFIG_SYS_I2C) */
#endif
#define DISP_LINE_LEN 16
__weak
void i2c_init_board(void)
{
- return;
}
/* TODO: Implement architecture-specific get/set functions */
*
* Returns I2C bus speed in Hz.
*/
+#if !defined(CONFIG_SYS_I2C)
+/*
+ * TODO: Implement architecture-specific get/set functions
+ * Should go away, if we switched completely to new multibus support
+ */
__weak
unsigned int i2c_get_bus_speed(void)
{
return 0;
}
+#endif
/**
* get_alen() - Small parser helper function to get address length
int found = 0;
#if defined(CONFIG_SYS_I2C_NOPROBES)
int k, skip;
- uchar bus = GET_BUS_NUM;
+ unsigned int bus = GET_BUS_NUM;
#endif /* NOPROBES */
if (argc == 2)
#if defined(CONFIG_SYS_I2C_NOPROBES)
skip = 0;
- for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
+ for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
skip = 1;
break;
#if defined(CONFIG_SYS_I2C_NOPROBES)
puts ("Excluded chip addresses:");
- for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
+ for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
if (COMPARE_BUS(bus,k))
printf(" %02X", NO_PROBE_ADDR(k));
}
}
#endif /* CONFIG_I2C_EDID */
-#if defined(CONFIG_I2C_MUX)
/**
- * do_i2c_add_bus() - Handle the "i2c bus" command-line command
+ * do_i2c_show_bus() - Handle the "i2c bus" command-line command
* @cmdtp: Command data struct pointer
* @flag: Command flag
* @argc: Command-line argument count
*
* Returns zero always.
*/
-static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+#if defined(CONFIG_SYS_I2C)
+int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int ret=0;
+ int i;
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+ int j;
+#endif
if (argc == 1) {
/* show all busses */
- I2C_MUX *mux;
- I2C_MUX_DEVICE *device = i2c_mux_devices;
-
- printf ("Busses reached over muxes:\n");
- while (device != NULL) {
- printf ("Bus ID: %x\n", device->busid);
- printf (" reached over Mux(es):\n");
- mux = device->mux;
- while (mux != NULL) {
- printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
- mux = mux->next;
+ for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
+ printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+ for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
+ if (i2c_bus[i].next_hop[j].chip == 0)
+ break;
+ printf("->%s@0x%2x:%d",
+ i2c_bus[i].next_hop[j].mux.name,
+ i2c_bus[i].next_hop[j].chip,
+ i2c_bus[i].next_hop[j].channel);
}
- device = device->next;
+#endif
+ printf("\n");
}
} else {
- (void)i2c_mux_ident_muxstring ((uchar *)argv[1]);
- ret = 0;
+ /* show specific bus */
+ i = simple_strtoul(argv[1], NULL, 10);
+ if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
+ printf("Invalid bus %d\n", i);
+ return -1;
+ }
+ printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+ for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
+ if (i2c_bus[i].next_hop[j].chip == 0)
+ break;
+ printf("->%s@0x%2x:%d",
+ i2c_bus[i].next_hop[j].mux.name,
+ i2c_bus[i].next_hop[j].chip,
+ i2c_bus[i].next_hop[j].channel);
+ }
+#endif
+ printf("\n");
}
- return ret;
+
+ return 0;
}
-#endif /* CONFIG_I2C_MUX */
+#endif
-#if defined(CONFIG_I2C_MULTI_BUS)
/**
* do_i2c_bus_num() - Handle the "i2c dev" command-line command
* @cmdtp: Command data struct pointer
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
-static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
+int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int bus_idx, ret=0;
+ int ret = 0;
+ unsigned int bus_no;
if (argc == 1)
/* querying current setting */
printf("Current bus is %d\n", i2c_get_bus_num());
else {
- bus_idx = simple_strtoul(argv[1], NULL, 10);
- printf("Setting bus to %d\n", bus_idx);
- ret = i2c_set_bus_num(bus_idx);
+ bus_no = simple_strtoul(argv[1], NULL, 10);
+ if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
+ printf("Invalid bus %d\n", bus_no);
+ return -1;
+ }
+ printf("Setting bus to %d\n", bus_no);
+ ret = i2c_set_bus_num(bus_no);
if (ret)
printf("Failure changing bus number (%d)\n", ret);
}
return ret;
}
-#endif /* CONFIG_I2C_MULTI_BUS */
+#endif /* defined(CONFIG_SYS_I2C) */
/**
* do_i2c_bus_speed() - Handle the "i2c speed" command-line command
*/
static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
+#if defined(CONFIG_SYS_I2C)
+ i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
+#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
return 0;
}
static cmd_tbl_t cmd_i2c_sub[] = {
-#if defined(CONFIG_I2C_MUX)
- U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
-#endif /* CONFIG_I2C_MUX */
+#if defined(CONFIG_SYS_I2C)
+ U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
+#endif
U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
-#if defined(CONFIG_I2C_MULTI_BUS)
+#if defined(CONFIG_SYS_I2C) || \
+ defined(CONFIG_I2C_MULTI_BUS)
U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
#endif /* CONFIG_I2C_MULTI_BUS */
#if defined(CONFIG_I2C_EDID)
/***************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char i2c_help_text[] =
-#if defined(CONFIG_I2C_MUX)
- "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
-#endif /* CONFIG_I2C_MUX */
+#if defined(CONFIG_SYS_I2C)
+ "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
+#endif
"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
-#if defined(CONFIG_I2C_MULTI_BUS)
+#if defined(CONFIG_SYS_I2C) || \
+ defined(CONFIG_I2C_MULTI_BUS)
"i2c dev [dev] - show or set current I2C bus\n"
#endif /* CONFIG_I2C_MULTI_BUS */
#if defined(CONFIG_I2C_EDID)
"I2C sub-system",
i2c_help_text
);
-
-#if defined(CONFIG_I2C_MUX)
-static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
-{
- I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
-
- if (i2c_mux_devices == NULL) {
- i2c_mux_devices = dev;
- return 0;
- }
- while (devtmp->next != NULL)
- devtmp = devtmp->next;
-
- devtmp->next = dev;
- return 0;
-}
-
-I2C_MUX_DEVICE *i2c_mux_search_device(int id)
-{
- I2C_MUX_DEVICE *device = i2c_mux_devices;
-
- while (device != NULL) {
- if (device->busid == id)
- return device;
- device = device->next;
- }
- return NULL;
-}
-
-/* searches in the buf from *pos the next ':'.
- * returns:
- * 0 if found (with *pos = where)
- * < 0 if an error occured
- * > 0 if the end of buf is reached
- */
-static int i2c_mux_search_next (int *pos, uchar *buf, int len)
-{
- while ((buf[*pos] != ':') && (*pos < len)) {
- *pos += 1;
- }
- if (*pos >= len)
- return 1;
- if (buf[*pos] != ':')
- return -1;
- return 0;
-}
-
-static int i2c_mux_get_busid (void)
-{
- int tmp = i2c_mux_busid;
-
- i2c_mux_busid ++;
- return tmp;
-}
-
-/* Analyses a Muxstring and immediately sends the
- commands to the muxes. Runs from flash.
- */
-int i2c_mux_ident_muxstring_f (uchar *buf)
-{
- int pos = 0;
- int oldpos;
- int ret = 0;
- int len = strlen((char *)buf);
- int chip;
- uchar channel;
- int was = 0;
-
- while (ret == 0) {
- oldpos = pos;
- /* search name */
- ret = i2c_mux_search_next(&pos, buf, len);
- if (ret != 0)
- printf ("ERROR\n");
- /* search address */
- pos ++;
- oldpos = pos;
- ret = i2c_mux_search_next(&pos, buf, len);
- if (ret != 0)
- printf ("ERROR\n");
- buf[pos] = 0;
- chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
- buf[pos] = ':';
- /* search channel */
- pos ++;
- oldpos = pos;
- ret = i2c_mux_search_next(&pos, buf, len);
- if (ret < 0)
- printf ("ERROR\n");
- was = 0;
- if (buf[pos] != 0) {
- buf[pos] = 0;
- was = 1;
- }
- channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
- if (was)
- buf[pos] = ':';
- if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
- printf ("Error setting Mux: chip:%x channel: \
- %x\n", chip, channel);
- return -1;
- }
- pos ++;
- oldpos = pos;
-
- }
- i2c_init_board();
-
- return 0;
-}
-
-/* Analyses a Muxstring and if this String is correct
- * adds a new I2C Bus.
- */
-I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
-{
- I2C_MUX_DEVICE *device;
- I2C_MUX *mux;
- int pos = 0;
- int oldpos;
- int ret = 0;
- int len = strlen((char *)buf);
- int was = 0;
-
- device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
- device->mux = NULL;
- device->busid = i2c_mux_get_busid ();
- device->next = NULL;
- while (ret == 0) {
- mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
- mux->next = NULL;
- /* search name of mux */
- oldpos = pos;
- ret = i2c_mux_search_next(&pos, buf, len);
- if (ret != 0)
- printf ("%s no name.\n", __FUNCTION__);
- mux->name = (char *)malloc (pos - oldpos + 1);
- memcpy (mux->name, &buf[oldpos], pos - oldpos);
- mux->name[pos - oldpos] = 0;
- /* search address */
- pos ++;
- oldpos = pos;
- ret = i2c_mux_search_next(&pos, buf, len);
- if (ret != 0)
- printf ("%s no mux address.\n", __FUNCTION__);
- buf[pos] = 0;
- mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
- buf[pos] = ':';
- /* search channel */
- pos ++;
- oldpos = pos;
- ret = i2c_mux_search_next(&pos, buf, len);
- if (ret < 0)
- printf ("%s no mux channel.\n", __FUNCTION__);
- was = 0;
- if (buf[pos] != 0) {
- buf[pos] = 0;
- was = 1;
- }
- mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
- if (was)
- buf[pos] = ':';
- if (device->mux == NULL)
- device->mux = mux;
- else {
- I2C_MUX *muxtmp = device->mux;
- while (muxtmp->next != NULL) {
- muxtmp = muxtmp->next;
- }
- muxtmp->next = mux;
- }
- pos ++;
- oldpos = pos;
- }
- if (ret > 0) {
- /* Add Device */
- i2c_mux_add_device (device);
- return device;
- }
-
- return NULL;
-}
-
-int i2x_mux_select_mux(int bus)
-{
- I2C_MUX_DEVICE *dev;
- I2C_MUX *mux;
-
- if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
- /* select Default Mux Bus */
-#if defined(CONFIG_SYS_I2C_IVM_BUS)
- i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
-#else
- {
- unsigned char *buf;
- buf = (unsigned char *) getenv("EEprom_ivm");
- if (buf != NULL)
- i2c_mux_ident_muxstring_f (buf);
- }
-#endif
- return 0;
- }
- dev = i2c_mux_search_device(bus);
- if (dev == NULL)
- return -1;
-
- mux = dev->mux;
- while (mux != NULL) {
- /* do deblocking on each level of mux, before mux config */
- i2c_init_board();
- if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
- printf ("Error setting Mux: chip:%x channel: \
- %x\n", mux->chip, mux->channel);
- return -1;
- }
- mux = mux->next;
- }
- /* do deblocking on each level of mux and after mux config */
- i2c_init_board();
- return 0;
-}
-#endif /* CONFIG_I2C_MUX */
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
int old_bus = i2c_get_bus_num();
- if (gd->flags & GD_FLG_RELOC) {
- if (env_eeprom_bus == -1) {
- I2C_MUX_DEVICE *dev = NULL;
- dev = i2c_mux_ident_muxstring(
- (uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
- if (dev != NULL)
- env_eeprom_bus = dev->busid;
- else
- printf("error adding env eeprom bus.\n");
- }
- if (old_bus != env_eeprom_bus) {
- i2c_set_bus_num(env_eeprom_bus);
- old_bus = env_eeprom_bus;
- }
- } else {
- rcode = i2c_mux_ident_muxstring_f(
- (uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
- }
+ if (old_bus != CONFIG_I2C_ENV_EEPROM_BUS)
+ i2c_set_bus_num(CONFIG_I2C_ENV_EEPROM_BUS);
#endif
rcode = eeprom_read(dev_addr, offset, buffer, cnt);
if (old_bus != env_eeprom_bus)
i2c_set_bus_num(old_bus);
#endif
+
return rcode;
}
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
int old_bus = i2c_get_bus_num();
- rcode = i2c_mux_ident_muxstring_f((uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
+ if (old_bus != CONFIG_I2C_ENV_EEPROM_BUS)
+ i2c_set_bus_num(CONFIG_I2C_ENV_EEPROM_BUS);
#endif
+
rcode = eeprom_write(dev_addr, offset, buffer, cnt);
+
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
i2c_set_bus_num(old_bus);
#endif
/*
+ * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Changes for multibus/multiadapter I2C support.
+ *
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*
#ifdef CONFIG_LOGBUFFER
#include <logbuff.h>
#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
#include <i2c.h>
#endif
#ifdef CONFIG_ARM_DCC
drv_arm_dcc_init ();
#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
+#if defined(CONFIG_HARD_I2C)
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
+#endif
#ifdef CONFIG_LCD
drv_lcd_init ();
#endif
COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
-COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
-COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o
COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
-COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
-COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
+COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
+COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
+COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
+COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
+COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
COBJS := $(COBJS-y)
/*
* Copyright 2006,2009 Freescale Semiconductor, Inc.
*
+ * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ * Changes for multibus/multiadapter I2C support.
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
-
-#ifdef CONFIG_HARD_I2C
-
#include <command.h>
#include <i2c.h> /* Functional interface */
-
#include <asm/io.h>
#include <asm/fsl_i2c.h> /* HW definitions */
DECLARE_GLOBAL_DATA_PTR;
-/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
- * Default is bus 0. This is necessary because the DDR initialization
- * runs from ROM, and we can't switch buses because we can't modify
- * the global variables.
- */
-#ifndef CONFIG_SYS_SPD_BUS_NUM
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#endif
-static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
-#if defined(CONFIG_I2C_MUX)
-static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
-#endif
-
-static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
-
static const struct fsl_i2c *i2c_dev[2] = {
- (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
-#ifdef CONFIG_SYS_I2C2_OFFSET
- (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
+ (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
+#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
+ (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
#endif
};
return gd->arch.i2c1_clk; /* I2C1 clock */
}
-void
-i2c_init(int speed, int slaveadd)
+static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
const struct fsl_i2c *dev;
- unsigned int temp;
- int bus_num, i;
#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* Call board specific i2c bus reset routine before accessing the
*/
i2c_init_board();
#endif
-#ifdef CONFIG_SYS_I2C2_OFFSET
- bus_num = 2;
-#else
- bus_num = 1;
-#endif
- for (i = 0; i < bus_num; i++) {
- dev = i2c_dev[i];
-
- writeb(0, &dev->cr); /* stop I2C controller */
- udelay(5); /* let it shutdown in peace */
- temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed);
- if (gd->flags & GD_FLG_RELOC)
- i2c_bus_speed[i] = temp;
- writeb(slaveadd << 1, &dev->adr);/* write slave address */
- writeb(0x0, &dev->sr); /* clear status register */
- writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
- }
+ dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+
+ writeb(0, &dev->cr); /* stop I2C controller */
+ udelay(5); /* let it shutdown in peace */
+ set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
+ writeb(slaveadd << 1, &dev->adr);/* write slave address */
+ writeb(0x0, &dev->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
/* Call board specific i2c bus reset routine AFTER the bus has been
}
static int
-i2c_wait4bus(void)
+i2c_wait4bus(struct i2c_adapter *adap)
{
+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
- while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
+ while (readb(&dev->sr) & I2C_SR_MBB) {
if ((get_ticks() - timeval) > timeout)
return -1;
}
}
static __inline__ int
-i2c_wait(int write)
+i2c_wait(struct i2c_adapter *adap, int write)
{
u32 csr;
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
do {
- csr = readb(&i2c_dev[i2c_bus_num]->sr);
+ csr = readb(&dev->sr);
if (!(csr & I2C_SR_MIF))
continue;
/* Read again to allow register to stabilise */
- csr = readb(&i2c_dev[i2c_bus_num]->sr);
+ csr = readb(&dev->sr);
- writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
+ writeb(0x0, &dev->sr);
if (csr & I2C_SR_MAL) {
debug("i2c_wait: MAL\n");
}
static __inline__ int
-i2c_write_addr (u8 dev, u8 dir, int rsta)
+i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
{
+ struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
| (rsta ? I2C_CR_RSTA : 0),
- &i2c_dev[i2c_bus_num]->cr);
+ &device->cr);
- writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
+ writeb((dev << 1) | dir, &device->dr);
- if (i2c_wait(I2C_WRITE_BIT) < 0)
+ if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
return 0;
return 1;
}
static __inline__ int
-__i2c_write(u8 *data, int length)
+__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
{
+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i;
for (i = 0; i < length; i++) {
- writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
+ writeb(data[i], &dev->dr);
- if (i2c_wait(I2C_WRITE_BIT) < 0)
+ if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
break;
}
}
static __inline__ int
-__i2c_read(u8 *data, int length)
+__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
{
+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
- &i2c_dev[i2c_bus_num]->cr);
+ &dev->cr);
/* dummy read */
- readb(&i2c_dev[i2c_bus_num]->dr);
+ readb(&dev->dr);
for (i = 0; i < length; i++) {
- if (i2c_wait(I2C_READ_BIT) < 0)
+ if (i2c_wait(adap, I2C_READ_BIT) < 0)
break;
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
- &i2c_dev[i2c_bus_num]->cr);
+ &dev->cr);
/* Do not generate stop on last byte */
if (i == length - 1)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
- &i2c_dev[i2c_bus_num]->cr);
+ &dev->cr);
- data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
+ data[i] = readb(&dev->dr);
}
return i;
}
-int
-i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+static int
+fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
+ int length)
{
+ struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i = -1; /* signal error */
u8 *a = (u8*)&addr;
- if (i2c_wait4bus() < 0)
+ if (i2c_wait4bus(adap) < 0)
return -1;
if ((!length || alen > 0)
- && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
- && __i2c_write(&a[4 - alen], alen) == alen)
+ && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
+ && __i2c_write(adap, &a[4 - alen], alen) == alen)
i = 0; /* No error so far */
if (length &&
- i2c_write_addr(dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
- i = __i2c_read(data, length);
+ i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
+ i = __i2c_read(adap, data, length);
- writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
+ writeb(I2C_CR_MEN, &device->cr);
- if (i2c_wait4bus()) /* Wait until STOP */
+ if (i2c_wait4bus(adap)) /* Wait until STOP */
debug("i2c_read: wait4bus timed out\n");
if (i == length)
return -1;
}
-int
-i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+static int
+fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
+ u8 *data, int length)
{
+ struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i = -1; /* signal error */
u8 *a = (u8*)&addr;
- if (i2c_wait4bus() >= 0
- && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
- && __i2c_write(&a[4 - alen], alen) == alen) {
- i = __i2c_write(data, length);
+ if (i2c_wait4bus(adap) >= 0 &&
+ i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write(adap, &a[4 - alen], alen) == alen) {
+ i = __i2c_write(adap, data, length);
}
- writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
- if (i2c_wait4bus()) /* Wait until STOP */
+ writeb(I2C_CR_MEN, &device->cr);
+ if (i2c_wait4bus(adap)) /* Wait until STOP */
debug("i2c_write: wait4bus timed out\n");
if (i == length)
return -1;
}
-int
-i2c_probe(uchar chip)
+static int
+fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
/* For unknow reason the controller will ACK when
* probing for a slave with the same address, so skip
* it.
*/
- if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
- return -1;
-
- return i2c_read(chip, 0, 0, NULL, 0);
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
-#if defined(CONFIG_I2C_MUX)
- if (bus < CONFIG_SYS_MAX_I2C_BUS) {
- i2c_bus_num = bus;
- } else {
- int ret;
-
- ret = i2x_mux_select_mux(bus);
- if (ret)
- return ret;
- i2c_bus_num = 0;
- }
- i2c_bus_num_mux = bus;
-#else
-#ifdef CONFIG_SYS_I2C2_OFFSET
- if (bus > 1) {
-#else
- if (bus > 0) {
-#endif
+ if (chip == (readb(&dev->adr) >> 1))
return -1;
- }
- i2c_bus_num = bus;
-#endif
- return 0;
+ return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
}
-int i2c_set_bus_speed(unsigned int speed)
+static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
- unsigned int i2c_clk = (i2c_bus_num == 1)
- ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
- writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
- i2c_bus_speed[i2c_bus_num] =
- set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
- writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
+ writeb(0, &dev->cr); /* stop controller */
+ set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
+ writeb(I2C_CR_MEN, &dev->cr); /* start controller */
return 0;
}
-unsigned int i2c_get_bus_num(void)
-{
-#if defined(CONFIG_I2C_MUX)
- return i2c_bus_num_mux;
-#else
- return i2c_bus_num;
+/*
+ * Register fsl i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+ fsl_i2c_write, fsl_i2c_set_bus_speed,
+ CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
+ 0)
+#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
+U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+ fsl_i2c_write, fsl_i2c_set_bus_speed,
+ CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
+ 1)
#endif
-}
-
-unsigned int i2c_get_bus_speed(void)
-{
- return i2c_bus_speed[i2c_bus_num];
-}
-
-#endif /* CONFIG_HARD_I2C */
--- /dev/null
+/*
+ * Faraday I2C Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+#include "fti2c010.h"
+
+#ifndef CONFIG_HARD_I2C
+#error "fti2c010: CONFIG_HARD_I2C is not defined"
+#endif
+
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
+#endif
+
+#ifndef CONFIG_FTI2C010_FREQ
+#define CONFIG_FTI2C010_FREQ clk_get_rate("I2C")
+#endif
+
+/* command timeout */
+#define CFG_CMD_TIMEOUT 10 /* ms */
+
+/* 7-bit chip address + 1-bit read/write */
+#define I2C_RD(chip) ((((chip) << 1) & 0xff) | 1)
+#define I2C_WR(chip) (((chip) << 1) & 0xff)
+
+struct fti2c010_chip {
+ void __iomem *regs;
+ uint bus;
+ uint speed;
+};
+
+static struct fti2c010_chip chip_list[] = {
+ {
+ .bus = 0,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE,
+ },
+#ifdef CONFIG_I2C_MULTI_BUS
+# ifdef CONFIG_FTI2C010_BASE1
+ {
+ .bus = 1,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE1,
+ },
+# endif
+# ifdef CONFIG_FTI2C010_BASE2
+ {
+ .bus = 2,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE2,
+ },
+# endif
+# ifdef CONFIG_FTI2C010_BASE3
+ {
+ .bus = 3,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE3,
+ },
+# endif
+#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
+};
+
+static struct fti2c010_chip *curr = chip_list;
+
+static int fti2c010_wait(uint32_t mask)
+{
+ int ret = -1;
+ uint32_t stat, ts;
+ struct fti2c010_regs *regs = curr->regs;
+
+ for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+ stat = readl(®s->sr);
+ if ((stat & mask) == mask) {
+ ret = 0;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * u-boot I2C API
+ */
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+ if (speed || !curr->speed)
+ i2c_set_bus_speed(speed);
+
+ /* if slave mode disabled */
+ if (!slaveaddr)
+ return;
+
+ /*
+ * TODO:
+ * Implement slave mode, but is it really necessary?
+ */
+}
+
+/*
+ * Probe the given I2C chip address. Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uchar chip)
+{
+ int ret;
+ struct fti2c010_regs *regs = curr->regs;
+
+ i2c_init(0, 0);
+
+ /* 1. Select slave device (7bits Address + 1bit R/W) */
+ writel(I2C_WR(chip), ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+ if (ret)
+ return ret;
+
+ /* 2. Select device register */
+ writel(0, ®s->dr);
+ writel(CR_ENABLE | CR_TBEN, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+
+ return ret;
+}
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int ret, pos;
+ uchar paddr[4];
+ struct fti2c010_regs *regs = curr->regs;
+
+ i2c_init(0, 0);
+
+ paddr[0] = (addr >> 0) & 0xFF;
+ paddr[1] = (addr >> 8) & 0xFF;
+ paddr[2] = (addr >> 16) & 0xFF;
+ paddr[3] = (addr >> 24) & 0xFF;
+
+ /*
+ * Phase A. Set register address
+ */
+
+ /* A.1 Select slave device (7bits Address + 1bit R/W) */
+ writel(I2C_WR(chip), ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+ if (ret)
+ return ret;
+
+ /* A.2 Select device register */
+ for (pos = 0; pos < alen; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+
+ writel(paddr[pos], ®s->dr);
+ writel(ctrl, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * Phase B. Get register data
+ */
+
+ /* B.1 Select slave device (7bits Address + 1bit R/W) */
+ writel(I2C_RD(chip), ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+ if (ret)
+ return ret;
+
+ /* B.2 Get register data */
+ for (pos = 0; pos < len; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+ uint32_t stat = SR_DR;
+
+ if (pos == len - 1) {
+ ctrl |= CR_NAK | CR_STOP;
+ stat |= SR_ACK;
+ }
+ writel(ctrl, ®s->cr);
+ ret = fti2c010_wait(stat);
+ if (ret)
+ break;
+ buf[pos] = (uchar)(readl(®s->dr) & 0xFF);
+ }
+
+ return ret;
+}
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int ret, pos;
+ uchar paddr[4];
+ struct fti2c010_regs *regs = curr->regs;
+
+ i2c_init(0, 0);
+
+ paddr[0] = (addr >> 0) & 0xFF;
+ paddr[1] = (addr >> 8) & 0xFF;
+ paddr[2] = (addr >> 16) & 0xFF;
+ paddr[3] = (addr >> 24) & 0xFF;
+
+ /*
+ * Phase A. Set register address
+ *
+ * A.1 Select slave device (7bits Address + 1bit R/W)
+ */
+ writel(I2C_WR(chip), ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+ if (ret)
+ return ret;
+
+ /* A.2 Select device register */
+ for (pos = 0; pos < alen; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+
+ writel(paddr[pos], ®s->dr);
+ writel(ctrl, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * Phase B. Set register data
+ */
+ for (pos = 0; pos < len; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+
+ if (pos == len - 1)
+ ctrl |= CR_STOP;
+ writel(buf[pos], ®s->dr);
+ writel(ctrl, ®s->cr);
+ ret = fti2c010_wait(SR_DT);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Functions for setting the current I2C bus and its speed
+ */
+#ifdef CONFIG_I2C_MULTI_BUS
+
+/*
+ * i2c_set_bus_num:
+ *
+ * Change the active I2C bus. Subsequent read/write calls will
+ * go to this one.
+ *
+ * bus - bus index, zero based
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_set_bus_num(uint bus)
+{
+ if (bus >= ARRAY_SIZE(chip_list))
+ return -1;
+ curr = chip_list + bus;
+ i2c_init(0, 0);
+ return 0;
+}
+
+/*
+ * i2c_get_bus_num:
+ *
+ * Returns index of currently active I2C bus. Zero-based.
+ */
+
+uint i2c_get_bus_num(void)
+{
+ return curr->bus;
+}
+
+#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
+
+/*
+ * i2c_set_bus_speed:
+ *
+ * Change the speed of the active I2C bus
+ *
+ * speed - bus speed in Hz
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_set_bus_speed(uint speed)
+{
+ struct fti2c010_regs *regs = curr->regs;
+ uint clk = CONFIG_FTI2C010_FREQ;
+ uint gsr = 0, tsr = 32;
+ uint spd, div;
+
+ if (!speed)
+ speed = CONFIG_SYS_I2C_SPEED;
+
+ for (div = 0; div < 0x3ffff; ++div) {
+ /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
+ spd = clk / (2 * (div + 2) + gsr);
+ if (spd <= speed)
+ break;
+ }
+
+ if (curr->speed == spd)
+ return 0;
+
+ writel(CR_I2CRST, ®s->cr);
+ mdelay(100);
+ if (readl(®s->cr) & CR_I2CRST) {
+ printf("fti2c010: reset timeout\n");
+ return -1;
+ }
+
+ curr->speed = spd;
+
+ writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
+ writel(CDR_DIV(div), ®s->cdr);
+
+ return 0;
+}
+
+/*
+ * i2c_get_bus_speed:
+ *
+ * Returns speed of currently active I2C bus in Hz
+ */
+
+uint i2c_get_bus_speed(void)
+{
+ return curr->speed;
+}
--- /dev/null
+/*
+ * Faraday I2C Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef __FTI2C010_H
+#define __FTI2C010_H
+
+/*
+ * FTI2C010 registers
+ */
+struct fti2c010_regs {
+ uint32_t cr; /* 0x00: control register */
+ uint32_t sr; /* 0x04: status register */
+ uint32_t cdr; /* 0x08: clock division register */
+ uint32_t dr; /* 0x0c: data register */
+ uint32_t sar; /* 0x10: slave address register */
+ uint32_t tgsr;/* 0x14: time & glitch suppression register */
+ uint32_t bmr; /* 0x18: bus monitor register */
+ uint32_t rsvd[5];
+ uint32_t revr;/* 0x30: revision register */
+};
+
+/*
+ * control register
+ */
+#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */
+#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */
+#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */
+#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */
+#define CR_DRIRQ 0x200 /* rx interrupt (both) */
+#define CR_DTIRQ 0x100 /* tx interrupt (both) */
+#define CR_TBEN 0x80 /* tx enable (both) */
+#define CR_NAK 0x40 /* NACK (both) */
+#define CR_STOP 0x20 /* stop (master) */
+#define CR_START 0x10 /* start (master) */
+#define CR_GCEN 0x8 /* general call support (slave) */
+#define CR_SCLEN 0x4 /* enable clock out (master) */
+#define CR_I2CEN 0x2 /* enable I2C (both) */
+#define CR_I2CRST 0x1 /* reset I2C (both) */
+#define CR_ENABLE \
+ (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN)
+
+/*
+ * status register
+ */
+#define SR_CLRAL 0x400 /* clear arbitration lost */
+#define SR_CLRGC 0x200 /* clear general call */
+#define SR_CLRSAM 0x100 /* clear slave address match */
+#define SR_CLRSTOP 0x80 /* clear stop */
+#define SR_CLRNAKR 0x40 /* clear NACK respond */
+#define SR_DR 0x20 /* rx ready */
+#define SR_DT 0x10 /* tx done */
+#define SR_BB 0x8 /* bus busy */
+#define SR_BUSY 0x4 /* chip busy */
+#define SR_ACK 0x2 /* ACK/NACK received */
+#define SR_RW 0x1 /* set when master-rx or slave-tx mode */
+
+/*
+ * clock division register
+ */
+#define CDR_DIV(n) ((n) & 0x3ffff)
+
+/*
+ * time & glitch suppression register
+ */
+#define TGSR_GSR(n) (((n) & 0x7) << 10)
+#define TGSR_TSR(n) ((n) & 0x3ff)
+
+/*
+ * bus monitor register
+ */
+#define BMR_SCL 0x2 /* SCL is pull-up */
+#define BMR_SDA 0x1 /* SDA is pull-up */
+
+#endif /* __FTI2C010_H */
--- /dev/null
+/*
+ * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * (C) Copyright 2012
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Multibus/multiadapter I2C core functions (wrappers)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <i2c.h>
+
+struct i2c_adapter *i2c_get_adapter(int index)
+{
+ struct i2c_adapter *i2c_adap_p = ll_entry_start(struct i2c_adapter,
+ i2c);
+ int max = ll_entry_count(struct i2c_adapter, i2c);
+ int i;
+
+ if (index >= max) {
+ printf("Error, wrong i2c adapter %d max %d possible\n",
+ index, max);
+ return i2c_adap_p;
+ }
+ if (index == 0)
+ return i2c_adap_p;
+
+ for (i = 0; i < index; i++)
+ i2c_adap_p++;
+
+ return i2c_adap_p;
+}
+
+#if !defined(CONFIG_SYS_I2C_DIRECT_BUS)
+struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] =
+ CONFIG_SYS_I2C_BUSES;
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void i2c_reloc_fixup(void)
+{
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+ struct i2c_adapter *i2c_adap_p = ll_entry_start(struct i2c_adapter,
+ i2c);
+ struct i2c_adapter *tmp = i2c_adap_p;
+ int max = ll_entry_count(struct i2c_adapter, i2c);
+ int i;
+ unsigned long addr;
+
+ if (gd->reloc_off == 0)
+ return;
+
+ for (i = 0; i < max; i++) {
+ /* adapter itself */
+ addr = (unsigned long)i2c_adap_p;
+ addr += gd->reloc_off;
+ i2c_adap_p = (struct i2c_adapter *)addr;
+ /* i2c_init() */
+ addr = (unsigned long)i2c_adap_p->init;
+ addr += gd->reloc_off;
+ i2c_adap_p->init = (void (*)(int, int))addr;
+ /* i2c_probe() */
+ addr = (unsigned long)i2c_adap_p->probe;
+ addr += gd->reloc_off;
+ i2c_adap_p->probe = (int (*)(uint8_t))addr;
+ /* i2c_read() */
+ addr = (unsigned long)i2c_adap_p->read;
+ addr += gd->reloc_off;
+ i2c_adap_p->read = (int (*)(uint8_t, uint, int, uint8_t *,
+ int))addr;
+ /* i2c_write() */
+ addr = (unsigned long)i2c_adap_p->write;
+ addr += gd->reloc_off;
+ i2c_adap_p->write = (int (*)(uint8_t, uint, int, uint8_t *,
+ int))addr;
+ /* i2c_set_bus_speed() */
+ addr = (unsigned long)i2c_adap_p->set_bus_speed;
+ addr += gd->reloc_off;
+ i2c_adap_p->set_bus_speed = (uint (*)(uint))addr;
+ /* name */
+ addr = (unsigned long)i2c_adap_p->name;
+ addr += gd->reloc_off;
+ i2c_adap_p->name = (char *)addr;
+ tmp++;
+ i2c_adap_p = tmp;
+ }
+#endif
+}
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+/*
+ * i2c_mux_set()
+ * -------------
+ *
+ * This turns on the given channel on I2C multiplexer chip connected to
+ * a given I2C adapter directly or via other multiplexers. In the latter
+ * case the entire multiplexer chain must be initialized first starting
+ * with the one connected directly to the adapter. When disabling a chain
+ * muxes must be programmed in reverse order, starting with the one
+ * farthest from the adapter.
+ *
+ * mux_id is the multiplexer chip type from defined in i2c.h. So far only
+ * NXP (Philips) PCA954x multiplexers are supported. Switches are NOT
+ * supported (anybody uses them?)
+ */
+
+static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip,
+ int channel)
+{
+ uint8_t buf;
+ int ret;
+
+ /* channel < 0 - turn off the mux */
+ if (channel < 0) {
+ buf = 0;
+ ret = adap->write(adap, chip, 0, 0, &buf, 1);
+ if (ret)
+ printf("%s: Could not turn off the mux.\n", __func__);
+ return ret;
+ }
+
+ switch (mux_id) {
+ case I2C_MUX_PCA9540_ID:
+ case I2C_MUX_PCA9542_ID:
+ if (channel > 1)
+ return -1;
+ buf = (uint8_t)((channel & 0x01) | (1 << 2));
+ break;
+ case I2C_MUX_PCA9544_ID:
+ if (channel > 3)
+ return -1;
+ buf = (uint8_t)((channel & 0x03) | (1 << 2));
+ break;
+ case I2C_MUX_PCA9547_ID:
+ if (channel > 7)
+ return -1;
+ buf = (uint8_t)((channel & 0x07) | (1 << 3));
+ break;
+ default:
+ printf("%s: wrong mux id: %d\n", __func__, mux_id);
+ return -1;
+ }
+
+ ret = adap->write(adap, chip, 0, 0, &buf, 1);
+ if (ret)
+ printf("%s: could not set mux: id: %d chip: %x channel: %d\n",
+ __func__, mux_id, chip, channel);
+ return ret;
+}
+
+static int i2c_mux_set_all(void)
+{
+ struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
+ int i;
+
+ /* Connect requested bus if behind muxes */
+ if (i2c_bus_tmp->next_hop[0].chip != 0) {
+ /* Set all muxes along the path to that bus */
+ for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) {
+ int ret;
+
+ if (i2c_bus_tmp->next_hop[i].chip == 0)
+ break;
+
+ ret = i2c_mux_set(I2C_ADAP,
+ i2c_bus_tmp->next_hop[i].mux.id,
+ i2c_bus_tmp->next_hop[i].chip,
+ i2c_bus_tmp->next_hop[i].channel);
+ if (ret != 0)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int i2c_mux_disconnet_all(void)
+{
+ struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
+ int i;
+ uint8_t buf;
+
+ if (I2C_ADAP->init_done == 0)
+ return 0;
+
+ /* Disconnect current bus (turn off muxes if any) */
+ if ((i2c_bus_tmp->next_hop[0].chip != 0) &&
+ (I2C_ADAP->init_done != 0)) {
+ i = CONFIG_SYS_I2C_MAX_HOPS;
+ do {
+ uint8_t chip;
+ int ret;
+
+ chip = i2c_bus_tmp->next_hop[--i].chip;
+ if (chip == 0)
+ continue;
+
+ ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1);
+ if (ret != 0) {
+ printf("i2c: mux diconnect error\n");
+ return ret;
+ }
+ } while (i > 0);
+ }
+
+ return 0;
+}
+#endif
+
+/*
+ * i2c_init_bus():
+ * ---------------
+ *
+ * Initializes one bus. Will initialize the parent adapter. No current bus
+ * changes, no mux (if any) setup.
+ */
+static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr)
+{
+ if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES)
+ return;
+
+ I2C_ADAP->init(I2C_ADAP, speed, slaveaddr);
+
+ if (gd->flags & GD_FLG_RELOC) {
+ I2C_ADAP->init_done = 1;
+ I2C_ADAP->speed = speed;
+ I2C_ADAP->slaveaddr = slaveaddr;
+ }
+}
+
+/* implement possible board specific board init */
+static void __def_i2c_init_board(void)
+{
+}
+void i2c_init_board(void)
+ __attribute__((weak, alias("__def_i2c_init_board")));
+
+/*
+ * i2c_init_all():
+ *
+ * not longer needed, will deleted. Actual init the SPD_BUS
+ * for compatibility.
+ * i2c_adap[] must be initialized beforehead with function pointers and
+ * data, including speed and slaveaddr.
+ */
+void i2c_init_all(void)
+{
+ i2c_init_board();
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+ return;
+}
+
+/*
+ * i2c_get_bus_num():
+ * ------------------
+ *
+ * Returns index of currently active I2C bus. Zero-based.
+ */
+unsigned int i2c_get_bus_num(void)
+{
+ return gd->cur_i2c_bus;
+}
+
+/*
+ * i2c_set_bus_num():
+ * ------------------
+ *
+ * Change the active I2C bus. Subsequent read/write calls will
+ * go to this one. Sets all of the muxes in a proper condition
+ * if that bus is behind muxes.
+ * If previously selected bus is behind the muxes turns off all the
+ * muxes along the path to that bus.
+ *
+ * bus - bus index, zero based
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_set_bus_num(unsigned int bus)
+{
+ int max = ll_entry_count(struct i2c_adapter, i2c);
+
+ if (I2C_ADAPTER(bus) >= max) {
+ printf("Error, wrong i2c adapter %d max %d possible\n",
+ I2C_ADAPTER(bus), max);
+ return -2;
+ }
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+ if (bus >= CONFIG_SYS_NUM_I2C_BUSES)
+ return -1;
+#endif
+
+ if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
+ return 0;
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+ i2c_mux_disconnet_all();
+#endif
+
+ gd->cur_i2c_bus = bus;
+ if (I2C_ADAP->init_done == 0)
+ i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr);
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+ i2c_mux_set_all();
+#endif
+ return 0;
+}
+
+/*
+ * Probe the given I2C chip address. Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uint8_t chip)
+{
+ return I2C_ADAP->probe(I2C_ADAP, chip);
+}
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uint8_t chip, unsigned int addr, int alen,
+ uint8_t *buffer, int len)
+{
+ return I2C_ADAP->read(I2C_ADAP, chip, addr, alen, buffer, len);
+}
+
+int i2c_write(uint8_t chip, unsigned int addr, int alen,
+ uint8_t *buffer, int len)
+{
+ return I2C_ADAP->write(I2C_ADAP, chip, addr, alen, buffer, len);
+}
+
+unsigned int i2c_set_bus_speed(unsigned int speed)
+{
+ unsigned int ret;
+
+ if (I2C_ADAP->set_bus_speed == NULL)
+ return 0;
+ ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed);
+ if (gd->flags & GD_FLG_RELOC)
+ I2C_ADAP->speed = ret;
+
+ return ret;
+}
+
+unsigned int i2c_get_bus_speed(void)
+{
+ struct i2c_adapter *cur = I2C_ADAP;
+ return cur->speed;
+}
+
+uint8_t i2c_reg_read(uint8_t addr, uint8_t reg)
+{
+ uint8_t buf;
+
+#ifdef CONFIG_8xx
+ /* MPC8xx needs this. Maybe one day we can get rid of it. */
+ /* maybe it is now the time for it ... */
+ i2c_set_bus_num(i2c_get_bus_num());
+#endif
+ i2c_read(addr, reg, 1, &buf, 1);
+
+#ifdef DEBUG
+ printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n",
+ __func__, i2c_get_bus_num(), addr, reg, buf);
+#endif
+
+ return buf;
+}
+
+void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val)
+{
+#ifdef CONFIG_8xx
+ /* MPC8xx needs this. Maybe one day we can get rid of it. */
+ /* maybe it is now the time for it ... */
+ i2c_set_bus_num(i2c_get_bus_num());
+#endif
+
+#ifdef DEBUG
+ printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n",
+ __func__, i2c_get_bus_num(), addr, reg, val);
+#endif
+
+ i2c_write(addr, reg, 1, &val, 1);
+}
+
+void __i2c_init(int speed, int slaveaddr)
+{
+ i2c_init_bus(i2c_get_bus_num(), speed, slaveaddr);
+}
+void i2c_init(int speed, int slaveaddr)
+ __attribute__((weak, alias("__i2c_init")));
#include <i2c.h>
#include <watchdog.h>
+#ifdef I2C_QUIRK_REG
+struct mxc_i2c_regs {
+ uint8_t iadr;
+ uint8_t ifdr;
+ uint8_t i2cr;
+ uint8_t i2sr;
+ uint8_t i2dr;
+};
+#else
struct mxc_i2c_regs {
uint32_t iadr;
uint32_t ifdr;
uint32_t i2sr;
uint32_t i2dr;
};
+#endif
-#define I2CR_IEN (1 << 7)
#define I2CR_IIEN (1 << 6)
#define I2CR_MSTA (1 << 5)
#define I2CR_MTX (1 << 4)
#define I2SR_IIF (1 << 1)
#define I2SR_RX_NO_AK (1 << 0)
+#ifdef I2C_QUIRK_REG
+#define I2CR_IEN (0 << 7)
+#define I2CR_IDIS (1 << 7)
+#define I2SR_IIF_CLEAR (1 << 1)
+#else
+#define I2CR_IEN (1 << 7)
+#define I2CR_IDIS (0 << 7)
+#define I2SR_IIF_CLEAR (0 << 1)
+#endif
+
#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif
+#ifdef I2C_QUIRK_REG
+static u16 i2c_clk_div[60][2] = {
+ { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
+ { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
+ { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
+ { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
+ { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
+ { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
+ { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
+ { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
+ { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
+ { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
+ { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
+ { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
+ { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
+ { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
+ { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
+};
+#else
static u16 i2c_clk_div[50][2] = {
{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
{ 3072, 0x1E }, { 3840, 0x1F }
};
+#endif
/*
* Calculate and set proper clock divider
writeb(idx, &i2c_regs->ifdr);
/* Reset module */
- writeb(0, &i2c_regs->i2cr);
+ writeb(I2CR_IDIS, &i2c_regs->i2cr);
writeb(0, &i2c_regs->i2sr);
return 0;
}
for (;;) {
sr = readb(&i2c_regs->i2sr);
if (sr & I2SR_IAL) {
+#ifdef I2C_QUIRK_REG
+ writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
+#else
writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
+#endif
printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
__func__, sr, readb(&i2c_regs->i2cr), state);
return -ERESTART;
{
int ret;
- writeb(0, &i2c_regs->i2sr);
+ writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
writeb(byte, &i2c_regs->i2dr);
ret = wait_for_sr_state(i2c_regs, ST_IIF);
if (ret < 0)
int ret;
/* Enable I2C controller */
+#ifdef I2C_QUIRK_REG
+ if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
+#else
if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
+#endif
writeb(I2CR_IEN, &i2c_regs->i2cr);
/* Wait for controller to be stable */
udelay(50);
}
if (readb(&i2c_regs->iadr) == (chip << 1))
writeb((chip << 1) ^ 2, &i2c_regs->iadr);
- writeb(0, &i2c_regs->i2sr);
+ writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
if (ret < 0)
return ret;
printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
retry);
if (ret != -ERESTART)
- writeb(0, &i2c_regs->i2cr); /* Disable controller */
+ /* Disable controller */
+ writeb(I2CR_IDIS, &i2c_regs->i2cr);
udelay(100);
if (i2c_idle_bus(i2c_regs) < 0)
break;
if (len == 1)
temp |= I2CR_TX_NO_AK;
writeb(temp, &i2c_regs->i2cr);
- writeb(0, &i2c_regs->i2sr);
+ writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
/* read data */
temp |= I2CR_TX_NO_AK;
writeb(temp, &i2c_regs->i2cr);
}
- writeb(0, &i2c_regs->i2sr);
+ writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
buf[i] = readb(&i2c_regs->i2dr);
}
i2c_imx_stop(i2c_regs);
#include <i2c.h>
#include <asm/io.h>
-#ifdef CONFIG_HARD_I2C
-
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_I2C_MULTI_BUS)
-/*
- * Initialize the bus pointer to whatever one the SPD EEPROM is on.
- * Default is bus 0. This is necessary because the DDR initialization
- * runs from ROM, and we can't switch buses because we can't modify
- * the global variables.
- */
-#ifndef CONFIG_SYS_SPD_BUS_NUM
-#define CONFIG_SYS_SPD_BUS_NUM 0
+static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr)
+{
+ unsigned long base;
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100);
+#elif defined(CONFIG_440) || defined(CONFIG_405EX)
+/* all remaining 440 variants */
+ base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100);
+#else
+/* all 405 variants */
+ base = 0xEF600500 + (hwadapnr * 0x100);
#endif
-static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
- CONFIG_SYS_SPD_BUS_NUM;
-#endif /* CONFIG_I2C_MULTI_BUS */
+ return (struct ppc4xx_i2c *)base;
+}
-static void _i2c_bus_reset(void)
+static void _i2c_bus_reset(struct i2c_adapter *adap)
{
- struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
+ struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
int i;
u8 dc;
out_8(&i2c->xtcntlss, 0);
}
-void i2c_init(int speed, int slaveaddr)
+static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
- struct ppc4xx_i2c *i2c;
+ struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
int val, divisor;
- int bus;
#ifdef CONFIG_SYS_I2C_INIT_BOARD
/*
i2c_init_board();
#endif
- for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
- I2C_SET_BUS(bus);
-
- /* Set i2c pointer after calling I2C_SET_BUS() */
- i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
-
- /* Handle possible failed I2C state */
- /* FIXME: put this into i2c_init_board()? */
- _i2c_bus_reset();
+ /* Handle possible failed I2C state */
+ /* FIXME: put this into i2c_init_board()? */
+ _i2c_bus_reset(adap);
- /* clear lo master address */
- out_8(&i2c->lmadr, 0);
+ /* clear lo master address */
+ out_8(&i2c->lmadr, 0);
- /* clear hi master address */
- out_8(&i2c->hmadr, 0);
-
- /* clear lo slave address */
- out_8(&i2c->lsadr, 0);
+ /* clear hi master address */
+ out_8(&i2c->hmadr, 0);
- /* clear hi slave address */
- out_8(&i2c->hsadr, 0);
+ /* clear lo slave address */
+ out_8(&i2c->lsadr, 0);
- /* Clock divide Register */
- /* set divisor according to freq_opb */
- divisor = (get_OPB_freq() - 1) / 10000000;
- if (divisor == 0)
- divisor = 1;
- out_8(&i2c->clkdiv, divisor);
+ /* clear hi slave address */
+ out_8(&i2c->hsadr, 0);
- /* no interrupts */
- out_8(&i2c->intrmsk, 0);
+ /* Clock divide Register */
+ /* set divisor according to freq_opb */
+ divisor = (get_OPB_freq() - 1) / 10000000;
+ if (divisor == 0)
+ divisor = 1;
+ out_8(&i2c->clkdiv, divisor);
- /* clear transfer count */
- out_8(&i2c->xfrcnt, 0);
+ /* no interrupts */
+ out_8(&i2c->intrmsk, 0);
- /* clear extended control & stat */
- /* write 1 in SRC SRS SWC SWS to clear these fields */
- out_8(&i2c->xtcntlss, 0xF0);
+ /* clear transfer count */
+ out_8(&i2c->xfrcnt, 0);
- /* Mode Control Register
- Flush Slave/Master data buffer */
- out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
+ /* clear extended control & stat */
+ /* write 1 in SRC SRS SWC SWS to clear these fields */
+ out_8(&i2c->xtcntlss, 0xF0);
- val = in_8(&i2c->mdcntl);
+ /* Mode Control Register
+ Flush Slave/Master data buffer */
+ out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
- /* Ignore General Call, slave transfers are ignored,
- * disable interrupts, exit unknown bus state, enable hold
- * SCL 100kHz normaly or FastMode for 400kHz and above
- */
+ val = in_8(&i2c->mdcntl);
- val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
- if (speed >= 400000)
- val |= IIC_MDCNTL_FSM;
- out_8(&i2c->mdcntl, val);
+ /* Ignore General Call, slave transfers are ignored,
+ * disable interrupts, exit unknown bus state, enable hold
+ * SCL 100kHz normaly or FastMode for 400kHz and above
+ */
- /* clear control reg */
- out_8(&i2c->cntl, 0x00);
- }
+ val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
+ if (speed >= 400000)
+ val |= IIC_MDCNTL_FSM;
+ out_8(&i2c->mdcntl, val);
- /* set to SPD bus as default bus upon powerup */
- I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+ /* clear control reg */
+ out_8(&i2c->cntl, 0x00);
}
/*
*
* It does not check XFRCNT.
*/
-static int i2c_transfer(unsigned char cmd_type,
+static int _i2c_transfer(struct i2c_adapter *adap,
+ unsigned char cmd_type,
unsigned char chip,
unsigned char addr[],
unsigned char addr_len,
unsigned char data[],
unsigned short data_len)
{
- struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
+ struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
u8 *ptr;
int reading;
int tran, cnt;
return result;
}
-int i2c_probe(uchar chip)
+static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
uchar buf[1];
* address was <ACK>ed (i.e. there was a chip at that address which
* drove the data line low).
*/
- return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0);
+ return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0);
}
-static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
- int len, int read)
+static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len, int read)
{
uchar xaddr[4];
int ret;
chip |= ((addr >> (alen * 8)) &
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen,
- buffer, len)) != 0) {
+ ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen,
+ buffer, len);
+ if (ret) {
printf("I2C %s: failed %d\n", read ? "read" : "write", ret);
-
return 1;
}
return 0;
}
-int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
+static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
- return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1);
+ return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1);
}
-int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
+static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
- return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0);
+ return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
}
-#if defined(CONFIG_I2C_MULTI_BUS)
-/*
- * Functions for multiple I2C bus handling
- */
-unsigned int i2c_get_bus_num(void)
+static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
- return i2c_bus_num;
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
- if (bus >= CONFIG_SYS_MAX_I2C_BUS)
+ if (speed != adap->speed)
return -1;
-
- i2c_bus_num = bus;
-
- return 0;
+ return speed;
}
-#endif /* CONFIG_I2C_MULTI_BUS */
-#endif /* CONFIG_HARD_I2C */
+
+/*
+ * Register ppc4xx i2c adapters
+ */
+#ifdef CONFIG_SYS_I2C_PPC4XX_CH0
+U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe,
+ ppc4xx_i2c_read, ppc4xx_i2c_write,
+ ppc4xx_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_PPC4XX_SPEED_0,
+ CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0)
+#endif
+#ifdef CONFIG_SYS_I2C_PPC4XX_CH1
+U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe,
+ ppc4xx_i2c_read, ppc4xx_i2c_write,
+ ppc4xx_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_PPC4XX_SPEED_1,
+ CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1)
+#endif
/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ * Changes for multibus/multiadapter I2C support.
+ *
* (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
/* #define DEBUG_I2C */
-#ifdef DEBUG_I2C
DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef I2C_SOFT_DECLARATIONS
+# if defined(CONFIG_MPC8260)
+# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = \
+ ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
+# elif defined(CONFIG_8xx)
+# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = \
+ (immap_t *)CONFIG_SYS_IMMR;
+# else
+# define I2C_SOFT_DECLARATIONS
+# endif
+#endif
+
+#if !defined(CONFIG_SYS_SOFT_I2C_SPEED)
+#define CONFIG_SYS_SOFT_I2C_SPEED CONFIG_SYS_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_SOFT_I2C_SLAVE)
+#define CONFIG_SYS_SOFT_I2C_SLAVE CONFIG_SYS_I2C_SLAVE
#endif
/*-----------------------------------------------------------------------
* Definitions
*/
-
#define RETRIES 0
#define I2C_ACK 0 /* PD_SDA level to ack a byte */
#define PRINTD(fmt,args...)
#endif
-#if defined(CONFIG_I2C_MULTI_BUS)
-static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
-#endif /* CONFIG_I2C_MULTI_BUS */
-
/*-----------------------------------------------------------------------
* Local functions
*/
return(nack); /* not a nack is an ack */
}
-#if defined(CONFIG_I2C_MULTI_BUS)
-/*
- * Functions for multiple I2C bus handling
- */
-unsigned int i2c_get_bus_num(void)
-{
- return i2c_bus_num;
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
-#if defined(CONFIG_I2C_MUX)
- if (bus < CONFIG_SYS_MAX_I2C_BUS) {
- i2c_bus_num = bus;
- } else {
- int ret;
-
- ret = i2x_mux_select_mux(bus);
- i2c_init_board();
- if (ret == 0)
- i2c_bus_num = bus;
- else
- return ret;
- }
-#else
- if (bus >= CONFIG_SYS_MAX_I2C_BUS)
- return -1;
- i2c_bus_num = bus;
-#endif
- return 0;
-}
-#endif
-
/*-----------------------------------------------------------------------
* if ack == I2C_ACK, ACK the byte so can continue reading, else
* send I2C_NOACK to end the read.
return(data);
}
-/*=====================================================================*/
-/* Public Functions */
-/*=====================================================================*/
-
/*-----------------------------------------------------------------------
* Initialization
*/
-void i2c_init (int speed, int slaveaddr)
+static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
#if defined(CONFIG_SYS_I2C_INIT_BOARD)
/* call board specific i2c bus reset routine before accessing the */
* completion of EEPROM writes since the chip stops responding until
* the write completes (typically 10mSec).
*/
-int i2c_probe(uchar addr)
+static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
{
int rc;
/*-----------------------------------------------------------------------
* Read bytes
*/
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
int shift;
PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
/*-----------------------------------------------------------------------
* Write bytes
*/
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
int shift, failures = 0;
send_stop();
return(failures);
}
+
+/*
+ * Register soft i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(soft0, soft_i2c_init, soft_i2c_probe,
+ soft_i2c_read, soft_i2c_write, NULL,
+ CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
+ 0)
+#if defined(I2C_SOFT_DECLARATIONS2)
+U_BOOT_I2C_ADAP_COMPLETE(soft1, soft_i2c_init, soft_i2c_probe,
+ soft_i2c_read, soft_i2c_write, NULL,
+ CONFIG_SYS_I2C_SOFT_SPEED_2,
+ CONFIG_SYS_I2C_SOFT_SLAVE_2,
+ 1)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS3)
+U_BOOT_I2C_ADAP_COMPLETE(soft2, soft_i2c_init, soft_i2c_probe,
+ soft_i2c_read, soft_i2c_write, NULL,
+ CONFIG_SYS_I2C_SOFT_SPEED_3,
+ CONFIG_SYS_I2C_SOFT_SLAVE_3,
+ 2)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS4)
+U_BOOT_I2C_ADAP_COMPLETE(soft3, soft_i2c_init, soft_i2c_probe,
+ soft_i2c_read, soft_i2c_write, NULL,
+ CONFIG_SYS_I2C_SOFT_SPEED_4,
+ CONFIG_SYS_I2C_SOFT_SLAVE_4,
+ 3)
+#endif
DECLARE_GLOBAL_DATA_PTR;
-static unsigned int i2c_bus_num;
-
/* Information about i2c controller */
struct i2c_bus {
int id;
return error;
}
-static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
+ u32 len)
{
int error;
struct i2c_trans_info trans_info;
trans_info.num_bytes = len;
trans_info.is_10bit_address = 0;
- error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
+ error = send_recv_packets(bus, &trans_info);
if (error)
debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
return error;
}
-static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data,
+ u32 len)
{
int error;
struct i2c_trans_info trans_info;
trans_info.num_bytes = len;
trans_info.is_10bit_address = 0;
- error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
+ error = send_recv_packets(bus, &trans_info);
if (error)
debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
#error "Please enable device tree support to use this driver"
#endif
-unsigned int i2c_get_bus_speed(void)
+/**
+ * Check that a bus number is valid and return a pointer to it
+ *
+ * @param bus_num Bus number to check / return
+ * @return pointer to bus, if valid, else NULL
+ */
+static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap)
{
- return i2c_controllers[i2c_bus_num].speed;
+ struct i2c_bus *bus;
+
+ bus = &i2c_controllers[adap->hwadapnr];
+ if (!bus->inited) {
+ debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
+ return NULL;
+ }
+
+ return bus;
}
-int i2c_set_bus_speed(unsigned int speed)
+static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
- struct i2c_bus *i2c_bus;
+ struct i2c_bus *bus;
- i2c_bus = &i2c_controllers[i2c_bus_num];
- i2c_bus->speed = speed;
- i2c_init_controller(i2c_bus);
+ bus = tegra_i2c_get_bus(adap);
+ if (!bus)
+ return 0;
+ bus->speed = speed;
+ i2c_init_controller(bus);
return 0;
}
return;
}
-void i2c_init(int speed, int slaveaddr)
+static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
/* This will override the speed selected in the fdt for that port */
debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
}
/* i2c write version without the register address */
-int i2c_write_data(uchar chip, uchar *buffer, int len)
+int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
{
int rc;
debug("\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra_i2c_write_data(chip << 1, buffer, len);
+ rc = tegra_i2c_write_data(bus, chip << 1, buffer, len);
if (rc)
debug("i2c_write_data(): rc=%d\n", rc);
}
/* i2c read version without the register address */
-int i2c_read_data(uchar chip, uchar *buffer, int len)
+int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
{
int rc;
debug("inside i2c_read_data():\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra_i2c_read_data(chip << 1, buffer, len);
+ rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
if (rc) {
debug("i2c_read_data(): rc=%d\n", rc);
return rc;
}
/* Probe to see if a chip is present. */
-int i2c_probe(uchar chip)
+static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
+ struct i2c_bus *bus;
int rc;
uchar reg;
debug("i2c_probe: addr=0x%x\n", chip);
+ bus = tegra_i2c_get_bus(adap);
+ if (!bus)
+ return 1;
reg = 0;
- rc = i2c_write_data(chip, ®, 1);
+ rc = i2c_write_data(bus, chip, ®, 1);
if (rc) {
debug("Error probing 0x%x.\n", chip);
return 1;
}
/* Read bytes */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
+ struct i2c_bus *bus;
uint offset;
int i;
debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
chip, addr, len);
+ bus = tegra_i2c_get_bus(adap);
+ if (!bus)
+ return 1;
if (!i2c_addr_ok(addr, alen)) {
debug("i2c_read: Bad address %x.%d.\n", addr, alen);
return 1;
data[alen - i - 1] =
(addr + offset) >> (8 * i);
}
- if (i2c_write_data(chip, data, alen)) {
+ if (i2c_write_data(bus, chip, data, alen)) {
debug("i2c_read: error sending (0x%x)\n",
addr);
return 1;
}
}
- if (i2c_read_data(chip, buffer + offset, 1)) {
+ if (i2c_read_data(bus, chip, buffer + offset, 1)) {
debug("i2c_read: error reading (0x%x)\n", addr);
return 1;
}
}
/* Write bytes */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
+ struct i2c_bus *bus;
uint offset;
int i;
debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
chip, addr, len);
+ bus = tegra_i2c_get_bus(adap);
+ if (!bus)
+ return 1;
if (!i2c_addr_ok(addr, alen)) {
debug("i2c_write: Bad address %x.%d.\n", addr, alen);
return 1;
for (i = 0; i < alen; i++)
data[alen - i - 1] = (addr + offset) >> (8 * i);
data[alen] = buffer[offset];
- if (i2c_write_data(chip, data, alen + 1)) {
+ if (i2c_write_data(bus, chip, data, alen + 1)) {
debug("i2c_write: error sending (0x%x)\n", addr);
return 1;
}
return 0;
}
-#if defined(CONFIG_I2C_MULTI_BUS)
-/*
- * Functions for multiple I2C bus handling
- */
-unsigned int i2c_get_bus_num(void)
-{
- return i2c_bus_num;
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
- if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited)
- return -1;
- i2c_bus_num = bus;
-
- return 0;
-}
-#endif
-
int tegra_i2c_get_dvc_bus_num(void)
{
int i;
- for (i = 0; i < CONFIG_SYS_MAX_I2C_BUS; i++) {
+ for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
struct i2c_bus *bus = &i2c_controllers[i];
if (bus->inited && bus->is_dvc)
return -1;
}
+
+/*
+ * Register soft i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
+ tegra_i2c_read, tegra_i2c_write,
+ tegra_i2c_set_bus_speed, 100000, 0, 0)
+U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
+ tegra_i2c_read, tegra_i2c_write,
+ tegra_i2c_set_bus_speed, 100000, 0, 1)
+U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
+ tegra_i2c_read, tegra_i2c_write,
+ tegra_i2c_set_bus_speed, 100000, 0, 2)
+U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
+ tegra_i2c_read, tegra_i2c_write,
+ tegra_i2c_set_bus_speed, 100000, 0, 3)
char env_buf[32]; /* buffer for getenv() before reloc. */
#ifdef CONFIG_TRACE
void *trace_buff; /* The trace buffer */
+#endif
+#if defined(CONFIG_SYS_I2C)
+ int cur_i2c_bus; /* current used i2c bus */
#endif
struct arch_global_data arch; /* architecture-specific data */
} gd_t;
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_HARD_I2C 1 /* To enable I2C support */
+#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x118000
-#define CONFIG_SYS_I2C2_OFFSET 0x119000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
/*
* RTC configuration
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
/* I2C EEPROM */
#define CONFIG_CMD_EEPROM
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C EEPROM */
#define CONFIG_ID_EEPROM
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC32) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C/EEPROM/RTC configuration
*/
-#define CONFIG_SOFT_I2C /* Software I2C support enabled */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
/*-----------------------------------------------------------------------
* I2C/EEPROM/RTC configuration
*/
-#define CONFIG_SOFT_I2C /* Software I2C support enabled */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_ETHADDR 00:40:a6:80:14:5
*/
-#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SDRAM_BANK0 1
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_IDENT_STRING "Cray L1"
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*
* I2C
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
#define CONFIG_SYS_SPD_BUS_NUM 0
#define IIC1_MCP3021_ADDR 0x4d
#define IIC1_USB2507_ADDR 0x2c
-#ifdef CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
-#endif
+#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} }
+
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
/* CAT24WC08/16... */
/*
* Enable I2C and select the hardware/software driver
*/
-#define CONFIG_HARD_I2C 1 /* CPM based I2C */
-#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
+#define CONFIG_HARD_I2C 1 /* CPM based I2C */
+#undef CONFIG_SYS_I2C_SOFT /* Bit-banged I2C */
#ifdef CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */
-#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */
+#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */
+#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */
#endif
-#ifdef CONFIG_SOFT_I2C
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if (bit) \
+ immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else \
+ immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if (bit) \
+ immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else \
+ immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif
/*
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
#if 0 /* test-only */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#else
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
#endif
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
#define CONFIG_SYS_EEPROM_WREN 1
* configuration items that the driver uses to drive the port pins.
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly. Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
+#endif /* CONFIG_SYS_I2C_SOFT */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* -------------------------------------------------------------------- */
/* Generic FreeScale hardware I2C support */
-#define CONFIG_HARD_I2C
-#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
#define CONFIG_CMD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-
-/* I2C bus configuration */
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_DOS_PARTITION
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
/*
* Command line configuration.
#define CONFIG_MISC_INIT_R 1
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
/*
* Software (bit-bang) I2C driver configuration
*/
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
/*
* Software (bit-bang) I2C driver configuration
*/
-#ifdef CONFIG_SOFT_I2C
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
/*
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
/*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C hardware support */
-#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
/*-----------------------------------------------------------------------
* Environment
/*
* enable I2C and select the hardware/software driver
*/
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
/*-----------------------------------------------------------------------
* I2C Configuration
/*
* enable I2C and select the hardware/software driver
*/
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#ifdef CONFIG_SOFT_I2C
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
+#endif /* CONFIG_SYS_I2C_SOFT */
/*-----------------------------------------------------------------------
#undef CONFIG_MCFPIT
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#undef CONFIG_MCFPIT
/* I2c */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
#undef CONFIG_MCFPIT
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x00000300
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_i2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_HOSTNAME M5253DEMO
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x00000280
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#endif
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x00000300
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
#endif
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x00000300
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#undef CONFIG_MCFPIT
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#undef CONFIG_MCFPIT
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#undef CONFIG_MCFPIT
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#undef CONFIG_MCFPIT
/* I2c */
-#undef CONFIG_FSL_I2C
+#undef CONFIG_SYS_FSL_I2C
#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#undef CONFIG_MCFPIT
/* I2c */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
#undef CONFIG_MCFPIT
/* I2c */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSLI2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
#endif
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x00008F00
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* PCI */
#endif
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x00008F00
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* PCI */
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 120000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/*
* General PCI
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C hardware support */
-#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
/*-----------------------------------------------------------------------
* Environment
#undef CONFIG_UCODE_PATCH
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0xFE
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
* The Atmel EEPROM uses 16Bit addressing.
***************************************************************/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* SPI on header J8
#define CONFIG_SYS_HUSH_PARSER
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* General PCI
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave addr */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Board info - revision and where boot from
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Config on-board EEPROM
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Config on-board RTC
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* SPI */
#define CONFIG_MPC8XXX_SPI
#define CONFIG_PCI
#define CONFIG_RTC_DS1337
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
/*
*/
/* I2C */
-#ifdef CONFIG_HARD_I2C
+#ifdef CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
/* Don't probe these addresses: */
#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
{1, CONFIG_SYS_I2C_8574_ADDR2}, \
#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
-#undef CONFIG_SOFT_I2C
-
#endif
/* Compact Flash */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
-#ifdef CONFIG_HARD_I2C
+#ifdef CONFIG_SYS_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#endif
#define CONFIG_CMD_PCI
#endif
-#ifdef CONFIG_HARD_I2C
+#ifdef CONFIG_SYS_I2C
#define CONFIG_CMD_I2C
#endif
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
/*
* Config on-board RTC
#define CONFIG_OF_STDOUT_VIA_ALIAS
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
/*
* General PCI
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Config on-board RTC
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Config on-board RTC
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
/*
* I2C2 EEPROM
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3100
/*
* General PCI
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* EEPROM */
#define CONFIG_ID_EEPROM
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* EEPROM */
#define CONFIG_ID_EEPROM
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* General PCI
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* I2C2 EEPROM
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* I2C2 EEPROM
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* General PCI
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* RapidIO MMU
#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET
#define CONFIG_MPC8XXX_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MISC_INIT_R
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 100000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/*
* DDR Setup
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C EEPROM */
#undef CONFIG_ID_EEPROM
#define CONFIG_FIT_VERBOSE
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* I2C2 EEPROM
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/*
* I2C2 EEPROM
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* I2C2 EEPROM
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
/*
* I2C2 EEPROM
#define CONFIG_FIT_VERBOSE 1
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* I2C2 EEPROM
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
/*
* I2C2 EEPROM
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x118000
-#define CONFIG_SYS_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/*
* RapidIO
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
* EEPROM of the SDRAM
* The Atmel EEPROM uses 16Bit addressing.
***************************************************************/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* I2C EEPROM (24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
#define CONFIG_SYS_EEPROM_WREN 1
"bootm"
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
"bootm"
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
/*
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*
* I2C EEPROM (24W16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
-#undef CONFIG_SORT_I2C /* To I2C with software support */
+#undef CONFIG_SYS_I2C_SOFT /* To I2C with software support */
#define CONFIG_SYS_I2C_SPEED 4700 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
+#if defined(CONFIG_SYS_I2C_SOFT)
+#define CONFIG_SYS_SYS_I2C_SOFT_SPEED 4700 /* I2C speed and slave address */
+#define CONFIG_SYS_SYS_I2C_SOFT_SLAVE 0x7F
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(50)
+#endif /* #define(CONFIG_SYS_I2C_SOFT) */
#define CONFIG_SYS_I2C_LCD_ADDR 0x8 /* LCD Control */
#define CONFIG_SYS_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
* I2C Configuration
*-----------------------------------------------------------------------------
*/
-#define CONFIG_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0x34
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0x34
/* enable I2C and select the hardware/software driver */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+#define CONFIG_SYS_I2C 1
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0x34
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x34
+#endif
+
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 40000 /* 40 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
+/* Software (bit-bang) I2C driver configuration */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if (bit) \
+ immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else \
+ immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if (bit) \
+ immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else \
+ immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+/* M41T11 Serial Access Timekeeper(R) SRAM */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+/* play along with the linux driver */
+#define CONFIG_SYS_M41T11_BASE_YEAR 1900
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
#endif
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C /* I2C bit-banged */
-
-# define CONFIG_SYS_I2C_SPEED 50000 /* 50 kHz is supposed to work */
-# define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
/*
#define CONFIG_SYS_HUSH_PARSER
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* General PCI
#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
-#define CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_HARD_I2C 1 /* To enable I2C support */
+#undef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly. Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
+#endif /* CONFIG_SYS_I2C_SOFT */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_HARD_I2C 1 /* To enable I2C support */
+#undef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly. Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
+#endif /* CONFIG_SYS_I2C_SOFT */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C
*/
-#define CONFIG_SOFT_I2C
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#if defined (CONFIG_SOFT_I2C)
#if 0 /* push-pull */
#define SDA 0x00800000
#define SCL 0x00000008
#define I2C_ACTIVE {DIR1|=SDA;}
#define I2C_TRISTATE {DIR1&=~SDA;}
#endif
-#endif
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
+/*
+ * The Catalyst CAT24WC32 has 32 byte page write mode using
+ * last 5 bits of the address
+ */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#if defined (CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
+# define CONFIG_SYS_I2C
+# define CONFIG_SYS_I2C_SOFT_SPEED 100000
+# define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
+/**/
# define SDA0 0x40
# define SCL0 0x80
# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
# define I2C_DELAY {udelay(5);}
# define I2C_ACTIVE {DDR0|=SDA0;}
# define I2C_TRISTATE {DDR0&=~SDA0;}
-# define CONFIG_SYS_I2C_SPEED 100000
-# define CONFIG_SYS_I2C_SLAVE 0x7F
+
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_FACT_ADDR 0x57
#endif
* Environment handler
* only the first 6k in EEPROM are available for user. Of that we use 256b
*/
-#define CONFIG_SOFT_I2C
#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET 0x1000
#define CONFIG_ENV_SIZE 0x0700
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x2000
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0xFE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R
-#if defined (CONFIG_SOFT_I2C)
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
+/**/
#define SDA 0x00010
#define SCL 0x00020
#define __I2C_DIR immr->im_cpm.cp_pbdir
#define I2C_DELAY { udelay(5); }
#define I2C_ACTIVE { __I2C_DIR |= SDA; }
#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
-#endif
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_BOOTCOMMAND "run flash_self"
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
/*
* Software (bit-bang) I2C driver configuration
#if CONFIG_I2C
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
/*
* Software (bit-bang) I2C driver configuration
*/
#define CONFIG_SYS_DTT_HYSTERESIS 3
#else
+#undef CONFIG_SYS_I2C
#undef CONFIG_HARD_I2C
-#undef CONFIG_SOFT_I2C
+#undef CONFIG_SYS_I2C_SOFT
#endif
/*
/*
* I2C
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
#define CONFIG_SYS_EEPROM_WREN 1
/*
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (ATMEL 24C04N)
*/
-#define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
/*-----------------------------------------------------------------------
* I2C EEPROM (PCF8594C)
/*
* I2C
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
/*
* Ethernet/EMAC/PHY
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
/* I2C speed and slave address */
#undef CONFIG_MCFPIT
/* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 80000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/*
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
-#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C_SOFT
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#endif
/*
* Misc Settings
#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
-
/*
* Memory Settings
*/
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL PF3
+#define PF_SDA PF2
+#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
+#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); \
+ *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); \
+ *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); \
+ asm("ssync;")
+#define I2C_SDA(bit) if (bit) { \
+ *pFIO_FLAG_S = PF_SDA; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SDA; \
+ asm("ssync;"); \
+ }
+#define I2C_SCL(bit) if (bit) { \
+ *pFIO_FLAG_S = PF_SCL; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SCL; \
+ asm("ssync;"); \
+ }
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
-
/*
* SPI Settings
*/
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C_SOFT
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
-
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0
+#endif
/*
* Compact Flash / IDE / ATA Settings
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C_SOFT
+#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0
+#endif
/*
* Misc Settings
# ifdef CONFIG_SPI_FLASH
# define CONFIG_CMD_SF
# endif
-# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
# define CONFIG_CMD_I2C
# define CONFIG_SOFT_I2C_READ_REPEATED_START
# endif
/*
* I2C Settings
*/
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
# ifndef CONFIG_SYS_I2C_SPEED
# define CONFIG_SYS_I2C_SPEED 50000
# endif
#define SHARED_RESOURCES 1
/* Is I2C bit-banged? */
-#undef CONFIG_SOFT_I2
/*
* Clock Settings
# undef CONFIG_CMD_NET
#endif
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
# define CONFIG_CMD_I2C
#endif
* Note these pins are arbitrarily chosen because we aren't using
* them yet. You can (and probably should) change these values!
*/
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0xFE
+#define CONFIG_SYS_SOFT_I2C_SPEED 50000
+#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE
#endif
/*
* Soft I2C settings (BF561 does not have hard I2C)
* PF12,13 on SPI connector 0.
*/
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
# define CONFIG_CMD_I2C
# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12
# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13
/*
* I2C
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
* I2C stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid i2c probe hangup (why?) */
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#if defined(CONFIG_CMD_EEPROM)
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
-#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/*
* I2C
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_CMD_I2C
-
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* Probing DP501 I2C-Bridge will hang */
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \
{0, 0x3b}, {0, 0x50} }
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x118000
-#define CONFIG_SYS_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
/*
* RapidIO
#define CONFIG_USART_ID 0/* ignored in arm */
#undef CONFIG_HARD_I2C
-#undef CONFIG_SOFT_I2C
#define AT91_PIN_SDA (1<<25)
#define AT91_PIN_SCL (1<<26)
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_DHCP
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#endif
* I2C configuration
*
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */
/*
* MII PHY configuration
* I2C configuration
*
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */
/*
* MII PHY configuration
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
-#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
* configuration items that the driver uses to drive the port pins.
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly. Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
+#endif /* CONFIG_SYS_I2C_SOFT */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*
* I2C stuff
*/
-#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
/*
* I2C stuff
*/
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
/*
* FLASH organization
* configuration items that the driver uses to drive the port pins.
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_I2C_OFFSET 0x00000300
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_FSL_I2C_SPEED 100000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
* I2C-Bus
*/
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
-
-#ifndef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0
/* Software I2C driver configuration */
else \
writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
-
-#endif /* CONFIG_HARD_I2C */
+#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
/* I2C-RTC */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */
/*
* Software (bit-bang) I2C driver configuration
*/
-#ifdef CONFIG_SOFT_I2C
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
+#endif /* CONFIG_SYS_I2C_SOFT */
/* #define CONFIG_RTC_DS174x */
/* I2C */
#define CONFIG_SYS_MAX_I2C_BUS 1
-#define CONFIG_SYS_I2C_SLAVE 0
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0
+
#define I2C_SOFT_DECLARATIONS
#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
/*
* I2C
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
/*
* Default environment variables
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-
/*
* Misc Settings
*/
/*
* I2C
*/
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/*
* I2C
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
/*
* I2C stuff
*/
-#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_PCA9698 1 /* NXP PCA9698 */
/*
* I2C stuff
*/
-#define CONFIG_SYS_I2C_SPEED 400000
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
/*
* Software (bit-bang) I2C driver configuration
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
#define IIC0_BOOTPROM_ADDR 0x50
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 1
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MUX
/* Support the IVM EEprom */
#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
#endif /* CFG_SYS_RAMBOOT */
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_NUM_I2C_BUSES 4
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 200000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 200000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+ {1, {I2C_NULL_HOP} } }
+
+#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
+#define CONFIG_SYS_DTT_BUS_NUM 1
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
CONFIG_KM_DEF_ARCH \
- "EEprom_ivm=pca9547:70:9\0" \
"newenv=" \
"prot off 0xF00C0000 +0x40000 && " \
"era 0xF00C0000 +0x40000\0" \
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SF
-#define CONFIG_SOFT_I2C /* I2C bit-banged */
/* SPI NOR Flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 8100000
/*
* I2C related stuff
*/
+#undef CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+
#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
-#if defined(CONFIG_SOFT_I2C)
+#if defined(CONFIG_SYS_I2C_SOFT)
+
+#define CONFIG_SYS_NUM_I2C_BUSES 6
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+ }
+
#ifndef __ASSEMBLY__
#include <asm/arch-kirkwood/gpio.h>
extern void __set_direction(unsigned pin, int high);
#define I2C_DELAY udelay(1)
#define I2C_SOFT_DECLARATIONS
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0
+#define CONFIG_SYS_I2C_SOFT_SPEED 100000
#endif
/* EEprom support 24C128, 24C256 valid for environment eeprom */
#define CONFIG_SYS_EEPROM_WREN
#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
-#define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0"
+#define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS
#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
#else
#define CONFIG_KM_NEW_ENV \
"newenv=setenv addr 0x100000 && " \
- "i2c dev 1; mw.b ${addr} 0 4 && " \
+ "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \
+ "mw.b ${addr} 0 4 && " \
"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
CONFIG_KM_DEF_ENV \
CONFIG_KM_NEW_ENV \
"arch=arm\0" \
- "EEprom_ivm=" KM_IVM_BUS "\0" \
""
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_BOARD_EXTRA_ENV \
CONFIG_KM_DEF_ENV \
- "EEprom_ivm=pca9544a:70:4 \0" \
"unlock=yes\0" \
"newenv=" \
"prot off 0xFE0C0000 +0x40000 && " \
#endif /* CONFIG_ENV_IS_IN_FLASH */
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_NUM_I2C_BUSES 3
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
+#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
+ {0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
+
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/*
* Software (bit-bang) I2C driver configuration
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
+#define CONFIG_SYS_DTT_BUS_NUM 2
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
#define CONFIG_HOSTNAME km_kirkwood
#define CONFIG_KM_DISABLE_PCIE
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/* KM_KIRKWOOD_PCI */
#elif defined(CONFIG_KM_KIRKWOOD_PCI)
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
#define CONFIG_HOSTNAME km_kirkwood_pci
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_FPGA_CONFIG
/* KM_NUSA */
#elif defined(CONFIG_KM_NUSA)
-#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_IDENT_STRING "\nKeymile NUSA"
#define CONFIG_HOSTNAME kmnusa
#undef CONFIG_SYS_KWD_CONFIG
#elif defined(CONFIG_KM_MGCOGE3UN)
#define CONFIG_IDENT_STRING "\nKeymile COGE3UN"
#define CONFIG_HOSTNAME mgcoge3un
-#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
/* KMCOGE5UN */
#elif defined(CONFIG_KM_COGE5UN)
#define CONFIG_IDENT_STRING "\nKeymile COGE5UN"
-#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
#elif defined(CONFIG_KM_PORTL2)
#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
#define CONFIG_HOSTNAME portl2
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_PIGGY4_88E6061
/* KM_SUV31 */
#elif defined(CONFIG_KM_SUV31)
-#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_IDENT_STRING "\nKeymile SUV31"
#define CONFIG_HOSTNAME kmsuv31
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#include "km/km_arm.h"
#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
+#define KM_ENV_BUS 5 /* I2C2 (Mux-Port 5)*/
#endif
#if defined(CONFIG_KM_PIGGY4_88E6352)
/*
* I2C
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#undef CONFIG_STATUS_LED /* Status LED disabled */
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
/*
* I2C
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/*
* General PCI
/*
* I2C buses and peripherals
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* I2C RTC - M41T81 */
#define CONFIG_RTC_M41T62
/*
* I2C stuff
*/
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
/* RTC */
#define CONFIG_RTC_DS1337
#ifndef __ASSEMBLY__
#include <asm/arch/gpio.h>
#define CONFIG_CMD_I2C
-#define CONFIG_SOFT_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT 1 /* I2C bit-banged */
+#define I2C_SOFT_DEFS
+#define CONFIG_SYS_I2C_SOFT_SPEED 400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define __SDA 63
#define __SCL 62
#define I2C_SDA(x) nmk_gpio_set(__SDA, x)
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
/* RTC and I2C stuff */
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#undef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#ifdef CONFIG_SOFT_I2C
-# define CONFIG_I2C_CMD_TREE
-# define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED 100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
+
/* Configure data and clock pins for pio */
# define I2C_INIT { \
at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
/* Set clock pin */
# define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
# define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
+#endif /* CONFIG_SYS_I2C_SOFT */
/*
* BOOTP options
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
/*
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
/*-----------------------------------------------------------------------
* I2C RTC
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
*/
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define IIC0_BOOTPROM_ADDR 0x50
#define IIC0_ALT_BOOTPROM_ADDR 0x54
/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3)
#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0)
-#define CONFIG_SOFT_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 7
#define CONFIG_USB_GADGET
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0
#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 7
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
/*
* Software (bit-bang) I2C driver configuration
*/
-#ifdef CONFIG_SOFT_I2C
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
/* Define this to reserve an entire FLASH sector for
* environment variables. Otherwise, the environment will be
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
/*-----------------------------------------------------------------------
* PCI stuff
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C1_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
/* TSEC */
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
/*
* General PCI
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* RapidIO MMU
* IIC stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
#define I2C_INIT
#define I2C_ACTIVE 0
#define I2C_TRISTATE 0
-#define CONFIG_SYS_I2C_SPEED 100000 /* use the standard 100kHz speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* mask valid bits */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* mask valid bits */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
/* I2C */
-#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 4
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/*
* I2C
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_PROMPT "Snapper> "
/* I2C - Bit-bashed */
-#define CONFIG_SOFT_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#define CONFIG_I2C_MULTI_BUS
#define I2C_INIT do { \
at91_set_gpio_output(AT91_PIN_PA23, 1); \
at91_set_gpio_output(AT91_PIN_PA24, 1); \
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 102124
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 102124
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C RTC */
#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
*/
#if defined(CONFIG_CMD_I2C)
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
#endif
/*-----------------------------------------------------------------------
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+
#if 0
#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
#else
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CONFIG_SYS_I2C_NOPROBES
#endif
-#define CONFIG_SYS_I2C_OFFSET 0x3000
/* RapdIO Map configuration, mapped 1:1.
*/
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#undef CONFIG_SYS_I2C_NOPROBES
-#define CONFIG_SYS_I2C_OFFSET 0x3000
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
/*
* I2C
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x118000
-#define CONFIG_SYS_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 100000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
* I2C stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid i2c probe hangup (why?) */
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#undef CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#endif
/* remove I2C support */
-#ifdef CONFIG_TEGRA_I2C
-#undef CONFIG_TEGRA_I2C
+#ifdef CONFIG_SYS_I2C_TEGRA
+#undef CONFIG_SYS_I2C_TEGRA
#endif
#ifdef CONFIG_CMD_I2C
#undef CONFIG_CMD_I2C
#define CONFIG_CMD_USB
/* I2C support must always be enabled */
-#define CONFIG_SOFT_I2C
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
+
#define I2C0_PORT AT91_PIO_PORTA
#define SDA0_PIN 23
#define SCL0_PIN 24
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SOFT_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 15
#define CONFIG_CMD_SF
/* I2C */
-#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 4
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
*/
#define CONFIG_U8500_I2C
#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */
*/
/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#ifdef CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
/*-----------------------------------------------------------------------
* I2C EEPROM (24C164)
*------------------------------------------------------------------*/
#if 1
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#endif
/*
* I2C/EEPROM
*/
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
/*
* Software (bit-bang) I2C driver configuration
#undef CONFIG_CMD_USB
#undef CONFIG_SMC911X
-#undef CONFIG_SOFT_I2C
+#undef CONFIG_SYS_I2C_SOFT
#undef CONFIG_SOURCE
#undef CONFIG_SYS_LONGHELP
#undef CONFIG_TIMESTAMP
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C0_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x82000000
#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
#ifndef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
/* Software I2C driver configuration */
-
#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
#define CONFIG_OF_STDOUT_VIA_ALIAS
/* I2C */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
-#define CONFIG_SYS_I2C1_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
* I2C stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
-#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 4
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/*
* I2C
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7f
/* I2C EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 100000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* PEX8518 slave I2C interface */
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* PEX8518 slave I2C interface */
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C DS7505 temperature sensor */
#define CONFIG_DTT_LM75
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define IIC0_BOOTPROM_ADDR 0x50
#define IIC0_ALT_BOOTPROM_ADDR 0x54
/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
/* #if defined(CONFIG_CMD_EEPROM) */
/* #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
/* these are for the ST M24C02 2kbit serial i2c eeprom */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */
COMPAT_INFINEON_SLB9635_TPM, /* Infineon SLB9635 TPM */
COMPAT_INFINEON_SLB9645_TPM, /* Infineon SLB9645 TPM */
+ COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */
COMPAT_COUNT,
};
/*
+ * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2009 - 2013 Heiko Schocher <hs@denx.de>
+ * Changes for multibus/multiadapter I2C support.
+ *
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-#ifdef CONFIG_I2C_MULTI_BUS
-#define MAX_I2C_BUS 2
-#define I2C_MULTI_BUS 1
+#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
+/* no muxes used bus = i2c adapters */
+#define CONFIG_SYS_I2C_DIRECT_BUS 1
+#define CONFIG_SYS_I2C_MAX_HOPS 0
+#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
#else
-#define MAX_I2C_BUS 1
-#define I2C_MULTI_BUS 0
-#endif
-
-#if !defined(CONFIG_SYS_MAX_I2C_BUS)
-#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS
+/* we use i2c muxes */
+#undef CONFIG_SYS_I2C_DIRECT_BUS
#endif
/* define the I2C bus number for RTC and DTT if not already done */
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
+struct i2c_adapter {
+ void (*init)(struct i2c_adapter *adap, int speed,
+ int slaveaddr);
+ int (*probe)(struct i2c_adapter *adap, uint8_t chip);
+ int (*read)(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer,
+ int len);
+ int (*write)(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer,
+ int len);
+ uint (*set_bus_speed)(struct i2c_adapter *adap,
+ uint speed);
+ int speed;
+ int slaveaddr;
+ int init_done;
+ int hwadapnr;
+ char *name;
+};
+
+#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
+ _set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
+ { \
+ .init = _init, \
+ .probe = _probe, \
+ .read = _read, \
+ .write = _write, \
+ .set_bus_speed = _set_speed, \
+ .speed = _speed, \
+ .slaveaddr = _slaveaddr, \
+ .init_done = 0, \
+ .hwadapnr = _hwadapnr, \
+ .name = #_name \
+};
+
+#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
+ _set_speed, _speed, _slaveaddr, _hwadapnr) \
+ ll_entry_declare(struct i2c_adapter, _name, i2c) = \
+ U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
+ _set_speed, _speed, _slaveaddr, _hwadapnr, _name);
+
+struct i2c_adapter *i2c_get_adapter(int index);
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+struct i2c_mux {
+ int id;
+ char name[16];
+};
+
+struct i2c_next_hop {
+ struct i2c_mux mux;
+ uint8_t chip;
+ uint8_t channel;
+};
+
+struct i2c_bus_hose {
+ int adapter;
+ struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS];
+};
+#define I2C_NULL_HOP {{-1, ""}, 0, 0}
+extern struct i2c_bus_hose i2c_bus[];
+
+#define I2C_ADAPTER(bus) i2c_bus[bus].adapter
+#else
+#define I2C_ADAPTER(bus) bus
+#endif
+#define I2C_BUS gd->cur_i2c_bus
+
+#define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus))
+#define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus)
+#define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr)
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#define I2C_MUX_PCA9540_ID 1
+#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"}
+#define I2C_MUX_PCA9542_ID 2
+#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
+#define I2C_MUX_PCA9544_ID 3
+#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
+#define I2C_MUX_PCA9547_ID 4
+#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
+#endif
+
#ifndef I2C_SOFT_DECLARATIONS
# if defined(CONFIG_MPC8260)
# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
void i2c_board_late_init(void);
#endif
-#if defined(CONFIG_I2C_MUX)
-
-typedef struct _mux {
- uchar chip;
- uchar channel;
- char *name;
- struct _mux *next;
-} I2C_MUX;
-
-typedef struct _mux_device {
- int busid;
- I2C_MUX *mux; /* List of muxes, to reach the device */
- struct _mux_device *next;
-} I2C_MUX_DEVICE;
-
-I2C_MUX_DEVICE *i2c_mux_search_device(int id);
-I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
-int i2x_mux_select_mux(int bus);
-int i2c_mux_ident_muxstring_f (uchar *buf);
+#ifdef CONFIG_SYS_I2C
+/*
+ * i2c_get_bus_num:
+ *
+ * Returns index of currently active I2C bus. Zero-based.
+ */
+unsigned int i2c_get_bus_num(void);
+
+/*
+ * i2c_set_bus_num:
+ *
+ * Change the active I2C bus. Subsequent read/write calls will
+ * go to this one.
+ *
+ * bus - bus index, zero based
+ *
+ * Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_num(unsigned int bus);
+
+/*
+ * i2c_init_all():
+ *
+ * Initializes all I2C adapters in the system. All i2c_adap structures must
+ * be initialized beforehead with function pointers and data, including
+ * speed and slaveaddr. Returns 0 on success, non-0 on failure.
+ */
+void i2c_init_all(void);
+
+/*
+ * Probe the given I2C chip address. Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uint8_t chip);
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uint8_t chip, unsigned int addr, int alen,
+ uint8_t *buffer, int len);
+
+int i2c_write(uint8_t chip, unsigned int addr, int alen,
+ uint8_t *buffer, int len);
+
+/*
+ * Utility routines to read/write registers.
+ */
+uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
+
+void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
+
+/*
+ * i2c_set_bus_speed:
+ *
+ * Change the speed of the active I2C bus
+ *
+ * speed - bus speed in Hz
+ *
+ * Returns: new bus speed
+ *
+ */
+unsigned int i2c_set_bus_speed(unsigned int speed);
+
+/*
+ * i2c_get_bus_speed:
+ *
+ * Returns speed of currently active I2C bus in Hz
+ */
+
+unsigned int i2c_get_bus_speed(void);
+
+/*
+ * i2c_reloc_fixup:
+ *
+ * Adjusts I2C pointers after U-Boot is relocated to DRAM
+ */
+void i2c_reloc_fixup(void);
+#if defined(CONFIG_SYS_I2C_SOFT)
+void i2c_soft_init(void);
+void i2c_soft_active(void);
+void i2c_soft_tristate(void);
+int i2c_soft_read(void);
+void i2c_soft_sda(int bit);
+void i2c_soft_scl(int bit);
+void i2c_soft_delay(void);
#endif
+#else
/*
* Probe the given I2C chip address. Returns 0 if a chip responded,
*/
unsigned int i2c_get_bus_speed(void);
+#endif /* CONFIG_SYS_I2C */
+
+/*
+ * only for backwardcompatibility, should go away if we switched
+ * completely to new multibus support.
+ */
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
+# if !defined(CONFIG_SYS_MAX_I2C_BUS)
+# define CONFIG_SYS_MAX_I2C_BUS 2
+# endif
+# define I2C_MULTI_BUS 0
+#else
+# define CONFIG_SYS_MAX_I2C_BUS 1
+# define I2C_MULTI_BUS 0
+#endif
/* NOTE: These two functions MUST be always_inline to avoid code growth! */
static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"),
COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"),
+ COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
projects / karo-tx-uboot.git / commitdiff