arm, imx6, i2c: add I2C4 for MX6DL
authorHeiko Schocher <hs@denx.de>
Wed, 13 May 2015 05:50:47 +0000 (07:50 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 1 Sep 2015 12:59:55 +0000 (14:59 +0200)
add I2C4 modul for MX6DL based boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/imx-common/i2c-mxv7.c
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
drivers/i2c/mxc_i2c.c

index 7f67941..8e2086e 100644 (file)
@@ -234,23 +234,34 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 #endif
 
 #ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 reg;
        u32 mask;
 
-       if (i2c_num > 2)
+       if (i2c_num > 3)
                return -EINVAL;
-
-       mask = MXC_CCM_CCGR_CG_MASK
-               << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
-       reg = __raw_readl(&imx_ccm->CCGR2);
-       if (enable)
-               reg |= mask;
-       else
-               reg &= ~mask;
-       __raw_writel(reg, &imx_ccm->CCGR2);
+       if (i2c_num < 3) {
+               mask = MXC_CCM_CCGR_CG_MASK
+                       << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+                       + (i2c_num << 1));
+               reg = __raw_readl(&imx_ccm->CCGR2);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, &imx_ccm->CCGR2);
+       } else {
+               mask = MXC_CCM_CCGR_CG_MASK
+                       << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
+               reg = __raw_readl(&imx_ccm->CCGR1);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, &imx_ccm->CCGR1);
+       }
        return 0;
 }
 #endif
index 1a632e7..33205fb 100644 (file)
@@ -67,9 +67,12 @@ static void * const i2c_bases[] = {
 #ifdef I2C3_BASE_ADDR
        (void *)I2C3_BASE_ADDR,
 #endif
+#ifdef I2C4_BASE_ADDR
+       (void *)I2C4_BASE_ADDR,
+#endif
 };
 
-/* i2c_index can be from 0 - 2 */
+/* i2c_index can be from 0 - 3 */
 int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
              struct i2c_pads_info *p)
 {
index ce465c6..fdbffad 100644 (file)
@@ -547,6 +547,8 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET               10
 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET               8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK                 (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                        12
 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                  (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET          14
index 8f47fd7..07119bd 100644 (file)
 #define UART3_BASE                     (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                     (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                     (AIPS2_OFF_BASE_ADDR + 0x74000)
-#define IP2APB_USBPHY1_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x78000)
-#define IP2APB_USBPHY2_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x7C000)
+#define I2C4_BASE_ADDR                 (AIPS2_OFF_BASE_ADDR + 0x78000)
 
 #ifdef CONFIG_SOC_MX6SX
 #define GIS_BASE_ADDR                  (AIPS3_ARB_BASE_ADDR + 0x04000)
index da55c6b..0a00506 100644 (file)
@@ -415,7 +415,10 @@ static void * const i2c_bases[] = {
        defined(CONFIG_SOC_MX6) || defined(CONFIG_SOC_LS102XA)
        (void *)I2C1_BASE_ADDR,
        (void *)I2C2_BASE_ADDR,
-       (void *)I2C3_BASE_ADDR
+       (void *)I2C3_BASE_ADDR,
+#if defined(CONFIG_SOC_MX6DL)
+       (void *)I2C4_BASE_ADDR
+#endif
 #elif defined(CONFIG_SOC_VF610)
        (void *)I2C0_BASE_ADDR
 #elif defined(CONFIG_FSL_LSCH3)