/errlog
/reloc_off
-!/spl/Makefile
/spl/*
+!/spl/Makefile
/tpl/
#
#
VERSION = 2014
-PATCHLEVEL = 04
+PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
#
# If $(quiet) is empty, the whole command will be printed.
-# If it is set to "quiet_", only the short version will be printed.
+# If it is set to "quiet_", only the short version will be printed.
# If it is set to "silent_", nothing will be printed at all, since
# the variable $(silent_cmd_cc_o_c) doesn't exist.
#
endif
endif
+# Prohibit date/time macros, which would make the build non-deterministic
+KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
+
ifneq ($(CONFIG_SYS_TEXT_BASE),)
KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
endif
u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
+MKIMAGEFLAGS_u-boot-spl.gph = -A $(ARCH) -T gpimage -C none \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n SPL
+spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+ --gap-fill=0
+u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
+ $(call if_changed,pad_cat)
+
ifneq ($(CONFIG_TEGRA),)
OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
$(call cmd,u-boot__) common/system_map.o
endif
-# The actual objects are generated when descending,
+# The actual objects are generated when descending,
# make sure no implicit rule kicks in
$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
-# FIXME Should go into a make.lib or something
+# FIXME Should go into a make.lib or something
# ===========================================================================
quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs)))
directory according to the instructions in cogent/README.
+Sandbox Environment:
+--------------------
+
+U-Boot can be built natively to run on a Linux host using the 'sandbox'
+board. This allows feature development which is not board- or architecture-
+specific to be undertaken on a native platform. The sandbox is also used to
+run some of U-Boot's tests.
+
+See board/sandbox/sandbox/README.sandbox for more details.
+
+
Configuration Options:
----------------------
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
+ CONFIG_SYS_GENERIC_GLOBAL_DATA
+ Defines global data is initialized in generic board board_init_f().
+ If this macro is defined, global data is created and cleared in
+ generic board board_init_f(). Without this macro, architecture/board
+ should initialize global data before calling board_init_f().
+
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
+ CONFIG_SERIAL_HW_FLOW_CONTROL
+
+ Define this variable to enable hw flow control in serial driver.
+ Current user of this option is drivers/serial/nsl16550.c driver
- Console Interface:
Depending on board, define exactly one serial port
supports MMC, NAND and YMODEM loading of U-Boot and NAND
NAND loading of the Linux Kernel.
+ CONFIG_SPL_OS_BOOT
+ Enable booting directly to an OS from SPL.
+ See also: doc/README.falcon
+
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
+ CONFIG_SPL_MTD_SUPPORT
+ Support for the MTD subsystem within SPL. Useful for
+ environment on NAND support within SPL.
+
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
drivers/ddr/fsl/libddr.o in SPL binary.
- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
Enables the RTC32K OSC on AM33xx based plattforms
+- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+ Option to disable subpage write in NAND driver
+ driver that uses this:
+ drivers/mtd/nand/davinci_nand.c
+
Freescale QE/FMAN Firmware Support:
-----------------------------------
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_LMB
#endif /*__ASM_ARC_CONFIG_H_ */
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch/spl.h>
#include "cpu.h"
void spl_board_init(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ struct apb_misc_pp_ctlr *apb_misc =
+ (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
/* enable JTAG */
- writel(0xC0, &pmt->pmt_cfg_ctl);
+ writel(0xC0, &apb_misc->cfg_ctl);
board_init_uart_f();
debug("enable_cpu_power_rail entry\n");
/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
- pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
/*
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
debug("enable_cpu_power_rail entry\n");
/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
- pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
pmic_enable_cpu_vdd();
}
#if defined(CONFIG_SYS_DA850_PLL_INIT)
-void da850_waitloop(unsigned long loopcnt)
+static void da850_waitloop(unsigned long loopcnt)
{
unsigned long i;
asm(" NOP");
}
-int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
+static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
{
if (reg == davinci_pllc0_regs)
/* Unlock PLL registers. */
#endif /* CONFIG_SYS_DA850_PLL_INIT */
#if defined(CONFIG_SYS_DA850_DDR_INIT)
-int da850_ddr_setup(void)
+static int da850_ddr_setup(void)
{
unsigned long tmp;
}
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
lpsc_on(DAVINCI_LPSC_UART0);
}
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
}
#endif
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
}
#endif
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_DM646X_LPSC_I2C);
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
+obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_TEGRA) += tegra-common/
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
return 0;
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
while (readl(&wdtimer->wdtwwps) != 0x0)
;
}
-#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void s_init(void)
{
/*
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_TI81XX
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;
--- /dev/null
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int timer_init(void)
+{
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ ulong nowl, nowu;
+
+ asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (nowl), "=r" (nowu));
+
+ gd->arch.tbl = nowl;
+ gd->arch.tbu = nowu;
+
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+
+ulong get_timer(ulong base)
+{
+ return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long endtime;
+
+ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+ 1000UL);
+
+ endtime += get_ticks();
+
+ while (get_ticks() < endtime)
+ ;
+}
+
+ulong get_tbclk(void)
+{
+ return gd->arch.timer_rate_hz;
+}
--- /dev/null
+#
+# (C) Copyright 2012-2014
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += aemif.o
+obj-y += init.o
+obj-y += psc.o
+obj-y += clock.o
+obj-y += cmd_clock.o
+obj-y += cmd_mon.o
+obj-y += keystone_nav.o
+obj-y += msmc.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-y += ddr3.o
--- /dev/null
+/*
+ * Keystone2: Asynchronous EMIF Configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emif_defs.h>
+
+#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
+#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
+#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
+#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
+#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
+#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
+#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
+#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
+#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
+#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
+
+#define set_config_field(reg, field, val) \
+ do { \
+ if (val != -1) { \
+ reg &= ~AEMIF_CFG_##field(0xffffffff); \
+ reg |= AEMIF_CFG_##field(val); \
+ } \
+ } while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+ unsigned long tmp;
+
+ if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+ tmp = __raw_readl(&davinci_emif_regs->nandfcr);
+ tmp |= (1 << cs);
+ __raw_writel(tmp, &davinci_emif_regs->nandfcr);
+
+ } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+ tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
+ tmp |= (1 << cs);
+ __raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
+ }
+
+ tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
+
+ set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
+ set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
+ set_config_field(tmp, WR_SETUP, cfg->wr_setup);
+ set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
+ set_config_field(tmp, WR_HOLD, cfg->wr_hold);
+ set_config_field(tmp, RD_SETUP, cfg->rd_setup);
+ set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
+ set_config_field(tmp, RD_HOLD, cfg->rd_hold);
+ set_config_field(tmp, TURN_AROUND, cfg->turn_around);
+ set_config_field(tmp, WIDTH, cfg->width);
+
+ __raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+ int cs;
+
+ for (cs = 0; cs < num_cs; cs++)
+ configure_async_emif(cs, config + cs);
+}
--- /dev/null
+/*
+ * Keystone2: pll initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+static void wait_for_completion(const struct pll_init_data *data)
+{
+ int i;
+ for (i = 0; i < 100; i++) {
+ sdelay(450);
+ if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
+ break;
+ }
+}
+
+struct pll_regs {
+ u32 reg0, reg1;
+};
+
+static const struct pll_regs pll_regs[] = {
+ [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
+ [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
+ [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
+ [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
+ [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
+};
+
+/* Fout = Fref * NF(mult) / NR(prediv) / OD */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(K2HK_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = K2HK_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = K2HK_ARMPLLCTL0;
+ break;
+ case DDR3A_PLL:
+ ret = external_clk[ddr3a_clk];
+ reg = K2HK_DDR3APLLCTL0;
+ break;
+ case DDR3B_PLL:
+ ret = external_clk[ddr3b_clk];
+ reg = K2HK_DDR3BPLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
+ case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
+ case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+ return 0;
+}
+
+void init_pll(const struct pll_init_data *data)
+{
+ u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
+
+ pllm = data->pll_m - 1;
+ plld = (data->pll_d - 1) & PLL_DIV_MASK;
+ pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
+
+ if (data->pll == MAIN_PLL) {
+ /* The requered delay before main PLL configuration */
+ sdelay(210000);
+
+ tmp = pllctl_reg_read(data->pll, secctl);
+
+ if (tmp & (PLLCTL_BYPASS)) {
+ setbits_le32(pll_regs[data->pll].reg1,
+ BIT(MAIN_ENSAT_OFFSET));
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
+ PLLCTL_PLLENSRC);
+ sdelay(340);
+
+ pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+ sdelay(21000);
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+ } else {
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
+ PLLCTL_PLLENSRC);
+ sdelay(340);
+ }
+
+ pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
+
+ clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
+ (pllm << 6));
+
+ /* Set the BWADJ (12 bit field) */
+ tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
+ clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+ (tmp_ctl << PLL_BWADJ_LO_SHIFT));
+ clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+ (tmp_ctl >> 8));
+
+ /*
+ * Set the pll divider (6 bit field) *
+ * PLLD[5:0] is located in MAINPLLCTL0
+ */
+ clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+
+ /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
+ pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
+ (pllod << PLL_CLKOD_SHIFT));
+ wait_for_completion(data);
+
+ pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
+ pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
+ pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
+ pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
+ pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
+
+ pllctl_reg_setbits(data->pll, alnctl, 0x1f);
+
+ /*
+ * Set GOSET bit in PLLCMD to initiate the GO operation
+ * to change the divide
+ */
+ pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
+ sdelay(1500); /* wait for the phase adj */
+ wait_for_completion(data);
+
+ /* Reset PLL */
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+ sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
+
+ pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
+
+ tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+
+ } else if (data->pll == TETRIS_PLL) {
+ bwadj = pllm >> 1;
+ /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
+ setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ /*
+ * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
+ * only applicable for Kepler
+ */
+ clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
+ setbits_le32(pll_regs[data->pll].reg1 ,
+ PLL_PLLRST | PLLCTL_ENSAT);
+
+ /*
+ * 3 Program PLLM and PLLD in PLLCTL0 register
+ * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
+ * PLLCTL1 register. BWADJ value must be set
+ * to ((PLLM + 1) >> 1) – 1)
+ */
+ tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
+ (pllm << 6) |
+ (plld & PLL_DIV_MASK) |
+ (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
+ __raw_writel(tmp, pll_regs[data->pll].reg0);
+
+ /* Set BWADJ[11:8] bits */
+ tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp &= ~(PLL_BWADJ_HI_MASK);
+ tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
+ __raw_writel(tmp, pll_regs[data->pll].reg1);
+ /*
+ * 5 Wait for at least 5 us based on the reference
+ * clock (PLL reset time)
+ */
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+
+ /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
+ clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+ /*
+ * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
+ * (PLL lock time)
+ */
+ sdelay(105000);
+ /* 8 disable bypass */
+ clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ /*
+ * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
+ * only applicable for Kepler
+ */
+ setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ } else {
+ setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+ /*
+ * process keeps state of Bypass bit while programming
+ * all other DDR PLL settings
+ */
+ tmp = __raw_readl(pll_regs[data->pll].reg0);
+ tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
+
+ /*
+ * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
+ * bypass disabled
+ */
+ bwadj = pllm >> 1;
+ tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
+ (pllm << PLL_MULT_SHIFT) |
+ (plld & PLL_DIV_MASK) |
+ (pllod << PLL_CLKOD_SHIFT);
+ __raw_writel(tmp, pll_regs[data->pll].reg0);
+
+ /* Set BWADJ[11:8] bits */
+ tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp &= ~(PLL_BWADJ_HI_MASK);
+ tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
+
+ /* set PLL Select (bit 13) for PASS PLL */
+ if (data->pll == PASS_PLL)
+ tmp |= PLLCTL_PAPLL;
+
+ __raw_writel(tmp, pll_regs[data->pll].reg1);
+
+ /* Reset bit: bit 14 for both DDR3 & PASS PLL */
+ tmp = PLL_PLLRST;
+ /* Set RESET bit = 1 */
+ setbits_le32(pll_regs[data->pll].reg1, tmp);
+ /* Wait for a minimum of 7 us*/
+ sdelay(21000);
+ /* Clear RESET bit */
+ clrbits_le32(pll_regs[data->pll].reg1, tmp);
+ sdelay(105000);
+
+ /* clear BYPASS (Enable PLL Mode) */
+ clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+ }
+
+ /*
+ * This is required to provide a delay between multiple
+ * consequent PPL configurations
+ */
+ sdelay(210000);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+ int i;
+
+ for (i = 0; i < num_pll; i++)
+ init_pll(&config[i]);
+}
--- /dev/null
+/*
+ * keystone2: commands for clocks
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/psc_defs.h>
+
+struct pll_init_data cmd_pll_data = {
+ .pll = MAIN_PLL,
+ .pll_m = 16,
+ .pll_d = 1,
+ .pll_od = 2,
+};
+
+int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 5)
+ goto pll_cmd_usage;
+
+ if (strncmp(argv[1], "pa", 2) == 0)
+ cmd_pll_data.pll = PASS_PLL;
+ else if (strncmp(argv[1], "arm", 3) == 0)
+ cmd_pll_data.pll = TETRIS_PLL;
+ else if (strncmp(argv[1], "ddr3a", 5) == 0)
+ cmd_pll_data.pll = DDR3A_PLL;
+ else if (strncmp(argv[1], "ddr3b", 5) == 0)
+ cmd_pll_data.pll = DDR3B_PLL;
+ else
+ goto pll_cmd_usage;
+
+ cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10);
+ cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10);
+ cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10);
+
+ printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
+ cmd_pll_data.pll, cmd_pll_data.pll_m,
+ cmd_pll_data.pll_d, cmd_pll_data.pll_od);
+ init_pll(&cmd_pll_data);
+
+ return 0;
+
+pll_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ "set pll multiplier and pre divider",
+ "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
+);
+
+int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int clk;
+ unsigned int freq;
+
+ if (argc != 2)
+ goto getclk_cmd_usage;
+
+ clk = simple_strtoul(argv[1], NULL, 10);
+
+ freq = clk_get_rate(clk);
+ printf("clock index [%d] - frequency %u\n", clk, freq);
+ return 0;
+
+getclk_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ getclk, 2, 0, do_getclk_cmd,
+ "get clock rate",
+ "<clk index>\n"
+ "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+);
+
+int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int psc_module;
+ int res;
+
+ if (argc != 3)
+ goto psc_cmd_usage;
+
+ psc_module = simple_strtoul(argv[1], NULL, 10);
+ if (strcmp(argv[2], "en") == 0) {
+ res = psc_enable_module(psc_module);
+ printf("psc_enable_module(%d) - %s\n", psc_module,
+ (res) ? "ERROR" : "OK");
+ return 0;
+ }
+
+ if (strcmp(argv[2], "di") == 0) {
+ res = psc_disable_module(psc_module);
+ printf("psc_disable_module(%d) - %s\n", psc_module,
+ (res) ? "ERROR" : "OK");
+ return 0;
+ }
+
+ if (strcmp(argv[2], "domain") == 0) {
+ res = psc_disable_domain(psc_module);
+ printf("psc_disable_domain(%d) - %s\n", psc_module,
+ (res) ? "ERROR" : "OK");
+ return 0;
+ }
+
+psc_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ psc, 3, 0, do_psc_cmd,
+ "<enable/disable psc module os disable domain>",
+ "<mod/domain index> <en|di|domain>\n"
+ "See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
+);
--- /dev/null
+/*
+ * K2HK: secure kernel command file
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+asm(".arch_extension sec\n\t");
+
+static int mon_install(u32 addr, u32 dpsc, u32 freq)
+{
+ int result;
+
+ __asm__ __volatile__ (
+ "stmfd r13!, {lr}\n"
+ "mov r0, %1\n"
+ "mov r1, %2\n"
+ "mov r2, %3\n"
+ "blx r0\n"
+ "ldmfd r13!, {lr}\n"
+ : "=&r" (result)
+ : "r" (addr), "r" (dpsc), "r" (freq)
+ : "cc", "r0", "r1", "r2", "memory");
+ return result;
+}
+
+static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 addr, dpsc_base = 0x1E80000, freq;
+ int rcode = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ freq = clk_get_rate(sys_clk0_6_clk);
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ rcode = mon_install(addr, dpsc_base, freq);
+ printf("## installed monitor, freq [%d], status %d\n",
+ freq, rcode);
+
+ return 0;
+}
+
+U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
+ "Install boot kernel at 'addr'",
+ ""
+);
+
+static void core_spin(void)
+{
+ while (1)
+ ; /* forever */;
+}
+
+int mon_power_on(int core_id, void *ep)
+{
+ int result;
+
+ asm volatile (
+ "stmfd r13!, {lr}\n"
+ "mov r1, %1\n"
+ "mov r2, %2\n"
+ "mov r0, #0\n"
+ "smc #0\n"
+ "ldmfd r13!, {lr}\n"
+ : "=&r" (result)
+ : "r" (core_id), "r" (ep)
+ : "cc", "r0", "r1", "r2", "memory");
+ return result;
+}
+
+int mon_power_off(int core_id)
+{
+ int result;
+
+ asm volatile (
+ "stmfd r13!, {lr}\n"
+ "mov r1, %1\n"
+ "mov r0, #1\n"
+ "smc #1\n"
+ "ldmfd r13!, {lr}\n"
+ : "=&r" (result)
+ : "r" (core_id)
+ : "cc", "r0", "r1", "memory");
+ return result;
+}
+
+int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int rcode = 0, core_id, on;
+ void (*fn)(void);
+
+ fn = core_spin;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ core_id = simple_strtoul(argv[1], NULL, 16);
+ on = simple_strtoul(argv[2], NULL, 16);
+
+ if (on)
+ rcode = mon_power_on(core_id, fn);
+ else
+ rcode = mon_power_off(core_id);
+
+ if (on) {
+ if (!rcode)
+ printf("core %d powered on successfully\n", core_id);
+ else
+ printf("core %d power on failure\n", core_id);
+ } else {
+ printf("core %d powered off successfully\n", core_id);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(mon_power, 3, 0, do_mon_power,
+ "Power On/Off secondary core",
+ "mon_power <coreid> <oper>\n"
+ "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n"
+ ""
+);
--- /dev/null
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+{
+ unsigned int tmp;
+
+ while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
+ & 0x00000001) != 0x00000001)
+ ;
+
+ __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
+
+ tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
+ tmp &= ~(phy_cfg->pgcr1_mask);
+ tmp |= phy_cfg->pgcr1_val;
+ __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
+
+ __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
+ __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
+ __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
+ __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
+
+ tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
+ tmp &= ~(phy_cfg->dcr_mask);
+ tmp |= phy_cfg->dcr_val;
+ __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
+
+ __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
+ __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
+ __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
+ __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
+ __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
+ __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
+ __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
+ __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
+
+ __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
+ __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
+ __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
+
+ __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
+ while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
+ ;
+
+ __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
+ while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
+ ;
+}
+
+void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+{
+ __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
+ __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
+ __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
+ __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
+ __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
+ __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
+ __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
+}
--- /dev/null
+/*
+ * Keystone2: Architecture initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+
+void chip_configuration_unlock(void)
+{
+ __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
+ __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+ chip_configuration_unlock();
+ icache_enable();
+
+#ifdef CONFIG_SOC_K2HK
+ share_all_segments(8);
+ share_all_segments(9);
+ share_all_segments(10); /* QM PDSP */
+ share_all_segments(11); /* PCIE */
+#endif
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
+ u32 tmp;
+
+ tmp = *rstctrl & KS2_RSTCTRL_MASK;
+ *rstctrl = tmp | KS2_RSTCTRL_KEY;
+
+ *rstctrl &= KS2_RSTCTRL_SWRST;
+
+ for (;;)
+ ;
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+#endif
+}
--- /dev/null
+/*
+ * Multicore Navigator driver for TI Keystone 2 devices.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/keystone_nav.h>
+
+static int soc_type =
+#ifdef CONFIG_SOC_K2HK
+ k2hk;
+#endif
+
+struct qm_config k2hk_qm_memmap = {
+ .stat_cfg = 0x02a40000,
+ .queue = (struct qm_reg_queue *)0x02a80000,
+ .mngr_vbusm = 0x23a80000,
+ .i_lram = 0x00100000,
+ .proxy = (struct qm_reg_queue *)0x02ac0000,
+ .status_ram = 0x02a06000,
+ .mngr_cfg = (struct qm_cfg_reg *)0x02a02000,
+ .intd_cfg = 0x02a0c000,
+ .desc_mem = (struct descr_mem_setup_reg *)0x02a03000,
+ .region_num = 64,
+ .pdsp_cmd = 0x02a20000,
+ .pdsp_ctl = 0x02a0f000,
+ .pdsp_iram = 0x02a10000,
+ .qpool_num = 4000,
+};
+
+/*
+ * We are going to use only one type of descriptors - host packet
+ * descriptors. We staticaly allocate memory for them here
+ */
+struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
+
+static struct qm_config *qm_cfg;
+
+inline int num_of_desc_to_reg(int num_descr)
+{
+ int j, num;
+
+ for (j = 0, num = 32; j < 15; j++, num *= 2) {
+ if (num_descr <= num)
+ return j;
+ }
+
+ return 15;
+}
+
+static int _qm_init(struct qm_config *cfg)
+{
+ u32 j;
+
+ if (cfg == NULL)
+ return QM_ERR;
+
+ qm_cfg = cfg;
+
+ qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
+ qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8;
+ qm_cfg->mngr_cfg->link_ram_base1 = 0;
+ qm_cfg->mngr_cfg->link_ram_size1 = 0;
+ qm_cfg->mngr_cfg->link_ram_base2 = 0;
+
+ qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
+ qm_cfg->desc_mem[0].start_idx = 0;
+ qm_cfg->desc_mem[0].desc_reg_size =
+ (((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
+ num_of_desc_to_reg(HDESC_NUM);
+
+ memset(desc_pool, 0, sizeof(desc_pool));
+ for (j = 0; j < HDESC_NUM; j++)
+ qm_push(&desc_pool[j], qm_cfg->qpool_num);
+
+ return QM_OK;
+}
+
+int qm_init(void)
+{
+ switch (soc_type) {
+ case k2hk:
+ return _qm_init(&k2hk_qm_memmap);
+ }
+
+ return QM_ERR;
+}
+
+void qm_close(void)
+{
+ u32 j;
+
+ if (qm_cfg == NULL)
+ return;
+
+ queue_close(qm_cfg->qpool_num);
+
+ qm_cfg->mngr_cfg->link_ram_base0 = 0;
+ qm_cfg->mngr_cfg->link_ram_size0 = 0;
+ qm_cfg->mngr_cfg->link_ram_base1 = 0;
+ qm_cfg->mngr_cfg->link_ram_size1 = 0;
+ qm_cfg->mngr_cfg->link_ram_base2 = 0;
+
+ for (j = 0; j < qm_cfg->region_num; j++) {
+ qm_cfg->desc_mem[j].base_addr = 0;
+ qm_cfg->desc_mem[j].start_idx = 0;
+ qm_cfg->desc_mem[j].desc_reg_size = 0;
+ }
+
+ qm_cfg = NULL;
+}
+
+void qm_push(struct qm_host_desc *hd, u32 qnum)
+{
+ u32 regd;
+
+ if (!qm_cfg)
+ return;
+
+ cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
+ regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
+ writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
+}
+
+void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+ void *buff_ptr, u32 buff_len)
+{
+ hd->orig_buff_len = buff_len;
+ hd->buff_len = buff_len;
+ hd->orig_buff_ptr = (u32)buff_ptr;
+ hd->buff_ptr = (u32)buff_ptr;
+ qm_push(hd, qnum);
+}
+
+struct qm_host_desc *qm_pop(u32 qnum)
+{
+ u32 uhd;
+
+ if (!qm_cfg)
+ return NULL;
+
+ uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
+ if (uhd)
+ cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
+
+ return (struct qm_host_desc *)uhd;
+}
+
+struct qm_host_desc *qm_pop_from_free_pool(void)
+{
+ if (!qm_cfg)
+ return NULL;
+
+ return qm_pop(qm_cfg->qpool_num);
+}
+
+void queue_close(u32 qnum)
+{
+ struct qm_host_desc *hd;
+
+ while ((hd = qm_pop(qnum)))
+ ;
+}
+
+/*
+ * DMA API
+ */
+
+struct pktdma_cfg k2hk_netcp_pktdma = {
+ .global = (struct global_ctl_regs *)0x02004000,
+ .tx_ch = (struct tx_chan_regs *)0x02004400,
+ .tx_ch_num = 9,
+ .rx_ch = (struct rx_chan_regs *)0x02004800,
+ .rx_ch_num = 26,
+ .tx_sched = (u32 *)0x02004c00,
+ .rx_flows = (struct rx_flow_regs *)0x02005000,
+ .rx_flow_num = 32,
+ .rx_free_q = 4001,
+ .rx_rcv_q = 4002,
+ .tx_snd_q = 648,
+};
+
+struct pktdma_cfg *netcp;
+
+static int netcp_rx_disable(void)
+{
+ u32 j, v, k;
+
+ for (j = 0; j < netcp->rx_ch_num; j++) {
+ v = readl(&netcp->rx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+
+ writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
+ for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
+ udelay(100);
+ v = readl(&netcp->rx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+ }
+ /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
+ }
+
+ /* Clear all of the flow registers */
+ for (j = 0; j < netcp->rx_flow_num; j++) {
+ writel(0, &netcp->rx_flows[j].control);
+ writel(0, &netcp->rx_flows[j].tags);
+ writel(0, &netcp->rx_flows[j].tag_sel);
+ writel(0, &netcp->rx_flows[j].fdq_sel[0]);
+ writel(0, &netcp->rx_flows[j].fdq_sel[1]);
+ writel(0, &netcp->rx_flows[j].thresh[0]);
+ writel(0, &netcp->rx_flows[j].thresh[1]);
+ writel(0, &netcp->rx_flows[j].thresh[2]);
+ }
+
+ return QM_OK;
+}
+
+static int netcp_tx_disable(void)
+{
+ u32 j, v, k;
+
+ for (j = 0; j < netcp->tx_ch_num; j++) {
+ v = readl(&netcp->tx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+
+ writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
+ for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
+ udelay(100);
+ v = readl(&netcp->tx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+ }
+ /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
+ }
+
+ return QM_OK;
+}
+
+static int _netcp_init(struct pktdma_cfg *netcp_cfg,
+ struct rx_buff_desc *rx_buffers)
+{
+ u32 j, v;
+ struct qm_host_desc *hd;
+ u8 *rx_ptr;
+
+ if (netcp_cfg == NULL || rx_buffers == NULL ||
+ rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
+ return QM_ERR;
+
+ netcp = netcp_cfg;
+ netcp->rx_flow = rx_buffers->rx_flow;
+
+ /* init rx queue */
+ rx_ptr = rx_buffers->buff_ptr;
+
+ for (j = 0; j < rx_buffers->num_buffs; j++) {
+ hd = qm_pop(qm_cfg->qpool_num);
+ if (hd == NULL)
+ return QM_ERR;
+
+ qm_buff_push(hd, netcp->rx_free_q,
+ rx_ptr, rx_buffers->buff_len);
+
+ rx_ptr += rx_buffers->buff_len;
+ }
+
+ netcp_rx_disable();
+
+ /* configure rx channels */
+ v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
+ writel(v, &netcp->rx_flows[netcp->rx_flow].control);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
+
+ v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
+ netcp->rx_free_q);
+
+ writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
+ writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
+
+ for (j = 0; j < netcp->rx_ch_num; j++)
+ writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
+
+ /* configure tx channels */
+ /* Disable loopback in the tx direction */
+ writel(0, &netcp->global->emulation_control);
+
+/* TODO: make it dependend on a soc type variable */
+#ifdef CONFIG_SOC_K2HK
+ /* Set QM base address, only for K2x devices */
+ writel(0x23a80000, &netcp->global->qm_base_addr[0]);
+#endif
+
+ /* Enable all channels. The current state isn't important */
+ for (j = 0; j < netcp->tx_ch_num; j++) {
+ writel(0, &netcp->tx_ch[j].cfg_b);
+ writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
+ }
+
+ return QM_OK;
+}
+
+int netcp_init(struct rx_buff_desc *rx_buffers)
+{
+ switch (soc_type) {
+ case k2hk:
+ _netcp_init(&k2hk_netcp_pktdma, rx_buffers);
+ return QM_OK;
+ }
+ return QM_ERR;
+}
+
+int netcp_close(void)
+{
+ if (!netcp)
+ return QM_ERR;
+
+ netcp_tx_disable();
+ netcp_rx_disable();
+
+ queue_close(netcp->rx_free_q);
+ queue_close(netcp->rx_rcv_q);
+ queue_close(netcp->tx_snd_q);
+
+ return QM_OK;
+}
+
+int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
+{
+ struct qm_host_desc *hd;
+
+ hd = qm_pop(qm_cfg->qpool_num);
+ if (hd == NULL)
+ return QM_ERR;
+
+ hd->desc_info = num_bytes;
+ hd->swinfo[2] = swinfo2;
+ hd->packet_info = qm_cfg->qpool_num;
+
+ qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
+
+ return QM_OK;
+}
+
+void *netcp_recv(u32 **pkt, int *num_bytes)
+{
+ struct qm_host_desc *hd;
+
+ hd = qm_pop(netcp->rx_rcv_q);
+ if (!hd)
+ return NULL;
+
+ *pkt = (u32 *)hd->buff_ptr;
+ *num_bytes = hd->desc_info & 0x3fffff;
+
+ return hd;
+}
+
+void netcp_release_rxhd(void *hd)
+{
+ struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
+
+ _hd->buff_len = _hd->orig_buff_len;
+ _hd->buff_ptr = _hd->orig_buff_ptr;
+
+ qm_push(_hd, netcp->rx_free_q);
+}
--- /dev/null
+/*
+ * MSMC controller utilities
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+struct mpax {
+ u32 mpaxl;
+ u32 mpaxh;
+};
+
+struct msms_regs {
+ u32 pid;
+ u32 _res_04;
+ u32 smcerrar;
+ u32 smcerrxr;
+ u32 smedcc;
+ u32 smcea;
+ u32 smsecc;
+ u32 smpfar;
+ u32 smpfxr;
+ u32 smpfr;
+ u32 smpfcr;
+ u32 _res_2c;
+ u32 sbndc[8];
+ u32 sbndm;
+ u32 sbnde;
+ u32 _res_58;
+ u32 cfglck;
+ u32 cfgulck;
+ u32 cfglckstat;
+ u32 sms_mpax_lck;
+ u32 sms_mpax_ulck;
+ u32 sms_mpax_lckstat;
+ u32 ses_mpax_lck;
+ u32 ses_mpax_ulck;
+ u32 ses_mpax_lckstat;
+ u32 smestat;
+ u32 smirstat;
+ u32 smirc;
+ u32 smiestat;
+ u32 smiec;
+ u32 _res_94_c0[12];
+ u32 smncerrar;
+ u32 smncerrxr;
+ u32 smncea;
+ u32 _res_d0_1fc[76];
+ struct mpax sms[16][8];
+ struct mpax ses[16][8];
+};
+
+
+void share_all_segments(int priv_id)
+{
+ struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+ int j;
+
+ for (j = 0; j < 8; j++) {
+ msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful;
+ msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
+ }
+}
--- /dev/null
+/*
+ * Keystone: PSC configuration module
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/psc_defs.h>
+
+#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
+#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
+
+#ifdef CONFIG_SOC_K2HK
+#define DEVICE_PSC_BASE K2HK_PSC_BASE
+#endif
+
+int psc_delay(void)
+{
+ udelay(10);
+ return 10;
+}
+
+/*
+ * FUNCTION PURPOSE: Wait for end of transitional state
+ *
+ * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
+ * to be complete.
+ *
+ * Since this is boot loader code it is *ASSUMED* that interrupts
+ * are disabled and no other core is mucking around with the psc
+ * at the same time.
+ *
+ * Returns 0 when the domain is free. Returns -1 if a timeout
+ * occurred waiting for the completion.
+ */
+int psc_wait(u32 domain_num)
+{
+ u32 retry;
+ u32 ptstat;
+
+ /*
+ * Do nothing if the power domain is in transition. This should never
+ * happen since the boot code is the only software accesses psc.
+ * It's still remotely possible that the hardware state machines
+ * initiate transitions.
+ * Don't trap if the domain (or a module in this domain) is
+ * stuck in transition.
+ */
+ retry = 0;
+
+ do {
+ ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+ ptstat = ptstat & (1 << domain_num);
+ } while ((ptstat != 0) && ((retry += psc_delay()) <
+ PSC_PTSTAT_TIMEOUT_LIMIT));
+
+ if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
+ return -1;
+
+ return 0;
+}
+
+u32 psc_get_domain_num(u32 mod_num)
+{
+ u32 domain_num;
+
+ /* Get the power domain associated with the module number */
+ domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ PSC_REG_MDCFG(mod_num));
+ domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
+
+ return domain_num;
+}
+
+/*
+ * FUNCTION PURPOSE: Power up/down a module
+ *
+ * DESCRIPTION: Powers up/down the requested module and the associated power
+ * domain if required. No action is taken it the module is
+ * already powered up/down.
+ *
+ * This only controls modules. The domain in which the module
+ * resides will be left in the power on state. Multiple modules
+ * can exist in a power domain, so powering down the domain based
+ * on a single module is not done.
+ *
+ * Returns 0 on success, -1 if the module can't be powered up, or
+ * if there is a timeout waiting for the transition.
+ */
+int psc_set_state(u32 mod_num, u32 state)
+{
+ u32 domain_num;
+ u32 pdctl;
+ u32 mdctl;
+ u32 ptcmd;
+ u32 reset_iso;
+ u32 v;
+
+ /*
+ * Get the power domain associated with the module number, and reset
+ * isolation functionality
+ */
+ v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ domain_num = PSC_REG_MDCFG_GET_PD(v);
+ reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
+
+ /* Wait for the status of the domain/module to be non-transitional */
+ if (psc_wait(domain_num) != 0)
+ return -1;
+
+ /*
+ * Perform configuration even if the current status matches the
+ * existing state
+ *
+ * Set the next state of the power domain to on. It's OK if the domain
+ * is always on. This code will not ever power down a domain, so no
+ * change is made if the new state is power down.
+ */
+ if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
+ pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ PSC_REG_PDCTL(domain_num));
+ pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
+ PSC_REG_VAL_PDCTL_NEXT_ON);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+ pdctl);
+ }
+
+ /* Set the next state for the module to enabled/disabled */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
+ mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+ /* Trigger the enable */
+ ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd |= (u32)(1<<domain_num);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+
+ /* Wait on the complete */
+ return psc_wait(domain_num);
+}
+
+/*
+ * FUNCTION PURPOSE: Power up a module
+ *
+ * DESCRIPTION: Powers up the requested module and the associated power domain
+ * if required. No action is taken it the module is already
+ * powered up.
+ *
+ * Returns 0 on success, -1 if the module can't be powered up, or
+ * if there is a timeout waiting for the transition.
+ */
+int psc_enable_module(u32 mod_num)
+{
+ u32 mdctl;
+
+ /* Set the bit to apply reset */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
+ return 0;
+
+ return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
+}
+
+/*
+ * FUNCTION PURPOSE: Power down a module
+ *
+ * DESCRIPTION: Powers down the requested module.
+ *
+ * Returns 0 on success, -1 on failure or timeout.
+ */
+int psc_disable_module(u32 mod_num)
+{
+ u32 mdctl;
+
+ /* Set the bit to apply reset */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ if ((mdctl & 0x3f) == 0)
+ return 0;
+ mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+ return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
+}
+
+/*
+ * FUNCTION PURPOSE: Set the reset isolation bit in mdctl
+ *
+ * DESCRIPTION: The reset isolation enable bit is set. The state of the module
+ * is not changed. Returns 0 if the module config showed that
+ * reset isolation is supported. Returns 1 otherwise. This is not
+ * an error, but setting the bit in mdctl has no effect.
+ */
+int psc_set_reset_iso(u32 mod_num)
+{
+ u32 v;
+ u32 mdctl;
+
+ /* Set the reset isolation bit */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+ v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * FUNCTION PURPOSE: Disable a power domain
+ *
+ * DESCRIPTION: The power domain is disabled
+ */
+int psc_disable_domain(u32 domain_num)
+{
+ u32 pdctl;
+ u32 ptcmd;
+
+ pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+ pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
+ pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+
+ ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd |= (u32)(1 << domain_num);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+
+ return psc_wait(domain_num);
+}
--- /dev/null
+/*
+ * common spl init code
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <spl.h>
+#include <spi_flash.h>
+
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts("Unknown boot device\n");
+ hang();
+#endif
+}
*((u32 *)(dev_data + BOOT_MODE_OFFSET));
}
}
+
+#ifdef CONFIG_DRA7XX
+ /*
+ * We get different values for QSPI_1 and QSPI_4 being used, but
+ * don't actually care about this difference. Rather than
+ * mangle the later code, if we're coming in as QSPI_4 just
+ * change to the QSPI_1 value.
+ */
+ if (gd->arch.omap_boot_params.omap_bootdevice == 11)
+ gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI;
+#endif
}
#ifdef CONFIG_SPL_BUILD
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <asm/arch/sys_proto.h>
static void do_cancel_out(u32 *num, u32 *den, u32 factor)
{
while (1) {
*den = (*den + 1) / 2;
}
}
+
+void __weak usb_fake_mac_from_die_id(u32 *id)
+{
+ uint8_t device_mac[6];
+
+ if (!getenv("usbethaddr")) {
+ /*
+ * create a fake MAC address from the processor ID code.
+ * first byte is 0x02 to signify locally administered.
+ */
+ device_mac[0] = 0x02;
+ device_mac[1] = id[3] & 0xff;
+ device_mac[2] = id[2] & 0xff;
+ device_mac[3] = id[1] & 0xff;
+ device_mac[4] = id[0] & 0xff;
+ device_mac[5] = (id[0] >> 8) & 0xff;
+
+ eth_setenv_enetaddr("usbethaddr", device_mac);
+ }
+}
* should not be running and does not generate a PRCM reset.
*/
- sr32(&prcm_base->fclken_wkup, 5, 1, 1);
- sr32(&prcm_base->iclken_wkup, 5, 1, 1);
+ setbits_le32(&prcm_base->fclken_wkup, 0x20);
+ setbits_le32(&prcm_base->iclken_wkup, 0x20);
wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
writel(WD_UNLOCK1, &wd2_base->wspr);
if (xip_safe) {
/*
* CORE DPLL
- * sr32(CM_CLKSEL2_EMU) set override to work when asleep
*/
- sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
*/
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
- sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
- sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x001F0000, (CORE_M3X2 + 1) << 16) ;
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+ clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
- sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000003, CORE_L3_DIV);
/* GFX */
- sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
+ clrsetbits_le32(&prcm_base->clksel_gfx,
+ 0x00000007, GFX_DIV);
/* RESET MGR */
- sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+ clrsetbits_le32(&prcm_base->clksel_wkup,
+ 0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
- sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
- sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&p0, 4, 4, ptr->fsel);
+ clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&p1, 27, 5, ptr->m2);
+ clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&p1, 16, 11, ptr->m);
+ clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&p1, 8, 7, ptr->n);
+ clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&p1, 6, 1, 0);
+ clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
- sr32(&p2, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&p2, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&p2, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&p2, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
ptr = ptr + clk_index;
/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/*
* and then the actual divisor value
*/
/* M6 */
- sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
- sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x1F000000, (PER_M6X2 + 1) << 24);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x1F000000, PER_M6X2 << 24);
/* M5 */
- sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
- sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
+ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
+ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
/* M4 */
- sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
- sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
/* M3 */
- sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
- sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
+ clrsetbits_le32(&prcm_base->clksel_dss,
+ 0x00001F00, (PER_M3X2 + 1) << 8);
+ clrsetbits_le32(&prcm_base->clksel_dss,
+ 0x00001F00, PER_M3X2 << 8);
/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
- sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
+ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
/* Workaround end */
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
- sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel2_pll,
+ 0x0007FF00, ptr->m << 8);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
/* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
- sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}
ptr = ptr + clk_index;
/* PER2 DPLL (DPLL5) */
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
- sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
- sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
- sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
+ /* set M2 (usbtll_fck) */
+ clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
+ /* set m (11-bit multiplier) */
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
+ /* set n (7-bit divider)*/
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
+ /* FREQSEL */
+ clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
+ /* lock mode */
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
}
/* MPU DPLL (unlocked already) */
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
+ 0x0000001F, ptr->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
+ 0x0007FF00, ptr->m << 8);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
+ 0x0000007F, ptr->n);
/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
- sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x000000F0, ptr->fsel << 4);
}
static void iva_init_34xx(u32 sil_index, u32 clk_index)
/* IVA DPLL */
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x00000007, PLL_STOP);
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
+ 0x0000001F, ptr->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+ 0x0007FF00, ptr->m << 8);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+ 0x0000007F, ptr->n);
/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
- sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x000000F0, ptr->fsel << 4);
/* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
}
/* CORE DPLL */
/* Select relock bypass: CM_CLKEN_PLL[0:2] */
- sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
- sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+ clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
- sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000003, CORE_L3_DIV);
/* GFX */
- sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
+ clrsetbits_le32(&prcm_base->clksel_gfx,
+ 0x00000007, GFX_DIV_36X);
/* RESET MGR */
- sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+ clrsetbits_le32(&prcm_base->clksel_wkup,
+ 0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
- sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
- sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&p0, 4, 4, ptr->fsel);
+ clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&p1, 27, 5, ptr->m2);
+ clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&p1, 16, 11, ptr->m);
+ clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&p1, 8, 7, ptr->n);
+ clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&p1, 6, 1, 0);
+ clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
- sr32(&p2, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&p2, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&p2, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&p2, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
ptr += clk_index;
/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
- sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
+ clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
- sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
+ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
- sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
- sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
- sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
- sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
+ clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}
ptr = ptr + clk_index;
/* PER2 DPLL (DPLL5) */
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
- sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
- sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
+ /* set M2 (usbtll_fck) */
+ clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
+ /* set m (11-bit multiplier) */
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
+ /* set n (7-bit divider)*/
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
+ /* lock mode */
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
}
/* MPU DPLL (unlocked already */
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
}
static void iva_init_36xx(u32 sil_index, u32 clk_index)
/* IVA DPLL */
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
}
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
/* set input crystal speed */
- sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
+ clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
/* If the input clock is greater than 19.2M always divide/2 */
if (sys_clkin_sel > 2) {
/* input clock divider */
- sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
+ clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
clk_index = sys_clkin_sel / 2;
} else {
/* input clock divider */
- sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
+ clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
clk_index = sys_clkin_sel;
}
* input divider to /1 as it should never set to /6.5
* in this case.
*/
- if (sys_clkin_sel != 1) /* 13 MHz */
+ if (sys_clkin_sel != 1) { /* 13 MHz */
/* Bit 8: DPLL4_CLKINP_DIV */
- sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
+ clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
+ }
/* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
mpu_init_36xx(0, clk_index);
/* Lock MPU DPLL to set frequency */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
} else {
sil_index = 1;
/* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
}
/* Set up GPTimers to sys_clk source only */
- sr32(&prcm_base->clksel_per, 0, 8, 0xff);
- sr32(&prcm_base->clksel_wkup, 0, 1, 1);
+ setbits_le32(&prcm_base->clksel_per, 0x000000FF);
+ setbits_le32(&prcm_base->clksel_wkup, 1);
sdelay(5000);
}
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
+ setbits_le32(&prcm_base->iclken_usbhost, 1);
/*
* Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
* and USBHOST_120M_FCLK (USBHOST_FCLK2)
*/
- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
+ setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
/* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
+ setbits_le32(&prcm_base->iclken3_core, 0x00000004);
/* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
+ setbits_le32(&prcm_base->fclken3_core, 0x00000004);
}
/******************************************************************************
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable GP2 timer. */
- sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
- sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
- sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
+ setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
+ setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
+ setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
- sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
- sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
+ setbits_le32(&prcm_base->fclken1_core, 0x00002000);
+ setbits_le32(&prcm_base->iclken1_core, 0x00002000);
/* UART 3 Clocks */
- sr32(&prcm_base->fclken_per, 11, 1, 0x1);
- sr32(&prcm_base->iclken_per, 11, 1, 0x1);
+ setbits_le32(&prcm_base->fclken_per, 0x00000800);
+ setbits_le32(&prcm_base->iclken_per, 0x00000800);
#endif
#ifdef CONFIG_OMAP3_GPIO_2
- sr32(&prcm_base->fclken_per, 13, 1, 1);
- sr32(&prcm_base->iclken_per, 13, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00002000);
+ setbits_le32(&prcm_base->iclken_per, 0x00002000);
#endif
#ifdef CONFIG_OMAP3_GPIO_3
- sr32(&prcm_base->fclken_per, 14, 1, 1);
- sr32(&prcm_base->iclken_per, 14, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00004000);
+ setbits_le32(&prcm_base->iclken_per, 0x00004000);
#endif
#ifdef CONFIG_OMAP3_GPIO_4
- sr32(&prcm_base->fclken_per, 15, 1, 1);
- sr32(&prcm_base->iclken_per, 15, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00008000);
+ setbits_le32(&prcm_base->iclken_per, 0x00008000);
#endif
#ifdef CONFIG_OMAP3_GPIO_5
- sr32(&prcm_base->fclken_per, 16, 1, 1);
- sr32(&prcm_base->iclken_per, 16, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00010000);
+ setbits_le32(&prcm_base->iclken_per, 0x00010000);
#endif
#ifdef CONFIG_OMAP3_GPIO_6
- sr32(&prcm_base->fclken_per, 17, 1, 1);
- sr32(&prcm_base->iclken_per, 17, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00020000);
+ setbits_le32(&prcm_base->iclken_per, 0x00020000);
#endif
#ifdef CONFIG_SYS_I2C_OMAP34XX
/* Turn on all 3 I2C clocks */
- sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
- sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
+ setbits_le32(&prcm_base->fclken1_core, 0x00038000);
+ setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
#endif
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
- sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
+ setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
if (get_cpu_family() != CPU_AM35XX)
- sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
-
- sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
- sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
- sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
- sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
- sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
- sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
- sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
+ out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
+
+ out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
+ out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
+ out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
+ out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
+ out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
+ out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+ out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
if (get_cpu_family() != CPU_AM35XX) {
- sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
- sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+ out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
+ out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
}
sdelay(1000);
"1.2"};
#endif /* CONFIG_DISPLAY_CPUINFO */
+/*****************************************************************
+ * get_dieid(u32 *id) - read die ID
+ *****************************************************************/
+void get_dieid(u32 *id)
+{
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+
+ id[3] = readl(&id_base->die_id_0);
+ id[2] = readl(&id_base->die_id_1);
+ id[1] = readl(&id_base->die_id_2);
+ id[0] = readl(&id_base->die_id_3);
+}
+
/*****************************************************************
* dieid_num_r(void) - read and set die ID
*****************************************************************/
void dieid_num_r(void)
{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
char *uid_s, die_id[34];
u32 id[4];
uid_s = getenv("dieid#");
if (uid_s == NULL) {
- id[3] = readl(&id_base->die_id_0);
- id[2] = readl(&id_base->die_id_1);
- id[1] = readl(&id_base->die_id_2);
- id[0] = readl(&id_base->die_id_3);
+ get_dieid(id);
sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
setenv("dieid#", die_id);
uid_s = die_id;
"bne 1b":"=r" (loops):"0"(loops));
}
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = readl((u32)addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- writel(tmp, (u32)addr);
-}
-
/*********************************************************************
* wait_on_value() - common routine to allow waiting for changes in
* volatile regs.
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += ap.o
+obj-y += board.o
+obj-y += cache.o
+obj-y += clock.o
obj-y += lowlevel_init.o
-obj-y += ap.o board.o clock.o cache.o
+obj-y += pinmux-common.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
--- /dev/null
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+ (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
+
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) \
+ (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
+
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+ (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) \
+ (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
+
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) \
+ (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) \
+ (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
+
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+ (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
+ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+ (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
+ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
+
+#if defined(CONFIG_TEGRA20)
+
+#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
+#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
+
+#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
+#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
+
+#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
+#define TRI_SHIFT(grp) ((grp) % 32)
+
+#else
+
+#define REG(pin) _R(0x3000 + ((pin) * 4))
+
+#define MUX_REG(pin) REG(pin)
+#define MUX_SHIFT(pin) 0
+
+#define PULL_REG(pin) REG(pin)
+#define PULL_SHIFT(pin) 2
+
+#define TRI_REG(pin) REG(pin)
+#define TRI_SHIFT(pin) 4
+
+#endif /* CONFIG_TEGRA20 */
+
+#define DRV_REG(group) _R(0x868 + ((group) * 4))
+
+#define IO_SHIFT 5
+#define OD_SHIFT 6
+#define LOCK_SHIFT 7
+#define IO_RESET_SHIFT 8
+#define RCV_SEL_SHIFT 9
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+ u32 *reg = MUX_REG(pin);
+ int i, mux = -1;
+ u32 val;
+
+ /* Error check on pin and func */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_func_isvalid(func));
+
+ if (func >= PMUX_FUNC_RSVD1) {
+ mux = (func - PMUX_FUNC_RSVD1) & 3;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 4; i++) {
+ if (tegra_soc_pingroups[pin].funcs[i] == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ val = readl(reg);
+ val &= ~(3 << MUX_SHIFT(pin));
+ val |= (mux << MUX_SHIFT(pin));
+ writel(val, reg);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+ u32 *reg = PULL_REG(pin);
+ u32 val;
+
+ /* Error check on pin and pupd */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_pupd_isvalid(pupd));
+
+ val = readl(reg);
+ val &= ~(3 << PULL_SHIFT(pin));
+ val |= (pupd << PULL_SHIFT(pin));
+ writel(val, reg);
+}
+
+static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
+{
+ u32 *reg = TRI_REG(pin);
+ u32 val;
+
+ /* Error check on pin */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_tristate_isvalid(tri));
+
+ val = readl(reg);
+ if (tri == PMUX_TRI_TRISTATE)
+ val |= (1 << TRI_SHIFT(pin));
+ else
+ val &= ~(1 << TRI_SHIFT(pin));
+ writel(val, reg);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
+}
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (io == PMUX_PIN_NONE)
+ return;
+
+ /* Error check on pin and io */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_io_isvalid(io));
+
+ val = readl(reg);
+ if (io == PMUX_PIN_INPUT)
+ val |= (io & 1) << IO_SHIFT;
+ else
+ val &= ~(1 << IO_SHIFT);
+ writel(val, reg);
+}
+
+static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (lock == PMUX_PIN_LOCK_DEFAULT)
+ return;
+
+ /* Error check on pin and lock */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_lock_isvalid(lock));
+
+ val = readl(reg);
+ if (lock == PMUX_PIN_LOCK_ENABLE) {
+ val |= (1 << LOCK_SHIFT);
+ } else {
+ if (val & (1 << LOCK_SHIFT))
+ printf("%s: Cannot clear LOCK bit!\n", __func__);
+ val &= ~(1 << LOCK_SHIFT);
+ }
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (od == PMUX_PIN_OD_DEFAULT)
+ return;
+
+ /* Error check on pin and od */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_od_isvalid(od));
+
+ val = readl(reg);
+ if (od == PMUX_PIN_OD_ENABLE)
+ val |= (1 << OD_SHIFT);
+ else
+ val &= ~(1 << OD_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_ioreset(enum pmux_pingrp pin,
+ enum pmux_pin_ioreset ioreset)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+ return;
+
+ /* Error check on pin and ioreset */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_ioreset_isvalid(ioreset));
+
+ val = readl(reg);
+ if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+ val |= (1 << IO_RESET_SHIFT);
+ else
+ val &= ~(1 << IO_RESET_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
+ enum pmux_pin_rcv_sel rcv_sel)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+ return;
+
+ /* Error check on pin and rcv_sel */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+ val = readl(reg);
+ if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+ val |= (1 << RCV_SEL_SHIFT);
+ else
+ val &= ~(1 << RCV_SEL_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
+{
+ enum pmux_pingrp pin = config->pingrp;
+
+ pinmux_set_func(pin, config->func);
+ pinmux_set_pullupdown(pin, config->pull);
+ pinmux_set_tristate(pin, config->tristate);
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+ pinmux_set_io(pin, config->io);
+ pinmux_set_lock(pin, config->lock);
+ pinmux_set_od(pin, config->od);
+ pinmux_set_ioreset(pin, config->ioreset);
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+ pinmux_set_rcv_sel(pin, config->rcv_sel);
+#endif
+#endif
+}
+
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+ int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_pingrp(&config[i]);
+}
+
+#ifdef TEGRA_PMX_HAS_DRVGRPS
+
+#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
+
+#define pmux_slw_isvalid(slw) \
+ (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
+
+#define pmux_drv_isvalid(drv) \
+ (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
+
+#define pmux_lpmd_isvalid(lpm) \
+ (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
+
+#define pmux_schmt_isvalid(schmt) \
+ (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
+
+#define pmux_hsm_isvalid(hsm) \
+ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
+
+#define HSM_SHIFT 2
+#define SCHMT_SHIFT 3
+#define LPMD_SHIFT 4
+#define LPMD_MASK (3 << LPMD_SHIFT)
+#define DRVDN_SHIFT 12
+#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
+#define DRVUP_SHIFT 20
+#define DRVUP_MASK (0x7F << DRVUP_SHIFT)
+#define SLWR_SHIFT 28
+#define SLWR_MASK (3 << SLWR_SHIFT)
+#define SLWF_SHIFT 30
+#define SLWF_MASK (3 << SLWF_SHIFT)
+
+static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwf == PMUX_SLWF_NONE)
+ return;
+
+ /* Error check on pad and slwf */
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_slw_isvalid(slwf));
+
+ val = readl(reg);
+ val &= ~SLWF_MASK;
+ val |= (slwf << SLWF_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwr == PMUX_SLWR_NONE)
+ return;
+
+ /* Error check on pad and slwr */
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_slw_isvalid(slwr));
+
+ val = readl(reg);
+ val &= ~SLWR_MASK;
+ val |= (slwr << SLWR_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvup == PMUX_DRVUP_NONE)
+ return;
+
+ /* Error check on pad and drvup */
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_drv_isvalid(drvup));
+
+ val = readl(reg);
+ val &= ~DRVUP_MASK;
+ val |= (drvup << DRVUP_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvdn == PMUX_DRVDN_NONE)
+ return;
+
+ /* Error check on pad and drvdn */
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_drv_isvalid(drvdn));
+
+ val = readl(reg);
+ val &= ~DRVDN_MASK;
+ val |= (drvdn << DRVDN_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (lpmd == PMUX_LPMD_NONE)
+ return;
+
+ /* Error check pad and lpmd value */
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_lpmd_isvalid(lpmd));
+
+ val = readl(reg);
+ val &= ~LPMD_MASK;
+ val |= (lpmd << LPMD_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (schmt == PMUX_SCHMT_NONE)
+ return;
+
+ /* Error check pad */
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_schmt_isvalid(schmt));
+
+ val = readl(reg);
+ if (schmt == PMUX_SCHMT_ENABLE)
+ val |= (1 << SCHMT_SHIFT);
+ else
+ val &= ~(1 << SCHMT_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
+{
+ u32 *reg = DRV_REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (hsm == PMUX_HSM_NONE)
+ return;
+
+ /* Error check pad */
+ assert(pmux_drvgrp_isvalid(grp));
+ assert(pmux_hsm_isvalid(hsm));
+
+ val = readl(reg);
+ if (hsm == PMUX_HSM_ENABLE)
+ val |= (1 << HSM_SHIFT);
+ else
+ val &= ~(1 << HSM_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+
+static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
+{
+ enum pmux_drvgrp grp = config->drvgrp;
+
+ pinmux_set_drvup_slwf(grp, config->slwf);
+ pinmux_set_drvdn_slwr(grp, config->slwr);
+ pinmux_set_drvup(grp, config->drvup);
+ pinmux_set_drvdn(grp, config->drvdn);
+ pinmux_set_lpmd(grp, config->lpmd);
+ pinmux_set_schmt(grp, config->schmt);
+ pinmux_set_hsm(grp, config->hsm);
+}
+
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+ int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_drvgrp(&config[i]);
+}
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GMI:
- pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
-
- pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
- pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
-
- pinmux_tristate_disable(PINGRP_GMI_A16);
- pinmux_tristate_disable(PINGRP_GMI_A17);
- pinmux_tristate_disable(PINGRP_GMI_A18);
- pinmux_tristate_disable(PINGRP_GMI_A19);
+ pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_FUNC_UARTD);
+
+ pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
+
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
+ pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
break;
}
break;
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
-/* Tegra114 pin multiplexing functions */
-
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_func func_safe;
- enum pmux_vddio vddio;
- enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT 0
-#define PMUX_PULL_SHIFT 2
-#define PMUX_TRISTATE_SHIFT 4
-#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT 5
-#define PMUX_OD_SHIFT 6
-#define PMUX_LOCK_SHIFT 7
-#define PMUX_IO_RESET_SHIFT 8
-#define PMUX_RCV_SEL_SHIFT 9
-
-#define PGRP_HSM_SHIFT 2
-#define PGRP_SCHMT_SHIFT 3
-#define PGRP_LPMD_SHIFT 4
-#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT 12
-#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT 20
-#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT 28
-#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT 30
-#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
-
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
- { \
- .vddio = PMUX_VDDIO_ ## vdd, \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
- .func_safe = PMUX_FUNC_RSVD1, \
- .io = PMUX_PIN_ ## iod, \
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
}
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
- PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+#define PIN_RESERVED {}
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
- /* NAME VDD f0 f1 f2 f3 */
- PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
- PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
- PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
- PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
+static const struct pmux_pingrp_desc tegra114_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
+ PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_SCLK_PP3, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(PV0, USB, RSVD2, RSVD3, RSVD4),
+ PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
+ PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
+ PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
+ PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
+ PIN_RESERVED,
PIN_RESERVED,
- PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
+ /* Offset 0x3068 */
+ PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
- PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
PIN_RESERVED,
+ /* Offset 0x3110 */
+ PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
- PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
- PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
- PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
- PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
- PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
- PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
- PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
- PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
- PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
- PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
- PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
- PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
- PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
- PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
- PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
- PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
- PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
- PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
- PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
- PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
- PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
- PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
- PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3280 */
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
- PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
- PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
- PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
- PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
- PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
- PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
- PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
- PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
- PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
- PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
- PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
- PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
- PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
- PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
- PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
- PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
- PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
- PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
- PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
- PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
- PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
- PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
- PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
- PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
- PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
- PIN_RESERVED,
- PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
- PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
- PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
- PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
- PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
- PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
- PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
- PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
- PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
- PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved by t114: 0x3404 */
- PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3164 */
+ PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_RTS_N_PJ6, UARTA, UARTB, RSVD3, SPI4),
+ PIN(UART2_CTS_N_PJ5, UARTA, UARTB, RSVD3, SPI4),
+ PIN(UART3_TXD_PW6, UARTC, RSVD2, RSVD3, SPI4),
+ PIN(UART3_RXD_PW7, UARTC, RSVD2, RSVD3, SPI4),
+ PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4),
+ PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, DISPLAYA),
+ PIN(PU0, OWR, UARTA, RSVD3, RSVD4),
+ PIN(PU1, RSVD1, UARTA, RSVD3, RSVD4),
+ PIN(PU2, RSVD1, UARTA, RSVD3, RSVD4),
+ PIN(PU3, PWM0, UARTA, DISPLAYA, DISPLAYB),
+ PIN(PU4, PWM1, UARTA, DISPLAYA, DISPLAYB),
+ PIN(PU5, PWM2, UARTA, DISPLAYA, DISPLAYB),
+ PIN(PU6, PWM3, UARTA, USB, DISPLAYB),
+ PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_FS_PP4, I2S3, RSVD2, DTV, RSVD4),
+ PIN(DAP4_DIN_PP5, I2S3, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_DOUT_PP6, I2S3, RSVD2, DTV, RSVD4),
+ PIN(DAP4_SCLK_PP7, I2S3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
+ PIN(GMI_IORDY_PI5, SDMMC2, RSVD2, GMI, TRACE),
+ PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV),
+ PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE),
+ PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE),
+ PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB),
+ PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC),
+ PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE),
+ PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT),
+ PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE),
+ PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4),
+ PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, SDMMC2),
+ PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_AD8_PH0, PWM0, NAND, GMI, DTV),
+ PIN(GMI_AD9_PH1, PWM1, NAND, GMI, CLDVFS),
+ PIN(GMI_AD10_PH2, PWM2, NAND, GMI, CLDVFS),
+ PIN(GMI_AD11_PH3, PWM3, NAND, GMI, USB),
+ PIN(GMI_AD12_PH4, SDMMC2, NAND, GMI, RSVD4),
+ PIN(GMI_AD13_PH5, SDMMC2, NAND, GMI, RSVD4),
+ PIN(GMI_AD14_PH6, SDMMC2, NAND, GMI, DTV),
+ PIN(GMI_AD15_PH7, SDMMC2, NAND, GMI, DTV),
+ PIN(GMI_A16_PJ7, UARTD, TRACE, GMI, GMI_ALT),
+ PIN(GMI_A17_PB0, UARTD, RSVD2, GMI, TRACE),
+ PIN(GMI_A18_PB1, UARTD, RSVD2, GMI, TRACE),
+ PIN(GMI_A19_PK7, UARTD, SPI4, GMI, TRACE),
+ PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, SPI4),
+ PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, SOC),
+ PIN(GMI_DQS_P_PJ3, SDMMC2, NAND, GMI, TRACE),
+ PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
+ PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
+ PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x3284 */
+ PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, RSVD4),
+ PIN(PCC1, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(PBB0, I2S4, VI, VI_ALT1, VI_ALT3),
+ PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, RSVD4),
+ PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, RSVD4),
+ PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, RSVD4),
+ PIN(PBB7, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW3_PR3, KBC, DISPLAYA, RSVD3, DISPLAYB),
+ PIN(KB_ROW4_PR4, KBC, DISPLAYA, SPI2, DISPLAYB),
+ PIN(KB_ROW5_PR5, KBC, DISPLAYA, SPI2, DISPLAYB),
+ PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+ PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
+ PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x32fc */
+ PIN(KB_COL0_PQ0, KBC, USB, SPI2, EMC_DLL),
+ PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, EMC_DLL),
+ PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
+ PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
+ PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4),
+ PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, RSVD4),
+ PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
+ PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
+ PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
+ PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
+ PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
+ PIN(CLK1_REQ_PEE2, DAP, DAP1, RSVD3, RSVD4),
+ PIN(CLK1_OUT_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
+ PIN(SPDIF_IN_PK6, SPDIF, USB, RSVD3, RSVD4),
+ PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, RSVD4),
+ PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, RSVD4),
+ PIN(DVFS_PWM_PX0, SPI6, CLDVFS, RSVD3, RSVD4),
+ PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, RSVD3, RSVD4),
+ PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, RSVD3, RSVD4),
+ PIN(DVFS_CLK_PX2, SPI6, CLDVFS, RSVD3, RSVD4),
+ PIN(GPIO_X4_AUD_PX4, RSVD1, SPI1, SPI2, DAP2),
+ PIN(GPIO_X5_AUD_PX5, RSVD1, SPI1, SPI2, RSVD4),
+ PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, RSVD4),
+ PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3390 */
+ PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
+ PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
+ PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
+ PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x33e0 */
+ PIN(HDMI_CEC_PEE3, CEC, SDMMC3, RSVD3, SOC),
+ PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
+ PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
+ PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
+ PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
+ PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
+ PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_CLK_LB, SDMMC2, NAND, GMI, RSVD4),
+ PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
-
- reg = readl(tri);
- if (enable)
- reg |= PMUX_TRISTATE_MASK;
- else
- reg &= ~PMUX_TRISTATE_MASK;
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pull = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- reg = readl(pull);
- reg &= ~(0x3 << PMUX_PULL_SHIFT);
- reg |= (pupd << PMUX_PULL_SHIFT);
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *muxctl = &pmt->pmt_ctl[pin];
- int i, mux = -1;
- u32 reg;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
- if (func & PMUX_FUNC_RSVD1) {
- mux = func & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- reg = readl(muxctl);
- reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
- reg |= (mux << PMUX_MUXCTL_SHIFT);
- writel(reg, muxctl);
-
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_io = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- reg = readl(pin_io);
- reg &= ~(0x1 << PMUX_IO_SHIFT);
- reg |= (io & 0x1) << PMUX_IO_SHIFT;
- writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_lock = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return 0;
-
- reg = readl(pin_lock);
- reg &= ~(0x1 << PMUX_LOCK_SHIFT);
- if (lock == PMUX_PIN_LOCK_ENABLE)
- reg |= (0x1 << PMUX_LOCK_SHIFT);
- else {
- /* lock == DISABLE, which isn't possible */
- printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
- __func__, lock);
- }
- writel(reg, pin_lock);
-
- return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_od = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return 0;
-
- reg = readl(pin_od);
- reg &= ~(0x1 << PMUX_OD_SHIFT);
- if (od == PMUX_PIN_OD_ENABLE)
- reg |= (0x1 << PMUX_OD_SHIFT);
- writel(reg, pin_od);
-
- return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_ioreset = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return 0;
-
- reg = readl(pin_ioreset);
- reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- reg |= (0x1 << PMUX_IO_RESET_SHIFT);
- writel(reg, pin_ioreset);
-
- return 0;
-}
-
-static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
- enum pmux_pin_rcv_sel rcv_sel)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and rcv_sel */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
- if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
- return 0;
-
- reg = readl(pin_rcv_sel);
- reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
- if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
- reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
- writel(reg, pin_rcv_sel);
-
- return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
- pinmux_set_io(pin, config->io);
- pinmux_set_lock(pin, config->lock);
- pinmux_set_od(pin, config->od);
- pinmux_set_ioreset(pin, config->ioreset);
- pinmux_set_rcv_sel(pin, config->rcv_sel);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwf = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwf */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwf));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PGRP_SLWF_NONE)
- return 0;
-
- reg = readl(pad_slwf);
- reg &= ~PGRP_SLWF_MASK;
- reg |= (slwf << PGRP_SLWF_SHIFT);
- writel(reg, pad_slwf);
-
- return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwr = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwr */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwr));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PGRP_SLWR_NONE)
- return 0;
-
- reg = readl(pad_slwr);
- reg &= ~PGRP_SLWR_MASK;
- reg |= (slwr << PGRP_SLWR_SHIFT);
- writel(reg, pad_slwr);
-
- return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvup = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvup */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvup));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PGRP_DRVUP_NONE)
- return 0;
-
- reg = readl(pad_drvup);
- reg &= ~PGRP_DRVUP_MASK;
- reg |= (drvup << PGRP_DRVUP_SHIFT);
- writel(reg, pad_drvup);
-
- return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvdn = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvdn */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvdn));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PGRP_DRVDN_NONE)
- return 0;
-
- reg = readl(pad_drvdn);
- reg &= ~PGRP_DRVDN_MASK;
- reg |= (drvdn << PGRP_DRVDN_SHIFT);
- writel(reg, pad_drvdn);
-
- return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_lpmd = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad and lpmd value */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_lpmd_isvalid(lpmd));
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PGRP_LPMD_NONE)
- return 0;
-
- reg = readl(pad_lpmd);
- reg &= ~PGRP_LPMD_MASK;
- reg |= (lpmd << PGRP_LPMD_SHIFT);
- writel(reg, pad_lpmd);
-
- return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_schmt = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (schmt == PGRP_SCHMT_NONE)
- return 0;
-
- reg = readl(pad_schmt);
- reg &= ~(1 << PGRP_SCHMT_SHIFT);
- if (schmt == PGRP_SCHMT_ENABLE)
- reg |= (0x1 << PGRP_SCHMT_SHIFT);
- writel(reg, pad_schmt);
-
- return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_hsm = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (hsm == PGRP_HSM_NONE)
- return 0;
-
- reg = readl(pad_hsm);
- reg &= ~(1 << PGRP_HSM_SHIFT);
- if (hsm == PGRP_HSM_ENABLE)
- reg |= (0x1 << PGRP_HSM_SHIFT);
- writel(reg, pad_hsm);
-
- return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
- enum pdrive_pingrp pad = config->padgrp;
-
- padgrp_set_drvup_slwf(pad, config->slwf);
- padgrp_set_drvdn_slwr(pad, config->slwr);
- padgrp_set_drvup(pad, config->drvup);
- padgrp_set_drvdn(pad, config->drvdn);
- padgrp_set_lpmd(pad, config->lpmd);
- padgrp_set_schmt(pad, config->schmt);
- padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- padctrl_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
- pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
- pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
- pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
- pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
- pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
- pinmux_tristate_disable(PINGRP_GPIO_PJ7);
- pinmux_tristate_disable(PINGRP_GPIO_PB0);
- pinmux_tristate_disable(PINGRP_GPIO_PB1);
- pinmux_tristate_disable(PINGRP_GPIO_PK7);
+ pinmux_tristate_disable(PMUX_PINGRP_PJ7);
+ pinmux_tristate_disable(PMUX_PINGRP_PB0);
+ pinmux_tristate_disable(PMUX_PINGRP_PB1);
+ pinmux_tristate_disable(PMUX_PINGRP_PK7);
break;
}
break;
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_KBC:
- pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_FUNC_UARTA);
- pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
- pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
- pinmux_tristate_disable(PINGRP_KB_ROW9);
- pinmux_tristate_disable(PINGRP_KB_ROW10);
+ pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
+ pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
break;
}
break;
/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
-/* Tegra124 pin multiplexing functions */
-
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_func func_safe;
- enum pmux_vddio vddio;
- enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT 0
-#define PMUX_PULL_SHIFT 2
-#define PMUX_TRISTATE_SHIFT 4
-#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT 5
-#define PMUX_OD_SHIFT 6
-#define PMUX_LOCK_SHIFT 7
-#define PMUX_IO_RESET_SHIFT 8
-#define PMUX_RCV_SEL_SHIFT 9
-
-#define PGRP_HSM_SHIFT 2
-#define PGRP_SCHMT_SHIFT 3
-#define PGRP_LPMD_SHIFT 4
-#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT 12
-#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT 20
-#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT 28
-#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT 30
-#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
-
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
- { \
- .vddio = PMUX_VDDIO_ ## vdd, \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
- .func_safe = PMUX_FUNC_RSVD1, \
- .io = PMUX_PIN_ ## iod, \
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
}
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
- PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+#define PIN_RESERVED {}
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
- /* NAME VDD f0 f1 f2 f3 */
- PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
- PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
- PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
- PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
- PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
- PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
- PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */
+static const struct pmux_pingrp_desc tegra124_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
+ PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
+ PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, RSVD4),
+ PIN(DAP3_SCLK_PP3, I2S2, SPI5, RSVD3, DISPLAYB),
+ PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
+ PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
+ PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
+ PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
+ PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
PIN_RESERVED,
- PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */
PIN_RESERVED,
+ /* Offset 0x3068 */
+ PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
- PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */
PIN_RESERVED,
PIN_RESERVED,
+ /* Offset 0x3110 */
+ PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
- PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
- PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
- PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
- PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
- PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
- PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
- PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
- PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
- PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
- PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
- PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
- PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
- PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
- PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
- PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
- PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
- PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
- PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
- PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
- PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
- PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
- PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
- PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
- PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
- PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
- PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
- PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
- PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
- PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
- PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
- PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
- PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
- PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
- PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3280 */
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
- PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
- PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
- PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
- PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
- PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
- PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
- PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
- PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
- PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
- PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
- PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
- PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
- PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
- PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
- PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
- PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
- PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
- PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
- PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
- PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
- PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
- PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
- PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
- PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
- PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
- PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
- PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
- PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
- PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
- PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
- PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */
- PIN_RESERVED,
- PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
- PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
- PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
- PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
- PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
- PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
- PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
- PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
- PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
- PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
- PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED, /* Reserved: 0x3404 */
- PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3164 */
+ PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
+ PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
+ PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
+ PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, SPI4),
+ PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, SPI4),
+ PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI),
+ PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, GMI),
+ PIN(PU0, OWR, UARTA, GMI, RSVD4),
+ PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU3, PWM0, UARTA, GMI, DISPLAYB),
+ PIN(PU4, PWM1, UARTA, GMI, DISPLAYB),
+ PIN(PU5, PWM2, UARTA, GMI, DISPLAYB),
+ PIN(PU6, PWM3, UARTA, RSVD3, GMI),
+ PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_FS_PP4, I2S3, GMI, DTV, RSVD4),
+ PIN(DAP4_DIN_PP5, I2S3, GMI, RSVD3, RSVD4),
+ PIN(DAP4_DOUT_PP6, I2S3, GMI, DTV, RSVD4),
+ PIN(DAP4_SCLK_PP7, I2S3, GMI, RSVD3, RSVD4),
+ PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
+ PIN(PC7, RSVD1, RSVD2, GMI, GMI_ALT),
+ PIN(PI5, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(PI7, RSVD1, TRACE, GMI, DTV),
+ PIN(PK0, RSVD1, SDMMC3, GMI, SOC),
+ PIN(PK1, SDMMC2, TRACE, GMI, RSVD4),
+ PIN(PJ0, RSVD1, RSVD2, GMI, USB),
+ PIN(PJ2, RSVD1, RSVD2, GMI, SOC),
+ PIN(PK3, SDMMC2, TRACE, GMI, CCLA),
+ PIN(PK4, SDMMC2, RSVD2, GMI, GMI_ALT),
+ PIN(PK2, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PI3, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PI6, RSVD1, RSVD2, GMI, SDMMC2),
+ PIN(PG0, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PG1, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PG2, RSVD1, TRACE, GMI, RSVD4),
+ PIN(PG3, RSVD1, TRACE, GMI, RSVD4),
+ PIN(PG4, RSVD1, TMDS, GMI, SPI4),
+ PIN(PG5, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PG6, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PG7, RSVD1, RSVD2, GMI, SPI4),
+ PIN(PH0, PWM0, TRACE, GMI, DTV),
+ PIN(PH1, PWM1, TMDS, GMI, DISPLAYA),
+ PIN(PH2, PWM2, TMDS, GMI, CLDVFS),
+ PIN(PH3, PWM3, SPI4, GMI, CLDVFS),
+ PIN(PH4, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(PH5, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(PH6, SDMMC2, TRACE, GMI, DTV),
+ PIN(PH7, SDMMC2, TRACE, GMI, DTV),
+ PIN(PJ7, UARTD, RSVD2, GMI, GMI_ALT),
+ PIN(PB0, UARTD, RSVD2, GMI, RSVD4),
+ PIN(PB1, UARTD, RSVD2, GMI, RSVD4),
+ PIN(PK7, UARTD, RSVD2, GMI, RSVD4),
+ PIN(PI0, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PI1, RSVD1, RSVD2, GMI, RSVD4),
+ PIN(PI2, SDMMC2, TRACE, GMI, RSVD4),
+ PIN(PI4, SPI4, TRACE, GMI, DISPLAYA),
+ PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
+ PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, RSVD3, RSVD4),
+ PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
+ PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x3284 */
+ PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC2),
+ PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC2),
+ PIN(PBB0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT),
+ PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC2),
+ PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC2),
+ PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC2),
+ PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC2),
+ PIN(PBB5, VGP5, DISPLAYA, RSVD3, SDMMC2),
+ PIN(PBB6, I2S4, RSVD2, DISPLAYB, SDMMC2),
+ PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC2),
+ PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2),
+ PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW3_PR3, KBC, DISPLAYA, SYS, DISPLAYB),
+ PIN(KB_ROW4_PR4, KBC, DISPLAYA, RSVD3, DISPLAYB),
+ PIN(KB_ROW5_PR5, KBC, DISPLAYA, RSVD3, DISPLAYB),
+ PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+ PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
+ PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
+ PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
+ PIN(KB_ROW11_PS3, KBC, RSVD2, RSVD3, IRDA),
+ PIN(KB_ROW12_PS4, KBC, RSVD2, RSVD3, IRDA),
+ PIN(KB_ROW13_PS5, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_ROW14_PS6, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_ROW15_PS7, KBC, SOC, RSVD3, RSVD4),
+ PIN(KB_COL0_PQ0, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
+ PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
+ PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
+ PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC3, RSVD4),
+ PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, UARTD),
+ PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, UARTD),
+ PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x3324 */
+ PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
+ PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
+ PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
+ PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SATA),
+ PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
+ PIN(DAP_MCLK1_REQ_PEE2, DAP, DAP1, SATA, RSVD4),
+ PIN(DAP_MCLK1_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
+ PIN(SPDIF_IN_PK6, SPDIF, RSVD2, RSVD3, I2C3),
+ PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, I2C3),
+ PIN(DAP2_FS_PA2, I2S1, HDA, GMI, RSVD4),
+ PIN(DAP2_DIN_PA4, I2S1, HDA, GMI, RSVD4),
+ PIN(DAP2_DOUT_PA5, I2S1, HDA, GMI, RSVD4),
+ PIN(DAP2_SCLK_PA3, I2S1, HDA, GMI, RSVD4),
+ PIN(DVFS_PWM_PX0, SPI6, CLDVFS, GMI, RSVD4),
+ PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, GMI, RSVD4),
+ PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, GMI, RSVD4),
+ PIN(DVFS_CLK_PX2, SPI6, CLDVFS, GMI, RSVD4),
+ PIN(GPIO_X4_AUD_PX4, GMI, SPI1, SPI2, DAP2),
+ PIN(GPIO_X5_AUD_PX5, GMI, SPI1, SPI2, RSVD4),
+ PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, GMI),
+ PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3390 */
+ PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
+ PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
+ PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
+ PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
+ PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x33bc */
+ PIN(PEX_L0_RST_N_PDD1, PE0, RSVD2, RSVD3, RSVD4),
+ PIN(PEX_L0_CLKREQ_N_PDD2, PE0, RSVD2, RSVD3, RSVD4),
+ PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
+ /* Offset 0x33cc */
+ PIN(PEX_L1_RST_N_PDD5, PE1, RSVD2, RSVD3, RSVD4),
+ PIN(PEX_L1_CLKREQ_N_PDD6, PE1, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x33e0 */
+ PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
+ PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
+ PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
+ PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
+ PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
+ PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_CLK_LB, SDMMC2, RSVD2, GMI, RSVD4),
+ PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+ PIN(KB_ROW16_PT0, KBC, RSVD2, RSVD3, UARTC),
+ PIN(KB_ROW17_PT1, KBC, RSVD2, RSVD3, UARTC),
+ PIN(USB_VBUS_EN2_PFF1, USB, RSVD2, RSVD3, RSVD4),
+ PIN(PFF2, SATA, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ /* Offset 0x3430 */
+ PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
-
- reg = readl(tri);
- if (enable)
- reg |= PMUX_TRISTATE_MASK;
- else
- reg &= ~PMUX_TRISTATE_MASK;
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pull = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- reg = readl(pull);
- reg &= ~(0x3 << PMUX_PULL_SHIFT);
- reg |= (pupd << PMUX_PULL_SHIFT);
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *muxctl = &pmt->pmt_ctl[pin];
- int i, mux = -1;
- u32 reg;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
- if (func & PMUX_FUNC_RSVD1) {
- mux = func & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- reg = readl(muxctl);
- reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
- reg |= (mux << PMUX_MUXCTL_SHIFT);
- writel(reg, muxctl);
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_io = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- reg = readl(pin_io);
- reg &= ~(0x1 << PMUX_IO_SHIFT);
- reg |= (io & 0x1) << PMUX_IO_SHIFT;
- writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_lock = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return 0;
-
- reg = readl(pin_lock);
- reg &= ~(0x1 << PMUX_LOCK_SHIFT);
- if (lock == PMUX_PIN_LOCK_ENABLE) {
- reg |= (0x1 << PMUX_LOCK_SHIFT);
- } else {
- /* lock == DISABLE, which isn't possible */
- printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
- __func__, lock);
- }
- writel(reg, pin_lock);
-
- return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_od = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return 0;
-
- reg = readl(pin_od);
- reg &= ~(0x1 << PMUX_OD_SHIFT);
- if (od == PMUX_PIN_OD_ENABLE)
- reg |= (0x1 << PMUX_OD_SHIFT);
- writel(reg, pin_od);
-
- return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_ioreset = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return 0;
-
- reg = readl(pin_ioreset);
- reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- reg |= (0x1 << PMUX_IO_RESET_SHIFT);
- writel(reg, pin_ioreset);
-
- return 0;
-}
-
-static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
- enum pmux_pin_rcv_sel rcv_sel)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and rcv_sel */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
- if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
- return 0;
-
- reg = readl(pin_rcv_sel);
- reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
- if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
- reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
- writel(reg, pin_rcv_sel);
-
- return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
- pinmux_set_io(pin, config->io);
- pinmux_set_lock(pin, config->lock);
- pinmux_set_od(pin, config->od);
- pinmux_set_ioreset(pin, config->ioreset);
- pinmux_set_rcv_sel(pin, config->rcv_sel);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwf = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwf */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwf));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PGRP_SLWF_NONE)
- return 0;
-
- reg = readl(pad_slwf);
- reg &= ~PGRP_SLWF_MASK;
- reg |= (slwf << PGRP_SLWF_SHIFT);
- writel(reg, pad_slwf);
-
- return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwr = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwr */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwr));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PGRP_SLWR_NONE)
- return 0;
-
- reg = readl(pad_slwr);
- reg &= ~PGRP_SLWR_MASK;
- reg |= (slwr << PGRP_SLWR_SHIFT);
- writel(reg, pad_slwr);
-
- return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvup = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvup */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvup));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PGRP_DRVUP_NONE)
- return 0;
-
- reg = readl(pad_drvup);
- reg &= ~PGRP_DRVUP_MASK;
- reg |= (drvup << PGRP_DRVUP_SHIFT);
- writel(reg, pad_drvup);
-
- return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvdn = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvdn */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvdn));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PGRP_DRVDN_NONE)
- return 0;
-
- reg = readl(pad_drvdn);
- reg &= ~PGRP_DRVDN_MASK;
- reg |= (drvdn << PGRP_DRVDN_SHIFT);
- writel(reg, pad_drvdn);
-
- return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_lpmd = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad and lpmd value */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_lpmd_isvalid(lpmd));
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PGRP_LPMD_NONE)
- return 0;
-
- reg = readl(pad_lpmd);
- reg &= ~PGRP_LPMD_MASK;
- reg |= (lpmd << PGRP_LPMD_SHIFT);
- writel(reg, pad_lpmd);
-
- return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_schmt = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (schmt == PGRP_SCHMT_NONE)
- return 0;
-
- reg = readl(pad_schmt);
- reg &= ~(1 << PGRP_SCHMT_SHIFT);
- if (schmt == PGRP_SCHMT_ENABLE)
- reg |= (0x1 << PGRP_SCHMT_SHIFT);
- writel(reg, pad_schmt);
-
- return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_hsm = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- /* NONE means unspecified/do not change/use POR value */
- if (hsm == PGRP_HSM_NONE)
- return 0;
-
- reg = readl(pad_hsm);
- reg &= ~(1 << PGRP_HSM_SHIFT);
- if (hsm == PGRP_HSM_ENABLE)
- reg |= (0x1 << PGRP_HSM_SHIFT);
- writel(reg, pad_hsm);
-
- return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
- enum pdrive_pingrp pad = config->padgrp;
-
- padgrp_set_drvup_slwf(pad, config->slwf);
- padgrp_set_drvdn_slwr(pad, config->slwr);
- padgrp_set_drvup(pad, config->drvup);
- padgrp_set_drvdn(pad, config->drvdn);
- padgrp_set_lpmd(pad, config->lpmd);
- padgrp_set_schmt(pad, config->schmt);
- padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- padctrl_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
-#include <asm/arch/apb_misc.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
#include <asm/arch/tegra.h>
* The PINMUX macro is used to set up pinmux tables.
*/
#define PINMUX(grp, mux, pupd, tri) \
- {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+ {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
-static const struct pingroup_config disp1_default[] = {
+static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(LDI, DISPA, NORMAL, NORMAL),
PINMUX(LHP0, DISPA, NORMAL, NORMAL),
PINMUX(LHP1, DISPA, NORMAL, NORMAL),
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_IRRX_IRTX:
- pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_IRRX);
- pinmux_tristate_disable(PINGRP_IRTX);
+ pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_IRRX);
+ pinmux_tristate_disable(PMUX_PINGRP_IRTX);
break;
case FUNCMUX_UART1_UAA_UAB:
- pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_UAA);
- pinmux_tristate_disable(PINGRP_UAB);
+ pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAB);
bad_config = 0;
break;
case FUNCMUX_UART1_GPU:
- pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_GPU);
+ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_GPU);
bad_config = 0;
break;
case FUNCMUX_UART1_SDIO1:
- pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_SDIO1);
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
bad_config = 0;
break;
}
* state the group to avoid driving any signal onto it
* until we know what's connected.
*/
- pinmux_tristate_enable(PINGRP_SDB);
- pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+ pinmux_tristate_enable(PMUX_PINGRP_SDB);
+ pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
}
break;
case PERIPH_ID_UART2:
if (config == FUNCMUX_UART2_UAD) {
- pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
- pinmux_tristate_disable(PINGRP_UAD);
+ pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
+ pinmux_tristate_disable(PMUX_PINGRP_UAD);
}
break;
case PERIPH_ID_UART4:
if (config == FUNCMUX_UART4_GMC) {
- pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
- pinmux_tristate_disable(PINGRP_GMC);
+ pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
+ pinmux_tristate_disable(PMUX_PINGRP_GMC);
}
break;
case PERIPH_ID_DVC_I2C:
/* there is only one selection, pinmux_config is ignored */
if (config == FUNCMUX_DVC_I2CP) {
- pinmux_set_func(PINGRP_I2CP, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PINGRP_I2CP);
+ pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
+ pinmux_tristate_disable(PMUX_PINGRP_I2CP);
}
break;
case PERIPH_ID_I2C1:
/* support pinmux_config of 0 for now, */
if (config == FUNCMUX_I2C1_RM) {
- pinmux_set_func(PINGRP_RM, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PINGRP_RM);
+ pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
+ pinmux_tristate_disable(PMUX_PINGRP_RM);
}
break;
case PERIPH_ID_I2C2: /* I2C2 */
switch (config) {
case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */
- pinmux_set_func(PINGRP_DDC, PMUX_FUNC_I2C2);
+ pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
/* PTA to HDMI */
- pinmux_set_func(PINGRP_PTA, PMUX_FUNC_HDMI);
- pinmux_tristate_disable(PINGRP_DDC);
+ pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
+ pinmux_tristate_disable(PMUX_PINGRP_DDC);
break;
case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */
- pinmux_set_func(PINGRP_PTA, PMUX_FUNC_I2C2);
+ pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
/* set DDC_SEL to RSVDx (RSVD2 works for now) */
- pinmux_set_func(PINGRP_DDC, PMUX_FUNC_RSVD2);
- pinmux_tristate_disable(PINGRP_PTA);
+ pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
+ pinmux_tristate_disable(PMUX_PINGRP_PTA);
bad_config = 0;
break;
}
case PERIPH_ID_I2C3: /* I2C3 */
/* support pinmux_config of 0 for now */
if (config == FUNCMUX_I2C3_DTF) {
- pinmux_set_func(PINGRP_DTF, PMUX_FUNC_I2C3);
- pinmux_tristate_disable(PINGRP_DTF);
+ pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
+ pinmux_tristate_disable(PMUX_PINGRP_DTF);
}
break;
case PERIPH_ID_SDMMC1:
if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
- pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
- pinmux_tristate_disable(PINGRP_SDIO1);
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
}
break;
case PERIPH_ID_SDMMC2:
if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
- pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
- pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
+ pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
+ pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
- pinmux_tristate_disable(PINGRP_DTA);
- pinmux_tristate_disable(PINGRP_DTD);
+ pinmux_tristate_disable(PMUX_PINGRP_DTA);
+ pinmux_tristate_disable(PMUX_PINGRP_DTD);
}
break;
case PERIPH_ID_SDMMC3:
switch (config) {
case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
- pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3);
-
- pinmux_tristate_disable(PINGRP_SLXA);
- pinmux_tristate_disable(PINGRP_SLXC);
- pinmux_tristate_disable(PINGRP_SLXD);
- pinmux_tristate_disable(PINGRP_SLXK);
+ pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
+
+ pinmux_tristate_disable(PMUX_PINGRP_SLXA);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXC);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXD);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXK);
/* fall through */
case FUNCMUX_SDMMC3_SDB_4BIT:
- pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
- pinmux_tristate_disable(PINGRP_SDB);
- pinmux_tristate_disable(PINGRP_SDC);
- pinmux_tristate_disable(PINGRP_SDD);
+ pinmux_tristate_disable(PMUX_PINGRP_SDB);
+ pinmux_tristate_disable(PMUX_PINGRP_SDC);
+ pinmux_tristate_disable(PMUX_PINGRP_SDD);
bad_config = 0;
break;
}
case PERIPH_ID_SDMMC4:
switch (config) {
case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
- pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_ATC);
- pinmux_tristate_disable(PINGRP_ATD);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
break;
case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
- pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_GME);
+ pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
+ pinmux_tristate_disable(PMUX_PINGRP_GME);
/* fall through */
case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
- pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_ATB);
- pinmux_tristate_disable(PINGRP_GMA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATB);
+ pinmux_tristate_disable(PMUX_PINGRP_GMA);
bad_config = 0;
break;
}
case PERIPH_ID_KBC:
if (config == FUNCMUX_DEFAULT) {
- enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB,
- PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE,
- PINGRP_KBCF};
+ enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
+ PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
+ PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
+ PMUX_PINGRP_KBCF};
int i;
for (i = 0; i < ARRAY_SIZE(grp); i++) {
case PERIPH_ID_USB2:
if (config == FUNCMUX_USB2_ULPI) {
- pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI);
- pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI);
- pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI);
+ pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
+ pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
+ pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
- pinmux_tristate_disable(PINGRP_UAA);
- pinmux_tristate_disable(PINGRP_UAB);
- pinmux_tristate_disable(PINGRP_UDA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAB);
+ pinmux_tristate_disable(PMUX_PINGRP_UDA);
}
break;
case PERIPH_ID_SPI1:
if (config == FUNCMUX_SPI1_GMC_GMD) {
- pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
- pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+ pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
+ pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
- pinmux_tristate_disable(PINGRP_GMC);
- pinmux_tristate_disable(PINGRP_GMD);
+ pinmux_tristate_disable(PMUX_PINGRP_GMC);
+ pinmux_tristate_disable(PMUX_PINGRP_GMD);
}
break;
case PERIPH_ID_NDFLASH:
switch (config) {
case FUNCMUX_NDFLASH_ATC:
- pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
- pinmux_tristate_disable(PINGRP_ATC);
+ pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
break;
case FUNCMUX_NDFLASH_KBC_8_BIT:
- pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND);
- pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
-
- pinmux_tristate_disable(PINGRP_KBCA);
- pinmux_tristate_disable(PINGRP_KBCC);
- pinmux_tristate_disable(PINGRP_KBCD);
- pinmux_tristate_disable(PINGRP_KBCE);
- pinmux_tristate_disable(PINGRP_KBCF);
+ pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
+
+ pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCC);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCD);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCE);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCF);
bad_config = 0;
break;
if (config == FUNCMUX_DEFAULT) {
int i;
- for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
+ for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
pinmux_set_func(i, PMUX_FUNC_DISPA);
pinmux_tristate_disable(i);
pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
}
- pinmux_config_table(disp1_default,
- ARRAY_SIZE(disp1_default));
+ pinmux_config_pingrp_table(disp1_default,
+ ARRAY_SIZE(disp1_default));
}
break;
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-
/*
* This defines the order of the pin mux control bits in the registers. For
* some reason there is no correspendence between the tristate, pin mux and
PUCTL_NONE = -1
};
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_func func_safe;
- enum pmux_vddio vddio;
- enum pmux_ctlid ctl_id;
- enum pmux_pullid pull_id;
-};
-
-
-/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
-#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
-
-/* Mask value for a tristate (within TRISTATE_REG(id)) */
-#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
-
-/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
-#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
-
-/* Converts a PUCTL id to a shift position */
-#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
-
-/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
-#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
-
-/* Converts a MUXCTL id to a shift position */
-#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
-
/* Convenient macro for defining pin group properties */
-#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
+#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
+ PMUX_FUNC_ ## f0, \
+ PMUX_FUNC_ ## f1, \
+ PMUX_FUNC_ ## f2, \
+ PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_ ## f_safe, \
.ctl_id = mux, \
.pull_id = pupd \
}
/* A normal pin group where the mux name and pull-up name match */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
- PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
- MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
+#define PIN(pingrp, f0, f1, f2, f3) \
+ PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
/* A pin group where the pull-up name doesn't have a 1-1 mapping */
-#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
- PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
- MUXCTL_ ## pg_name, PUCTL_ ## pupd)
+#define PINP(pingrp, f0, f1, f2, f3, pupd) \
+ PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
/* A pin group number which is not used */
#define PIN_RESERVED \
- PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
-
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
- PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
- PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
- PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
- PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
- PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
- PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
- PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
- PLLC_OUT1),
- PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
-
- PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
- PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
- PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
- PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
- PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
- PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
- PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
- PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
-
- PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
- GPSLXAU),
- PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
- PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
- PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
- PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
- PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
- PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
- PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
-
- PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
- PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
- PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
- PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
- PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
- PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
- PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
- PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
-
- PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
- PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
- PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
+ PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
+
+#define DRVGRP(drvgrp) \
+ PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
+
+static const struct pmux_pingrp_desc tegra20_pingroups[] = {
+ PIN(ATA, IDE, NAND, GMI, RSVD4),
+ PIN(ATB, IDE, NAND, GMI, SDIO4),
+ PIN(ATC, IDE, NAND, GMI, SDIO4),
+ PIN(ATD, IDE, NAND, GMI, SDIO4),
+ PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
+ PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
+ PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
+ PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
+
+ PIN(DAP2, DAP2, TWC, RSVD3, GMI),
+ PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
+ PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
+ PIN(DTB, RSVD1, RSVD2, VI, SPI1),
+ PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
+ PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
+ PIN(DTE, RSVD1, RSVD2, VI, SPI1),
+
+ PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
+ PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
+ PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
+ PIN(IRTX, UARTA, UARTB, GMI, SPI4),
+ PIN(IRRX, UARTA, UARTB, GMI, SPI4),
+ PIN(KBCB, KBC, NAND, SDIO2, MIO),
+ PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
+ PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
+
+ PIN(PTA, I2C2, HDMI, GMI, RSVD4),
+ PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
+ PIN(KBCE, KBC, NAND, OWR, RSVD4),
+ PIN(KBCF, KBC, NAND, TRACE, MIO),
+ PIN(GMA, UARTE, SPI3, GMI, SDIO4),
+ PIN(GMC, UARTD, SPI4, GMI, SFLASH),
+ PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
+ PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
+
+ PIN(GME, RSVD1, DAP5, GMI, SDIO4),
+ PIN(SDC, PWM, TWC, SDIO3, SPI3),
+ PIN(SDD, UARTA, PWM, SDIO3, SPI3),
PIN_RESERVED,
- PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
- PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
- PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
- PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
-
- PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
- PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
- PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
- PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
- PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
- PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
- PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
- PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
-
- PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
- PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
- PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
- PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
- PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
- PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
- PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
- PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
+ PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
+ PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
+ PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
+ PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
+
+ PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
+ PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
+ PIN(SPIA, SPI1, SPI2, SPI3, GMI),
+ PIN(SPIB, SPI1, SPI2, SPI3, GMI),
+ PIN(SPIC, SPI1, SPI2, SPI3, GMI),
+ PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
+
+ PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
+ PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
+ PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
+ PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
+ PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
+ PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UCB, UARTC, PWM, GMI, RSVD4),
PIN_RESERVED,
- PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
- PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
+ PIN(ATE, IDE, NAND, GMI, RSVD4),
+ PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
PIN_RESERVED,
PIN_RESERVED,
- PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
- PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
- PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
+ PIN(GMB, IDE, NAND, GMI, GMI_INT),
+ PIN(GMD, RSVD1, NAND, GMI, SFLASH),
+ PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
/* 64 */
- PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
-
- PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
-
- PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
- PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
- PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
- PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
- PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
- PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
- PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
- PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
-
- PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
- PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
- PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
- PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
- PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
- PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
+ PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
+
+ PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
+
+ PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
+ PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
+ PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
+ PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
+ PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
+ PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
+ PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
+ PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
+
+ PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
+ PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
+ PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
+ PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
+ PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
+ PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
/* 96 */
- PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
- PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
- PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
- PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
- PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
- PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
-
- PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
+ PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
+ PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
+ PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
+ PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
+ PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
+ PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
+
+ PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
PIN_RESERVED,
- PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
- PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
- PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
- PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
- PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
- PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
+ PIN(KBCD, KBC, NAND, SDIO2, MIO),
+ PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(DTF, I2C3, RSVD2, VI, RSVD4),
+ PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
+ PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
+ PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
/* these pin groups only have pullup and pull down control */
- PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
- PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
- PUCTL_NONE),
+ DRVGRP(CK32),
+ DRVGRP(DDRC),
+ DRVGRP(PMCA),
+ DRVGRP(PMCB),
+ DRVGRP(PMCC),
+ DRVGRP(PMCD),
+ DRVGRP(PMCE),
+ DRVGRP(XM2C),
+ DRVGRP(XM2D),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
- u32 reg;
-
- reg = readl(tri);
- if (enable)
- reg |= TRISTATE_MASK(pin);
- else
- reg &= ~TRISTATE_MASK(pin);
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
- u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
- u32 mask_bit;
- u32 reg;
- mask_bit = PULL_SHIFT(pull_id);
-
- reg = readl(pull);
- reg &= ~(0x3 << mask_bit);
- reg |= pupd << mask_bit;
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
- u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
- u32 mask_bit;
- int i, mux = -1;
- u32 reg;
-
- assert(pmux_func_isvalid(func));
-
- /* Handle special values */
- if (func >= PMUX_FUNC_RSVD1) {
- mux = (func - PMUX_FUNC_RSVD1) & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- mask_bit = MUXCTL_SHIFT(mux_id);
- reg = readl(muxctl);
- reg &= ~(0x3 << mask_bit);
- reg |= mux << mask_bit;
- writel(reg, muxctl);
-}
-
-void pinmux_config_pingroup(const struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
-}
-
-void pinmux_config_table(const struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
#include <asm/arch/sdram_param.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/fuse.h>
{
u32 ram_code;
struct sdram_params sdram;
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ struct apb_misc_pp_ctlr *apb_misc =
+ (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
union fbio_spare_reg fbio_spare;
/* get ram code that is used as index to array sdram_params in BCT */
- ram_code = (readl(&pmt->pmt_strap_opt_a) >>
- STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
+ ram_code = (readl(&apb_misc->strapping_opt_a) >>
+ STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
memcpy(&sdram,
(char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
sizeof(sdram));
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/warmboot.h>
void wb_start(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ struct apb_misc_pp_ctlr *apb_misc =
+ (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst =
u32 reg;
/* enable JTAG & TBE */
- writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
+ writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
/* Are we running where we're supposed to be? */
asm volatile (
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_ULPI:
- pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_ULPI_DATA0);
- pinmux_tristate_disable(PINGRP_ULPI_DATA1);
- pinmux_tristate_disable(PINGRP_ULPI_DATA2);
- pinmux_tristate_disable(PINGRP_ULPI_DATA3);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3);
+ pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4);
break;
}
break;
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
-/* Tegra30 pin multiplexing functions */
-
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-struct tegra_pingroup_desc {
- const char *name;
- enum pmux_func funcs[4];
- enum pmux_func func_safe;
- enum pmux_vddio vddio;
- enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT 0
-#define PMUX_PULL_SHIFT 2
-#define PMUX_TRISTATE_SHIFT 4
-#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT 5
-#define PMUX_OD_SHIFT 6
-#define PMUX_LOCK_SHIFT 7
-#define PMUX_IO_RESET_SHIFT 8
-
-#define PGRP_HSM_SHIFT 2
-#define PGRP_SCHMT_SHIFT 3
-#define PGRP_LPMD_SHIFT 4
-#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT 12
-#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT 20
-#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT 28
-#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT 30
-#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
-
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
- { \
- .vddio = PMUX_VDDIO_ ## vdd, \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
- .func_safe = PMUX_FUNC_RSVD1, \
- .io = PMUX_PIN_ ## iod, \
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
}
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
- PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
- /* NAME VDD f0 f1 f2 f3 */
- PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
- PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
- PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
- PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
- PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
- PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
- PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
- PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
- PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
- PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
- PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
- PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
- PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
- PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
- PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
- PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
- PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
- PINI(VI_MCLK, VI, VI, VI, VI, VI),
- PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
- PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
- PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
- PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
- PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
- PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
- PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
- PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
- PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
- PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
- PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
- PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
- PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
- PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
- PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
- PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
- PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
- PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
- PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
- PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
- PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
- PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
- PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
- PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
- PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
- PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
- PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
- PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
- PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
- PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
- PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
- PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
- PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
- PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
- PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
- PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
- PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
- PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
- PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
- PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
- PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
- PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
- PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
- PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
- PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
- PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
- PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
- PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
- PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
- PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
- PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
- PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
- PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
- PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
- PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
- PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
- PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
- PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
- PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
- PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
- PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
- PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
- PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
- PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
- PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
- PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
- PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
- PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
- PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
- PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
- PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
- PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
- PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
- PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
- PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
- PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
- PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
- PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
- PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
- PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
- PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
- PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
- PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
- PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
- PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
- PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
- PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra30_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
+ PIN(ULPI_CLK_PY0, SPI1, RSVD2, UARTD, ULPI),
+ PIN(ULPI_DIR_PY1, SPI1, RSVD2, UARTD, ULPI),
+ PIN(ULPI_NXT_PY2, SPI1, RSVD2, UARTD, ULPI),
+ PIN(ULPI_STP_PY3, SPI1, RSVD2, UARTD, ULPI),
+ PIN(DAP3_FS_PP0, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DIN_PP1, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(DAP3_DOUT_PP2, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(DAP3_SCLK_PP3, I2S2, RSVD2, DISPLAYA, DISPLAYB),
+ PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA),
+ PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA),
+ PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA),
+ PIN(PV2, OWR, RSVD2, RSVD3, RSVD4),
+ PIN(PV3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
+ PIN(LCD_PWR1_PC1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_PWR2_PC6, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_SDIN_PZ2, DISPLAYA, DISPLAYB, SPI5, RSVD4),
+ PIN(LCD_SDOUT_PN5, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_WR_N_PZ3, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_CS0_N_PN4, DISPLAYA, DISPLAYB, SPI5, RSVD4),
+ PIN(LCD_DC0_PN6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_SCK_PZ4, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_PWR0_PB2, DISPLAYA, DISPLAYB, SPI5, HDCP),
+ PIN(LCD_PCLK_PB3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_DE_PJ1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_HSYNC_PJ3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_VSYNC_PJ4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D0_PE0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D1_PE1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D2_PE2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D3_PE3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D4_PE4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D5_PE5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D6_PE6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D7_PE7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D8_PF0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D9_PF1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D10_PF2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D11_PF3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D12_PF4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D13_PF5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D14_PF6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D15_PF7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D16_PM0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D17_PM1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D18_PM2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D19_PM3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D20_PM4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D21_PM5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D22_PM6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_D23_PM7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_CS1_N_PW0, DISPLAYA, DISPLAYB, SPI5, RSVD4),
+ PIN(LCD_M1_PW1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(LCD_DC1_PD2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
+ PIN(HDMI_INT_PN7, HDMI, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN(CRT_HSYNC_PV6, CRT, RSVD2, RSVD3, RSVD4),
+ PIN(CRT_VSYNC_PV7, CRT, RSVD2, RSVD3, RSVD4),
+ PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4),
+ PIN(VI_D10_PT2, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_D11_PT3, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_PCLK_PT0, RSVD1, SDMMC2, VI, RSVD4),
+ PIN(VI_MCLK_PT1, VI, VI_ALT1, VI_ALT2, VI_ALT3),
+ PIN(VI_VSYNC_PD6, DDR, RSVD2, VI, RSVD4),
+ PIN(VI_HSYNC_PD7, DDR, RSVD2, VI, RSVD4),
+ PIN(UART2_RXD_PC3, UARTB, SPDIF, UARTA, SPI4),
+ PIN(UART2_TXD_PC2, UARTB, SPDIF, UARTA, SPI4),
+ PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
+ PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
+ PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UART3_CTS_N_PA1, UARTC, RSVD2, GMI, RSVD4),
+ PIN(UART3_RTS_N_PC0, UARTC, PWM0, GMI, RSVD4),
+ PIN(PU0, OWR, UARTA, GMI, RSVD4),
+ PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
+ PIN(PU3, PWM0, UARTA, GMI, RSVD4),
+ PIN(PU4, PWM1, UARTA, GMI, RSVD4),
+ PIN(PU5, PWM2, UARTA, GMI, RSVD4),
+ PIN(PU6, PWM3, UARTA, GMI, RSVD4),
+ PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
+ PIN(DAP4_FS_PP4, I2S3, RSVD2, GMI, RSVD4),
+ PIN(DAP4_DIN_PP5, I2S3, RSVD2, GMI, RSVD4),
+ PIN(DAP4_DOUT_PP6, I2S3, RSVD2, GMI, RSVD4),
+ PIN(DAP4_SCLK_PP7, I2S3, RSVD2, GMI, RSVD4),
+ PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
+ PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
+ PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV),
+ PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV),
+ PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT),
+ PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SATA),
+ PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, GMI_ALT),
+ PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD8_PH0, PWM0, NAND, GMI, RSVD4),
+ PIN(GMI_AD9_PH1, PWM1, NAND, GMI, RSVD4),
+ PIN(GMI_AD10_PH2, PWM2, NAND, GMI, RSVD4),
+ PIN(GMI_AD11_PH3, PWM3, NAND, GMI, RSVD4),
+ PIN(GMI_AD12_PH4, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD13_PH5, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD14_PH6, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_AD15_PH7, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_A16_PJ7, UARTD, SPI4, GMI, GMI_ALT),
+ PIN(GMI_A17_PB0, UARTD, SPI4, GMI, DTV),
+ PIN(GMI_A18_PB1, UARTD, SPI4, GMI, DTV),
+ PIN(GMI_A19_PK7, UARTD, SPI4, GMI, RSVD4),
+ PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_DQS_PI2, RSVD1, NAND, GMI, RSVD4),
+ PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
+ PIN(GEN2_I2C_SCL_PT5, I2C2, HDCP, GMI, RSVD4),
+ PIN(GEN2_I2C_SDA_PT6, I2C2, HDCP, GMI, RSVD4),
+ PIN(SDMMC4_CLK_PCC4, INVALID, NAND, GMI, SDMMC4),
+ PIN(SDMMC4_CMD_PT7, I2C3, NAND, GMI, SDMMC4),
+ PIN(SDMMC4_DAT0_PAA0, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT1_PAA1, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT2_PAA2, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT3_PAA3, UARTE, SPI3, GMI, SDMMC4),
+ PIN(SDMMC4_DAT4_PAA4, I2C3, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_DAT5_PAA5, VGP3, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_DAT6_PAA6, VGP4, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_DAT7_PAA7, VGP5, I2S4, GMI, SDMMC4),
+ PIN(SDMMC4_RST_N_PCC3, VGP6, RSVD2, RSVD3, SDMMC4),
+ PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC4),
+ PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC4),
+ PIN(PBB0, I2S4, RSVD2, RSVD3, SDMMC4),
+ PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC4),
+ PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC4),
+ PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, SDMMC4),
+ PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC4),
+ PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
+ PIN(JTAG_RTCK_PU7, RTCK, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PIN(KB_ROW0_PR0, KBC, NAND, RSVD3, RSVD4),
+ PIN(KB_ROW1_PR1, KBC, NAND, RSVD3, RSVD4),
+ PIN(KB_ROW2_PR2, KBC, NAND, RSVD3, RSVD4),
+ PIN(KB_ROW3_PR3, KBC, NAND, RSVD3, INVALID),
+ PIN(KB_ROW4_PR4, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_ROW5_PR5, KBC, NAND, TRACE, OWR),
+ PIN(KB_ROW6_PR6, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW7_PR7, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW8_PS0, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW9_PS1, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW10_PS2, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW11_PS3, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW12_PS4, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW13_PS5, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW14_PS6, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_ROW15_PS7, KBC, NAND, SDMMC2, MIO),
+ PIN(KB_COL0_PQ0, KBC, NAND, TRACE, TEST),
+ PIN(KB_COL1_PQ1, KBC, NAND, TRACE, TEST),
+ PIN(KB_COL2_PQ2, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL3_PQ3, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL4_PQ4, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL5_PQ5, KBC, NAND, TRACE, RSVD4),
+ PIN(KB_COL6_PQ6, KBC, NAND, TRACE, MIO),
+ PIN(KB_COL7_PQ7, KBC, NAND, TRACE, MIO),
+ PIN(CLK_32K_OUT_PA0, BLINK, RSVD2, RSVD3, RSVD4),
+ PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PIN(CORE_PWR_REQ, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PIN(CPU_PWR_REQ, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PIN(PWR_INT_N, PWR_INT_N, RSVD2, RSVD3, RSVD4),
+ PIN(CLK_32K_IN, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
+ PIN(OWR, OWR, CEC, RSVD3, RSVD4),
+ PIN(DAP1_FS_PN0, I2S0, HDA, GMI, SDMMC2),
+ PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, SDMMC2),
+ PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SDMMC2),
+ PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, SDMMC2),
+ PIN(CLK1_REQ_PEE2, DAP, HDA, RSVD3, RSVD4),
+ PIN(CLK1_OUT_PW4, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
+ PIN(SPDIF_IN_PK6, SPDIF, HDA, I2C1, SDMMC2),
+ PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, I2C1, SDMMC2),
+ PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, GMI),
+ PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, GMI),
+ PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, GMI),
+ PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, GMI),
+ PIN(SPI2_MOSI_PX0, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI2_MISO_PX1, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI2_CS0_N_PX3, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI2_SCK_PX2, SPI6, SPI2, SPI3, GMI),
+ PIN(SPI1_MOSI_PX4, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPI1_SCK_PX5, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPI1_CS0_N_PX6, SPI2, SPI1, SPI2_ALT, GMI),
+ PIN(SPI1_MISO_PX7, SPI3, SPI1, SPI2_ALT, RSVD4),
+ PIN(SPI2_CS1_N_PW2, SPI3, SPI2, SPI2_ALT, I2C1),
+ PIN(SPI2_CS2_N_PW3, SPI3, SPI2, SPI2_ALT, I2C1),
+ PIN(SDMMC3_CLK_PA6, UARTA, PWM2, SDMMC3, SPI3),
+ PIN(SDMMC3_CMD_PA7, UARTA, PWM3, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT0_PB7, RSVD1, RSVD2, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT1_PB6, RSVD1, RSVD2, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT2_PB5, RSVD1, PWM1, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT3_PB4, RSVD1, PWM0, SDMMC3, SPI3),
+ PIN(SDMMC3_DAT4_PD1, PWM1, SPI4, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT5_PD0, PWM0, SPI4, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT6_PD3, SPDIF, SPI4, SDMMC3, SPI2),
+ PIN(SDMMC3_DAT7_PD4, SPDIF, SPI4, SDMMC3, SPI2),
+ PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
+ PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
+ PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
};
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *tri = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
-
- reg = readl(tri);
- if (enable)
- reg |= PMUX_TRISTATE_MASK;
- else
- reg &= ~PMUX_TRISTATE_MASK;
- writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pull = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- reg = readl(pull);
- reg &= ~(0x3 << PMUX_PULL_SHIFT);
- reg |= (pupd << PMUX_PULL_SHIFT);
- writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *muxctl = &pmt->pmt_ctl[pin];
- int i, mux = -1;
- u32 reg;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
- if (func & PMUX_FUNC_RSVD1) {
- mux = func & 0x3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- reg = readl(muxctl);
- reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
- reg |= (mux << PMUX_MUXCTL_SHIFT);
- writel(reg, muxctl);
-
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_io = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- reg = readl(pin_io);
- reg &= ~(0x1 << PMUX_IO_SHIFT);
- reg |= (io & 0x1) << PMUX_IO_SHIFT;
- writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_lock = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return 0;
-
- reg = readl(pin_lock);
- reg &= ~(0x1 << PMUX_LOCK_SHIFT);
- if (lock == PMUX_PIN_LOCK_ENABLE)
- reg |= (0x1 << PMUX_LOCK_SHIFT);
- else {
- /* lock == DISABLE, which isn't possible */
- printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
- __func__, lock);
- }
- writel(reg, pin_lock);
-
- return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_od = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return 0;
-
- reg = readl(pin_od);
- reg &= ~(0x1 << PMUX_OD_SHIFT);
- if (od == PMUX_PIN_OD_ENABLE)
- reg |= (0x1 << PMUX_OD_SHIFT);
- writel(reg, pin_od);
-
- return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pin_ioreset = &pmt->pmt_ctl[pin];
- u32 reg;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return 0;
-
- reg = readl(pin_ioreset);
- reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- reg |= (0x1 << PMUX_IO_RESET_SHIFT);
- writel(reg, pin_ioreset);
-
- return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
- enum pmux_pingrp pin = config->pingroup;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
- pinmux_set_io(pin, config->io);
- pinmux_set_lock(pin, config->lock);
- pinmux_set_od(pin, config->od);
- pinmux_set_ioreset(pin, config->ioreset);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
- int slwf)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwf = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwf */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwf));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PGRP_SLWF_NONE)
- return 0;
-
- reg = readl(pad_slwf);
- reg &= ~PGRP_SLWF_MASK;
- reg |= (slwf << PGRP_SLWF_SHIFT);
- writel(reg, pad_slwf);
-
- return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_slwr = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and slwr */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_slw_isvalid(slwr));
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PGRP_SLWR_NONE)
- return 0;
-
- reg = readl(pad_slwr);
- reg &= ~PGRP_SLWR_MASK;
- reg |= (slwr << PGRP_SLWR_SHIFT);
- writel(reg, pad_slwr);
-
- return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvup = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvup */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvup));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PGRP_DRVUP_NONE)
- return 0;
-
- reg = readl(pad_drvup);
- reg &= ~PGRP_DRVUP_MASK;
- reg |= (drvup << PGRP_DRVUP_SHIFT);
- writel(reg, pad_drvup);
-
- return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_drvdn = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check on pad and drvdn */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_drv_isvalid(drvdn));
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PGRP_DRVDN_NONE)
- return 0;
-
- reg = readl(pad_drvdn);
- reg &= ~PGRP_DRVDN_MASK;
- reg |= (drvdn << PGRP_DRVDN_SHIFT);
- writel(reg, pad_drvdn);
-
- return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_lpmd = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad and lpmd value */
- assert(pmux_padgrp_isvalid(pad));
- assert(pmux_pad_lpmd_isvalid(lpmd));
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PGRP_LPMD_NONE)
- return 0;
-
- reg = readl(pad_lpmd);
- reg &= ~PGRP_LPMD_MASK;
- reg |= (lpmd << PGRP_LPMD_SHIFT);
- writel(reg, pad_lpmd);
-
- return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_schmt = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- reg = readl(pad_schmt);
- reg &= ~(1 << PGRP_SCHMT_SHIFT);
- if (schmt == PGRP_SCHMT_ENABLE)
- reg |= (0x1 << PGRP_SCHMT_SHIFT);
- writel(reg, pad_schmt);
-
- return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad,
- enum pgrp_hsm hsm)
-{
- struct pmux_tri_ctlr *pmt =
- (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 *pad_hsm = &pmt->pmt_drive[pad];
- u32 reg;
-
- /* Error check pad */
- assert(pmux_padgrp_isvalid(pad));
-
- reg = readl(pad_hsm);
- reg &= ~(1 << PGRP_HSM_SHIFT);
- if (hsm == PGRP_HSM_ENABLE)
- reg |= (0x1 << PGRP_HSM_SHIFT);
- writel(reg, pad_hsm);
-
- return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
- enum pdrive_pingrp pad = config->padgrp;
-
- padgrp_set_drvup_slwf(pad, config->slwf);
- padgrp_set_drvdn_slwr(pad, config->slwr);
- padgrp_set_drvup(pad, config->drvup);
- padgrp_set_drvdn(pad, config->drvdn);
- padgrp_set_lpmd(pad, config->lpmd);
- padgrp_set_schmt(pad, config->schmt);
- padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- padctrl_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;
tegra30-cardhu.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
+ tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
--- /dev/null
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+ model = "NVIDIA Jetson TK1";
+ compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
+
+ aliases {
+ i2c0 = "/i2c@7000d000";
+ i2c1 = "/i2c@7000c000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ i2c5 = "/i2c@7000d100";
+ sdhci0 = "/sdhci@700b0600";
+ sdhci1 = "/sdhci@700b0400";
+ spi0 = "/spi@7000d400";
+ spi1 = "/spi@7000da00";
+ usb0 = "/usb@7d008000";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d100 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ spi@7000d400 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
+ sdhci@700b0400 {
+ status = "okay";
+ cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+ power-gpios = <&gpio 136 0>; /* gpio PR0 */
+ bus-width = <4>;
+ };
+
+ sdhci@700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ usb@7d008000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+ };
+};
#define dv_maskbits(addr, val) \
writel((readl(addr) & val), addr)
-void da850_waitloop(unsigned long loopcnt);
-int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
void da850_lpc_transition(unsigned char pscnum, unsigned char module,
unsigned char domain, unsigned char state);
-int da850_ddr_setup(void);
void da850_psc_init(void);
void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value);
/*
- * (C) Copyright 2004
+ * (C) Copyright 2004-2014
* Texas Instruments, <www.ti.com>
*
* Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _DAVINCI_I2C_H_
-#define _DAVINCI_I2C_H_
-
-#define I2C_WRITE 0
-#define I2C_READ 1
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
#define I2C_BASE 0x01c22000
#endif
-#define I2C_OA (I2C_BASE + 0x00)
-#define I2C_IE (I2C_BASE + 0x04)
-#define I2C_STAT (I2C_BASE + 0x08)
-#define I2C_SCLL (I2C_BASE + 0x0c)
-#define I2C_SCLH (I2C_BASE + 0x10)
-#define I2C_CNT (I2C_BASE + 0x14)
-#define I2C_DRR (I2C_BASE + 0x18)
-#define I2C_SA (I2C_BASE + 0x1c)
-#define I2C_DXR (I2C_BASE + 0x20)
-#define I2C_CON (I2C_BASE + 0x24)
-#define I2C_IV (I2C_BASE + 0x28)
-#define I2C_PSC (I2C_BASE + 0x30)
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
-#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_BB (1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1 << 9) /* Address as slave */
-#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
-#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
-
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK 7
-#define I2C_INTCODE_NONE 0
-#define I2C_INTCODE_AL 1 /* Arbitration lost */
-#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY 3 /* Register access ready */
-#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
-#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
-#define I2C_INTCODE_SCD 6 /* Stop condition detect */
-
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN (1 << 5) /* I2C module enable */
-#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
-#define I2C_CON_MST (1 << 10) /* Master/slave mode */
-#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
-#define I2C_CON_XA (1 << 8) /* Expand address */
-#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
-#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
-#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
-
-#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
-
#endif
--- /dev/null
+/*
+ * K2HK: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2HK_H
+#define __ASM_ARCH_CLOCK_K2HK_H
+
+#include <asm/arch/hardware.h>
+
+#ifndef __ASSEMBLY__
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ tetris_clk,
+ ddr3a_clk,
+ ddr3b_clk,
+ mcm_clk,
+ pcie_clk,
+ sgmii_srio_clk,
+ xgmii_clk,
+ usb_clk,
+ rp1_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+ core_pll_clk,
+ pass_pll_clk,
+ tetris_pll_clk,
+ ddr3a_pll_clk,
+ ddr3b_pll_clk,
+ sys_clk0_clk,
+ sys_clk0_1_clk,
+ sys_clk0_2_clk,
+ sys_clk0_3_clk,
+ sys_clk0_4_clk,
+ sys_clk0_6_clk,
+ sys_clk0_8_clk,
+ sys_clk0_12_clk,
+ sys_clk0_24_clk,
+ sys_clk1_clk,
+ sys_clk1_3_clk,
+ sys_clk1_4_clk,
+ sys_clk1_6_clk,
+ sys_clk1_12_clk,
+ sys_clk2_clk,
+ sys_clk3_clk
+};
+
+#define K2HK_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ TETRIS_PLL,
+ DDR3A_PLL,
+ DDR3B_PLL,
+};
+#define MAIN_PLL CORE_PLL
+
+/* PLL configuration data */
+struct pll_init_data {
+ int pll;
+ int pll_m; /* PLL Multiplier */
+ int pll_d; /* PLL divider */
+ int pll_od; /* PLL output divider */
+};
+
+#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
+#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
+#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
+#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
+#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
+#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
+#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
+#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
+#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
+#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
+#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
+#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
+#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
+#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
+#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
+#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
+#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
+
+void init_plls(int num_pll, struct pll_init_data *config);
+void init_pll(const struct pll_init_data *data);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * keystone2: common clock header file
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/clock-k2hk.h>
+#endif
+
+#endif
--- /dev/null
+/*
+ * keystone2: common pll clock definitions
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CLOCK_DEFS_H_
+#define _CLOCK_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+#define BIT(x) (1 << (x))
+
+/* PLL Control Registers */
+struct pllctl_regs {
+ u32 ctl; /* 00 */
+ u32 ocsel; /* 04 */
+ u32 secctl; /* 08 */
+ u32 resv0;
+ u32 mult; /* 10 */
+ u32 prediv; /* 14 */
+ u32 div1; /* 18 */
+ u32 div2; /* 1c */
+ u32 div3; /* 20 */
+ u32 oscdiv1; /* 24 */
+ u32 resv1; /* 28 */
+ u32 bpdiv; /* 2c */
+ u32 wakeup; /* 30 */
+ u32 resv2;
+ u32 cmd; /* 38 */
+ u32 stat; /* 3c */
+ u32 alnctl; /* 40 */
+ u32 dchange; /* 44 */
+ u32 cken; /* 48 */
+ u32 ckstat; /* 4c */
+ u32 systat; /* 50 */
+ u32 ckctl; /* 54 */
+ u32 resv3[2];
+ u32 div4; /* 60 */
+ u32 div5; /* 64 */
+ u32 div6; /* 68 */
+ u32 div7; /* 6c */
+ u32 div8; /* 70 */
+ u32 div9; /* 74 */
+ u32 div10; /* 78 */
+ u32 div11; /* 7c */
+ u32 div12; /* 80 */
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+ (struct pllctl_regs *)(CLOCK_BASE + 0x100)
+};
+
+#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val) \
+ pllctl_reg_write(pll, reg, \
+ (pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, mask, 0)
+
+#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
+
+/* PLLCTL Bits */
+#define PLLCTL_BYPASS BIT(23)
+#define PLL_PLLRST BIT(14)
+#define PLLCTL_PAPLL BIT(13)
+#define PLLCTL_CLKMODE BIT(8)
+#define PLLCTL_PLLSELB BIT(7)
+#define PLLCTL_ENSAT BIT(6)
+#define PLLCTL_PLLENSRC BIT(5)
+#define PLLCTL_PLLDIS BIT(4)
+#define PLLCTL_PLLRST BIT(3)
+#define PLLCTL_PLLPWRDN BIT(1)
+#define PLLCTL_PLLEN BIT(0)
+#define PLLSTAT_GO BIT(0)
+
+#define MAIN_ENSAT_OFFSET 6
+
+#define PLLDIV_ENABLE BIT(15)
+
+#define PLL_DIV_MASK 0x3f
+#define PLL_MULT_MASK 0x1fff
+#define PLL_MULT_SHIFT 6
+#define PLLM_MULT_HI_MASK 0x7f
+#define PLLM_MULT_HI_SHIFT 12
+#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
+#define PLLM_MULT_LO_MASK 0x3f
+#define PLL_CLKOD_MASK 0xf
+#define PLL_CLKOD_SHIFT 19
+#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
+#define PLL_BWADJ_LO_MASK 0xff
+#define PLL_BWADJ_LO_SHIFT 24
+#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
+#define PLL_BWADJ_HI_MASK 0xf
+
+#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1)
+#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4)
+#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17)
+
+#endif /* _CLOCK_DEFS_H_ */
--- /dev/null
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EMAC_DEFS_H_
+#define _EMAC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define DEVICE_REG32_R(a) readl(a)
+#define DEVICE_REG32_W(a, v) writel(v, a)
+
+#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
+#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
+#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+#ifdef CONFIG_SOC_K2HK
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
+#endif
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+#define MII_STATUS_LINK_MASK (0x4)
+
+/* Marvell 88E1111 PHY ID */
+#define PHY_MARVELL_88E1111 (0x01410cc0)
+
+#define MDIO_CONTROL_IDLE (0x80000000)
+#define MDIO_CONTROL_ENABLE (0x40000000)
+#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
+#define MDIO_CONTROL_FAULT (0x80000)
+#define MDIO_USERACCESS0_GO (0x80000000)
+#define MDIO_USERACCESS0_WRITE_READ (0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
+#define MDIO_USERACCESS0_ACK (0x20000000)
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
+#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
+#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
+#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+
+struct mac_sl_cfg {
+ u_int32_t max_rx_len; /* Maximum receive packet length. */
+ u_int32_t ctl; /* Control bitfield */
+};
+
+/*
+ * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
+#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
+#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
+#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
+#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
+#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
+#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
+#define GMACSL_ENABLE_GIG_MODE (1 << 7)
+#define GMACSL_TX_ENABLE_PACE (1 << 6)
+#define GMACSL_ENABLE (1 << 5)
+#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
+#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
+#define GMACSL_ENABLE_LOOPBACK (1 << 1)
+#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
+
+/*
+ * DEFINTITION: function return values
+ */
+#define GMACSL_RET_OK 0
+#define GMACSL_RET_INVALID_PORT -1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
+
+/* Register offsets */
+#define CPGMACSL_REG_ID 0x00
+#define CPGMACSL_REG_CTL 0x04
+#define CPGMACSL_REG_STATUS 0x08
+#define CPGMACSL_REG_RESET 0x0c
+#define CPGMACSL_REG_MAXLEN 0x10
+#define CPGMACSL_REG_BOFF 0x14
+#define CPGMACSL_REG_RX_PAUSE 0x18
+#define CPGMACSL_REG_TX_PAURSE 0x1c
+#define CPGMACSL_REG_EM_CTL 0x20
+#define CPGMACSL_REG_PRI 0x24
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
+#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
+
+/* Maxlen register values */
+#define CPGMAC_REG_MAXLEN_LEN 0x3fff
+
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
+#define CPSW_CTL_P0_ENABLE (1 << 2)
+#define CPSW_CTL_VLAN_AWARE (1 << 1)
+#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
+
+#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
+#define DEVICE_CPSW_BASE (0x02090800)
+#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
+#define SWITCH_MAX_PKT_SIZE 9000
+
+/* Register offsets */
+#define CPSW_REG_CTL 0x004
+#define CPSW_REG_STAT_PORT_EN 0x00c
+#define CPSW_REG_MAXLEN 0x040
+#define CPSW_REG_ALE_CONTROL 0x608
+#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
+
+/* Register values */
+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
+
+#define SGMII_REG_STATUS_LOCK BIT(4)
+#define SGMII_REG_STATUS_LINK BIT(0)
+#define SGMII_REG_STATUS_AUTONEG BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG BIT(0)
+#define SGMII_REG_CONTROL_MASTER BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE BIT(0)
+#define SGMII_REG_MR_ADV_LINK BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG 0
+#define SGMII_LINK_MAC_PHY 1
+#define SGMII_LINK_MAC_MAC_FORCED 2
+#define SGMII_LINK_MAC_FIBER 3
+#define SGMII_LINK_MAC_PHY_FORCED 4
+
+#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
+#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
+ KS2_PASS_BASE + 0x00090200, \
+ KS2_PASS_BASE + 0x00090400, \
+ KS2_PASS_BASE + 0x00090500}
+
+#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+
+/*
+ * SGMII registers
+ */
+#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
+
+#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
+#define DEVICE_N_GMACSL_PORTS 4
+#define DEVICE_EMACSL_RESET_POLL_COUNT 100
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
+
+#ifdef CONFIG_SOC_K2HK
+#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
+#endif
+
+#define hw_config_streaming_switch() \
+ DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
+ DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+ dv_reg version;
+ dv_reg control;
+ dv_reg alive;
+ dv_reg link;
+ dv_reg linkintraw;
+ dv_reg linkintmasked;
+ u_int8_t rsvd0[8];
+ dv_reg userintraw;
+ dv_reg userintmasked;
+ dv_reg userintmaskset;
+ dv_reg userintmaskclear;
+ u_int8_t rsvd1[80];
+ dv_reg useraccess0;
+ dv_reg userphysel0;
+ dv_reg useraccess1;
+ dv_reg userphysel1;
+};
+
+/* Ethernet MAC Registers Structure */
+struct emac_regs {
+ dv_reg idver;
+ dv_reg maccontrol;
+ dv_reg macstatus;
+ dv_reg soft_reset;
+ dv_reg rx_maxlen;
+ u32 rsvd0;
+ dv_reg rx_pause;
+ dv_reg tx_pause;
+ dv_reg emcontrol;
+ dv_reg pri_map;
+ u32 rsvd1[6];
+};
+
+#define SGMII_ACCESS(port, reg) \
+ *((volatile unsigned int *)(sgmiis[port] + reg))
+
+struct eth_priv_t {
+ char int_name[32];
+ int rx_flow;
+ int phy_addr;
+ int slave_port;
+ int sgmii_link_type;
+};
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif /* _EMAC_DEFS_H_ */
--- /dev/null
+/*
+ * emif definitions to re-use davinci emif driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EMIF_DEFS_H_
+#define _EMIF_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+struct davinci_emif_regs {
+ uint32_t ercsr;
+ uint32_t awccr;
+ uint32_t sdbcr;
+ uint32_t sdrcr;
+ uint32_t abncr[4];
+ uint32_t sdtimr;
+ uint32_t ddrsr;
+ uint32_t ddrphycr;
+ uint32_t ddrphysr;
+ uint32_t totar;
+ uint32_t totactr;
+ uint32_t ddrphyid_rev;
+ uint32_t sdsretr;
+ uint32_t eirr;
+ uint32_t eimr;
+ uint32_t eimsr;
+ uint32_t eimcr;
+ uint32_t ioctrlr;
+ uint32_t iostatr;
+ uint32_t rsvd0;
+ uint32_t one_nand_cr;
+ uint32_t nandfcr;
+ uint32_t nandfsr;
+ uint32_t rsvd1[2];
+ uint32_t nandfecc[4];
+ uint32_t rsvd2[15];
+ uint32_t nand4biteccload;
+ uint32_t nand4bitecc[4];
+ uint32_t nanderradd1;
+ uint32_t nanderradd2;
+ uint32_t nanderrval1;
+ uint32_t nanderrval2;
+};
+
+#define davinci_emif_regs \
+ ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
+
+#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
+#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
+
+/* Chip Select setup */
+#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
+#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
+#define DAVINCI_ABCR_WSETUP(n) ((n) << 26)
+#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20)
+#define DAVINCI_ABCR_WHOLD(n) ((n) << 17)
+#define DAVINCI_ABCR_RSETUP(n) ((n) << 13)
+#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7)
+#define DAVINCI_ABCR_RHOLD(n) ((n) << 4)
+#define DAVINCI_ABCR_TA(n) ((n) << 2)
+#define DAVINCI_ABCR_ASIZE_16BIT 1
+#define DAVINCI_ABCR_ASIZE_8BIT 0
+
+#endif
--- /dev/null
+/*
+ * K2HK: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_K2HK_H
+#define __ASM_ARCH_HARDWARE_K2HK_H
+
+#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
+#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
+#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
+#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
+#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
+
+#define K2HK_PLL_CNTRL_BASE 0x02310000
+#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
+#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY 0x5a69
+#define KS2_RSTCTRL_MASK 0xffff0000
+#define KS2_RSTCTRL_SWRST 0xfffe0000
+
+#define K2HK_PSC_BASE 0x02350000
+#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
+#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
+#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
+
+#define ARM_PLL_EN BIT(13)
+
+#define K2HK_SPI0_BASE 0x21000400
+#define K2HK_SPI1_BASE 0x21000600
+#define K2HK_SPI2_BASE 0x21000800
+#define K2HK_SPI_BASE K2HK_SPI0_BASE
+
+/* Chip configuration unlock codes and registers */
+#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KEYSTONE_KICK0_MAGIC 0x83e70b13
+#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x02000000
+
+/* PLL control registers */
+#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
+#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+/* Power and Sleep Controller (PSC) Domains */
+#define K2HK_LPSC_MOD 0
+#define K2HK_LPSC_DUMMY1 1
+#define K2HK_LPSC_USB 2
+#define K2HK_LPSC_EMIF25_SPI 3
+#define K2HK_LPSC_TSIP 4
+#define K2HK_LPSC_DEBUGSS_TRC 5
+#define K2HK_LPSC_TETB_TRC 6
+#define K2HK_LPSC_PKTPROC 7
+#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
+#define K2HK_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
+#define K2HK_LPSC_CRYPTO 9
+#define K2HK_LPSC_PCIE 10
+#define K2HK_LPSC_SRIO 11
+#define K2HK_LPSC_VUSR0 12
+#define K2HK_LPSC_CHIP_SRSS 13
+#define K2HK_LPSC_MSMC 14
+#define K2HK_LPSC_GEM_0 15
+#define K2HK_LPSC_GEM_1 16
+#define K2HK_LPSC_GEM_2 17
+#define K2HK_LPSC_GEM_3 18
+#define K2HK_LPSC_GEM_4 19
+#define K2HK_LPSC_GEM_5 20
+#define K2HK_LPSC_GEM_6 21
+#define K2HK_LPSC_GEM_7 22
+#define K2HK_LPSC_EMIF4F_DDR3A 23
+#define K2HK_LPSC_EMIF4F_DDR3B 24
+#define K2HK_LPSC_TAC 25
+#define K2HK_LPSC_RAC 26
+#define K2HK_LPSC_RAC_1 27
+#define K2HK_LPSC_FFTC_A 28
+#define K2HK_LPSC_FFTC_B 29
+#define K2HK_LPSC_FFTC_C 30
+#define K2HK_LPSC_FFTC_D 31
+#define K2HK_LPSC_FFTC_E 32
+#define K2HK_LPSC_FFTC_F 33
+#define K2HK_LPSC_AI2 34
+#define K2HK_LPSC_TCP3D_0 35
+#define K2HK_LPSC_TCP3D_1 36
+#define K2HK_LPSC_TCP3D_2 37
+#define K2HK_LPSC_TCP3D_3 38
+#define K2HK_LPSC_VCP2X4_A 39
+#define K2HK_LPSC_CP2X4_B 40
+#define K2HK_LPSC_VCP2X4_C 41
+#define K2HK_LPSC_VCP2X4_D 42
+#define K2HK_LPSC_VCP2X4_E 43
+#define K2HK_LPSC_VCP2X4_F 44
+#define K2HK_LPSC_VCP2X4_G 45
+#define K2HK_LPSC_VCP2X4_H 46
+#define K2HK_LPSC_BCP 47
+#define K2HK_LPSC_DXB 48
+#define K2HK_LPSC_VUSR1 49
+#define K2HK_LPSC_XGE 50
+#define K2HK_LPSC_ARM_SREFLEX 51
+#define K2HK_LPSC_TETRIS 52
+
+#define K2HK_UART0_BASE 0x02530c00
+
+/* DDR3A definitions */
+#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
+#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
+#define K2HK_DDR3A_DDRPHYC 0x02329000
+/* DDR3B definitions */
+#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
+#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
+#define K2HK_DDR3B_DDRPHYC 0x02328000
+
+/* Queue manager */
+#define DEVICE_QM_MANAGER_BASE 0x02a02000
+#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
+#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
+#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
+#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
+#define DEVICE_QM_NUM_LINKRAMS 2
+#define DEVICE_QM_NUM_MEMREGIONS 20
+
+#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
+#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
+#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
+#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
+
+#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
+#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
+#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
+
+/* MSMC control */
+#define K2HK_MSMC_CTRL_BASE 0x0bc00000
+
+#endif /* __ASM_ARCH_HARDWARE_H */
--- /dev/null
+/*
+ * Keystone2: Common SoC definitions, structures etc.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+
+#define REG(addr) (*(volatile unsigned int *)(addr))
+#define REG_P(addr) ((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int dv_reg;
+typedef volatile unsigned int *dv_reg_p;
+
+#define ASYNC_EMIF_NUM_CS 4
+#define ASYNC_EMIF_MODE_NOR 0
+#define ASYNC_EMIF_MODE_NAND 1
+#define ASYNC_EMIF_MODE_ONENAND 2
+#define ASYNC_EMIF_PRESERVE -1
+
+struct async_emif_config {
+ unsigned mode;
+ unsigned select_strobe;
+ unsigned extend_wait;
+ unsigned wr_setup;
+ unsigned wr_strobe;
+ unsigned wr_hold;
+ unsigned rd_setup;
+ unsigned rd_strobe;
+ unsigned rd_hold;
+ unsigned turn_around;
+ enum {
+ ASYNC_EMIF_8 = 0,
+ ASYNC_EMIF_16 = 1,
+ ASYNC_EMIF_32 = 2,
+ } width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+struct ddr3_phy_config {
+ unsigned int pllcr;
+ unsigned int pgcr1_mask;
+ unsigned int pgcr1_val;
+ unsigned int ptr0;
+ unsigned int ptr1;
+ unsigned int ptr2;
+ unsigned int ptr3;
+ unsigned int ptr4;
+ unsigned int dcr_mask;
+ unsigned int dcr_val;
+ unsigned int dtpr0;
+ unsigned int dtpr1;
+ unsigned int dtpr2;
+ unsigned int mr0;
+ unsigned int mr1;
+ unsigned int mr2;
+ unsigned int dtcr;
+ unsigned int pgcr2;
+ unsigned int zq0cr1;
+ unsigned int zq1cr1;
+ unsigned int zq2cr1;
+ unsigned int pir_v1;
+ unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+ unsigned int sdcfg;
+ unsigned int sdtim1;
+ unsigned int sdtim2;
+ unsigned int sdtim3;
+ unsigned int sdtim4;
+ unsigned int zqcfg;
+ unsigned int sdrfc;
+};
+
+#endif
+
+#define BIT(x) (1 << (x))
+
+#define KS2_DDRPHY_PIR_OFFSET 0x04
+#define KS2_DDRPHY_PGCR0_OFFSET 0x08
+#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
+#define KS2_DDRPHY_PGSR0_OFFSET 0x10
+#define KS2_DDRPHY_PGSR1_OFFSET 0x14
+#define KS2_DDRPHY_PLLCR_OFFSET 0x18
+#define KS2_DDRPHY_PTR0_OFFSET 0x1C
+#define KS2_DDRPHY_PTR1_OFFSET 0x20
+#define KS2_DDRPHY_PTR2_OFFSET 0x24
+#define KS2_DDRPHY_PTR3_OFFSET 0x28
+#define KS2_DDRPHY_PTR4_OFFSET 0x2C
+#define KS2_DDRPHY_DCR_OFFSET 0x44
+
+#define KS2_DDRPHY_DTPR0_OFFSET 0x48
+#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
+#define KS2_DDRPHY_DTPR2_OFFSET 0x50
+
+#define KS2_DDRPHY_MR0_OFFSET 0x54
+#define KS2_DDRPHY_MR1_OFFSET 0x58
+#define KS2_DDRPHY_MR2_OFFSET 0x5C
+#define KS2_DDRPHY_DTCR_OFFSET 0x68
+#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
+
+#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
+#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
+#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
+#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
+
+#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
+
+#define IODDRM_MASK 0x00000180
+#define ZCKSEL_MASK 0x01800000
+#define CL_MASK 0x00000072
+#define WR_MASK 0x00000E00
+#define BL_MASK 0x00000003
+#define RRMODE_MASK 0x00040000
+#define UDIMM_MASK 0x20000000
+#define BYTEMASK_MASK 0x0003FC00
+#define MPRDQ_MASK 0x00000080
+#define PDQ_MASK 0x00000070
+#define NOSRA_MASK 0x08000000
+#define ECC_MASK 0x00000001
+
+#define KS2_DDR3_MIDR_OFFSET 0x00
+#define KS2_DDR3_STATUS_OFFSET 0x04
+#define KS2_DDR3_SDCFG_OFFSET 0x08
+#define KS2_DDR3_SDRFC_OFFSET 0x10
+#define KS2_DDR3_SDTIM1_OFFSET 0x18
+#define KS2_DDR3_SDTIM2_OFFSET 0x1C
+#define KS2_DDR3_SDTIM3_OFFSET 0x20
+#define KS2_DDR3_SDTIM4_OFFSET 0x28
+#define KS2_DDR3_PMCTL_OFFSET 0x38
+#define KS2_DDR3_ZQCFG_OFFSET 0xC8
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/hardware-k2hk.h>
+#endif
+
+#ifndef __ASSEMBLY__
+static inline int cpu_is_k2hk(void)
+{
+ unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb981) ? 1 : 0;
+}
+
+static inline int cpu_revision(void)
+{
+ unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int rev = (jtag_id >> 28) & 0xf;
+
+ return rev;
+}
+
+void share_all_segments(int priv_id);
+int cpu_to_bus(u32 *ptr, u32 length);
+void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+void init_ddr3(void);
+void sdelay(unsigned long);
+
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
--- /dev/null
+/*
+ * keystone: i2c driver definitions
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
+
+#define I2C0_BASE 0x02530000
+#define I2C1_BASE 0x02530400
+#define I2C2_BASE 0x02530800
+#define I2C_BASE I2C0_BASE
+
+#endif
--- /dev/null
+/*
+ * Multicore Navigator definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NAV_H_
+#define _KEYSTONE_NAV_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+enum soc_type_t {
+ k2hk
+};
+
+#define QM_OK 0
+#define QM_ERR -1
+#define QM_DESC_TYPE_HOST 0
+#define QM_DESC_PSINFO_IN_DESCR 0
+#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \
+ (QM_DESC_PSINFO_IN_DESCR << 22)
+
+/* Packet Info */
+#define QM_DESC_PINFO_EPIB 1
+#define QM_DESC_PINFO_RETURN_OWN 1
+#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \
+ (QM_DESC_PINFO_RETURN_OWN << 15)
+
+struct qm_cfg_reg {
+ u32 revision;
+ u32 __pad1;
+ u32 divert;
+ u32 link_ram_base0;
+ u32 link_ram_size0;
+ u32 link_ram_base1;
+ u32 link_ram_size1;
+ u32 link_ram_base2;
+ u32 starvation[0];
+};
+
+struct descr_mem_setup_reg {
+ u32 base_addr;
+ u32 start_idx;
+ u32 desc_reg_size;
+ u32 _res0;
+};
+
+struct qm_reg_queue {
+ u32 entry_count;
+ u32 byte_count;
+ u32 packet_size;
+ u32 ptr_size_thresh;
+};
+
+struct qm_config {
+ /* QM module addresses */
+ u32 stat_cfg; /* status and config */
+ struct qm_reg_queue *queue; /* management region */
+ u32 mngr_vbusm; /* management region (VBUSM) */
+ u32 i_lram; /* internal linking RAM */
+ struct qm_reg_queue *proxy;
+ u32 status_ram;
+ struct qm_cfg_reg *mngr_cfg;
+ /* Queue manager config region */
+ u32 intd_cfg; /* QMSS INTD config region */
+ struct descr_mem_setup_reg *desc_mem;
+ /* descritor memory setup region*/
+ u32 region_num;
+ u32 pdsp_cmd; /* PDSP1 command interface */
+ u32 pdsp_ctl; /* PDSP1 control registers */
+ u32 pdsp_iram;
+ /* QM configuration parameters */
+
+ u32 qpool_num; /* */
+};
+
+struct qm_host_desc {
+ u32 desc_info;
+ u32 tag_info;
+ u32 packet_info;
+ u32 buff_len;
+ u32 buff_ptr;
+ u32 next_bdptr;
+ u32 orig_buff_len;
+ u32 orig_buff_ptr;
+ u32 timestamp;
+ u32 swinfo[3];
+ u32 ps_data[20];
+};
+
+#define HDESC_NUM 256
+
+int qm_init(void);
+void qm_close(void);
+void qm_push(struct qm_host_desc *hd, u32 qnum);
+struct qm_host_desc *qm_pop(u32 qnum);
+
+void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+ void *buff_ptr, u32 buff_len);
+
+struct qm_host_desc *qm_pop_from_free_pool(void);
+void queue_close(u32 qnum);
+
+/*
+ * DMA API
+ */
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
+ psloc, sopoff, qmgr, qnum) \
+ (((einfo & 1) << 30) | \
+ ((psinfo & 1) << 29) | \
+ ((rxerr & 1) << 28) | \
+ ((desc & 3) << 26) | \
+ ((psloc & 1) << 25) | \
+ ((sopoff & 0x1ff) << 16) | \
+ ((qmgr & 3) << 12) | \
+ ((qnum & 0xfff) << 0))
+
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
+ (((fd0qm & 3) << 28) | \
+ ((fd0qnum & 0xfff) << 16) | \
+ ((fd1qm & 3) << 12) | \
+ ((fd1qnum & 0xfff) << 0))
+
+#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
+#define CPDMA_CHAN_A_TDOWN (1 << 30)
+#define TDOWN_TIMEOUT_COUNT 100
+
+struct global_ctl_regs {
+ u32 revision;
+ u32 perf_control;
+ u32 emulation_control;
+ u32 priority_control;
+ u32 qm_base_addr[4];
+};
+
+struct tx_chan_regs {
+ u32 cfg_a;
+ u32 cfg_b;
+ u32 res[6];
+};
+
+struct rx_chan_regs {
+ u32 cfg_a;
+ u32 res[7];
+};
+
+struct rx_flow_regs {
+ u32 control;
+ u32 tags;
+ u32 tag_sel;
+ u32 fdq_sel[2];
+ u32 thresh[3];
+};
+
+struct pktdma_cfg {
+ struct global_ctl_regs *global;
+ struct tx_chan_regs *tx_ch;
+ u32 tx_ch_num;
+ struct rx_chan_regs *rx_ch;
+ u32 rx_ch_num;
+ u32 *tx_sched;
+ struct rx_flow_regs *rx_flows;
+ u32 rx_flow_num;
+
+ u32 rx_free_q;
+ u32 rx_rcv_q;
+ u32 tx_snd_q;
+
+ u32 rx_flow; /* flow that is used for RX */
+};
+
+/*
+ * packet dma user allocates memory for rx buffers
+ * and describe it in the following structure
+ */
+struct rx_buff_desc {
+ u8 *buff_ptr;
+ u32 num_buffs;
+ u32 buff_len;
+ u32 rx_flow;
+};
+
+int netcp_close(void);
+int netcp_init(struct rx_buff_desc *rx_buffers);
+int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
+void *netcp_recv(u32 **pkt, int *num_bytes);
+void netcp_release_rxhd(void *hd);
+
+#endif /* _KEYSTONE_NAV_H_ */
--- /dev/null
+/*
+ * nand driver definitions to re-use davinci nand driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <linux/mtd/nand.h>
+
+#define MASK_CLE 0x4000
+#define MASK_ALE 0x2000
+
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _PSC_DEFS_H_
+#define _PSC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+/*
+ * FILE PURPOSE: Local Power Sleep Controller definitions
+ *
+ * FILE NAME: psc_defs.h
+ *
+ * DESCRIPTION: Provides local definitions for the power saver controller
+ *
+ */
+
+/* Register offsets */
+#define PSC_REG_PTCMD 0x120
+#define PSC_REG_PSTAT 0x128
+#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x)))
+#define PSC_REG_PDCTL(x) (0x300 + (4 * (x)))
+#define PSC_REG_MDCFG(x) (0x600 + (4 * (x)))
+#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
+#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
+
+#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
+ (u32)1)) << ((u32)y)))
+
+#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y)
+#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \
+ ((((u32)f) << (y)) & BOOTBITMASK(x, y))
+
+/* PDCTL */
+#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0)
+#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12)
+
+/* PDSTAT */
+#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0)
+
+/* MDCFG */
+#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16)
+#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14)
+
+/* MDCTL */
+#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0)
+#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8)
+#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \
+ 12, 12)
+
+/* MDSTAT */
+#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0)
+#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
+
+/* PDCTL states */
+#define PSC_REG_VAL_PDCTL_NEXT_ON 1
+#define PSC_REG_VAL_PDCTL_NEXT_OFF 0
+
+#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0
+
+/* MDCTL states */
+#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0
+#define PSC_REG_VAL_MDCTL_NEXT_OFF 2
+#define PSC_REG_VAL_MDCTL_NEXT_ON 3
+
+/* MDSTAT states */
+#define PSC_REG_VAL_MDSTAT_STATE_ON 3
+#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
+#define PSC_REG_VAL_MDSTAT_STATE_OFF 2
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22
+
+/*
+ * Timeout limit on checking PTSTAT. This is the number of times the
+ * wait function will be called before giving up.
+ */
+#define PSC_PTSTAT_TIMEOUT_LIMIT 100
+
+u32 psc_get_domain_num(u32 mod_num);
+int psc_enable_module(u32 mod_num);
+int psc_disable_module(u32 mod_num);
+int psc_disable_domain(u32 domain_num);
+
+#endif /* _PSC_DEFS_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_SPL_H_
+
+#define BOOT_DEVICE_SPI 2
+
+#endif
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <linux/mtd/omap_gpmc.h>
+#include <asm/omap_common.h>
typedef struct {
u32 mtype;
void try_unlock_memory(void);
u32 get_boot_type(void);
void invalidate_dcache(u32);
-void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
void omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void dieid_num_r(void);
+void get_dieid(u32 *id);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
u32 warm_reset(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void setup_clocks_for_console(void);
struct apb_misc_pp_ctlr {
u32 reserved0[2];
u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+ u32 reserved1[6]; /* 0x0c .. 0x20 */
+ u32 cfg_ctl; /* 0x24 */
};
/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
* an empty stub function will be called.
*/
+void pinmux_init(void); /* overrideable general pinmux setup */
void pin_mux_usb(void); /* overrideable USB pinmux setup */
void pin_mux_spi(void); /* overrideable SPI pinmux setup */
void pin_mux_nand(void); /* overrideable NAND pinmux setup */
--- /dev/null
+/*
+ * (C) Copyright 2010-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA_PINMUX_H_
+#define _TEGRA_PINMUX_H_
+
+#include <asm/arch/tegra.h>
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+ PMUX_PIN_NONE,
+};
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+enum pmux_pin_rcv_sel {
+ PMUX_PIN_RCV_SEL_DEFAULT = 0,
+ PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_HIGH,
+};
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pmux_pingrp_config {
+ u32 pingrp:16; /* pin group PMUX_PINGRP_... */
+ u32 func:8; /* function to assign PMUX_FUNC_... */
+ u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
+ u32 tristate:2; /* tristate or normal PMUX_TRI_... */
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+ u32 io:2; /* input or output PMUX_PIN_... */
+ u32 lock:2; /* lock enable/disable PMUX_PIN... */
+ u32 od:2; /* open-drain or push-pull driver */
+ u32 ioreset:2; /* input/output reset PMUX_PIN... */
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+ u32 rcv_sel:2; /* select between High and Normal */
+ /* VIL/VIH receivers */
+#endif
+#endif
+};
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+#endif
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+ int len);
+
+#ifdef TEGRA_PMX_HAS_DRVGRPS
+
+#define PMUX_SLWF_MIN 0
+#define PMUX_SLWF_MAX 3
+#define PMUX_SLWF_NONE -1
+
+#define PMUX_SLWR_MIN 0
+#define PMUX_SLWR_MAX 3
+#define PMUX_SLWR_NONE -1
+
+#define PMUX_DRVUP_MIN 0
+#define PMUX_DRVUP_MAX 127
+#define PMUX_DRVUP_NONE -1
+
+#define PMUX_DRVDN_MIN 0
+#define PMUX_DRVDN_MAX 127
+#define PMUX_DRVDN_NONE -1
+
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+ PMUX_LPMD_X8 = 0,
+ PMUX_LPMD_X4,
+ PMUX_LPMD_X2,
+ PMUX_LPMD_X,
+ PMUX_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+ PMUX_SCHMT_DISABLE = 0,
+ PMUX_SCHMT_ENABLE = 1,
+ PMUX_SCHMT_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+ PMUX_HSM_DISABLE = 0,
+ PMUX_HSM_ENABLE = 1,
+ PMUX_HSM_NONE = -1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct pmux_drvgrp_config {
+ u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */
+ u32 slwf:3; /* falling edge slew */
+ u32 slwr:3; /* rising edge slew */
+ u32 drvup:8; /* pull-up drive strength */
+ u32 drvdn:8; /* pull-down drive strength */
+ u32 lpmd:3; /* low-power mode selection */
+ u32 schmt:2; /* schmidt enable */
+ u32 hsm:2; /* high-speed mode enable */
+};
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+ int len);
+
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
+
+struct pmux_pingrp_desc {
+ u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+ u8 ctl_id;
+ u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
+#endif /* _TEGRA_PINMUX_H_ */
#ifndef _TEGRA_USB_H_
#define _TEGRA_USB_H_
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+ /* 0x000 */
+ uint id;
+ uint reserved0;
+ uint host;
+ uint device;
+
+ /* 0x010 */
+ uint txbuf;
+ uint rxbuf;
+ uint reserved1[2];
+
+ /* 0x020 */
+ uint reserved2[56];
+
+ /* 0x100 */
+ u16 cap_length;
+ u16 hci_version;
+ uint hcs_params;
+ uint hcc_params;
+ uint reserved3[5];
+
+ /* 0x120 */
+ uint dci_version;
+ uint dcc_params;
+ uint reserved4[2];
+
+#ifdef CONFIG_TEGRA20
+ /* 0x130 */
+ uint reserved4_2[4];
+
+ /* 0x140 */
+ uint usb_cmd;
+ uint usb_sts;
+ uint usb_intr;
+ uint frindex;
+
+ /* 0x150 */
+ uint reserved5;
+ uint periodic_list_base;
+ uint async_list_addr;
+ uint async_tt_sts;
+
+ /* 0x160 */
+ uint burst_size;
+ uint tx_fill_tuning;
+ uint reserved6; /* is this port_sc1 on some controllers? */
+ uint icusb_ctrl;
+
+ /* 0x170 */
+ uint ulpi_viewport;
+ uint reserved7;
+ uint endpt_nak;
+ uint endpt_nak_enable;
+
+ /* 0x180 */
+ uint reserved;
+ uint port_sc1;
+ uint reserved8[6];
+
+ /* 0x1a0 */
+ uint reserved9;
+ uint otgsc;
+ uint usb_mode;
+ uint endpt_setup_stat;
+
+ /* 0x1b0 */
+ uint reserved10[20];
+
+ /* 0x200 */
+ uint reserved11[0x80];
+#else
+ /* 0x130 */
+ uint usb_cmd;
+ uint usb_sts;
+ uint usb_intr;
+ uint frindex;
+
+ /* 0x140 */
+ uint reserved5;
+ uint periodic_list_base;
+ uint async_list_addr;
+ uint reserved5_1;
+
+ /* 0x150 */
+ uint burst_size;
+ uint tx_fill_tuning;
+ uint reserved6;
+ uint icusb_ctrl;
+
+ /* 0x160 */
+ uint ulpi_viewport;
+ uint reserved7[3];
+
+ /* 0x170 */
+ uint reserved;
+ uint port_sc1;
+ uint reserved8[6];
+
+ /* 0x190 */
+ uint reserved9[8];
+
+ /* 0x1b0 */
+ uint reserved10;
+ uint hostpc1_devlc;
+ uint reserved10_1[2];
+
+ /* 0x1c0 */
+ uint reserved10_2[4];
+
+ /* 0x1d0 */
+ uint reserved10_3[4];
+
+ /* 0x1e0 */
+ uint reserved10_4[4];
+
+ /* 0x1f0 */
+ uint reserved10_5;
+ uint otgsc;
+ uint usb_mode;
+ uint reserved10_6;
+
+ /* 0x200 */
+ uint endpt_nak;
+ uint endpt_nak_enable;
+ uint endpt_setup_stat;
+ uint reserved11_1[0x7D];
+#endif
+
+ /* 0x400 */
+ uint susp_ctrl;
+ uint phy_vbus_sensors;
+ uint phy_vbus_wakeup_id;
+ uint phy_alt_vbus_sys;
+
+#ifdef CONFIG_TEGRA20
+ /* 0x410 */
+ uint usb1_legacy_ctrl;
+ uint reserved12[4];
+
+ /* 0x424 */
+ uint ulpi_timing_ctrl_0;
+ uint ulpi_timing_ctrl_1;
+ uint reserved13[53];
+#else
+
+ /* 0x410 */
+ uint usb1_legacy_ctrl;
+ uint reserved12[3];
+
+ /* 0x420 */
+ uint reserved13[56];
+#endif
+
+ /* 0x500 */
+ uint reserved14[64 * 3];
+
+ /* 0x800 */
+ uint utmip_pll_cfg0;
+ uint utmip_pll_cfg1;
+ uint utmip_xcvr_cfg0;
+ uint utmip_bias_cfg0;
+
+ /* 0x810 */
+ uint utmip_hsrx_cfg0;
+ uint utmip_hsrx_cfg1;
+ uint utmip_fslsrx_cfg0;
+ uint utmip_fslsrx_cfg1;
+
+ /* 0x820 */
+ uint utmip_tx_cfg0;
+ uint utmip_misc_cfg0;
+ uint utmip_misc_cfg1;
+ uint utmip_debounce_cfg0;
+
+ /* 0x830 */
+ uint utmip_bat_chrg_cfg0;
+ uint utmip_spare_cfg0;
+ uint utmip_xcvr_cfg1;
+ uint utmip_bias_cfg1;
+};
+
/* USB1_LEGACY_CTRL */
#define USB1_NO_LEGACY_MODE 1
#define USB_PHY_CLK_VALID (1 << 7)
#define USB_SUSP_CLR (1 << 5)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
/* USB2_IF_USB_SUSP_CTRL_0 */
#define ULPI_PHY_ENB (1 << 13)
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
+#endif
+
/* USBx_UTMIP_MISC_CFG0 */
#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
+
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
#define UTMIP_PLLU_STABLE_COUNT_MASK \
(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
-#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
/* USBx_UTMIP_PLL_CFG1_0 */
+/* Tegra 3 and later: Moved to Clock and Reset register space */
#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
#define IC_ENB1 (1 << 3)
-/* PORTSC1, USB1, defined for Tegra20 */
+#ifdef CONFIG_TEGRA20
+/* PORTSC1, USB1 */
#define PTS1_SHIFT 31
#define PTS1_MASK (1 << PTS1_SHIFT)
#define STS1 (1 << 30)
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT 30
+#define PTS_MASK (3U << PTS_SHIFT)
+#define STS (1 << 29)
+#else
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT 29
+#define PTS_MASK (0x7U << PTS_SHIFT)
+#define STS (1 << 28)
+#endif
+
#define PTS_UTMI 0
#define PTS_RESERVED 1
#define PTS_ULPI 2
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA114_PINMUX_H_
#define _TEGRA114_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
- PINGRP_CLK2_REQ,
- PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- PINGRP_GMI_WP_N,
- PINGRP_GMI_IORDY,
- PINGRP_GMI_WAIT,
- PINGRP_GMI_ADV_N,
- PINGRP_GMI_CLK,
- PINGRP_GMI_CS0_N,
- PINGRP_GMI_CS1_N,
- PINGRP_GMI_CS2_N,
- PINGRP_GMI_CS3_N,
- PINGRP_GMI_CS4_N,
- PINGRP_GMI_CS6_N,
- PINGRP_GMI_CS7_N,
- PINGRP_GMI_AD0,
- PINGRP_GMI_AD1,
- PINGRP_GMI_AD2,
- PINGRP_GMI_AD3,
- PINGRP_GMI_AD4,
- PINGRP_GMI_AD5,
- PINGRP_GMI_AD6,
- PINGRP_GMI_AD7,
- PINGRP_GMI_AD8,
- PINGRP_GMI_AD9,
- PINGRP_GMI_AD10,
- PINGRP_GMI_AD11,
- PINGRP_GMI_AD12,
- PINGRP_GMI_AD13,
- PINGRP_GMI_AD14,
- PINGRP_GMI_AD15,
- PINGRP_GMI_A16,
- PINGRP_GMI_A17,
- PINGRP_GMI_A18,
- PINGRP_GMI_A19,
- PINGRP_GMI_WR_N,
- PINGRP_GMI_OE_N,
- PINGRP_GMI_DQS,
- PINGRP_GMI_RST_N,
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_SYS_CLK_REQ,
- PINGRP_CORE_PWR_REQ,
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_DVFS_PWM,
- PINGRP_GPIO_X1_AUD,
- PINGRP_GPIO_X3_AUD,
- PINGRP_DVFS_CLK,
- PINGRP_GPIO_X4_AUD,
- PINGRP_GPIO_X5_AUD,
- PINGRP_GPIO_X6_AUD,
- PINGRP_GPIO_X7_AUD,
- PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
- PINGRP_SDMMC1_WP_N,
- PINGRP_SDMMC3_CD_N,
- PINGRP_GPIO_W2_AUD,
- PINGRP_GPIO_W3_AUD,
- PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
- PINGRP_USB_VBUS_EN1,
- PINGRP_SDMMC3_CLK_LB_IN,
- PINGRP_SDMMC3_CLK_LB_OUT,
- PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
- PINGRP_COUNT,
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_GMI_WP_N_PC7,
+ PMUX_PINGRP_GMI_IORDY_PI5,
+ PMUX_PINGRP_GMI_WAIT_PI7,
+ PMUX_PINGRP_GMI_ADV_N_PK0,
+ PMUX_PINGRP_GMI_CLK_PK1,
+ PMUX_PINGRP_GMI_CS0_N_PJ0,
+ PMUX_PINGRP_GMI_CS1_N_PJ2,
+ PMUX_PINGRP_GMI_CS2_N_PK3,
+ PMUX_PINGRP_GMI_CS3_N_PK4,
+ PMUX_PINGRP_GMI_CS4_N_PK2,
+ PMUX_PINGRP_GMI_CS6_N_PI3,
+ PMUX_PINGRP_GMI_CS7_N_PI6,
+ PMUX_PINGRP_GMI_AD0_PG0,
+ PMUX_PINGRP_GMI_AD1_PG1,
+ PMUX_PINGRP_GMI_AD2_PG2,
+ PMUX_PINGRP_GMI_AD3_PG3,
+ PMUX_PINGRP_GMI_AD4_PG4,
+ PMUX_PINGRP_GMI_AD5_PG5,
+ PMUX_PINGRP_GMI_AD6_PG6,
+ PMUX_PINGRP_GMI_AD7_PG7,
+ PMUX_PINGRP_GMI_AD8_PH0,
+ PMUX_PINGRP_GMI_AD9_PH1,
+ PMUX_PINGRP_GMI_AD10_PH2,
+ PMUX_PINGRP_GMI_AD11_PH3,
+ PMUX_PINGRP_GMI_AD12_PH4,
+ PMUX_PINGRP_GMI_AD13_PH5,
+ PMUX_PINGRP_GMI_AD14_PH6,
+ PMUX_PINGRP_GMI_AD15_PH7,
+ PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_PINGRP_GMI_WR_N_PI0,
+ PMUX_PINGRP_GMI_OE_N_PI1,
+ PMUX_PINGRP_GMI_DQS_P_PJ3,
+ PMUX_PINGRP_GMI_RST_N_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+ PMUX_PINGRP_CORE_PWR_REQ,
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_CLK1_REQ_PEE2,
+ PMUX_PINGRP_CLK1_OUT_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_DVFS_PWM_PX0,
+ PMUX_PINGRP_GPIO_X1_AUD_PX1,
+ PMUX_PINGRP_GPIO_X3_AUD_PX3,
+ PMUX_PINGRP_DVFS_CLK_PX2,
+ PMUX_PINGRP_GPIO_X4_AUD_PX4,
+ PMUX_PINGRP_GPIO_X5_AUD_PX5,
+ PMUX_PINGRP_GPIO_X6_AUD_PX6,
+ PMUX_PINGRP_GPIO_X7_AUD_PX7,
+ PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+ PMUX_PINGRP_SDMMC1_WP_N_PV3,
+ PMUX_PINGRP_SDMMC3_CD_N_PV2,
+ PMUX_PINGRP_GPIO_W2_AUD_PW2,
+ PMUX_PINGRP_GPIO_W3_AUD_PW3,
+ PMUX_PINGRP_USB_VBUS_EN0_PN4,
+ PMUX_PINGRP_USB_VBUS_EN1_PN5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+ PMUX_PINGRP_GMI_CLK_LB,
+ PMUX_PINGRP_RESET_OUT_N,
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
- PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
- PDRIVE_PINGROUP_DAP5,
- PDRIVE_PINGROUP_VBUS,
- PDRIVE_PINGROUP_AO3,
- PDRIVE_PINGROUP_HVC,
- PDRIVE_PINGROUP_SDIO4,
- PDRIVE_PINGROUP_AO0,
- PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_DAP1 = (0x28 / 4),
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_DDC = (0x94 / 4),
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GME = (0xa8 / 4),
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_DEV3 = (0xc4 / 4),
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_AT6 = (0x12c / 4),
+ PMUX_DRVGRP_DAP5,
+ PMUX_DRVGRP_USB_VBUS_EN,
+ PMUX_DRVGRP_AO3,
+ PMUX_DRVGRP_HV0,
+ PMUX_DRVGRP_SDIO4,
+ PMUX_DRVGRP_AO0,
+ PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
- PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
- PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
- PMUX_FUNC_HDMI,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
- PMUX_FUNC_KBC,
- PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
- PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
- PMUX_FUNC_OWR,
- PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
- PMUX_FUNC_RTCK,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC2,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI2_ALT,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_UARTE,
- PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- /* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
+ PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYA_ALT,
+ PMUX_FUNC_DISPLAYB,
PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
+ PMUX_FUNC_IRDA,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_NAND,
PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
- PMUX_FUNC_SATA,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_RESET_OUT_N,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- /* End of Tegra3 MUX selectors */
- PMUX_FUNC_USB,
- PMUX_FUNC_SOC,
- PMUX_FUNC_CPU,
- PMUX_FUNC_CLK,
- PMUX_FUNC_PWRON,
- PMUX_FUNC_PMI,
- PMUX_FUNC_CLDVFS,
- PMUX_FUNC_RESET_OUT_N,
- /* End of Tegra114 MUX selectors */
-
- PMUX_FUNC_SAFE,
- PMUX_FUNC_MAX,
-
- PMUX_FUNC_INVALID = 0x4000,
- PMUX_FUNC_RSVD1 = 0x8000,
- PMUX_FUNC_RSVD2 = 0x8001,
- PMUX_FUNC_RSVD3 = 0x8002,
- PMUX_FUNC_RSVD4 = 0x8003,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
- || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
- && ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
- PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
- PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE -1
-#define PGRP_HSM_NONE PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
- (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
- (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
- (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* t114 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
- enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
- /* VIL/VIH receivers */
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_RSVD1,
+ PMUX_FUNC_RSVD2,
+ PMUX_FUNC_RSVD3,
+ PMUX_FUNC_RSVD4,
+ PMUX_FUNC_COUNT,
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
-#endif /* _TEGRA114_PINMUX_H_ */
+#endif /* _TEGRA114_PINMUX_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA114_USB_H_
-#define _TEGRA114_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[2];
-
- /* 0x130 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x140 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint reserved5_1;
-
- /* 0x150 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6;
- uint icusb_ctrl;
-
- /* 0x160 */
- uint ulpi_viewport;
- uint reserved7[3];
-
- /* 0x170 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x190 */
- uint reserved9[8];
-
- /* 0x1b0 */
- uint reserved10;
- uint hostpc1_devlc;
- uint reserved10_1[2];
-
- /* 0x1c0 */
- uint reserved10_2[4];
-
- /* 0x1d0 */
- uint reserved10_3[4];
-
- /* 0x1e0 */
- uint reserved10_4[4];
-
- /* 0x1f0 */
- uint reserved10_5;
- uint otgsc;
- uint usb_mode;
- uint reserved10_6;
-
- /* 0x200 */
- uint endpt_nak;
- uint endpt_nak_enable;
- uint endpt_setup_stat;
- uint reserved11_1[0x7D];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[3];
-
- /* 0x420 */
- uint reserved13[56];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB2D_HOSTPC1_DEVLC_0 */
-#define PTS_SHIFT 29
-#define PTS_MASK (0x7U << PTS_SHIFT)
-
-#define STS (1 << 28)
-#endif /* _TEGRA114_USB_H_ */
/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA124_PINMUX_H_
#define _TEGRA124_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
- PINGRP_CLK2_REQ,
- PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
- PINGRP_GPIO_PC7, /* offset 0x31c0 */
- PINGRP_GPIO_PI5,
- PINGRP_GPIO_PI7,
- PINGRP_GPIO_PK0,
- PINGRP_GPIO_PK1,
- PINGRP_GPIO_PJ0,
- PINGRP_GPIO_PJ2,
- PINGRP_GPIO_PK3,
- PINGRP_GPIO_PK4,
- PINGRP_GPIO_PK2,
- PINGRP_GPIO_PI3,
- PINGRP_GPIO_PI6,
- PINGRP_GPIO_PG0,
- PINGRP_GPIO_PG1,
- PINGRP_GPIO_PG2,
- PINGRP_GPIO_PG3,
- PINGRP_GPIO_PG4,
- PINGRP_GPIO_PG5,
- PINGRP_GPIO_PG6,
- PINGRP_GPIO_PG7,
- PINGRP_GPIO_PH0,
- PINGRP_GPIO_PH1,
- PINGRP_GPIO_PH2,
- PINGRP_GPIO_PH3,
- PINGRP_GPIO_PH4,
- PINGRP_GPIO_PH5,
- PINGRP_GPIO_PH6,
- PINGRP_GPIO_PH7,
- PINGRP_GPIO_PJ7,
- PINGRP_GPIO_PB0,
- PINGRP_GPIO_PB1,
- PINGRP_GPIO_PK7,
- PINGRP_GPIO_PI0,
- PINGRP_GPIO_PI1,
- PINGRP_GPIO_PI2,
- PINGRP_GPIO_PI4, /* offset 0x324c */
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_ROW11,
- PINGRP_KB_ROW12,
- PINGRP_KB_ROW13,
- PINGRP_KB_ROW14,
- PINGRP_KB_ROW15,
- PINGRP_KB_COL0, /* offset 0x32fc */
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_DVFS_PWM,
- PINGRP_GPIO_X1_AUD,
- PINGRP_GPIO_X3_AUD,
- PINGRP_DVFS_CLK,
- PINGRP_GPIO_X4_AUD,
- PINGRP_GPIO_X5_AUD,
- PINGRP_GPIO_X6_AUD,
- PINGRP_GPIO_X7_AUD,
- PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
- PINGRP_PEX_L0_CLKREQ,
- PINGRP_PEX_WAKE,
- PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
- PINGRP_PEX_L1_CLKREQ,
- PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
- PINGRP_SDMMC1_WP_N,
- PINGRP_SDMMC3_CD_N,
- PINGRP_GPIO_W2_AUD,
- PINGRP_GPIO_W3_AUD,
- PINGRP_USB_VBUS_EN0,
- PINGRP_USB_VBUS_EN1,
- PINGRP_SDMMC3_CLK_LB_IN,
- PINGRP_SDMMC3_CLK_LB_OUT,
- PINGRP_GMI_CLK_LB,
- PINGRP_RESET_OUT_N,
- PINGRP_KB_ROW16, /* offset 0x340c */
- PINGRP_KB_ROW17,
- PINGRP_USB_VBUS_EN2,
- PINGRP_GPIO_PFF2,
- PINGRP_DP_HPD, /* last reg offset = 0x3430 */
- PINGRP_COUNT,
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_PC7,
+ PMUX_PINGRP_PI5,
+ PMUX_PINGRP_PI7,
+ PMUX_PINGRP_PK0,
+ PMUX_PINGRP_PK1,
+ PMUX_PINGRP_PJ0,
+ PMUX_PINGRP_PJ2,
+ PMUX_PINGRP_PK3,
+ PMUX_PINGRP_PK4,
+ PMUX_PINGRP_PK2,
+ PMUX_PINGRP_PI3,
+ PMUX_PINGRP_PI6,
+ PMUX_PINGRP_PG0,
+ PMUX_PINGRP_PG1,
+ PMUX_PINGRP_PG2,
+ PMUX_PINGRP_PG3,
+ PMUX_PINGRP_PG4,
+ PMUX_PINGRP_PG5,
+ PMUX_PINGRP_PG6,
+ PMUX_PINGRP_PG7,
+ PMUX_PINGRP_PH0,
+ PMUX_PINGRP_PH1,
+ PMUX_PINGRP_PH2,
+ PMUX_PINGRP_PH3,
+ PMUX_PINGRP_PH4,
+ PMUX_PINGRP_PH5,
+ PMUX_PINGRP_PH6,
+ PMUX_PINGRP_PH7,
+ PMUX_PINGRP_PJ7,
+ PMUX_PINGRP_PB0,
+ PMUX_PINGRP_PB1,
+ PMUX_PINGRP_PK7,
+ PMUX_PINGRP_PI0,
+ PMUX_PINGRP_PI1,
+ PMUX_PINGRP_PI2,
+ PMUX_PINGRP_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_ROW11_PS3,
+ PMUX_PINGRP_KB_ROW12_PS4,
+ PMUX_PINGRP_KB_ROW13_PS5,
+ PMUX_PINGRP_KB_ROW14_PS6,
+ PMUX_PINGRP_KB_ROW15_PS7,
+ PMUX_PINGRP_KB_COL0_PQ0,
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
+ PMUX_PINGRP_DAP_MCLK1_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_DVFS_PWM_PX0,
+ PMUX_PINGRP_GPIO_X1_AUD_PX1,
+ PMUX_PINGRP_GPIO_X3_AUD_PX3,
+ PMUX_PINGRP_DVFS_CLK_PX2,
+ PMUX_PINGRP_GPIO_X4_AUD_PX4,
+ PMUX_PINGRP_GPIO_X5_AUD_PX5,
+ PMUX_PINGRP_GPIO_X6_AUD_PX6,
+ PMUX_PINGRP_GPIO_X7_AUD_PX7,
+ PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
+ PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+ PMUX_PINGRP_PEX_WAKE_N_PDD3,
+ PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
+ PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+ PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+ PMUX_PINGRP_SDMMC1_WP_N_PV3,
+ PMUX_PINGRP_SDMMC3_CD_N_PV2,
+ PMUX_PINGRP_GPIO_W2_AUD_PW2,
+ PMUX_PINGRP_GPIO_W3_AUD_PW3,
+ PMUX_PINGRP_USB_VBUS_EN0_PN4,
+ PMUX_PINGRP_USB_VBUS_EN1_PN5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+ PMUX_PINGRP_GMI_CLK_LB,
+ PMUX_PINGRP_RESET_OUT_N,
+ PMUX_PINGRP_KB_ROW16_PT0,
+ PMUX_PINGRP_KB_ROW17_PT1,
+ PMUX_PINGRP_USB_VBUS_EN2_PFF1,
+ PMUX_PINGRP_PFF2,
+ PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
- PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
- PDRIVE_PINGROUP_DAP5,
- PDRIVE_PINGROUP_VBUS,
- PDRIVE_PINGROUP_AO3,
- PDRIVE_PINGROUP_HVC,
- PDRIVE_PINGROUP_SDIO4,
- PDRIVE_PINGROUP_AO0,
- PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_DAP1 = (0x28 / 4),
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_DDC = (0x94 / 4),
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GME = (0xa8 / 4),
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_GPV,
+ PMUX_DRVGRP_DEV3,
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_AT6 = (0x12c / 4),
+ PMUX_DRVGRP_DAP5,
+ PMUX_DRVGRP_USB_VBUS_EN,
+ PMUX_DRVGRP_AO3 = (0x140 / 4),
+ PMUX_DRVGRP_AO0 = (0x148 / 4),
+ PMUX_DRVGRP_HV0,
+ PMUX_DRVGRP_SDIO4 = (0x15c / 4),
+ PMUX_DRVGRP_AO4,
+ PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
- PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
- PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
- PMUX_FUNC_HDMI,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
- PMUX_FUNC_KBC,
- PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
- PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
- PMUX_FUNC_OWR,
- PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
- PMUX_FUNC_RTCK,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC2,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI2_ALT,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_UARTE,
- PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- /* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
+ PMUX_FUNC_CCLA,
PMUX_FUNC_CEC,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
+ PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYA_ALT,
+ PMUX_FUNC_DISPLAYB,
+ PMUX_FUNC_DP,
PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
- PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
- PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_IRDA,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PE,
+ PMUX_FUNC_PE0,
+ PMUX_FUNC_PE1,
+ PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_RESET_OUT_N,
+ PMUX_FUNC_RTCK,
PMUX_FUNC_SATA,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
- PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_SYS,
+ PMUX_FUNC_TMDS,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- /* End of Tegra3 MUX selectors */
- PMUX_FUNC_USB,
- PMUX_FUNC_SOC,
- PMUX_FUNC_CPU,
- PMUX_FUNC_CLK,
- PMUX_FUNC_PWRON,
- PMUX_FUNC_PMI,
- PMUX_FUNC_CLDVFS,
- PMUX_FUNC_RESET_OUT_N,
- /* End of Tegra114 MUX selectors */
-
- PMUX_FUNC_SAFE,
- PMUX_FUNC_MAX,
-
- PMUX_FUNC_INVALID = 0x4000,
- PMUX_FUNC_RSVD1 = 0x8000,
- PMUX_FUNC_RSVD2 = 0x8001,
- PMUX_FUNC_RSVD3 = 0x8002,
- PMUX_FUNC_RSVD4 = 0x8003,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) \
- ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
- (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) \
- (((tristate) >= PMUX_TRI_NORMAL) && \
- ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
- PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
- PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE -1
-#define PGRP_HSM_NONE PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
- (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
- (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
- (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* Tegra124 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
- enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
- /* VIL/VIH receivers */
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_VIMCLK2,
+ PMUX_FUNC_VIMCLK2_ALT,
+ PMUX_FUNC_RSVD1,
+ PMUX_FUNC_RSVD2,
+ PMUX_FUNC_RSVD3,
+ PMUX_FUNC_RSVD4,
+ PMUX_FUNC_COUNT,
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
-#endif /* _TEGRA124_PINMUX_H_ */
+#endif /* _TEGRA124_PINMUX_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TEGRA124_USB_H_
-#define _TEGRA124_USB_H_
-
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[2];
-
- /* 0x130 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x140 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint reserved5_1;
-
- /* 0x150 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6;
- uint icusb_ctrl;
-
- /* 0x160 */
- uint ulpi_viewport;
- uint reserved7;
- uint reserved7_0;
- uint reserved7_1;
-
- /* 0x170 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x190 */
- uint reserved9[8];
-
- /* 0x1b0 */
- uint reserved10;
- uint hostpc1_devlc;
- uint reserved10_1[2];
-
- /* 0x1c0 */
- uint reserved10_2[4];
-
- /* 0x1d0 */
- uint reserved10_3[4];
-
- /* 0x1e0 */
- uint reserved10_4[4];
-
- /* 0x1f0 */
- uint reserved10_5;
- uint otgsc;
- uint usb_mode;
- uint reserved10_6;
-
- /* 0x200 */
- uint endpt_nak;
- uint endpt_nak_enable;
- uint endpt_setup_stat;
- uint reserved11_1[0x7D];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[3];
-
- /* 0x420 */
- uint reserved13[56];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB1_LEGACY_CTRL */
-#define USB1_NO_LEGACY_MODE 1
-
-#define VBUS_SENSE_CTL_SHIFT 1
-#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
-#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
-#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
-#define VBUS_SENSE_CTL_AB_SESS_VLD 2
-#define VBUS_SENSE_CTL_A_SESS_VLD 3
-
-/* USBx_IF_USB_SUSP_CTRL_0 */
-#define UTMIP_PHY_ENB (1 << 12)
-#define UTMIP_RESET (1 << 11)
-#define USB_PHY_CLK_VALID (1 << 7)
-#define USB_SUSP_CLR (1 << 5)
-
-/* USBx_UTMIP_MISC_CFG0 */
-#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
-
-/* USBx_UTMIP_MISC_CFG1 */
-#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
-
-/* Moved to Clock and Reset register space */
-#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
-#define UTMIP_PLLU_STABLE_COUNT_MASK \
- (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
-/* Moved to Clock and Reset register space */
-#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
-#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
- (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
-
-/* USBx_UTMIP_PLL_CFG1_0 */
-/* Moved to Clock and Reset register space */
-#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
-#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
- (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
-#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
-#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
-
-/* USBx_UTMIP_BIAS_CFG0_0 */
-#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
-#define UTMIP_OTGPD (1 << 11)
-#define UTMIP_BIASPD (1 << 10)
-#define UTMIP_HSDISCON_LEVEL_SHIFT 2
-#define UTMIP_HSDISCON_LEVEL_MASK \
- (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
-#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
-#define UTMIP_HSSQUELCH_LEVEL_MASK \
- (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
-
-/* USBx_UTMIP_BIAS_CFG1_0 */
-#define UTMIP_FORCE_PDTRK_POWERDOWN 1
-#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
-#define UTMIP_BIAS_PDTRK_COUNT_MASK \
- (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
-
-/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
-#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
-#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
-
-/* USBx_UTMIP_TX_CFG0_0 */
-#define UTMIP_FS_PREAMBLE_J (1 << 19)
-
-/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
-#define UTMIP_PD_CHRG 1
-
-/* USBx_UTMIP_SPARE_CFG0_0 */
-#define FUSE_SETUP_SEL (1 << 3)
-
-/* USBx_UTMIP_HSRX_CFG0_0 */
-#define UTMIP_IDLE_WAIT_SHIFT 15
-#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
-#define UTMIP_ELASTIC_LIMIT_SHIFT 10
-#define UTMIP_ELASTIC_LIMIT_MASK \
- (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
-
-/* USBx_UTMIP_HSRX_CFG0_1 */
-#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
-#define UTMIP_HS_SYNC_START_DLY_MASK \
- (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
-
-/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
-#define IC_ENB1 (1 << 3)
-
-/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
-#define PTS1_SHIFT 31
-#define PTS1_MASK (1 << PTS1_SHIFT)
-#define STS1 (1 << 30)
-
-/* USB2D_HOSTPC1_DEVLC_0 */
-#define PTS_SHIFT 29
-#define PTS_MASK (0x7U << PTS_SHIFT)
-#define PTS_UTMI 0
-#define PTS_RESERVED 1
-#define PTS_ULPI 2
-#define PTS_ICUSB_SER 3
-#define PTS_HSIC 4
-
-#define STS (1 << 28)
-
-/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
-#define WKOC (1 << 22)
-#define WKDS (1 << 21)
-#define WKCN (1 << 20)
-
-/* USBx_UTMIP_XCVR_CFG0_0 */
-#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
-#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
-#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
-#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
-#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
-#define UTMIP_XCVR_HSSLEW_MSB_MASK \
- (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
-#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_SHIFT 0
-#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
-
-/* USBx_UTMIP_XCVR_CFG1_0 */
-#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
-#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
- (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
-#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
-#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
-#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
-
-/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
-#define VBUS_VLD_STS (1 << 26)
-
-#endif /* _TEGRA124_USB_H_ */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _PINMUX_H_
-#define _PINMUX_H_
+#ifndef _TEGRA20_PINMUX_H_
+#define _TEGRA20_PINMUX_H_
/*
* Pin groups which we adjust. There are three basic attributes of each pin
*/
enum pmux_pingrp {
/* APB_MISC_PP_TRISTATE_REG_A_0 */
- PINGRP_ATA,
- PINGRP_ATB,
- PINGRP_ATC,
- PINGRP_ATD,
- PINGRP_CDEV1,
- PINGRP_CDEV2,
- PINGRP_CSUS,
- PINGRP_DAP1,
-
- PINGRP_DAP2,
- PINGRP_DAP3,
- PINGRP_DAP4,
- PINGRP_DTA,
- PINGRP_DTB,
- PINGRP_DTC,
- PINGRP_DTD,
- PINGRP_DTE,
-
- PINGRP_GPU,
- PINGRP_GPV,
- PINGRP_I2CP,
- PINGRP_IRTX,
- PINGRP_IRRX,
- PINGRP_KBCB,
- PINGRP_KBCA,
- PINGRP_PMC,
-
- PINGRP_PTA,
- PINGRP_RM,
- PINGRP_KBCE,
- PINGRP_KBCF,
- PINGRP_GMA,
- PINGRP_GMC,
- PINGRP_SDIO1,
- PINGRP_OWC,
+ PMUX_PINGRP_ATA,
+ PMUX_PINGRP_ATB,
+ PMUX_PINGRP_ATC,
+ PMUX_PINGRP_ATD,
+ PMUX_PINGRP_CDEV1,
+ PMUX_PINGRP_CDEV2,
+ PMUX_PINGRP_CSUS,
+ PMUX_PINGRP_DAP1,
+
+ PMUX_PINGRP_DAP2,
+ PMUX_PINGRP_DAP3,
+ PMUX_PINGRP_DAP4,
+ PMUX_PINGRP_DTA,
+ PMUX_PINGRP_DTB,
+ PMUX_PINGRP_DTC,
+ PMUX_PINGRP_DTD,
+ PMUX_PINGRP_DTE,
+
+ PMUX_PINGRP_GPU,
+ PMUX_PINGRP_GPV,
+ PMUX_PINGRP_I2CP,
+ PMUX_PINGRP_IRTX,
+ PMUX_PINGRP_IRRX,
+ PMUX_PINGRP_KBCB,
+ PMUX_PINGRP_KBCA,
+ PMUX_PINGRP_PMC,
+
+ PMUX_PINGRP_PTA,
+ PMUX_PINGRP_RM,
+ PMUX_PINGRP_KBCE,
+ PMUX_PINGRP_KBCF,
+ PMUX_PINGRP_GMA,
+ PMUX_PINGRP_GMC,
+ PMUX_PINGRP_SDIO1,
+ PMUX_PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
- PINGRP_GME,
- PINGRP_SDC,
- PINGRP_SDD,
- PINGRP_RESERVED0,
- PINGRP_SLXA,
- PINGRP_SLXC,
- PINGRP_SLXD,
- PINGRP_SLXK,
-
- PINGRP_SPDI,
- PINGRP_SPDO,
- PINGRP_SPIA,
- PINGRP_SPIB,
- PINGRP_SPIC,
- PINGRP_SPID,
- PINGRP_SPIE,
- PINGRP_SPIF,
-
- PINGRP_SPIG,
- PINGRP_SPIH,
- PINGRP_UAA,
- PINGRP_UAB,
- PINGRP_UAC,
- PINGRP_UAD,
- PINGRP_UCA,
- PINGRP_UCB,
-
- PINGRP_RESERVED1,
- PINGRP_ATE,
- PINGRP_KBCC,
- PINGRP_RESERVED2,
- PINGRP_RESERVED3,
- PINGRP_GMB,
- PINGRP_GMD,
- PINGRP_DDC,
+ PMUX_PINGRP_GME,
+ PMUX_PINGRP_SDC,
+ PMUX_PINGRP_SDD,
+ PMUX_PINGRP_RESERVED0,
+ PMUX_PINGRP_SLXA,
+ PMUX_PINGRP_SLXC,
+ PMUX_PINGRP_SLXD,
+ PMUX_PINGRP_SLXK,
+
+ PMUX_PINGRP_SPDI,
+ PMUX_PINGRP_SPDO,
+ PMUX_PINGRP_SPIA,
+ PMUX_PINGRP_SPIB,
+ PMUX_PINGRP_SPIC,
+ PMUX_PINGRP_SPID,
+ PMUX_PINGRP_SPIE,
+ PMUX_PINGRP_SPIF,
+
+ PMUX_PINGRP_SPIG,
+ PMUX_PINGRP_SPIH,
+ PMUX_PINGRP_UAA,
+ PMUX_PINGRP_UAB,
+ PMUX_PINGRP_UAC,
+ PMUX_PINGRP_UAD,
+ PMUX_PINGRP_UCA,
+ PMUX_PINGRP_UCB,
+
+ PMUX_PINGRP_RESERVED1,
+ PMUX_PINGRP_ATE,
+ PMUX_PINGRP_KBCC,
+ PMUX_PINGRP_RESERVED2,
+ PMUX_PINGRP_RESERVED3,
+ PMUX_PINGRP_GMB,
+ PMUX_PINGRP_GMD,
+ PMUX_PINGRP_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
- PINGRP_LD0,
- PINGRP_LD1,
- PINGRP_LD2,
- PINGRP_LD3,
- PINGRP_LD4,
- PINGRP_LD5,
- PINGRP_LD6,
- PINGRP_LD7,
-
- PINGRP_LD8,
- PINGRP_LD9,
- PINGRP_LD10,
- PINGRP_LD11,
- PINGRP_LD12,
- PINGRP_LD13,
- PINGRP_LD14,
- PINGRP_LD15,
-
- PINGRP_LD16,
- PINGRP_LD17,
- PINGRP_LHP0,
- PINGRP_LHP1,
- PINGRP_LHP2,
- PINGRP_LVP0,
- PINGRP_LVP1,
- PINGRP_HDINT,
-
- PINGRP_LM0,
- PINGRP_LM1,
- PINGRP_LVS,
- PINGRP_LSC0,
- PINGRP_LSC1,
- PINGRP_LSCK,
- PINGRP_LDC,
- PINGRP_LCSN,
+ PMUX_PINGRP_LD0,
+ PMUX_PINGRP_LD1,
+ PMUX_PINGRP_LD2,
+ PMUX_PINGRP_LD3,
+ PMUX_PINGRP_LD4,
+ PMUX_PINGRP_LD5,
+ PMUX_PINGRP_LD6,
+ PMUX_PINGRP_LD7,
+
+ PMUX_PINGRP_LD8,
+ PMUX_PINGRP_LD9,
+ PMUX_PINGRP_LD10,
+ PMUX_PINGRP_LD11,
+ PMUX_PINGRP_LD12,
+ PMUX_PINGRP_LD13,
+ PMUX_PINGRP_LD14,
+ PMUX_PINGRP_LD15,
+
+ PMUX_PINGRP_LD16,
+ PMUX_PINGRP_LD17,
+ PMUX_PINGRP_LHP0,
+ PMUX_PINGRP_LHP1,
+ PMUX_PINGRP_LHP2,
+ PMUX_PINGRP_LVP0,
+ PMUX_PINGRP_LVP1,
+ PMUX_PINGRP_HDINT,
+
+ PMUX_PINGRP_LM0,
+ PMUX_PINGRP_LM1,
+ PMUX_PINGRP_LVS,
+ PMUX_PINGRP_LSC0,
+ PMUX_PINGRP_LSC1,
+ PMUX_PINGRP_LSCK,
+ PMUX_PINGRP_LDC,
+ PMUX_PINGRP_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
- PINGRP_LSPI,
- PINGRP_LSDA,
- PINGRP_LSDI,
- PINGRP_LPW0,
- PINGRP_LPW1,
- PINGRP_LPW2,
- PINGRP_LDI,
- PINGRP_LHS,
-
- PINGRP_LPP,
- PINGRP_RESERVED4,
- PINGRP_KBCD,
- PINGRP_GPU7,
- PINGRP_DTF,
- PINGRP_UDA,
- PINGRP_CRTP,
- PINGRP_SDB,
+ PMUX_PINGRP_LSPI,
+ PMUX_PINGRP_LSDA,
+ PMUX_PINGRP_LSDI,
+ PMUX_PINGRP_LPW0,
+ PMUX_PINGRP_LPW1,
+ PMUX_PINGRP_LPW2,
+ PMUX_PINGRP_LDI,
+ PMUX_PINGRP_LHS,
+
+ PMUX_PINGRP_LPP,
+ PMUX_PINGRP_RESERVED4,
+ PMUX_PINGRP_KBCD,
+ PMUX_PINGRP_GPU7,
+ PMUX_PINGRP_DTF,
+ PMUX_PINGRP_UDA,
+ PMUX_PINGRP_CRTP,
+ PMUX_PINGRP_SDB,
/* these pin groups only have pullup and pull down control */
- PINGRP_FIRST_NO_MUX,
- PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
- PINGRP_DDRC,
- PINGRP_PMCA,
- PINGRP_PMCB,
- PINGRP_PMCC,
- PINGRP_PMCD,
- PINGRP_PMCE,
- PINGRP_XM2C,
- PINGRP_XM2D,
-
- PINGRP_COUNT,
+ PMUX_PINGRP_CK32,
+ PMUX_PINGRP_DDRC,
+ PMUX_PINGRP_PMCA,
+ PMUX_PINGRP_PMCB,
+ PMUX_PINGRP_PMCC,
+ PMUX_PINGRP_PMCD,
+ PMUX_PINGRP_PMCE,
+ PMUX_PINGRP_XM2C,
+ PMUX_PINGRP_XM2D,
+ PMUX_PINGRP_COUNT,
};
/*
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
- PMUX_FUNC_SAFE,
-
- /* These don't have a name, but can be used in the table */
PMUX_FUNC_RSVD1,
PMUX_FUNC_RSVD2,
PMUX_FUNC_RSVD3,
PMUX_FUNC_RSVD4,
- PMUX_FUNC_RSVD, /* Not valid and should not be used */
-
PMUX_FUNC_COUNT,
-
- PMUX_FUNC_NONE = -1,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
- (func) != PMUX_FUNC_RSVD)
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
-
- PMUX_VDDIO_NONE
-};
-
-enum {
- PMUX_TRISTATE_REGS = 4,
- PMUX_MUX_REGS = 7,
- PMUX_PULL_REGS = 5,
-};
-
-/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
-
- uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */
- uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */
- uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(const struct pingroup_config *config);
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/**
- * Configuure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(const struct pingroup_config *config, int len);
+#include <asm/arch-tegra/pinmux.h>
-#endif /* PINMUX_H */
+#endif /* _TEGRA20_PINMUX_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA20_USB_H_
-#define _TEGRA20_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[6];
-
- /* 0x140 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x150 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint async_tt_sts;
-
- /* 0x160 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6; /* is this port_sc1 on some controllers? */
- uint icusb_ctrl;
-
- /* 0x170 */
- uint ulpi_viewport;
- uint reserved7;
- uint endpt_nak;
- uint endpt_nak_enable;
-
- /* 0x180 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x1a0 */
- uint reserved9;
- uint otgsc;
- uint usb_mode;
- uint endpt_setup_stat;
-
- /* 0x1b0 */
- uint reserved10[20];
-
- /* 0x200 */
- uint reserved11[0x80];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[4];
-
- /* 0x424 */
- uint ulpi_timing_ctrl_0;
- uint ulpi_timing_ctrl_1;
- uint reserved13[53];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB2_IF_ULPI_TIMING_CTRL_0 */
-#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
-#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
-
-/* USB2_IF_ULPI_TIMING_CTRL_1 */
-#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
-#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
-#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
-#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
-#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
-#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
-
-/* PORTSC, USB2, USB3 */
-#define PTS_SHIFT 30
-#define PTS_MASK (3U << PTS_SHIFT)
-
-#define STS (1 << 29)
-#endif /* _TEGRA20_USB_H_ */
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA30_PINMUX_H_
#define _TEGRA30_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_GPIO_PV2,
- PINGRP_GPIO_PV3,
- PINGRP_CLK2_OUT,
- PINGRP_CLK2_REQ,
- PINGRP_LCD_PWR1,
- PINGRP_LCD_PWR2,
- PINGRP_LCD_SDIN,
- PINGRP_LCD_SDOUT,
- PINGRP_LCD_WR_N,
- PINGRP_LCD_CS0_N,
- PINGRP_LCD_DC0,
- PINGRP_LCD_SCK,
- PINGRP_LCD_PWR0,
- PINGRP_LCD_PCLK,
- PINGRP_LCD_DE,
- PINGRP_LCD_HSYNC,
- PINGRP_LCD_VSYNC,
- PINGRP_LCD_D0,
- PINGRP_LCD_D1,
- PINGRP_LCD_D2,
- PINGRP_LCD_D3,
- PINGRP_LCD_D4,
- PINGRP_LCD_D5,
- PINGRP_LCD_D6,
- PINGRP_LCD_D7,
- PINGRP_LCD_D8,
- PINGRP_LCD_D9,
- PINGRP_LCD_D10,
- PINGRP_LCD_D11,
- PINGRP_LCD_D12,
- PINGRP_LCD_D13,
- PINGRP_LCD_D14,
- PINGRP_LCD_D15,
- PINGRP_LCD_D16,
- PINGRP_LCD_D17,
- PINGRP_LCD_D18,
- PINGRP_LCD_D19,
- PINGRP_LCD_D20,
- PINGRP_LCD_D21,
- PINGRP_LCD_D22,
- PINGRP_LCD_D23,
- PINGRP_LCD_CS1_N,
- PINGRP_LCD_M1,
- PINGRP_LCD_DC1,
- PINGRP_HDMI_INT,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_CRT_HSYNC,
- PINGRP_CRT_VSYNC,
- PINGRP_VI_D0,
- PINGRP_VI_D1,
- PINGRP_VI_D2,
- PINGRP_VI_D3,
- PINGRP_VI_D4,
- PINGRP_VI_D5,
- PINGRP_VI_D6,
- PINGRP_VI_D7,
- PINGRP_VI_D8,
- PINGRP_VI_D9,
- PINGRP_VI_D10,
- PINGRP_VI_D11,
- PINGRP_VI_PCLK,
- PINGRP_VI_MCLK,
- PINGRP_VI_VSYNC,
- PINGRP_VI_HSYNC,
- PINGRP_UART2_RXD,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- PINGRP_GMI_WP_N,
- PINGRP_GMI_IORDY,
- PINGRP_GMI_WAIT,
- PINGRP_GMI_ADV_N,
- PINGRP_GMI_CLK,
- PINGRP_GMI_CS0_N,
- PINGRP_GMI_CS1_N,
- PINGRP_GMI_CS2_N,
- PINGRP_GMI_CS3_N,
- PINGRP_GMI_CS4_N,
- PINGRP_GMI_CS6_N,
- PINGRP_GMI_CS7_N,
- PINGRP_GMI_AD0,
- PINGRP_GMI_AD1,
- PINGRP_GMI_AD2,
- PINGRP_GMI_AD3,
- PINGRP_GMI_AD4,
- PINGRP_GMI_AD5,
- PINGRP_GMI_AD6,
- PINGRP_GMI_AD7,
- PINGRP_GMI_AD8,
- PINGRP_GMI_AD9,
- PINGRP_GMI_AD10,
- PINGRP_GMI_AD11,
- PINGRP_GMI_AD12,
- PINGRP_GMI_AD13,
- PINGRP_GMI_AD14,
- PINGRP_GMI_AD15,
- PINGRP_GMI_A16,
- PINGRP_GMI_A17,
- PINGRP_GMI_A18,
- PINGRP_GMI_A19,
- PINGRP_GMI_WR_N,
- PINGRP_GMI_OE_N,
- PINGRP_GMI_DQS,
- PINGRP_GMI_RST_N,
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_SDMMC4_RST_N,
- PINGRP_CAM_MCLK,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_ROW11,
- PINGRP_KB_ROW12,
- PINGRP_KB_ROW13,
- PINGRP_KB_ROW14,
- PINGRP_KB_ROW15,
- PINGRP_KB_COL0,
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_SYS_CLK_REQ,
- PINGRP_CORE_PWR_REQ,
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_SPI2_MOSI,
- PINGRP_SPI2_MISO,
- PINGRP_SPI2_CS0_N,
- PINGRP_SPI2_SCK,
- PINGRP_SPI1_MOSI,
- PINGRP_SPI1_SCK,
- PINGRP_SPI1_CS0_N,
- PINGRP_SPI1_MISO,
- PINGRP_SPI2_CS1_N,
- PINGRP_SPI2_CS2_N,
- PINGRP_SDMMC3_CLK,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_SDMMC3_DAT4,
- PINGRP_SDMMC3_DAT5,
- PINGRP_SDMMC3_DAT6,
- PINGRP_SDMMC3_DAT7,
- PINGRP_PEX_L0_PRSNT_N,
- PINGRP_PEX_L0_RST_N,
- PINGRP_PEX_L0_CLKREQ_N,
- PINGRP_PEX_WAKE_N,
- PINGRP_PEX_L1_PRSNT_N,
- PINGRP_PEX_L1_RST_N,
- PINGRP_PEX_L1_CLKREQ_N,
- PINGRP_PEX_L2_PRSNT_N,
- PINGRP_PEX_L2_RST_N,
- PINGRP_PEX_L2_CLKREQ_N,
- PINGRP_HDMI_CEC, /* offset 0x33e0 */
- PINGRP_COUNT,
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_PV2,
+ PMUX_PINGRP_PV3,
+ PMUX_PINGRP_CLK2_OUT_PW5,
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_LCD_PWR1_PC1,
+ PMUX_PINGRP_LCD_PWR2_PC6,
+ PMUX_PINGRP_LCD_SDIN_PZ2,
+ PMUX_PINGRP_LCD_SDOUT_PN5,
+ PMUX_PINGRP_LCD_WR_N_PZ3,
+ PMUX_PINGRP_LCD_CS0_N_PN4,
+ PMUX_PINGRP_LCD_DC0_PN6,
+ PMUX_PINGRP_LCD_SCK_PZ4,
+ PMUX_PINGRP_LCD_PWR0_PB2,
+ PMUX_PINGRP_LCD_PCLK_PB3,
+ PMUX_PINGRP_LCD_DE_PJ1,
+ PMUX_PINGRP_LCD_HSYNC_PJ3,
+ PMUX_PINGRP_LCD_VSYNC_PJ4,
+ PMUX_PINGRP_LCD_D0_PE0,
+ PMUX_PINGRP_LCD_D1_PE1,
+ PMUX_PINGRP_LCD_D2_PE2,
+ PMUX_PINGRP_LCD_D3_PE3,
+ PMUX_PINGRP_LCD_D4_PE4,
+ PMUX_PINGRP_LCD_D5_PE5,
+ PMUX_PINGRP_LCD_D6_PE6,
+ PMUX_PINGRP_LCD_D7_PE7,
+ PMUX_PINGRP_LCD_D8_PF0,
+ PMUX_PINGRP_LCD_D9_PF1,
+ PMUX_PINGRP_LCD_D10_PF2,
+ PMUX_PINGRP_LCD_D11_PF3,
+ PMUX_PINGRP_LCD_D12_PF4,
+ PMUX_PINGRP_LCD_D13_PF5,
+ PMUX_PINGRP_LCD_D14_PF6,
+ PMUX_PINGRP_LCD_D15_PF7,
+ PMUX_PINGRP_LCD_D16_PM0,
+ PMUX_PINGRP_LCD_D17_PM1,
+ PMUX_PINGRP_LCD_D18_PM2,
+ PMUX_PINGRP_LCD_D19_PM3,
+ PMUX_PINGRP_LCD_D20_PM4,
+ PMUX_PINGRP_LCD_D21_PM5,
+ PMUX_PINGRP_LCD_D22_PM6,
+ PMUX_PINGRP_LCD_D23_PM7,
+ PMUX_PINGRP_LCD_CS1_N_PW0,
+ PMUX_PINGRP_LCD_M1_PW1,
+ PMUX_PINGRP_LCD_DC1_PD2,
+ PMUX_PINGRP_HDMI_INT_PN7,
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_CRT_HSYNC_PV6,
+ PMUX_PINGRP_CRT_VSYNC_PV7,
+ PMUX_PINGRP_VI_D0_PT4,
+ PMUX_PINGRP_VI_D1_PD5,
+ PMUX_PINGRP_VI_D2_PL0,
+ PMUX_PINGRP_VI_D3_PL1,
+ PMUX_PINGRP_VI_D4_PL2,
+ PMUX_PINGRP_VI_D5_PL3,
+ PMUX_PINGRP_VI_D6_PL4,
+ PMUX_PINGRP_VI_D7_PL5,
+ PMUX_PINGRP_VI_D8_PL6,
+ PMUX_PINGRP_VI_D9_PL7,
+ PMUX_PINGRP_VI_D10_PT2,
+ PMUX_PINGRP_VI_D11_PT3,
+ PMUX_PINGRP_VI_PCLK_PT0,
+ PMUX_PINGRP_VI_MCLK_PT1,
+ PMUX_PINGRP_VI_VSYNC_PD6,
+ PMUX_PINGRP_VI_HSYNC_PD7,
+ PMUX_PINGRP_UART2_RXD_PC3,
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_GMI_WP_N_PC7,
+ PMUX_PINGRP_GMI_IORDY_PI5,
+ PMUX_PINGRP_GMI_WAIT_PI7,
+ PMUX_PINGRP_GMI_ADV_N_PK0,
+ PMUX_PINGRP_GMI_CLK_PK1,
+ PMUX_PINGRP_GMI_CS0_N_PJ0,
+ PMUX_PINGRP_GMI_CS1_N_PJ2,
+ PMUX_PINGRP_GMI_CS2_N_PK3,
+ PMUX_PINGRP_GMI_CS3_N_PK4,
+ PMUX_PINGRP_GMI_CS4_N_PK2,
+ PMUX_PINGRP_GMI_CS6_N_PI3,
+ PMUX_PINGRP_GMI_CS7_N_PI6,
+ PMUX_PINGRP_GMI_AD0_PG0,
+ PMUX_PINGRP_GMI_AD1_PG1,
+ PMUX_PINGRP_GMI_AD2_PG2,
+ PMUX_PINGRP_GMI_AD3_PG3,
+ PMUX_PINGRP_GMI_AD4_PG4,
+ PMUX_PINGRP_GMI_AD5_PG5,
+ PMUX_PINGRP_GMI_AD6_PG6,
+ PMUX_PINGRP_GMI_AD7_PG7,
+ PMUX_PINGRP_GMI_AD8_PH0,
+ PMUX_PINGRP_GMI_AD9_PH1,
+ PMUX_PINGRP_GMI_AD10_PH2,
+ PMUX_PINGRP_GMI_AD11_PH3,
+ PMUX_PINGRP_GMI_AD12_PH4,
+ PMUX_PINGRP_GMI_AD13_PH5,
+ PMUX_PINGRP_GMI_AD14_PH6,
+ PMUX_PINGRP_GMI_AD15_PH7,
+ PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_PINGRP_GMI_WR_N_PI0,
+ PMUX_PINGRP_GMI_OE_N_PI1,
+ PMUX_PINGRP_GMI_DQS_PI2,
+ PMUX_PINGRP_GMI_RST_N_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_SDMMC4_RST_N_PCC3,
+ PMUX_PINGRP_CAM_MCLK_PCC0,
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK_PU7,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_ROW11_PS3,
+ PMUX_PINGRP_KB_ROW12_PS4,
+ PMUX_PINGRP_KB_ROW13_PS5,
+ PMUX_PINGRP_KB_ROW14_PS6,
+ PMUX_PINGRP_KB_ROW15_PS7,
+ PMUX_PINGRP_KB_COL0_PQ0,
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+ PMUX_PINGRP_CORE_PWR_REQ,
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_CLK1_REQ_PEE2,
+ PMUX_PINGRP_CLK1_OUT_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_SPI2_MOSI_PX0,
+ PMUX_PINGRP_SPI2_MISO_PX1,
+ PMUX_PINGRP_SPI2_CS0_N_PX3,
+ PMUX_PINGRP_SPI2_SCK_PX2,
+ PMUX_PINGRP_SPI1_MOSI_PX4,
+ PMUX_PINGRP_SPI1_SCK_PX5,
+ PMUX_PINGRP_SPI1_CS0_N_PX6,
+ PMUX_PINGRP_SPI1_MISO_PX7,
+ PMUX_PINGRP_SPI2_CS1_N_PW2,
+ PMUX_PINGRP_SPI2_CS2_N_PW3,
+ PMUX_PINGRP_SDMMC3_CLK_PA6,
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_SDMMC3_DAT4_PD1,
+ PMUX_PINGRP_SDMMC3_DAT5_PD0,
+ PMUX_PINGRP_SDMMC3_DAT6_PD3,
+ PMUX_PINGRP_SDMMC3_DAT7_PD4,
+ PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
+ PMUX_PINGRP_PEX_L0_RST_N_PDD1,
+ PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+ PMUX_PINGRP_PEX_WAKE_N_PDD3,
+ PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
+ PMUX_PINGRP_PEX_L1_RST_N_PDD5,
+ PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+ PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
+ PMUX_PINGRP_PEX_L2_RST_N_PCC6,
+ PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
+ PMUX_PINGRP_HDMI_CEC_PEE3,
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_CSUS,
- PDRIVE_PINGROUP_DAP1,
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_LCD1,
- PDRIVE_PINGROUP_LCD2,
- PDRIVE_PINGROUP_SDIO2,
- PDRIVE_PINGROUP_SDIO3,
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
- PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
- PDRIVE_PINGROUP_DDC,
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GMB,
- PDRIVE_PINGROUP_GMC,
- PDRIVE_PINGROUP_GMD,
- PDRIVE_PINGROUP_GME,
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_GPV,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_CSUS,
+ PMUX_DRVGRP_DAP1,
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_LCD1,
+ PMUX_DRVGRP_LCD2,
+ PMUX_DRVGRP_SDIO2,
+ PMUX_DRVGRP_SDIO3,
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_VI1,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_CRT = (0x90 / 4),
+ PMUX_DRVGRP_DDC,
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GMB,
+ PMUX_DRVGRP_GMC,
+ PMUX_DRVGRP_GMD,
+ PMUX_DRVGRP_GME,
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_GPV,
+ PMUX_DRVGRP_DEV3,
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK_12M_OUT,
+ PMUX_FUNC_CLK_32K_IN,
+ PMUX_FUNC_CORE_PWR_REQ,
+ PMUX_FUNC_CPU_PWR_REQ,
PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYB,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HDCP,
PMUX_FUNC_HDMI,
+ PMUX_FUNC_HSI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_INVALID,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
+ PMUX_FUNC_NAND_ALT,
PMUX_FUNC_OWR,
PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_PWR_INT_N,
PMUX_FUNC_RTCK,
+ PMUX_FUNC_SATA,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI2_ALT,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_TEST,
PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_UARTE,
PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- PMUX_FUNC_BLINK,
- PMUX_FUNC_CEC,
- PMUX_FUNC_CLK12,
- PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
- PMUX_FUNC_DEV3,
- PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
- PMUX_FUNC_EMC_DLL,
- PMUX_FUNC_EXTPERIPH1,
- PMUX_FUNC_EXTPERIPH2,
- PMUX_FUNC_EXTPERIPH3,
- PMUX_FUNC_GMI_ALT,
- PMUX_FUNC_HDA,
- PMUX_FUNC_HSI,
- PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
- PMUX_FUNC_I2CPWR,
- PMUX_FUNC_I2S0,
- PMUX_FUNC_I2S1,
- PMUX_FUNC_I2S2,
- PMUX_FUNC_I2S3,
- PMUX_FUNC_I2S4,
- PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
- PMUX_FUNC_PWM0,
- PMUX_FUNC_PWM1,
- PMUX_FUNC_PWM2,
- PMUX_FUNC_PWM3,
- PMUX_FUNC_SATA,
- PMUX_FUNC_SPI5,
- PMUX_FUNC_SPI6,
- PMUX_FUNC_SYSCLK,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- PMUX_FUNC_CLK_12M_OUT,
- PMUX_FUNC_HDCP,
- PMUX_FUNC_TEST,
- PMUX_FUNC_CORE_PWR_REQ,
- PMUX_FUNC_CPU_PWR_REQ,
- PMUX_FUNC_PWR_INT_N,
- PMUX_FUNC_CLK_32K_IN,
- PMUX_FUNC_SAFE,
-
- PMUX_FUNC_MAX,
-
- PMUX_FUNC_RSVD1 = 0x8000,
- PMUX_FUNC_RSVD2 = 0x8001,
- PMUX_FUNC_RSVD3 = 0x8002,
- PMUX_FUNC_RSVD4 = 0x8003,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
- || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
- && ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* t30 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_RSVD1,
+ PMUX_FUNC_RSVD2,
+ PMUX_FUNC_RSVD3,
+ PMUX_FUNC_RSVD4,
+ PMUX_FUNC_COUNT,
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
-#endif /* _TEGRA30_PINMUX_H_ */
+#endif /* _TEGRA30_PINMUX_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA30_USB_H_
-#define _TEGRA30_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[2];
-
- /* 0x130 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x140 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint reserved5_1;
-
- /* 0x150 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6;
- uint icusb_ctrl;
-
- /* 0x160 */
- uint ulpi_viewport;
- uint reserved7[3];
-
- /* 0x170 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x190 */
- uint reserved9[8];
-
- /* 0x1b0 */
- uint reserved10;
- uint hostpc1_devlc;
- uint reserved10_1[2];
-
- /* 0x1c0 */
- uint reserved10_2[4];
-
- /* 0x1d0 */
- uint reserved10_3[4];
-
- /* 0x1e0 */
- uint reserved10_4[4];
-
- /* 0x1f0 */
- uint reserved10_5;
- uint otgsc;
- uint usb_mode;
- uint reserved10_6;
-
- /* 0x200 */
- uint endpt_nak;
- uint endpt_nak_enable;
- uint endpt_setup_stat;
- uint reserved11_1[0x7D];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[3];
-
- /* 0x420 */
- uint reserved13[56];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB2_IF_ULPI_TIMING_CTRL_0 */
-#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
-#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
-
-/* USB2_IF_ULPI_TIMING_CTRL_1 */
-#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
-#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
-#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
-#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
-#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
-#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
-
-/* USB2D_HOSTPC1_DEVLC_0 */
-#define PTS_SHIFT 29
-#define PTS_MASK (0x7U << PTS_SHIFT)
-
-#define STS (1 << 28)
-#endif /* _TEGRA30_USB_H_ */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
u32 txdone, u32 txdone_mask, u32 opp);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
+void usb_fake_mac_from_die_id(u32 *id);
+
/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL 0
#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
#ifndef __ASSEMBLY__
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
- gd->bd->bi_baudrate = gd->baudrate;
/* Ram ist board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
- unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;
*/
bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
bd->bi_dram[0].size = sdram_size;
- bd->bi_baudrate = gd->baudrate;
memcpy(new_gd, gd, sizeof(gd_t));
+++ /dev/null
-/*
- * net.h - misc Blackfin network helpers
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_RAND_MAC__
-#define __ASM_BFIN_RAND_MAC__
-
-/* If the board does not have a real MAC assigned to it, then generate a
- * locally administrated pseudo-random one based on CYCLES and compile date.
- */
-static inline void bfin_gen_rand_mac(uchar *mac_addr)
-{
- /* make something up */
- const char s[] = __DATE__;
- size_t i;
- u32 cycles;
- for (i = 0; i < 6; ++i) {
- asm("%0 = CYCLES;" : "=r" (cycles));
- mac_addr[i] = cycles ^ s[i];
- }
- mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
-}
-
-#endif
#define _U_BOOT_H_ 1
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
- gd->bd->bi_baudrate = gd->baudrate;
return 0;
}
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" \\-bd: %p\n", gd->bd);
- printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
printf(" |-bi_memsize: %lx\n", bd->bi_memsize);
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
- unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
#endif
- bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned int bi_baudrate; /* Console Baudrate */
ulong bi_boot_params; /* where this board expects params */
} bd_t;
memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
gd->bd = bd;
gd->baudrate = CONFIG_BAUDRATE;
- bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#else /* !CONFIG_SYS_GENERIC_BOARD */
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
*/
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */
bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */
- bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
memcpy(id, (void *)gd, sizeof(gd_t));
#include <environment.h>
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
addr_sp &= ~0x07;
debug("New Stack Pointer is: %08lx\n", addr_sp);
- gd->bd->bi_baudrate = gd->baudrate;
/* Ram isn't board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();
#define _U_BOOT_H_
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
WATCHDOG_RESET();
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
check_erratum_a007212();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ puts("Work-around for Erratum A-005434 enabled\n");
+#endif
return 0;
}
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
+ if (SVR_SOC_VER(svr) == SVR_T4080) {
+ ccsr_rcpm_t *rcpm =
+ (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+ setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+ FSL_CORENET_DEVDISR2_DTSEC1_9);
+ setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+ setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+ /* It needs SW to disable core4~7 as HW design sake on T4080 */
+ for (i = 4; i < 8; i++)
+ cpu_disable(i);
+
+ /* request core4~7 into PH20 state, prior to entering PCL10
+ * state, all cores in cluster should be placed in PH20 state.
+ */
+ setbits_be32(&rcpm->pcph20setr, 0xf0);
+
+ /* put the 2nd cluster into PCL10 state */
+ setbits_be32(&rcpm->clpcl10setr, 1 << 1);
+ }
+#endif
+
if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
puts("Unicore software on multiprocessor system!!\n"
}
#endif
-void cpu_init_f (void)
+ulong cpu_init_f(void)
{
+ ulong flag = 0;
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+ flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
+ return flag;
}
/* Implement a dummy function for those platforms w/o SERDES */
int enable_cluster_l2(void)
{
int i = 0;
- u32 cluster;
+ u32 cluster, svr = get_svr();
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
+ /* only the L2 of first cluster should be enabled as expected on T4080,
+ * but there is no EOC in the first cluster as HW sake, so return here
+ * to skip enabling L2 cache of the 2nd cluster.
+ */
+ if (SVR_SOC_VER(svr) == SVR_T4080)
+ return 0;
+
cluster = in_be32(&gur->tp_cluster[i].lower);
if (cluster & TP_CLUSTER_EOC)
return 0;
}
#endif
+ init_used_tlb_cams();
return 0;
}
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
+#ifdef CONFIG_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
+#endif
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
#ifdef CONFIG_CPM2
do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
- "current-speed", bd->bi_baudrate, 1);
+ "current-speed", gd->baudrate, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
"clock-frequency", bd->bi_brgfreq, 1);
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
if (SVR_MAJ(get_svr()) >= 2)
mem_pll_rat *= 2;
#endif
DECLARE_GLOBAL_DATA_PTR;
-void cpu_init_f(void)
+ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
#endif
+
+ return 0;
}
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#endif
mtspr HID0,r0
-#ifndef CONFIG_E500MC
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
mtmsr r3
isync
- bl cpu_init_f
+ bl cpu_init_f /* return boot_flag for calling board_init_f */
bl board_init_f
isync
};
#endif
+#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_BASE(1, 307),
SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
OUTPUT_ARCH(powerpc)
SECTIONS
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
OUTPUT_ARCH(powerpc)
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifdef CONFIG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
/* bl l2cache_enable */
/* run 1st part of board init code (from Flash) */
+ li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
sync
CPU_TYPE_ENTRY(T4240, T4240, 0),
CPU_TYPE_ENTRY(T4120, T4120, 0),
CPU_TYPE_ENTRY(T4160, T4160, 0),
+ CPU_TYPE_ENTRY(T4080, T4080, 4),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
+ CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
CPU_TYPE_ENTRY(B4220, B4220, 0),
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
-u32 cpu_mask(void)
+__weak u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
/*
* Return the number of cores on this SOC.
*/
-int cpu_numcores(void)
+__weak int cpu_numcores(void)
{
struct cpu_type *cpu = gd->arch.cpu;
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A005434
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
-#define CONFIG_MAX_CPUS 8
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_SYS_NUM_FM1_DTSEC 7
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_NUM_FM2_DTSEC 7
+#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#if defined(CONFIG_PPC_T4160)
+#define CONFIG_MAX_CPUS 8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#elif defined(CONFIG_PPC_T4080)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
+#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
u32 svr = get_svr();
if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
case SVR_T4160:
+ case SVR_T4080:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T1040:
return IS_SVR_REV(svr, 1, 0);
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0);
case SVR_P5040:
return IS_SVR_REV(svr, 1, 0);
}
#if defined(CONFIG_B4860QDS) || \
defined(CONFIG_T4240QDS) || \
defined(CONFIG_T2080QDS) || \
+ defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
- defined(CONFIG_T1040RDB)
+ defined(CONFIG_T104xRDB)
#define CONFIG_SYS_CPC_REINIT_F
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
+#define SVR_T4080 0x824102
#define SVR_C291 0x850000
#define SVR_C292 0x850020
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
+#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
- bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
CONFIG_ARCH_DEVICE_TREE := sandbox
+
+# Define this to avoid linking with SDL, which requires SDL libraries
+# This can solve 'sdl-config: Command not found' errors
+ifneq ($(NO_SDL),)
+PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL
+endif
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_SANDBOX_ARCH
/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned int bi_baudrate; /* Console Baudrate */
unsigned long bi_boot_params; /* where this board expects params */
} bd_t;
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();
#include <config.h>
+#define TIMER_BASE_CLK 1000000
+#define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
+
DECLARE_GLOBAL_DATA_PTR;
/* reset CPU (jump to 0, without reset) */
while (get_timer(start) < ticks) ;
}
-/* initiate and setup timer0 interrupt to 1MHz
+/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
* Return irq number for timer int or a negative number for
* dealing with self
*/
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
- /* 1ms ticks */
+ /* SYS_HZ ticks per second */
leon2->Timer_Counter_1 = 0;
- leon2->Timer_Reload_1 = 999; /* (((1000000 / 100) - 1)) */
+ leon2->Timer_Reload_1 = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
leon2->Timer_Control_1 =
(LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD);
return LEON2_TIMER1_IRQNO;
}
+ulong get_tbclk(void)
+{
+ return TIMER_BASE_CLK;
+}
+
/*
* This function is intended for SHORT delays only.
*/
unsigned long cpu_usec2ticks(unsigned long usec)
{
- /* timer set to 1kHz ==> 1 clk tick = 1 msec */
- if (usec < 1000)
+ if (usec < US_PER_TICK)
return 1;
- return (usec / 1000);
+ return usec / US_PER_TICK;
}
unsigned long cpu_ticks2usec(unsigned long ticks)
{
- /* 1tick = 1usec */
- return ticks * 1000;
+ return ticks * US_PER_TICK;
}
#include <config.h>
+#define TIMER_BASE_CLK 1000000
+#define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
+
DECLARE_GLOBAL_DATA_PTR;
/* reset CPU (jump to 0, without reset) */
while (get_timer(start) < ticks) ;
}
-/* initiate and setup timer0 interrupt to 1MHz
+/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
* Return irq number for timer int or a negative number for
* dealing with self
*/
int timer_interrupt_init_cpu(void)
{
- /* 1ms ticks */
+ /* SYS_HZ ticks per second */
gptimer->e[0].val = 0;
- gptimer->e[0].rld = 999; /* (((1000000 / 100) - 1)) */
+ gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
gptimer->e[0].ctrl =
(LEON3_GPTIMER_EN |
LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
return gptimer_irq;
}
+ulong get_tbclk(void)
+{
+ return TIMER_BASE_CLK;
+}
+
/*
* This function is intended for SHORT delays only.
*/
unsigned long cpu_usec2ticks(unsigned long usec)
{
- /* timer set to 1kHz ==> 1 clk tick = 1 msec */
- if (usec < 1000)
+ if (usec < US_PER_TICK)
return 1;
- return (usec / 1000);
+ return usec / US_PER_TICK;
}
unsigned long cpu_ticks2usec(unsigned long ticks)
{
- /* 1tick = 1usec */
- return ticks * 1000;
+ return ticks * US_PER_TICK;
}
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
env_init();
getenv_f("boot_os", s, sizeof(s));
- if ((s != NULL) && (strcmp(s, "yes") == 0))
+ if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
+ *s == 't' || *s == 'T'))
return 0;
return 1;
{
unsigned int reg;
-#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
-#endif
acadia_gpio_init();
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
- board/amcc/bamboo/init.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/amcc/canyonlands/init.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x20000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x80000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/amcc/sequoia/init.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
* Spartan2 code is used to download our Spartan 3 :) code is compatible.
* Just take care about the file size
*/
-Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
+xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_pre_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_fn,
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_spartan3,
slave_parallel,
1196128l/8,
(void *)&fpga_fns,
0,
+ &spartan3_op,
"3s200aft256"}
};
}
/* Set the FPGA's PROG_B line to the specified level */
-int xilinx_pgm_fn(int assert, int flush, int cookie)
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
-int xilinx_init_fn(int cookie)
+int xilinx_init_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
}
/* Test the state of the active-high FPGA DONE pin */
-int xilinx_done_fn(int cookie)
+int xilinx_done_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
}
/* Abort an FPGA operation */
-int xilinx_abort_fn(int cookie)
+int xilinx_abort_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
/* ensure all SPI peripherals and FPGAs are deselected */
return rc;
}
-int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
return assert_clk;
}
-int xilinx_wr_fn(int assert_write, int flush, int cookie)
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
return assert_write;
}
-int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
{
size_t bytecount = 0;
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
* relocated at runtime.
* FIXME: relocation not yet working for coldfire, see below!
*/
-Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
- xilinx_pgm_fn,
- xilinx_clk_fn,
- xilinx_init_fn,
- xilinx_done_fn,
- xilinx_wr_fn,
+ xilinx_pgm_config_fn,
+ xilinx_clk_config_fn,
+ xilinx_init_config_fn,
+ xilinx_done_config_fn,
+ xilinx_wr_config_fn,
0,
- xilinx_fastwr_fn
+ xilinx_fastwr_config_fn
};
-Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)&xilinx_fns,
- 0}
+ 0,
+ &spartan3_op}
};
/* Initialize the fpga. Return 1 on success, 0 on failure. */
* so set stuff here instead of static initialisation:
*/
xilinx_fns.pre = xilinx_pre_config_fn;
- xilinx_fns.pgm = xilinx_pgm_fn;
- xilinx_fns.clk = xilinx_clk_fn;
- xilinx_fns.init = xilinx_init_fn;
- xilinx_fns.done = xilinx_done_fn;
- xilinx_fns.wr = xilinx_wr_fn;
- xilinx_fns.bwr = xilinx_fastwr_fn;
+ xilinx_fns.pgm = xilinx_pgm_config_fn;
+ xilinx_fns.clk = xilinx_clk_config_fn;
+ xilinx_fns.init = xilinx_init_config_fn;
+ xilinx_fns.done = xilinx_done_config_fn;
+ xilinx_fns.wr = xilinx_wr_config_fn;
+ xilinx_fns.bwr = xilinx_fastwr_config_fn;
xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
fpga_add(fpga_xilinx, &xilinx_fpga[i]);
}
#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
#define _PINMUX_CONFIG_TAMONTEN_NG_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tamonten_ng_pinmux_common[] = {
+static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = {
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS6_N, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, RSVD1, UP, NORMAL, INPUT),
/* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C4 pinmux */
- I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* Power I2C pinmux */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* UART1 */
- DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
/* UART2 */
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
/* UART3 */
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
/* UART4 */
- DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DIR, UARTD, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
/* DAP */
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
/* I2S1 */
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
/* SPDIF */
- DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
/* I2S2 */
- DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
/* DAP4 */
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
/* Tamonten GPIO */
- DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, RSVD1, NORMAL, NORMAL, INPUT),
/* LCD */
- DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
/* BT656 */
- LV_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D11, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
/* GPIOs */
- DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, INPUT),
/* LCD BL */
- DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, RSVD4, NORMAL, NORMAL, OUTPUT),
/* SPI4 */
- DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
/* Video input GPIO */
- DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, NORMAL, INPUT),
/* Sensor GPIO */
- DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, NORMAL, INPUT),
/* JTAG */
- DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
/* Power controls */
- DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, INPUT),
/* SPI1 */
- DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
/* PMU */
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
/* PCI */
- DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/* HDMI */
- DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
};
-static struct pingroup_config unused_pins_lowpower[] = {
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
/* UART1 - NC */
- DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT),
/* UART2 - NC */
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
/* DAP - NC */
- DEFAULT_PINMUX(CLK1_REQ, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, NORMAL, INPUT),
/* DAP4 - NC */
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
/* Tamonten GPIO - NC */
- DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
/* BT656 - NC */
- LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
/* GPIO - NC */
- DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, RSVD1, NORMAL, NORMAL, INPUT),
/* Video input - NC */
- DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW11, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, RSVD1, NORMAL, NORMAL, INPUT),
/* KBC keys - NC */
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
/* PMU - NC */
- DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, RSVD1, NORMAL, NORMAL, INPUT),
/* Power rails GPIO - NC */
- DEFAULT_PINMUX(SPI2_SCK, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_SCK_PX2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, RSVD1, NORMAL, NORMAL, INPUT),
/* Others - NC */
- DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
};
-static struct padctrl_config tamonten_ng_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config tamonten_ng_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
};
void pinmux_init(void)
{
- pinmux_config_table(tamonten_ng_pinmux_common,
- ARRAY_SIZE(tamonten_ng_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
- ARRAY_SIZE(unused_pins_lowpower));
+ pinmux_config_pingrp_table(tamonten_ng_pinmux_common,
+ ARRAY_SIZE(tamonten_ng_pinmux_common));
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(tamonten_ng_padctrl,
- ARRAY_SIZE(tamonten_ng_padctrl));
+ pinmux_config_drvgrp_table(tamonten_ng_padctrl,
+ ARRAY_SIZE(tamonten_ng_padctrl));
}
void gpio_early_init(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
/* for write-protect GPIO PI6 */
- pinmux_tristate_disable(PINGRP_ATA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* for CD GPIO PH2 */
- pinmux_tristate_disable(PINGRP_ATD);
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
}
#endif
return assert_clk;
}
-Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
(void *)&balloon3_fpga_fns, 0);
/* Initialize the FPGA */
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/gpio.h>
-#include <asm/net.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <netdev.h>
#include <spi.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
DECLARE_GLOBAL_DATA_PTR;
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
DECLARE_GLOBAL_DATA_PTR;
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <net.h>
#include <asm/mach-common/bits/bootrom.h>
#include <netdev.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
printf("Entering rescue mode..\n");
#ifdef CONFIG_RANDOM_MACADDR
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- eth_random_enetaddr(enetaddr);
+ eth_random_addr(enetaddr);
if (eth_setenv_enetaddr("ethaddr", enetaddr)) {
printf("Failed to set ethernet address\n");
set_led(LED_ALARM_BLINKING);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include "gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}
void pin_mux_mmc(void)
{
/* SDMMC4: config 3, x8 on 2nd set of pins */
- pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PINGRP_ATB);
- pinmux_tristate_disable(PINGRP_GMA);
- pinmux_tristate_disable(PINGRP_GME);
+ pinmux_tristate_disable(PMUX_PINGRP_ATB);
+ pinmux_tristate_disable(PMUX_PINGRP_GMA);
+ pinmux_tristate_disable(PMUX_PINGRP_GME);
/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
- pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
- pinmux_tristate_disable(PINGRP_SDIO1);
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
/* For power GPIO PV1 */
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
/* For CD GPIO PV5 */
- pinmux_tristate_disable(PINGRP_GPV);
+ pinmux_tristate_disable(PMUX_PINGRP_GPV);
}
#endif
debug("init display pinmux\n");
/* EN_VDD_PANEL GPIO A4 */
- pinmux_tristate_disable(PINGRP_DAP2);
+ pinmux_tristate_disable(PMUX_PINGRP_DAP2);
}
#endif
* USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
* in the current device tree.
*/
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
void pin_mux_spi(void)
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
/* For CD GPIO PP1 */
- pinmux_tristate_disable(PINGRP_DAP3);
+ pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifndef RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS 0xfffffffc
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <net.h>
#include <netdev.h>
#include <asm/gpio.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#define USE_SP_CODE
#ifdef USE_SP_CODE
-Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_config_fn,
};
#else
-Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
};
#endif
-Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
+xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_pre_config_fn,
ngcc_fpga_pgm_fn,
ngcc_fpga_clk_fn,
ngcc_fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(
#ifdef USE_SP_CODE
slave_parallel,
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/idt8t49n222a_serdes_clk.h"
+#include "../common/zm7300.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
return 0;
}
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_last;
+ int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
+ int ret;
+ unsigned int orig_i2c_speed;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+ debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
+ vid, vdd_target/10);
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("b4qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 && vdd_override <= 1212) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ if (vdd_target == 0) {
+ printf("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ * Voltage monitor LSB is 4mv.
+ */
+ vdd_last = read_voltage();
+ if (vdd_last < 0) {
+ printf("VID: abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+
+ debug("VID: Core voltage is at %d mV\n", vdd_last);
+ ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
+ if (ret) {
+ printf("VID: I2c failed to switch channel to DPM\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* Round up to the value of step of Voltage regulator */
+ voltage = roundup(vdd_target, ZM_STEP);
+ debug("VID: rounded up voltage = %d\n", voltage);
+
+ /* lower the speed to 100kHz to access ZM7300 device */
+ debug("VID: Setting bus speed to 100KHz if not already set\n");
+ orig_i2c_speed = i2c_get_bus_speed();
+ if (orig_i2c_speed != 100000)
+ i2c_set_bus_speed(100000);
+
+ /* Read the existing level on board, if equal to requsted one,
+ no need to re-set */
+ existing_voltage = zm_read_voltage();
+
+ /* allowing the voltage difference of one step 0.0125V acceptable */
+ if ((existing_voltage >= voltage) &&
+ (existing_voltage < (voltage + ZM_STEP))) {
+ debug("VID: voltage already set as requested,returning\n");
+ ret = existing_voltage;
+ goto out;
+ }
+ debug("VID: Changing voltage for board from %dmV to %dmV\n",
+ existing_voltage/10, voltage/10);
+
+ if (zm_disable_wp() < 0) {
+ ret = -1;
+ goto out;
+ }
+ /* Change Voltage: the change is done through all the steps in the
+ way, to avoid reset to the board due to power good signal fail
+ in big voltage change gap jump.
+ */
+ if (existing_voltage > voltage) {
+ temp_voltage = existing_voltage - ZM_STEP;
+ while (temp_voltage >= voltage) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage -= ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping down vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ } else {
+ temp_voltage = existing_voltage + ZM_STEP;
+ while (temp_voltage < (voltage + ZM_STEP)) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage += ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping up vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ }
+
+ if (zm_enable_wp() < 0)
+ ret = -1;
+
+ /* restore the speed to 400kHz */
+out: debug("VID: Restore the I2C bus speed to %dKHz\n",
+ orig_i2c_speed/1000);
+ i2c_set_bus_speed(orig_i2c_speed);
+ if (ret < 0)
+ goto exit;
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_last = read_voltage();
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage %d mV\n", vdd_last);
+ else
+ ret = -1;
+
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
int configure_vsc3316_3308(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0) < 0)
+ printf("Warning: Adjusting core voltage failed\n");
+
/* SerDes1 refclks need to be set again, as default clks
* are not suitable for CPRI and onboard SGMIIs to work
* simultaneously.
obj-$(CONFIG_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_ZM7300) += zm7300.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
/* some boards with non-256-bytes EEPROM have special define */
/* for MAX_NUM_PORTS in board-specific file */
#ifndef MAX_NUM_PORTS
-#define MAX_NUM_PORTS 23
+#define MAX_NUM_PORTS 16
#endif
#define NXID_VERSION 1
#endif
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
- u32 crc; /* x+1 CRC32 checksum */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */
+ u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
+ u32 crc; /* 0xfc - 0xff CRC32 checksum */
#endif
} e;
if (read_eeprom()) {
printf("Read failed.\n");
- return -1;
+ return 0;
}
if (!is_valid) {
printf("Invalid ID (%02x %02x %02x %02x)\n",
e.id[0], e.id[1], e.id[2], e.id[3]);
- return -1;
+ return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
crcp = (void *)&e + crc_offset;
if (crc != be32_to_cpu(*crcp)) {
printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
- return -1;
+ return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power-One ZM7300 DPM */
+#include "zm7300.h"
+
+#define DPM_WP 0x96
+#define WRP_OPCODE 0x01
+#define WRM_OPCODE 0x02
+#define RRP_OPCODE 0x11
+
+#define DPM_SUCCESS 0x01
+#define DPM_EXEC_FAIL 0x00
+
+static const uint16_t hex_to_1_10mv[] = {
+ 5000,
+ 5125,
+ 5250,
+ 5375,
+ 5500,
+ 5625,
+ 5750,
+ 5875,
+ 6000,
+ 6125,
+ 6250,
+ 6375,
+ 6500,
+ 6625,
+ 6750,
+ 6875,
+ 7000,
+ 7125,
+ 7250,
+ 7375,
+ 7500,
+ 7625,
+ 7750,
+ 7875,
+ 8000,
+ 8125,
+ 8250,
+ 8375,
+ 8500,
+ 8625,
+ 8750,
+ 8875,
+ 9000,
+ 9125,
+ 9250,
+ 9375,
+ 9500, /* 0.95mV */
+ 9625,
+ 9750,
+ 9875,
+ 10000, /* 1.0V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 11125,
+ 11250,
+ 11375,
+ 11500,
+ 11625,
+ 11750,
+ 11875,
+ 12000,
+ 12125,
+ 12250,
+ 12375,
+ 0, /* reserved */
+};
+
+
+/* Read Data d from Register r of POL p */
+u8 dpm_rrp(uchar r)
+{
+ u8 ret[5];
+
+ ret[0] = RRP_OPCODE;
+ /* POL is 0 */
+ ret[1] = 0;
+ ret[2] = r;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
+ if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("RRP_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into DPM register r (RAM) */
+int dpm_wrm(u8 r, u8 d)
+{
+ u8 ret[5];
+
+ ret[0] = WRM_OPCODE;
+ ret[1] = r;
+ ret[2] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRM_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into Register r of POL(s) a */
+int dpm_wrp(u8 r, u8 d)
+{
+ u8 ret[7];
+
+ ret[0] = WRP_OPCODE;
+ /* only POL0 is present */
+ ret[1] = 0x01;
+ ret[2] = 0x00;
+ ret[3] = 0x00;
+ ret[4] = 0x00;
+ ret[5] = r;
+ ret[6] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRP_OPCODE returned success data is %x\n", ret[0]);
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+/* Uses the DPM command RRP */
+u8 zm_read(uchar reg)
+{
+ u8 d;
+ d = dpm_rrp(reg);
+ return d;
+}
+
+/* ZM_write --
+ Steps:
+ a. Write data to the register
+ b. Read data from register and compare to written value
+ c. Return return_code & voltage_read
+*/
+u8 zm_write(u8 reg, u8 data)
+{
+ u8 d;
+
+ /* write data to register */
+ dpm_wrp(reg, data);
+
+ /* read register and compare to written value */
+ d = dpm_rrp(reg);
+ if (d != data) {
+ printf("zm_write : Comparison register data failed\n");
+ return -1;
+ }
+
+ return d;
+}
+
+/* zm_write_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_write_voltage(int voltage)
+{
+ u8 reg = 0x7, vid;
+ uint16_t voltage_read;
+ u8 ret;
+
+ vid = (voltage - 5000) / ZM_STEP;
+
+ ret = zm_write(reg, vid);
+ if (ret != -1) {
+ voltage_read = hex_to_1_10mv[ret];
+ debug("voltage set to %dmV\n", voltage_read/10);
+ return voltage_read;
+ }
+ return -1;
+}
+
+/* zm_read_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_read_voltage(void)
+{
+ u8 reg = 0x7;
+ u8 ret;
+ int voltage;
+
+ ret = zm_read(reg);
+ if (ret != -1) {
+ voltage = hex_to_1_10mv[ret];
+ debug("Voltage read is %dmV\n", voltage/10);
+ return voltage;
+ } else {
+ return -1;
+ }
+}
+
+int zm_disable_wp()
+{
+ u8 new_wp_value;
+
+ /* Disable using Write-Protect register 0x96 */
+ new_wp_value = 0x8;
+ if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
+ printf("Disable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
+int zm_enable_wp()
+{
+ u8 orig_wp_value;
+ orig_wp_value = 0x0;
+
+ /* Enable using Write-Protect register 0x96 */
+ if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
+ printf("Enable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ZM7300_H_
+#define __ZM7300_H 1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define ZM_STEP 125
+int zm7300_set_voltage(int voltage_1_10mv);
+int zm_write_voltage(int voltage);
+int zm_read_voltage(void);
+int zm_disable_wp(void);
+int zm_enable_wp(void);
+
+#endif /* __ZM7300_H_ */
# SPDX-License-Identifier: GPL-2.0+
#
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-y += p1_p2_rdb.o
+obj-$(CONFIG_PCI) += pci.o
+endif
obj-y += ddr.o
obj-y += law.o
-obj-$(CONFIG_PCI) += pci.o
obj-y += tlb.o
+
+endif
phys_size_t fixed_sdram (void)
{
- char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
cpu = gd->arch.cpu;
- /* P1020 and it's derivatives support max 32bit DDR width */
- if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
- ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
- } else {
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- }
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
#if defined(CONFIG_SYS_RAMBOOT)
return ddr_size;
#endif
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
if(ddr_freq_mhz <= 400)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(ddr_freq_mhz <= 800)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = bus_clk;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
0, 4, BOOKE_PAGESZ_256K, 1),
#endif /* #if defined(CONFIG_PCI) */
+#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1G, 1)
get_sys_info(&sys_info);
return sys_info.freq_systembus;
}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+ /*
+ * The QEMU u-boot target only needs to drive the first core,
+ * spinning and device tree nodes get driven by QEMU itself
+ */
+ return 1;
+}
+
+/*
+ * Return a 32-bit mask indicating which cores are present on this SOC.
+ */
+u32 cpu_mask(void)
+{
+ return (1 << cpu_numcores()) - 1;
+}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
+ /* does not provide HW signals for power management */
+ CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += ddr.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data\n"
+ "rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+
+#include "../common/fman.h"
+#include "t4rdb.h"
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ if (srds_prtcl_s1 == 28) {
+ /* SGMII */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
+ fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
+ } else {
+ puts("Invalid SerDes1 protocol for T4240RDB\n");
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ if (srds_prtcl_s2 == 56) {
+ /* SGMII && XFI */
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
+ } else {
+ puts("Invalid SerDes2 protocol for T4240RDB\n");
+ }
+
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t4rdb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ printf("Board: %sRDB, ", cpu->name);
+
+ puts("SERDES Reference Clocks:\n");
+ printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
+ " SERDES3=100MHz SERDES4=100MHz\n");
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
+
+/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name> = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock : Critical clocks which are not printed already
+ * RCW : RCW source if not printed already
+ * Misc : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+ int rcwsrc;
+
+ /* RCW section SW3[4] */
+ rcwsrc = 0x0;
+ puts("RCW source = ");
+ switch (rcwsrc & 0x1) {
+ case 0x1:
+ puts("SDHC/eMMC\n");
+ break;
+ default:
+ puts("I2C normal addressing\n");
+ break;
+ }
+}
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#slow mdio clock
+095fc030 00008148
+095fd030 00808148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 28_56_2_10
+16070019 18101916 00000000 00000000
+70701050 00448c00 6c020000 f5000000
+00000000 ee0000ee 00000000 000287fc
+00000000 50000000 00000000 00000028
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T4RDB_H__
+#define __T4RDB_H__
+
+#undef CONFIG_SYS_NUM_FM1_DTSEC
+#undef CONFIG_SYS_NUM_FM2_DTSEC
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM2_DTSEC 4
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 512K SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
/* Note that these are pointers to code that is in Flash. They will be
* relocated at runtime.
*/
-Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Virtex2,
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *) &fpga_fns,
#include <common.h>
#include <net.h>
#include <netdev.h>
-#include <asm/net.h>
int checkboard(void)
{
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr("ethaddr", enetaddr);
}
#define ZL30158_RST 8
-#define ZL30343_RST 9
+#define BFTIC4_RST 0
int board_early_init_f(void)
{
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
- /* take the Zarlinks out of reset as soon as possible */
- qrio_prst(ZL30158_RST, false, false);
- qrio_prst(ZL30343_RST, false, false);
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
- /* and set their reset to power-up only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
return 0;
}
if (ret)
printf("error triggering PCIe FPGA config\n");
+ /* enable the Unit LED (red) & Boot LED (on) */
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
return ret;
}
return 66666666;
}
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
+
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+ /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
+
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
+
return 0;
}
#define NUM_SRDS_BANKS 2
-#define PHY_RST 15
int misc_init_r(void)
{
}
}
- /* take the mgmt eth phy out of reset */
- qrio_prst(PHY_RST, false, false);
-
return 0;
}
#endif
#if defined(CONFIG_LAST_STAGE_INIT)
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMCOGE4)
+ /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+ u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
set_km_env();
+
return 0;
}
#endif
fdt_fixup_fman_mac_addresses(blob);
#endif
}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
#define PRSTCFG_POWUP_RST 0x3
void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_wdmask(u8 bit, bool wden);
void qrio_prstcfg(u8 bit, u8 mode);
+void qrio_set_leds(void);
+void qrio_enable_app_buffer(void);
void pci_of_setup(void *blob, bd_t *bd);
#
#PBI commands
-#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
-#Freescale's errarta sheet suggests it may be done with PBI
+#Configure ALTCBAR for DCSR -> DCSR@89000000
+091380c0 000009C4
09000010 00000000
+091380c0 000009C4
09000014 00000000
+091380c0 000009C4
09000018 81d00000
-09021008 0000f000
-09021028 0000f000
-09021048 0000f000
-09021068 0000f000
+#Workaround for A-004849
+091380c0 000009C4
+890B0050 00000002
+091380c0 000009C4
+890B0054 00000002
+091380c0 000009C4
+890B0058 00000002
+091380c0 000009C4
+890B005C 00000002
+091380c0 000009C4
+890B0090 00000002
+091380c0 000009C4
+890B0094 00000002
+091380c0 000009C4
+890B0098 00000002
+091380c0 000009C4
+890B009C 00000002
+091380c0 000009C4
+890B0108 00000012
+091380c0 000009C4
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+89021008 0000f000
+091380c0 000009C4
+89021028 0000f000
+091380c0 000009C4
+89021048 0000f000
+091380c0 000009C4
+89021068 0000f000
+091380c0 000009C4
+#Flush PBL data
+09138000 00000000
+#Disable ALTCBAR
09000018 00000000
+091380c0 000009C4
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000
}
#define PCIE_SW_RST 14
-#define PEXHC_SW_RST 13
-#define HOOPER_SW_RST 12
+#define PEXHC_RST 13
+#define HOOPER_RST 12
void pci_init_board(void)
{
- /* first wait for the PCIe FPGA to be configured
+ qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+
+ /* wait for the PCIe FPGA to be configured
* it has been triggered earlier in board_early_init_r */
- int ret = wait_for_fpga_config();
- if (ret)
+ if (wait_for_fpga_config())
printf("error finishing PCIe FPGA config\n");
qrio_prst(PCIE_SW_RST, false, false);
- qrio_prst(PEXHC_SW_RST, false, false);
- qrio_prst(HOOPER_SW_RST, false, false);
+ qrio_prst(PEXHC_RST, false, false);
+ qrio_prst(HOOPER_RST, false, false);
/* Hooper is not direcly PCIe capable */
mdelay(50);
#define WDMASK_OFF 0x16
-static void qrio_wdmask(u8 bit, bool wden)
+void qrio_wdmask(u8 bit, bool wden)
{
u16 wdmask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
}
+
+#define CTRLH_OFF 0x02
+#define CTRLH_WRL_BOOT 0x01
+#define CTRLH_WRL_UNITRUN 0x02
+
+void qrio_set_leds(void)
+{
+ u8 ctrlh;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* set UNIT LED to RED and BOOT LED to ON */
+ ctrlh = in_8(qrio_base + CTRLH_OFF);
+ ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
+ out_8(qrio_base + CTRLH_OFF, ctrlh);
+}
+
+#define CTRLL_OFF 0x03
+#define CTRLL_WRB_BUFENA 0x20
+
+void qrio_enable_app_buffer(void)
+{
+ u8 ctrll;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* enable application buffer */
+ ctrll = in_8(qrio_base + CTRLL_OFF);
+ ctrll |= (CTRLL_WRB_BUFENA);
+ out_8(qrio_base + CTRLL_OFF, ctrll);
+}
#64 bytes RCW data
14600000 00000000 28200000 00000000
148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F0428002
+00000000 00000000 00000000 F0428816
00000000 00000000 00000000 00000000
# (mem base + reserved)
# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
+#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
+/* gpmc_cfg is initialized by gpmc_init and we use it here */
+extern struct gpmc *gpmc_cfg;
+
+/* GPMC definitions for Ethenet Controller LAN9211 */
+static const u32 gpmc_lab_enet[] = {
+ ZOOM1_ENET_GPMC_CONF1,
+ ZOOM1_ENET_GPMC_CONF2,
+ ZOOM1_ENET_GPMC_CONF3,
+ ZOOM1_ENET_GPMC_CONF4,
+ ZOOM1_ENET_GPMC_CONF5,
+ ZOOM1_ENET_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
/*
* Routine: board_init
* Description: Early hardware init.
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* CS1 is Ethernet LAN9211 */
+ enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
+ DEBUG_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
/* boot param addr */
int board_eth_init(bd_t *bis)
{
int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+
+#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR "ethaddr"
+
+ struct eth_device *dev;
+ uchar eth_addr[6];
+
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+ dev = eth_get_dev_by_index(0);
+ if (dev) {
+ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+ } else {
+ printf("zoom1: Couldn't get eth device\n");
+ rc = -1;
+ }
+ }
#endif
+
return rc;
}
#endif
"NAND",
};
+#define ZOOM1_ENET_GPMC_CONF1 0x00611000
+#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01
+#define ZOOM1_ENET_GPMC_CONF3 0x00080803
+#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09
+#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F
+#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4
+
/*
* IEN - Input Enable
* IDIS - Input Disable
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
#include "fpga.h"
#include "mvsmr.h"
-Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+xilinx_spartan3_slave_serial_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
0
};
-Xilinx_desc spartan3 = {
- Xilinx_Spartan2,
+xilinx_desc spartan3 = {
+ xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
(void *) &fpga_fns,
}
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* update "memory" property in the blob
*/
/* baudrate */
nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial");
if (nodeoffset >= 0) {
- speed = cpu_to_be32 (bd->bi_baudrate);
+ speed = cpu_to_be32 (gd->baudrate);
ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed,
sizeof (unsigned long));
if (ret < 0)
u32 BoardType = get_BoardType ();
char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
char *p;
- bd_t *bd = gd->bd;
hw_watchdog_reset ();
if ((p = getenv ("console_nr")) != NULL) {
unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
- bd->bi_baudrate &= ~3;
- bd->bi_baudrate |= con_nr & 3;
+ gd->baudrate &= ~3;
+ gd->baudrate |= con_nr & 3;
}
return 0;
}
*/
void pinmux_init(void)
{
- pinmux_config_table(tegra3_pinmux_common,
+ pinmux_config_pingrp_table(tegra3_pinmux_common,
ARRAY_SIZE(tegra3_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
+ pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
+ pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
}
#if defined(CONFIG_TEGRA_MMC)
#ifndef _PINMUX_CONFIG_CARDHU_H_
#define _PINMUX_CONFIG_CARDHU_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tegra3_pinmux_common[] = {
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
/* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* I2C4 pinmux */
- I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
/* Power I2C pinmux */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
- LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
- DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
- DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
- DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+ DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
/* KBC keys */
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
/* GPIOs */
/* SDMMC1 CD gpio */
- DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
/* SDMMC1 WP gpio */
- LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
/* Touch panel GPIO */
/* Touch IRQ */
- DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
/* Touch RESET */
- DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
/* Power rails GPIO */
- DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
- LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
};
-static struct pingroup_config unused_pins_lowpower[] = {
- DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
};
-static struct padctrl_config cardhu_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config cardhu_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
};
#endif
#ifdef CONFIG_USB_EHCI_TEGRA
#include <asm/arch-tegra/usb.h>
-#include <asm/arch/usb.h>
#include <usb.h>
#endif
#ifdef CONFIG_TEGRA_MMC
CONFIG_TEGRA_BOARD_STRING
};
+void __pinmux_init(void)
+{
+}
+
+void pinmux_init(void) __attribute__((weak, alias("__pinmux_init")));
+
void __pin_mux_usb(void)
{
}
int board_early_init_f(void)
{
-#if !defined(CONFIG_TEGRA20)
pinmux_init();
-#endif
board_init_uart_f();
/* Initialize periph GPIOs */
*/
void pinmux_init(void)
{
- pinmux_config_table(tegra114_pinmux_set_nontristate,
+ pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate,
ARRAY_SIZE(tegra114_pinmux_set_nontristate));
- pinmux_config_table(tegra114_pinmux_common,
+ pinmux_config_pingrp_table(tegra114_pinmux_common,
ARRAY_SIZE(tegra114_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
+ pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl));
+ pinmux_config_drvgrp_table(dalmore_padctrl,
+ ARRAY_SIZE(dalmore_padctrl));
}
#if defined(CONFIG_TEGRA_MMC)
#ifndef _PINMUX_CONFIG_DALMORE_H_
#define _PINMUX_CONFIG_DALMORE_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
#define USB_PINMUX CEC_PINMUX
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tegra114_pinmux_common[] = {
+static struct pmux_pingrp_config tegra114_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
/* I2S0 pinmux */
- DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
/* I2S1 pinmux */
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
/* I2S3 pinmux */
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
/* CLDVFS pinmux */
- DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
/* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* VI pinmux */
- VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* VI_ALT1 pinmux */
- VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* VGP4 pinmux */
- VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux */
- DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
/* SPI4 pinmux */
- DEFAULT_PINMUX(GMI_AD5, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD6, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD7, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS6_N, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WR_N, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT),
/* PWM1 pinmux */
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
/* SOC pinmux */
- DEFAULT_PINMUX(GMI_CS1_N, SOC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_OE_N, SOC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT),
/* EXTPERIPH2 pinmux */
- DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
/* SDMMC4 pinmux */
- DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
/* BLINK pinmux */
- DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
/* KBC pinmux */
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
/*Audio Codec*/
- DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
/* UARTA pinmux */
- DEFAULT_PINMUX(KB_ROW10, UARTA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* SYSCLK pinmux */
- DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
/* EXTPERIPH3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB pinmux */
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
/* IRDA pinmux */
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
/* UARTC pinmux */
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
/* OWR pinmux */
- DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
/* CEC pinmux */
- CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* I2C4 pinmux */
- DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
- DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
/* USB pinmux */
- USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* nct */
- DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT),
};
-static struct pingroup_config unused_pins_lowpower[] = {
- DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT),
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
-static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
- DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_W3_AUD, SPI6, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X1_AUD, RSVD3, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(DAP3_FS, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_DIN, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_SCLK, I2S2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(GPIO_PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PCC1, RSVD3, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PCC2, RSVD3, DOWN, NORMAL, INPUT),
-
- DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD10, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD12, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD13, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD8, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_ADV_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CLK, GMI, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS0_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS2_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS3_N, GMI, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS4_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS7_N, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_DQS, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_IORDY, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WP_N, GMI, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(SDMMC1_WP_N, SPI4, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
-
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(CLK3_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
-
- DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
+static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
+ DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
};
-static struct padctrl_config dalmore_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config dalmore_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};
funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
/* For power GPIO PI6 */
- pinmux_tristate_disable(PINGRP_ATA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* For CD GPIO PH2 */
- pinmux_tristate_disable(PINGRP_ATD);
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
/* For power GPIO PT3 */
- pinmux_tristate_disable(PINGRP_DTB);
+ pinmux_tristate_disable(PMUX_PINGRP_DTB);
/* For CD GPIO PI5 */
- pinmux_tristate_disable(PINGRP_ATC);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
}
#endif
void pin_mux_usb(void)
{
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
- pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
- pinmux_tristate_disable(PINGRP_CDEV2);
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
/* USB2 PHY reset GPIO */
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
void pin_mux_display(void)
{
- pinmux_set_func(PINGRP_SDC, PMUX_FUNC_PWM);
- pinmux_tristate_disable(PINGRP_SDC);
+ pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_SDC);
}
--- /dev/null
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../venice2/as3722_init.o
+obj-y += jetson-tk1.o
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-jetson-tk1.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(jetson_tk1_pingrps,
+ ARRAY_SIZE(jetson_tk1_pingrps));
+
+ pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
+ ARRAY_SIZE(jetson_tk1_drvgrps));
+}
--- /dev/null
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
+#define _PINMUX_CONFIG_JETSON_TK1_H_
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
+ PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PC7, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH2, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK1, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(GPIO_W2_AUD_PW2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, RSVD2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
+ PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_JETSON_TK1_H */
funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
/* For power GPIO PI6 */
- pinmux_tristate_disable(PINGRP_ATA);
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* For CD GPIO PI5 */
- pinmux_tristate_disable(PINGRP_ATC);
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
}
#endif
void pin_mux_usb(void)
{
/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
- pinmux_tristate_disable(PINGRP_SLXK);
+ pinmux_tristate_disable(PMUX_PINGRP_SLXK);
}
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
#define AS3722_LDCONTROL_REG 0x4E
+#ifdef CONFIG_BOARD_JETSON_TK1
+#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
+#else
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
+#endif
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
- .pingroup = PINGRP_##_pingroup, \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
-#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingroup = PINGRP_##_pingroup, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define USB_PINMUX CEC_PINMUX
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
- .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
- .lpmd = PGRP_LPMD_##_lpmd, \
- .schmt = PGRP_SCHMT_##_schmt, \
- .hsm = PGRP_HSM_##_hsm, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
}
-static struct pingroup_config tegra124_pinmux_common[] = {
+static struct pmux_pingrp_config tegra124_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
- DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
/* I2S0 pinmux */
- DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
/* I2S1 pinmux */
- DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
/* I2S3 pinmux */
- DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
/* CLDVFS pinmux */
- DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
/* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4, ULPI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5, ULPI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
/* EC KBC/SPI */
- DEFAULT_PINMUX(ULPI_CLK, SPI1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DIR, SPI1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
/* I2C3 (TPM) pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux (UART4 on Servo board, unused) */
- DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PB0, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PB1, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT),
/* SPI4 (Winbond 'boot ROM') */
- DEFAULT_PINMUX(GPIO_PG5, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG6, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG7, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PI3, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT),
/* Touch IRQ */
- DEFAULT_PINMUX(GPIO_W3_AUD, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT),
/* PWM1 pinmux */
- DEFAULT_PINMUX(GPIO_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT),
/* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
/* SDMMC4 pinmux */
- DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
/* BLINK pinmux */
- DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
/* KBC pinmux */
- DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
/* Misc */
- DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
/* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
- DEFAULT_PINMUX(KB_ROW9, UARTA, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
/* EXTPERIPH3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB, GPS */
- DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
/* UARTC (WIFI/BT) */
- DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
/* CEC pinmux */
- CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* I2C4 (HDMI_DDC) pinmux */
- DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
- DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
/* USB pinmux */
- USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* Unused, marked SNN_ on schematic, TRISTATE 'em */
- DEFAULT_PINMUX(GPIO_PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PH3, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PI7, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_X5_AUD, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_X6_AUD, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(USB_VBUS_EN2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL5, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW3, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW5, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW13, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW14, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW16, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_FS, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CLK2_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC1_WP_N, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT),
};
-static struct pingroup_config unused_pins_lowpower[] = {
- DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
-static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
- DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
+static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = {
+ DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
/* EN_VDD_BL */
- DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
/* MODEM */
- DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
/* BOOT_SEL0-3 */
- DEFAULT_PINMUX(GPIO_PG0, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG1, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG2, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PG3, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
/* TS_SHDN_L */
- DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT),
};
-static struct padctrl_config venice2_padctrl[] = {
- /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config venice2_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};
*/
void pinmux_init(void)
{
- pinmux_config_table(tegra124_pinmux_set_nontristate,
- ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+ pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
+ ARRAY_SIZE(tegra124_pinmux_set_nontristate));
- pinmux_config_table(tegra124_pinmux_common,
- ARRAY_SIZE(tegra124_pinmux_common));
+ pinmux_config_pingrp_table(tegra124_pinmux_common,
+ ARRAY_SIZE(tegra124_pinmux_common));
- pinmux_config_table(unused_pins_lowpower,
- ARRAY_SIZE(unused_pins_lowpower));
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
- padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
+ pinmux_config_drvgrp_table(venice2_padctrl,
+ ARRAY_SIZE(venice2_padctrl));
}
--- /dev/null
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Native Execution of U-Boot
+==========================
+
+The 'sandbox' architecture is designed to allow U-Boot to run under Linux on
+almost any hardware. To achieve this it builds U-Boot (so far as possible)
+as a normal C application with a main() and normal C libraries.
+
+All of U-Boot's architecture-specific code therefore cannot be built as part
+of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test
+all the generic code, not specific to any one architecture. The idea is to
+create unit tests which we can run to test this upper level code.
+
+CONFIG_SANDBOX is defined when building a native board.
+
+The chosen vendor and board names are also 'sandbox', so there is a single
+board in board/sandbox/sandbox.
+
+CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
+machines.
+
+Note that standalone/API support is not available at present.
+
+
+Basic Operation
+---------------
+
+To run sandbox U-Boot use something like:
+
+ make sandbox_config all
+ ./u-boot
+
+Note:
+ If you get errors about 'sdl-config: Command not found' you may need to
+ install libsdl1.2-dev or similar to get SDL support. Alternatively you can
+ build sandbox without SDL (i.e. no display/keyboard support) by removing
+ the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:
+
+ make sandbox_config all NO_SDL=1
+ ./u-boot
+
+
+U-Boot will start on your computer, showing a sandbox emulation of the serial
+console:
+
+
+U-Boot 2014.04 (Mar 20 2014 - 19:06:00)
+
+DRAM: 128 MiB
+Using default environment
+
+In: serial
+Out: lcd
+Err: lcd
+=>
+
+You can issue commands as your would normally. If the command you want is
+not supported you can add it to include/configs/sandbox.h.
+
+To exit, type 'reset' or press Ctrl-C.
+
+
+Console / LCD support
+---------------------
+
+Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the
+sandbox with LCD and keyboard emulation, using something like:
+
+ ./u-boot -d u-boot.dtb -l
+
+This will start U-Boot with a window showing the contents of the LCD. If
+that window has the focus then you will be able to type commands as you
+would on the console. You can adjust the display settings in the device
+tree file - see arch/sandbox/dts/sandbox.dts.
+
+
+Command-line Options
+--------------------
+
+Various options are available, mostly for test purposes. Use -h to see
+available options. Some of these are described below.
+
+The terminal is normally in what is called 'raw-with-sigs' mode. This means
+that you can use arrow keys for command editing and history, but if you
+press Ctrl-C, U-Boot will exit instead of handling this as a keypress.
+
+Other options are 'raw' (so Ctrl-C is handled within U-Boot) and 'cooked'
+(where the terminal is in cooked mode and cursor keys will not work, Ctrl-C
+will exit).
+
+As mentioned above, -l causes the LCD emulation window to be shown.
+
+A device tree binary file can be provided with -d. If you edit the source
+(it is stored at arch/sandbox/dts/sandbox.dts) you must rebuild U-Boot to
+recreate the binary file.
+
+To execute commands directly, use the -c option. You can specify a single
+command, or multiple commands separated by a semicolon, as is normal in
+U-Boot. Be careful with quoting as the shall will normally process and
+swallow quotes. When -c is used, U-Boot exists after the command is complete,
+but you can force it to go to interactive mode instead with -i.
+
+
+Memory Emulation
+----------------
+
+Memory emulation is supported, with the size set by CONFIG_SYS_SDRAM_SIZE.
+The -m option can be used to read memory from a file on start-up and write
+it when shutting down. This allows preserving of memory contents across
+test runs. You can tell U-Boot to remove the memory file after it is read
+(on start-up) with the --rm_memory option.
+
+To access U-Boot's emulated memory within the code, use map_sysmem(). This
+function is used throughout U-Boot to ensure that emulated memory is used
+rather than the U-Boot application memory. This provides memory starting
+at 0 and extending to the size of the emulation.
+
+
+Storing State
+-------------
+
+With sandbox you can write drivers which emulate the operation of drivers on
+real devices. Some of these drivers may want to record state which is
+preserved across U-Boot runs. This is particularly useful for testing. For
+example, the contents of a SPI flash chip should not disappear just because
+U-Boot exits.
+
+State is stored in a device tree file in a simple format which is driver-
+specific. You then use the -s option to specify the state file. Use -r to
+make U-Boot read the state on start-up (otherwise it starts empty) and -w
+to write it on exit (otherwise the stored state is left unchanged and any
+changes U-Boot made will be lost). You can also use -n to tell U-Boot to
+ignore any problems with missing state. This is useful when first running
+since the state file will be empty.
+
+The device tree file has one node for each driver - the driver can store
+whatever properties it likes in there. See 'Writing Sandbox Drivers' below
+for more details on how to get drivers to read and write their state.
+
+
+Running and Booting
+-------------------
+
+Since there is no machine architecture, sandbox U-Boot cannot actually boot
+a kernel, but it does support the bootm command. Filesystems, memory
+commands, hashing, FIT images, verified boot and many other features are
+supported.
+
+When 'bootm' runs a kernel, sandbox will exit, as U-Boot does on a real
+machine. Of course in this case, no kernel is run.
+
+It is also possible to tell U-Boot that it has jumped from a temporary
+previous U-Boot binary, with the -j option. That binary is automatically
+removed by the U-Boot that gets the -j option. This allows you to write
+tests which emulate the action of chain-loading U-Boot, typically used in
+a situation where a second 'updatable' U-Boot is stored on your board. It
+is very risky to overwrite or upgrade the only U-Boot on a board, since a
+power or other failure will brick the board and require return to the
+manufacturer in the case of a consumer device.
+
+
+Supported Drivers
+-----------------
+
+U-Boot sandbox supports these emulations:
+
+- Block devices
+- Chrome OS EC
+- GPIO
+- Host filesystem (access files on the host from within U-Boot)
+- Keyboard (Chrome OS)
+- LCD
+- Serial (for console only)
+- Sound (incomplete - see sandbox_sdl_sound_init() for details)
+- SPI
+- SPI flash
+- TPM (Trusted Platform Module)
+
+Notable omissions are networking and I2C.
+
+A wide range of commands is implemented. Filesystems which use a block
+device are supported.
+
+Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports
+driver model (CONFIG_DM) and associated commands.
+
+
+SPI Emulation
+-------------
+
+Sandbox supports SPI and SPI flash emulation.
+
+This is controlled by the spi_sf argument, the format of which is:
+
+ bus:cs:device:file
+
+ bus - SPI bus number
+ cs - SPI chip select number
+ device - SPI device emulation name
+ file - File on disk containing the data
+
+For example:
+
+ dd if=/dev/zero of=spi.bin bs=1M count=4
+ ./u-boot --spi_sf 0:0:M25P16:spi.bin
+
+With this setup you can issue SPI flash commands as normal:
+
+=>sf probe
+SF: Detected M25P16 with page size 64 KiB, total 2 MiB
+=>sf read 0 0 10000
+SF: 65536 bytes @ 0x0 Read: OK
+=>
+
+Since this is a full SPI emulation (rather than just flash), you can
+also use low-level SPI commands:
+
+=>sspi 0:0 32 9f
+FF202015
+
+This is issuing a READ_ID command and getting back 20 (ST Micro) part
+0x2015 (the M25P16).
+
+Drivers are connected to a particular bus/cs using sandbox's state
+structure (see the 'spi' member). A set of operations must be provided
+for each driver.
+
+
+Configuration settings for the curious are:
+
+CONFIG_SANDBOX_SPI_MAX_BUS
+ The maximum number of SPI buses supported by the driver (default 1).
+
+CONFIG_SANDBOX_SPI_MAX_CS
+ The maximum number of chip selects supported by the driver
+ (default 10).
+
+CONFIG_SPI_IDLE_VAL
+ The idle value on the SPI bus
+
+
+Writing Sandbox Drivers
+-----------------------
+
+Generally you should put your driver in a file containing the word 'sandbox'
+and put it in the same directory as other drivers of its type. You can then
+implement the same hooks as the other drivers.
+
+To access U-Boot's emulated memory, use map_sysmem() as mentioned above.
+
+If your driver needs to store configuration or state (such as SPI flash
+contents or emulated chip registers), you can use the device tree as
+described above. Define handlers for this with the SANDBOX_STATE_IO macro.
+See arch/sandbox/include/asm/state.h for documentation. In short you provide
+a node name, compatible string and functions to read and write the state.
+Since writing the state can expand the device tree, you may need to use
+state_setprop() which does this automatically and avoids running out of
+space. See existing code for examples.
+
+
+Testing
+-------
+
+U-Boot sandbox can be used to run various tests, mostly in the test/
+directory. These include:
+
+ command_ut
+ - Unit tests for command parsing and handling
+ compression
+ - Unit tests for U-Boot's compression algorithms, useful for
+ security checking. It supports gzip, bzip2, lzma and lzo.
+ driver model
+ - test/dm/test-dm.sh to run these.
+ image
+ - Unit tests for images:
+ test/image/test-imagetools.sh - multi-file images
+ test/image/test-fit.py - FIT images
+ tracing
+ - test/trace/test-trace.sh tests the tracing system (see README.trace)
+ verified boot
+ - See test/vboot/vboot_test.sh for this
+
+If you change or enhance any of the above subsystems, you shold write or
+expand a test and include it with your patch series submission. Test
+coverage in U-Boot is limited, as we need to work to improve it.
+
+Note that many of these tests are implemented as commands which you can
+run natively on your board if desired (and enabled).
+
+It would be useful to have a central script to run all of these.
+
+--
+Simon Glass <sjg@chromium.org>
+Updated 22-Mar-14
+++ /dev/null
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-Native Execution of U-Boot
-==========================
-
-The 'sandbox' architecture is designed to allow U-Boot to run under Linux on
-almost any hardware. To achieve this it builds U-Boot (so far as possible)
-as a normal C application with a main() and normal C libraries.
-
-All of U-Boot's architecture-specific code therefore cannot be built as part
-of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test
-all the generic code, not specific to any one architecture. The idea is to
-create unit tests which we can run to test this upper level code.
-
-CONFIG_SANDBOX is defined when building a native board.
-
-The chosen vendor and board names are also 'sandbox', so there is a single
-board in board/sandbox/sandbox.
-
-CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
-machines.
-
-Note that standalone/API support is not available at present.
-
-The serial driver is a very simple implementation which reads and writes to
-the console. It does not set the terminal into raw mode, so cursor keys and
-history will not work yet.
-
-
-SPI Emulation
--------------
-
-Sandbox supports SPI and SPI flash emulation.
-
-This is controlled by the spi_sf argument, the format of which is:
-
- bus:cs:device:file
-
- bus - SPI bus number
- cs - SPI chip select number
- device - SPI device emulation name
- file - File on disk containing the data
-
-For example:
-
- dd if=/dev/zero of=spi.bin bs=1M count=4
- ./u-boot --spi_sf 0:0:M25P16:spi.bin
-
-With this setup you can issue SPI flash commands as normal:
-
-=>sf probe
-SF: Detected M25P16 with page size 64 KiB, total 2 MiB
-=>sf read 0 0 10000
-SF: 65536 bytes @ 0x0 Read: OK
-=>
-
-Since this is a full SPI emulation (rather than just flash), you can
-also use low-level SPI commands:
-
-=>sspi 0:0 32 9f
-FF202015
-
-This is issuing a READ_ID command and getting back 20 (ST Micro) part
-0x2015 (the M25P16).
-
-Drivers are connected to a particular bus/cs using sandbox's state
-structure (see the 'spi' member). A set of operations must be provided
-for each driver.
-
-
-Configuration settings for the curious are:
-
-CONFIG_SANDBOX_SPI_MAX_BUS
- The maximum number of SPI buses supported by the driver (default 1).
-
-CONFIG_SANDBOX_SPI_MAX_CS
- The maximum number of chip selects supported by the driver
- (default 10).
-
-CONFIG_SPI_IDLE_VAL
- The idle value on the SPI bus
-
-
-Tests
------
-
-So far we have no tests, but when we do these will be documented here.
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
return assert_write;
}
-static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_post_config_fn,
};
-static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
};
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}
return assert_clk;
}
-Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
+xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
+xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
(void *)&mt_ventoux_fpga_fns, 0);
/* Initialize the FPGA */
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
+#include <environment.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
- return (serial_tstc() && serial_getc() == 'c');
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
}
#endif
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
+ bool generate_fake_mac = false;
/* Enable i2c2 pullup resisters */
writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
break;
case REVISION_XM_C:
printf("Beagle xM Rev C\n");
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
break;
default:
printf("Beagle unknown 0x%02x\n", get_board_revision());
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
}
switch (get_expansion_id()) {
musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
#endif
+ if (generate_fake_mac) {
+ u32 id[4];
+
+ get_dieid(id);
+ usb_fake_mac_from_die_id(id);
+ }
+
return 0;
}
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
+#include <environment.h>
#include "mux_data.h"
}
#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DRIVER_TI_CPSW
/* Delay value to add to calibrated value */
--- /dev/null
+#
+# K2HK-EVM: board Makefile
+# (C) Copyright 2012-2014
+# Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += ddr3.o
--- /dev/null
+U-Boot port for Texas Instruments XTCIEVMK2X
+============================================
+
+Author: Murali Karicheri <m-karicheri2@ti.com>
+
+This README has information on the u-boot port for XTCIEVMK2X EVM board.
+Documentation for this board can be found at
+ http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
+
+The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K.
+More details on these SoCs are available at company websites
+ K2K: http://www.ti.com/product/tci6638k2k
+ K2H: http://www.ti.com/product/tci6638k2h
+
+Board configuration:
+====================
+
+Some of the peripherals that are configured by u-boot are:-
+
+1. 2GB DDR3 (can support 8GB SO DIMM as well)
+2. 512M NAND (over ti emif16 bus)
+3. 6MB MSM SRAM (part of the SoC)
+4. two 1GBit Ethernet ports (SoC supports upto 4)
+5. two UART ports
+6. three i2c interfaces
+7. three spi interfaces (only 1 interface supported in driver)
+
+There are seperate PLLs to drive clocks to Tetris ARM and Peripherals.
+To bring up SMP Linux on this board, there is a boot monitor
+code that will be installed in MSMC SRAM. There is command available
+to install this image from u-boot.
+
+The port related files can be found at following folders
+ keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
+ K2HK evm board files: board/ti/k2hk_evm/
+
+board configuration file: include/configs/k2hk_evm.h
+
+Supported boot modes:
+ - SPI NOR boot
+
+Supported image formats:-
+ - u-boot.bin: for loading and running u-boot.bin through Texas instruments
+ code composure studio (CCS)
+ - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+
+Build instructions:
+===================
+
+To build u-boot.bin
+ >make k2hk_evm_config
+ >make u-boot-spi.gph
+
+To build u-boot-spi.gph
+ >make k2hk_evm_config
+ >make u-boot-spi.gph
+
+Load and Run U-Boot on K2HK EVM using CCS
+=========================================
+
+Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
+on EVM. See instructions at below link for installing CCS on a Windows PC.
+http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
+Installing_Code_Composer_Studio
+Use u-boot.bin from the build folder for loading annd running u-boot binary
+on EVM. Follow instructions at
+http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
+to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
+and Power ON the EVM. Follow instructions to connect serial port of EVM to
+PC and start TeraTerm or Hyper Terminal.
+
+Start CCS on a Windows machine and Launch Target
+configuration as instructed at http://processors.wiki.ti.com/index.php/
+MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
+The instructions provided in the above link uses a script for
+loading the u-boot binary on the target EVM. Instead do the following:-
+
+1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
+ isconnected: Unknown)" at the debug window (This is created once Target
+ configuration is launched) and select "Connect Target".
+2. Once target connect is successful, choose Tools->Load Memory option from the
+ top level menu. At the Load Memory window, choose the file u-boot.bin
+ through "Browse" button and click "next >" button. In the next window, enter
+ Start address as 0xc001000, choose Type-size "32 bits" and click "Finish"
+ button.
+3. Click View -> Registers from the top level menu to view registers window.
+4. From Registers, window expand "Core Registers" to view PC. Edit PC value
+ to be 0xc001000. From the "Run" top level menu, select "Free Run"
+5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
+ below and type any key to stop autoboot as instructed :=
+
+U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
+
+I2C: ready
+Detected SO-DIMM [SQR-SD3T-2G1333SED]
+DRAM: 1.1 GiB
+NAND: 512 MiB
+Net: K2HK_EMAC
+Warning: K2HK_EMAC using MAC address from net device
+, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
+Hit any key to stop autoboot: 0
+
+SPI NOR Flash programming instructions
+======================================
+U-Boot image can be flashed to first 512KB of the NOR flash using following
+instructions:-
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+ CortexA15_1 (Free Running)"
+3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+ using CCS", but using address 0x87000000.
+4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+ setenv addr_uboot 0x87000000
+ setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
+ run burn_uboot
+ Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+ to "SPI Little Endian Boot mode" as per instruction at
+ http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
--- /dev/null
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/psc_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 device_big_endian;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 125000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 125000000,
+ [ddr3a_clk] = 100000000,
+ [ddr3b_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_srio_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+ [rp1_clk] = 123456789 /* TODO: cannot find
+ what is that */
+};
+
+static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
+ { /* CS0 */
+ .mode = ASYNC_EMIF_MODE_NAND,
+ .wr_setup = 0xf,
+ .wr_strobe = 0x3f,
+ .wr_hold = 7,
+ .rd_setup = 0xf,
+ .rd_strobe = 0x3f,
+ .rd_hold = 7,
+ .turn_around = 3,
+ .width = ASYNC_EMIF_8,
+ },
+
+};
+
+static struct pll_init_data pll_config[] = {
+ CORE_PLL_1228,
+ PASS_PLL_983,
+ TETRIS_PLL_1200,
+};
+
+int dram_init(void)
+{
+ init_ddr3();
+
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2HK_EMAC",
+ .rx_flow = 22,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC1",
+ .rx_flow = 23,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC2",
+ .rx_flow = 24,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2HK_EMAC3",
+ .rx_flow = 25,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_eth_env_param(char *env_name)
+{
+ char *env;
+ int res = -1;
+
+ env = getenv(env_name);
+ if (env)
+ res = simple_strtol(env, NULL, 0);
+
+ return res;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int j;
+ int res;
+ char link_type_name[32];
+
+ for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
+ j++) {
+ sprintf(link_type_name, "sgmii%d_link_type", j);
+ res = get_eth_env_param(link_type_name);
+ if (res >= 0)
+ eth_priv_cfg[j].sgmii_link_type = res;
+
+ keystone2_emac_initialize(ð_priv_cfg[j]);
+ }
+
+ return 0;
+}
+#endif
+
+/* Byte swap the 32-bit data if the device is BE */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+ u32 i;
+
+ if (device_big_endian)
+ for (i = 0; i < length; i++, ptr++)
+ *ptr = __swab32(*ptr);
+
+ return 0;
+}
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ init_plls(ARRAY_SIZE(pll_config), pll_config);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#define K2_DDR3_START_ADDR 0x80000000
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 start[2];
+ u64 size[2];
+ char name[32], *env, *endp;
+ int lpae, nodeoffset;
+ u32 ddr3a_size;
+ int nbanks;
+
+ env = getenv("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+
+ ddr3a_size = 0;
+ if (lpae) {
+ env = getenv("ddr3a_size");
+ if (env)
+ ddr3a_size = simple_strtol(env, NULL, 10);
+ if ((ddr3a_size != 8) && (ddr3a_size != 4))
+ ddr3a_size = 0;
+ }
+
+ nbanks = 1;
+ start[0] = bd->bi_dram[0].start;
+ size[0] = bd->bi_dram[0].size;
+
+ /* adjust memory start address for LPAE */
+ if (lpae) {
+ start[0] -= K2_DDR3_START_ADDR;
+ start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+ }
+
+ if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
+ size[1] = ((u64)ddr3a_size - 2) << 30;
+ start[1] = 0x880000000;
+ nbanks++;
+ }
+
+ /* reserve memory at start of bank */
+ sprintf(name, "mem_reserve_head");
+ env = getenv(name);
+ if (env) {
+ start[0] += ustrtoul(env, &endp, 0);
+ size[0] -= ustrtoul(env, &endp, 0);
+ }
+
+ sprintf(name, "mem_reserve");
+ env = getenv(name);
+ if (env)
+ size[0] -= ustrtoul(env, &endp, 0);
+
+ fdt_fixup_memory_banks(blob, start, size, nbanks);
+
+ /* Fix up the initrd */
+ if (lpae) {
+ u64 initrd_start, initrd_end;
+ u32 *prop1, *prop2;
+ int err;
+ nodeoffset = fdt_path_offset(blob, "/chosen");
+ if (nodeoffset >= 0) {
+ prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-start", NULL);
+ prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-end", NULL);
+ if (prop1 && prop2) {
+ initrd_start = __be32_to_cpu(*prop1);
+ initrd_start -= K2_DDR3_START_ADDR;
+ initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_start = __cpu_to_be64(initrd_start);
+ initrd_end = __be32_to_cpu(*prop2);
+ initrd_end -= K2_DDR3_START_ADDR;
+ initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_end = __cpu_to_be64(initrd_end);
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-start");
+ if (err < 0)
+ puts("error deleting initrd-start\n");
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-end");
+ if (err < 0)
+ puts("error deleting initrd-end\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-start",
+ &initrd_start,
+ sizeof(initrd_start));
+ if (err < 0)
+ puts("error adding initrd-start\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-end",
+ &initrd_end,
+ sizeof(initrd_end));
+ if (err < 0)
+ puts("error adding linux,initrd-end\n");
+ }
+ }
+ }
+}
+
+void ft_board_setup_ex(void *blob, bd_t *bd)
+{
+ int lpae;
+ char *env;
+ u64 *reserve_start, size;
+
+ env = getenv("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+
+ if (lpae) {
+ /*
+ * the initrd and other reserved memory areas are
+ * embedded in in the DTB itslef. fix up these addresses
+ * to 36 bit format
+ */
+ reserve_start = (u64 *)((char *)blob +
+ fdt_off_mem_rsvmap(blob));
+ while (1) {
+ *reserve_start = __cpu_to_be64(*reserve_start);
+ size = __cpu_to_be64(*(reserve_start + 1));
+ if (size) {
+ *reserve_start -= K2_DDR3_START_ADDR;
+ *reserve_start +=
+ CONFIG_SYS_LPAE_SDRAM_BASE;
+ *reserve_start =
+ __cpu_to_be64(*reserve_start);
+ } else {
+ break;
+ }
+ reserve_start += 2;
+ }
+ }
+}
+#endif
--- /dev/null
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+/************************* *****************************/
+static struct ddr3_phy_config ddr3phy_1600_64A = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27)),
+ .dtpr0 = 0xA19DBB66ul,
+ .dtpr1 = 0x12868300ul,
+ .dtpr2 = 0x50035200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x730035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1600_64 = {
+ .sdcfg = 0x6200CE6aul,
+ .sdtim1 = 0x16709C55ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF54ul,
+ .sdtim4 = 0x553F0CFFul,
+ .zqcfg = 0xF0073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+static struct ddr3_phy_config ddr3phy_1600_32 = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27)),
+ .dtpr0 = 0xA19DBB66ul,
+ .dtpr1 = 0x12868300ul,
+ .dtpr2 = 0x50035200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x730035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1600_32 = {
+ .sdcfg = 0x6200DE6aul,
+ .sdtim1 = 0x16709C55ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF54ul,
+ .sdtim4 = 0x553F0CFFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+/************************* *****************************/
+static struct ddr3_phy_config ddr3phy_1333_64A = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
+ NOSRA_MASK | UDIMM_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x12857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1333_64 = {
+ .sdcfg = 0x62008C62ul,
+ .sdtim1 = 0x125C8044ul,
+ .sdtim2 = 0x00001D29ul,
+ .sdtim3 = 0x32CDFF43ul,
+ .sdtim4 = 0x543F0ADFul,
+ .zqcfg = 0xF0073200ul,
+ .sdrfc = 0x00001457ul,
+};
+
+static struct ddr3_phy_config ddr3phy_1333_32 = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
+ NOSRA_MASK | UDIMM_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x12857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1333_32 = {
+ .sdcfg = 0x62009C62ul,
+ .sdtim1 = 0x125C8044ul,
+ .sdtim2 = 0x00001D29ul,
+ .sdtim3 = 0x32CDFF43ul,
+ .sdtim4 = 0x543F0ADFul,
+ .zqcfg = 0xf0073200ul,
+ .sdrfc = 0x00001457ul,
+};
+
+/************************* *****************************/
+static struct ddr3_phy_config ddr3phy_1333_64 = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x12857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+/******************************************************/
+int get_dimm_params(char *dimm_name)
+{
+ u8 spd_params[256];
+ int ret;
+ int old_bus;
+
+ i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+ old_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+ i2c_set_bus_num(old_bus);
+
+ dimm_name[0] = '\0';
+
+ if (ret) {
+ puts("Cannot read DIMM params\n");
+ return 1;
+ }
+
+ /*
+ * We need to convert spd data to dimm parameters
+ * and to DDR3 EMIF and PHY regirsters values.
+ * For now we just return DIMM type string value.
+ * Caller may use this value to choose appropriate
+ * a pre-set DDR3 configuration
+ */
+
+ strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+ dimm_name[18] = '\0';
+
+ return 0;
+}
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
+
+void init_ddr3(void)
+{
+ char dimm_name[32];
+
+ get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ init_pll(&ddr3a_400);
+ if (cpu_revision() > 0) {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
+ printf("DRAM: Capacity 8 GiB (includes reported below)\n");
+ } else {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
+ printf("DRAM: Capacity 4 GiB (includes reported below)\n");
+ }
+ } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
+ init_pll(&ddr3a_333);
+ if (cpu_revision() > 0) {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
+ } else {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
+ }
+ } else {
+ printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+ while (1)
+ ;
+ }
+
+ init_pll(&ddr3b_333);
+ init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
+ init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
+}
int misc_init_r(void)
{
int reg;
- uint8_t device_mac[6];
+ u32 id[4];
#ifdef CONFIG_PALMAS_POWER
palmas_init_settings();
#endif
- if (!getenv("usbethaddr")) {
- reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
-
- /*
- * create a fake MAC address from the processor ID code.
- * first byte is 0x02 to signify locally administered.
- */
- device_mac[0] = 0x02;
- device_mac[1] = readl(reg + 0x10) & 0xff;
- device_mac[2] = readl(reg + 0xC) & 0xff;
- device_mac[3] = readl(reg + 0x8) & 0xff;
- device_mac[4] = readl(reg) & 0xff;
- device_mac[5] = (readl(reg) >> 8) & 0xff;
-
- eth_setenv_enetaddr("usbethaddr", device_mac);
- }
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ id[0] = readl(reg);
+ id[1] = readl(reg + 0x8);
+ id[2] = readl(reg + 0xC);
+ id[3] = readl(reg + 0x10);
+ usb_fake_mac_from_die_id(id);
return 0;
}
{
int phy_type;
u32 auxclk, altclksrc;
- uint8_t device_mac[6];
+ u32 id[4];
/* EHCI is not supported on ES1.0 */
if (omap_revision() == OMAP4430_ES1_0)
writel(altclksrc, &scrm->altclksrc);
- if (!getenv("usbethaddr")) {
- /*
- * create a fake MAC address from the processor ID code.
- * first byte is 0x02 to signify locally administered.
- */
- device_mac[0] = 0x02;
- device_mac[1] = readl(STD_FUSE_DIE_ID_3) & 0xff;
- device_mac[2] = readl(STD_FUSE_DIE_ID_2) & 0xff;
- device_mac[3] = readl(STD_FUSE_DIE_ID_1) & 0xff;
- device_mac[4] = readl(STD_FUSE_DIE_ID_0) & 0xff;
- device_mac[5] = (readl(STD_FUSE_DIE_ID_0) >> 8) & 0xff;
-
- eth_setenv_enetaddr("usbethaddr", device_mac);
- }
+ id[0] = readl(STD_FUSE_DIE_ID_0);
+ id[1] = readl(STD_FUSE_DIE_ID_1);
+ id[2] = readl(STD_FUSE_DIE_ID_2);
+ id[3] = readl(STD_FUSE_DIE_ID_3);
+ usb_fake_mac_from_die_id(id);
return 0;
}
/* Now we can enable our port clocks */
utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
- sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
+ setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
/* module internal USB bus to connect ethernet chipset */
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
/* ULPI reference clock output */
- pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
- pinmux_tristate_disable(PINGRP_CDEV2);
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
/* PHY reset GPIO */
- pinmux_tristate_disable(PINGRP_UAC);
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
/* VBus GPIO */
- pinmux_tristate_disable(PINGRP_DTE);
+ pinmux_tristate_disable(PMUX_PINGRP_DTE);
}
#endif
colibri_t20_common_pin_mux_usb();
/* USB 1 aka Tegra USB port 3 VBus*/
- pinmux_tristate_disable(PINGRP_SPIG);
+ pinmux_tristate_disable(PMUX_PINGRP_SPIG);
}
#endif
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
- pinmux_tristate_disable(PINGRP_GMB);
+ pinmux_tristate_disable(PMUX_PINGRP_GMB);
}
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+xilinx_desc fpga;
/* It can be done differently */
-Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
int board_init(void)
# Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers
###########################################################################################################
-Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
-Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
-Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
-Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
-Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
-Active arm arm1136 mx31 - - imx31_phycore - -
-Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
-Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at>
-Active arm arm1136 mx31 logicpd - imx31_litekit - -
-Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de>
-Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -
-Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de>
-Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de>
-Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org>
-Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
-Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org>
-Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
-Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
-Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
-Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek - Andreas Bießmann <andreas.devel@gmail.com>
-Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann <andreas.devel@gmail.com>
-Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 - Jens Scharsig <esw@bus-elektronik.de>
-Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
-Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard <eric@eukrea.com>
-Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
-Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
-Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
-Active arm arm920t ks8695 - - cm41xx - -
-Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
-Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
-Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
-Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org>
-Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com>
-Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com>
-Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com>
-Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com>
-Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com>
-Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen <voice.shen@atmel.com>
-Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
-Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
-Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com>
-Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com>
-Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com>
-Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de>
-Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de>
-Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
-Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
-Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de>
-Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard <eric@eukrea.com>
-Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at>
-Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at>
-Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at>
-Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de>
-Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de>
-Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de>
-Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
-Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
-Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx - Heiko Schocher <hs@denx.de>
-Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de>
-Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com>
-Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara <sudhakar.raj@ti.com>
-Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara <sudhakar.raj@ti.com>
-Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara <sudhakar.raj@ti.com>
-Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
-Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
-Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj <s-paulraj@ti.com>
-Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj <s-paulraj@ti.com>
-Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj <s-paulraj@ti.com>
-Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj <s-paulraj@ti.com>
-Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj <s-paulraj@ti.com>
-Active arm arm926ejs davinci davinci dvevm davinci_dvevm - -
-Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic <sbabic@denx.de>
-Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - -
-Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - -
-Active arm arm926ejs davinci davinci sonata davinci_sonata - -
-Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher <hs@denx.de>
-Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at>
-Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc>
-Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc>
-Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com>
-Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
-Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org>
-Active arm arm926ejs kirkwood karo tk71 tk71 - -
-Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 -
-Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot <simon.guinot@sequanux.org>
-Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
-Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 -
-Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot <simon.guinot@sequanux.org>
-Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 -
-Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
-Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - -
-Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net>
-Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com>
-Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT -
-Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE -
-Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org>
-Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu>
-Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com>
-Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com>
-Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de>
-Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com>
-Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de>
-Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
-Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de>
-Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de>
-Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit - Lauri Hintsala <lauri.hintsala@bluegiga.com>
-Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut <marek.vasut@gmail.com>
-Active arm arm926ejs mxs denx m28evk m28evk - Marek Vasut <marek.vasut@gmail.com>
-Active arm arm926ejs mxs freescale mx23evk mx23evk - Otavio Salvador <otavio@ossystems.com.br>
-Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com>
-Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de>
-Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
-Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
-Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
-Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
-Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
-Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
-Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
-Active arm arm926ejs spear spear - x600 - Stefan Roese <sr@denx.de>
-Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com>
-Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand -
-Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty -
-Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand -
-Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar <vipin.kumar@st.com>
-Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand -
-Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR -
-Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty -
-Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand -
-Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR -
-Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar <vipin.kumar@st.com>
-Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand -
-Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR -
-Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty -
-Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand -
-Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR -
-Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar <vipin.kumar@st.com>
-Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand -
-Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty -
-Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand -
-Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB -
-Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB -
-Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB -
-Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij@linaro.org>
-Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij@linaro.org>
-Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
-Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
-Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
-Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com>
-Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
-Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
-Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
-Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
-Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
-Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
-Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
-Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
-Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
-Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
-Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
-Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
-Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
-Active arm armv7 am33xx ti ti816x ti816x_evm - -
-Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
-Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_nandflash sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
-Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
-Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
-Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
-Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger <tim.kryger@linaro.org>
-Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org>
-Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
-Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
-Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
-Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
-Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
-Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
-Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
-Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
-Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com>
-Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
-Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
-Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
-Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu <r64343@freescale.com>
-Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu <r64343@freescale.com>
-Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
-Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
-Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de>
-Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
-Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
-Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
-Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
-Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
-Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
-Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>
-Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it>
-Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il>
-Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de>
-Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber <weber@corscience.de>
-Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com>
-Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND -
-Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND -
-Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com>
-Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com>
-Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com>
-Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones <michael.jones@matrix-vision.de>
-Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár <pali.rohar@gmail.com>
-Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese <sr@denx.de>
-Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen <linuxfae@technexion.com>
-Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de>
-Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de>
-Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com>
-Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini <trini@ti.com>
-Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com>
-Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - -
-Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
-Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
-Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
-Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
-Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
-Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
-Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>
-Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
-Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
-Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>
-Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
-Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
-Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
-Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
-Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
-Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
-Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com>
-Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
-Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
-Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>
-Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
-Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
-Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com>
-Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren <twarren@nvidia.com>
-Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
-Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
-Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de>
-Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
-Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
-Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
-Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
-Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
-Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
-Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
-Active arm pxa - - - xaeniax - -
-Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de>
-Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
-Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
-Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
-Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
-Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
-Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
-Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
-Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
-Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
-Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch>
-Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch>
-Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
-Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
-Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
-Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
-Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
-Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
-Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
-Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
-Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>
-Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf52x2 - - cobra5272 cobra5272 - -
-Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
-Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
-Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - -
-Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
-Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
-Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
-Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
-Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
-Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner <w.wegner@astro-kom.de>
-Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
-Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
-Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
-Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
-Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
-Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
-Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 -
-Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 -
-Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
-Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
-Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
-Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
-Active mips mips32 - imgtec malta maltael malta:SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
-Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
-Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
-Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
-Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE -
-Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC -
-Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND -
-Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE -
-Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE -
-Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM -
-Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND -
-Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -
-Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE -
-Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
-Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
-Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
-Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
-Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
-Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
-Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
-Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
-Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
-Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com>
-Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com>
-Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com>
-Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com>
-Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com>
-Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-Active powerpc 74xx_7xx - - - ppmc7xx - -
-Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de>
-Active powerpc 74xx_7xx - eltec elppc ELPPC - -
-Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com>
-Active powerpc 74xx_7xx - Marvell db64360 DB64360 - -
-Active powerpc 74xx_7xx - Marvell db64460 DB64460 - -
-Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de>
-Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de>
-Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com>
-Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - -
-Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 -
-Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xx - - cmi cmi_mpc5xx - -
-Active powerpc mpc5xx - mpl pati PATI - -
-Active powerpc mpc5xxx - - - canmb - -
-Active powerpc mpc5xxx - - - cm5200 - -
-Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de>
-Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de>
-Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de>
-Active powerpc mpc5xxx - - - motionpro - -
-Active powerpc mpc5xxx - - - munices - -
-Active powerpc mpc5xxx - - - v38b - -
-Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de>
-Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
-Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
-Active powerpc mpc5xxx - - bc3450 BC3450 - -
-Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
-Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
-Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
-Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
-Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
-Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
-Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
-Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
-Active powerpc mpc5xxx - - icecube Lite5200 IceCube -
-Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
-Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
-Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B -
-Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -
-Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -
-Active powerpc mpc5xxx - - mcc200 mcc200 - -
-Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 -
-Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -
-Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
-Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM -
-Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 -
-Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
-Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM -
-Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM -
-Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 -
-Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
-Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 -
-Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de>
-Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de>
-Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
-Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner <Wagner@Microsys.de>
-Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 -
-Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 -
-Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 -
-Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 -
-Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin <agust@denx.de>
-Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister <Pfister_Werner@intercontrol.de>
-Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de>
-Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
-Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
-Active powerpc mpc5xxx - manroland - hmi1001 - -
-Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de>
-Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
-Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl@gmail.com>
-Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
-Active powerpc mpc5xxx - tqc tqm5200 aev - -
-Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B -
-Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH -
-Active powerpc mpc5xxx - tqc tqm5200 charon - Heiko Schocher <hs@denx.de>
-Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 -
-Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP -
-Active powerpc mpc5xxx - tqc tqm5200 TB5200 - -
-Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B -
-Active powerpc mpc5xxx - tqc tqm5200 TQM5200 - -
-Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B -
-Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 -
-Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 -
-Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S -
-Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -
-Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu>
-Active powerpc mpc824x - - a3000 A3000 - -
-Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner <Wagner@Microsys.de>
-Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
-Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
-Active powerpc mpc824x - - mvblue MVBLUE - -
-Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
-Active powerpc mpc8260 - - - ep82xxm - -
-Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
-Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
-Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
-Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
-Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - cpu87 CPU87 - -
-Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
-Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - ids ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
-Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
-Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
-Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
-Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm828 PM828 - -
-Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI -
-Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
-Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
-Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com>
-Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz -
-Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - tqc tqm8272 TQM8272 - -
-Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
-Active powerpc mpc83xx - - sbc8349 sbc8349 - Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de>
-Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc83xx - esd vme8349 vme8349 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com>
-Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ -
-Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ -
-Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
-Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
-Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
-Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips <kim.phillips@freescale.com>
-Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX -
-Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 -
-Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 -
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
-Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs@denx.de>
-Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher <hs@denx.de>
-Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
-Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
-Active powerpc mpc83xx - tqc tqm834x TQM834x - -
-Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc85xx - - socrates socrates - -
-Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
-Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
-Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
-Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
-Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
-Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
-Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS - -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS - -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P5040DS - -
-Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
-Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
-Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - -
-Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
-Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
-Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
-Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
-Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
-Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SDCARD P1010RDB:P1010RDB_PA,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH P1010RDB:P1010RDB_PA,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND P1010RDB:P1010RDB_PA,NAND -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND_SECBOOT P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR P1010RDB:P1010RDB_PA -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR_SECBOOT P1010RDB:P1010RDB_PA,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SDCARD P1010RDB:P1010RDB_PA,SDCARD -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH P1010RDB:P1010RDB_PA,SPIFLASH -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND P1010RDB:P1010RDB_PB,36BIT,NAND -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR P1010RDB:P1010RDB_PB,36BIT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SDCARD P1010RDB:P1010RDB_PB,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH P1010RDB:P1010RDB_PB,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND P1010RDB:P1010RDB_PB,NAND -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND_SECBOOT P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR P1010RDB:P1010RDB_PB -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR_SECBOOT P1010RDB:P1010RDB_PB,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SDCARD P1010RDB:P1010RDB_PB,SDCARD -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH P1010RDB:P1010RDB_PB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT -
-Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
-Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
-Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
-Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD -
-Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH -
-Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 -
-Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder <iws@ovro.caltech.edu>
-Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder <iws@ovro.caltech.edu>
-Active powerpc mpc85xx - freescale p2020ds P2020DS - -
-Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT -
-Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 -
-Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD -
-Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB - -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t1040qds T1040QDS_D4 T1040QDS:PPC_T1040,SYS_FSL_DDR4 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t1040qds T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <Priyanka.Jain@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
-Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SECURE_BOOT T104xRDB:PPC_T1040,SECURE_BOOT,T1040RDB Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <Priyanka.Jain@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
-Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
-Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SECURE_BOOT T208xQDS:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 -
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
-Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
-Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
-Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
-Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
-Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf@suse.de>
-Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
-Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
-Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
-Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
-Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - xes - xpedite520x - -
-Active powerpc mpc85xx - xes - xpedite537x - -
-Active powerpc mpc85xx - xes - xpedite550x - -
-Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
-Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
-Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc86xx - xes - xpedite517x - -
-Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - - quantum - -
-Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - - spc1920 - -
-Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
-Active powerpc mpc8xx - - - v37 - -
-Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
-Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
-Active powerpc mpc8xx - - fads MPC86xADS - -
-Active powerpc mpc8xx - - fads MPC885ADS - -
-Active powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson <kd@flaga.is>
-Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
-Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
-Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 -
-Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 -
-Active powerpc mpc8xx - - netta NETTA - -
-Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 -
-Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 -
-Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 -
-Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr>
-Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
-Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - rbc823 RBC823 - -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
-Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
-Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
-Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de>
-Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de>
-Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org>
-Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de>
-Active powerpc mpc8xx - snmc qs850 QS823 - -
-Active powerpc mpc8xx - snmc qs850 QS850 - -
-Active powerpc mpc8xx - snmc qs860t QS860T - -
-Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx NSCU - -
-Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TK885D - -
-Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM823M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM850M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM855M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM860M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM862L - -
-Active powerpc mpc8xx - tqc tqm8xx TQM862M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM866M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM885D - -
-Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx virtlab2 - -
-Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de>
-Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com>
-Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com>
-Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
-Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de>
-Active powerpc ppc4xx - - - sbc405 - -
-Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
-Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com>
-Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org>
-Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com>
-Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com>
-Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - bubinga - -
-Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com>
-Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com>
-Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
-Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - yucca - -
-Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
-Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
-Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 -
-Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -
-Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -
-Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd pci405 PCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd plu405 PLU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd pmc405 PMC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd pmc405de PMC405DE - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd pmc440 PMC440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch>
-Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch>
-Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch>
-Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
-Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org>
-Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
-Active sh sh2 - renesas rsk7269 rsk7269 - -
-Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com>
-Active sh sh3 - - ms7720se ms7720se - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-Active sh sh3 - - shmin shmin - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - - espt espt - -
-Active sh sh4 - - ms7722se ms7722se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - - ms7750se ms7750se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - alphaproject ap_sh4a_4a ap_sh4a_4a - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - renesas ap325rxa ap325rxa - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - renesas ecovec ecovec - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - renesas MigoR MigoR - -
-Active sh sh4 - renesas r0p7734 r0p7734 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - renesas sh7752evb sh7752evb - -
-Active sh sh4 - renesas sh7753evb sh7753evb - -
-Active sh sh4 - renesas sh7757lcr sh7757lcr - -
-Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Active sh sh4 - renesas sh7785lcr sh7785lcr - -
-Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 -
-Active sparc leon2 - gaisler - grsim_leon2 - -
-Active sparc leon3 - gaisler - gr_cpci_ax2000 - -
-Active sparc leon3 - gaisler - gr_ep2s60 - -
-Active sparc leon3 - gaisler - gr_xc3s_1500 - -
-Active sparc leon3 - gaisler - grsim - -
-Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
+Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
+Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
+Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
+Active arm arm1136 mx31 - - imx31_phycore - -
+Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
+Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at>
+Active arm arm1136 mx31 logicpd - imx31_litekit - -
+Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de>
+Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -
+Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de>
+Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de>
+Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org>
+Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
+Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org>
+Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
+Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
+Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
+Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek - Andreas Bießmann <andreas.devel@gmail.com>
+Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann <andreas.devel@gmail.com>
+Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 - Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard <eric@eukrea.com>
+Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
+Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
+Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
+Active arm arm920t ks8695 - - cm41xx - -
+Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
+Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
+Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
+Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org>
+Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com>
+Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com>
+Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com>
+Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de>
+Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at>
+Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at>
+Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at>
+Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de>
+Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de>
+Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de>
+Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
+Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
+Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx - Heiko Schocher <hs@denx.de>
+Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de>
+Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com>
+Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dvevm davinci_dvevm - -
+Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic <sbabic@denx.de>
+Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - -
+Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - -
+Active arm arm926ejs davinci davinci sonata davinci_sonata - -
+Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher <hs@denx.de>
+Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at>
+Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc>
+Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc>
+Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com>
+Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
+Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org>
+Active arm arm926ejs kirkwood karo tk71 tk71 - -
+Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 -
+Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 -
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 -
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - -
+Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net>
+Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com>
+Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT -
+Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE -
+Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org>
+Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu>
+Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com>
+Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com>
+Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de>
+Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com>
+Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de>
+Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
+Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de>
+Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de>
+Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit - Lauri Hintsala <lauri.hintsala@bluegiga.com>
+Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs mxs denx m28evk m28evk - Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs mxs freescale mx23evk mx23evk - Otavio Salvador <otavio@ossystems.com.br>
+Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de>
+Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
+Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
+Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
+Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
+Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
+Active arm arm926ejs spear spear - x600 - Stefan Roese <sr@denx.de>
+Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand -
+Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty -
+Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand -
+Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand -
+Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR -
+Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty -
+Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand -
+Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR -
+Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand -
+Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR -
+Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty -
+Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand -
+Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR -
+Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand -
+Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty -
+Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand -
+Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB -
+Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB -
+Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB -
+Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij@linaro.org>
+Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij@linaro.org>
+Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
+Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
+Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
+Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
+Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
+Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
+Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
+Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
+Active arm armv7 am33xx ti ti816x ti816x_evm - -
+Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
+Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_nandflash sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
+Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
+Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
+Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
+Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger <tim.kryger@linaro.org>
+Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org>
+Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
+Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
+Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
+Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
+Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
+Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
+Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com>
+Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
+Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
+Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
+Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
+Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu <r64343@freescale.com>
+Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu <r64343@freescale.com>
+Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
+Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
+Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de>
+Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
+Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
+Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
+Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
+Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
+Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
+Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>
+Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it>
+Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il>
+Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de>
+Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber <weber@corscience.de>
+Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com>
+Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND -
+Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND -
+Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com>
+Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com>
+Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com>
+Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones <michael.jones@matrix-vision.de>
+Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár <pali.rohar@gmail.com>
+Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese <sr@denx.de>
+Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen <linuxfae@technexion.com>
+Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de>
+Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de>
+Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com>
+Active arm armv7 omap3 ti beagle omap3_beagle omap3_beagle:NAND Tom Rini <trini@ti.com>
+Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com>
+Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - -
+Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
+Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
+Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
+Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
+Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
+Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
+Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>
+Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
+Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
+Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
+Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
+Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
+Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra124 nvidia jetson-tk1 jetson-tk1 jetson-tk1:BOARD_JETSON_TK1= Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
+Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
+Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>
+Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de>
+Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
+Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
+Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
+Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
+Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
+Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
+Active arm pxa - - - xaeniax - -
+Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de>
+Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
+Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
+Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
+Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
+Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
+Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
+Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
+Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
+Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch>
+Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch>
+Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
+Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
+Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
+Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
+Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
+Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
+Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
+Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
+Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>
+Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf52x2 - - cobra5272 cobra5272 - -
+Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
+Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
+Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - -
+Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
+Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
+Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
+Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
+Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
+Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner <w.wegner@astro-kom.de>
+Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 -
+Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 -
+Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
+Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
+Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
+Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
+Active mips mips32 - imgtec malta maltael malta:SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
+Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
+Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
+Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC -
+Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND -
+Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM -
+Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND -
+Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE -
+Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
+Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
+Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
+Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
+Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com>
+Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com>
+Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com>
+Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com>
+Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com>
+Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+Active powerpc 74xx_7xx - - - ppmc7xx - -
+Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de>
+Active powerpc 74xx_7xx - eltec elppc ELPPC - -
+Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com>
+Active powerpc 74xx_7xx - Marvell db64360 DB64360 - -
+Active powerpc 74xx_7xx - Marvell db64460 DB64460 - -
+Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de>
+Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de>
+Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com>
+Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - -
+Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 -
+Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xx - - cmi cmi_mpc5xx - -
+Active powerpc mpc5xx - mpl pati PATI - -
+Active powerpc mpc5xxx - - - canmb - -
+Active powerpc mpc5xxx - - - cm5200 - -
+Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de>
+Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de>
+Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - - - motionpro - -
+Active powerpc mpc5xxx - - - munices - -
+Active powerpc mpc5xxx - - - v38b - -
+Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de>
+Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
+Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
+Active powerpc mpc5xxx - - bc3450 BC3450 - -
+Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
+Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
+Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
+Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
+Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
+Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
+Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
+Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc5xxx - - icecube Lite5200 IceCube -
+Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
+Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B -
+Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -
+Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -
+Active powerpc mpc5xxx - - mcc200 mcc200 - -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 -
+Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 -
+Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 -
+Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - manroland - hmi1001 - -
+Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl@gmail.com>
+Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
+Active powerpc mpc5xxx - tqc tqm5200 aev - -
+Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B -
+Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH -
+Active powerpc mpc5xxx - tqc tqm5200 charon - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 -
+Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP -
+Active powerpc mpc5xxx - tqc tqm5200 TB5200 - -
+Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200 - -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu>
+Active powerpc mpc824x - - a3000 A3000 - -
+Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
+Active powerpc mpc824x - - mvblue MVBLUE - -
+Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
+Active powerpc mpc8260 - - - ep82xxm - -
+Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
+Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
+Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
+Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - cpu87 CPU87 - -
+Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
+Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
+Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
+Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm828 PM828 - -
+Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI -
+Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com>
+Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz -
+Active powerpc mpc8260 - ids ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8272 TQM8272 - -
+Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
+Active powerpc mpc83xx - - sbc8349 sbc8349 - Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc83xx - esd vme8349 vme8349 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com>
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ -
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ -
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
+Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips <kim.phillips@freescale.com>
+Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX -
+Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
+Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs@denx.de>
+Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher <hs@denx.de>
+Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
+Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
+Active powerpc mpc83xx - tqc tqm834x TQM834x - -
+Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - socrates socrates - -
+Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
+Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
+Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS - -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS - -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS - -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
+Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
+Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - -
+Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
+Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
+Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
+Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
+Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
+Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - York Sun <yorksun@freescale.com>
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT York Sun <yorksun@freescale.com>
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SDCARD P1010RDB:P1010RDB_PA,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH P1010RDB:P1010RDB_PA,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND P1010RDB:P1010RDB_PA,NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND_SECBOOT P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR P1010RDB:P1010RDB_PA -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR_SECBOOT P1010RDB:P1010RDB_PA,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SDCARD P1010RDB:P1010RDB_PA,SDCARD -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH P1010RDB:P1010RDB_PA,SPIFLASH -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND P1010RDB:P1010RDB_PB,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR P1010RDB:P1010RDB_PB,36BIT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SDCARD P1010RDB:P1010RDB_PB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH P1010RDB:P1010RDB_PB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND P1010RDB:P1010RDB_PB,NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND_SECBOOT P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR P1010RDB:P1010RDB_PB -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR_SECBOOT P1010RDB:P1010RDB_PB,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SDCARD P1010RDB:P1010RDB_PB,SDCARD -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH P1010RDB:P1010RDB_PB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
+Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
+Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 -
+Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder <iws@ovro.caltech.edu>
+Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder <iws@ovro.caltech.edu>
+Active powerpc mpc85xx - freescale p2020ds P2020DS - -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB - -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf@suse.de>
+Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t1040qds T1040QDS_D4 T1040QDS:PPC_T1040,SYS_FSL_DDR4 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t1040qds T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SECURE_BOOT T104xRDB:PPC_T1040,SECURE_BOOT,T1040RDB Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SECURE_BOOT T208xQDS:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SECURE_BOOT T208xRDB:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
+Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4rdb T4160RDB T4240RDB:PPC_T4160 Chunhe Lan <Chunhe.Lan@freescale.com>
+Active powerpc mpc85xx - freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan <Chunhe.Lan@freescale.com>
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc85xx - xes - xpedite520x - -
+Active powerpc mpc85xx - xes - xpedite537x - -
+Active powerpc mpc85xx - xes - xpedite550x - -
+Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
+Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc86xx - xes - xpedite517x - -
+Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - - quantum - -
+Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - - spc1920 - -
+Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
+Active powerpc mpc8xx - - - v37 - -
+Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
+Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
+Active powerpc mpc8xx - - fads MPC86xADS - -
+Active powerpc mpc8xx - - fads MPC885ADS - -
+Active powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson <kd@flaga.is>
+Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
+Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
+Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 -
+Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 -
+Active powerpc mpc8xx - - netta NETTA - -
+Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 -
+Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 -
+Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 -
+Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr>
+Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
+Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - rbc823 RBC823 - -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
+Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
+Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de>
+Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de>
+Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org>
+Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de>
+Active powerpc mpc8xx - snmc qs850 QS823 - -
+Active powerpc mpc8xx - snmc qs850 QS850 - -
+Active powerpc mpc8xx - snmc qs860t QS860T - -
+Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx NSCU - -
+Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TK885D - -
+Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM823M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM850M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM855M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM860M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM862L - -
+Active powerpc mpc8xx - tqc tqm8xx TQM862M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM866M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM885D - -
+Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx virtlab2 - -
+Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de>
+Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com>
+Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com>
+Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
+Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de>
+Active powerpc ppc4xx - - - sbc405 - -
+Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
+Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com>
+Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org>
+Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com>
+Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com>
+Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - bubinga - -
+Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com>
+Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com>
+Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
+Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - yucca - -
+Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
+Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
+Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 -
+Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -
+Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pci405 PCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd plu405 PLU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pmc405 PMC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pmc405de PMC405DE - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pmc440 PMC440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch>
+Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch>
+Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch>
+Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
+Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active sandbox sandbox - - sandbox sandbox - Simon Glass <sjg@chromium.org>
+Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
+Active sh sh2 - renesas rsk7269 rsk7269 - -
+Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com>
+Active sh sh3 - - ms7720se ms7720se - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Active sh sh3 - - shmin shmin - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - - espt espt - -
+Active sh sh4 - - ms7722se ms7722se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - - ms7750se ms7750se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - alphaproject ap_sh4a_4a ap_sh4a_4a - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas ap325rxa ap325rxa - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas ecovec ecovec - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas MigoR MigoR - -
+Active sh sh4 - renesas r0p7734 r0p7734 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas sh7752evb sh7752evb - -
+Active sh sh4 - renesas sh7753evb sh7753evb - -
+Active sh sh4 - renesas sh7757lcr sh7757lcr - -
+Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas sh7785lcr sh7785lcr - -
+Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 -
+Active sparc leon2 - gaisler - grsim_leon2 - -
+Active sparc leon3 - gaisler - gr_cpci_ax2000 - -
+Active sparc leon3 - gaisler - gr_ep2s60 - -
+Active sparc leon3 - gaisler - gr_xc3s_1500 - -
+Active sparc leon3 - gaisler - grsim - -
+Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
# The following were moved to "Orphan" in April, 2014
-Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
-Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
-Orphan powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
-Orphan powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
+Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
+Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
+Orphan powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
+Orphan powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
# The following were moved to "Orphan" in March, 2014
-Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
-Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
-Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
-Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
-Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
-Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
-Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
-Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <travis.sawyer@sandburst.com>
-Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer <travis.sawyer@sandburst.com>
+Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P
MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR
- Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
+Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
+Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
+Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK
- Anton Vorontsov <avorontsov@ru.mvista.com>
+Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33
MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
+Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX
- Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7
- Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
+Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
+Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <travis.sawyer@sandburst.com>
+Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer <travis.sawyer@sandburst.com>
# The following were move to "Orphan" in September, 2013
-Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
static int show_dram_config(void)
{
- ulong size;
+ unsigned long long size;
#ifdef CONFIG_NR_DRAM_BANKS
int i;
}
#endif
-static int setup_baud_rate(void)
-{
- /* Ick, can we get rid of this line? */
- gd->bd->bi_baudrate = gd->baudrate;
-
- return 0;
-}
-
static int setup_dram_config(void)
{
/* Ram is board specific, so move it to board code ... */
INIT_FUNC_WATCHDOG_RESET
setup_board_part2,
#endif
- setup_baud_rate,
display_new_sp,
#ifdef CONFIG_SYS_EXTBDINFO
setup_board_extra,
void board_init_f(ulong boot_flags)
{
-#ifndef CONFIG_X86
+#ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA
+ /*
+ * For some archtectures, global data is initialized and used before
+ * calling this function. The data should be preserved. For others,
+ * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack
+ * here to host global data until relocation.
+ */
gd_t data;
gd = &data;
-#endif
/*
* Clear global data before it is accessed at debug print
* in initcall_run_list. Otherwise the debug print probably
* get the wrong vaule of gd->have_console.
*/
-#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
- !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
- !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
zero_global_data();
#endif
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
printf("IP addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %6u bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", gd->baudrate);
print_num("relocaddr", gd->relocaddr);
board_detail();
return 0;
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
#if defined(CONFIG_CMD_NET)
print_eths();
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %6u bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", gd->baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
#if defined(CONFIG_CMD_NET)
print_eths();
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %d bps\n", gd->baudrate);
return 0;
}
image_buf = map_sysmem(image_start, image_len);
switch (comp) {
case IH_COMP_NONE:
- if (load == blob_start || load == image_start) {
+ if (load == image_start) {
printf(" XIP %s ... ", type_name);
no_overlap = 1;
} else {
#include <watchdog.h>
#include <linux/stddef.h>
#include <asm/byteorder.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int argc, char * const argv[])
{
char buf[32];
- char *addr, *cmd, *res;
+ ulong addr;
+ char *ptr, *cmd, *res;
size_t size = 0;
ssize_t len;
env_t *envp;
if (argc < 1)
return CMD_RET_USAGE;
- addr = (char *)simple_strtoul(argv[0], NULL, 16);
+ addr = simple_strtoul(argv[0], NULL, 16);
+ ptr = map_sysmem(addr, size);
if (size)
- memset(addr, '\0', size);
+ memset(ptr, '\0', size);
argc--;
argv++;
if (sep) { /* export as text file */
len = hexport_r(&env_htab, sep,
H_MATCH_KEY | H_MATCH_IDENT,
- &addr, size, argc, argv);
+ &ptr, size, argc, argv);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
return 0;
}
- envp = (env_t *)addr;
+ envp = (env_t *)ptr;
if (chk) /* export as checksum protected block */
res = (char *)envp->data;
else /* export as raw binary data */
- res = addr;
+ res = ptr;
len = hexport_r(&env_htab, '\0',
H_MATCH_KEY | H_MATCH_IDENT,
static int do_env_import(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- char *cmd, *addr;
+ ulong addr;
+ char *cmd, *ptr;
char sep = '\n';
int chk = 0;
int fmt = 0;
if (!fmt)
printf("## Warning: defaulting to text format\n");
- addr = (char *)simple_strtoul(argv[0], NULL, 16);
+ addr = simple_strtoul(argv[0], NULL, 16);
+ ptr = map_sysmem(addr, 0);
if (argc == 2) {
size = simple_strtoul(argv[1], NULL, 16);
puts("## Error: external checksum format must pass size\n");
return CMD_RET_FAILURE;
} else {
- char *s = addr;
+ char *s = ptr;
size = 0;
if (chk) {
uint32_t crc;
- env_t *ep = (env_t *)addr;
+ env_t *ep = (env_t *)ptr;
size -= offsetof(env_t, data);
memcpy(&crc, &ep->crc, sizeof(crc));
puts("## Error: bad CRC, import failed\n");
return 1;
}
- addr = (char *)ep->data;
+ ptr = (char *)ep->data;
}
- if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR,
- 0, NULL) == 0) {
+ if (himport_r(&env_htab, ptr, size, sep, del ? 0 : H_NOCLEAR, 0,
+ NULL) == 0) {
error("Environment import failed: errno = %d\n", errno);
return 1;
}
printf("\ntime:");
if (minutes)
printf(" %lu minutes,", minutes);
- printf(" %lu.%03lu seconds, %lu ticks\n",
- seconds, milliseconds, cycles);
+ printf(" %lu.%03lu seconds\n", seconds, milliseconds);
}
static int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int init_mmc_for_env(struct mmc *mmc)
{
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
+#endif
+
if (!mmc) {
puts("No MMC card found\n");
return -1;
#ifdef CONFIG_SYS_MMC_ENV_PART
if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) {
- if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
- CONFIG_SYS_MMC_ENV_PART)) {
+ if (mmc_switch_part(dev, CONFIG_SYS_MMC_ENV_PART)) {
puts("MMC partition switch failed\n");
return -1;
}
static void fini_mmc_for_env(struct mmc *mmc)
{
#ifdef CONFIG_SYS_MMC_ENV_PART
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num)
- mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
- mmc->part_num);
+ mmc_switch_part(dev, mmc->part_num);
#endif
}
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(CONFIG_SYS_MMC_ENV_DEV, blk_start,
- blk_cnt, (uchar *)buffer);
+ n = mmc->block_dev.block_read(dev, blk_start, blk_cnt, (uchar *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
- struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ struct mmc *mmc;
u32 offset1, offset2;
int read1_fail = 0, read2_fail = 0;
int crc1_ok = 0, crc2_ok = 0;
env_t *ep;
int ret;
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1);
ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env2, 1);
- if (tmp_env1 == NULL || tmp_env2 == NULL) {
- puts("Can't allocate buffers for environment\n");
- ret = 1;
- goto err;
- }
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
+
+ mmc = find_mmc_device(dev);
if (init_mmc_for_env(mmc)) {
ret = 1;
{
#if !defined(ENV_IS_EMBEDDED)
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
- struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ struct mmc *mmc;
u32 offset;
int ret;
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
+
+ mmc = find_mmc_device(dev);
if (init_mmc_for_env(mmc)) {
ret = 1;
i->p = the_command;
#else
int n;
- static char the_command[CONFIG_SYS_CBSIZE];
+ static char the_command[CONFIG_SYS_CBSIZE + 1];
#ifdef CONFIG_BOOT_RETRY_TIME
# ifndef CONFIG_RESET_TO_RETRY
if (!ft_verify_fdt(blob))
return -1;
+#ifdef CONFIG_SOC_K2HK
+ if (IMAGE_OF_BOARD_SETUP)
+ ft_board_setup_ex(blob, gd->bd);
+#endif
+
return 0;
}
{ IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", },
{ IH_TYPE_FIRMWARE, "firmware", "Firmware", },
{ IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", },
+ { IH_TYPE_GPIMAGE, "gpimage", "TI Keystone SPL Image",},
{ IH_TYPE_KERNEL, "kernel", "Kernel Image", },
{ IH_TYPE_KERNEL_NOLOAD, "kernel_noload", "Kernel Image (no loading done)", },
{ IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",},
return 1;
}
- if (run_command(arg, flag) != 0)
+ if (run_command_list(arg, -1, flag) != 0)
return 1;
}
return 0;
int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition)
{
int err;
+ __maybe_unused char *file;
err = spl_register_fat_device(block_dev, partition);
if (err)
return err;
+#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT)
+ file = getenv("falcon_args_file");
+ if (file) {
+ err = file_fat_read(file, (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
+ if (err <= 0) {
+ printf("spl: error reading image %s, err - %d, falling back to default\n",
+ file, err);
+ goto defaults;
+ }
+ file = getenv("falcon_image_file");
+ if (file) {
+ err = spl_load_image_fat(block_dev, partition, file);
+ if (err != 0) {
+ puts("spl: falling back to default\n");
+ goto defaults;
+ }
+
+ return 0;
+ } else
+ puts("spl: falcon_image_file not set in environment, falling back to default\n");
+ } else
+ puts("spl: falcon_args_file not set in environment, falling back to default\n");
+
+defaults:
+#endif
+
err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
(void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
if (err <= 0) {
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
- return;
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ gpt_head, &gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+ __func__);
+ return;
+ } else {
+ printf("%s: *** Using Backup GPT ***\n",
+ __func__);
+ }
}
debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
- return -1;
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ gpt_head, &gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+ __func__);
+ return -1;
+ } else {
+ printf("%s: *** Using Backup GPT ***\n",
+ __func__);
+ }
}
if (part > le32_to_cpu(gpt_head->num_partition_entries) ||
!= pte_blk_cnt)
goto err;
- /* recalculate the values for the Second GPT Header */
+ /* recalculate the values for the Backup GPT Header */
val = le64_to_cpu(gpt_h->my_lba);
gpt_h->my_lba = gpt_h->alternate_lba;
gpt_h->alternate_lba = cpu_to_le64(val);
Returns "0" if SPL should start the kernel, "1" if U-Boot
must be started.
+Environment variables
+---------------------
+
+A board may chose to look at the environment for decisions about falcon
+mode. In this case the following variables may be supported:
+
+boot_os : Set to yes/Yes/true/True/1 to enable booting to OS,
+ any other value to fall back to U-Boot (including
+ unset)
+falcon_args_file : Filename to load as the 'args' portion of falcon mode
+ rather than the hard-coded value.
+falcon_image_file : Filename to load as the OS image portion of falcon
+ mode rather than the hard-coded value.
Using spl command
-----------------
Background
----------
-U-Boot has tranditionally had a board.c file for each architecture. This has
+U-Boot has traditionally had a board.c file for each architecture. This has
introduced quite a lot of duplication, with each architecture tending to do
initialisation slightly differently. To address this, a new 'generic board
init' feature was introduced a year ago in March 2013 (further motivation is
|Partition n |
| |
----------------------------------------------------------
- LBA -34 |Entry 1|Entry 2| Entry 3| Entry 4| Secondary
- -------------------------------------------------- (bkp)
- LBA -33 |Entries 5 - 128 | GPT
+ LBA -34 |Entry 1|Entry 2| Entry 3| Entry 4| Backup
+ -------------------------------------------------- GPT
+ LBA -33 |Entries 5 - 128 |
| |
| |
LBA -2 | |
--------------------------------------------------
- LBA -1 |Secondary GPT Header |
+ LBA -1 |Backup GPT Header |
----------------------------------------------------------
For a legacy reasons, GPT's LBA 0 sector has a MBR structure. It is called
"LBA -1" means the last addressable block (in the mmc subsystem:
"dev_desc->lba - 1")
-Primary/Secondary GPT header:
+Primary/Backup GPT header:
----------------------------
Offset Size Description
GPT headers and partition entries are protected by CRC32 (the POSIX CRC32).
-Primary GPT header and Secondary GPT header have swapped values of "Current LBA"
+Primary GPT header and Backup GPT header have swapped values of "Current LBA"
and "Backup LBA" and therefore different CRC32 check-sum.
CRC32 for GPT headers (field "CRC of header") are calculated up till
the whole array entry ( Number_of_partition_entries *
sizeof(partition_entry_size (usually 128)))
-Observe, how Secondary GPT is placed in the memory. It is NOT a mirror reflect
+Observe, how Backup GPT is placed in the memory. It is NOT a mirror reflect
of the Primary.
Partition Entry Format:
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_sp_info(xilinx_desc *desc ); */
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_ss_info(xilinx_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
- ret_val = Spartan2_ss_load (desc, buf, bsize);
+ ret_val = spartan2_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
- ret_val = Spartan2_sp_load (desc, buf, bsize);
+ ret_val = spartan2_sp_load(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
- ret_val = Spartan2_ss_dump (desc, buf, bsize);
+ ret_val = spartan2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
- ret_val = Spartan2_sp_dump (desc, buf, bsize);
+ ret_val = spartan2_sp_dump(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan2_info( Xilinx_desc *desc )
+static int spartan2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
return ret_val;
}
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
/* ------------------------------------------------------------------------- */
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
+ xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
int i;
unsigned char val;
return ret_val;
}
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan2_op = {
+ .load = spartan2_load,
+ .dump = spartan2_dump,
+ .info = spartan2_info,
+};
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan3_sp_info(Xilinx_desc *desc ); */
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_sp_info(xilinx_desc *desc ); */
-static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan3_ss_info(Xilinx_desc *desc); */
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_ss_info(xilinx_desc *desc); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
- ret_val = Spartan3_ss_load (desc, buf, bsize);
+ ret_val = spartan3_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
- ret_val = Spartan3_sp_load (desc, buf, bsize);
+ ret_val = spartan3_sp_load(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
- ret_val = Spartan3_ss_dump (desc, buf, bsize);
+ ret_val = spartan3_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
- ret_val = Spartan3_sp_dump (desc, buf, bsize);
+ ret_val = spartan3_sp_dump(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan3_info( Xilinx_desc *desc )
+static int spartan3_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
return ret_val;
}
-static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
/* ------------------------------------------------------------------------- */
-static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
+ xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns;
int i;
unsigned char val;
return ret_val;
}
-static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan3_op = {
+ .load = spartan3_load,
+ .dump = spartan3_dump,
+ .info = spartan3_info,
+};
#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
- ret_val = Virtex2_ss_load (desc, buf, bsize);
+ ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
- ret_val = Virtex2_ssm_load (desc, buf, bsize);
+ ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
- ret_val = Virtex2_ss_dump (desc, buf, bsize);
+ ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
- ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+ ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Virtex2_info (Xilinx_desc * desc)
+static int virtex2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
__FUNCTION__, __LINE__, fn);
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
return ret_val;
}
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
/* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+ .load = virtex2_load,
+ .dump = virtex2_dump,
+ .info = virtex2_info,
+};
#include <spartan3.h>
#include <zynqpl.h>
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* Define FPGA_DEBUG to get debug printf's */
-#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
/* Local Static Functions */
-static int xilinx_validate (Xilinx_desc * desc, char *fn);
+static int xilinx_validate(xilinx_desc *desc, char *fn);
/* ------------------------------------------------------------------------- */
unsigned char *dataptr;
unsigned int i;
const fpga_desc *desc;
- Xilinx_desc *xdesc;
+ xilinx_desc *xdesc;
dataptr = (unsigned char *)fpgadata;
/* Find out fpga_description */
return FPGA_FAIL;
}
} else {
- printf("%s: Please fill correct device ID to Xilinx_desc\n",
+ printf("%s: Please fill correct device ID to xilinx_desc\n",
__func__);
}
printf(" part number = \"%s\"\n", buffer);
return fpga_load(devnum, dataptr, swapsize);
}
-int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
- int ret_val = FPGA_FAIL; /* assume a failure */
-
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
- } else
- switch (desc->family) {
- case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
- PRINTF ("%s: Launching the Spartan-II Loader...\n",
- __FUNCTION__);
- ret_val = Spartan2_load (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
- PRINTF ("%s: Launching the Spartan-III Loader...\n",
- __FUNCTION__);
- ret_val = Spartan3_load (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-III devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Virtex2:
-#if defined(CONFIG_FPGA_VIRTEX2)
- PRINTF ("%s: Launching the Virtex-II Loader...\n",
- __FUNCTION__);
- ret_val = Virtex2_load (desc, buf, bsize);
-#else
- printf ("%s: No support for Virtex-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
- PRINTF("%s: Launching the Zynq PL Loader...\n",
- __func__);
- ret_val = zynq_load(desc, buf, bsize);
-#else
- printf("%s: No support for Zynq devices.\n",
- __func__);
-#endif
- break;
-
- default:
- printf ("%s: Unsupported family type, %d\n",
- __FUNCTION__, desc->family);
- }
+ return FPGA_FAIL;
+ }
- return ret_val;
+ return desc->operations->load(desc, buf, bsize);
}
-int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
- int ret_val = FPGA_FAIL; /* assume a failure */
-
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
- } else
- switch (desc->family) {
- case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
- PRINTF ("%s: Launching the Spartan-II Reader...\n",
- __FUNCTION__);
- ret_val = Spartan2_dump (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
- PRINTF ("%s: Launching the Spartan-III Reader...\n",
- __FUNCTION__);
- ret_val = Spartan3_dump (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-III devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Virtex2:
-#if defined( CONFIG_FPGA_VIRTEX2)
- PRINTF ("%s: Launching the Virtex-II Reader...\n",
- __FUNCTION__);
- ret_val = Virtex2_dump (desc, buf, bsize);
-#else
- printf ("%s: No support for Virtex-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
- PRINTF("%s: Launching the Zynq PL Reader...\n",
- __func__);
- ret_val = zynq_dump(desc, buf, bsize);
-#else
- printf("%s: No support for Zynq devices.\n",
- __func__);
-#endif
- break;
-
- default:
- printf ("%s: Unsupported family type, %d\n",
- __FUNCTION__, desc->family);
- }
+ return FPGA_FAIL;
+ }
- return ret_val;
+ return desc->operations->dump(desc, buf, bsize);
}
-int xilinx_info (Xilinx_desc * desc)
+int xilinx_info(xilinx_desc *desc)
{
int ret_val = FPGA_FAIL;
if (xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("Family: \t");
switch (desc->family) {
- case Xilinx_Spartan2:
+ case xilinx_spartan2:
printf ("Spartan-II\n");
break;
- case Xilinx_Spartan3:
+ case xilinx_spartan3:
printf ("Spartan-III\n");
break;
- case Xilinx_Virtex2:
+ case xilinx_virtex2:
printf ("Virtex-II\n");
break;
case xilinx_zynq:
if (desc->iface_fns) {
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
- switch (desc->family) {
- case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
- Spartan2_info (desc);
-#else
- /* just in case */
- printf ("%s: No support for Spartan-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
- Spartan3_info (desc);
-#else
- /* just in case */
- printf ("%s: No support for Spartan-III devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Virtex2:
-#if defined(CONFIG_FPGA_VIRTEX2)
- Virtex2_info (desc);
-#else
- /* just in case */
- printf ("%s: No support for Virtex-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
- zynq_info(desc);
-#else
- /* just in case */
- printf("%s: No support for Zynq devices.\n",
- __func__);
-#endif
- /* Add new family types here */
- default:
- /* we don't need a message here - we give one up above */
- ;
- }
+ desc->operations->info(desc);
} else
printf ("No Device Function Table.\n");
/* ------------------------------------------------------------------------- */
-static int xilinx_validate (Xilinx_desc * desc, char *fn)
+static int xilinx_validate(xilinx_desc *desc, char *fn)
{
int ret_val = false;
#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
-int zynq_info(Xilinx_desc *desc)
+static int zynq_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
}
/* Loop can be huge - support CTRL + C */
if (ctrlc())
- return 0;
+ return NULL;
}
- return 0;
+ return NULL;
}
-
-int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
{
- unsigned long ts; /* Timestamp */
- u32 partialbit = 0;
- u32 i, control, isr_status, status, swap, diff;
- u32 *buf_start;
-
- /* Detect if we are going working with partial or full bitstream */
- if (bsize != desc->size) {
- printf("%s: Working with partial bitstream\n", __func__);
- partialbit = 1;
- }
+ unsigned long ts;
+ u32 isr_status;
- buf_start = check_data((u8 *)buf, bsize, &swap);
- if (!buf_start)
- return FPGA_FAIL;
-
- /* Check if data is postpone from start */
- diff = (u32)buf_start - (u32)buf;
- if (diff) {
- printf("%s: Bitstream is not validated yet (diff %x)\n",
- __func__, diff);
- return FPGA_FAIL;
- }
+ /* Set up the transfer */
+ writel((u32)srcbuf, &devcfg_base->dma_src_addr);
+ writel(dstbuf, &devcfg_base->dma_dst_addr);
+ writel(srclen, &devcfg_base->dma_src_len);
+ writel(dstlen, &devcfg_base->dma_dst_len);
- if ((u32)buf < SZ_1M) {
- printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
- __func__, (u32)buf);
- return FPGA_FAIL;
- }
+ isr_status = readl(&devcfg_base->int_sts);
- if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
- u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+ /* Polling the PCAP_INIT status for Set */
+ ts = get_timer(0);
+ while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
+ if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
+ debug("%s: Error: isr = 0x%08X\n", __func__,
+ isr_status);
+ debug("%s: Write count = 0x%08X\n", __func__,
+ readl(&devcfg_base->write_count));
+ debug("%s: Read count = 0x%08X\n", __func__,
+ readl(&devcfg_base->read_count));
- /*
- * This might be dangerous but permits to flash if
- * ARCH_DMA_MINALIGN is greater than header size
- */
- if (new_buf > buf_start) {
- debug("%s: Aligned buffer is after buffer start\n",
- __func__);
- new_buf -= ARCH_DMA_MINALIGN;
+ return FPGA_FAIL;
}
+ if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
+ printf("%s: Timeout wait for DMA to complete\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(&devcfg_base->int_sts);
+ }
- printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
- (u32)buf_start, (u32)new_buf, swap);
-
- for (i = 0; i < (bsize/4); i++)
- new_buf[i] = load_word(&buf_start[i], swap);
-
- swap = SWAP_DONE;
- buf = new_buf;
- } else if (swap != SWAP_DONE) {
- /* For bitstream which are aligned */
- u32 *new_buf = (u32 *)buf;
+ debug("%s: DMA transfer is done\n", __func__);
- printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
- swap);
+ /* Clear out the DMA status */
+ writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
- for (i = 0; i < (bsize/4); i++)
- new_buf[i] = load_word(&buf_start[i], swap);
+ return FPGA_SUCCESS;
+}
- swap = SWAP_DONE;
- }
+static int zynq_dma_xfer_init(u32 partialbit)
+{
+ u32 status, control, isr_status;
+ unsigned long ts;
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
}
+ return FPGA_SUCCESS;
+}
+
+static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
+{
+ u32 *new_buf;
+ u32 i;
+
+ if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+ new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+
+ /*
+ * This might be dangerous but permits to flash if
+ * ARCH_DMA_MINALIGN is greater than header size
+ */
+ if (new_buf > buf) {
+ debug("%s: Aligned buffer is after buffer start\n",
+ __func__);
+ new_buf -= ARCH_DMA_MINALIGN;
+ }
+ printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
+ (u32)buf, (u32)new_buf, swap);
+
+ for (i = 0; i < (len/4); i++)
+ new_buf[i] = load_word(&buf[i], swap);
+
+ buf = new_buf;
+ } else if (swap != SWAP_DONE) {
+ /* For bitstream which are aligned */
+ u32 *new_buf = (u32 *)buf;
+
+ printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+ swap);
+
+ for (i = 0; i < (len/4); i++)
+ new_buf[i] = load_word(&buf[i], swap);
+ }
+
+ return buf;
+}
+
+static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
+ size_t bsize, u32 blocksize, u32 *swap,
+ u32 *partialbit)
+{
+ u32 *buf_start;
+ u32 diff;
+
+ /* Detect if we are going working with partial or full bitstream */
+ if (bsize != desc->size) {
+ printf("%s: Working with partial bitstream\n", __func__);
+ *partialbit = 1;
+ }
+ buf_start = check_data((u8 *)buf, blocksize, swap);
+
+ if (!buf_start)
+ return FPGA_FAIL;
+
+ /* Check if data is postpone from start */
+ diff = (u32)buf_start - (u32)buf;
+ if (diff) {
+ printf("%s: Bitstream is not validated yet (diff %x)\n",
+ __func__, diff);
+ return FPGA_FAIL;
+ }
+
+ if ((u32)buf < SZ_1M) {
+ printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
+ __func__, (u32)buf);
+ return FPGA_FAIL;
+ }
+
+ if (zynq_dma_xfer_init(*partialbit))
+ return FPGA_FAIL;
+
+ return 0;
+}
+
+
+static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+{
+ unsigned long ts; /* Timestamp */
+ u32 partialbit = 0;
+ u32 isr_status, swap;
+
+ /*
+ * send bsize inplace of blocksize as it was not a bitstream
+ * in chunks
+ */
+ if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
+ &partialbit))
+ return FPGA_FAIL;
+
+ buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
+
debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
debug("%s: Size = %zu\n", __func__, bsize);
flush_dcache_range((u32)buf, (u32)buf +
roundup(bsize, ARCH_DMA_MINALIGN));
- /* Set up the transfer */
- writel((u32)buf | 1, &devcfg_base->dma_src_addr);
- writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
- writel(bsize >> 2, &devcfg_base->dma_src_len);
- writel(0, &devcfg_base->dma_dst_len);
+ if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
+ return FPGA_FAIL;
isr_status = readl(&devcfg_base->int_sts);
-
- /* Polling the PCAP_INIT status for Set */
- ts = get_timer(0);
- while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
- if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
- debug("%s: Error: isr = 0x%08X\n", __func__,
- isr_status);
- debug("%s: Write count = 0x%08X\n", __func__,
- readl(&devcfg_base->write_count));
- debug("%s: Read count = 0x%08X\n", __func__,
- readl(&devcfg_base->read_count));
-
- return FPGA_FAIL;
- }
- if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
- printf("%s: Timeout wait for DMA to complete\n",
- __func__);
- return FPGA_FAIL;
- }
- isr_status = readl(&devcfg_base->int_sts);
- }
-
- debug("%s: DMA transfer is done\n", __func__);
-
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
debug("%s: FPGA config done\n", __func__);
- /* Clear out the DMA status */
- writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
-
if (!partialbit)
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS;
}
-int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op zynq_op = {
+ .load = zynq_load,
+ .dump = zynq_dump,
+ .info = zynq_info,
+};
#
obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
-obj-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
obj-$(CONFIG_DW_I2C) += designware_i2c.o
obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
/*
* TI DaVinci (TMS320DM644x) I2C driver.
*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
* --------------------------------------------------------
*
* SPDX-License-Identifier: GPL-2.0+
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/arch/i2c_defs.h>
+#include <asm/io.h>
+#include "davinci_i2c.h"
#define CHECK_NACK() \
do {\
if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
- REG(I2C_CON) = 0;\
- return(1);\
- }\
+ REG(&(i2c_base->i2c_con)) = 0;\
+ return 1;\
+ } \
} while (0)
+static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap);
-static int wait_for_bus(void)
+static int wait_for_bus(struct i2c_adapter *adap)
{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
int stat, timeout;
- REG(I2C_STAT) = 0xffff;
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
for (timeout = 0; timeout < 10; timeout++) {
- if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
- REG(I2C_STAT) = 0xffff;
- return(0);
+ stat = REG(&(i2c_base->i2c_stat));
+ if (!((stat) & I2C_STAT_BB)) {
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ return 0;
}
- REG(I2C_STAT) = stat;
+ REG(&(i2c_base->i2c_stat)) = stat;
udelay(50000);
}
- REG(I2C_STAT) = 0xffff;
- return(1);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ return 1;
}
-static int poll_i2c_irq(int mask)
+static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
int stat, timeout;
for (timeout = 0; timeout < 10; timeout++) {
udelay(1000);
- stat = REG(I2C_STAT);
- if (stat & mask) {
- return(stat);
- }
+ stat = REG(&(i2c_base->i2c_stat));
+ if (stat & mask)
+ return stat;
}
- REG(I2C_STAT) = 0xffff;
- return(stat | I2C_TIMEOUT);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ return stat | I2C_TIMEOUT;
}
-
-void flush_rx(void)
+static void flush_rx(struct i2c_adapter *adap)
{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+
while (1) {
- if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
+ if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
break;
- REG(I2C_DRR);
- REG(I2C_STAT) = I2C_STAT_RRDY;
+ REG(&(i2c_base->i2c_drr));
+ REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
udelay(1000);
}
}
+static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+ uint32_t div, psc;
+
+ psc = 2;
+ /* SCLL + SCLH */
+ div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
+ REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
+ REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
+ REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
+
+ adap->speed = speed;
+ return 0;
+}
-void i2c_init(int speed, int slaveadd)
+static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
- u_int32_t div, psc;
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
- if (REG(I2C_CON) & I2C_CON_EN) {
- REG(I2C_CON) = 0;
- udelay (50000);
+ if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
+ REG(&(i2c_base->i2c_con)) = 0;
+ udelay(50000);
}
- psc = 2;
- div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
- REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
- REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
- REG(I2C_SCLH) = div - REG(I2C_SCLL);
+ davinci_i2c_setspeed(adap, speed);
- REG(I2C_OA) = slaveadd;
- REG(I2C_CNT) = 0;
+ REG(&(i2c_base->i2c_oa)) = slaveadd;
+ REG(&(i2c_base->i2c_cnt)) = 0;
/* Interrupts must be enabled or I2C module won't work */
- REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
+ REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
/* Now enable I2C controller (get it out of reset) */
- REG(I2C_CON) = I2C_CON_EN;
+ REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
udelay(1000);
}
-int i2c_set_bus_speed(unsigned int speed)
-{
- i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
- return 0;
-}
-
-int i2c_probe(u_int8_t chip)
+static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
int rc = 1;
- if (chip == REG(I2C_OA)) {
- return(rc);
- }
+ if (chip == REG(&(i2c_base->i2c_oa)))
+ return rc;
- REG(I2C_CON) = 0;
- if (wait_for_bus()) {return(1);}
+ REG(&(i2c_base->i2c_con)) = 0;
+ if (wait_for_bus(adap))
+ return 1;
/* try to read one byte from current (or only) address */
- REG(I2C_CNT) = 1;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
- udelay (50000);
+ REG(&(i2c_base->i2c_cnt)) = 1;
+ REG(&(i2c_base->i2c_sa)) = chip;
+ REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+ I2C_CON_STP);
+ udelay(50000);
- if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
+ if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
rc = 0;
- flush_rx();
- REG(I2C_STAT) = 0xffff;
+ flush_rx(adap);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
} else {
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CON) |= I2C_CON_STP;
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
udelay(20000);
- if (wait_for_bus()) {return(1);}
+ if (wait_for_bus(adap))
+ return 1;
}
- flush_rx();
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CNT) = 0;
- return(rc);
+ flush_rx(adap);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&(i2c_base->i2c_cnt)) = 0;
+ return rc;
}
-
-int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+ uint32_t addr, int alen, uint8_t *buf, int len)
{
- u_int32_t tmp;
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+ uint32_t tmp;
int i;
if ((alen < 0) || (alen > 2)) {
- printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
- return(1);
+ printf("%s(): bogus address length %x\n", __func__, alen);
+ return 1;
}
- if (wait_for_bus()) {return(1);}
+ if (wait_for_bus(adap))
+ return 1;
if (alen != 0) {
/* Start address phase */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
- REG(I2C_CNT) = alen;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = tmp;
+ REG(&(i2c_base->i2c_cnt)) = alen;
+ REG(&(i2c_base->i2c_sa)) = chip;
+ REG(&(i2c_base->i2c_con)) = tmp;
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+ tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK();
switch (alen) {
- case 2:
- /* Send address MSByte */
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = (addr >> 8) & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
-
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
- CHECK_NACK();
- /* No break, fall through */
- case 1:
- /* Send address LSByte */
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = addr & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
-
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
-
- CHECK_NACK();
-
- if (!(tmp & I2C_STAT_ARDY)) {
- REG(I2C_CON) = 0;
- return(1);
- }
+ case 2:
+ /* Send address MSByte */
+ if (tmp & I2C_STAT_XRDY) {
+ REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
+ } else {
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
+ }
+
+ tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
+
+ CHECK_NACK();
+ /* No break, fall through */
+ case 1:
+ /* Send address LSByte */
+ if (tmp & I2C_STAT_XRDY) {
+ REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
+ } else {
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
+ }
+
+ tmp = poll_i2c_irq(adap, I2C_STAT_XRDY |
+ I2C_STAT_NACK | I2C_STAT_ARDY);
+
+ CHECK_NACK();
+
+ if (!(tmp & I2C_STAT_ARDY)) {
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
+ }
}
}
/* Address phase is over, now read 'len' bytes and stop */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
- REG(I2C_CNT) = len & 0xffff;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = tmp;
+ REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
+ REG(&(i2c_base->i2c_sa)) = chip;
+ REG(&(i2c_base->i2c_con)) = tmp;
for (i = 0; i < len; i++) {
- tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
+ tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK |
+ I2C_STAT_ROVR);
CHECK_NACK();
if (tmp & I2C_STAT_RRDY) {
- buf[i] = REG(I2C_DRR);
+ buf[i] = REG(&(i2c_base->i2c_drr));
} else {
- REG(I2C_CON) = 0;
- return(1);
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
}
}
- tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
+ tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
CHECK_NACK();
if (!(tmp & I2C_STAT_SCD)) {
- REG(I2C_CON) = 0;
- return(1);
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
}
- flush_rx();
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CNT) = 0;
- REG(I2C_CON) = 0;
+ flush_rx(adap);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&(i2c_base->i2c_cnt)) = 0;
+ REG(&(i2c_base->i2c_con)) = 0;
- return(0);
+ return 0;
}
-
-int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
+ uint32_t addr, int alen, uint8_t *buf, int len)
{
- u_int32_t tmp;
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+ uint32_t tmp;
int i;
if ((alen < 0) || (alen > 2)) {
- printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
- return(1);
+ printf("%s(): bogus address length %x\n", __func__, alen);
+ return 1;
}
if (len < 0) {
- printf("%s(): bogus length %x\n", __FUNCTION__, len);
- return(1);
+ printf("%s(): bogus length %x\n", __func__, len);
+ return 1;
}
- if (wait_for_bus()) {return(1);}
+ if (wait_for_bus(adap))
+ return 1;
/* Start address phase */
- tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
- REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = tmp;
+ tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+ I2C_CON_TRX | I2C_CON_STP;
+ REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
+ len & 0xffff : (len & 0xffff) + alen;
+ REG(&(i2c_base->i2c_sa)) = chip;
+ REG(&(i2c_base->i2c_con)) = tmp;
switch (alen) {
- case 2:
- /* Send address MSByte */
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+ case 2:
+ /* Send address MSByte */
+ tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
- CHECK_NACK();
+ CHECK_NACK();
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = (addr >> 8) & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
- /* No break, fall through */
- case 1:
- /* Send address LSByte */
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+ if (tmp & I2C_STAT_XRDY) {
+ REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
+ } else {
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
+ }
+ /* No break, fall through */
+ case 1:
+ /* Send address LSByte */
+ tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
- CHECK_NACK();
+ CHECK_NACK();
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = addr & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
+ if (tmp & I2C_STAT_XRDY) {
+ REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
+ } else {
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
+ }
}
for (i = 0; i < len; i++) {
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+ tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK();
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = buf[i];
- } else {
- return(1);
- }
+ if (tmp & I2C_STAT_XRDY)
+ REG(&(i2c_base->i2c_dxr)) = buf[i];
+ else
+ return 1;
}
- tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
+ tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
CHECK_NACK();
if (!(tmp & I2C_STAT_SCD)) {
- REG(I2C_CON) = 0;
- return(1);
+ REG(&(i2c_base->i2c_con)) = 0;
+ return 1;
}
- flush_rx();
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CNT) = 0;
- REG(I2C_CON) = 0;
+ flush_rx(adap);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&(i2c_base->i2c_cnt)) = 0;
+ REG(&(i2c_base->i2c_con)) = 0;
+
+ return 0;
+}
+
+static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
+{
+ switch (adap->hwadapnr) {
+#if I2C_BUS_MAX >= 3
+ case 2:
+ return (struct i2c_regs *)I2C2_BASE;
+#endif
+#if I2C_BUS_MAX >= 2
+ case 1:
+ return (struct i2c_regs *)I2C1_BASE;
+#endif
+ case 0:
+ return (struct i2c_regs *)I2C_BASE;
+
+ default:
+ printf("wrong hwadapnr: %d\n", adap->hwadapnr);
+ }
- return(0);
+ return NULL;
}
+
+U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
+ davinci_i2c_read, davinci_i2c_write,
+ davinci_i2c_setspeed,
+ CONFIG_SYS_DAVINCI_I2C_SPEED,
+ CONFIG_SYS_DAVINCI_I2C_SLAVE,
+ 0)
+
+#if I2C_BUS_MAX >= 2
+U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
+ davinci_i2c_read, davinci_i2c_write,
+ davinci_i2c_setspeed,
+ CONFIG_SYS_DAVINCI_I2C_SPEED1,
+ CONFIG_SYS_DAVINCI_I2C_SLAVE1,
+ 1)
+#endif
+
+#if I2C_BUS_MAX >= 3
+U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
+ davinci_i2c_read, davinci_i2c_write,
+ davinci_i2c_setspeed,
+ CONFIG_SYS_DAVINCI_I2C_SPEED2,
+ CONFIG_SYS_DAVINCI_I2C_SLAVE2,
+ 2)
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004-2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DAVINCI_I2C_H_
+#define _DAVINCI_I2C_H_
+
+#define I2C_WRITE 0
+#define I2C_READ 1
+
+struct i2c_regs {
+ u32 i2c_oa;
+ u32 i2c_ie;
+ u32 i2c_stat;
+ u32 i2c_scll;
+ u32 i2c_sclh;
+ u32 i2c_cnt;
+ u32 i2c_drr;
+ u32 i2c_sa;
+ u32 i2c_dxr;
+ u32 i2c_con;
+ u32 i2c_iv;
+ u32 res_2c;
+ u32 i2c_psc;
+};
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK 7
+#define I2C_INTCODE_NONE 0
+#define I2C_INTCODE_AL 1 /* Arbitration lost */
+#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY 3 /* Register access ready */
+#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
+#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
+#define I2C_INTCODE_SCD 6 /* Stop condition detect */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 5) /* I2C module enable */
+#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */
+#define I2C_CON_XA (1 << 8) /* Expand address */
+#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
+#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
+
+#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
+
+#endif
*/
#define TWSI_FREQUENCY(m, n) \
- ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))))
-
-/*
- * These are required to be reprogrammed before enabling the controller
- * because a reset loses them.
- * Default values come from the spec, but a twsi_reset will change them.
- * twsi_slave_address left uninitialized lest checkpatch.pl complains.
- */
-
-/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */
-static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */
-/* Default frequency corresponding to default m=4, n=4 */
-static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4);
-/* Default slave address is 0 (so is an uninitialized static) */
-static u8 twsi_slave_address;
+ (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
/*
* Reset controller.
* Controller reset also resets the baud rate and slave address, so
* re-establish them.
*/
-static void twsi_reset(void)
+static void twsi_reset(u8 baud_rate, u8 slave_address)
{
/* ensure controller will be enabled by any twsi*() function */
twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
/* wait 2 ms -- this is what the Marvell LSP does */
udelay(20000);
/* set baud rate */
- writel(twsi_baud_rate, &twsi->baudrate);
+ writel(baud_rate, &twsi->baudrate);
/* set slave address even though we don't use it */
- writel(twsi_slave_address, &twsi->slave_address);
+ writel(slave_address, &twsi->slave_address);
writel(0, &twsi->xtnd_slave_addr);
/* assert STOP but don't care for the result */
(void) twsi_stop(0);
}
}
}
- /* save baud rate and slave for later calls to twsi_reset */
- twsi_baud_rate = baud;
- twsi_actual_speed = highest_speed;
- twsi_slave_address = slaveadd;
/* reset controller */
- twsi_reset();
+ twsi_reset(baud, slaveadd);
}
/*
break;
}
#ifdef DEBUG
- zynq_i2c_debug_status(zynq_i2c));
+ zynq_i2c_debug_status(zynq_i2c);
#endif
/* Clear interrupt status flags */
writel(int_status & mask, &zynq_i2c->interrupt_status);
clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
#ifdef DEBUG
- zynq_i2c_debug_status();
+ zynq_i2c_debug_status(zynq_i2c);
#endif
return 0;
}
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o
obj-$(CONFIG_SPL_NAND_INIT) += nand.o
+ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
+obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
+endif
else # not spl
#include <linux/mtd/nand_ecc.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-static nand_info_t mtd;
+nand_info_t nand_info[1];
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = nand_info[0].priv;
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(&nand_info[0]))
;
/* Emulate NAND_CMD_READOOB */
}
/* Begin command latch cycle */
- hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_RESET) {
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&mtd))
+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ while (!this->dev_ready(&nand_info[0]))
;
return 0;
}
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- hwctrl(&mtd, offs & 0xff,
+ hwctrl(&nand_info[0], offs & 0xff,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+ hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+ hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_READ0) {
/* Latch in address */
- hwctrl(&mtd, NAND_CMD_READSTART,
+ hwctrl(&nand_info[0], NAND_CMD_READSTART,
NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(&nand_info[0]))
;
} else if (cmd == NAND_CMD_RNDOUT) {
- hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+ hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
}
return 0;
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = nand_info[0].priv;
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
NAND_CMD_READOOB);
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = nand_info[0].priv;
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
nand_command(block, page, 0, NAND_CMD_READ0);
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(&mtd, NAND_ECC_READ);
+ this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
- this->read_buf(&mtd, p, eccsize);
+ this->read_buf(&nand_info[0], p, eccsize);
nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
- this->read_buf(&mtd, oob, eccbytes);
- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ this->read_buf(&nand_info[0], oob, eccbytes);
+ this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
data_pos += eccsize;
oob_pos += eccbytes;
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
/*
* Init board specific nand support
*/
- mtd.priv = &nand_chip;
+ nand_info[0].priv = &nand_chip;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, 0);
+ nand_chip.select_chip(&nand_info[0], 0);
/* NAND chip may require reset after power-on */
nand_command(0, 0, 0, NAND_CMD_RESET);
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, -1);
+ nand_chip.select_chip(&nand_info[0], -1);
}
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
nand->bbt_options |= NAND_BBT_USE_FLASH;
#endif
+#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
#include <spi_flash.h>
#include <spl.h>
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Load the kernel, check for a valid header we can parse, and if found load
+ * the kernel and then device tree.
+ */
+static int spi_load_image_os(struct spi_flash *flash,
+ struct image_header *header)
+{
+ /* Read for a header, parse or error out. */
+ spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40,
+ (void *)header);
+
+ if (image_get_magic(header) != IH_MAGIC)
+ return -1;
+
+ spl_parse_image_header(header);
+
+ spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
+ spl_image.size, (void *)spl_image.load_addr);
+
+ /* Read device tree. */
+ spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS,
+ CONFIG_SYS_SPI_ARGS_SIZE,
+ (void *)CONFIG_SYS_SPL_ARGS_ADDR);
+
+ return 0;
+}
+#endif
+
/*
* The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
/* use CONFIG_SYS_TEXT_BASE as temporary storage area */
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
- /* Load u-boot, mkimage header is 64 bytes. */
- spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
- (void *)header);
- spl_parse_image_header(header);
- spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
- spl_image.size, (void *)spl_image.load_addr);
+#ifdef CONFIG_SPL_OS_BOOT
+ if (spl_start_uboot() || spi_load_image_os(flash, header))
+#endif
+ {
+ /* Load u-boot, mkimage header is 64 bytes. */
+ spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
+ (void *)header);
+ spl_parse_image_header(header);
+ spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+ spl_image.size, (void *)spl_image.load_addr);
+ }
}
obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GRETH) += greth.o
+obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
if (!phydev)
return -1;
+ phy_connect_dev(phydev, dev);
+
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
if (!is_valid_ether_addr(dev->enetaddr)) {
#ifdef CONFIG_RANDOM_MACADDR
printf("Bad MAC address (uninitialized EEPROM?), randomizing\n");
- eth_random_enetaddr(dev->enetaddr);
+ eth_random_addr(dev->enetaddr);
printf("MAC: %pM\n", dev->enetaddr);
#else
printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
obj-$(CONFIG_PPC_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o
obj-$(CONFIG_PPC_T4160) += t4240.o
+obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- } else {
+ } else
setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
- }
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- } else {
+ } else
setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
- }
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
dev->recv = ftmac110_recv;
if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr))
- eth_random_enetaddr(dev->enetaddr);
+ eth_random_addr(dev->enetaddr);
/* allocate tx descriptors (it must be 16 bytes aligned) */
chip->txd = dma_alloc_coherent(
--- /dev/null
+/*
+ * Ethernet driver for TI K2HK EVM.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+
+#include <net.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/keystone_nav.h>
+
+unsigned int emac_dbg;
+
+unsigned int emac_open;
+static unsigned int sys_has_mdio = 1;
+
+#ifdef KEYSTONE2_EMAC_GIG_ENABLE
+#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
+#else
+#define emac_gigabit_enable(x) /* no gigabit to enable */
+#endif
+
+#define RX_BUFF_NUMS 24
+#define RX_BUFF_LEN 1520
+#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
+
+static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
+
+struct rx_buff_desc net_rx_buffs = {
+ .buff_ptr = rx_buffs,
+ .num_buffs = RX_BUFF_NUMS,
+ .buff_len = RX_BUFF_LEN,
+ .rx_flow = 22,
+};
+
+static void keystone2_eth_mdio_enable(void);
+
+static int gen_get_link_speed(int phy_addr);
+
+/* EMAC Addresses */
+static volatile struct emac_regs *adap_emac =
+ (struct emac_regs *)EMAC_EMACSL_BASE_ADDR;
+static volatile struct mdio_regs *adap_mdio =
+ (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
+
+int keystone2_eth_read_mac_addr(struct eth_device *dev)
+{
+ struct eth_priv_t *eth_priv;
+ u32 maca = 0;
+ u32 macb = 0;
+
+ eth_priv = (struct eth_priv_t *)dev->priv;
+
+ /* Read the e-fuse mac address */
+ if (eth_priv->slave_port == 1) {
+ maca = __raw_readl(MAC_ID_BASE_ADDR);
+ macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
+ }
+
+ dev->enetaddr[0] = (macb >> 8) & 0xff;
+ dev->enetaddr[1] = (macb >> 0) & 0xff;
+ dev->enetaddr[2] = (maca >> 24) & 0xff;
+ dev->enetaddr[3] = (maca >> 16) & 0xff;
+ dev->enetaddr[4] = (maca >> 8) & 0xff;
+ dev->enetaddr[5] = (maca >> 0) & 0xff;
+
+ return 0;
+}
+
+static void keystone2_eth_mdio_enable(void)
+{
+ u_int32_t clkdiv;
+
+ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+
+ writel((clkdiv & 0xffff) |
+ MDIO_CONTROL_ENABLE |
+ MDIO_CONTROL_FAULT |
+ MDIO_CONTROL_FAULT_ENABLE,
+ &adap_mdio->control);
+
+ while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
+ ;
+}
+
+/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
+int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
+{
+ int tmp;
+
+ while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
+ ;
+
+ writel(MDIO_USERACCESS0_GO |
+ MDIO_USERACCESS0_WRITE_READ |
+ ((reg_num & 0x1f) << 21) |
+ ((phy_addr & 0x1f) << 16),
+ &adap_mdio->useraccess0);
+
+ /* Wait for command to complete */
+ while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
+ ;
+
+ if (tmp & MDIO_USERACCESS0_ACK) {
+ *data = tmp & 0xffff;
+ return 0;
+ }
+
+ *data = -1;
+ return -1;
+}
+
+/*
+ * Write to a PHY register via MDIO inteface.
+ * Blocks until operation is complete.
+ */
+int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
+{
+ while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
+ ;
+
+ writel(MDIO_USERACCESS0_GO |
+ MDIO_USERACCESS0_WRITE_WRITE |
+ ((reg_num & 0x1f) << 21) |
+ ((phy_addr & 0x1f) << 16) |
+ (data & 0xffff),
+ &adap_mdio->useraccess0);
+
+ /* Wait for command to complete */
+ while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
+ ;
+
+ return 0;
+}
+
+/* PHY functions for a generic PHY */
+static int gen_get_link_speed(int phy_addr)
+{
+ u_int16_t tmp;
+
+ if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) &&
+ (tmp & 0x04)) {
+ return 0;
+ }
+
+ return -1;
+}
+
+static void __attribute__((unused))
+ keystone2_eth_gigabit_enable(struct eth_device *dev)
+{
+ u_int16_t data;
+ struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+
+ if (sys_has_mdio) {
+ if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) ||
+ !(data & (1 << 6))) /* speed selection MSB */
+ return;
+ }
+
+ /*
+ * Check if link detected is giga-bit
+ * If Gigabit mode detected, enable gigbit in MAC
+ */
+ writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) |
+ EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
+ &(adap_emac[eth_priv->slave_port - 1].maccontrol))
+ ;
+}
+
+int keystone_sgmii_link_status(int port)
+{
+ u32 status = 0;
+
+ status = __raw_readl(SGMII_STATUS_REG(port));
+
+ return status & SGMII_REG_STATUS_LINK;
+}
+
+
+int keystone_get_link_status(struct eth_device *dev)
+{
+ struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+ int sgmii_link;
+ int link_state = 0;
+#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
+ int j;
+
+ for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
+ j++) {
+#endif
+ sgmii_link =
+ keystone_sgmii_link_status(eth_priv->slave_port - 1);
+
+ if (sgmii_link) {
+ link_state = 1;
+
+ if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
+ if (gen_get_link_speed(eth_priv->phy_addr))
+ link_state = 0;
+ }
+#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
+ }
+#endif
+ return link_state;
+}
+
+int keystone_sgmii_config(int port, int interface)
+{
+ unsigned int i, status, mask;
+ unsigned int mr_adv_ability, control;
+
+ switch (interface) {
+ case SGMII_LINK_MAC_MAC_AUTONEG:
+ mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
+ SGMII_REG_MR_ADV_LINK |
+ SGMII_REG_MR_ADV_FULL_DUPLEX |
+ SGMII_REG_MR_ADV_GIG_MODE);
+ control = (SGMII_REG_CONTROL_MASTER |
+ SGMII_REG_CONTROL_AUTONEG);
+
+ break;
+ case SGMII_LINK_MAC_PHY:
+ case SGMII_LINK_MAC_PHY_FORCED:
+ mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
+ control = SGMII_REG_CONTROL_AUTONEG;
+
+ break;
+ case SGMII_LINK_MAC_MAC_FORCED:
+ mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
+ SGMII_REG_MR_ADV_LINK |
+ SGMII_REG_MR_ADV_FULL_DUPLEX |
+ SGMII_REG_MR_ADV_GIG_MODE);
+ control = SGMII_REG_CONTROL_MASTER;
+
+ break;
+ case SGMII_LINK_MAC_FIBER:
+ mr_adv_ability = 0x20;
+ control = SGMII_REG_CONTROL_AUTONEG;
+
+ break;
+ default:
+ mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
+ control = SGMII_REG_CONTROL_AUTONEG;
+ }
+
+ __raw_writel(0, SGMII_CTL_REG(port));
+
+ /*
+ * Wait for the SerDes pll to lock,
+ * but don't trap if lock is never read
+ */
+ for (i = 0; i < 1000; i++) {
+ udelay(2000);
+ status = __raw_readl(SGMII_STATUS_REG(port));
+ if ((status & SGMII_REG_STATUS_LOCK) != 0)
+ break;
+ }
+
+ __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
+ __raw_writel(control, SGMII_CTL_REG(port));
+
+
+ mask = SGMII_REG_STATUS_LINK;
+
+ if (control & SGMII_REG_CONTROL_AUTONEG)
+ mask |= SGMII_REG_STATUS_AUTONEG;
+
+ for (i = 0; i < 1000; i++) {
+ status = __raw_readl(SGMII_STATUS_REG(port));
+ if ((status & mask) == mask)
+ break;
+ }
+
+ return 0;
+}
+
+int mac_sl_reset(u32 port)
+{
+ u32 i, v;
+
+ if (port >= DEVICE_N_GMACSL_PORTS)
+ return GMACSL_RET_INVALID_PORT;
+
+ /* Set the soft reset bit */
+ DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) +
+ CPGMACSL_REG_RESET, CPGMAC_REG_RESET_VAL_RESET);
+
+ /* Wait for the bit to clear */
+ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
+ v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) +
+ CPGMACSL_REG_RESET);
+ if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
+ CPGMAC_REG_RESET_VAL_RESET)
+ return GMACSL_RET_OK;
+ }
+
+ /* Timeout on the reset */
+ return GMACSL_RET_WARN_RESET_INCOMPLETE;
+}
+
+int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
+{
+ u32 v, i;
+ int ret = GMACSL_RET_OK;
+
+ if (port >= DEVICE_N_GMACSL_PORTS)
+ return GMACSL_RET_INVALID_PORT;
+
+ if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
+ cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
+ ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
+ }
+
+ /* Must wait if the device is undergoing reset */
+ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
+ v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) +
+ CPGMACSL_REG_RESET);
+ if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
+ CPGMAC_REG_RESET_VAL_RESET)
+ break;
+ }
+
+ if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
+ return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
+
+ DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN,
+ cfg->max_rx_len);
+
+ DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL,
+ cfg->ctl);
+
+ return ret;
+}
+
+int ethss_config(u32 ctl, u32 max_pkt_size)
+{
+ u32 i;
+
+ /* Max length register */
+ DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_MAXLEN, max_pkt_size);
+
+ /* Control register */
+ DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_CTL, ctl);
+
+ /* All statistics enabled by default */
+ DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN,
+ CPSW_REG_VAL_STAT_ENABLE_ALL);
+
+ /* Reset and enable the ALE */
+ DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL,
+ CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
+ CPSW_REG_VAL_ALE_CTL_BYPASS);
+
+ /* All ports put into forward mode */
+ for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
+ DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i),
+ CPSW_REG_VAL_PORTCTL_FORWARD_MODE);
+
+ return 0;
+}
+
+int ethss_start(void)
+{
+ int i;
+ struct mac_sl_cfg cfg;
+
+ cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
+ cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
+
+ for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
+ mac_sl_reset(i);
+ mac_sl_config(i, &cfg);
+ }
+
+ return 0;
+}
+
+int ethss_stop(void)
+{
+ int i;
+
+ for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
+ mac_sl_reset(i);
+
+ return 0;
+}
+
+int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
+{
+ if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
+ num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
+
+ return netcp_send(buffer, num_bytes, (slave_port_num) << 16);
+}
+
+/* Eth device open */
+static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
+{
+ u_int32_t clkdiv;
+ int link;
+ struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+
+ debug("+ emac_open\n");
+
+ net_rx_buffs.rx_flow = eth_priv->rx_flow;
+
+ sys_has_mdio =
+ (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
+
+ psc_enable_module(KS2_LPSC_PA);
+ psc_enable_module(KS2_LPSC_CPGMAC);
+
+ sgmii_serdes_setup_156p25mhz();
+
+ if (sys_has_mdio)
+ keystone2_eth_mdio_enable();
+
+ keystone_sgmii_config(eth_priv->slave_port - 1,
+ eth_priv->sgmii_link_type);
+
+ udelay(10000);
+
+ /* On chip switch configuration */
+ ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
+
+ /* TODO: add error handling code */
+ if (qm_init()) {
+ printf("ERROR: qm_init()\n");
+ return -1;
+ }
+ if (netcp_init(&net_rx_buffs)) {
+ qm_close();
+ printf("ERROR: netcp_init()\n");
+ return -1;
+ }
+
+ /*
+ * Streaming switch configuration. If not present this
+ * statement is defined to void in target.h.
+ * If present this is usually defined to a series of register writes
+ */
+ hw_config_streaming_switch();
+
+ if (sys_has_mdio) {
+ /* Init MDIO & get link state */
+ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+ writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE |
+ MDIO_CONTROL_FAULT, &adap_mdio->control)
+ ;
+
+ /* We need to wait for MDIO to start */
+ udelay(1000);
+
+ link = keystone_get_link_status(dev);
+ if (link == 0) {
+ netcp_close();
+ qm_close();
+ return -1;
+ }
+ }
+
+ emac_gigabit_enable(dev);
+
+ ethss_start();
+
+ debug("- emac_open\n");
+
+ emac_open = 1;
+
+ return 0;
+}
+
+/* Eth device close */
+void keystone2_eth_close(struct eth_device *dev)
+{
+ debug("+ emac_close\n");
+
+ if (!emac_open)
+ return;
+
+ ethss_stop();
+
+ netcp_close();
+ qm_close();
+
+ emac_open = 0;
+
+ debug("- emac_close\n");
+}
+
+static int tx_send_loop;
+
+/*
+ * This function sends a single packet on the network and returns
+ * positive number (number of bytes transmitted) or negative for error
+ */
+static int keystone2_eth_send_packet(struct eth_device *dev,
+ void *packet, int length)
+{
+ int ret_status = -1;
+ struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+
+ tx_send_loop = 0;
+
+ if (keystone_get_link_status(dev) == 0)
+ return -1;
+
+ emac_gigabit_enable(dev);
+
+ if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
+ return ret_status;
+
+ if (keystone_get_link_status(dev) == 0)
+ return -1;
+
+ emac_gigabit_enable(dev);
+
+ return length;
+}
+
+/*
+ * This function handles receipt of a packet from the network
+ */
+static int keystone2_eth_rcv_packet(struct eth_device *dev)
+{
+ void *hd;
+ int pkt_size;
+ u32 *pkt;
+
+ hd = netcp_recv(&pkt, &pkt_size);
+ if (hd == NULL)
+ return 0;
+
+ NetReceive((uchar *)pkt, pkt_size);
+
+ netcp_release_rxhd(hd);
+
+ return pkt_size;
+}
+
+/*
+ * This function initializes the EMAC hardware.
+ */
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
+{
+ struct eth_device *dev;
+
+ dev = malloc(sizeof(struct eth_device));
+ if (dev == NULL)
+ return -1;
+
+ memset(dev, 0, sizeof(struct eth_device));
+
+ strcpy(dev->name, eth_priv->int_name);
+ dev->priv = eth_priv;
+
+ keystone2_eth_read_mac_addr(dev);
+
+ dev->iobase = 0;
+ dev->init = keystone2_eth_open;
+ dev->halt = keystone2_eth_close;
+ dev->send = keystone2_eth_send_packet;
+ dev->recv = keystone2_eth_rcv_packet;
+
+ eth_register(dev);
+
+ return 0;
+}
+
+void sgmii_serdes_setup_156p25mhz(void)
+{
+ unsigned int cnt;
+
+ /*
+ * configure Serializer/Deserializer (SerDes) hardware. SerDes IP
+ * hardware vendor published only register addresses and their values
+ * to be used for configuring SerDes. So had to use hardcoded values
+ * below.
+ */
+ clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
+ clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
+ clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
+ clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
+ clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
+
+ clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
+ clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
+ clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
+ clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
+ clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
+ clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
+ clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
+ clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
+ clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
+ clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
+
+ clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
+ clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
+ clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
+ clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
+ clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
+ clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
+ clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
+ clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
+ clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
+ clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
+
+ clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
+ clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
+ clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
+ clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
+ clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
+ clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
+ clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
+ clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
+ clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
+ clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
+
+ clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
+ clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
+ clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
+ clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
+ clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
+ clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
+ clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
+ clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
+ clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
+ clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
+
+ clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
+ clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
+ clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
+ clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
+ clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
+ clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
+ clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
+ clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
+ clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
+ clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
+ clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
+ clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
+
+ clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
+ clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
+ clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
+ clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
+ clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
+ clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
+ clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
+ clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
+ clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
+ clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
+ clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
+ clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
+ clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
+
+ /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
+ clrbits_le32(0x0232a010, 1 << 28);
+
+ /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
+ clrbits_le32(0x0232a228, 1 << 29);
+ writel(0xF800F8C0, 0x0232bfe0);
+ clrbits_le32(0x0232a428, 1 << 29);
+ writel(0xF800F8C0, 0x0232bfe4);
+ clrbits_le32(0x0232a628, 1 << 29);
+ writel(0xF800F8C0, 0x0232bfe8);
+ clrbits_le32(0x0232a828, 1 << 29);
+ writel(0xF800F8C0, 0x0232bfec);
+
+ /*Enable pll via the pll_ctrl 0x0014*/
+ writel(0xe0000000, 0x0232bff4)
+ ;
+
+ /*Waiting for SGMII Serdes PLL lock.*/
+ for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--)
+ ;
+
+ for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--)
+ ;
+
+ for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--)
+ ;
+
+ for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--)
+ ;
+
+ udelay(45000);
+}
+
+void sgmii_serdes_shutdown(void)
+{
+ /*
+ * shutdown SerDes hardware. SerDes hardware vendor published only
+ * register addresses and their values. So had to use hardcoded
+ * values below.
+ */
+ clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13);
+ setbits_le32(0x02320228, 1 << 29);
+ clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13);
+ setbits_le32(0x02320428, 1 << 29);
+ clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13);
+ setbits_le32(0x02320628, 1 << 29);
+ clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13);
+ setbits_le32(0x02320828, 1 << 29);
+
+ clrbits_le32(0x02320034, 3 << 29);
+ setbits_le32(0x02320010, 1 << 28);
+}
regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
- genphy_config_aneg(phydev);
-
- phy_reset(phydev);
+ phydev->supported = phydev->drv->features;
return 0;
}
#include <phy.h>
#include <errno.h>
#include <linux/err.h>
+#include <linux/compiler.h>
/* Generic PHY support and helper functions */
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, stores it in @phy_id and returns zero on success.
*/
-static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
#define MIIM_VSC8514_18G_QSGMII 0x80e0
#define MIIM_VSC8514_18G_CMDSTAT 0x8000
+/* Vitesse VSC8664 Control/Status Register */
+#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
+#define MIIM_VSC8664_ADDITIONAL_DEV 0x16
+#define MIIM_VSC8664_EPHY_CON 0x17
+#define MIIM_VSC8664_LED_CON 0x1E
+
+#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
+
/* CIS8201 */
static int vitesse_config(struct phy_device *phydev)
{
return 0;
}
+static int vsc8664_config(struct phy_device *phydev)
+{
+ u32 val;
+
+ /* Enable MAC interface auto-negotiation */
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
+ val |= (1 << 13);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+ PHY_EXT_PAGE_ACCESS_EXTENDED);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
+ val |= (1 << 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+ /* Enable LED blink */
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
+ val &= ~(1 << 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static struct phy_driver VSC8211_driver = {
.name = "Vitesse VSC8211",
.uid = 0xfc4b0,
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8664_driver = {
+ .name = "Vitesse VSC8664",
+ .uid = 0x70660,
+ .mask = 0xffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8664_config,
+ .startup = &vitesse_startup,
+ .shutdown = &genphy_shutdown,
+};
+
/* Vitesse bought Cicada, so we'll put these here */
static struct phy_driver cis8201_driver = {
.name = "CIS8201",
phy_register(&VSC8574_driver);
phy_register(&VSC8514_driver);
phy_register(&VSC8662_driver);
+ phy_register(&VSC8664_driver);
phy_register(&cis8201_driver);
phy_register(&cis8204_driver);
u64 size)
{
u32 sz = (__ilog2_u64(size) - 1);
- u32 flag = PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ u32 flag = 0;
+#else
+ u32 flag = PIWAR_LOCAL;
+#endif
+
+ flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
out_be32(&pi->pitar, r->phys_start >> 12);
out_be32(&pi->piwbar, r->bus_start >> 12);
};
#define MAX_I2C_RETRY 3
-int tps6586x_read(int reg)
+static int tps6586x_read(int reg)
{
int i;
uchar data;
return retval;
}
-int tps6586x_write(int reg, uchar *data, uint len)
+static int tps6586x_write(int reg, uchar *data, uint len)
{
int i;
int retval = -1;
#include "asm/immap_qe.h"
#include "qe.h"
+#define MPC85xx_DEVDISR_QE_DISABLE 0x1
+
qe_map_t *qe_immr = NULL;
static qe_snum_t snums[QE_NUM_OF_SNUM];
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
-
+#ifdef CONFIG_DEEP_SLEEP
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
if (!firmware) {
printf("Invalid address\n");
return -EINVAL;
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
return -EPERM;
}
#define serial_in(y) readb(y)
#endif
+#if defined(CONFIG_K2HK_EVM)
+#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
+#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
+#undef UART_MCRVAL
+#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
+#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
+#else
+#define UART_MCRVAL (UART_MCR_RTS)
+#endif
+#endif
+
#ifndef CONFIG_SYS_NS16550_IER
#define CONFIG_SYS_NS16550_IER 0x00
#endif /* CONFIG_SYS_NS16550_IER */
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, &com_port->mdr1);
#endif /* CONFIG_OMAP */
+#if defined(CONFIG_K2HK_EVM)
+ serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
+#endif
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
}
gd->baudrate = baudrate;
-#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
- gd->bd->bi_baudrate = baudrate;
-#endif
serial_setbrg();
unsigned char c;
int ret, saved_baud, b;
struct serial_device *saved_dev, *s;
- bd_t *bd = gd->bd;
/* Save current serial state */
ret = 0;
saved_dev = serial_current;
- saved_baud = bd->bi_baudrate;
+ saved_baud = gd->baudrate;
for (s = serial_devices; s; s = s->next) {
/* If this driver doesn't support loop back, skip it */
/* Test every available baud rate */
for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
- bd->bi_baudrate = bauds[b];
+ gd->baudrate = bauds[b];
serial_setbrg();
/*
done:
/* Restore previous serial state */
serial_current = saved_dev;
- bd->bi_baudrate = saved_baud;
+ gd->baudrate = saved_baud;
serial_reinit_all();
serial_setbrg();
if (!ds)
return NULL;
- ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE;
+ ds->slave.bus = bus;
+ ds->slave.cs = cs;
+
+ switch (bus) {
+ case SPI0_BUS:
+ ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
+ break;
+#ifdef CONFIG_SYS_SPI1
+ case SPI1_BUS:
+ ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
+ break;
+#endif
+#ifdef CONFIG_SYS_SPI2
+ case SPI2_BUS:
+ ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
+ break;
+#endif
+ default: /* Invalid bus number */
+ return NULL;
+ }
+
ds->freq = max_hz;
return &ds->slave;
writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
/* CS, CLK, SIMO and SOMI are functional pins */
- writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK |
+ writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
/* setup format */
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- return bus == 0 && cs == 0;
+ int ret = 0;
+
+ switch (bus) {
+ case SPI0_BUS:
+ if (cs < SPI0_NUM_CS)
+ ret = 1;
+ break;
+#ifdef CONFIG_SYS_SPI1
+ case SPI1_BUS:
+ if (cs < SPI1_NUM_CS)
+ ret = 1;
+ break;
+#endif
+#ifdef CONFIG_SYS_SPI2
+ case SPI2_BUS:
+ if (cs < SPI2_NUM_CS)
+ ret = 1;
+ break;
+#endif
+ default:
+ /* Invalid bus number. Do nothing */
+ break;
+ }
+ return ret;
}
void spi_cs_activate(struct spi_slave *slave)
/* SPIDEF */
#define SPIDEF_CSDEF0_MASK BIT(0)
+#define SPI0_BUS 0
+#define SPI0_BASE CONFIG_SYS_SPI_BASE
+/*
+ * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
+ * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
+ * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
+ */
+#ifndef CONFIG_SYS_SPI0
+#define SPI0_NUM_CS 1
+#else
+#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
+#endif
+
+/*
+ * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
+ * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
+ */
+#ifdef CONFIG_SYS_SPI1
+#define SPI1_BUS 1
+#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
+#define SPI1_BASE CONFIG_SYS_SPI1_BASE
+#endif
+
+/*
+ * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
+ * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
+ */
+#ifdef CONFIG_SYS_SPI2
+#define SPI2_BUS 2
+#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
+#define SPI2_BASE CONFIG_SYS_SPI2_BASE
+#endif
+
struct davinci_spi_slave {
struct spi_slave slave;
struct davinci_spi_regs *regs;
* SPI pins on Tegra20 are muxed - change pinmux later due to UART
* issue.
*/
- pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
- pinmux_tristate_disable(PINGRP_LSPI);
- pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
+ pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
+ pinmux_tristate_disable(PMUX_PINGRP_LSPI);
+ pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
return 0;
}
qslave->cmd |= QSPI_RD_SNGL;
debug("rx cmd %08x dc %08x\n",
qslave->cmd, qslave->dc);
+ #ifdef CONFIG_DRA7XX
+ udelay(500);
+ #endif
writel(qslave->cmd, &qslave->base->cmd);
status = readl(&qslave->base->status);
timeout = QSPI_TIMEOUT;
if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
- setbits_be32(&ehci->control, UTMI_PHY_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_UTMI);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ UTMI_PHY_EN);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
- setbits_be32(&ehci->control, USB_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ USB_EN);
} else {
- setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
- clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_ULPI);
+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+ CONTROL_REGISTER_W1C_MASK, USB_EN);
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
#include <asm/arch/clock.h>
#include <asm/arch-tegra/usb.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch/usb.h>
#include <usb.h>
#include <usb/ulpi.h>
#include <libfdt.h>
if (config->periph_id == PERIPH_ID_USBD)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
+ if (config->periph_id == PERIPH_ID_USB2)
+ clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+ UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
if (config->periph_id == PERIPH_ID_USB3)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+#if defined(CONFIG_TEGRA20)
+ if (config->periph_id == PERIPH_ID_USBD) {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
+ PTS_UTMI << PTS1_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS1);
+ } else {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
+ }
+#else
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS);
+ clrbits_le32(&usbctlr->hostpc1_devlc, STS);
+#endif
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
/* Select ULPI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+#if defined(CONFIG_TEGRA20)
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_ULPI << PTS_SHIFT);
+#else
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+ PTS_ULPI << PTS_SHIFT);
+#endif
/* enable ULPI transceiver */
setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
lcdc_writel(®s->lcdc_lcdcfg1, value);
- value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
- value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
+ value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
+ value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
lcdc_writel(®s->lcdc_lcdcfg2, value);
- value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
- value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
+ value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
+ value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
lcdc_writel(®s->lcdc_lcdcfg3, value);
/* Display size */
#include <common.h>
#include <asm/errno.h>
+#include <asm/global_data.h>
#include <linux/string.h>
#include <linux/list.h>
#include <linux/fb.h>
#include "mxcfb.h"
#include "ipu_regs.h"
+DECLARE_GLOBAL_DATA_PTR;
+
static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
fbi->screen_size = fbi->fix.smem_len;
+ gd->fb_base = fbi->fix.smem_start;
+
/* Clear the screen */
memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
break;
case STAGE_PWM:
/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
- pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM);
- pinmux_tristate_disable(PINGRP_GPU);
+ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_GPU);
pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
break;
restart:
fs->curr_blkno++;
/* get the blockbitmap index respective to blockno */
- if (fs->blksz != 1024) {
- bg_idx = fs->curr_blkno / blk_per_grp;
- } else {
- bg_idx = fs->curr_blkno / blk_per_grp;
+ bg_idx = fs->curr_blkno / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = fs->curr_blkno % blk_per_grp;
if (!remainder)
bg_idx--;
return blknr;
}
-void ext4fs_close(void)
+/**
+ * ext4fs_reinit_global() - Reinitialize values of ext4 write implementation's
+ * global pointers
+ *
+ * This function assures that for a file with the same name but different size
+ * the sequential store on the ext4 filesystem will be correct.
+ *
+ * In this function the global data, responsible for internal representation
+ * of the ext4 data are initialized to the reset state. Without this, during
+ * replacement of the smaller file with the bigger truncation of new file was
+ * performed.
+ */
+void ext4fs_reinit_global(void)
{
- if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) {
- ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen);
- ext4fs_file = NULL;
- }
- if (ext4fs_root != NULL) {
- free(ext4fs_root);
- ext4fs_root = NULL;
- }
if (ext4fs_indir1_block != NULL) {
free(ext4fs_indir1_block);
ext4fs_indir1_block = NULL;
ext4fs_indir3_blkno = -1;
}
}
+void ext4fs_close(void)
+{
+ if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) {
+ ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen);
+ ext4fs_file = NULL;
+ }
+ if (ext4fs_root != NULL) {
+ free(ext4fs_root);
+ ext4fs_root = NULL;
+ }
+
+ ext4fs_reinit_global();
+}
int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
struct ext2fs_node **fnode, int *ftype)
if (inode->b.blocks.indir_block != 0) {
debug("SIPB releasing %u\n", inode->b.blocks.indir_block);
blknr = inode->b.blocks.indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
break;
debug("DICB releasing %u\n", *di_buffer);
- if (fs->blksz != 1024) {
- bg_idx = (*di_buffer) / blk_per_grp;
- } else {
- bg_idx = (*di_buffer) / blk_per_grp;
- remainder = (*di_buffer) % blk_per_grp;
+ bg_idx = *di_buffer / blk_per_grp;
+ if (fs->blksz == 1024) {
+ remainder = *di_buffer % blk_per_grp;
if (!remainder)
bg_idx--;
}
/* removing the parent double indirect block */
blknr = inode->b.blocks.double_indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
for (j = 0; j < fs->blksz / sizeof(int); j++) {
if (*tip_buffer == 0)
break;
- if (fs->blksz != 1024) {
- bg_idx = (*tip_buffer) / blk_per_grp;
- } else {
- bg_idx = (*tip_buffer) / blk_per_grp;
-
- remainder = (*tip_buffer) % blk_per_grp;
+ bg_idx = *tip_buffer / blk_per_grp;
+ if (fs->blksz == 1024) {
+ remainder = *tip_buffer % blk_per_grp;
if (!remainder)
bg_idx--;
}
* removing the grand parent blocks
* which is connected to inode
*/
- if (fs->blksz != 1024) {
- bg_idx = (*tigp_buffer) / blk_per_grp;
- } else {
- bg_idx = (*tigp_buffer) / blk_per_grp;
-
- remainder = (*tigp_buffer) % blk_per_grp;
+ bg_idx = *tigp_buffer / blk_per_grp;
+ if (fs->blksz == 1024) {
+ remainder = *tigp_buffer % blk_per_grp;
if (!remainder)
bg_idx--;
}
/* removing the grand parent triple indirect block */
blknr = inode->b.blocks.triple_indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
for (i = 0; i < no_blocks; i++) {
blknr = read_allocated_block(&(node_inode->inode), i);
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
no_blocks++;
for (i = 0; i < no_blocks; i++) {
blknr = read_allocated_block(&inode, i);
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
ext4fs_update();
ext4fs_deinit();
+ ext4fs_reinit_global();
if (ext4fs_init() != 0) {
printf("error in File System init\n");
__u32 ret = 0x00;
__u16 val1, val2;
+ if (CHECK_CLUST(entry, mydata->fatsize)) {
+ printf("Error: Invalid FAT entry: 0x%08x\n", entry);
+ return ret;
+ }
+
switch (mydata->fatsize) {
case 32:
bufnum = entry / FAT32BUFSIZE;
return dentptr;
}
+ /*
+ * In FAT16/12, the root dir is locate before data area, shows
+ * in following:
+ * -------------------------------------------------------------
+ * | Boot | FAT1 & 2 | Root dir | Data (start from cluster #2) |
+ * -------------------------------------------------------------
+ *
+ * As a result if curclust is in Root dir, it is a negative
+ * number or 0, 1.
+ *
+ */
+ if (mydata->fatsize != 32 && (int)curclust <= 1) {
+ /* Current clust is in root dir, set to next clust */
+ curclust++;
+ if ((int)curclust <= 1)
+ continue; /* continue to find */
+
+ /* Reach the end of root dir */
+ empty_dentptr = dentptr;
+ return NULL;
+ }
+
curclust = get_fatent_value(mydata, dir_curclust);
- if ((curclust >= 0xffffff8) || (curclust >= 0xfff8)) {
+ if (IS_LAST_CLUST(curclust, mydata->fatsize)) {
empty_dentptr = dentptr;
return NULL;
}
}
mydata->fatbufnum = -1;
- mydata->fatbuf = malloc(FATBUFSIZE);
+ mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
if (mydata->fatbuf == NULL) {
debug("Error: allocating memory\n");
return -1;
ubifs_msg("reserved for root: %llu bytes (%llu KiB)",
c->report_rp_size, c->report_rp_size >> 10);
- dbg_msg("compiled on: " __DATE__ " at " __TIME__);
dbg_msg("min. I/O unit size: %d bytes", c->min_io_size);
dbg_msg("LEB size: %d bytes (%d KiB)",
c->leb_size, c->leb_size >> 10);
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
+#ifdef CONFIG_MPC85xx
+ulong cpu_init_f(void);
+#endif
int cpu_init_r (void);
#if defined(CONFIG_MPC8260)
#include <u-boot/crc.h>
/* lib/rand.c */
-#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND)
#define RAND_MAX -1U
void srand(unsigned int seed);
unsigned int rand(void);
unsigned int rand_r(unsigned int *seedp);
-#endif
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
#define CONFIG_LIB_RAND
#endif
+#if defined(CONFIG_API) && defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#endif
+
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> "
#endif
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* B4860 QDS board configuration file
*/
#define IDT_SERDES1_ADDRESS 0x6E
#define IDT_SERDES2_ADDRESS 0x6C
+/* Voltage monitor on channel 2*/
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_ZM7300
+#define I2C_MUX_CH_DPM 0xa
+#define I2C_DPM_ADDR 0x28
+
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=b4860qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=b4860qds/b4860qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/* For emulation this causes u-boot to jump to the start of the proof point
app code automatically */
#endif
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/* High Level Configuration Options */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#ifdef CONFIG_P1011RDB
#define CONFIG_P1011
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P1020RDB
#define CONFIG_P1020
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P2010RDB
#define CONFIG_P2010
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_P2020RDB
#define CONFIG_P2020
-#endif
-
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
+#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
- /*
- * Config the L2 Cache as L2 SRAM
- */
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
+#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
+/*
+ * P1020 and it's derivatives support max 32bit DDR width
+ * So Reduce available DDR size
+*/
+#define CONFIG_SYS_SDRAM_SIZE 512
+#else
+#define CONFIG_SYS_SDRAM_SIZE 1024
+#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
- defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
+#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
- #define CONFIG_ENV_IS_IN_SPI_FLASH
- #define CONFIG_ENV_SPI_BUS 0
- #define CONFIG_ENV_SPI_CS 0
- #define CONFIG_ENV_SPI_MAX_HZ 10000000
- #define CONFIG_ENV_SPI_MODE 0
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
- #define CONFIG_ENV_SECT_SIZE 0x10000
- #define CONFIG_ENV_SIZE 0x2000
-#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (512 * 0x800)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
+
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"ramdiskfile=t1040qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t1040qds/t1040qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
"ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
"fdtaddr=c00000\0" \
"fdtfile=" __stringify(FDTFILE) "\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=t2080qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080qds/t2080qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
"ramdiskfile=t2080rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080rdb/t2080rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
"ramdiskfile=t4240emu/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240emu/t4240emu.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the proof point
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=t4240qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T4240 RDB board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240RDB
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
+#endif
+
+#define CONFIG_DDR_ECC
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ 133333333
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x52
+#define SPD_EEPROM_ADDRESS2 0x54
+#define SPD_EEPROM_ADDRESS3 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_MUX_CH_VSC3316_FS 0xc
+#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_CORTINA
+#define CONFIG_CORTINA_FW_ADDR 0xefe00000
+#define CONFIG_CORTINA_FW_LENGTH 0x40000
+#define CONFIG_PHY_TERANETICS
+#define SGMII_PHY_ADDR1 0x0
+#define SGMII_PHY_ADDR2 0x1
+#define SGMII_PHY_ADDR3 0x2
+#define SGMII_PHY_ADDR4 0x3
+#define SGMII_PHY_ADDR5 0x4
+#define SGMII_PHY_ADDR6 0x5
+#define SGMII_PHY_ADDR7 0x6
+#define SGMII_PHY_ADDR8 0x7
+#define FM1_10GEC1_PHY_ADDR 0x10
+#define FM1_10GEC2_PHY_ADDR 0x11
+#define FM2_10GEC1_PHY_ADDR 0x12
+#define FM2_10GEC2_PHY_ADDR 0x13
+#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
+#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240rdb/t4240rdb.dtb\0" \
+ "bdev=sda3\0"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#ifdef CONFIG_SECURE_BOOT
+/* Secure Boot target was not getting build for T4240 because of
+ * increased binary size. So the size is being reduced by removing USB
+ * which is anyways not used in Secure Environment.
+ */
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* __CONFIG_H */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "fdt_high=0xffffffff\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"boot_fdt=try\0" \
- "rdaddr=0x81000000\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"nfsopts=nolock\0" \
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
"::off\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+ "ramroot=/dev/ram0 rw\0" \
"ramrootfstype=ext2\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-/* SPI flash. */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND
* 0x442000 - 0x800000 : Userland
*/
#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
-#undef CONFIG_SPL_SPI_SUPPORT
#ifdef CONFIG_NOR_BOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ (128 << 20))
#define CONFIG_SPL_YMODEM_SUPPORT
/* Enabling L2 Cache */
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
-/* SPI SPL */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "fdt_high=0xffffffff\0" \
- "rdaddr=0x81000000\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"usbroot=/dev/sda2 rw\0" \
"usbrootfstype=ext4 rootwait\0" \
"usbdev=0\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+ "ramroot=/dev/ram0 rw\0" \
"ramrootfstype=ext2\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
#define CONFIG_ROOTPATH "/romfs/brettl2"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
#endif
#define CONFIG_PHY_ADDR 3
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf526-ezbrd
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf527-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf537-pnav
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_ROOTPATH "/romfs"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_RESET_PHY_R
/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define CONFIG_HOSTNAME cm-bf527
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME cm-bf537e
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME cm-bf537u
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p4080ds/p4080ds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
/*
* I2C Configuration
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
-#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*
* I2C EEPROM definitions for catalyst 24W256 EEPROM chip
/*
* I2C Configuration
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 25000
-#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
/*
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define DM9000_DATA (CONFIG_DM9000_BASE + 16)
/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x10
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10
/* NAND */
#define CONFIG_NAND_DAVINCI
#define CONFIG_NET_RETRY_COUNT 10
/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define CONFIG_BAUDRATE 115200
/* I2C Configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 10
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
/*===================*/
/* I2C Configuration */
/*===================*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
/*===================*/
/* I2C Configuration */
/*===================*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/* I2C Configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
/*===================*/
/* I2C Configuration */
/*===================*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
+
+#define CONFIG_LIB_RAND
#endif
/*
#define CONFIG_DRA7XX
+#ifndef CONFIG_QSPI_BOOT
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_ENV_OFFSET 0xE0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
#define CONFIG_CMD_SAVEENV
#if (CONFIG_CONS_INDEX == 1)
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x010000 : QSPI.SPL (64KiB)
+ * 0x010000 - 0x020000 : QSPI.SPL.backup1 (64KiB)
+ * 0x020000 - 0x030000 : QSPI.SPL.backup2 (64KiB)
+ * 0x030000 - 0x040000 : QSPI.SPL.backup3 (64KiB)
+ * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
+ * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
+ * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
+ * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
+ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
+ * 0x9E0000 - 0x2000000 : USERLAND
+ */
+#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
+#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
+#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
+#if defined(CONFIG_QSPI_BOOT)
+/* In SPL, use the environment and discard MMC support for space. */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SPL_MMC_SUPPORT
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE (64 << 10) /* 64 KiB */
+#endif
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
+#define CONFIG_ENV_OFFSET 0x1C0000
+#define CONFIG_ENV_OFFSET_REDUND 0x1D0000
+#endif
+
/* SPI SPL */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_SUPPORT_EMMC_BOOT
/*
* I2C Configuration
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*
* Network & Ethernet Configuration
/*
* I2C Configuration
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
#define CONFIG_CMD_I2C
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <config_distro_defaults.h>
+
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_FIT
-#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_SYS_TIMER_RATE (150000000/256)
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_CALXEDA_XGMAC
-/* PXE support */
-#define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
-#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.highbank"
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_SCSI
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
#define CONFIG_AUTOBOOT_KEYED
/*
* Miscellaneous configurable options
*/
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PROMPT "Highbank #"
-#define CONFIG_SYS_HUSH_PARSER
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_HZ 1000
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
+#define CONFIG_LIB_RAND
/*
* Flash Settings
--- /dev/null
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* Enable fdt support for Jetson TK1. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra124-jetson-tk1
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra124 (Jetson TK1) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS 6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Configuration header file for TI's k2hk-evm
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_K2HK_EVM_H
+#define __CONFIG_K2HK_EVM_H
+
+/* Platform type */
+#define CONFIG_SOC_K2HK
+#define CONFIG_K2HK_EVM
+
+/* U-Boot Build Configuration */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
+#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_THUMB_BUILD
+
+/* SoC Configuration */
+#define CONFIG_ARMV7
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_TEXT_BASE 0x0c001000
+#define CONFIG_SPL_TARGET "u-boot-spi.gph"
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory Configuration */
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
+#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
+#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE 0x0c200000
+#define CONFIG_SPL_PAD_TO 65536
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
+#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
+#define CONFIG_SPL_STACK_SIZE (8 * 1024)
+#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
+ CONFIG_SYS_SPL_MALLOC_SIZE + \
+ CONFIG_SPL_STACK_SIZE - 4)
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SPL_FRAMEWORK
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 K2HK_UART0_BASE
+#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* SPI Configuration */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI0
+#define CONFIG_SYS_SPI_BASE K2HK_SPI_BASE
+#define CONFIG_SYS_SPI0_NUM_CS 4
+#define CONFIG_SYS_SPI1
+#define CONFIG_SYS_SPI1_BASE K2HK_SPI1_BASE
+#define CONFIG_SYS_SPI1_NUM_CS 4
+#define CONFIG_SYS_SPI2
+#define CONFIG_SYS_SPI2_NUM_CS 4
+#define CONFIG_SYS_SPI2_BASE K2HK_SPI2_BASE
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_SPI_CLK clk_get_rate(K2HK_LPSC_EMIF25_SPI)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
+#define I2C_BUS_MAX 3
+
+/* EEPROM definitions */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 32
+#define CONFIG_NET_MULTI
+#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
+#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
+#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
+#define CONFIG_SYS_SGMII_RATESCALE 2
+
+/* NAND Configuration */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
+ "1024k(bootloader)ro,512k(params)ro," \
+ "-(ubifs)"
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_EEPROM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT "K2HK EVM # "
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE 2048
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "boot=ramfs\0" \
+ "tftp_root=/\0" \
+ "nfs_root=/export\0" \
+ "mem_lpae=1\0" \
+ "mem_reserve=512M\0" \
+ "addr_fdt=0x87000000\0" \
+ "addr_kern=0x88000000\0" \
+ "addr_mon=0x0c5f0000\0" \
+ "addr_uboot=0x87000000\0" \
+ "addr_fs=0x82000000\0" \
+ "addr_ubi=0x82000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "name_fdt=uImage-k2hk-evm.dtb\0" \
+ "name_fs=arago-console-image.cpio.gz\0" \
+ "name_kern=uImage-keystone-evm.bin\0" \
+ "name_mon=skern-keystone-evm.bin\0" \
+ "name_uboot=u-boot-spi-keystone-evm.gph\0" \
+ "name_ubi=keystone-evm-ubifs.ubi\0" \
+ "run_mon=mon_install ${addr_mon}\0" \
+ "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
+ "init_net=run args_all args_net\0" \
+ "init_ubi=run args_all args_ubi; " \
+ "ubi part ubifs; ubifsmount boot\0" \
+ "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
+ "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
+ "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
+ "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
+ "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
+ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
+ "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
+ "burn_uboot=sf probe; sf erase 0 0x100000; " \
+ "sf write ${addr_uboot} 0 ${filesize}\0" \
+ "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
+ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
+ "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
+ "${nfs_options} ip=dhcp\0" \
+ "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
+ "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
+ "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
+ "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
+ "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
+ "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
+ "burn_ubi=nand erase.part ubifs; " \
+ "nand write ${addr_ubi} ubifs ${filesize}\0" \
+ "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
+ "args_ramfs=setenv bootargs ${bootargs} earlyprintk " \
+ "rdinit=/sbin/init rw root=/dev/ram0 " \
+ "initrd=0x802000000,9M\0" \
+ "no_post=1\0" \
+ "mtdparts=mtdparts=davinci_nand.0:" \
+ "1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0"
+#define CONFIG_BOOTCOMMAND \
+ "run init_${boot} get_fdt_${boot} get_mon_${boot} " \
+ "get_kern_${boot} run_mon run_kern"
+#define CONFIG_BOOTARGS \
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_SYS_BARGSIZE 1024
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* we may include files below only after all above definitions */
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#define CONFIG_SYS_HZ_CLOCK clk_get_rate(K2HK_CLK1_6)
+
+#endif /* __CONFIG_K2HK_EVM_H */
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
/*
* Config the L3 Cache as L3 SRAM
#define CONFIG_KM_PNVRAM 0x80000
/* physical RAM MTD size [hex] */
#define CONFIG_KM_PHRAM 0x100000
-/* resereved pram area at the end of memroy [hex] */
-#define CONFIG_KM_RESERVED_PRAM 0x0
-/* enable protected RAM */
-#define CONFIG_PRAM 0
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page */
+#define CONFIG_KM_RESERVED_PRAM 0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
#define CONFIG_KM_CRAMFS_ADDR 0x2000000
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
*/
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
+#define CONFIG_CMD_ERRATA
/* we don't need flash support */
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+
/*
- * High Level Configuration Options
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs. We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <configs/ti_omap3_common.h>
/*
* Display CPU and Board information
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
#define CONFIG_MISC_INIT_R
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
-
-/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
/* Status LED */
#define CONFIG_STATUS_LED 1
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_FS_GENERIC /* Generic FS support */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
"1920k(u-boot),128k(u-boot-env),"\
"4m(kernel),-(fs)"
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_USB_STORAGE /* USB storage support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_LED /* LED support */
-#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
-#define CONFIG_CMD_NFS /* NFS support */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
#define CONFIG_CMD_GPIO /* Enable gpio command */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
/*
* TWL4030
*/
-#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/*
*/
#define CONFIG_SYS_NAND_QUIET_TEST 1
#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-/* Environment information */
-#define CONFIG_BOOTDELAY 3
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"rdaddr=0x81000000\0" \
"run mmcbootz; " \
"fi; " \
-#define CONFIG_AUTO_COMPLETE 1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_ALT_MEMTEST 1
-#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
- /* defaults */
-#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
-#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
- /* load address */
-
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#endif
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
#define CONFIG_OMAP3_SPI
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE 0x40200800
-#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
#endif /* __CONFIG_H */
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_NAND
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
+#include <configs/ti_omap3_common.h>
+
+/* Remove SPL boot option - we do not support that on LDP yet */
+#undef CONFIG_SPL
+#undef CONFIG_SPL_FRAMEWORK
+#undef CONFIG_SPL_OS_BOOT
+
+/* Generic NAND definition conflicts with debug_base */
+#undef CONFIG_SYS_NAND_BASE
/*
* Display CPU and Board information
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
#define CONFIG_MISC_INIT_R
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3 /* UART3 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
-
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND /* NAND support */
+#if defined(CONFIG_CMD_NAND)
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
+#endif
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
-#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
-#undef CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#undef CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
*/
-#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/*
* Board NAND Info.
*/
-#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
- /* partition */
/* Environment information */
-#define CONFIG_BOOTDELAY 10
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
+ "fdtaddr=0x80f80000\0" \
+ "bootfile=uImage\0" \
+ "fdtfile=omap3-ldp.dtb\0" \
+ "bootdir=/\0" \
+ "bootpart=0:1\0" \
"usbtty=cdc_acm\0" \
- "console=ttyS2,115200n8\0" \
+ "console=ttyO2,115200n8\0" \
"mmcdev=0\0" \
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
+ "mmczboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
- "if run loaduimage; then " \
+ "if run loadimage; then " \
"run mmcboot; " \
+ "else if run loadzimage; then " \
+ "run mmczboot; " \
"else run nandboot; " \
- "fi; " \
+ "fi; fi;" \
"fi; " \
"else run nandboot; fi"
-#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # "
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
- /* works on */
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) /* memtest */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_2 + \
0x01F00000) /* 31MB */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
- /* load address */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#endif
#define CONFIG_SYS_CACHELINE_SIZE 64
+#ifdef CONFIG_CMD_NET
+/* Ethernet (LAN9211 from SMSC9118 family) */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE DEBUG_BASE
+
+#endif
+
#endif /* __CONFIG_H */
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_ENV_OFFSET 0xE0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#endif
#endif
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
#define CONFIG_MMC
#ifdef CONFIG_MMC
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CROS_EC
#define CONFIG_CMD_CROS_EC
#define CONFIG_CROS_EC_SANDBOX
-#define CONFIG_KEYBOARD
-#define CONFIG_CROS_EC_KEYB
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SOUND_SANDBOX
#define CONFIG_CMD_SOUND
+#ifndef SANDBOX_NO_SDL
#define CONFIG_SANDBOX_SDL
+#endif
+
+/* LCD and keyboard require SDL support */
+#ifdef CONFIG_SANDBOX_SDL
#define CONFIG_LCD
#define CONFIG_VIDEO_SANDBOX_SDL
#define CONFIG_CMD_BMP
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define LCD_BPP LCD_COLOR16
+#define CONFIG_CROS_EC_KEYB
+#define CONFIG_KEYBOARD
+
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
+#else
+
+#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+#endif
#define CONFIG_GZIP_COMPRESSED
#define CONFIG_BZIP2
#ifndef __T4QDS_H
#define __T4QDS_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
#define CONFIG_HOSTNAME tcm-bf518
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME tcm-bf537
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
*/
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ (128 << 20))
/* Enable the watchdog inside of SPL */
#define CONFIG_SPL_WATCHDOG_SUPPORT
/* Common define for many platforms. */
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
/*
* We typically do not contain NOR flash. In the cases where we do, we
/*
* Our DDR memory always starts at 0x80000000 and U-Boot shall have
* relocated itself to higher in memory by the time this value is used.
+ * However, set this to a 32MB offset to allow for easier Linux kernel
+ * booting as the default is often used as the kernel load address.
*/
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+/*
+ * We setup defaults based on constraints from the Linux kernel, which should
+ * also be safe elsewhere. We have the default load at 32MB into DDR (for
+ * the kernel), FDT above 128MB (the maximum location for the end of the
+ * kernel), and the ramdisk 512KB above that (allowing for hopefully never
+ * seen large trees). We say all of this must be within the first 256MB
+ * as that will normally be within the kernel lowmem and thus visible via
+ * bootm_size and we only run on platforms with 256MB or more of memory.
+ */
+#define DEFAULT_LINUX_BOOT_ENV \
+ "loadaddr=0x82000000\0" \
+ "kernel_addr_r=0x82000000\0" \
+ "fdtaddr=0x88000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "rdaddr=0x88080000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+ "bootm_size=0x10000000\0"
/*
* Default to a quick boot delay.
*/
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
+#ifndef CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE 0x8000000
+#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
#endif
* We have the SPL malloc pool at the end of the BSS area.
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
+#endif
+#ifndef CONFIG_SPL_BSS_START_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+#endif
+#ifndef CONFIG_SYS_SPL_MALLOC_START
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
+#endif
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
-
/* FAT */
#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MTD_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
#define CONFIG_SPL_MAX_SIZE (54 * 1024)
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ (64 << 20))
+
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_NAND_BASE 0x30000000
#endif
/* Now bring in the rest of the common code. */
* Environment setup
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"console=ttyO2,115200n8\0" \
- "fdt_high=0xffffffff\0" \
- "fdtaddr=0x80f80000\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ (128 << 20))
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
-#define CONFIG_ENV_SIZE (128 << 10)
-
#include <configs/ti_armv7_common.h>
/*
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "fdt_high=0xffffffff\0" \
- "rdaddr=0x81000000\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ (128 << 20))
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
int ext4fs_read(char *buf, unsigned len);
int ext4fs_mount(unsigned part_length);
void ext4fs_close(void);
+void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
int ext4fs_exists(const char *filename);
void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
#define START(dent) (FAT2CPU16((dent)->start) \
+ (mydata->fatsize != 32 ? 0 : \
(FAT2CPU16((dent)->starthi) << 16)))
+#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \
+ ((fatsize) != 16 ? 0xff8 : 0xfff8) : \
+ 0xffffff8))
#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
- (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0))
+ (x) >= ((fatsize) != 32 ? \
+ ((fatsize) != 16 ? 0xff0 : 0xfff0) : \
+ 0xffffff0))
typedef struct boot_sector {
__u8 ignored[3]; /* Bootstrap code */
#endif
void ft_board_setup(void *blob, bd_t *bd);
+/*
+ * The keystone2 SOC requires all 32 bit aliased addresses to be converted
+ * to their 36 physical format. This has to happen after all fdt nodes
+ * are added or modified by the image_setup_libfdt(). The ft_board_setup_ex()
+ * called at the end of the image_setup_libfdt() is to do that convertion.
+ */
+void ft_board_setup_ex(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
void ft_pci_setup(void *blob, bd_t *bd);
#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */
#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */
#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */
+#define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */
/*
* Compression Types
extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr);
-#ifdef CONFIG_RANDOM_MACADDR
-/*
- * The u-boot policy does not allow hardcoded ethernet addresses. Under the
- * following circumstances a random generated address is allowed:
- * - in emergency cases, where you need a working network connection to set
- * the ethernet address.
- * Eg. you want a rescue boot and don't have a serial port to access the
- * CLI to set environment variables.
- *
- * In these cases, we generate a random locally administered ethernet address.
- *
- * Args:
- * enetaddr - returns 6 byte hardware address
- */
-extern void eth_random_enetaddr(uchar *enetaddr);
-#endif
-
extern int usb_eth_initialize(bd_t *bi);
extern int eth_init(bd_t *bis); /* Initialize the device */
extern int eth_send(void *packet, int length); /* Send a packet */
return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
}
+/**
+ * eth_random_addr - Generate software assigned random Ethernet address
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Generate a random Ethernet address (MAC) that is not multicast
+ * and has the local assigned bit set.
+ */
+static inline void eth_random_addr(uchar *addr)
+{
+ int i;
+ unsigned int seed = get_timer(0);
+
+ for (i = 0; i < 6; i++)
+ addr[i] = rand_r(&seed);
+
+ addr[0] &= 0xfe; /* clear multicast bit */
+ addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+}
+
/* Convert an IP address to a string */
extern void ip_to_string(IPaddr_t x, char *s);
#define UART_MCR_OUT1 0x04 /* Out 1 */
#define UART_MCR_OUT2 0x08 /* Out 2 */
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
#define UART_MCR_DMA_EN 0x04
#define UART_MCR_TX_DFR 0x08
#include <xilinx.h>
-extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan2_info(Xilinx_desc *desc);
-
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Spartan2_Slave_Parallel_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_spartan2_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
- Xilinx_post_fn post;
-} Xilinx_Spartan2_Slave_Serial_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fn wr;
+ xilinx_post_fn post;
+} xilinx_spartan2_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan2_op;
/* Device Image Sizes
*********************************************************************/
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
#endif /* _SPARTAN2_H_ */
#include <xilinx.h>
-extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan3_info(Xilinx_desc *desc);
-
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Spartan3_Slave_Parallel_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_spartan3_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
- Xilinx_post_fn post;
- Xilinx_bwr_fn bwr; /* block write function */
- Xilinx_abort_fn abort;
-} Xilinx_Spartan3_Slave_Serial_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fn wr;
+ xilinx_post_fn post;
+ xilinx_bwr_fn bwr; /* block write function */
+ xilinx_abort_fn abort;
+} xilinx_spartan3_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan3_op;
/* Device Image Sizes
*********************************************************************/
*********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
+ &spartan3_op }
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
+ &spartan3_op }
#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
#endif /* _SPARTAN3_H_ */
#include <asm/processor.h>
+#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
+
/* Global offsets */
#define FSL_SKIP_PCI 0x100
#include <xilinx.h>
-extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Virtex2_info(Xilinx_desc *desc);
+extern struct xilinx_fpga_op virtex2_op;
/*
* Slave SelectMap Implementation function table.
*/
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Virtex2_Slave_SelectMap_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_virtex2_slave_selectmap_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
-} Xilinx_Virtex2_Slave_Serial_fns;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+} xilinx_virtex2_slave_serial_fns;
/* Device Image Sizes (in bytes)
*********************************************************************/
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
#endif /* _VIRTEX2_H_ */
/* Xilinx types
*********************************************************************/
-typedef enum { /* typedef Xilinx_iface */
+typedef enum { /* typedef xilinx_iface */
min_xilinx_iface_type, /* low range check value */
slave_serial, /* serial data and external clock */
master_serial, /* serial data w/ internal clock (not used) */
slave_selectmap, /* slave SelectMap (virtex2) */
devcfg, /* devcfg interface (zynq) */
max_xilinx_iface_type /* insert all new types before this */
-} Xilinx_iface; /* end, typedef Xilinx_iface */
+} xilinx_iface; /* end, typedef xilinx_iface */
-typedef enum { /* typedef Xilinx_Family */
+typedef enum { /* typedef xilinx_family */
min_xilinx_type, /* low range check value */
- Xilinx_Spartan2, /* Spartan-II Family */
- Xilinx_VirtexE, /* Virtex-E Family */
- Xilinx_Virtex2, /* Virtex2 Family */
- Xilinx_Spartan3, /* Spartan-III Family */
+ xilinx_spartan2, /* Spartan-II Family */
+ xilinx_virtexE, /* Virtex-E Family */
+ xilinx_virtex2, /* Virtex2 Family */
+ xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
max_xilinx_type /* insert all new types before this */
-} Xilinx_Family; /* end, typedef Xilinx_Family */
+} xilinx_family; /* end, typedef xilinx_family */
-typedef struct { /* typedef Xilinx_desc */
- Xilinx_Family family; /* part type */
- Xilinx_iface iface; /* interface type */
+typedef struct { /* typedef xilinx_desc */
+ xilinx_family family; /* part type */
+ xilinx_iface iface; /* interface type */
size_t size; /* bytes of data part can accept */
void *iface_fns; /* interface function table */
int cookie; /* implementation specific cookie */
+ struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */
-} Xilinx_desc; /* end, typedef Xilinx_desc */
+} xilinx_desc; /* end, typedef xilinx_desc */
+
+struct xilinx_fpga_op {
+ int (*load)(xilinx_desc *, const void *, size_t);
+ int (*dump)(xilinx_desc *, const void *, size_t);
+ int (*info)(xilinx_desc *);
+};
/* Generic Xilinx Functions
*********************************************************************/
-extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int xilinx_info(Xilinx_desc *desc);
+int xilinx_load(xilinx_desc *desc, const void *image, size_t size);
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+int xilinx_info(xilinx_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
-typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie );
-typedef int (*Xilinx_init_fn)( int cookie );
-typedef int (*Xilinx_err_fn)( int cookie );
-typedef int (*Xilinx_done_fn)( int cookie );
-typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie );
-typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie );
-typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie );
-typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie );
-typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie );
-typedef int (*Xilinx_busy_fn)( int cookie );
-typedef int (*Xilinx_abort_fn)( int cookie );
-typedef int (*Xilinx_pre_fn)( int cookie );
-typedef int (*Xilinx_post_fn)( int cookie );
-typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
+typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
+typedef int (*xilinx_init_fn)(int cookie);
+typedef int (*xilinx_err_fn)(int cookie);
+typedef int (*xilinx_done_fn)(int cookie);
+typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
+typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
+typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
+typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
+typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
+typedef int (*xilinx_busy_fn)(int cookie);
+typedef int (*xilinx_abort_fn)(int cookie);
+typedef int (*xilinx_pre_fn)(int cookie);
+typedef int (*xilinx_post_fn)(int cookie);
+typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
#endif /* _XILINX_H_ */
#include <xilinx.h>
-extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int zynq_info(Xilinx_desc *desc);
+extern struct xilinx_fpga_op zynq_op;
#define XILINX_ZYNQ_7010 0x2
#define XILINX_ZYNQ_7015 0x1b
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
#endif /* _ZYNQPL_H_ */
#ifndef USE_HOSTCC
#include <common.h>
+#include <linux/string.h>
+#else
+#include <string.h>
#endif /* USE_HOSTCC */
#include <watchdog.h>
-#include <linux/string.h>
#include <sha256.h>
/*
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_B 0x10100000
-#define BOARDREV_C 0x00100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_50 50000000
-#define SYSCLK_100 100000000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- uint plat_ratio, bus_clk, sys_clk = 0;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- uint val, temp, sysclk_mask;
-
- val = pgpio->gpdat;
- sysclk_mask = val & SYSCLK_MASK;
- temp = val & BOARDREV_MASK;
- if (temp == BOARDREV_C) {
- if(sysclk_mask == 0)
- sys_clk = SYSCLK_66;
- else
- sys_clk = SYSCLK_100;
- } else if (temp == BOARDREV_B) {
- if(sysclk_mask == 0)
- sys_clk = SYSCLK_66;
- else
- sys_clk = SYSCLK_50;
- }
-
- plat_ratio = gur->porpllsr & 0x0000003e;
- plat_ratio >>= 1;
- bus_clk = plat_ratio * sys_clk;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to DDR and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
return ((skip_state = getenv(enetvar)) != NULL);
}
-#ifdef CONFIG_RANDOM_MACADDR
-void eth_random_enetaddr(uchar *enetaddr)
-{
- uint32_t rval;
-
- srand(get_timer(0));
-
- rval = rand();
- enetaddr[0] = rval & 0xff;
- enetaddr[1] = (rval >> 8) & 0xff;
- enetaddr[2] = (rval >> 16) & 0xff;
-
- rval = rand();
- enetaddr[3] = rval & 0xff;
- enetaddr[4] = (rval >> 8) & 0xff;
- enetaddr[5] = (rval >> 16) & 0xff;
-
- /* make sure it's local and unicast */
- enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01;
-}
-#endif
-
/*
* CPU and board-specific Ethernet initializations. Aliased function
* signals caller to move on
ifdef SOC
libs-y += $(CPUDIR)/$(SOC)/
endif
-libs-y += board/$(BOARDDIR)/
+libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/
libs-y += fs/
libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/
+libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/
libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
fdtdec.o \
fit_common.o \
fit_image.o \
+ gpimage.o \
+ gpimage-common.o \
image-fit.o \
image-host.o \
image.o \
--- /dev/null
+#include "../../lib/aes.c"
_min1 < _min2 ? _min1 : _min2; })
struct envdev_s {
- char devname[16]; /* Device name */
+ const char *devname; /* Device name */
ulong devoff; /* Device offset */
ulong env_size; /* environment size */
ulong erase_size; /* device erase size */
return -1;
}
#else
- strcpy (DEVNAME (0), DEVICE1_NAME);
+ DEVNAME (0) = DEVICE1_NAME;
DEVOFFSET (0) = DEVICE1_OFFSET;
ENVSIZE (0) = ENV1_SIZE;
/* Default values are: erase-size=env-size */
#endif
#ifdef HAVE_REDUND
- strcpy (DEVNAME (1), DEVICE2_NAME);
+ DEVNAME (1) = DEVICE2_NAME;
DEVOFFSET (1) = DEVICE2_OFFSET;
ENVSIZE (1) = ENV2_SIZE;
/* Default values are: erase-size=env-size */
int i = 0;
int rc;
char dump[128];
+ char *devname;
fp = fopen (fname, "r");
if (fp == NULL)
if (dump[0] == '#')
continue;
- rc = sscanf (dump, "%s %lx %lx %lx %lx",
- DEVNAME (i),
+ rc = sscanf (dump, "%ms %lx %lx %lx %lx",
+ &devname,
&DEVOFFSET (i),
&ENVSIZE (i),
&DEVESIZE (i),
if (rc < 3)
continue;
+ DEVNAME(i) = devname;
+
if (rc < 4)
/* Assume the erase size is the same as the env-size */
DEVESIZE(i) = ENVSIZE(i);
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated
+ * Refactored common functions in to gpimage-common.c. Include this common
+ * header file
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _GPIMAGE_H_
+#define _GPIMAGE_H_
+
+/* common headers for gpimage and omapimage formats */
+struct gp_header {
+ uint32_t size;
+ uint32_t load_addr;
+};
+#define GPIMAGE_HDR_SIZE (sizeof(struct gp_header))
+
+/* common functions across gpimage and omapimage handlers */
+int valid_gph_size(uint32_t size);
+int valid_gph_load_addr(uint32_t load_addr);
+int gph_verify_header(struct gp_header *gph, int be);
+void gph_print_header(const struct gp_header *gph, int be);
+void gph_set_header(struct gp_header *gph, uint32_t size, uint32_t load_addr,
+ int be);
+int gpimage_check_params(struct image_tool_params *params);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated
+ * Refactored common functions in to gpimage-common.c.
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "imagetool.h"
+#include <compiler.h>
+#include <image.h>
+#include "gpheader.h"
+
+/* Helper to convert size and load_addr to big endian */
+void to_be32(uint32_t *gph_size, uint32_t *gph_load_addr)
+{
+ *gph_size = cpu_to_be32(*gph_size);
+ *gph_load_addr = cpu_to_be32(*gph_load_addr);
+}
+
+int gph_verify_header(struct gp_header *gph, int be)
+{
+ uint32_t gph_size = gph->size, gph_load_addr = gph->load_addr;
+
+ if (be)
+ to_be32(&gph_size, &gph_load_addr);
+
+ if (!gph_size || !gph_load_addr)
+ return -1;
+
+ return 0;
+}
+
+void gph_print_header(const struct gp_header *gph, int be)
+{
+ uint32_t gph_size = gph->size, gph_load_addr = gph->load_addr;
+
+ if (be)
+ to_be32(&gph_size, &gph_load_addr);
+
+ if (!gph_size) {
+ fprintf(stderr, "Error: invalid image size %x\n", gph_size);
+ exit(EXIT_FAILURE);
+ }
+
+ if (!gph_load_addr) {
+ fprintf(stderr, "Error: invalid image load address %x\n",
+ gph_load_addr);
+ exit(EXIT_FAILURE);
+ }
+ printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr);
+}
+
+void gph_set_header(struct gp_header *gph, uint32_t size, uint32_t load_addr,
+ int be)
+{
+ gph->size = size;
+ gph->load_addr = load_addr;
+ if (be)
+ to_be32(&gph->size, &gph->load_addr);
+}
+
+int gpimage_check_params(struct image_tool_params *params)
+{
+ return (params->dflag && (params->fflag || params->lflag)) ||
+ (params->fflag && (params->dflag || params->lflag)) ||
+ (params->lflag && (params->dflag || params->fflag));
+}
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated
+ * Add gpimage format for keystone devices to format spl image. This is
+ * Based on omapimage.c
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "imagetool.h"
+#include <compiler.h>
+#include <image.h>
+#include "gpheader.h"
+
+static uint8_t gpimage_header[GPIMAGE_HDR_SIZE];
+
+/* to be in keystone gpimage */
+static int gpimage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_GPIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int gpimage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct gp_header *gph = (struct gp_header *)ptr;
+
+ return gph_verify_header(gph, 1);
+}
+
+static void gpimage_print_header(const void *ptr)
+{
+ const struct gp_header *gph = (struct gp_header *)ptr;
+
+ gph_print_header(gph, 1);
+}
+
+static void gpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ struct gp_header *gph = (struct gp_header *)ptr;
+
+ gph_set_header(gph, sbuf->st_size - GPIMAGE_HDR_SIZE, params->addr, 1);
+}
+
+/*
+ * gpimage parameters
+ */
+static struct image_type_params gpimage_params = {
+ .name = "TI KeyStone GP Image support",
+ .header_size = GPIMAGE_HDR_SIZE,
+ .hdr = (void *)&gpimage_header,
+ .check_image_type = gpimage_check_image_types,
+ .verify_header = gpimage_verify_header,
+ .print_header = gpimage_print_header,
+ .set_header = gpimage_set_header,
+ .check_params = gpimage_check_params,
+};
+
+void init_gpimage_type(void)
+{
+ register_image_type(&gpimage_params);
+}
init_ubl_image_type();
/* Init Davinci AIS support */
init_ais_image_type();
+ /* Init TI Keystone boot image generation/list support */
+ init_gpimage_type();
}
/*
void init_fit_image_type(void);
void init_ubl_image_type(void);
void init_omap_image_type(void);
+void init_gpimage_type(void);
void pbl_load_uboot(int fd, struct image_tool_params *mparams);
*/
#include "imagetool.h"
+#include <compiler.h>
#include <image.h>
+#include "gpheader.h"
#include "omapimage.h"
/* Header size is CH header rounded up to 512 bytes plus GP header */
#define OMAP_CH_HDR_SIZE 512
-#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
-#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
+#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE)
static int do_swap32 = 0;
-static uint32_t omapimage_swap32(uint32_t data)
-{
- uint32_t result = 0;
- result = (data & 0xFF000000) >> 24;
- result |= (data & 0x00FF0000) >> 8;
- result |= (data & 0x0000FF00) << 8;
- result |= (data & 0x000000FF) << 24;
- return result;
-}
-
static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
static int omapimage_check_image_types(uint8_t type)
{
if (type == IH_TYPE_OMAPIMAGE)
return EXIT_SUCCESS;
- else {
- return EXIT_FAILURE;
- }
-}
-
-/*
- * Only the simplest image type is currently supported:
- * TOC pointing to CHSETTINGS
- * TOC terminator
- * CHSETTINGS
- *
- * padding to OMAP_CH_HDR_SIZE bytes
- *
- * gp header
- * size
- * load_addr
- */
-static int valid_gph_size(uint32_t size)
-{
- return size;
-}
-
-static int valid_gph_load_addr(uint32_t load_addr)
-{
- return load_addr;
+ return EXIT_FAILURE;
}
static int omapimage_verify_header(unsigned char *ptr, int image_size,
{
struct ch_toc *toc = (struct ch_toc *)ptr;
struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
- uint32_t offset, size, gph_size, gph_load_addr;
+ uint32_t offset, size;
while (toc->section_offset != 0xffffffff
&& toc->section_size != 0xffffffff) {
if (do_swap32) {
- offset = omapimage_swap32(toc->section_offset);
- size = omapimage_swap32(toc->section_size);
+ offset = cpu_to_be32(toc->section_offset);
+ size = cpu_to_be32(toc->section_size);
} else {
offset = toc->section_offset;
size = toc->section_size;
toc++;
}
- if (do_swap32) {
- gph_size = omapimage_swap32(gph->size);
- gph_load_addr = omapimage_swap32(gph->load_addr);
- } else {
- gph_size = gph->size;
- gph_load_addr = gph->load_addr;
- }
-
- if (!valid_gph_size(gph_size))
- return -1;
- if (!valid_gph_load_addr(gph_load_addr))
- return -1;
-
- return 0;
+ return gph_verify_header(gph, do_swap32);
}
static void omapimage_print_section(struct ch_settings *chs)
const struct ch_toc *toc = (struct ch_toc *)ptr;
const struct gp_header *gph =
(struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
- uint32_t offset, size, gph_size, gph_load_addr;
+ uint32_t offset, size;
while (toc->section_offset != 0xffffffff
&& toc->section_size != 0xffffffff) {
if (do_swap32) {
- offset = omapimage_swap32(toc->section_offset);
- size = omapimage_swap32(toc->section_size);
+ offset = cpu_to_be32(toc->section_offset);
+ size = cpu_to_be32(toc->section_size);
} else {
offset = toc->section_offset;
size = toc->section_size;
toc++;
}
- if (do_swap32) {
- gph_size = omapimage_swap32(gph->size);
- gph_load_addr = omapimage_swap32(gph->load_addr);
- } else {
- gph_size = gph->size;
- gph_load_addr = gph->load_addr;
- }
-
- if (!valid_gph_size(gph_size)) {
- fprintf(stderr, "Error: invalid image size %x\n", gph_size);
- exit(EXIT_FAILURE);
- }
-
- if (!valid_gph_load_addr(gph_load_addr)) {
- fprintf(stderr, "Error: invalid image load address %x\n",
- gph_load_addr);
- exit(EXIT_FAILURE);
- }
-
- printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr);
+ gph_print_header(gph, do_swap32);
}
static int toc_offset(void *hdr, void *member)
toc++;
memset(toc, 0xff, sizeof(*toc));
- gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE;
- gph->load_addr = params->addr;
+ gph_set_header(gph, sbuf->st_size - OMAP_FILE_HDR_SIZE,
+ params->addr, 0);
if (strncmp(params->imagename, "byteswap", 8) == 0) {
do_swap32 = 1;
uint32_t *data = (uint32_t *)ptr;
while (swapped <= (sbuf->st_size / sizeof(uint32_t))) {
- *data = omapimage_swap32(*data);
+ *data = cpu_to_be32(*data);
swapped++;
data++;
}
}
}
-int omapimage_check_params(struct image_tool_params *params)
-{
- return (params->dflag && (params->fflag || params->lflag)) ||
- (params->fflag && (params->dflag || params->lflag)) ||
- (params->lflag && (params->dflag || params->fflag));
-}
-
/*
* omapimage parameters
*/
.verify_header = omapimage_verify_header,
.print_header = omapimage_print_header,
.set_header = omapimage_set_header,
- .check_params = omapimage_check_params,
+ .check_params = gpimage_check_params,
};
void init_omap_image_type(void)
uint32_t flags;
};
-struct gp_header {
- uint32_t size;
- uint32_t load_addr;
-};
-
#define KEY_CHSETTINGS 0xC0C0C0C1
#endif /* _OMAPIMAGE_H_ */
A sign-off is added automatically to your patches (this is
probably a bug). If you put this tag in your patches, it will
override the default signoff that patman automatically adds.
+ Multiple duplicate signoffs will be removed.
Tested-by: Their Name <email>
Reviewed-by: Their Name <email>
self.tags = []
self.changes = {}
self.cc_list = []
+ self.signoff_set = set()
self.notes = []
def AddChange(self, version, info):
cc_list: List of aliases or email addresses
"""
self.cc_list += cc_list
+
+ def CheckDuplicateSignoff(self, signoff):
+ """Check a list of signoffs we have send for this patch
+
+ Args:
+ signoff: Signoff line
+ Returns:
+ True if this signoff is new, False if we have already seen it.
+ """
+ if signoff in self.signoff_set:
+ return False
+ self.signoff_set.add(signoff)
+ return True
import sys
import terminal
+import checkpatch
import settings
Args:
fname: filename of patch file to apply
"""
+ col = terminal.Color()
cmd = ['git', 'am', fname]
pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE,
stderr=subprocess.PIPE)
print line
match = re_error.match(line)
if match:
- print GetWarningMsg('warning', match.group(1), int(match.group(2)),
- 'Patch failed')
+ print checkpatch.GetWarningMsg(col, 'warning', match.group(1),
+ int(match.group(2)), 'Patch failed')
return pipe.returncode == 0, stdout
def ApplyPatches(verbose, args, start_point):
re_allowed_after_test = re.compile('^Signed-off-by:')
# Signoffs
-re_signoff = re.compile('^Signed-off-by:')
+re_signoff = re.compile('^Signed-off-by: *(.*)')
# The start of the cover letter
re_cover = re.compile('^Cover-letter:')
commit_tag_match = re_commit_tag.match(line)
commit_match = re_commit.match(line) if self.is_log else None
cover_cc_match = re_cover_cc.match(line)
+ signoff_match = re_signoff.match(line)
tag_match = None
if self.state == STATE_PATCH_HEADER:
tag_match = re_tag.match(line)
if is_blank:
# Blank line ends this change list
self.in_change = 0
- elif line == '---' or re_signoff.match(line):
+ elif line == '---':
self.in_change = 0
out = self.ProcessLine(line)
else:
else:
self.tags.append(line);
+ # Suppress duplicate signoffs
+ elif signoff_match:
+ if (self.is_log or
+ self.commit.CheckDuplicateSignoff(signoff_match.group(1))):
+ out = [line]
+
# Well that means this is an ordinary line
else:
pos = 1
projects / karo-tx-uboot.git / commitdiff
