ddr: altera: sequencer: Wrap IO_* macros
authorMarek Vasut <marex@denx.de>
Sun, 2 Aug 2015 17:00:23 +0000 (19:00 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:17:37 +0000 (08:17 +0200)
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
arch/arm/mach-socfpga/include/mach/sdram.h
board/altera/socfpga/wrap_sdram_config.c
drivers/ddr/altera/sequencer.c

index eb40934..9d0e083 100644 (file)
@@ -17,6 +17,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
 
 #define SDR_CTRLGRP_ADDRESS    (SOCFPGA_SDR_ADDRESS | 0x5000)
 
@@ -180,6 +181,24 @@ struct socfpga_sdram_rw_mgr_config {
        u8      mem_virtual_groups_per_write_dqs;
 };
 
+struct socfpga_sdram_io_config {
+       u16     delay_per_opa_tap;
+       u8      delay_per_dchain_tap;
+       u8      delay_per_dqs_en_dchain_tap;
+       u8      dll_chain_length;
+       u8      dqdqs_out_phase_max;
+       u8      dqs_en_delay_max;
+       u8      dqs_en_delay_offset;
+       u8      dqs_en_phase_max;
+       u8      dqs_in_delay_max;
+       u8      dqs_in_reserve;
+       u8      dqs_out_reserve;
+       u8      io_in_delay_max;
+       u8      io_out1_delay_max;
+       u8      io_out2_delay_max;
+       u8      shift_dqs_en_when_shift_dqs;
+};
+
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
index 5fe1571..2697867 100644 (file)
@@ -249,6 +249,24 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
                RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
 };
 
+struct socfpga_sdram_io_config io_config = {
+       .delay_per_dchain_tap           = IO_DELAY_PER_DCHAIN_TAP,
+       .delay_per_dqs_en_dchain_tap    = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
+       .delay_per_opa_tap              = IO_DELAY_PER_OPA_TAP,
+       .dll_chain_length               = IO_DLL_CHAIN_LENGTH,
+       .dqdqs_out_phase_max            = IO_DQDQS_OUT_PHASE_MAX,
+       .dqs_en_delay_max               = IO_DQS_EN_DELAY_MAX,
+       .dqs_en_delay_offset            = IO_DQS_EN_DELAY_OFFSET,
+       .dqs_en_phase_max               = IO_DQS_EN_PHASE_MAX,
+       .dqs_in_delay_max               = IO_DQS_IN_DELAY_MAX,
+       .dqs_in_reserve                 = IO_DQS_IN_RESERVE,
+       .dqs_out_reserve                = IO_DQS_OUT_RESERVE,
+       .io_in_delay_max                = IO_IO_IN_DELAY_MAX,
+       .io_out1_delay_max              = IO_IO_OUT1_DELAY_MAX,
+       .io_out2_delay_max              = IO_IO_OUT2_DELAY_MAX,
+       .shift_dqs_en_when_shift_dqs    = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
+};
+
 const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
 {
        return &sdram_config;
@@ -270,3 +288,8 @@ const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
 {
        return &rw_mgr_config;
 }
+
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
+{
+       return &io_config;
+}
index 41af859..754eaa8 100644 (file)
@@ -42,6 +42,7 @@ static struct socfpga_sdr_ctrl *sdr_ctrl =
        (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
 const struct socfpga_sdram_rw_mgr_config *rwcfg;
+const struct socfpga_sdram_io_config *iocfg;
 
 #define DELTA_D                1
 
@@ -3699,6 +3700,7 @@ int sdram_calibration_full(void)
        gbl = &my_gbl;
 
        rwcfg = socfpga_get_sdram_rwmgr_config();
+       iocfg = socfpga_get_sdram_io_config();
 
        /* Set the calibration enabled by default */
        gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;