arm: socfpga: Add DW master SPI clock to clock_manager.c

This function will be needed by the upcoming Designware master SPI
driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index d869f47c88caab3aa3c06c48732f7f6cff5e646b..fa3b93a2572cb841c818337ecbceb4f34f7fd5fd 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
        return clock;
 }
 
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+       uint32_t reg, clock = 0;
+
+       clock = cm_get_per_vco_clk_hz();
+
+       /* get the clock prior L4 SP divider (periph_base_clk) */
+       reg = readl(&clock_manager_base->per_pll.perbaseclk);
+       clock /= (reg + 1);
+
+       return clock;
+}
+
 static void cm_print_clock_quick_summary(void)
 {
        printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
@@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void)
        printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
        printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
        printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+       printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
 }
 
 int set_cpu_clk_info(void)