Update MPC8544 DS PCI memory map

The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.

So make it use far less IO & memory space and have it use the shared LAW.  This
free's up a LAW for PCIe1 IO space.  Also reduce the amount of IO space needed
by each bus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index ea7d54dc302bb92e4a7eff57ecac204d4ce98484..900c3680c71dbb55bdda8a73acf66274123f17ee 100644 (file)
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -218,7 +218,7 @@ law_entry:
        .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
        .long   (CFG_PCI1_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+       .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
        .long   (CFG_LBC_CACHE_BASE>>12) & 0xfffff
        .long   LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
@@ -226,18 +226,17 @@ law_entry:
        .long   (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
        .long   LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
-       /* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region  */
+       .long   (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+       .long   LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
        .long   (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
        .long   LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
        .long   (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+       .long   LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
+       /* contains both PCIE3 MEM & IO space */
        .long   (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-       .long   (CFG_PCIE3_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
 4:
        entry_end

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index fcb92fac4b5a09c6a558e8d141c7f06bb725917b..746f360f9e19b0be609056957af6bb5ec74b807c 100644 (file)
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -282,7 +282,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
 #define CFG_PCI1_IO_BASE       0x00000000
 #define CFG_PCI1_IO_PHYS       0xe1000000
-#define CFG_PCI1_IO_SIZE       0x00100000      /* 1M */
+#define CFG_PCI1_IO_SIZE       0x00010000      /* 64k */
 
 /* PCI view of System Memory */
 #define CFG_PCI_MEMORY_BUS     0x00000000
@@ -294,26 +294,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCIE2_MEM_PHYS     CFG_PCIE2_MEM_BASE
 #define CFG_PCIE2_MEM_SIZE     0x20000000      /* 512M */
 #define CFG_PCIE2_IO_BASE      0x00000000
-#define CFG_PCIE2_IO_PHYS      0xe2000000
-#define CFG_PCIE2_IO_SIZE      0x00100000      /* 1M */
+#define CFG_PCIE2_IO_PHYS      0xe1010000
+#define CFG_PCIE2_IO_SIZE      0x00010000      /* 64k */
 
 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 #define CFG_PCIE1_MEM_BASE     0xa0000000
 #define CFG_PCIE1_MEM_PHYS     CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE     0x08000000      /* 128M */
-#define CFG_PCIE1_MEM_BASE2    0xa8000000
-#define CFG_PCIE1_MEM_PHYS2    CFG_PCIE1_MEM_BASE2
-#define CFG_PCIE1_MEM_SIZE2    0x04000000      /* 64M */
-#define CFG_PCIE1_IO_BASE      0x00000000      /* reuse mem LAW */
-#define CFG_PCIE1_IO_PHYS      0xaf000000
-#define CFG_PCIE1_IO_SIZE      0x00100000      /* 1M */
+#define CFG_PCIE1_MEM_SIZE     0x10000000      /* 256M */
+#define CFG_PCIE1_IO_BASE      0x00000000
+#define CFG_PCIE1_IO_PHYS      0xe1020000
+#define CFG_PCIE1_IO_SIZE      0x00010000      /* 64k */
 
 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 #define CFG_PCIE3_MEM_BASE     0xb0000000
 #define CFG_PCIE3_MEM_PHYS     CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE     0x10000000      /* 256M */
+#define CFG_PCIE3_MEM_SIZE     0x00100000      /* 1M */
 #define CFG_PCIE3_IO_BASE      0x00000000
-#define CFG_PCIE3_IO_PHYS      0xe3000000
+#define CFG_PCIE3_IO_PHYS      0xb0100000      /* reuse mem LAW */
 #define CFG_PCIE3_IO_SIZE      0x00100000      /* 1M */
 
 #if defined(CONFIG_PCI)