Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 30 Jun 2014 21:00:34 +0000 (23:00 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 30 Jun 2014 21:00:34 +0000 (23:00 +0200)
528 files changed:
.gitignore
Makefile
README
arch/.gitignore
arch/arc/include/asm/config.h
arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
arch/arm/cpu/arm926ejs/orion5x/cpu.c
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/cpu/armv7/at91/config.mk [new file with mode: 0644]
arch/arm/cpu/armv7/at91/cpu.c
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/lowlevel_init.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/exynos/power.c
arch/arm/cpu/armv7/exynos/spl_boot.c
arch/arm/cpu/armv7/keystone/init.c
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/omap-cache.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/omap3/mem.c
arch/arm/cpu/armv7/zynq/u-boot.lds
arch/arm/cpu/armv8/transition.S
arch/arm/cpu/at91-common/spl.c
arch/arm/dts/Makefile
arch/arm/dts/am335x-bone-common.dtsi [new file with mode: 0644]
arch/arm/dts/am335x-boneblack.dts [new file with mode: 0644]
arch/arm/dts/am33xx.dtsi [new file with mode: 0644]
arch/arm/dts/dt-bindings/gpio/gpio.h [new file with mode: 0644]
arch/arm/dts/dt-bindings/pinctrl/am33xx.h [new file with mode: 0644]
arch/arm/dts/dt-bindings/pinctrl/omap.h [new file with mode: 0644]
arch/arm/dts/exynos4.dtsi
arch/arm/dts/exynos4412-trats2.dts
arch/arm/dts/exynos5.dtsi
arch/arm/dts/exynos5250-snow.dts
arch/arm/dts/include/dt-bindings [new symlink]
arch/arm/dts/tegra114.dtsi
arch/arm/dts/tegra124-jetson-tk1.dts
arch/arm/dts/tegra124-venice2.dts
arch/arm/dts/tegra124.dtsi
arch/arm/dts/tegra20.dtsi
arch/arm/dts/tegra30-beaver.dts
arch/arm/dts/tegra30.dtsi
arch/arm/dts/tps65217.dtsi [new file with mode: 0644]
arch/arm/imx-common/Makefile
arch/arm/include/asm/arch-am33xx/clock.h
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-at91/at91_pmc.h
arch/arm/include/asm/arch-at91/at91sam9x5.h
arch/arm/include/asm/arch-at91/hardware.h
arch/arm/include/asm/arch-exynos/clk.h
arch/arm/include/asm/arch-exynos/power.h
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
arch/arm/include/asm/arch-keystone/hardware.h
arch/arm/include/asm/arch-omap3/mem.h
arch/arm/include/asm/arch-vf610/crm_regs.h
arch/arm/include/asm/arch-vf610/imx-regs.h
arch/arm/include/asm/arch-vf610/iomux-vf610.h
arch/arm/include/asm/atomic.h
arch/arm/include/asm/bitops.h
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/io.h
arch/arm/include/asm/proc-armv/processor.h
arch/arm/include/asm/processor.h
arch/arm/include/asm/ptrace.h
arch/arm/lib/board.c
arch/arm/lib/vectors.S
arch/avr32/cpu/cache.c
arch/avr32/include/asm/arch-at32ap700x/cacheflush.h
arch/avr32/include/asm/dma-mapping.h
arch/avr32/lib/board.c
arch/m68k/cpu/mcf532x/cpu_init.c
arch/m68k/cpu/mcf5445x/cpu_init.c
arch/m68k/include/asm/io.h
arch/m68k/include/asm/posix_types.h
arch/m68k/lib/board.c
arch/m68k/lib/bootm.c
arch/microblaze/dts/include/dt-bindings [new symlink]
arch/microblaze/lib/bootm.c
arch/openrisc/cpu/start.S
arch/openrisc/include/asm/spr-defs.h
arch/powerpc/cpu/mpc8260/pci.c
arch/powerpc/cpu/mpc8260/start.S
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
arch/powerpc/cpu/mpc85xx/t1040_ids.c
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
arch/powerpc/cpu/ppc4xx/cpu.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_law.h
arch/powerpc/include/asm/fsl_liodn.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/processor.h
arch/powerpc/lib/board.c
arch/sandbox/cpu/os.c
arch/sandbox/dts/include/dt-bindings [new symlink]
arch/sandbox/include/asm/bitops.h
arch/sandbox/include/asm/gpio.h
arch/sandbox/include/asm/io.h
arch/sandbox/include/asm/system.h
arch/x86/config.mk
arch/x86/cpu/config.mk
arch/x86/dts/include/dt-bindings [new symlink]
board/BuR/tseries/board.c
board/BuR/tseries/mux.c
board/Marvell/include/pci.h
board/abilis/tb100/Makefile [new file with mode: 0644]
board/abilis/tb100/tb100.c [new file with mode: 0644]
board/adder/Makefile [deleted file]
board/adder/adder.c [deleted file]
board/adder/u-boot.lds [deleted file]
board/ait/cam_enc_4xx/cam_enc_4xx.c
board/altera/common/sevenseg.c [deleted file]
board/altera/common/sevenseg.h [deleted file]
board/altera/nios2-generic/Makefile
board/amcc/yucca/cmd_yucca.c
board/astro/mcf5373l/fpga.c
board/astro/mcf5373l/mcf5373l.c
board/atmel/at91sam9261ek/at91sam9261ek.c
board/atmel/at91sam9263ek/at91sam9263ek.c
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/atmel/at91sam9rlek/at91sam9rlek.c
board/atmel/sama5d3_xplained/sama5d3_xplained.c
board/compulab/cm_t335/u-boot.lds
board/compulab/cm_t35/cm_t35.c
board/cray/L1/Makefile
board/eltec/elppc/misc.c
board/eltec/mhpc/mhpc.c
board/ep8248/Makefile [deleted file]
board/ep8248/ep8248.c [deleted file]
board/etin/debris/Makefile [deleted file]
board/etin/debris/debris.c [deleted file]
board/etin/debris/flash.c [deleted file]
board/etin/debris/phantom.c [deleted file]
board/etin/kvme080/Makefile [deleted file]
board/etin/kvme080/kvme080.c [deleted file]
board/etin/kvme080/multiverse.c [deleted file]
board/etin/kvme080/multiverse.h [deleted file]
board/freescale/b4860qds/b4860qds.c
board/freescale/m5253demo/flash.c
board/freescale/mpc8260ads/Makefile [deleted file]
board/freescale/mpc8260ads/flash.c [deleted file]
board/freescale/mpc8260ads/mpc8260ads.c [deleted file]
board/freescale/mx31ads/u-boot.lds
board/freescale/p1023rds/p1023rds.c
board/freescale/p1023rds/tlb.c
board/freescale/t208xqds/ddr.h
board/freescale/t208xqds/eth_t208xqds.c
board/freescale/t208xqds/t2080_rcw.cfg
board/freescale/t208xqds/t208xqds.c
board/freescale/t208xrdb/t2080_rcw.cfg
board/freescale/t4qds/eth.c
board/freescale/t4qds/t4240qds.c
board/freescale/t4qds/t4_rcw.cfg
board/freescale/t4rdb/eth.c
board/freescale/t4rdb/t4_rcw.cfg
board/freescale/vf610twr/vf610twr.c
board/gdsys/405ex/io64.c
board/gdsys/p1022/controlcenterd-id.c
board/gdsys/p1022/controlcenterd.c
board/hidden_dragon/Makefile [deleted file]
board/hidden_dragon/README [deleted file]
board/hidden_dragon/flash.c [deleted file]
board/hidden_dragon/hidden_dragon.c [deleted file]
board/hymod/hymod.c
board/hymod/input.c
board/ispan/Makefile [deleted file]
board/ispan/ispan.c [deleted file]
board/keymile/common/common.c
board/keymile/common/ivm.c
board/matrix_vision/mvblm7/Makefile
board/matrix_vision/mvsmr/Makefile
board/mcc200/auto_update.c
board/pcs440ep/pcs440ep.c
board/psyent/common/AMDLV065D.c
board/quad100hd/Makefile [deleted file]
board/quad100hd/nand.c [deleted file]
board/quad100hd/quad100hd.c [deleted file]
board/rattler/Makefile [deleted file]
board/rattler/rattler.c [deleted file]
board/ronetix/pm9261/pm9261.c
board/ronetix/pm9263/pm9263.c
board/samsung/common/board.c
board/samsung/goni/goni.c
board/samsung/smdk5250/Makefile
board/samsung/smdk5250/exynos5-dt.c
board/samsung/smdk5250/smdk5250.c [deleted file]
board/samsung/smdk5420/smdk5420.c
board/sheldon/simpc8313/Makefile [deleted file]
board/sheldon/simpc8313/README.simpc8313 [deleted file]
board/sheldon/simpc8313/sdram.c [deleted file]
board/sheldon/simpc8313/simpc8313.c [deleted file]
board/ti/am335x/u-boot.lds
board/ti/am43xx/Makefile
board/ti/am43xx/board.c
board/ttcontrol/vision2/imximage_hynix.cfg
board/zpc1900/Makefile [deleted file]
board/zpc1900/zpc1900.c [deleted file]
boards.cfg
common/Makefile
common/autoboot.c [new file with mode: 0644]
common/board_r.c
common/bootm.c [new file with mode: 0644]
common/bootm_os.c [new file with mode: 0644]
common/bootretry.c [new file with mode: 0644]
common/cli.c [new file with mode: 0644]
common/cli_hush.c [moved from common/hush.c with 99% similarity]
common/cli_readline.c [new file with mode: 0644]
common/cli_simple.c [new file with mode: 0644]
common/cmd_bedbug.c
common/cmd_bootm.c
common/cmd_bootmenu.c
common/cmd_dcr.c
common/cmd_demo.c
common/cmd_disk.c
common/cmd_fat.c
common/cmd_fdc.c
common/cmd_fdt.c
common/cmd_fpga.c
common/cmd_gpio.c
common/cmd_i2c.c
common/cmd_iotrace.c [new file with mode: 0644]
common/cmd_itest.c
common/cmd_md5sum.c
common/cmd_mem.c
common/cmd_mmc.c
common/cmd_nand.c
common/cmd_nvedit.c
common/cmd_pci.c
common/cmd_sandbox.c
common/cmd_sha1sum.c
common/cmd_source.c
common/cmd_ximg.c
common/env_eeprom.c
common/env_embedded.c
common/fdt_support.c
common/hash.c
common/image-fdt.c
common/image-fit.c
common/image-sig.c
common/image.c
common/iotrace.c [new file with mode: 0644]
common/main.c
common/menu.c
common/usb_hub.c
common/xyzModem.c
disk/part.c
disk/part_dos.c
disk/part_efi.c
doc/README.atmel_pmecc
doc/README.fdt-control
doc/README.nand
doc/README.scrapyard
doc/device-tree-bindings/exynos/dwmmc.txt
doc/device-tree-bindings/power/tps65090.txt [new file with mode: 0644]
doc/device-tree-bindings/regulator/tps65090.txt [new file with mode: 0644]
doc/driver-model/README.txt
doc/uImage.FIT/beaglebone_vboot.txt [new file with mode: 0644]
doc/uImage.FIT/howto.txt
doc/uImage.FIT/signature.txt
drivers/core/device.c
drivers/core/lists.c
drivers/core/root.c
drivers/core/uclass.c
drivers/crypto/ace_sha.c
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/interactive.c
drivers/demo/demo-shape.c
drivers/demo/demo-simple.c
drivers/demo/demo-uclass.c
drivers/dfu/dfu.c
drivers/fpga/altera.c
drivers/fpga/xilinx.c
drivers/gpio/at91_gpio.c
drivers/gpio/gpio-uclass.c
drivers/gpio/sandbox.c
drivers/i2c/kona_i2c.c
drivers/misc/cros_ec_sandbox.c
drivers/mmc/dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
drivers/mmc/gen_atmel_mci.c
drivers/mmc/kona_sdhci.c
drivers/mmc/mmc.c
drivers/mmc/rpmb.c
drivers/mmc/s5p_sdhci.c
drivers/mtd/nand/am335x_spl_bch.c
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_spl_simple.c
drivers/mtd/nand/omap_elm.c
drivers/mtd/nand/omap_gpmc.c
drivers/mtd/spi/sf_params.c
drivers/mtd/spi/sf_probe.c
drivers/net/macb.c
drivers/net/phy/phy.c
drivers/net/sh_eth.c
drivers/net/sh_eth.h
drivers/power/battery/bat_trats.c
drivers/power/battery/bat_trats2.c
drivers/power/mfd/pmic_max77693.c
drivers/power/pmic/Makefile
drivers/power/pmic/pmic_max8997.c
drivers/power/pmic/pmic_tps65090.c [new file with mode: 0644]
drivers/power/pmic/pmic_tps65218.c [new file with mode: 0644]
drivers/power/power_fsl.c
drivers/power/power_i2c.c
drivers/spi/Makefile
drivers/spi/fsl_espi.c
drivers/spi/fsl_qspi.c [new file with mode: 0644]
drivers/spi/fsl_qspi.h [new file with mode: 0644]
drivers/spi/soft_spi.c
drivers/spi/ti_qspi.c
drivers/usb/gadget/ci_udc.c
drivers/usb/gadget/ci_udc.h
drivers/video/atmel_hlcdfb.c
dts/Makefile
fs/ext4/ext4_common.c
fs/ext4/ext4_write.c
fs/fat/fat_write.c
fs/jffs2/jffs2_1pass.c
include/asm-generic/global_data.h
include/asm-generic/gpio.h
include/autoboot.h [new file with mode: 0644]
include/bootm.h [new file with mode: 0644]
include/bootretry.h [new file with mode: 0644]
include/cli.h [new file with mode: 0644]
include/cli_hush.h [moved from include/hush.h with 93% similarity]
include/command.h
include/common.h
include/config_fallbacks.h
include/configs/Adder.h [deleted file]
include/configs/HIDDEN_DRAGON.h [deleted file]
include/configs/ISPAN.h [deleted file]
include/configs/MPC8260ADS.h [deleted file]
include/configs/MPC8315ERDB.h
include/configs/MPC8536DS.h
include/configs/MPC8569MDS.h
include/configs/MPC8572DS.h
include/configs/P1023RDS.h
include/configs/Rattler.h [deleted file]
include/configs/SIMPC8313.h [deleted file]
include/configs/T1040QDS.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/ZPC1900.h [deleted file]
include/configs/am335x_evm.h
include/configs/am3517_crane.h
include/configs/am43xx_evm.h
include/configs/arndale.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9n12ek.h
include/configs/at91sam9x5ek.h
include/configs/atngw100mkii.h
include/configs/bcm28155_ap.h
include/configs/beaver.h
include/configs/bur_am335x_common.h
include/configs/cm_t335.h
include/configs/cm_t35.h
include/configs/corvus.h
include/configs/cpu9260.h
include/configs/debris.h [deleted file]
include/configs/devkit8000.h
include/configs/dig297.h
include/configs/ep8248.h [deleted file]
include/configs/ethernut5.h
include/configs/exynos4-dt.h
include/configs/exynos5-dt.h
include/configs/exynos5250-dt.h
include/configs/gw_ventana.h
include/configs/ids8313.h
include/configs/iocon.h
include/configs/jetson-tk1.h
include/configs/k2hk_evm.h
include/configs/kvme080.h [deleted file]
include/configs/mx25pdk.h
include/configs/mx35pdk.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/omap3_beagle.h
include/configs/omap3_evm_common.h
include/configs/omap3_igep00x0.h
include/configs/omap3_logic.h
include/configs/omap3_overo.h
include/configs/omap3_zoom1.h
include/configs/pengwyn.h
include/configs/quad100hd.h [deleted file]
include/configs/s5p_goni.h
include/configs/sama5d3_xplained.h
include/configs/sama5d3xek.h
include/configs/sandbox.h
include/configs/tam3517-common.h
include/configs/tao3530.h
include/configs/tb100.h [new file with mode: 0644]
include/configs/tegra-common-ums.h [new file with mode: 0644]
include/configs/tegra-common.h
include/configs/ti_am335x_common.h
include/configs/ti_armv7_common.h
include/configs/tseries.h
include/configs/venice2.h
include/configs/vf610twr.h
include/configs/vl_ma2sc.h
include/configs/woodburn_common.h
include/configs/zynq-common.h
include/dm-demo.h
include/dm.h
include/dm/device-internal.h
include/dm/device.h
include/dm/lists.h
include/dm/root.h
include/dm/test.h
include/dm/uclass-internal.h
include/dm/uclass.h
include/dt-bindings/gpio/gpio.h [new file with mode: 0644]
include/dt-bindings/gpio/tegra-gpio.h [new file with mode: 0644]
include/dt-bindings/interrupt-controller/arm-gic.h [new file with mode: 0644]
include/dt-bindings/interrupt-controller/irq.h [new file with mode: 0644]
include/dwmmc.h
include/fat.h
include/fdt_support.h
include/fdtdec.h
include/hash.h
include/image.h
include/initcall.h
include/iotrace.h [new file with mode: 0644]
include/linux/mtd/nand.h
include/linux/mtd/omap_elm.h
include/linux/mtd/omap_gpmc.h
include/mmc.h
include/mpc8260.h
include/part.h
include/power/max77693_pmic.h
include/power/max8997_pmic.h
include/power/pmic.h
include/power/tps65090_pmic.h [new file with mode: 0644]
include/power/tps65218.h [new file with mode: 0644]
include/tps6586x.h
include/u-boot/rsa-checksum.h [moved from include/rsa-checksum.h with 91% similarity]
include/u-boot/rsa.h [moved from include/rsa.h with 96% similarity]
include/u-boot/sha1.h [moved from include/sha1.h with 100% similarity]
include/u-boot/sha256.h [moved from include/sha256.h with 100% similarity]
lib/Makefile
lib/fdtdec.c
lib/fdtdec_common.c [new file with mode: 0644]
lib/initcall.c
lib/libfdt/fdt_ro.c
lib/lzma/LzmaTools.c
lib/rsa/rsa-checksum.c
lib/rsa/rsa-sign.c
lib/rsa/rsa-verify.c
lib/sha1.c
lib/sha256.c
lib/tpm.c
mkconfig
nand_spl/board/freescale/mpc8315erdb/Makefile [deleted file]
nand_spl/board/freescale/mpc8315erdb/u-boot.lds [deleted file]
nand_spl/board/freescale/mpc8536ds/Makefile [deleted file]
nand_spl/board/freescale/mpc8536ds/nand_boot.c [deleted file]
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nand_spl/board/freescale/mpc8572ds/nand_boot.c [deleted file]
nand_spl/board/freescale/p1023rds/Makefile [deleted file]
nand_spl/board/freescale/p1023rds/nand_boot.c [deleted file]
nand_spl/board/sheldon/simpc8313/Makefile [deleted file]
nand_spl/board/sheldon/simpc8313/config.mk [deleted file]
nand_spl/board/sheldon/simpc8313/u-boot.lds [deleted file]
nand_spl/nand_boot.c [deleted file]
nand_spl/nand_boot_fsl_elbc.c [deleted file]
net/net.c
scripts/Makefile.build
scripts/Makefile.host
scripts/Makefile.lib
scripts/Makefile.spl [moved from spl/Makefile with 96% similarity]
scripts/basic/fixdep.c
scripts/docproc.c
test/command_ut.c
test/dm/Makefile
test/dm/cmd_dm.c
test/dm/core.c
test/dm/gpio.c
test/dm/test-driver.c
test/dm/test-fdt.c
test/dm/test-main.c
test/dm/test-uclass.c
test/vboot/vboot_test.sh
tools/.gitignore
tools/Makefile
tools/atmel_pmecc_params.c [new file with mode: 0644]
tools/atmelimage.c [new file with mode: 0644]
tools/crc32.c [deleted file]
tools/dumpimage.h
tools/env_embedded.c [deleted file]
tools/fdt.c [deleted file]
tools/fdt_ro.c [deleted file]
tools/fdt_rw.c [deleted file]
tools/fdt_strerror.c [deleted file]
tools/fdt_wip.c [deleted file]
tools/fdtdec.c [deleted file]
tools/fit_check_sign.c
tools/fit_common.c
tools/fit_common.h
tools/fit_image.c
tools/fit_info.c
tools/image-fit.c [deleted file]
tools/image-host.c
tools/image-sig.c [deleted file]
tools/image.c [deleted file]
tools/imagetool.c
tools/imagetool.h
tools/md5.c [deleted file]
tools/mkimage.h
tools/mxsimage.c
tools/pbl_crc32.c [new file with mode: 0644]
tools/pbl_crc32.h [new file with mode: 0644]
tools/pblimage.c
tools/rsa-checksum.c [deleted file]
tools/rsa-sign.c [deleted file]
tools/rsa-verify.c [deleted file]
tools/sha1.c [deleted file]
tools/sha256.c [deleted file]
tools/ubsha1.c

index a6b2d1c..2ddf57f 100644 (file)
@@ -20,7 +20,9 @@
 *.bin
 *.patch
 *.cfgtmp
-*.dts.tmp
+
+# host programs on Cygwin
+*.exe
 
 # Build tree
 /build-*
@@ -47,8 +49,7 @@
 /errlog
 /reloc_off
 
-/spl/*
-!/spl/Makefile
+/spl/
 /tpl/
 
 #
index 966fd14..e429212 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
 VERSION = 2014
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -209,11 +209,6 @@ HOSTCXX      = g++
 HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
 HOSTCXXFLAGS = -O2
 
-ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1)
-HOSTCFLAGS  += -Wno-unused-value -Wno-unused-parameter \
-               -Wno-missing-field-initializers -fno-delete-null-pointer-checks
-endif
-
 ifeq ($(HOSTOS),cygwin)
 HOSTCFLAGS     += -ansi
 endif
@@ -249,18 +244,18 @@ endif
 KBUILD_MODULES :=
 KBUILD_BUILTIN := 1
 
-#      If we have only "make modules", don't compile built-in objects.
-#      When we're building modules with modversions, we need to consider
-#      the built-in objects during the descend as well, in order to
-#      make sure the checksums are up to date before we record them.
+# If we have only "make modules", don't compile built-in objects.
+# When we're building modules with modversions, we need to consider
+# the built-in objects during the descend as well, in order to
+# make sure the checksums are up to date before we record them.
 
 ifeq ($(MAKECMDGOALS),modules)
   KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1)
 endif
 
-#      If we have "make <whatever> modules", compile modules
-#      in addition to whatever we do anyway.
-#      Just "make" or "make all" shall build modules as well
+# If we have "make <whatever> modules", compile modules
+# in addition to whatever we do anyway.
+# Just "make" or "make all" shall build modules as well
 
 # U-Boot does not need modules
 #ifneq ($(filter all _all modules,$(MAKECMDGOALS)),)
@@ -320,15 +315,6 @@ endif
 
 export quiet Q KBUILD_VERBOSE
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -354,7 +340,7 @@ STRIP               = $(CROSS_COMPILE)strip
 OBJCOPY                = $(CROSS_COMPILE)objcopy
 OBJDUMP                = $(CROSS_COMPILE)objdump
 AWK            = awk
-RANLIB         = $(CROSS_COMPILE)RANLIB
+PERL           = perl
 DTC            = dtc
 CHECK          = sparse
 
@@ -376,8 +362,8 @@ export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
 export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
-export MAKE AWK
-export DTC CHECK CHECKFLAGS
+export MAKE AWK PERL
+export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
 export KBUILD_CFLAGS KBUILD_AFLAGS
@@ -515,12 +501,6 @@ endif
 
 # If there is no specified link script, we look in a number of places for it
 ifndef LDSCRIPT
-       ifeq ($(CONFIG_NAND_U_BOOT),y)
-               LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
-               ifeq ($(wildcard $(LDSCRIPT)),)
-                       LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
-               endif
-       endif
        ifeq ($(wildcard $(LDSCRIPT)),)
                LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
        endif
@@ -545,20 +525,6 @@ endif
 
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
 
-ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
-KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
-KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
-KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
-KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
-# Quiet clang warning: comparison of unsigned expression < 0 is always false
-KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
-# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
-# source of a reference will be _MergedGlobals and not on of the whitelisted names.
-# See modpost pattern 2
-KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
-endif
-
 KBUILD_CFLAGS  += -g
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
 # option to the assembler.
@@ -740,9 +706,8 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin System.map
+ALL-y += u-boot.srec u-boot.bin System.map binary_size_check
 
-ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
 ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
@@ -820,6 +785,18 @@ u-boot.hex u-boot.srec: u-boot FORCE
 
 OBJCOPYFLAGS_u-boot.bin := -O binary
 
+binary_size_check: u-boot.bin System.map FORCE
+       @file_size=`stat -c %s u-boot.bin` ; \
+       map_size=$(shell cat System.map | \
+               awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print strtonum("0x" end) - strtonum("0x" start)}'); \
+       if [ "" != "$$map_size" ]; then \
+               if test $$map_size -ne $$file_size; then \
+                       echo "System.map shows a binary size of $$map_size" >&2 ; \
+                       echo "  but u-boot.bin shows $$file_size" >&2 ; \
+                       exit 1; \
+               fi \
+       fi
+
 u-boot.bin: u-boot FORCE
        $(call if_changed,objcopy)
        $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
@@ -1148,33 +1125,16 @@ cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
 u-boot.lds: $(LDSCRIPT) prepare FORCE
        $(call if_changed_dep,cpp_lds)
 
-PHONY += nand_spl
-nand_spl: prepare
-       $(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
-       @echo >&2
-       @echo >&2 "==================== WARNING ====================="
-       @echo >&2 "nand_spl will not be included in v2014.07 release."
-       @echo >&2 "Please switch over to SPL."
-       @echo >&2 "Otherwise, this board will be removed."
-       @echo >&2 "=================================================="
-       @echo >&2
-
-nand_spl/u-boot-spl-16k.bin: nand_spl
-       @:
-
-u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE
-       $(call if_changed,cat)
-
 spl/u-boot-spl.bin: spl/u-boot-spl
        @:
 spl/u-boot-spl: tools prepare
-       $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
+       $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
 
 spl/sunxi-spl.bin: spl/u-boot-spl
        @:
 
 tpl/u-boot-tpl.bin: tools prepare
-       $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
+       $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
 
 TAG_SUBDIRS := $(u-boot-dirs) include
 
@@ -1254,14 +1214,12 @@ CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
               include/tpl-autoconf.mk
 
 # Directories & files removed with 'make clobber'
-CLOBBER_DIRS  += $(patsubst %,spl/%, $(filter-out Makefile, \
-                $(shell ls -1 spl 2>/dev/null))) \
-                tpl
-CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
+CLOBBER_DIRS  += spl tpl
+CLOBBER_FILES += u-boot* MLO* SPL System.map
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated          \
-                  .tmp_objdiff
+                 .tmp_objdiff
 MRPROPER_FILES += .config .config.old \
                  tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
                  include/config.h include/config.mk
@@ -1290,8 +1248,6 @@ clean: $(clean-dirs)
                -o -name '*.symtypes' -o -name 'modules.order' \
                -o -name modules.builtin -o -name '.tmp_*.o.*' \
                -o -name '*.gcno' \) -type f -print | xargs rm -f
-       @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
-               -path './nand_spl/*' -type l -print | xargs rm -f
 
 # clobber
 #
diff --git a/README b/README
index a280435..fe5cacb 100644 (file)
--- a/README
+++ b/README
@@ -321,14 +321,6 @@ The following options need to be configured:
                                          the LCD display every second with
                                          a "rotator" |\-/|\-/
 
-- Board flavour: (if CONFIG_MPC8260ADS is defined)
-               CONFIG_ADSTYPE
-               Possible values are:
-                       CONFIG_SYS_8260ADS      - original MPC8260ADS
-                       CONFIG_SYS_8266ADS      - MPC8266ADS
-                       CONFIG_SYS_PQ2FADS      - PQ2FADS-ZU or PQ2FADS-VR
-                       CONFIG_SYS_8272ADS      - MPC8272ADS
-
 - Marvell Family Member
                CONFIG_SYS_MVFS         - define it if you want to enable
                                          multiple fs option at one time
@@ -1008,6 +1000,7 @@ The following options need to be configured:
                CONFIG_CMD_IMLS           List all images found in NOR flash
                CONFIG_CMD_IMLS_NAND    * List all images found in NAND flash
                CONFIG_CMD_IMMAP        * IMMR dump support
+               CONFIG_CMD_IOTRACE      * I/O tracing for debugging
                CONFIG_CMD_IMPORTENV    * import an environment
                CONFIG_CMD_INI          * import data from an ini file into the env
                CONFIG_CMD_IRQ          * irqinfo
@@ -1179,6 +1172,28 @@ The following options need to be configured:
                Note that if the GPIO device uses I2C, then the I2C interface
                must also be configured. See I2C Support, below.
 
+- I/O tracing:
+               When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
+               accesses and can checksum them or write a list of them out
+               to memory. See the 'iotrace' command for details. This is
+               useful for testing device drivers since it can confirm that
+               the driver behaves the same way before and after a code
+               change. Currently this is supported on sandbox and arm. To
+               add support for your architecture, add '#include <iotrace.h>'
+               to the bottom of arch/<arch>/include/asm/io.h and test.
+
+               Example output from the 'iotrace stats' command is below.
+               Note that if the trace buffer is exhausted, the checksum will
+               still continue to operate.
+
+                       iotrace is enabled
+                       Start:  10000000        (buffer start address)
+                       Size:   00010000        (buffer size)
+                       Offset: 00000120        (current buffer offset)
+                       Output: 10000120        (start + offset)
+                       Count:  00000018        (number of trace records)
+                       CRC32:  9526fb66        (CRC32 of all trace records)
+
 - Timestamp Support:
 
                When CONFIG_TIMESTAMP is selected, the timestamp
@@ -1432,9 +1447,6 @@ The following options need to be configured:
                CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
                txfilltuning field in the EHCI controller on reset.
 
-               CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
-               interval for usb hub power-on delay.(minimum 100msec)
-
 - USB Device:
                Define the below if you wish to use the USB console.
                Once firmware is rebuilt from a serial console issue the
@@ -1645,6 +1657,12 @@ CBFS (Coreboot Filesystem) support
                filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
                and cbfsload.
 
+- FAT(File Allocation Table) filesystem cluster size:
+               CONFIG_FS_FAT_MAX_CLUSTSIZE
+
+               Define the max cluster size for fat operations else
+               a default value of 65536 will be defined.
+
 - Keyboard Support:
                CONFIG_ISA_KEYBOARD
 
@@ -3202,6 +3220,19 @@ FIT uImage format:
  -150  common/cmd_nand.c       Incorrect FIT image format
   151  common/cmd_nand.c       FIT image format OK
 
+- legacy image format:
+               CONFIG_IMAGE_FORMAT_LEGACY
+               enables the legacy image format support in U-Boot.
+
+               Default:
+               enabled if CONFIG_FIT_SIGNATURE is not defined.
+
+               CONFIG_DISABLE_IMAGE_LEGACY
+               disable the legacy image format
+
+               This define is introduced, as the legacy image format is
+               enabled per default for backward compatibility.
+
 - FIT image support:
                CONFIG_FIT
                Enable support for the FIT uImage format.
@@ -3218,6 +3249,11 @@ FIT uImage format:
                using a hash signed and verified using RSA. See
                doc/uImage.FIT/signature.txt for more details.
 
+               WARNING: When relying on signed FIT images with required
+               signature check the legacy image format is default
+               disabled. If a board need legacy image format support
+               enable this through CONFIG_IMAGE_FORMAT_LEGACY
+
 - Standalone program support:
                CONFIG_STANDALONE_LOAD_ADDR
 
@@ -5295,6 +5331,11 @@ Information structure as we define in include/asm-<arch>/u-boot.h,
 and make sure that your definition of IMAP_ADDR uses the same value
 as your U-Boot configuration in CONFIG_SYS_IMMR.
 
+Note that U-Boot now has a driver model, a unified model for drivers.
+If you are adding a new driver, plumb it into driver model. If there
+is no uclass available, you are encouraged to create one. See
+doc/driver-model.
+
 
 Configuring the Linux kernel:
 -----------------------------
index a1fbe01..2714b86 100644 (file)
@@ -1,2 +1 @@
 /*/include/asm/arch
-/*/include/asm/proc
index 3d331cc..e5be078 100644 (file)
@@ -8,6 +8,7 @@
 #define __ASM_ARC_CONFIG_H_
 
 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
 #define CONFIG_LMB
 
index 7d7725c..0e6c0da 100644 (file)
@@ -165,3 +165,20 @@ void at91_macb_hw_init(void)
 #endif
 }
 #endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 0, 0);        /* MCI0 CLK */
+       at91_set_a_periph(AT91_PIO_PORTA, 1, 0);        /* MCI0 CDA */
+       at91_set_a_periph(AT91_PIO_PORTA, 2, 0);        /* MCI0 DA0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 3, 0);        /* MCI0 DA1 */
+       at91_set_a_periph(AT91_PIO_PORTA, 4, 0);        /* MCI0 DA2 */
+       at91_set_a_periph(AT91_PIO_PORTA, 5, 0);        /* MCI0 DA3 */
+
+       /* Enable clock */
+       writel(1 << ATMEL_ID_MCI0, &pmc->pcer);
+}
+#endif
index d4711c0..da80240 100644 (file)
@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
-#include <hush.h>
 
 #define BUFLEN 16
 
@@ -211,7 +210,7 @@ static void kw_sysrst_action(void)
 
        debug("Starting %s process...\n", __FUNCTION__);
        ret = run_command(s, 0);
-       if (ret < 0)
+       if (ret != 0)
                debug("Error.. %s failed\n", __FUNCTION__);
        else
                debug("%s process finished\n", __FUNCTION__);
index b55c5f0..f88db3b 100644 (file)
@@ -15,7 +15,6 @@
 #include <asm/io.h>
 #include <u-boot/md5.h>
 #include <asm/arch/cpu.h>
-#include <hush.h>
 
 #define BUFLEN 16
 
index 28c16f8..828d10b 100644 (file)
@@ -143,6 +143,19 @@ int arch_misc_init(void)
 }
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * In the case of non-SPL based booting we'll want to call these
+ * functions a tiny bit later as it will require gd to be set and cleared
+ * and that's not true in s_init in this case so we cannot do it there.
+ */
+int board_early_init_f(void)
+{
+       prcm_init();
+       set_mux_conf_regs();
+
+       return 0;
+}
+
 /*
  * This function is the place to do per-board things such as ramp up the
  * MPU clock frequency.
@@ -224,7 +237,7 @@ void s_init(void)
        set_uart_mux_conf();
        setup_clocks_for_console();
        uart_soft_reset();
-#ifdef CONFIG_NOR_BOOT
+#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
        gd->baudrate = CONFIG_BAUDRATE;
        serial_init();
        gd->have_console = 1;
@@ -232,20 +245,13 @@ void s_init(void)
        gd = &gdata;
        preloader_console_init();
 #endif
-       prcm_init();
-       set_mux_conf_regs();
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
        /* Enable RTC32K clock */
        rtc32k_enable();
 #endif
+#ifdef CONFIG_SPL_BUILD
+       board_early_init_f();
        sdram_init();
-}
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-       /* Enable D-cache. I-cache is already enabled in start.S */
-       dcache_enable();
 }
-#endif /* !CONFIG_SYS_DCACHE_OFF */
+#endif
index 0672798..ec7d468 100644 (file)
@@ -170,8 +170,19 @@ void do_enable_clocks(u32 *const *clk_domains,
        };
 }
 
+/*
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first.  This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
+ */
+__weak void scale_vcores(void)
+{
+}
+
 void prcm_init()
 {
        enable_basic_clocks();
+       scale_vcores();
        setup_dplls();
 }
index d0bc234..31188c8 100644 (file)
@@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
 
 void setup_clocks_for_console(void)
 {
+       u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
        /* Do not add any spl_debug prints in this function */
        clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
                        CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
                        MODULE_CLKCTRL_MODULEMODE_MASK,
                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+       while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+               (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+               clkctrl = readl(&cmwkup->wkup_uart0ctrl);
+               idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+                        MODULE_CLKCTRL_IDLEST_SHIFT;
+       }
 }
 
 void enable_basic_clocks(void)
index 2c67c32..a7a3e88 100644 (file)
@@ -21,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+       sdram_init();
+#endif
+
        /* dram_init must store complete ramsize in gd->ram_size */
        gd->ram_size = get_ram_size(
                        (void *)CONFIG_SYS_SDRAM_BASE,
diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk
new file mode 100644 (file)
index 0000000..09eab70
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2014, Andreas BieƟmann <andreas.devel@googlemail.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y  += boot.bin
+else
+ALL-y  += u-boot.img
+endif
index 2fbf60d..8d86f97 100644 (file)
@@ -61,6 +61,8 @@ int print_cpuinfo(void)
 
 void enable_caches(void)
 {
+       icache_enable();
+       dcache_enable();
 }
 
 unsigned int get_chip_id(void)
index 1fea4d6..400d134 100644 (file)
@@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
        struct exynos4_clock *clk =
                (struct exynos4_clock *)samsung_get_base_clock();
-       unsigned int addr;
+       unsigned int addr, clear_bit, set_bit;
 
        /*
         * CLK_DIV_FSYS1
@@ -877,44 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
         * CLK_DIV_FSYS2
         * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
         * CLK_DIV_FSYS3
-        * MMC4_PRE_RATIO [15:8]
+        * MMC4_RATIO [3:0]
         */
        if (dev_index < 2) {
                addr = (unsigned int)&clk->div_fsys1;
-       }  else if (dev_index == 4) {
+               clear_bit = MASK_PRE_RATIO(dev_index);
+               set_bit = SET_PRE_RATIO(dev_index, div);
+       } else if (dev_index == 4) {
                addr = (unsigned int)&clk->div_fsys3;
                dev_index -= 4;
+               /* MMC4 is controlled with the MMC4_RATIO value */
+               clear_bit = MASK_RATIO(dev_index);
+               set_bit = SET_RATIO(dev_index, div);
        } else {
                addr = (unsigned int)&clk->div_fsys2;
                dev_index -= 2;
+               clear_bit = MASK_PRE_RATIO(dev_index);
+               set_bit = SET_PRE_RATIO(dev_index, div);
        }
 
-       clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
-                       (div & 0xff) << ((dev_index << 4) + 8));
-}
-
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
-       struct exynos4x12_clock *clk =
-               (struct exynos4x12_clock *)samsung_get_base_clock();
-       unsigned int addr;
-
-       /*
-        * CLK_DIV_FSYS1
-        * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
-        * CLK_DIV_FSYS2
-        * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
-        */
-       if (dev_index < 2) {
-               addr = (unsigned int)&clk->div_fsys1;
-       } else {
-               addr = (unsigned int)&clk->div_fsys2;
-               dev_index -= 2;
-       }
-
-       clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
-                       (div & 0xff) << ((dev_index << 4) + 8));
+       clrsetbits_le32(addr, clear_bit, set_bit);
 }
 
 /* exynos5: set the mmc clock */
@@ -1612,10 +1594,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
                else
                        exynos5_set_mmc_clk(dev_index, div);
        } else {
-               if (proid_is_exynos4412())
-                       exynos4x12_set_mmc_clk(dev_index, div);
-               else
-                       exynos4_set_mmc_clk(dev_index, div);
+               exynos4_set_mmc_clk(dev_index, div);
        }
 }
 
index 11fe5b8..dcc270f 100644 (file)
@@ -39,6 +39,7 @@ enum {
        DO_CLOCKS       = 1 << 1,
        DO_MEM_RESET    = 1 << 2,
        DO_UART         = 1 << 3,
+       DO_POWER        = 1 << 4,
 };
 
 int do_lowlevel_init(void)
@@ -48,6 +49,8 @@ int do_lowlevel_init(void)
 
        arch_cpu_init();
 
+       set_ps_hold_ctrl();
+
        reset_status = get_reset_status();
 
        switch (reset_status) {
@@ -60,9 +63,12 @@ int do_lowlevel_init(void)
                break;
        default:
                /* This is a normal boot (not a wake from sleep) */
-               actions = DO_CLOCKS | DO_MEM_RESET;
+               actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
        }
 
+       if (actions & DO_POWER)
+               set_ps_hold_ctrl();
+
        if (actions & DO_CLOCKS) {
                system_clock_init();
                mem_ctrl_init(actions & DO_MEM_RESET);
index ee7c2e5..86a0c75 100644 (file)
@@ -573,15 +573,26 @@ static void exynos4_i2c_config(int peripheral, int flags)
 static int exynos4_mmc_config(int peripheral, int flags)
 {
        int i, start = 0, start_ext = 0;
+       unsigned int func, ext_func;
 
        switch (peripheral) {
        case PERIPH_ID_SDMMC0:
                start = EXYNOS4_GPIO_K00;
                start_ext = EXYNOS4_GPIO_K13;
+               func = S5P_GPIO_FUNC(0x2);
+               ext_func = S5P_GPIO_FUNC(0x3);
                break;
        case PERIPH_ID_SDMMC2:
                start = EXYNOS4_GPIO_K20;
                start_ext = EXYNOS4_GPIO_K33;
+               func = S5P_GPIO_FUNC(0x2);
+               ext_func = S5P_GPIO_FUNC(0x3);
+               break;
+       case PERIPH_ID_SDMMC4:
+               start = EXYNOS4_GPIO_K00;
+               start_ext = EXYNOS4_GPIO_K13;
+               func = S5P_GPIO_FUNC(0x3);
+               ext_func = S5P_GPIO_FUNC(0x4);
                break;
        default:
                return -1;
@@ -589,13 +600,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
        for (i = start; i < (start + 7); i++) {
                if (i == (start + 2))
                        continue;
-               gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x2));
+               gpio_cfg_pin(i,  func);
                gpio_set_pull(i, S5P_GPIO_PULL_NONE);
                gpio_set_drv(i, S5P_GPIO_DRV_4X);
        }
+       /* SDMMC2 do not use 8bit mode at exynos4 */
        if (flags & PINMUX_FLAG_8BIT_MODE) {
                for (i = start_ext; i < (start_ext + 4); i++) {
-                       gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x3));
+                       gpio_cfg_pin(i,  ext_func);
                        gpio_set_pull(i, S5P_GPIO_PULL_NONE);
                        gpio_set_drv(i, S5P_GPIO_DRV_4X);
                }
@@ -676,15 +688,26 @@ static void exynos4x12_i2c_config(int peripheral, int flags)
 static int exynos4x12_mmc_config(int peripheral, int flags)
 {
        int i, start = 0, start_ext = 0;
+       unsigned int func, ext_func;
 
        switch (peripheral) {
        case PERIPH_ID_SDMMC0:
                start = EXYNOS4X12_GPIO_K00;
                start_ext = EXYNOS4X12_GPIO_K13;
+               func = S5P_GPIO_FUNC(0x2);
+               ext_func = S5P_GPIO_FUNC(0x3);
                break;
        case PERIPH_ID_SDMMC2:
                start = EXYNOS4X12_GPIO_K20;
                start_ext = EXYNOS4X12_GPIO_K33;
+               func = S5P_GPIO_FUNC(0x2);
+               ext_func = S5P_GPIO_FUNC(0x3);
+               break;
+       case PERIPH_ID_SDMMC4:
+               start = EXYNOS4_GPIO_K00;
+               start_ext = EXYNOS4_GPIO_K13;
+               func = S5P_GPIO_FUNC(0x3);
+               ext_func = S5P_GPIO_FUNC(0x4);
                break;
        default:
                return -1;
@@ -692,13 +715,13 @@ static int exynos4x12_mmc_config(int peripheral, int flags)
        for (i = start; i < (start + 7); i++) {
                if (i == (start + 2))
                        continue;
-               gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x2));
+               gpio_cfg_pin(i,  func);
                gpio_set_pull(i, S5P_GPIO_PULL_NONE);
                gpio_set_drv(i, S5P_GPIO_DRV_4X);
        }
        if (flags & PINMUX_FLAG_8BIT_MODE) {
                for (i = start_ext; i < (start_ext + 4); i++) {
-                       gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x3));
+                       gpio_cfg_pin(i,  ext_func);
                        gpio_set_pull(i, S5P_GPIO_PULL_NONE);
                        gpio_set_drv(i, S5P_GPIO_DRV_4X);
                }
@@ -759,10 +782,10 @@ static int exynos4_pinmux_config(int peripheral, int flags)
                break;
        case PERIPH_ID_SDMMC0:
        case PERIPH_ID_SDMMC2:
+       case PERIPH_ID_SDMMC4:
                return exynos4_mmc_config(peripheral, flags);
        case PERIPH_ID_SDMMC1:
        case PERIPH_ID_SDMMC3:
-       case PERIPH_ID_SDMMC4:
                debug("SDMMC device %d not implemented\n", peripheral);
                return -1;
        default:
@@ -794,10 +817,10 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
                break;
        case PERIPH_ID_SDMMC0:
        case PERIPH_ID_SDMMC2:
+       case PERIPH_ID_SDMMC4:
                return exynos4x12_mmc_config(peripheral, flags);
        case PERIPH_ID_SDMMC1:
        case PERIPH_ID_SDMMC3:
-       case PERIPH_ID_SDMMC4:
                debug("SDMMC device %d not implemented\n", peripheral);
                return -1;
        default:
index 563abd7..638ee0b 100644 (file)
@@ -112,6 +112,12 @@ static void exynos5_set_ps_hold_ctrl(void)
                        EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
 }
 
+/*
+ * Set ps_hold data driving value high
+ * This enables the machine to stay powered on
+ * after the initial power-on condition goes away
+ * (e.g. power button).
+ */
 void set_ps_hold_ctrl(void)
 {
        if (cpu_is_exynos5())
index ade45fd..7916630 100644 (file)
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include<common.h>
-#include<config.h>
+#include <common.h>
+#include <config.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
index 044015a..4df5ae1 100644 (file)
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <ns16550.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
@@ -30,6 +31,14 @@ int arch_cpu_init(void)
        share_all_segments(11); /* PCIE */
 #endif
 
+       /*
+        * just initialise the COM2 port so that TI specific
+        * UART register PWREMU_MGMT is initialized. Linux UART
+        * driver doesn't handle this.
+        */
+       NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
+                    CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
        return 0;
 }
 
index 5f5132f..7695e16 100644 (file)
@@ -22,6 +22,10 @@ obj-y        += pipe3-phy.o
 obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 
+ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+obj-y  += omap-cache.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y  += boot-common.o
 obj-y  += lowlevel_init.o
index ba97d9e..5f50a19 100644 (file)
 #include <asm/emif.h>
 #include <asm/omap_common.h>
 #include <linux/compiler.h>
-#include <asm/cache.h>
 #include <asm/system.h>
 
-#define ARMV7_DCACHE_WRITEBACK  0xe
-#define        ARMV7_DOMAIN_CLIENT     1
-#define ARMV7_DOMAIN_MASK      (0x3 << 0)
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -263,40 +258,3 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-       /* Enable D-cache. I-cache is already enabled in start.S */
-       dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
-       bd_t *bd = gd->bd;
-       int     i;
-
-       u32 start = bd->bi_dram[bank].start >> 20;
-       u32 size = bd->bi_dram[bank].size >> 20;
-       u32 end = start + size;
-
-       debug("%s: bank: %d\n", __func__, bank);
-       for (i = start; i < end; i++)
-               set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-
-}
-
-void arm_init_domains(void)
-{
-       u32 reg;
-
-       reg = get_dacr();
-       /*
-       * Set DOMAIN to client access so that all permissions
-       * set in pagetables are validated by the mmu.
-       */
-       reg &= ~ARMV7_DOMAIN_MASK;
-       reg |= ARMV7_DOMAIN_CLIENT;
-       set_dacr(reg);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c
new file mode 100644 (file)
index 0000000..579bebf
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Aneesh V        <aneesh@ti.com>
+ *     Steve Sakoman   <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARMV7_DCACHE_WRITEBACK  0xe
+#define ARMV7_DOMAIN_CLIENT    1
+#define ARMV7_DOMAIN_MASK      (0x3 << 0)
+
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+       bd_t *bd = gd->bd;
+       int     i;
+
+       u32 start = bd->bi_dram[bank].start >> 20;
+       u32 size = bd->bi_dram[bank].size >> 20;
+       u32 end = start + size;
+
+       debug("%s: bank: %d\n", __func__, bank);
+       for (i = start; i < end; i++)
+               set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+}
+
+void arm_init_domains(void)
+{
+       u32 reg;
+
+       reg = get_dacr();
+       /*
+       * Set DOMAIN to client access so that all permissions
+       * set in pagetables are validated by the mmu.
+       */
+       reg &= ~ARMV7_DOMAIN_MASK;
+       reg |= ARMV7_DOMAIN_CLIENT;
+       set_dacr(reg);
+}
index 9bb1a1c..e252e7f 100644 (file)
@@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void)
        omap3_update_aux_cr(0, 0x2);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-       /* Enable D-cache. I-cache is already enabled in start.S */
-       dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */
index e649409..1832aff 100644 (file)
 struct gpmc *gpmc_cfg;
 
 #if defined(CONFIG_CMD_NAND)
-#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-       SMNAND_GPMC_CONFIG1,
-       SMNAND_GPMC_CONFIG2,
-       SMNAND_GPMC_CONFIG3,
-       SMNAND_GPMC_CONFIG4,
-       SMNAND_GPMC_CONFIG5,
-       SMNAND_GPMC_CONFIG6,
-       0,
-};
-#else
 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
        M_NAND_GPMC_CONFIG1,
        M_NAND_GPMC_CONFIG2,
@@ -40,7 +29,6 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
        M_NAND_GPMC_CONFIG5,
        M_NAND_GPMC_CONFIG6, 0
 };
-#endif
 #endif /* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_CMD_ONENAND)
index 69500a6..4dc9bb0 100644 (file)
@@ -18,6 +18,7 @@ SECTIONS
        .text :
        {
                *(.__image_copy_start)
+               *(.vectors)
                CPUDIR/start.o (.text*)
                *(.text*)
        }
index e0a5946..38dea5c 100644 (file)
@@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1)
        mrs     x0, cnthctl_el2
        orr     x0, x0, #0x3            /* Enable EL1 access to timers */
        msr     cnthctl_el2, x0
-       msr     cntvoff_el2, x0
+       msr     cntvoff_el2, xzr
        mrs     x0, cntkctl_el1
        orr     x0, x0, #0x3            /* Enable EL0 access to timers */
        msr     cntkctl_el1, x0
index 7f4debb..cbb5a52 100644 (file)
@@ -20,6 +20,43 @@ static void at91_disable_wdt(void)
        writel(AT91_WDT_MR_WDDIS, &wdt->mr);
 }
 
+static void switch_to_main_crystal_osc(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       u32 tmp;
+
+       tmp = readl(&pmc->mor);
+       tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff);
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_MOSCEN;
+       tmp |= AT91_PMC_MOR_OSCOUNT(8);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+       while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS))
+               ;
+
+       tmp = readl(&pmc->mor);
+       tmp &= ~AT91_PMC_MOR_OSCBYPASS;
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+
+       tmp = readl(&pmc->mor);
+       tmp |= AT91_PMC_MOR_MOSCSEL;
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+
+       while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS))
+               ;
+
+       tmp = readl(&pmc->mor);
+       tmp &= ~AT91_PMC_MOR_MOSCRCEN;
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+}
+
 void at91_plla_init(u32 pllar)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -76,6 +113,8 @@ u32 spl_boot_mode(void)
 
 void s_init(void)
 {
+       switch_to_main_crystal_osc();
+
        /* disable watchdog */
        at91_disable_wdt();
 
index 5554615..61527a2 100644 (file)
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
        zynq-zc770-xm010.dtb \
        zynq-zc770-xm012.dtb \
        zynq-zc770-xm013.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
new file mode 100644 (file)
index 0000000..2f66ded
--- /dev/null
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+       model = "TI AM335x BeagleBone";
+       compatible = "ti,am335x-bone", "ti,am33xx";
+
+       cpus {
+               cpu@0 {
+                       cpu0-supply = <&dcdc2_reg>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>; /* 256 MB */
+       };
+
+       am33xx_pinmux: pinmux@44e10800 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&clkout2_pin>;
+
+               user_leds_s0: user_leds_s0 {
+                       pinctrl-single,pins = <
+                               0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                               0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
+                               0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
+                               0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a8.gpio1_24 */
+                       >;
+               };
+
+               i2c0_pins: pinmux_i2c0_pins {
+                       pinctrl-single,pins = <
+                               0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                               0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                       >;
+               };
+
+               uart0_pins: pinmux_uart0_pins {
+                       pinctrl-single,pins = <
+                               0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                               0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                       >;
+               };
+
+               clkout2_pin: pinmux_clkout2_pin {
+                       pinctrl-single,pins = <
+                               0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                       >;
+               };
+
+               cpsw_default: cpsw_default {
+                       pinctrl-single,pins = <
+                               /* Slave 1 */
+                               0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
+                               0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+                               0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
+                               0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+                               0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+                               0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+                               0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+                               0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
+                               0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
+                               0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
+                               0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
+                               0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
+                               0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */
+                       >;
+               };
+
+               cpsw_sleep: cpsw_sleep {
+                       pinctrl-single,pins = <
+                               /* Slave 1 reset value */
+                               0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       >;
+               };
+
+               davinci_mdio_default: davinci_mdio_default {
+                       pinctrl-single,pins = <
+                               /* MDIO */
+                               0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                               0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                       >;
+               };
+
+               davinci_mdio_sleep: davinci_mdio_sleep {
+                       pinctrl-single,pins = <
+                               /* MDIO reset value */
+                               0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                               0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       >;
+               };
+       };
+
+       ocp {
+               uart0: serial@44e09000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart0_pins>;
+
+                       status = "okay";
+               };
+
+               musb: usb@47400000 {
+                       status = "okay";
+
+                       control@44e10000 {
+                               status = "okay";
+                       };
+
+                       usb-phy@47401300 {
+                               status = "okay";
+                       };
+
+                       usb-phy@47401b00 {
+                               status = "okay";
+                       };
+
+                       usb@47401000 {
+                               status = "okay";
+                       };
+
+                       usb@47401800 {
+                               status = "okay";
+                               dr_mode = "host";
+                       };
+
+                       dma-controller@07402000  {
+                               status = "okay";
+                       };
+               };
+
+               i2c0: i2c@44e0b000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c0_pins>;
+
+                       status = "okay";
+                       clock-frequency = <400000>;
+
+                       tps: tps@24 {
+                               reg = <0x24>;
+                       };
+
+               };
+       };
+
+       leds {
+               pinctrl-names = "default";
+               pinctrl-0 = <&user_leds_s0>;
+
+               compatible = "gpio-leds";
+
+               led@2 {
+                       label = "beaglebone:green:heartbeat";
+                       gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+                       default-state = "off";
+               };
+
+               led@3 {
+                       label = "beaglebone:green:mmc0";
+                       gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "mmc0";
+                       default-state = "off";
+               };
+
+               led@4 {
+                       label = "beaglebone:green:usr2";
+                       gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               led@5 {
+                       label = "beaglebone:green:usr3";
+                       gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+       };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+       regulators {
+               dcdc1_reg: regulator@0 {
+                       regulator-always-on;
+               };
+
+               dcdc2_reg: regulator@1 {
+                       /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                       regulator-name = "vdd_mpu";
+                       regulator-min-microvolt = <925000>;
+                       regulator-max-microvolt = <1325000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               dcdc3_reg: regulator@2 {
+                       /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                       regulator-name = "vdd_core";
+                       regulator-min-microvolt = <925000>;
+                       regulator-max-microvolt = <1150000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               ldo1_reg: regulator@3 {
+                       regulator-always-on;
+               };
+
+               ldo2_reg: regulator@4 {
+                       regulator-always-on;
+               };
+
+               ldo3_reg: regulator@5 {
+                       regulator-always-on;
+               };
+
+               ldo4_reg: regulator@6 {
+                       regulator-always-on;
+               };
+       };
+};
+
+&cpsw_emac0 {
+       phy_id = <&davinci_mdio>, <0>;
+       phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+       phy_id = <&davinci_mdio>, <1>;
+       phy-mode = "mii";
+};
+
+&mac {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&cpsw_default>;
+       pinctrl-1 = <&cpsw_sleep>;
+
+};
+
+&davinci_mdio {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&davinci_mdio_default>;
+       pinctrl-1 = <&davinci_mdio_sleep>;
+};
diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts
new file mode 100644 (file)
index 0000000..197cadf
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+&ldo3_reg {
+       regulator-min-microvolt = <1800000>;
+       regulator-max-microvolt = <1800000>;
+       regulator-always-on;
+};
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
new file mode 100644 (file)
index 0000000..f9c5da9
--- /dev/null
@@ -0,0 +1,649 @@
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "ti,am33xx";
+       interrupt-parent = <&intc>;
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;
+               serial5 = &uart5;
+               d_can0 = &dcan0;
+               d_can1 = &dcan1;
+               usb0 = &usb0;
+               usb1 = &usb1;
+               phy0 = &usb0_phy;
+               phy1 = &usb1_phy;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu@0 {
+                       compatible = "arm,cortex-a8";
+                       device_type = "cpu";
+                       reg = <0>;
+
+                       /*
+                        * To consider voltage drop between PMIC and SoC,
+                        * tolerance value is reduced to 2% from 4% and
+                        * voltage value is increased as a precaution.
+                        */
+                       operating-points = <
+                               /* kHz    uV */
+                               720000  1285000
+                               600000  1225000
+                               500000  1125000
+                               275000  1125000
+                       >;
+                       voltage-tolerance = <2>; /* 2 percentage */
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
+               };
+       };
+
+       /*
+        * The soc node represents the soc top level view. It is uses for IPs
+        * that are not memory mapped in the MPU view or for the MPU itself.
+        */
+       soc {
+               compatible = "ti,omap-infra";
+               mpu {
+                       compatible = "ti,omap3-mpu";
+                       ti,hwmods = "mpu";
+               };
+       };
+
+       am33xx_pinmux: pinmux@44e10800 {
+               compatible = "pinctrl-single";
+               reg = <0x44e10800 0x0238>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x7f>;
+       };
+
+       /*
+        * XXX: Use a flat representation of the AM33XX interconnect.
+        * The real AM33XX interconnect network is quite complex.Since
+        * that will not bring real advantage to represent that in DT
+        * for the moment, just use a fake OCP bus entry to represent
+        * the whole bus hierarchy.
+        */
+       ocp {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               ti,hwmods = "l3_main";
+
+               intc: interrupt-controller@48200000 {
+                       compatible = "ti,omap2-intc";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       ti,intc-size = <128>;
+                       reg = <0x48200000 0x1000>;
+               };
+
+               gpio0: gpio@44e07000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio1";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x44e07000 0x1000>;
+                       interrupts = <96>;
+               };
+
+               gpio1: gpio@4804c000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio2";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x4804c000 0x1000>;
+                       interrupts = <98>;
+               };
+
+               gpio2: gpio@481ac000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio3";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x481ac000 0x1000>;
+                       interrupts = <32>;
+               };
+
+               gpio3: gpio@481ae000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio4";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x481ae000 0x1000>;
+                       interrupts = <62>;
+               };
+
+               uart0: serial@44e09000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart1";
+                       clock-frequency = <48000000>;
+                       reg = <0x44e09000 0x2000>;
+                       interrupts = <72>;
+                       status = "disabled";
+               };
+
+               uart1: serial@48022000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart2";
+                       clock-frequency = <48000000>;
+                       reg = <0x48022000 0x2000>;
+                       interrupts = <73>;
+                       status = "disabled";
+               };
+
+               uart2: serial@48024000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart3";
+                       clock-frequency = <48000000>;
+                       reg = <0x48024000 0x2000>;
+                       interrupts = <74>;
+                       status = "disabled";
+               };
+
+               uart3: serial@481a6000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart4";
+                       clock-frequency = <48000000>;
+                       reg = <0x481a6000 0x2000>;
+                       interrupts = <44>;
+                       status = "disabled";
+               };
+
+               uart4: serial@481a8000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart5";
+                       clock-frequency = <48000000>;
+                       reg = <0x481a8000 0x2000>;
+                       interrupts = <45>;
+                       status = "disabled";
+               };
+
+               uart5: serial@481aa000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart6";
+                       clock-frequency = <48000000>;
+                       reg = <0x481aa000 0x2000>;
+                       interrupts = <46>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@44e0b000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c1";
+                       reg = <0x44e0b000 0x1000>;
+                       interrupts = <70>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@4802a000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c2";
+                       reg = <0x4802a000 0x1000>;
+                       interrupts = <71>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@4819c000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c3";
+                       reg = <0x4819c000 0x1000>;
+                       interrupts = <30>;
+                       status = "disabled";
+               };
+
+               wdt2: wdt@44e35000 {
+                       compatible = "ti,omap3-wdt";
+                       ti,hwmods = "wd_timer2";
+                       reg = <0x44e35000 0x1000>;
+                       interrupts = <91>;
+               };
+
+               dcan0: d_can@481cc000 {
+                       compatible = "bosch,d_can";
+                       ti,hwmods = "d_can0";
+                       reg = <0x481cc000 0x2000
+                               0x44e10644 0x4>;
+                       interrupts = <52>;
+                       status = "disabled";
+               };
+
+               dcan1: d_can@481d0000 {
+                       compatible = "bosch,d_can";
+                       ti,hwmods = "d_can1";
+                       reg = <0x481d0000 0x2000
+                               0x44e10644 0x4>;
+                       interrupts = <55>;
+                       status = "disabled";
+               };
+
+               timer1: timer@44e31000 {
+                       compatible = "ti,am335x-timer-1ms";
+                       reg = <0x44e31000 0x400>;
+                       interrupts = <67>;
+                       ti,hwmods = "timer1";
+                       ti,timer-alwon;
+               };
+
+               timer2: timer@48040000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48040000 0x400>;
+                       interrupts = <68>;
+                       ti,hwmods = "timer2";
+               };
+
+               timer3: timer@48042000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48042000 0x400>;
+                       interrupts = <69>;
+                       ti,hwmods = "timer3";
+               };
+
+               timer4: timer@48044000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48044000 0x400>;
+                       interrupts = <92>;
+                       ti,hwmods = "timer4";
+                       ti,timer-pwm;
+               };
+
+               timer5: timer@48046000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48046000 0x400>;
+                       interrupts = <93>;
+                       ti,hwmods = "timer5";
+                       ti,timer-pwm;
+               };
+
+               timer6: timer@48048000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x48048000 0x400>;
+                       interrupts = <94>;
+                       ti,hwmods = "timer6";
+                       ti,timer-pwm;
+               };
+
+               timer7: timer@4804a000 {
+                       compatible = "ti,am335x-timer";
+                       reg = <0x4804a000 0x400>;
+                       interrupts = <95>;
+                       ti,hwmods = "timer7";
+                       ti,timer-pwm;
+               };
+
+               rtc@44e3e000 {
+                       compatible = "ti,da830-rtc";
+                       reg = <0x44e3e000 0x1000>;
+                       interrupts = <75
+                                     76>;
+                       ti,hwmods = "rtc";
+               };
+
+               spi0: spi@48030000 {
+                       compatible = "ti,omap4-mcspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x48030000 0x400>;
+                       interrupts = <65>;
+                       ti,spi-num-cs = <2>;
+                       ti,hwmods = "spi0";
+                       status = "disabled";
+               };
+
+               spi1: spi@481a0000 {
+                       compatible = "ti,omap4-mcspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x481a0000 0x400>;
+                       interrupts = <125>;
+                       ti,spi-num-cs = <2>;
+                       ti,hwmods = "spi1";
+                       status = "disabled";
+               };
+
+               usb: usb@47400000 {
+                       compatible = "ti,am33xx-usb";
+                       reg = <0x47400000 0x1000>;
+                       ranges;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ti,hwmods = "usb_otg_hs";
+                       status = "disabled";
+
+                       ctrl_mod: control@44e10000 {
+                               compatible = "ti,am335x-usb-ctrl-module";
+                               reg = <0x44e10620 0x10
+                                       0x44e10648 0x4>;
+                               reg-names = "phy_ctrl", "wakeup";
+                               status = "disabled";
+                       };
+
+                       usb0_phy: usb-phy@47401300 {
+                               compatible = "ti,am335x-usb-phy";
+                               reg = <0x47401300 0x100>;
+                               reg-names = "phy";
+                               status = "disabled";
+                               ti,ctrl_mod = <&ctrl_mod>;
+                       };
+
+                       usb0: usb@47401000 {
+                               compatible = "ti,musb-am33xx";
+                               status = "disabled";
+                               reg = <0x47401400 0x400
+                                       0x47401000 0x200>;
+                               reg-names = "mc", "control";
+
+                               interrupts = <18>;
+                               interrupt-names = "mc";
+                               dr_mode = "otg";
+                               mentor,multipoint = <1>;
+                               mentor,num-eps = <16>;
+                               mentor,ram-bits = <12>;
+                               mentor,power = <500>;
+                               phys = <&usb0_phy>;
+
+                               dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+                                       &cppi41dma  2 0 &cppi41dma  3 0
+                                       &cppi41dma  4 0 &cppi41dma  5 0
+                                       &cppi41dma  6 0 &cppi41dma  7 0
+                                       &cppi41dma  8 0 &cppi41dma  9 0
+                                       &cppi41dma 10 0 &cppi41dma 11 0
+                                       &cppi41dma 12 0 &cppi41dma 13 0
+                                       &cppi41dma 14 0 &cppi41dma  0 1
+                                       &cppi41dma  1 1 &cppi41dma  2 1
+                                       &cppi41dma  3 1 &cppi41dma  4 1
+                                       &cppi41dma  5 1 &cppi41dma  6 1
+                                       &cppi41dma  7 1 &cppi41dma  8 1
+                                       &cppi41dma  9 1 &cppi41dma 10 1
+                                       &cppi41dma 11 1 &cppi41dma 12 1
+                                       &cppi41dma 13 1 &cppi41dma 14 1>;
+                               dma-names =
+                                       "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                       "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                       "rx14", "rx15",
+                                       "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                       "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                       "tx14", "tx15";
+                       };
+
+                       usb1_phy: usb-phy@47401b00 {
+                               compatible = "ti,am335x-usb-phy";
+                               reg = <0x47401b00 0x100>;
+                               reg-names = "phy";
+                               status = "disabled";
+                               ti,ctrl_mod = <&ctrl_mod>;
+                       };
+
+                       usb1: usb@47401800 {
+                               compatible = "ti,musb-am33xx";
+                               status = "disabled";
+                               reg = <0x47401c00 0x400
+                                       0x47401800 0x200>;
+                               reg-names = "mc", "control";
+                               interrupts = <19>;
+                               interrupt-names = "mc";
+                               dr_mode = "otg";
+                               mentor,multipoint = <1>;
+                               mentor,num-eps = <16>;
+                               mentor,ram-bits = <12>;
+                               mentor,power = <500>;
+                               phys = <&usb1_phy>;
+
+                               dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+                                       &cppi41dma 17 0 &cppi41dma 18 0
+                                       &cppi41dma 19 0 &cppi41dma 20 0
+                                       &cppi41dma 21 0 &cppi41dma 22 0
+                                       &cppi41dma 23 0 &cppi41dma 24 0
+                                       &cppi41dma 25 0 &cppi41dma 26 0
+                                       &cppi41dma 27 0 &cppi41dma 28 0
+                                       &cppi41dma 29 0 &cppi41dma 15 1
+                                       &cppi41dma 16 1 &cppi41dma 17 1
+                                       &cppi41dma 18 1 &cppi41dma 19 1
+                                       &cppi41dma 20 1 &cppi41dma 21 1
+                                       &cppi41dma 22 1 &cppi41dma 23 1
+                                       &cppi41dma 24 1 &cppi41dma 25 1
+                                       &cppi41dma 26 1 &cppi41dma 27 1
+                                       &cppi41dma 28 1 &cppi41dma 29 1>;
+                               dma-names =
+                                       "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                       "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                       "rx14", "rx15",
+                                       "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                       "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                       "tx14", "tx15";
+                       };
+
+                       cppi41dma: dma-controller@07402000 {
+                               compatible = "ti,am3359-cppi41";
+                               reg =  <0x47400000 0x1000
+                                       0x47402000 0x1000
+                                       0x47403000 0x1000
+                                       0x47404000 0x4000>;
+                               reg-names = "glue", "controller", "scheduler", "queuemgr";
+                               interrupts = <17>;
+                               interrupt-names = "glue";
+                               #dma-cells = <2>;
+                               #dma-channels = <30>;
+                               #dma-requests = <256>;
+                               status = "disabled";
+                       };
+               };
+
+               epwmss0: epwmss@48300000 {
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48300000 0x10>;
+                       ti,hwmods = "epwmss0";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+                       ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+                                 0x48300180 0x48300180 0x80   /* EQEP */
+                                 0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+                       ecap0: ecap@48300100 {
+                               compatible = "ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48300100 0x80>;
+                               ti,hwmods = "ecap0";
+                               status = "disabled";
+                       };
+
+                       ehrpwm0: ehrpwm@48300200 {
+                               compatible = "ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48300200 0x80>;
+                               ti,hwmods = "ehrpwm0";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss1: epwmss@48302000 {
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48302000 0x10>;
+                       ti,hwmods = "epwmss1";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+                       ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+                                 0x48302180 0x48302180 0x80   /* EQEP */
+                                 0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+                       ecap1: ecap@48302100 {
+                               compatible = "ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48302100 0x80>;
+                               ti,hwmods = "ecap1";
+                               status = "disabled";
+                       };
+
+                       ehrpwm1: ehrpwm@48302200 {
+                               compatible = "ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48302200 0x80>;
+                               ti,hwmods = "ehrpwm1";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss2: epwmss@48304000 {
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48304000 0x10>;
+                       ti,hwmods = "epwmss2";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+                       ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+                                 0x48304180 0x48304180 0x80   /* EQEP */
+                                 0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+                       ecap2: ecap@48304100 {
+                               compatible = "ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48304100 0x80>;
+                               ti,hwmods = "ecap2";
+                               status = "disabled";
+                       };
+
+                       ehrpwm2: ehrpwm@48304200 {
+                               compatible = "ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48304200 0x80>;
+                               ti,hwmods = "ehrpwm2";
+                               status = "disabled";
+                       };
+               };
+
+               mac: ethernet@4a100000 {
+                       compatible = "ti,cpsw";
+                       ti,hwmods = "cpgmac0";
+                       cpdma_channels = <8>;
+                       ale_entries = <1024>;
+                       bd_ram_size = <0x2000>;
+                       no_bd_ram = <0>;
+                       rx_descs = <64>;
+                       mac_control = <0x20>;
+                       slaves = <2>;
+                       active_slave = <0>;
+                       cpts_clock_mult = <0x80000000>;
+                       cpts_clock_shift = <29>;
+                       reg = <0x4a100000 0x800
+                              0x4a101200 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       interrupt-parent = <&intc>;
+                       /*
+                        * c0_rx_thresh_pend
+                        * c0_rx_pend
+                        * c0_tx_pend
+                        * c0_misc_pend
+                        */
+                       interrupts = <40 41 42 43>;
+                       ranges;
+
+                       davinci_mdio: mdio@4a101000 {
+                               compatible = "ti,davinci_mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               ti,hwmods = "davinci_mdio";
+                               bus_freq = <1000000>;
+                               reg = <0x4a101000 0x100>;
+                       };
+
+                       cpsw_emac0: slave@4a100200 {
+                               /* Filled in by U-Boot */
+                               mac-address = [ 00 00 00 00 00 00 ];
+                       };
+
+                       cpsw_emac1: slave@4a100300 {
+                               /* Filled in by U-Boot */
+                               mac-address = [ 00 00 00 00 00 00 ];
+                       };
+               };
+
+               ocmcram: ocmcram@40300000 {
+                       compatible = "ti,am3352-ocmcram";
+                       reg = <0x40300000 0x10000>;
+                       ti,hwmods = "ocmcram";
+               };
+
+               wkup_m3: wkup_m3@44d00000 {
+                       compatible = "ti,am3353-wkup-m3";
+                       reg = <0x44d00000 0x4000        /* M3 UMEM */
+                              0x44d80000 0x2000>;      /* M3 DMEM */
+                       ti,hwmods = "wkup_m3";
+               };
+
+               elm: elm@48080000 {
+                       compatible = "ti,am3352-elm";
+                       reg = <0x48080000 0x2000>;
+                       interrupts = <4>;
+                       ti,hwmods = "elm";
+                       status = "disabled";
+               };
+
+               tscadc: tscadc@44e0d000 {
+                       compatible = "ti,am3359-tscadc";
+                       reg = <0x44e0d000 0x1000>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <16>;
+                       ti,hwmods = "adc_tsc";
+                       status = "disabled";
+
+                       tsc {
+                               compatible = "ti,am3359-tsc";
+                       };
+                       am335x_adc: adc {
+                               #io-channel-cells = <1>;
+                               compatible = "ti,am3359-adc";
+                       };
+               };
+
+               gpmc: gpmc@50000000 {
+                       compatible = "ti,am3352-gpmc";
+                       ti,hwmods = "gpmc";
+                       reg = <0x50000000 0x2000>;
+                       interrupts = <100>;
+                       gpmc,num-cs = <7>;
+                       gpmc,num-waitpins = <2>;
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+                       status = "disabled";
+               };
+       };
+};
diff --git a/arch/arm/dts/dt-bindings/gpio/gpio.h b/arch/arm/dts/dt-bindings/gpio/gpio.h
new file mode 100644 (file)
index 0000000..e6b1e0a
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#endif
diff --git a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h b/arch/arm/dts/dt-bindings/pinctrl/am33xx.h
new file mode 100644 (file)
index 0000000..2fbc804
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
+#define _DT_BINDINGS_PINCTRL_AM33XX_H
+
+#include <dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef PULL_ENA
+#undef INPUT_EN
+
+#define PULL_DISABLE           (1 << 3)
+#define INPUT_EN               (1 << 5)
+#define SLEWCTRL_FAST          (1 << 6)
+
+/* update macro depending on INPUT_EN and PULL_ENA */
+#undef PIN_OUTPUT
+#undef PIN_OUTPUT_PULLUP
+#undef PIN_OUTPUT_PULLDOWN
+#undef PIN_INPUT
+#undef PIN_INPUT_PULLUP
+#undef PIN_INPUT_PULLDOWN
+
+#define PIN_OUTPUT             (PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP      (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN    0
+#define PIN_INPUT              (INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP       (INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN     (INPUT_EN)
+
+/* undef non-existing modes */
+#undef PIN_OFF_NONE
+#undef PIN_OFF_OUTPUT_HIGH
+#undef PIN_OFF_OUTPUT_LOW
+#undef PIN_OFF_INPUT_PULLUP
+#undef PIN_OFF_INPUT_PULLDOWN
+#undef PIN_OFF_WAKEUPENABLE
+
+#endif
+
diff --git a/arch/arm/dts/dt-bindings/pinctrl/omap.h b/arch/arm/dts/dt-bindings/pinctrl/omap.h
new file mode 100644 (file)
index 0000000..edbd250
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
+#define _DT_BINDINGS_PINCTRL_OMAP_H
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0      0
+#define MUX_MODE1      1
+#define MUX_MODE2      2
+#define MUX_MODE3      3
+#define MUX_MODE4      4
+#define MUX_MODE5      5
+#define MUX_MODE6      6
+#define MUX_MODE7      7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA               (1 << 3)
+#define PULL_UP                        (1 << 4)
+#define ALTELECTRICALSEL       (1 << 5)
+
+/* 34xx specific mux bit defines */
+#define INPUT_EN               (1 << 8)
+#define OFF_EN                 (1 << 9)
+#define OFFOUT_EN              (1 << 10)
+#define OFFOUT_VAL             (1 << 11)
+#define OFF_PULL_EN            (1 << 12)
+#define OFF_PULL_UP            (1 << 13)
+#define WAKEUP_EN              (1 << 14)
+
+/* 44xx specific mux bit defines */
+#define WAKEUP_EVENT           (1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT             0
+#define PIN_OUTPUT_PULLUP      (PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN    (PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT              INPUT_EN
+#define PIN_INPUT_PULLUP       (PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN     (PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE           0
+#define PIN_OFF_OUTPUT_HIGH    (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW     (OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP   (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE   WAKEUP_EN
+
+#endif
+
index 71dc7eb..110eb43 100644 (file)
                interrupts = <0 78 0>;
        };
 
+       dwmmc@12550000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos-dwmmc";
+               reg = <0x12550000 0x1000>;
+               interrupts = <0 131 0>;
+       };
+
        gpio: gpio {
                gpio-controller;
                #gpio-cells = <2>;
index 1596f83..cc58c87 100644 (file)
@@ -31,6 +31,7 @@
                console = "/serial@13820000";
                mmc0 = "sdhci@12510000";
                mmc2 = "sdhci@12530000";
+               mmc4 = "dwmmc@12550000";
        };
 
        i2c@138d0000 {
                samsung,bus-width = <8>;
                samsung,timing = <1 3 3>;
                pwr-gpios = <&gpio 0xB2 0>;
+               status = "disabled";
        };
 
        sdhci@12520000 {
        sdhci@12540000 {
                status = "disabled";
        };
+
+       dwmmc@12550000 {
+               samsung,bus-width = <8>;
+               samsung,timing = <2 1 0>;
+               pwr-gpios = <&gpio 0xB2 0>;
+               fifoth_val = <0x203f0040>;
+               bus_hz = <400000000>;
+               div = <0x3>;
+               index = <4>;
+       };
 };
index f8c8741..a2b533a 100644 (file)
        mmc@12200000 {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "samsung,exynos5250-dwmmc";
+               compatible = "samsung,exynos-dwmmc";
                reg = <0x12200000 0x1000>;
                interrupts = <0 75 0>;
        };
        mmc@12210000 {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "samsung,exynos5250-dwmmc";
+               compatible = "samsung,exynos-dwmmc";
                reg = <0x12210000 0x1000>;
                interrupts = <0 76 0>;
        };
        mmc@12220000 {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "samsung,exynos5250-dwmmc";
+               compatible = "samsung,exynos-dwmmc";
                reg = <0x12220000 0x1000>;
                interrupts = <0 77 0>;
        };
        mmc@12230000 {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "samsung,exynos5250-dwmmc";
+               compatible = "samsung,exynos-dwmmc";
                reg = <0x12230000 0x1000>;
                interrupts = <0 78 0>;
        };
index 9b48a0c..ab4f2f8 100644 (file)
@@ -44,7 +44,7 @@
                        reg = <0x1e>;
                        compatible = "google,cros-ec";
                        i2c-max-frequency = <100000>;
-                       ec-interrupt = <&gpio 782 1>;
+                       ec-interrupt = <&gpio 182 1>;
                };
 
                power-regulator@48 {
@@ -60,7 +60,7 @@
                        reg = <0>;
                        compatible = "google,cros-ec";
                        spi-max-frequency = <5000000>;
-                       ec-interrupt = <&gpio 782 1>;
+                       ec-interrupt = <&gpio 182 1>;
                        optimise-flash-write;
                        status = "disabled";
                };
                        reg = <0x22>;
                        compatible = "maxim,max98095-codec";
                };
+
+               ptn3460-bridge@20 {
+                       compatible = "nxp,ptn3460";
+                       reg = <0x20>;
+                       /*
+                        * TODO(sjg@chromium.org): Use GPIOs here
+                        * powerdown-gpio = <&gpy2 5 0>;
+                        * reset-gpio = <&gpx1 5 0>;
+                        * edid-emulation = <5>;
+                        * pinctrl-names = "default";
+                        * pinctrl-0 = <&ptn3460_gpios>;
+                        */
+               };
        };
 
        i2c@12c60000 {
                        /* UP      LEFT    */
                        0x070b0067 0x070c0069>;
        };
+
+       fimd@14400000 {
+               samsung,vl-freq = <60>;
+               samsung,vl-col = <1366>;
+               samsung,vl-row = <768>;
+               samsung,vl-width = <1366>;
+               samsung,vl-height = <768>;
+
+               samsung,vl-clkp;
+               samsung,vl-dp;
+               samsung,vl-hsp;
+               samsung,vl-vsp;
+
+               samsung,vl-bpix = <4>;
+
+               samsung,vl-hspw = <32>;
+               samsung,vl-hbpd = <80>;
+               samsung,vl-hfpd = <48>;
+               samsung,vl-vspw = <5>;
+               samsung,vl-vbpd = <14>;
+               samsung,vl-vfpd = <3>;
+               samsung,vl-cmd-allow-len = <0xf>;
+
+               samsung,winid = <0>;
+               samsung,interface-mode = <1>;
+               samsung,dp-enabled = <1>;
+               samsung,dual-lcd-enabled = <0>;
+       };
+
+       dp@145b0000 {
+               samsung,lt-status = <0>;
+
+               samsung,master-mode = <0>;
+               samsung,bist-mode = <0>;
+               samsung,bist-pattern = <0>;
+               samsung,h-sync-polarity = <0>;
+               samsung,v-sync-polarity = <0>;
+               samsung,interlaced = <0>;
+               samsung,color-space = <0>;
+               samsung,dynamic-range = <0>;
+               samsung,ycbcr-coeff = <0>;
+               samsung,color-depth = <1>;
+       };
+
 };
diff --git a/arch/arm/dts/include/dt-bindings b/arch/arm/dts/include/dt-bindings
new file mode 120000 (symlink)
index 0000000..0cecb3d
--- /dev/null
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
index f52fcf1..59434e0 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
                              0 143 0x04>;
        };
 
-       gpio: gpio {
+       gpio: gpio@6000d000 {
                compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-               interrupts = <0 32 0x04
-                             0 33 0x04
-                             0 34 0x04
-                             0 35 0x04
-                             0 55 0x04
-                             0 87 0x04
-                             0 89 0x04
-                             0 125 0x04>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
index 52e8c0e..464287e 100644 (file)
@@ -17,7 +17,8 @@
                sdhci1 = "/sdhci@700b0400";
                spi0 = "/spi@7000d400";
                spi1 = "/spi@7000da00";
-               usb0 = "/usb@7d008000";
+               usb0 = "/usb@7d000000";
+               usb1 = "/usb@7d008000";
        };
 
        memory {
                bus-width = <8>;
        };
 
+       usb@7d000000 {
+               status = "okay";
+               dr_mode = "otg";
+               nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
+       };
+
        usb@7d008000 {
                status = "okay";
                nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
index 2f8d1dc..f003413 100644 (file)
@@ -17,7 +17,8 @@
                sdhci1 = "/sdhci@700b0400";
                spi0 = "/spi@7000d400";
                spi1 = "/spi@7000da00";
-               usb0 = "/usb@7d008000";
+               usb0 = "/usb@7d000000";
+               usb1 = "/usb@7d008000";
        };
 
        memory {
                bus-width = <8>;
        };
 
+       usb@7d000000 {
+               status = "okay";
+               dr_mode = "otg";
+               nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
+       };
+
        usb@7d008000 {
                status = "okay";
                nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
index 18a8b24..4561c5f 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
        gpio: gpio@6000d000 {
                compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-               interrupts = <0 32 0x04
-                             0 33 0x04
-                             0 34 0x04
-                             0 35 0x04
-                             0 55 0x04
-                             0 87 0x04
-                             0 89 0x04
-                             0 125 0x04>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
index 3805750..a524f6e 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
 
        gpio: gpio@6000d000 {
                compatible = "nvidia,tegra20-gpio";
-               reg = < 0x6000d000 0x1000 >;
-               interrupts = < 64 65 66 67 87 119 121 >;
+               reg = <0x6000d000 0x1000>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
+               #interrupt-cells = <2>;
+               interrupt-controller;
        };
 
        pinmux: pinmux@70000000 {
index a7cc93e..85e62e9 100644 (file)
@@ -14,7 +14,8 @@
                i2c4 = "/i2c@7000c700";
                sdhci0 = "/sdhci@78000600";
                sdhci1 = "/sdhci@78000000";
-               usb0 = "/usb@7d008000";
+               usb0 = "/usb@7d000000";
+               usb1 = "/usb@7d008000";
        };
 
        memory {
                bus-width = <8>;
        };
 
+       usb@7d000000 {
+               status = "okay";
+               dr_mode = "otg";
+               nvidia,vbus-gpio = <&gpio 238 0>; /* gpio DD6, PEX_L1_CLKREQ */
+       };
+
        usb@7d008000 {
                nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
                status = "okay";
index fee1c36..7be3791 100644 (file)
@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
                clocks = <&tegra_car 34>;
        };
 
-       gpio: gpio {
+       gpio: gpio@6000d000 {
                compatible = "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-               interrupts = <0 32 0x04
-                             0 33 0x04
-                             0 34 0x04
-                             0 35 0x04
-                             0 55 0x04
-                             0 87 0x04
-                             0 89 0x04
-                             0 125 0x04>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi
new file mode 100644 (file)
index 0000000..a632724
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+       compatible = "ti,tps65217";
+
+       regulators {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               dcdc1_reg: regulator@0 {
+                       reg = <0>;
+                       regulator-compatible = "dcdc1";
+               };
+
+               dcdc2_reg: regulator@1 {
+                       reg = <1>;
+                       regulator-compatible = "dcdc2";
+               };
+
+               dcdc3_reg: regulator@2 {
+                       reg = <2>;
+                       regulator-compatible = "dcdc3";
+               };
+
+               ldo1_reg: regulator@3 {
+                       reg = <3>;
+                       regulator-compatible = "ldo1";
+               };
+
+               ldo2_reg: regulator@4 {
+                       reg = <4>;
+                       regulator-compatible = "ldo2";
+               };
+
+               ldo3_reg: regulator@5 {
+                       reg = <5>;
+                       regulator-compatible = "ldo3";
+               };
+
+               ldo4_reg: regulator@6 {
+                       reg = <6>;
+                       regulator-compatible = "ldo4";
+               };
+       };
+};
index d4799e7..25a9d4c 100644 (file)
@@ -34,10 +34,6 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE
        $(Q)mkdir -p $(dir $@)
        $(call if_changed_dep,cpp_cfg)
 
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-       $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
 MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
        -e $(CONFIG_SYS_TEXT_BASE)
 
index f00fad3..4af6b57 100644 (file)
@@ -107,6 +107,7 @@ const struct dpll_params *get_dpll_mpu_params(void);
 const struct dpll_params *get_dpll_core_params(void);
 const struct dpll_params *get_dpll_per_params(void);
 const struct dpll_params *get_dpll_ddr_params(void);
+void scale_vcores(void);
 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 void prcm_init(void);
 void enable_basic_clocks(void);
index d9f0306..aa10fab 100644 (file)
 #define TCLR_PRE                       BIT(5)  /* Pre-scaler enable */
 #define TCLR_PTV_SHIFT                 (2)     /* Pre-scaler shift value */
 #define TCLR_PRE_DISABLE               CL_BIT(5) /* Pre-scalar disable */
-
+#define TCLR_CE                                BIT(6)  /* compare mode enable */
+#define TCLR_SCPWM                     BIT(7)  /* pwm outpin behaviour */
+#define TCLR_TCM                       BIT(8)  /* edge detection of input pin*/
+#define TCLR_TRG_SHIFT                 (10)    /* trigmode on pwm outpin */
+#define TCLR_PT                                BIT(12) /* pulse/toggle mode of outpin*/
+#define TCLR_CAPTMODE                  BIT(13) /* capture mode */
+#define TCLR_GPOCFG                    BIT(14) /* 0=output,1=input */
+
+#define TCFG_RESET                     BIT(0)  /* software reset */
+#define TCFG_EMUFREE                   BIT(1)  /* behaviour of tmr on debug */
+#define TCFG_IDLEMOD_SHIFT             (2)     /* power management */
 /* device type */
 #define DEVICE_MASK                    (BIT(8) | BIT(9) | BIT(10))
 #define TST_DEVICE                     0x0
@@ -87,7 +97,8 @@ struct cm_wkuppll {
        unsigned int wkctrlclkctrl;     /* offset 0x04 */
        unsigned int wkgpio0clkctrl;    /* offset 0x08 */
        unsigned int wkl4wkclkctrl;     /* offset 0x0c */
-       unsigned int resv2[4];
+       unsigned int timer0clkctrl;     /* offset 0x10 */
+       unsigned int resv2[3];
        unsigned int idlestdpllmpu;     /* offset 0x20 */
        unsigned int resv3[2];
        unsigned int clkseldpllmpu;     /* offset 0x2c */
@@ -121,7 +132,9 @@ struct cm_wkuppll {
        unsigned int wkup_uart0ctrl;    /* offset 0xB4 */
        unsigned int wkup_i2c0ctrl;     /* offset 0xB8 */
        unsigned int wkup_adctscctrl;   /* offset 0xBC */
-       unsigned int resv12[6];
+       unsigned int resv12;
+       unsigned int timer1clkctrl;     /* offset 0xC4 */
+       unsigned int resv13[4];
        unsigned int divm6dpllcore;     /* offset 0xD8 */
 };
 
@@ -178,7 +191,9 @@ struct cm_perpll {
        unsigned int epwmss2clkctrl;    /* offset 0xD8 */
        unsigned int l3instrclkctrl;    /* offset 0xDC */
        unsigned int l3clkctrl;         /* Offset 0xE0 */
-       unsigned int resv8[4];
+       unsigned int resv8[2];
+       unsigned int timer5clkctrl;     /* offset 0xEC */
+       unsigned int timer6clkctrl;     /* offset 0xF0 */
        unsigned int mmc1clkctrl;       /* offset 0xF4 */
        unsigned int mmc2clkctrl;       /* offset 0xF8 */
        unsigned int resv9[8];
@@ -191,9 +206,17 @@ struct cm_perpll {
 
 /* Encapsulating Display pll registers */
 struct cm_dpll {
-       unsigned int resv1[2];
+       unsigned int resv1;
+       unsigned int clktimer7clk;      /* offset 0x04 */
        unsigned int clktimer2clk;      /* offset 0x08 */
-       unsigned int resv2[10];
+       unsigned int clktimer3clk;      /* offset 0x0C */
+       unsigned int clktimer4clk;      /* offset 0x10 */
+       unsigned int resv2;
+       unsigned int clktimer5clk;      /* offset 0x18 */
+       unsigned int clktimer6clk;      /* offset 0x1C */
+       unsigned int resv3[2];
+       unsigned int clktimer1clk;      /* offset 0x28 */
+       unsigned int resv4[2];
        unsigned int clklcdcpixelclk;   /* offset 0x34 */
 };
 #else
index 4535608..04f6239 100644 (file)
@@ -70,7 +70,10 @@ typedef struct at91_pmc {
 
 #define AT91_PMC_MOR_MOSCEN            0x01
 #define AT91_PMC_MOR_OSCBYPASS         0x02
+#define AT91_PMC_MOR_MOSCRCEN          0x08
 #define AT91_PMC_MOR_OSCOUNT(x)                ((x & 0xff) << 8)
+#define AT91_PMC_MOR_KEY(x)            ((x & 0xff) << 16)
+#define AT91_PMC_MOR_MOSCSEL           (1 << 24)
 
 #define AT91_PMC_PLLXR_DIV(x)          (x & 0xFF)
 #define AT91_PMC_PLLXR_PLLCOUNT(x)     ((x & 0x3F) << 8)
@@ -142,6 +145,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_PCKRDY1           0x00000200
 #define AT91_PMC_IXR_PCKRDY2           0x00000400
 #define AT91_PMC_IXR_PCKRDY3           0x00000800
+#define AT91_PMC_IXR_MOSCSELS          0x00010000
 
 #define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define                AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
index a471038..d49c184 100644 (file)
@@ -12,6 +12,9 @@
 #ifndef __AT91SAM9X5_H__
 #define __AT91SAM9X5_H__
 
+#define CONFIG_ARM926EJS       /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY      /* it's a member of AT91 family */
+
 /*
  * Peripheral identifiers/interrupts.
  */
index a63f974..d712a0d 100644 (file)
@@ -25,8 +25,6 @@
 # include <asm/arch/at91sam9x5.h>
 #elif defined(CONFIG_AT91CAP9)
 # include <asm/arch/at91cap9.h>
-#elif defined(CONFIG_AT91X40)
-# include <asm/arch/at91x40.h>
 #elif defined(CONFIG_SAMA5D3)
 # include <asm/arch/sama5d3.h>
 #else
index cdeef32..ffbc07e 100644 (file)
 #define BPLL   5
 #define RPLL   6
 
+#define MASK_PRE_RATIO(x)      (0xff << ((x << 4) + 8))
+#define MASK_RATIO(x)          (0xf << (x << 4))
+#define SET_PRE_RATIO(x, y)    ((y & 0xff) << ((x << 4) + 8))
+#define SET_RATIO(x, y)                ((y & 0xf) << (x << 4))
+
 enum pll_src_bit {
        EXYNOS_SRC_MPLL = 6,
        EXYNOS_SRC_EPLL,
index c9609a2..a4b41ad 100644 (file)
@@ -1726,4 +1726,5 @@ uint32_t get_reset_status(void);
 
 /* Read the resume function and call it */
 void power_exit_wakeup(void);
+
 #endif
index 50ff13a..7ac2662 100644 (file)
 #define K2HK_LPSC_ARM_SREFLEX          51
 #define K2HK_LPSC_TETRIS               52
 
-#define K2HK_UART0_BASE                0x02530c00
-
 /* DDR3A definitions */
 #define K2HK_DDR3A_EMIF_CTRL_BASE      0x21010000
 #define K2HK_DDR3A_EMIF_DATA_BASE      0x80000000
index a305a0c..6c532ca 100644 (file)
@@ -142,6 +142,9 @@ struct ddr3_emif_config {
 #define KS2_DDR3_PMCTL_OFFSET           0x38
 #define KS2_DDR3_ZQCFG_OFFSET           0xC8
 
+#define KS2_UART0_BASE                 0x02530c00
+#define KS2_UART1_BASE                 0x02531000
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
index bdb1435..d2dfb1e 100644 (file)
@@ -354,14 +354,6 @@ enum {
 
 #define GPMC_CS_ENABLE         0x1
 
-#define SMNAND_GPMC_CONFIG1    0x00000800
-#define SMNAND_GPMC_CONFIG2    0x00141400
-#define SMNAND_GPMC_CONFIG3    0x00141400
-#define SMNAND_GPMC_CONFIG4    0x0F010F01
-#define SMNAND_GPMC_CONFIG5    0x010C1414
-#define SMNAND_GPMC_CONFIG6    0x1F0F0A80
-#define SMNAND_GPMC_CONFIG7    0x00000C44
-
 #define M_NAND_GPMC_CONFIG1    0x00001800
 #define M_NAND_GPMC_CONFIG2    0x00141400
 #define M_NAND_GPMC_CONFIG3    0x00141400
index e17c7d1..5256624 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -150,6 +150,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK             0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)               ((v) & 0x7)
 
+#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET                22
+#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK          (0x3 << 22)
+#define CCM_CSCMR1_QSPI0_CLK_SEL(v)            (((v) & 0x3) << 22)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET       18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK         (0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)           (((v) & 0x3) << 18)
@@ -161,6 +164,11 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK         (0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)           (((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_QSPI0_EN                    (1 << 4)
+#define CCM_CSCDR3_QSPI0_DIV(v)                        ((v) << 3)
+#define CCM_CSCDR3_QSPI0_X2_DIV(v)             ((v) << 2)
+#define CCM_CSCDR3_QSPI0_X4_DIV(v)             ((v) & 0x3)
+
 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET         4
 #define CCM_CSCMR2_RMII_CLK_SEL_MASK           (0x3 << 4)
 #define CCM_CSCMR2_RMII_CLK_SEL(v)             (((v) & 0x3) << 4)
@@ -170,6 +178,7 @@ struct anadig_reg {
 #define CCM_CCGR0_UART1_CTRL_MASK              (0x3 << 16)
 #define CCM_CCGR1_PIT_CTRL_MASK                        (0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK             (0x3 << 28)
+#define CCM_CCGR2_QSPI0_CTRL_MASK              (0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK             (0x3 << 16)
 #define CCM_CCGR2_PORTA_CTRL_MASK              (0x3 << 18)
 #define CCM_CCGR2_PORTB_CTRL_MASK              (0x3 << 20)
index 0c28e1b..bd6f680 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -87,6 +87,8 @@
 #define ENET_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00051000)
 
+#define QSPI0_AMBA_BASE                0x20000000
+
 /* MUX mode and PAD ctrl are in one register */
 #define CONFIG_IOMUX_SHARE_CONF_REG
 
index 88807d8..a965641 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -20,6 +20,9 @@
 #define VF610_I2C_PAD_CTRL     (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
                                PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
 
+#define VF610_QSPI_PAD_CTRL    (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
+                               PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
+
 enum {
        VF610_PAD_PTA6__RMII0_CLKIN             = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
        VF610_PAD_PTA6__RMII0_CLKOUT            = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -53,6 +56,18 @@ enum {
        VF610_PAD_PTA29__ESDHC1_DAT3            = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
        VF610_PAD_PTB14__I2C0_SCL               = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
        VF610_PAD_PTB15__I2C0_SDA               = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+       VF610_PAD_PTD0__QSPI0_A_QSCK            = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD1__QSPI0_A_CS0             = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD2__QSPI0_A_DATA3           = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD3__QSPI0_A_DATA2           = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD4__QSPI0_A_DATA1           = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD5__QSPI0_A_DATA0           = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD7__QSPI0_B_QSCK            = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD8__QSPI0_B_CS0             = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD9__QSPI0_B_DATA3           = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD10__QSPI0_B_DATA2          = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD11__QSPI0_B_DATA1          = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD12__QSPI0_B_DATA0          = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
        VF610_PAD_DDR_A15__DDR_A_15             = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A14__DDR_A_14             = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A13__DDR_A_13             = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
index 1b22eeb..34c07fe 100644 (file)
@@ -25,7 +25,7 @@ typedef struct { volatile int counter; } atomic_t;
 #define ATOMIC_INIT(i) { (i) }
 
 #ifdef __KERNEL__
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
 
 #define atomic_read(v) ((v)->counter)
 #define atomic_set(v,i)        (((v)->counter) = (i))
index 879e20e..597dafb 100644 (file)
@@ -17,7 +17,7 @@
 
 #ifdef __KERNEL__
 
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
 
 #define smp_mb__before_clear_bit()     do { } while (0)
 #define smp_mb__after_clear_bit()      do { } while (0)
index dfe1ebf..e91d4ac 100644 (file)
@@ -123,12 +123,14 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_SPEED_MED      (1 << 12)
 #define PAD_CTL_SPEED_HIGH     (3 << 12)
 
+#define PAD_CTL_DSE_150ohm     (1 << 6)
 #define PAD_CTL_DSE_50ohm      (3 << 6)
 #define PAD_CTL_DSE_25ohm      (6 << 6)
 #define PAD_CTL_DSE_20ohm      (7 << 6)
 
 #define PAD_CTL_PUS_47K_UP     (1 << 4 | PAD_CTL_PUE)
 #define PAD_CTL_PUS_100K_UP    (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP     (3 << 4 | PAD_CTL_PUE)
 #define PAD_CTL_PKE            (1 << 3)
 #define PAD_CTL_PUE            (1 << 2 | PAD_CTL_PKE)
 
index 6a1f05a..9f35fd6 100644 (file)
@@ -437,4 +437,7 @@ out:
 
 #endif /* __mem_isa */
 #endif /* __KERNEL__ */
+
+#include <iotrace.h>
+
 #endif /* __ASM_ARM_IO_H */
index 5bfab7f..532f207 100644 (file)
@@ -18,7 +18,7 @@
 #ifndef __ASM_PROC_PROCESSOR_H
 #define __ASM_PROC_PROCESSOR_H
 
-#include <asm/proc/domain.h>
+#include <asm/proc-armv/domain.h>
 
 #define KERNEL_STACK_SIZE      PAGE_SIZE
 
index 445d449..83481c6 100644 (file)
@@ -45,7 +45,7 @@ typedef unsigned long mm_segment_t;           /* domain register      */
 #if 0  /* XXX###XXX */
 #include <asm/arch/memory.h>
 #endif /* XXX###XXX */
-#include <asm/proc/processor.h>
+#include <asm/proc-armv/processor.h>
 #include <asm/types.h>
 
 union debug_insn {
index 73c9087..a836f6c 100644 (file)
@@ -11,7 +11,7 @@
 /* options set using PTRACE_SETOPTIONS */
 #define PTRACE_O_TRACESYSGOOD  0x00000001
 
-#include <asm/proc/ptrace.h>
+#include <asm/proc-armv/ptrace.h>
 
 #ifndef __ASSEMBLY__
 #define pc_pointer(v) \
index 9b473b5..76adaf3 100644 (file)
@@ -277,7 +277,7 @@ void board_init_f(ulong bootflag)
        gd->mon_len = (ulong)&__bss_end - (ulong)_start;
 #ifdef CONFIG_OF_EMBED
        /* Get a pointer to the FDT */
-       gd->fdt_blob = __dtb_db_begin;
+       gd->fdt_blob = __dtb_dt_begin;
 #elif defined CONFIG_OF_SEPARATE
        /* FDT is at end of image */
        gd->fdt_blob = &_end;
index d68cc47..e6538ef 100644 (file)
@@ -43,8 +43,6 @@
  *************************************************************************
  */
 
-_start:
-
 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
        .word   CONFIG_SYS_DV_NOR_BOOT_CFG
 #endif
index ab0374e..b3ffc33 100644 (file)
@@ -24,31 +24,31 @@ void dcache_clean_range(volatile void *start, size_t size)
        sync_write_buffer();
 }
 
-void dcache_invalidate_range(volatile void *start, size_t size)
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-       unsigned long v, begin, end, linesz;
+       unsigned long v, linesz;
 
        linesz = CONFIG_SYS_DCACHE_LINESZ;
 
        /* You asked for it, you got it */
-       begin = (unsigned long)start & ~(linesz - 1);
-       end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+       start = start & ~(linesz - 1);
+       stop = (stop + linesz - 1) & ~(linesz - 1);
 
-       for (v = begin; v < end; v += linesz)
+       for (v = start; v < stop; v += linesz)
                dcache_invalidate_line((void *)v);
 }
 
-void dcache_flush_range(volatile void *start, size_t size)
+void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-       unsigned long v, begin, end, linesz;
+       unsigned long v, linesz;
 
        linesz = CONFIG_SYS_DCACHE_LINESZ;
 
        /* You asked for it, you got it */
-       begin = (unsigned long)start & ~(linesz - 1);
-       end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+       start = start & ~(linesz - 1);
+       stop = (stop + linesz - 1) & ~(linesz - 1);
 
-       for (v = begin; v < end; v += linesz)
+       for (v = start; v < stop; v += linesz)
                dcache_flush_line((void *)v);
 
        sync_write_buffer();
index 13d6d3a..e08cd9d 100644 (file)
@@ -49,9 +49,7 @@ static inline void icache_invalidate_line(volatile void *vaddr)
  * Applies the above functions on all lines that are touched by the
  * specified virtual address range.
  */
-void dcache_invalidate_range(volatile void *start, size_t len);
 void dcache_clean_range(volatile void *start, size_t len);
-void dcache_flush_range(volatile void *start, size_t len);
 void icache_invalidate_range(volatile void *start, size_t len);
 
 static inline void dcache_flush_unlocked(void)
index 95ea81f..dbdd2fe 100644 (file)
@@ -23,13 +23,15 @@ static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
 
        switch (dir) {
        case DMA_BIDIRECTIONAL:
-               dcache_flush_range(vaddr, len);
+               flush_dcache_range((unsigned long)vaddr,
+                                  (unsigned long)vaddr + len);
                break;
        case DMA_TO_DEVICE:
                dcache_clean_range(vaddr, len);
                break;
        case DMA_FROM_DEVICE:
-               dcache_invalidate_range(vaddr, len);
+               invalidate_dcache_range((unsigned long)vaddr,
+                                       (unsigned long)vaddr + len);
                break;
        default:
                /* This will cause a linker error */
index 7680102..bf0997f 100644 (file)
@@ -65,8 +65,8 @@ static void dma_alloc_init(void)
        printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
               dma_alloc_start, dma_alloc_end);
 
-       dcache_invalidate_range(cached(dma_alloc_start),
-                               dma_alloc_end - dma_alloc_start);
+       invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
+                               dma_alloc_end);
 }
 
 void *dma_alloc_coherent(size_t len, unsigned long *handle)
index db7ded4..8d01f5f 100644 (file)
@@ -208,10 +208,10 @@ void cpu_init_f(void)
        scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
        fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+#ifndef CONFIG_WATCHDOG
        wdog_t *wdog = (wdog_t *) MMAP_WDOG;
 
        /* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
        out_be16(&wdog->cr, 0);
 #endif
 
index 9c324dc..b4a8eef 100644 (file)
@@ -364,9 +364,9 @@ void uart_port_conf(int port)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
        struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
-#ifdef CONFIG_MCF5445x
        if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
index 5a87a9b..2d2a519 100644 (file)
 #define writew(b,addr)         ((*(volatile u16 *) (addr)) = (b))
 #define writel(b,addr)         ((*(volatile u32 *) (addr)) = (b))
 #else
-#define readw(addr)            in_le16((volatile u16 *)(addr))
-#define readl(addr)            in_le32((volatile u32 *)(addr))
-#define writew(b,addr)         out_le16((volatile u16 *)(addr),(b))
-#define writel(b,addr)         out_le32((volatile u32 *)(addr),(b))
+#define readw(addr)            in_be16((volatile u16 *)(addr))
+#define readl(addr)            in_be32((volatile u32 *)(addr))
+#define writew(b,addr)         out_be16((volatile u16 *)(addr),(b))
+#define writel(b,addr)         out_be32((volatile u32 *)(addr),(b))
 #endif
 
 /*
index 4fbc040..b97d267 100644 (file)
@@ -15,7 +15,7 @@ typedef long          __kernel_off_t;
 typedef int            __kernel_pid_t;
 typedef unsigned int   __kernel_uid_t;
 typedef unsigned int   __kernel_gid_t;
-typedef unsigned int   __kernel_size_t;
+typedef unsigned long  __kernel_size_t;
 typedef int            __kernel_ssize_t;
 typedef long           __kernel_ptrdiff_t;
 typedef long           __kernel_time_t;
index 318ca01..9caff73 100644 (file)
@@ -31,9 +31,6 @@
 #endif
 #include <net.h>
 #include <serial.h>
-#if defined(CONFIG_CMD_BEDBUG)
-#include <cmd_bedbug.h>
-#endif
 #ifdef CONFIG_SYS_ALLOC_DPRAM
 #include <commproc.h>
 #endif
@@ -602,11 +599,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
        last_stage_init ();
 #endif
 
-#if defined(CONFIG_CMD_BEDBUG)
-       WATCHDOG_RESET ();
-       bedbug_init ();
-#endif
-
 #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
        /*
         * Export available size of memory for Linux,
@@ -628,13 +620,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
        }
 #endif
 
-#ifdef CONFIG_MODEM_SUPPORT
- {
-        extern int do_mdm_init;
-        do_mdm_init = gd->do_mdm_init;
- }
-#endif
-
 #ifdef CONFIG_WATCHDOG
        /* disable watchdog if environment is set */
        if ((s = getenv ("watchdog")) != NULL) {
index 804e01d..fa9c493 100644 (file)
@@ -50,11 +50,7 @@ void arch_lmb_reserve(struct lmb *lmb)
 
 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
 {
-       ulong rd_len;
-       ulong initrd_start, initrd_end;
        int ret;
-
-       ulong cmd_start, cmd_end;
        bd_t  *kbd;
        void  (*kernel) (bd_t *, ulong, ulong, ulong, ulong);
        struct lmb *lmb = &images->lmb;
@@ -96,7 +92,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
         *   sp+16: Start of command line string
         *   sp+20: End   of command line string
         */
-       (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+       (*kernel)(kbd, images->initrd_start, images->initrd_end,
+                 images->cmdline_start, images->cmdline_end);
        /* does not return */
 error:
        return 1;
diff --git a/arch/microblaze/dts/include/dt-bindings b/arch/microblaze/dts/include/dt-bindings
new file mode 120000 (symlink)
index 0000000..0cecb3d
--- /dev/null
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
index d60b307..6977dd6 100644 (file)
@@ -58,7 +58,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
        /* fixup the initrd now that we know where it should be */
        if (images->rd_start && images->rd_end && of_flat_tree)
                ret = fdt_initrd(of_flat_tree, images->rd_start,
-                                images->rd_end, 1);
+                                images->rd_end);
                if (ret)
                        return 1;
 
index c54b0cf..1ae3b75 100644 (file)
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
  * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
+ * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -40,9 +41,48 @@ __reset:
        l.ori   r3,r0,SPR_SR_SM
        l.mtspr r0,r3,SPR_SR
 
+       l.jal   _cur
+       l.nop
+_cur:
+       l.ori   r8, r9, 0               /* Get _cur current address */
+
+       l.movhi r3, hi(_cur)
+       l.ori   r3, r3, lo(_cur)
+       l.sfeq  r8, r3                  /* If we are running at the linked address */
+       l.bf    _no_vector_reloc        /* there is not need for relocation */
+        l.sub  r8, r8, r3
+
+       l.mfspr r4, r0, SPR_CPUCFGR
+       l.andi  r4, r4, SPR_CPUCFGR_EVBARP      /* Exception Vector Base Address Register present ? */
+       l.sfnei r4,0
+       l.bnf   _reloc_vectors
+       l.movhi r5, 0                   /* Destination */
+
+       l.mfspr r4, r0, SPR_EVBAR
+       l.add   r5, r5, r4
+
+_reloc_vectors:
+       /* Relocate vectors*/
+       l.movhi r5, 0                   /* Destination */
+       l.movhi r6, hi(__start)         /* Length */
+       l.ori   r6, r6, lo(__start)
+       l.ori   r3, r8, 0
+
+.L_relocvectors:
+       l.lwz   r7, 0(r3)
+       l.sw    0(r5), r7
+       l.addi  r5, r5, 4
+       l.sfeq  r5, r6
+       l.bnf   .L_relocvectors
+        l.addi r3, r3, 4
+
+_no_vector_reloc:
+
        /* Relocate u-boot */
-       l.movhi r3,hi(__start)          /* source start address */
+       l.movhi r3,hi(__start)          /* source start offset */
        l.ori   r3,r3,lo(__start)
+       l.add   r3,r8,r3
+
        l.movhi r4,hi(_stext)           /* dest start address */
        l.ori   r4,r4,lo(_stext)
        l.movhi r5,hi(__end)            /* dest end address */
@@ -56,19 +96,6 @@ __reset:
        l.bf    .L_reloc
         l.addi r4,r4,4                 /* delay slot */
 
-#ifdef CONFIG_SYS_RELOCATE_VECTORS
-       /* Relocate vectors from 0xf0000000 to 0x00000000 */
-       l.movhi r4, 0xf000 /* source */
-       l.movhi r5, 0      /* destination */
-       l.addi  r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
-.L_relocvectors:
-       l.lwz   r7, 0(r4)
-       l.sw    0(r5), r7
-       l.addi  r5, r5, 4
-       l.sfeq  r5,r6
-       l.bnf   .L_relocvectors
-        l.addi r4,r4, 4
-#endif
        l.movhi r4,hi(_start)
        l.ori   r4,r4,lo(_start)
        l.jr    r4
index a863b3e..e30d210 100644 (file)
 #define SPR_ICCFGR     (SPRGROUP_SYS + 6)
 #define SPR_DCFGR      (SPRGROUP_SYS + 7)
 #define SPR_PCCFGR     (SPRGROUP_SYS + 8)
+#define SPR_VR2                (SPRGROUP_SYS + 9)
+#define SPR_AVR                (SPRGROUP_SYS + 10)
+#define SPR_EVBAR      (SPRGROUP_SYS + 11)
+#define SPR_AECR       (SPRGROUP_SYS + 12)
+#define SPR_AESR       (SPRGROUP_SYS + 13)
 #define SPR_NPC                (SPRGROUP_SYS + 16)
 #define SPR_SR         (SPRGROUP_SYS + 17)
 #define SPR_PPC                (SPRGROUP_SYS + 18)
 #define SPR_CPUCFGR_OF32S      0x00000080 /* ORFPX32 supported */
 #define SPR_CPUCFGR_OF64S      0x00000100 /* ORFPX64 supported */
 #define SPR_CPUCFGR_OV64S      0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_RES                0xfffffc00 /* Reserved */
+#define SPR_CPUCFGR_ND         0x00000400 /* No delay slot */
+#define SPR_CPUCFGR_AVRP       0x00000800 /* Arch. Version Register present */
+#define SPR_CPUCFGR_EVBARP     0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
+#define SPR_CPUCFGR_ISRP       0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
+#define SPR_CPUCFGR_AECSRP     0x00004000 /* Arithmetic Exception Control Register (AECR) and */
+                                          /* Arithmetic Exception Status Register (AESR) presents */
+#define SPR_CPUCFGR_RES                0xffffc000 /* Reserved */
 
 /*
  * Bit definitions for the Debug configuration register and other
index 2c013bb..0a47fdc 100644 (file)
@@ -242,8 +242,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
        immap->im_siu_conf.sc_siumcr =
                (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
                | SIUMCR_LBPC01;
-#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/* nothing to do for this board here */
 #elif defined CONFIG_MPC8272
        immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
                                  ~SIUMCR_BBD &
index 324f132..d7eaf13 100644 (file)
@@ -137,19 +137,6 @@ _hrcw_table:
 
        .globl  _start
 _start:
-#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
-       lis     r3, CONFIG_SYS_DEFAULT_IMMR@h
-       nop
-       lwz     r4, 0(r3)
-       nop
-       rlwinm  r4, r4, 0, 8, 5
-       nop
-       oris    r4, r4, 0x0200
-       nop
-       stw     r4, 0(r3)
-       nop
-#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
-
        mfmsr   r5                      /* save msr contents            */
 
 #if defined(CONFIG_COGENT)
index 3d37a76..3a04a89 100644 (file)
@@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
                puts("Work-around for Erratum NMG ETSEC129 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+       puts("Work-around for Erratum A004508 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
        puts("Work-around for Erratum A004510 enabled\n");
 #endif
@@ -266,6 +269,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
        puts("Work-around for Erratum USB14 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+       puts("Work-around for Erratum A007186 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
        puts("Work-around for Erratum A006593 enabled\n");
 #endif
index d6cf885..78316a6 100644 (file)
@@ -225,6 +225,32 @@ static void disable_cpc_sram(void)
 }
 #endif
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+       int ret;
+       char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+       int tdm_hwconfig_enabled = 0;
+
+       /*
+        * Extract hwconfig from environment since environment
+        * is not setup properly yet. Search for tdm entry in
+        * hwconfig.
+        */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0) {
+               tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+               /* If tdm is defined in hwconfig, set law for tdm workaround */
+               if (tdm_hwconfig_enabled)
+                       set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+                                    LAW_TRGT_IF_CCSR);
+       }
+}
+#endif
+
 static void enable_cpc(void)
 {
        int i;
@@ -729,6 +755,9 @@ skip_l2:
        disable_cpc_sram();
 #endif
        enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+       enable_tdm_law();
+#endif
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
        /* needs to be in ram since code uses global static vars */
index ed80a84..85dfa5b 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/ctype.h>
 #include <asm/io.h>
 #include <asm/fsl_portals.h>
+#include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
@@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
        u32 bootpg = determine_mp_bootpg(NULL);
        u32 id = get_my_id();
        const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+       int ret;
+       int tdm_hwconfig_enabled = 0;
+       char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
 
        off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
        while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
                                "device_type", "cpu", 4);
        }
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define        CONFIG_MEM_HOLE_16M     0x1000000
+       /*
+        * Extract hwconfig from environment.
+        * Search for tdm entry in hwconfig.
+        */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0)
+               tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+       /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+       if (tdm_hwconfig_enabled) {
+               off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+                                     CONFIG_MEM_HOLE_16M);
+               if (off < 0)
+                       printf("Failed  to reserve memory for tdm: %s\n",
+                              fdt_strerror(off));
+       }
+#endif
+
        /* Reserve the boot page so OSes dont use it */
        if ((u64)bootpg < memory_limit) {
                off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
index 70e09ea..d1fc76a 100644 (file)
@@ -147,12 +147,43 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
        return -ENODEV;
 }
 
+#define BC3_SHIFT      9
+#define DC3_SHIFT      6
+#define FC3_SHIFT      0
+#define BC2_SHIFT      19
+#define DC2_SHIFT      16
+#define FC2_SHIFT      10
+#define BC1_SHIFT      29
+#define DC1_SHIFT      26
+#define FC1_SHIFT      20
+#define BC_MASK                0x1
+#define DC_MASK                0x7
+#define FC_MASK                0x3F
+
+#define FUSE_VAL_MASK          0x00000003
+#define FUSE_VAL_SHIFT         30
+#define CR0_DCBIAS_SHIFT       5
+#define CR1_FCAP_SHIFT         15
+#define CR1_BCAP_SHIFT         29
+#define FCAP_MASK              0x001F8000
+#define BCAP_MASK              0x20000000
+#define BCAP_OVD_MASK          0x10000000
+#define BYP_CAL_MASK           0x02000000
+
 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 {
        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        u64 serdes_prtcl_map = 0;
        u32 cfg;
        int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+       struct ccsr_sfp_regs  __iomem *sfp_regs =
+                       (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+       u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+       u32 bc_status, fc_status, dc_status, pll_sr2;
+       serdes_corenet_t  __iomem *srds_regs = (void *)sd_addr;
+       u32 sfp_spfr0, sel;
+#endif
 
        cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
        /* Is serdes enabled at all? */
@@ -161,6 +192,123 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
                return 0;
        }
 
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+       sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+       debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+       sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+       if (sel == 0x01 || sel == 0x02) {
+               for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+                       pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       debug("A007186: pll_num=%x pllcr0=%x\n",
+                             pll_num, pll_status);
+                       /* STEP 1 */
+                       /* Read factory pre-set SerDes calibration values
+                        * from fuse block(SFP scratch register-sfp_spfr0)
+                        */
+                       switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+                       case SRDS_PLLCR0_FRATE_SEL_3_0:
+                       case SRDS_PLLCR0_FRATE_SEL_3_072:
+                               debug("A007186: 3.0/3.072 protocol rate\n");
+                               bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+                               dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+                               fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+                               break;
+                       case SRDS_PLLCR0_FRATE_SEL_3_125:
+                               debug("A007186: 3.125 protocol rate\n");
+                               bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+                               dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+                               fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+                               break;
+                       case SRDS_PLLCR0_FRATE_SEL_3_75:
+                               debug("A007186: 3.75 protocol rate\n");
+                               bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+                               dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+                               fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+                               break;
+                       default:
+                               continue;
+                       }
+
+                       /* STEP 2 */
+                       /* Write SRDSxPLLnCR1[11:16] = FC
+                        * Write SRDSxPLLnCR1[2] = BC
+                        */
+                       pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+                       pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+                                     ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+                       out_be32(&srds_regs->bank[pll_num].pllcr1,
+                                (pll_cr_upd | pll_cr1));
+                       debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+                             pll_num, (pll_cr_upd | pll_cr1));
+                       /* Write SRDSxPLLnCR0[24:26] = DC
+                        */
+                       pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       out_be32(&srds_regs->bank[pll_num].pllcr0,
+                                pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+                       debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+                             pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+                       /* Write SRDSxPLLnCR1[3] = 1
+                        * Write SRDSxPLLnCR1[6] = 1
+                        */
+                       pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+                       pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+                       out_be32(&srds_regs->bank[pll_num].pllcr1,
+                                (pll_cr_upd | pll_cr1));
+                       debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+                             pll_num, (pll_cr_upd | pll_cr1));
+
+                       /* STEP 3 */
+                       /* Read the status Registers */
+                       /* Verify SRDSxPLLnSR2[8] = BC */
+                       pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+                       debug("A007186: pll_num=%x pllsr2=%x\n",
+                             pll_num, pll_sr2);
+                       bc_status = (pll_sr2 >> 23) & BC_MASK;
+                       if (bc_status != bc)
+                               debug("BC mismatch\n");
+                       fc_status = (pll_sr2 >> 16) & FC_MASK;
+                       if (fc_status != fc)
+                               debug("FC mismatch\n");
+                       pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+                                                               0x02000000);
+                       pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+                       dc_status = (pll_sr2 >> 17) & DC_MASK;
+                       if (dc_status != dc)
+                               debug("DC mismatch\n");
+                       pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+                                                               0xfdffffff);
+
+                       /* STEP 4 */
+                       /* Wait 750us to verify the PLL is locked
+                        * by checking SRDSxPLLnCR0[8] = 1.
+                        */
+                       udelay(750);
+                       pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+                       debug("A007186: pll_num=%x pllcr0=%x\n",
+                             pll_num, pll_status);
+
+                       if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+                               printf("A007186 Serdes PLL not locked\n");
+                       else
+                               debug("A007186 Serdes PLL locked\n");
+               }
+       }
+#endif
+
        cfg >>= sd_prctl_shift;
        printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
        if (!is_serdes_prtcl_valid(sd, cfg))