mmc: fsl_esdhc: Add support for DDR mode

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3c0a7450c921cce9ae69e23459fc3552f296bded..8e6160840a823735e7edfba402677002fd555563 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -341,7 +341,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
        esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 #if defined(CONFIG_FSL_USDHC)
        esdhc_write32(&regs->mixctrl,
-       (esdhc_read32(&regs->mixctrl) & ~0x7f) | (xfertyp & 0x7F));
+       (esdhc_read32(&regs->mixctrl) & ~0x7f) | (xfertyp & 0x7F)
+                       | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
        esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 #else
        esdhc_write32(&regs->xfertyp, xfertyp);
@@ -488,7 +489,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
                if ((sdhc_clk / (div * pre_div)) <= clock)
                        break;
 
-       pre_div >>= 1;
+       pre_div >>= mmc->ddr_mode ? 2 : 1;
        div -= 1;
 
        clk = (pre_div << 8) | (div << 4);
@@ -651,6 +652,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
        }
 
        cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+       cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+#endif
 
        if (cfg->max_bus_width > 0) {
                if (cfg->max_bus_width < 8)

diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index e0528ce4b928839ce1619d6694e3b08f9be58f57..29b72b2e9ddf718d62292c911f7366176207056e 100644 (file)
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -28,6 +28,8 @@
 #define CONFIG_SYS_PL310_BASE  L2_PL310_BASE
 #endif
 
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
 #define CONFIG_MP
 #define CONFIG_MXC_GPT_HCLK
 

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index dceed38342b9a5f98029276119b8d6479a7dc89c..4f0b72481f6d70cd1518c196a367468635a10589 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -109,6 +109,7 @@
 #define XFERTYP_RSPTYP_48_BUSY 0x00030000
 #define XFERTYP_MSBSEL         0x00000020
 #define XFERTYP_DTDSEL         0x00000010
+#define XFERTYP_DDREN          0x00000008
 #define XFERTYP_AC12EN         0x00000004
 #define XFERTYP_BCEN           0x00000002
 #define XFERTYP_DMAEN          0x00000001