arm: mx5: add ldb clock support

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 21fef9f55d8f144537577b264e6e98ebe5861def..02f3b4892b10f32b37d448bd4bd88afac072f0dc 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -76,7 +76,14 @@ int clk_enable(struct clk *clk)
 
        if (!clk)
                return 0;
+
+       if (clk->id >= 0)
+               printf("enabling %s.%d clock %d\n", clk->name, clk->id, clk->usecount);
+       else
+               printf("enabling %s clock %d\n", clk->name, clk->usecount);
        if (clk->usecount++ == 0) {
+               if (!clk->enable)
+                       return 0;
                ret = clk->enable(clk);
                if (ret)
                        clk->usecount--;
@@ -89,13 +96,17 @@ void clk_disable(struct clk *clk)
        if (!clk)
                return;
 
+       if (clk->id >= 0)
+               printf("disabling %s.%d clock %d\n", clk->name, clk->id, clk->usecount);
+       else
+               printf("disabling %s clock %d\n", clk->name, clk->usecount);
        if (!(--clk->usecount)) {
                if (clk->disable)
                        clk->disable(clk);
        }
        if (clk->usecount < 0) {
-               printf("%s: clk %p underflow\n", __func__, clk);
-               hang();
+               printf("%s: clk %p (%s) underflow\n", __func__, clk, clk->name);
+               //hang();
        }
 }
 
@@ -206,6 +217,72 @@ void ipu_clk_disable(void)
        setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
 }
 
+void ipu_di_clk_enable(int di)
+{
+       switch (di) {
+       case 0:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid DI index %d\n", __func__, di);
+       }
+}
+
+void ipu_di_clk_disable(int di)
+{
+       switch (di) {
+       case 0:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid DI index %d\n", __func__, di);
+       }
+}
+
+#ifdef CONFIG_MX53
+void ldb_clk_enable(int ldb)
+{
+       switch (ldb) {
+       case 0:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               setbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid LDB index %d\n", __func__, ldb);
+       }
+}
+
+void ldb_clk_disable(int ldb)
+{
+       switch (ldb) {
+       case 0:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
+               break;
+       case 1:
+               clrbits_le32(&mxc_ccm->CCGR6,
+                       MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
+               break;
+       default:
+               printf("%s: Invalid LDB index %d\n", __func__, ldb);
+       }
+}
+#endif
+
 #ifdef CONFIG_I2C_MXC
 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)

diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 5d795bd7f5b831f5228f03e58082711e0ce7e99f..e1bed5bf198827f60b14c15cfc3c1f51edda416d 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -102,5 +102,9 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_nfc_clk(unsigned char enable);
 void ipu_clk_enable(void);
 void ipu_clk_disable(void);
+void ipu_di_clk_enable(int di);
+void ipu_di_clk_disable(int di);
+void ldb_clk_enable(int ldb);
+void ldb_clk_disable(int ldb);
 
 #endif /* __ASM_ARCH_CLOCK_H */