mx6: Set shared override bit in PL310 AUX_CTRL register
authorFabio Estevam <fabio.estevam@freescale.com>
Wed, 11 Mar 2015 20:12:12 +0000 (17:12 -0300)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 1 Sep 2015 12:45:40 +0000 (14:45 +0200)
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/include/asm/pl310.h

index e9f69d4..6309c25 100644 (file)
@@ -721,6 +721,14 @@ void v7_outer_cache_enable(void)
        struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
        unsigned int val;
 
+
+       /*
+        * Set bit 22 in the auxiliary control register. If this bit
+        * is cleared, PL310 treats Normal Shared Non-cacheable
+        * accesses as Cacheable no-allocate.
+        */
+       setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
+
 #if defined CONFIG_SOC_MX6SL
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        val = readl(&iomux->gpr[11]);
index ddc245b..de7650e 100644 (file)
@@ -16,6 +16,8 @@
 #define L2X0_STNDBY_MODE_EN                    (1 << 0)
 #define L2X0_CTRL_EN                           1
 
+#define L310_SHARED_ATT_OVERRIDE_ENABLE                (1 << 22)
+
 struct pl310_regs {
        u32 pl310_cache_id;
        u32 pl310_cache_type;