ARM: Introduce erratum workaround for 621766

621766: Under a specific set of conditions, executing a sequence of
	NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index d0fc59313edbcdd97572628c4da525ceed79e1ab..d09bded9ee369d227f5d15aa4ccd84dbedd8ef45 100644 (file)
--- a/README
+++ b/README
@@ -695,6 +695,7 @@ The following options need to be configured:
                specific checks, but expect no product checks.
                CONFIG_ARM_ERRATA_430973
                CONFIG_ARM_ERRATA_454179
+               CONFIG_ARM_ERRATA_621766
                CONFIG_ARM_ERRATA_798870
 
 - Tegra SoC options:

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 41fb24cf321b25ed9ff3d6c4cdebea28e380fa0e..5050021e0210edec4f760a35baaa4fa763b966fd 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -213,6 +213,19 @@ skip_errata_454179:
        pop     {r1-r5}                 @ Restore the cpu info - fall through
 
 skip_errata_430973:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_621766
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_621766
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x1 << 5)     @ Set L1NEON bit
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_621766:
 #endif
 
        mov     pc, r5                  @ back to my caller