karo: tx6ul: fix ENET2_TX_CLK pad settings
authorLothar Waßmann <LW@KARO-electronics.de>
Thu, 4 Feb 2016 12:48:54 +0000 (13:48 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 4 Feb 2016 12:48:54 +0000 (13:48 +0100)
board/karo/tx6/tx6ul_ll_init.S

index c587d75..299e469 100644 (file)
@@ -510,7 +510,7 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET       0x020e0288
 
 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK     0x020e0368
-#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK     0x020e037c
+#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK     0x020e0388
 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B                0x020e0404
 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B                0x020e0408
 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00      0x020e040c
@@ -548,9 +548,9 @@ dcd_hdr:
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9)
        /* ENET_REF_CLK */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK, 0x00000014)
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000010b0)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000000b1)
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK, 0x00000014)
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000010b0)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000000b1)
        MXC_DCD_ITEM(IOMUXC_ENET1_REF_CLK1_SELECT_INPUT, 2)
        MXC_DCD_ITEM(IOMUXC_ENET2_REF_CLK2_SELECT_INPUT, 2)
        /* ETN PHY nRST */
@@ -598,9 +598,10 @@ dcd_hdr:
        MXC_DCD_ITEM(0x020c80b0, 0)
        MXC_DCD_ITEM(0x020c80c0, 1)
        MXC_DCD_ITEM(0x020c80a0, 0x0010201b) /* set video PLL to 648MHz */
+
        /* IOMUX: */
        MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000)
-       MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET1_TX_CLK output */
+       MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET[12]_TX_CLK output */
        MXC_DCD_ITEM(IOMUXC_GPR2, 0x00000000)
        MXC_DCD_ITEM(IOMUXC_GPR3, 0x00000fff)
        MXC_DCD_ITEM(IOMUXC_GPR4, 0x00000100)