ifneq ($(CONFIG_X86_RESET_VECTOR),)
rom: u-boot.rom FORCE
-u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
- $(srctree)/board/$(BOARDDIR)/mrc.bin
- $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp
- if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \
- $(objtree)/tools/ifdtool -D \
- $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \
- $(objtree)/tools/ifdtool \
- -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \
- fi
- $(objtree)/tools/ifdtool -w \
- $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
- $(objtree)/tools/ifdtool -w \
- $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \
- u-boot.tmp
- $(objtree)/tools/ifdtool -w \
- $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
- u-boot.tmp
- $(objtree)/tools/ifdtool -w \
- $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) \
- u-boot.tmp
- mv u-boot.tmp $@
+IFDTOOL=$(objtree)/tools/ifdtool
+IFDTOOL_FLAGS = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin
+IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
+
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+IFDTOOL_ME_FLAGS = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
+IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
+endif
+
+ifneq ($(CONFIG_HAVE_MRC),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
+endif
+
+ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME)
+endif
+
+quiet_cmd_ifdtool = IFDTOOL $@
+cmd_ifdtool = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
+endif
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
+cmd_ifdtool += mv u-boot.tmp $@
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin
+ $(call if_changed,ifdtool)
OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
u-boot-x86-16bit.bin: u-boot FORCE
/* Freeze channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset = (u32)(
- &freeze_controller_base->vioctrl +
- (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+ &freeze_controller_base->vioctrl + channel_id);
/*
* Assert active low enrnsl, plniotri
/* Thaw channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset
- = (u32)(&freeze_controller_base->vioctrl
- + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+ = (u32)(&freeze_controller_base->vioctrl + channel_id);
/*
* Assert active low bhniotri signal and
{
const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+ clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
+ (1 << RSTMGR_PERMODRST_SPIM1_LSB));
}
config TARGET_JETSON_TK1
bool "NVIDIA Tegra124 Jetson TK1 board"
+config TARGET_NYAN_BIG
+ bool "Google/NVIDIA Nyan-big Chrombook"
+ help
+ Nyan Big is a Tegra124 clamshell board that is very similar
+ to venice2, but it has a different panel, the sdcard CD and WP
+ sense are flipped, and it has a different revision of the AS3722
+ PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN
+ (13.3-inch HD, NVIDIA Tegra K1, 2GB).
+
config TARGET_VENICE2
bool "NVIDIA Tegra124 Venice2"
default "tegra124"
source "board/nvidia/jetson-tk1/Kconfig"
+source "board/nvidia/nyan-big/Kconfig"
source "board/nvidia/venice2/Kconfig"
endif
*/
#include <common.h>
+#include <i2c.h>
#include <tps6586x.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#define VDD_TRANSITION_STEP 0x06 /* 150mv */
#define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
+#define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
+
int pmu_set_nominal(void)
{
- int core, cpu, bus;
+ struct udevice *bus, *dev;
+ int core, cpu;
+ int ret;
/* by default, the table has been filled with T25 settings */
switch (tegra_get_chip_sku()) {
return -1;
}
- bus = tegra_i2c_get_dvc_bus_num();
- if (bus == -1) {
+ ret = tegra_i2c_get_dvc_bus(&bus);
+ if (ret) {
debug("%s: Cannot find DVC I2C bus\n", __func__);
- return -1;
+ return ret;
}
- tps6586x_init(bus);
+ ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find DVC I2C chip\n", __func__);
+ return ret;
+ }
+
+ tps6586x_init(dev);
tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
VDD_TRANSITION_RATE, VDD_RELATION);
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
+ tegra124-nyan-big.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
--- /dev/null
+/*
+ * Keyboard dts fragment for devices that use cros-ec-keyboard
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <dt-bindings/input/input.h>
+
+&cros_ec {
+ keyboard-controller {
+ compatible = "google,cros-ec-keyb";
+ keypad,num-rows = <8>;
+ keypad,num-columns = <13>;
+ google,needs-ghost-filter;
+
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
+ MATRIX_KEY(0x00, 0x02, KEY_F1)
+ MATRIX_KEY(0x00, 0x03, KEY_B)
+ MATRIX_KEY(0x00, 0x04, KEY_F10)
+ MATRIX_KEY(0x00, 0x06, KEY_N)
+ MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
+ MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
+
+ MATRIX_KEY(0x01, 0x01, KEY_ESC)
+ MATRIX_KEY(0x01, 0x02, KEY_F4)
+ MATRIX_KEY(0x01, 0x03, KEY_G)
+ MATRIX_KEY(0x01, 0x04, KEY_F7)
+ MATRIX_KEY(0x01, 0x06, KEY_H)
+ MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
+ MATRIX_KEY(0x01, 0x09, KEY_F9)
+ MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
+
+ MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
+ MATRIX_KEY(0x02, 0x01, KEY_TAB)
+ MATRIX_KEY(0x02, 0x02, KEY_F3)
+ MATRIX_KEY(0x02, 0x03, KEY_T)
+ MATRIX_KEY(0x02, 0x04, KEY_F6)
+ MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
+ MATRIX_KEY(0x02, 0x06, KEY_Y)
+ MATRIX_KEY(0x02, 0x07, KEY_102ND)
+ MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
+ MATRIX_KEY(0x02, 0x09, KEY_F8)
+
+ MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
+ MATRIX_KEY(0x03, 0x02, KEY_F2)
+ MATRIX_KEY(0x03, 0x03, KEY_5)
+ MATRIX_KEY(0x03, 0x04, KEY_F5)
+ MATRIX_KEY(0x03, 0x06, KEY_6)
+ MATRIX_KEY(0x03, 0x08, KEY_MINUS)
+ MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
+
+ MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
+ MATRIX_KEY(0x04, 0x01, KEY_A)
+ MATRIX_KEY(0x04, 0x02, KEY_D)
+ MATRIX_KEY(0x04, 0x03, KEY_F)
+ MATRIX_KEY(0x04, 0x04, KEY_S)
+ MATRIX_KEY(0x04, 0x05, KEY_K)
+ MATRIX_KEY(0x04, 0x06, KEY_J)
+ MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
+ MATRIX_KEY(0x04, 0x09, KEY_L)
+ MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
+ MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
+
+ MATRIX_KEY(0x05, 0x01, KEY_Z)
+ MATRIX_KEY(0x05, 0x02, KEY_C)
+ MATRIX_KEY(0x05, 0x03, KEY_V)
+ MATRIX_KEY(0x05, 0x04, KEY_X)
+ MATRIX_KEY(0x05, 0x05, KEY_COMMA)
+ MATRIX_KEY(0x05, 0x06, KEY_M)
+ MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
+ MATRIX_KEY(0x05, 0x08, KEY_SLASH)
+ MATRIX_KEY(0x05, 0x09, KEY_DOT)
+ MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
+
+ MATRIX_KEY(0x06, 0x01, KEY_1)
+ MATRIX_KEY(0x06, 0x02, KEY_3)
+ MATRIX_KEY(0x06, 0x03, KEY_4)
+ MATRIX_KEY(0x06, 0x04, KEY_2)
+ MATRIX_KEY(0x06, 0x05, KEY_8)
+ MATRIX_KEY(0x06, 0x06, KEY_7)
+ MATRIX_KEY(0x06, 0x08, KEY_0)
+ MATRIX_KEY(0x06, 0x09, KEY_9)
+ MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
+ MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
+ MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
+
+ MATRIX_KEY(0x07, 0x01, KEY_Q)
+ MATRIX_KEY(0x07, 0x02, KEY_E)
+ MATRIX_KEY(0x07, 0x03, KEY_R)
+ MATRIX_KEY(0x07, 0x04, KEY_W)
+ MATRIX_KEY(0x07, 0x05, KEY_I)
+ MATRIX_KEY(0x07, 0x06, KEY_U)
+ MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
+ MATRIX_KEY(0x07, 0x08, KEY_P)
+ MATRIX_KEY(0x07, 0x09, KEY_O)
+ MATRIX_KEY(0x07, 0x0b, KEY_UP)
+ MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
+ >;
+ };
+};
/*
* Copyright (C) 2012 Altera <www.altera.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "skeleton.dtsi"
clock-names = "biu", "ciu";
};
+ qspi: spi@ff705000 {
+ compatible = "cadence,qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ ext-decoder = <0>; /* external decoder */
+ num-chipselect = <4>;
+ fifo-depth = <128>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
+ spi0: spi@fff00000 {
+ compatible = "snps,dw-spi-mmio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 154 4>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ tx-dma-channel = <&pdma 16>;
+ rx-dma-channel = <&pdma 17>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
+ spi1: spi@fff01000 {
+ compatible = "snps,dw-spi-mmio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff01000 0x1000>;
+ interrupts = <0 156 4>;
+ num-chipselect = <4>;
+ bus-num = <1>;
+ tx-dma-channel = <&pdma 20>;
+ rx-dma-channel = <&pdma 21>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/*
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "socfpga_cyclone5.dtsi"
bootargs = "console=ttyS0,115200";
};
+ aliases {
+ spi0 = "/spi@ff705000"; /* QSPI */
+ spi1 = "/spi@fff00000";
+ spi2 = "/spi@fff01000";
+ };
+
memory {
name = "memory";
device_type = "memory";
&mmc {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
- i2c5 = "/i2c@7000d100";
sdhci0 = "/sdhci@700b0600";
sdhci1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
--- /dev/null
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+ model = "Acer Chromebook 13 CB5-311";
+ compatible = "google,nyan-big", "nvidia,tegra124";
+
+ aliases {
+ console = &uarta;
+ i2c0 = "/i2c@7000d000";
+ i2c1 = "/i2c@7000c000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ i2c5 = "/i2c@7000d100";
+ rtc0 = "/i2c@0,7000d000/pmic@40";
+ rtc1 = "/rtc@0,7000e000";
+ sdhci0 = "/sdhci@700b0600";
+ sdhci1 = "/sdhci@700b0400";
+ spi0 = "/spi@7000d400";
+ spi1 = "/spi@7000da00";
+ usb0 = "/usb@7d000000";
+ usb1 = "/usb@7d008000";
+ };
+
+ memory {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ serial@70006000 {
+ /* Debug connector on the bottom of the board near SD card. */
+ status = "okay";
+ };
+
+ pwm@7000a000 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ acodec: audio-codec@10 {
+ compatible = "maxim,max98090";
+ reg = <0x10>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tpm@20 {
+ compatible = "infineon,slb9645tt";
+ reg = <0x20>;
+ };
+ };
+
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: pmic@40 {
+ compatible = "ams,as3722";
+ reg = <0x40>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ ams,system-power-controller;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&as3722_default>;
+
+ as3722_default: pinmux {
+ gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ gpio1 {
+ pins = "gpio1";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio2_4_7 {
+ pins = "gpio2", "gpio4", "gpio7";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio3_6 {
+ pins = "gpio3", "gpio6";
+ bias-high-impedance;
+ };
+
+ gpio5 {
+ pins = "gpio5";
+ function = "clk32k-out";
+ bias-pull-down;
+ };
+ };
+ };
+ };
+
+ spi@7000d400 {
+ status = "okay";
+
+ cros_ec: cros-ec@0 {
+ compatible = "google,cros-ec-spi";
+ spi-max-frequency = <3000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+ reg = <0>;
+
+ google,cros-ec-spi-msg-delay = <2000>;
+
+ i2c-tunnel {
+ compatible = "google,cros-ec-i2c-tunnel";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ google,remote-bus = <0>;
+
+ charger: bq24735@9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(J, 0)
+ GPIO_ACTIVE_HIGH>;
+ ti,ac-detect-gpios = <&gpio
+ TEGRA_GPIO(J, 0)
+ GPIO_ACTIVE_HIGH>;
+ };
+
+ battery: sbs-battery@b {
+ compatible = "sbs,sbs-battery";
+ reg = <0xb>;
+ sbs,i2c-retry-count = <2>;
+ sbs,poll-retry-count = <10>;
+ power-supplies = <&charger>;
+ };
+ };
+ };
+ };
+
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ flash@0 {
+ compatible = "winbond,w25q32dw";
+ reg = <0>;
+ };
+ };
+
+ pmc@7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <0>;
+ nvidia,cpu-pwr-good-time = <500>;
+ nvidia,cpu-pwr-off-time = <300>;
+ nvidia,core-pwr-good-time = <641 3845>;
+ nvidia,core-pwr-off-time = <61036>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+ };
+
+ hda@70030000 {
+ status = "okay";
+ };
+
+ sdhci@700b0000 { /* WiFi/BT on this bus */
+ status = "okay";
+ power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ };
+
+ sdhci@700b0400 { /* SD Card on this bus */
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ no-1-8-v;
+ };
+
+ sdhci@700b0600 { /* eMMC on this bus */
+ status = "okay";
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ };
+
+ ahub@70300000 {
+ i2s@70301100 {
+ status = "okay";
+ };
+ };
+
+ usb@7d000000 { /* Rear external USB port. */
+ status = "okay";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ };
+
+ usb@7d004000 { /* Internal webcam. */
+ status = "okay";
+ };
+
+ usb-phy@7d004000 {
+ status = "okay";
+ };
+
+ usb@7d008000 { /* Left external USB port. */
+ status = "okay";
+ };
+
+ usb-phy@7d008000 {
+ status = "okay";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm 1 1000000>;
+
+ default-brightness-level = <224>;
+ brightness-levels =
+ < 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31
+ 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255
+ 256>;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ lid {
+ label = "Lid";
+ gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+ linux,input-type = <5>;
+ linux,code = <KEY_RESERVED>;
+ debounce-interval = <1>;
+ gpio-key,wakeup;
+ };
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <30>;
+ gpio-key,wakeup;
+ };
+ };
+
+ panel: panel {
+ compatible = "auo,b133xtn01";
+
+ backlight = <&backlight>;
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-max98090-nyan-big",
+ "nvidia,tegra-audio-max98090";
+ nvidia,model = "Acer Chromebook 13";
+
+ nvidia,audio-routing =
+ "Headphones", "HPR",
+ "Headphones", "HPL",
+ "Speakers", "SPKR",
+ "Speakers", "SPKL",
+ "Mic Jack", "MICBIAS",
+ "DMICL", "Int Mic",
+ "DMICR", "Int Mic",
+ "IN34", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&acodec>;
+
+ clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+ <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
+ };
+};
+
+#include "cros-ec-keyboard.dtsi"
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
status = "disabled";
};
+ pwm: pwm@7000a000 {
+ compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
+ clocks = <&tegra_car TEGRA124_CLK_PWM>;
+ resets = <&tegra_car 17>;
+ reset-names = "pwm";
+ status = "disabled";
+ };
+
spi@7000d400 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>;
status = "disabled";
};
+ ahub@70300000 {
+ compatible = "nvidia,tegra124-ahub";
+ reg = <0x70300000 0x200>,
+ <0x70300800 0x800>,
+ <0x70300200 0x600>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
+ <&tegra_car TEGRA124_CLK_APBIF>;
+ clock-names = "d_audio", "apbif";
+ resets = <&tegra_car 106>, /* d_audio */
+ <&tegra_car 107>, /* apbif */
+ <&tegra_car 30>, /* i2s0 */
+ <&tegra_car 11>, /* i2s1 */
+ <&tegra_car 18>, /* i2s2 */
+ <&tegra_car 101>, /* i2s3 */
+ <&tegra_car 102>, /* i2s4 */
+ <&tegra_car 108>, /* dam0 */
+ <&tegra_car 109>, /* dam1 */
+ <&tegra_car 110>, /* dam2 */
+ <&tegra_car 10>, /* spdif */
+ <&tegra_car 153>, /* amx */
+ <&tegra_car 185>, /* amx1 */
+ <&tegra_car 154>, /* adx */
+ <&tegra_car 180>, /* adx1 */
+ <&tegra_car 186>, /* afc0 */
+ <&tegra_car 187>, /* afc1 */
+ <&tegra_car 188>, /* afc2 */
+ <&tegra_car 189>, /* afc3 */
+ <&tegra_car 190>, /* afc4 */
+ <&tegra_car 191>; /* afc5 */
+ reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+ "i2s3", "i2s4", "dam0", "dam1", "dam2",
+ "spdif", "amx", "amx1", "adx", "adx1",
+ "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
+ dmas = <&apbdma 1>, <&apbdma 1>,
+ <&apbdma 2>, <&apbdma 2>,
+ <&apbdma 3>, <&apbdma 3>,
+ <&apbdma 4>, <&apbdma 4>,
+ <&apbdma 6>, <&apbdma 6>,
+ <&apbdma 7>, <&apbdma 7>,
+ <&apbdma 12>, <&apbdma 12>,
+ <&apbdma 13>, <&apbdma 13>,
+ <&apbdma 14>, <&apbdma 14>,
+ <&apbdma 29>, <&apbdma 29>;
+ dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+ "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+ "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+ "rx9", "tx9";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tegra_i2s0: i2s@70301000 {
+ compatible = "nvidia,tegra124-i2s";
+ reg = <0x70301000 0x100>;
+ nvidia,ahub-cif-ids = <4 4>;
+ clocks = <&tegra_car TEGRA124_CLK_I2S0>;
+ resets = <&tegra_car 30>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s1: i2s@70301100 {
+ compatible = "nvidia,tegra124-i2s";
+ reg = <0x70301100 0x100>;
+ nvidia,ahub-cif-ids = <5 5>;
+ clocks = <&tegra_car TEGRA124_CLK_I2S1>;
+ resets = <&tegra_car 11>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s2: i2s@70301200 {
+ compatible = "nvidia,tegra124-i2s";
+ reg = <0x70301200 0x100>;
+ nvidia,ahub-cif-ids = <6 6>;
+ clocks = <&tegra_car TEGRA124_CLK_I2S2>;
+ resets = <&tegra_car 18>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s3: i2s@70301300 {
+ compatible = "nvidia,tegra124-i2s";
+ reg = <0x70301300 0x100>;
+ nvidia,ahub-cif-ids = <7 7>;
+ clocks = <&tegra_car TEGRA124_CLK_I2S3>;
+ resets = <&tegra_car 101>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s4: i2s@70301400 {
+ compatible = "nvidia,tegra124-i2s";
+ reg = <0x70301400 0x100>;
+ nvidia,ahub-cif-ids = <8 8>;
+ clocks = <&tegra_car TEGRA124_CLK_I2S4>;
+ resets = <&tegra_car 102>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+ };
+
usb@7d000000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x7d000000 0x4000>;
model = "Avionic Design Tamonten™ NG Evaluation Carrier";
compatible = "ad,tec-ng", "nvidia,tegra30";
+ aliases {
+ i2c0 = "/i2c@7000c400";
+ };
+
/* GEN2 */
i2c@7000c400 {
status = "okay";
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
#endif
typedef struct {
#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
-#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
void sys_mgr_frzctrl_freeze_req(void);
void sys_mgr_frzctrl_thaw_req(void);
u32 padding[2];
u32 fifo_single_byte;
u32 fifo_double_byte;
+ u32 fifo_triple_byte;
u32 fifo_quad_byte;
};
*
* @return number of bus, or -1 if there is no DVC active
*/
-int tegra_i2c_get_dvc_bus_num(void);
+int tegra_i2c_get_dvc_bus(struct udevice **busp);
#endif /* _TEGRA_I2C_H_ */
num-gpios = <20>;
};
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ compatible = "sandbox,i2c";
+ clock-frequency = <400000>;
+ eeprom@2c {
+ reg = <0x2c>;
+ compatible = "i2c-eeprom";
+ emul {
+ compatible = "sandbox,i2c-eeprom";
+ sandbox,filename = "i2c.bin";
+ sandbox,size = <128>;
+ };
+ };
+ };
+
spi@0 {
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+/*
+ * Test-related constants for sandbox
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_TEST_H
+#define __ASM_TEST_H
+
+/* The sandbox driver always permits an I2C device with this address */
+#define SANDBOX_I2C_TEST_ADDR 0x59
+
+enum sandbox_i2c_eeprom_test_mode {
+ SIE_TEST_MODE_NONE,
+ /* Permits read/write of only one byte per I2C transaction */
+ SIE_TEST_MODE_SINGLE_BYTE,
+};
+
+void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
+ enum sandbox_i2c_eeprom_test_mode mode);
+
+void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
+
+#endif
config SMM_TSEG_SIZE
hex
+config BOARD_ROMSIZE_KB_512
+ bool
+config BOARD_ROMSIZE_KB_1024
+ bool
+config BOARD_ROMSIZE_KB_2048
+ bool
+config BOARD_ROMSIZE_KB_4096
+ bool
+config BOARD_ROMSIZE_KB_8192
+ bool
+config BOARD_ROMSIZE_KB_16384
+ bool
+
+choice
+ prompt "ROM chip size"
+ default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
+ default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
+ default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
+ default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
+ default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
+ default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
+ help
+ Select the size of the ROM chip you intend to flash U-Boot on.
+
+ The build system will take care of creating a u-boot.rom file
+ of the matching size.
+
+config UBOOT_ROMSIZE_KB_512
+ bool "512 KB"
+ help
+ Choose this option if you have a 512 KB ROM chip.
+
+config UBOOT_ROMSIZE_KB_1024
+ bool "1024 KB (1 MB)"
+ help
+ Choose this option if you have a 1024 KB (1 MB) ROM chip.
+
+config UBOOT_ROMSIZE_KB_2048
+ bool "2048 KB (2 MB)"
+ help
+ Choose this option if you have a 2048 KB (2 MB) ROM chip.
+
+config UBOOT_ROMSIZE_KB_4096
+ bool "4096 KB (4 MB)"
+ help
+ Choose this option if you have a 4096 KB (4 MB) ROM chip.
+
+config UBOOT_ROMSIZE_KB_8192
+ bool "8192 KB (8 MB)"
+ help
+ Choose this option if you have a 8192 KB (8 MB) ROM chip.
+
+config UBOOT_ROMSIZE_KB_16384
+ bool "16384 KB (16 MB)"
+ help
+ Choose this option if you have a 16384 KB (16 MB) ROM chip.
+
+endchoice
+
+# Map the config names to an integer (KB).
+config UBOOT_ROMSIZE_KB
+ int
+ default 512 if UBOOT_ROMSIZE_KB_512
+ default 1024 if UBOOT_ROMSIZE_KB_1024
+ default 2048 if UBOOT_ROMSIZE_KB_2048
+ default 4096 if UBOOT_ROMSIZE_KB_4096
+ default 8192 if UBOOT_ROMSIZE_KB_8192
+ default 16384 if UBOOT_ROMSIZE_KB_16384
+
+# Map the config names to a hex value (bytes).
config ROM_SIZE
hex
- default 0x800000
+ default 0x80000 if UBOOT_ROMSIZE_KB_512
+ default 0x100000 if UBOOT_ROMSIZE_KB_1024
+ default 0x200000 if UBOOT_ROMSIZE_KB_2048
+ default 0x400000 if UBOOT_ROMSIZE_KB_4096
+ default 0x800000 if UBOOT_ROMSIZE_KB_8192
+ default 0xc00000 if UBOOT_ROMSIZE_KB_12288
+ default 0x1000000 if UBOOT_ROMSIZE_KB_16384
config HAVE_INTEL_ME
bool "Platform requires Intel Management Engine"
static int report_bist_failure(void)
{
if (gd->arch.bist != 0) {
+ post_code(POST_BIST_FAILURE);
printf("BIST failed: %08x\n", gd->arch.bist);
return -EFAULT;
}
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/fsp_support.h>
+
+void update_fsp_upd(struct upd_region_t *fsp_upd)
+{
+ /* Override any UPD setting if required */
+
+ /* Uncomment the line below to enable DEBUG message */
+ /* fsp_upd->serial_dbgport_type = 1; */
+
+ /* Examples on how to initialize the pointers in UPD region */
+ /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */
+}
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/fsp_support.h>
+#include <asm/post.h>
+
+/**
+ * Reads a 64-bit value from memory that may be unaligned.
+ *
+ * This function returns the 64-bit value pointed to by buf. The function
+ * guarantees that the read operation does not produce an alignment fault.
+ *
+ * If the buf is NULL, then ASSERT().
+ *
+ * @buf: Pointer to a 64-bit value that may be unaligned.
+ *
+ * @return: The 64-bit value read from buf.
+ */
+static u64 read_unaligned64(const u64 *buf)
+{
+ ASSERT(buf != NULL);
+
+ return *buf;
+}
+
+/**
+ * Compares two GUIDs
+ *
+ * If the GUIDs are identical then TRUE is returned.
+ * If there are any bit differences in the two GUIDs, then FALSE is returned.
+ *
+ * If guid1 is NULL, then ASSERT().
+ * If guid2 is NULL, then ASSERT().
+ *
+ * @guid1: A pointer to a 128 bit GUID.
+ * @guid2: A pointer to a 128 bit GUID.
+ *
+ * @retval TRUE: guid1 and guid2 are identical.
+ * @retval FALSE: guid1 and guid2 are not identical.
+ */
+static unsigned char compare_guid(const struct efi_guid_t *guid1,
+ const struct efi_guid_t *guid2)
+{
+ u64 guid1_low;
+ u64 guid2_low;
+ u64 guid1_high;
+ u64 guid2_high;
+
+ guid1_low = read_unaligned64((const u64 *)guid1);
+ guid2_low = read_unaligned64((const u64 *)guid2);
+ guid1_high = read_unaligned64((const u64 *)guid1 + 1);
+ guid2_high = read_unaligned64((const u64 *)guid2 + 1);
+
+ return (unsigned char)(guid1_low == guid2_low && guid1_high == guid2_high);
+}
+
+u32 __attribute__((optimize("O0"))) find_fsp_header(void)
+{
+ volatile register u8 *fsp asm("eax");
+
+ /* Initalize the FSP base */
+ fsp = (u8 *)CONFIG_FSP_LOCATION;
+
+ /* Check the FV signature, _FVH */
+ if (((struct fv_header_t *)fsp)->sign == 0x4856465F) {
+ /* Go to the end of the FV header and align the address */
+ fsp += ((struct fv_header_t *)fsp)->ext_hdr_off;
+ fsp += ((struct fv_ext_header_t *)fsp)->ext_hdr_size;
+ fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8);
+ } else {
+ fsp = 0;
+ }
+
+ /* Check the FFS GUID */
+ if (fsp &&
+ (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[0] == 0x912740BE) &&
+ (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[1] == 0x47342284) &&
+ (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[2] == 0xB08471B9) &&
+ (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[3] == 0x0C3F3527)) {
+ /* Add the FFS header size to find the raw section header */
+ fsp += sizeof(struct ffs_file_header_t);
+ } else {
+ fsp = 0;
+ }
+
+ if (fsp &&
+ ((struct raw_section_t *)fsp)->type == EFI_SECTION_RAW) {
+ /* Add the raw section header size to find the FSP header */
+ fsp += sizeof(struct raw_section_t);
+ } else {
+ fsp = 0;
+ }
+
+ return (u32)fsp;
+}
+
+void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list)
+{
+ u32 stack_len;
+ u32 stack_base;
+ u32 stack_top;
+
+ post_code(POST_MRC);
+
+ ASSERT(status == 0);
+
+ /* Get the migrated stack in normal memory */
+ stack_base = (u32)get_bootloader_tmp_mem(hob_list, &stack_len);
+ ASSERT(stack_base != 0);
+ stack_top = stack_base + stack_len - sizeof(u32);
+
+ /*
+ * Old stack base is stored at the very end of the stack top,
+ * use it to calculate the migrated shared data base
+ */
+ shared_data = (struct shared_data_t *)(stack_base +
+ ((u32)shared_data - *(u32 *)stack_top));
+
+ /* The boot loader main function entry */
+ fsp_init_done(hob_list);
+}
+
+void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
+{
+ struct shared_data_t shared_data;
+ fsp_init_f init;
+ struct fsp_init_params_t params;
+ struct fspinit_rtbuf_t rt_buf;
+ struct vpd_region_t *fsp_vpd;
+ struct fsp_header_t *fsp_hdr;
+ struct fsp_init_params_t *params_ptr;
+ struct upd_region_t *fsp_upd;
+
+ fsp_hdr = (struct fsp_header_t *)find_fsp_header();
+ if (fsp_hdr == NULL) {
+ /* No valid FSP info header was found */
+ ASSERT(FALSE);
+ }
+
+ fsp_upd = (struct upd_region_t *)&shared_data.fsp_upd;
+ memset((void *)&rt_buf, 0, sizeof(struct fspinit_rtbuf_t));
+
+ /* Reserve a gap in stack top */
+ rt_buf.common.stack_top = (u32 *)stack_top - 32;
+ rt_buf.common.boot_mode = boot_mode;
+ rt_buf.common.upd_data = (struct upd_region_t *)fsp_upd;
+
+ /* Get VPD region start */
+ fsp_vpd = (struct vpd_region_t *)(fsp_hdr->img_base +
+ fsp_hdr->cfg_region_off);
+
+ /* Verifify the VPD data region is valid */
+ ASSERT((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
+ (fsp_vpd->sign == VPD_IMAGE_ID));
+
+ /* Copy default data from Flash */
+ memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
+ sizeof(struct upd_region_t));
+
+ /* Verifify the UPD data region is valid */
+ ASSERT(fsp_upd->terminator == 0x55AA);
+
+ /* Override any UPD setting if required */
+ update_fsp_upd(fsp_upd);
+
+ memset((void *)¶ms, 0, sizeof(struct fsp_init_params_t));
+ params.nvs_buf = nvs_buf;
+ params.rt_buf = (struct fspinit_rtbuf_t *)&rt_buf;
+ params.continuation = (fsp_continuation_f)asm_continuation;
+
+ init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
+ params_ptr = ¶ms;
+
+ shared_data.fsp_hdr = fsp_hdr;
+ shared_data.stack_top = (u32 *)stack_top;
+
+ post_code(POST_PRE_MRC);
+
+ /*
+ * Use ASM code to ensure the register value in EAX & ECX
+ * will be passed into BlContinuationFunc
+ */
+ asm volatile (
+ "pushl %0;"
+ "call *%%eax;"
+ ".global asm_continuation;"
+ "asm_continuation:;"
+ "movl %%ebx, %%eax;" /* shared_data */
+ "movl 4(%%esp), %%edx;" /* status */
+ "movl 8(%%esp), %%ecx;" /* hob_list */
+ "jmp fsp_continue;"
+ : : "m"(params_ptr), "a"(init), "b"(&shared_data)
+ );
+
+ /*
+ * Should never get here.
+ * Control will continue from romstage_main_continue_asm.
+ * This line below is to prevent the compiler from optimizing
+ * structure intialization.
+ */
+ init(¶ms);
+
+ /*
+ * Should never return.
+ * Control will continue from ContinuationFunc
+ */
+ ASSERT(FALSE);
+}
+
+u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase)
+{
+ fsp_notify_f notify;
+ struct fsp_notify_params_t params;
+ struct fsp_notify_params_t *params_ptr;
+ u32 status;
+
+ if (!fsp_hdr)
+ fsp_hdr = (struct fsp_header_t *)find_fsp_header();
+
+ if (fsp_hdr == NULL) {
+ /* No valid FSP info header */
+ ASSERT(FALSE);
+ }
+
+ notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
+ params.phase = phase;
+ params_ptr = ¶ms;
+
+ /*
+ * Use ASM code to ensure correct parameter is on the stack for
+ * FspNotify as U-Boot is using different ABI from FSP
+ */
+ asm volatile (
+ "pushl %1;" /* push notify phase */
+ "call *%%eax;" /* call FspNotify */
+ "addl $4, %%esp;" /* clean up the stack */
+ : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr)
+ );
+
+ return status;
+}
+
+u32 get_usable_lowmem_top(const void *hob_list)
+{
+ union hob_pointers_t hob;
+ phys_addr_t phys_start;
+ u32 top;
+
+ /* Get the HOB list for processing */
+ hob.raw = (void *)hob_list;
+
+ /* * Collect memory ranges */
+ top = 0x100000;
+ while (!END_OF_HOB(hob)) {
+ if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+ if (hob.res_desc->type == RES_SYS_MEM) {
+ phys_start = hob.res_desc->phys_start;
+ /* Need memory above 1MB to be collected here */
+ if (phys_start >= 0x100000 &&
+ phys_start < (phys_addr_t)0x100000000)
+ top += (u32)(hob.res_desc->len);
+ }
+ }
+ hob.raw = GET_NEXT_HOB(hob);
+ }
+
+ return top;
+}
+
+u64 get_usable_highmem_top(const void *hob_list)
+{
+ union hob_pointers_t hob;
+ phys_addr_t phys_start;
+ u64 top;
+
+ /* Get the HOB list for processing */
+ hob.raw = (void *)hob_list;
+
+ /* Collect memory ranges */
+ top = 0x100000000;
+ while (!END_OF_HOB(hob)) {
+ if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+ if (hob.res_desc->type == RES_SYS_MEM) {
+ phys_start = hob.res_desc->phys_start;
+ /* Need memory above 1MB to be collected here */
+ if (phys_start >= (phys_addr_t)0x100000000)
+ top += (u32)(hob.res_desc->len);
+ }
+ }
+ hob.raw = GET_NEXT_HOB(hob);
+ }
+
+ return top;
+}
+
+u64 get_fsp_reserved_mem_from_guid(const void *hob_list, u64 *len,
+ struct efi_guid_t *guid)
+{
+ union hob_pointers_t hob;
+
+ /* Get the HOB list for processing */
+ hob.raw = (void *)hob_list;
+
+ /* Collect memory ranges */
+ while (!END_OF_HOB(hob)) {
+ if (hob.hdr->type == HOB_TYPE_RES_DESC) {
+ if (hob.res_desc->type == RES_MEM_RESERVED) {
+ if (compare_guid(&hob.res_desc->owner, guid)) {
+ if (len)
+ *len = (u32)(hob.res_desc->len);
+
+ return (u64)(hob.res_desc->phys_start);
+ }
+ }
+ }
+ hob.raw = GET_NEXT_HOB(hob);
+ }
+
+ return 0;
+}
+
+u32 get_fsp_reserved_mem(const void *hob_list, u32 *len)
+{
+ const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
+ u64 length;
+ u32 base;
+
+ base = (u32)get_fsp_reserved_mem_from_guid(hob_list,
+ &length, (struct efi_guid_t *)&guid);
+ if ((len != 0) && (base != 0))
+ *len = (u32)length;
+
+ return base;
+}
+
+u32 get_tseg_reserved_mem(const void *hob_list, u32 *len)
+{
+ const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
+ u64 length;
+ u32 base;
+
+ base = (u32)get_fsp_reserved_mem_from_guid(hob_list,
+ &length, (struct efi_guid_t *)&guid);
+ if ((len != 0) && (base != 0))
+ *len = (u32)length;
+
+ return base;
+}
+
+void *get_next_hob(u16 type, const void *hob_list)
+{
+ union hob_pointers_t hob;
+
+ ASSERT(hob_list != NULL);
+
+ hob.raw = (u8 *)hob_list;
+
+ /* Parse the HOB list until end of list or matching type is found */
+ while (!END_OF_HOB(hob)) {
+ if (hob.hdr->type == type)
+ return hob.raw;
+
+ hob.raw = GET_NEXT_HOB(hob);
+ }
+
+ return NULL;
+}
+
+void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list)
+{
+ union hob_pointers_t hob;
+
+ hob.raw = (u8 *)hob_list;
+ while ((hob.raw = get_next_hob(HOB_TYPE_GUID_EXT,
+ hob.raw)) != NULL) {
+ if (compare_guid(guid, &hob.guid->name))
+ break;
+ hob.raw = GET_NEXT_HOB(hob);
+ }
+
+ return hob.raw;
+}
+
+void *get_guid_hob_data(const void *hob_list, u32 *len, struct efi_guid_t *guid)
+{
+ u8 *guid_hob;
+
+ guid_hob = get_next_guid_hob(guid, hob_list);
+ if (guid_hob == NULL) {
+ return NULL;
+ } else {
+ if (len)
+ *len = GET_GUID_HOB_DATA_SIZE(guid_hob);
+
+ return GET_GUID_HOB_DATA(guid_hob);
+ }
+}
+
+void *get_fsp_nvs_data(const void *hob_list, u32 *len)
+{
+ const struct efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+
+ return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid);
+}
+
+void *get_bootloader_tmp_mem(const void *hob_list, u32 *len)
+{
+ const struct efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
+
+ return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid);
+}
/*
- * U-boot - x86 Startup Code
+ * U-Boot - x86 Startup Code
*
* (C) Copyright 2008-2011
* Graeme Russ, <graeme.russ@gmail.com>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <generated/generic-asm-offsets.h>
+#include <generated/asm-offsets.h>
.section .text
.code32
jmp car_init
.globl car_init_ret
car_init_ret:
+#ifndef CONFIG_HAVE_FSP
/*
* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
* or fully initialised SDRAM - we really don't care which)
#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
#endif
+#else
+ /*
+ * When we get here after car_init, esp points to a temporary stack
+ * and esi holds the HOB list address returned by the FSP.
+ */
+#endif
/* Reserve space on stack for global data */
subl $GENERATED_GBL_DATA_SIZE, %esp
movl %esp, %edi
rep stosb
+#ifdef CONFIG_HAVE_FSP
+ /* Store HOB list */
+ movl %esp, %edx
+ addl $GD_HOB_LIST, %edx
+ movl %esi, (%edx)
+#endif
+
/* Setup first parameter to setup_gdt, pointer to global_data */
movl %esp, %eax
dtb-y += link.dtb \
chromebook_link.dtb \
- alex.dtb
+ alex.dtb \
+ crownbay.dtb
targets += $(dtb-y)
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "coreboot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Intel Crown Bay";
+ compatible = "intel,crownbay", "intel,queensbay";
+
+ config {
+ silent_console = <0>;
+ };
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+
+ serial {
+ reg = <0x3f8 8>;
+ clock-frequency = <115200>;
+ };
+
+ chosen { };
+ memory { device_type = "memory"; reg = <0 0>; };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich7";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "sst,25vf016b", "spi-flash";
+ memory-map = <0xffe00000 0x00200000>;
+ };
+ };
+};
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
#ifndef ASM_ARCH_PEI_DATA_H
#define ASM_ARCH_PEI_DATA_H
+#include <linux/linkage.h>
+
struct pch_usb3_controller_settings {
/* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
uint16_t mode;
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_API_H__
+#define __FSP_API_H__
+
+/*
+ * FspInit continuation function prototype.
+ * Control will be returned to this callback function after FspInit API call.
+ */
+typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
+
+#pragma pack(1)
+
+struct fsp_init_params_t {
+ /* Non-volatile storage buffer pointer */
+ void *nvs_buf;
+ /* Runtime buffer pointer */
+ void *rt_buf;
+ /* Continuation function address */
+ fsp_continuation_f continuation;
+};
+
+struct common_buf_t {
+ /*
+ * Stack top pointer used by the bootloader. The new stack frame will be
+ * set up at this location after FspInit API call.
+ */
+ u32 *stack_top;
+ u32 boot_mode; /* Current system boot mode */
+ void *upd_data; /* User platform configuraiton data region */
+ u32 reserved[7]; /* Reserved */
+};
+
+enum fsp_phase_t {
+ /* Notification code for post PCI enuermation */
+ INIT_PHASE_PCI = 0x20,
+ /* Notification code before transfering control to the payload */
+ INIT_PHASE_BOOT = 0x40
+};
+
+struct fsp_notify_params_t {
+ /* Notification phase used for NotifyPhase API */
+ enum fsp_phase_t phase;
+};
+
+#pragma pack()
+
+/* FspInit API function prototype */
+typedef u32 (*fsp_init_f)(struct fsp_init_params_t *param);
+
+/* FspNotify API function prototype */
+typedef u32 (*fsp_notify_f)(struct fsp_notify_params_t *param);
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_BOOT_MODE_H__
+#define __FSP_BOOT_MODE_H__
+
+/* 0x21 - 0xf..f are reserved */
+#define BOOT_FULL_CONFIG 0x00
+#define BOOT_MINIMAL_CONFIG 0x01
+#define BOOT_NO_CONFIG_CHANGES 0x02
+#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03
+#define BOOT_DEFAULT_SETTINGS 0x04
+#define BOOT_ON_S4_RESUME 0x05
+#define BOOT_ON_S5_RESUME 0x06
+#define BOOT_ON_S2_RESUME 0x10
+#define BOOT_ON_S3_RESUME 0x11
+#define BOOT_ON_FLASH_UPDATE 0x12
+#define BOOT_IN_RECOVERY_MODE 0x20
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_FFS_H__
+#define __FSP_FFS_H__
+
+#pragma pack(1)
+
+/* Used to verify the integrity of the file */
+union ffs_integrity_t {
+ struct {
+ /*
+ * The IntegrityCheck.checksum.header field is an 8-bit
+ * checksum of the file header. The State and
+ * IntegrityCheck.checksum.file fields are assumed to be zero
+ * and the checksum is calculated such that the entire header
+ * sums to zero.
+ */
+ u8 header;
+ /*
+ * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of
+ * the Attributes field is set to one, the
+ * IntegrityCheck.checksum.file field is an 8-bit checksum of
+ * the file data. If the FFS_ATTRIB_CHECKSUM bit of the
+ * Attributes field is cleared to zero, the
+ * IntegrityCheck.checksum.file field must be initialized with
+ * a value of 0xAA. The IntegrityCheck.checksum.file field is
+ * valid any time the EFI_FILE_DATA_VALID bit is set in the
+ * State field.
+ */
+ u8 file;
+ } checksum;
+
+ /* This is the full 16 bits of the IntegrityCheck field */
+ u16 checksum16;
+};
+
+/*
+ * Each file begins with the header that describe the
+ * contents and state of the files.
+ */
+struct ffs_file_header_t {
+ /*
+ * This GUID is the file name.
+ * It is used to uniquely identify the file.
+ */
+ struct efi_guid_t name;
+ /* Used to verify the integrity of the file */
+ union ffs_integrity_t integrity;
+ /* Identifies the type of file */
+ u8 type;
+ /* Declares various file attribute bits */
+ u8 attr;
+ /* The length of the file in bytes, including the FFS header */
+ u8 size[3];
+ /*
+ * Used to track the state of the file throughout the life of
+ * the file from creation to deletion.
+ */
+ u8 state;
+};
+
+struct ffs_file_header2_t {
+ /*
+ * This GUID is the file name. It is used to uniquely identify the file.
+ * There may be only one instance of a file with the file name GUID of
+ * Name in any given firmware volume, except if the file type is
+ * EFI_FV_FILE_TYPE_FFS_PAD.
+ */
+ struct efi_guid_t name;
+ /* Used to verify the integrity of the file */
+ union ffs_integrity_t integrity;
+ /* Identifies the type of file */
+ u8 type;
+ /* Declares various file attribute bits */
+ u8 attr;
+ /*
+ * The length of the file in bytes, including the FFS header.
+ * The length of the file data is either
+ * (size - sizeof(struct ffs_file_header_t)). This calculation means a
+ * zero-length file has a size of 24 bytes, which is
+ * sizeof(struct ffs_file_header_t). Size is not required to be a
+ * multiple of 8 bytes. Given a file F, the next file header is located
+ * at the next 8-byte aligned firmware volume offset following the last
+ * byte of the file F.
+ */
+ u8 size[3];
+ /*
+ * Used to track the state of the file throughout the life of
+ * the file from creation to deletion.
+ */
+ u8 state;
+ /*
+ * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
+ * and size must be set to zero.
+ * If FFS_ATTRIB_LARGE_FILE is not set then
+ * struct ffs_file_header_t is used.
+ */
+ u32 ext_size;
+};
+
+/*
+ * Pseudo type. It is used as a wild card when retrieving sections.
+ * The section type EFI_SECTION_ALL matches all section types.
+ */
+#define EFI_SECTION_ALL 0x00
+
+/* Encapsulation section Type values */
+#define EFI_SECTION_COMPRESSION 0x01
+#define EFI_SECTION_GUID_DEFINED 0x02
+#define EFI_SECTION_DISPOSABLE 0x03
+
+/* Leaf section Type values */
+#define EFI_SECTION_PE32 0x10
+#define EFI_SECTION_PIC 0x11
+#define EFI_SECTION_TE 0x12
+#define EFI_SECTION_DXE_DEPEX 0x13
+#define EFI_SECTION_VERSION 0x14
+#define EFI_SECTION_USER_INTERFACE 0x15
+#define EFI_SECTION_COMPATIBILITY16 0x16
+#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
+#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
+#define EFI_SECTION_RAW 0x19
+#define EFI_SECTION_PEI_DEPEX 0x1B
+#define EFI_SECTION_SMM_DEPEX 0x1C
+
+/* Common section header */
+struct raw_section_t {
+ /*
+ * A 24-bit unsigned integer that contains the total size of
+ * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
+ */
+ u8 size[3];
+ u8 type;
+};
+
+struct raw_section2_t {
+ /*
+ * A 24-bit unsigned integer that contains the total size of
+ * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
+ */
+ u8 size[3];
+ u8 type;
+ /*
+ * If size is 0xFFFFFF, then ext_size contains the size of
+ * the section. If size is not equal to 0xFFFFFF, then this
+ * field does not exist.
+ */
+ u32 ext_size;
+};
+
+#pragma pack()
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_FV___
+#define __FSP_FV___
+
+/* Value of EFI_FV_FILE_ATTRIBUTES */
+#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
+#define EFI_FV_FILE_ATTR_FIXED 0x00000100
+#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
+
+/* Attributes bit definitions */
+#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
+#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
+#define EFI_FVB2_READ_STATUS 0x00000004
+#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
+#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
+#define EFI_FVB2_WRITE_STATUS 0x00000020
+#define EFI_FVB2_LOCK_CAP 0x00000040
+#define EFI_FVB2_LOCK_STATUS 0x00000080
+#define EFI_FVB2_STICKY_WRITE 0x00000200
+#define EFI_FVB2_MEMORY_MAPPED 0x00000400
+#define EFI_FVB2_ERASE_POLARITY 0x00000800
+#define EFI_FVB2_READ_LOCK_CAP 0x00001000
+#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
+#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
+#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
+#define EFI_FVB2_ALIGNMENT 0x001F0000
+#define EFI_FVB2_ALIGNMENT_1 0x00000000
+#define EFI_FVB2_ALIGNMENT_2 0x00010000
+#define EFI_FVB2_ALIGNMENT_4 0x00020000
+#define EFI_FVB2_ALIGNMENT_8 0x00030000
+#define EFI_FVB2_ALIGNMENT_16 0x00040000
+#define EFI_FVB2_ALIGNMENT_32 0x00050000
+#define EFI_FVB2_ALIGNMENT_64 0x00060000
+#define EFI_FVB2_ALIGNMENT_128 0x00070000
+#define EFI_FVB2_ALIGNMENT_256 0x00080000
+#define EFI_FVB2_ALIGNMENT_512 0x00090000
+#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
+#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
+#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
+#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
+#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
+#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
+#define EFI_FVB2_ALIGNMENT_64K 0x00100000
+#define EFI_FVB2_ALIGNMENT_128K 0x00110000
+#define EFI_FVB2_ALIGNMENT_256K 0x00120000
+#define EFI_FVB2_ALIGNMENT_512K 0x00130000
+#define EFI_FVB2_ALIGNMENT_1M 0x00140000
+#define EFI_FVB2_ALIGNMENT_2M 0x00150000
+#define EFI_FVB2_ALIGNMENT_4M 0x00160000
+#define EFI_FVB2_ALIGNMENT_8M 0x00170000
+#define EFI_FVB2_ALIGNMENT_16M 0x00180000
+#define EFI_FVB2_ALIGNMENT_32M 0x00190000
+#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
+#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
+#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
+#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
+#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
+#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
+
+struct fv_blkmap_entry_t {
+ /* The number of sequential blocks which are of the same size */
+ u32 num_blocks;
+ /* The size of the blocks */
+ u32 length;
+};
+
+/* Describes the features and layout of the firmware volume */
+struct fv_header_t {
+ /*
+ * The first 16 bytes are reserved to allow for the reset vector of
+ * processors whose reset vector is at address 0.
+ */
+ u8 zero_vec[16];
+ /*
+ * Declares the file system with which the firmware volume
+ * is formatted.
+ */
+ struct efi_guid_t fs_guid;
+ /*
+ * Length in bytes of the complete firmware volume, including
+ * the header.
+ */
+ u64 fv_len;
+ /* Set to EFI_FVH_SIGNATURE */
+ u32 sign;
+ /*
+ * Declares capabilities and power-on defaults for the firmware
+ * volume.
+ */
+ u32 attr;
+ /* Length in bytes of the complete firmware volume header */
+ u16 hdr_len;
+ /*
+ * A 16-bit checksum of the firmware volume header.
+ * A valid header sums to zero.
+ */
+ u16 checksum;
+ /*
+ * Offset, relative to the start of the header, of the extended
+ * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is
+ * no extended header.
+ */
+ u16 ext_hdr_off;
+ /* This field must always be set to zero */
+ u8 reserved[1];
+ /*
+ * Set to 2. Future versions of this specification may define new
+ * header fields and will increment the Revision field accordingly.
+ */
+ u8 rev;
+ /*
+ * An array of run-length encoded FvBlockMapEntry structures.
+ * The array is terminated with an entry of {0,0}.
+ */
+ struct fv_blkmap_entry_t block_map[1];
+};
+
+#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
+
+/* Firmware Volume Header Revision definition */
+#define EFI_FVH_REVISION 0x02
+
+/* Extension header pointed by ExtHeaderOffset of volume header */
+struct fv_ext_header_t {
+ /* firmware volume name */
+ struct efi_guid_t fv_name;
+ /* Size of the rest of the extension header including this structure */
+ u32 ext_hdr_size;
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_HOB_H__
+#define __FSP_HOB_H__
+
+/* Type of HOB Header */
+#define HOB_TYPE_MEM_ALLOC 0x0002
+#define HOB_TYPE_RES_DESC 0x0003
+#define HOB_TYPE_GUID_EXT 0x0004
+#define HOB_TYPE_UNUSED 0xFFFE
+#define HOB_TYPE_EOH 0xFFFF
+
+/*
+ * Describes the format and size of the data inside the HOB.
+ * All HOBs must contain this generic HOB header.
+ */
+struct hob_header_t {
+ u16 type; /* HOB type */
+ u16 len; /* HOB length */
+ u32 reserved; /* always zero */
+};
+
+/* Enumeration of memory types introduced in UEFI */
+enum efi_mem_type_t {
+ EFI_RESERVED_MEMORY_TYPE,
+ /*
+ * The code portions of a loaded application.
+ * (Note that UEFI OS loaders are UEFI applications.)
+ */
+ EFI_LOADER_CODE,
+ /*
+ * The data portions of a loaded application and
+ * the default data allocation type used by an application
+ * to allocate pool memory.
+ */
+ EFI_LOADER_DATA,
+ /* The code portions of a loaded Boot Services Driver */
+ EFI_BOOT_SERVICES_CODE,
+ /*
+ * The data portions of a loaded Boot Serves Driver and
+ * the default data allocation type used by a Boot Services
+ * Driver to allocate pool memory.
+ */
+ EFI_BOOT_SERVICES_DATA,
+ /* The code portions of a loaded Runtime Services Driver */
+ EFI_RUNTIME_SERVICES_CODE,
+ /*
+ * The data portions of a loaded Runtime Services Driver and
+ * the default data allocation type used by a Runtime Services
+ * Driver to allocate pool memory.
+ */
+ EFI_RUNTIME_SERVICES_DATA,
+ /* Free (unallocated) memory */
+ EFI_CONVENTIONAL_MEMORY,
+ /* Memory in which errors have been detected */
+ EFI_UNUSABLE_MEMORY,
+ /* Memory that holds the ACPI tables */
+ EFI_ACPI_RECLAIM_MEMORY,
+ /* Address space reserved for use by the firmware */
+ EFI_ACPI_MEMORY_NVS,
+ /*
+ * Used by system firmware to request that a memory-mapped IO region
+ * be mapped by the OS to a virtual address so it can be accessed by
+ * EFI runtime services.
+ */
+ EFI_MMAP_IO,
+ /*
+ * System memory-mapped IO region that is used to translate
+ * memory cycles to IO cycles by the processor.
+ */
+ EFI_MMAP_IO_PORT,
+ /*
+ * Address space reserved by the firmware for code that is
+ * part of the processor.
+ */
+ EFI_PAL_CODE,
+ EFI_MAX_MEMORY_TYPE
+};
+
+/*
+ * Describes all memory ranges used during the HOB producer phase that
+ * exist outside the HOB list. This HOB type describes how memory is used,
+ * not the physical attributes of memory.
+ */
+struct hob_mem_alloc_t {
+ struct hob_header_t hdr;
+ /*
+ * A GUID that defines the memory allocation region's type and purpose,
+ * as well as other fields within the memory allocation HOB. This GUID
+ * is used to define the additional data within the HOB that may be
+ * present for the memory allocation HOB. Type efi_guid_t is defined in
+ * InstallProtocolInterface() in the UEFI 2.0 specification.
+ */
+ struct efi_guid_t name;
+ /*
+ * The base address of memory allocated by this HOB.
+ * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
+ * specification.
+ */
+ phys_addr_t mem_base;
+ /* The length in bytes of memory allocated by this HOB */
+ phys_size_t mem_len;
+ /*
+ * Defines the type of memory allocated by this HOB.
+ * The memory type definition follows the EFI_MEMORY_TYPE definition.
+ * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
+ * specification.
+ */
+ enum efi_mem_type_t mem_type;
+ /* padding */
+ u8 reserved[4];
+};
+
+/* Value of ResourceType in HOB_RES_DESC */
+#define RES_SYS_MEM 0x00000000
+#define RES_MMAP_IO 0x00000001
+#define RES_IO 0x00000002
+#define RES_FW_DEVICE 0x00000003
+#define RES_MMAP_IO_PORT 0x00000004
+#define RES_MEM_RESERVED 0x00000005
+#define RES_IO_RESERVED 0x00000006
+#define RES_MAX_MEM_TYPE 0x00000007
+
+/*
+ * These types can be ORed together as needed.
+ *
+ * The first three enumerations describe settings
+ * The rest of the settings describe capabilities
+ */
+#define RES_ATTR_PRESENT 0x00000001
+#define RES_ATTR_INITIALIZED 0x00000002
+#define RES_ATTR_TESTED 0x00000004
+#define RES_ATTR_SINGLE_BIT_ECC 0x00000008
+#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010
+#define RES_ATTR_ECC_RESERVED_1 0x00000020
+#define RES_ATTR_ECC_RESERVED_2 0x00000040
+#define RES_ATTR_READ_PROTECTED 0x00000080
+#define RES_ATTR_WRITE_PROTECTED 0x00000100
+#define RES_ATTR_EXECUTION_PROTECTED 0x00000200
+#define RES_ATTR_UNCACHEABLE 0x00000400
+#define RES_ATTR_WRITE_COMBINEABLE 0x00000800
+#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000
+#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000
+#define RES_ATTR_16_BIT_IO 0x00004000
+#define RES_ATTR_32_BIT_IO 0x00008000
+#define RES_ATTR_64_BIT_IO 0x00010000
+#define RES_ATTR_UNCACHED_EXPORTED 0x00020000
+
+/*
+ * Describes the resource properties of all fixed, nonrelocatable resource
+ * ranges found on the processor host bus during the HOB producer phase.
+ */
+struct hob_res_desc_t {
+ struct hob_header_t hdr;
+ /*
+ * A GUID representing the owner of the resource. This GUID is
+ * used by HOB consumer phase components to correlate device
+ * ownership of a resource.
+ */
+ struct efi_guid_t owner;
+ u32 type;
+ u32 attr;
+ /* The physical start address of the resource region */
+ phys_addr_t phys_start;
+ /* The number of bytes of the resource region */
+ phys_size_t len;
+};
+
+/*
+ * Allows writers of executable content in the HOB producer phase to
+ * maintain and manage HOBs with specific GUID.
+ */
+struct hob_guid_t {
+ struct hob_header_t hdr;
+ /* A GUID that defines the contents of this HOB */
+ struct efi_guid_t name;
+ /* GUID specific data goes here */
+};
+
+/* Union of all the possible HOB Types */
+union hob_pointers_t {
+ struct hob_header_t *hdr;
+ struct hob_mem_alloc_t *mem_alloc;
+ struct hob_res_desc_t *res_desc;
+ struct hob_guid_t *guid;
+ u8 *raw;
+};
+
+/**
+ * Returns the type of a HOB.
+ *
+ * This macro returns the type field from the HOB header for the
+ * HOB specified by hob.
+ *
+ * @hob: A pointer to a HOB.
+ *
+ * @return: HOB type.
+ */
+#define GET_HOB_TYPE(hob) \
+ ((*(struct hob_header_t **)&(hob))->type)
+
+/**
+ * Returns the length, in bytes, of a HOB.
+ *
+ * This macro returns the len field from the HOB header for the
+ * HOB specified by hob.
+ *
+ * @hob: A pointer to a HOB.
+ *
+ * @return: HOB length.
+ */
+#define GET_HOB_LENGTH(hob) \
+ ((*(struct hob_header_t **)&(hob))->len)
+
+/**
+ * Returns a pointer to the next HOB in the HOB list.
+ *
+ * This macro returns a pointer to HOB that follows the HOB specified by hob
+ * in the HOB List.
+ *
+ * @hob: A pointer to a HOB.
+ *
+ * @return: A pointer to the next HOB in the HOB list.
+ */
+#define GET_NEXT_HOB(hob) \
+ (void *)(*(u8 **)&(hob) + GET_HOB_LENGTH(hob))
+
+/**
+ * Determines if a HOB is the last HOB in the HOB list.
+ *
+ * This macro determine if the HOB specified by hob is the last HOB in the
+ * HOB list. If hob is last HOB in the HOB list, then TRUE is returned.
+ * Otherwise, FALSE is returned.
+ *
+ * @hob: A pointer to a HOB.
+ *
+ * @retval TRUE: The HOB specified by hob is the last HOB in the HOB list.
+ * @retval FALSE: The HOB specified by hob is not the last HOB in the HOB list.
+ */
+#define END_OF_HOB(hob) (GET_HOB_TYPE(hob) == (u16)HOB_TYPE_EOH)
+
+/**
+ * Returns a pointer to data buffer from a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * This macro returns a pointer to the data buffer in a HOB specified by hob.
+ * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * @hob: A pointer to a HOB.
+ *
+ * @return: A pointer to the data buffer in a HOB.
+ */
+#define GET_GUID_HOB_DATA(hob) \
+ (void *)(*(u8 **)&(hob) + sizeof(struct hob_guid_t))
+
+/**
+ * Returns the size of the data buffer from a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * This macro returns the size, in bytes, of the data buffer in a HOB
+ * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * @hob: A pointer to a HOB.
+ *
+ * @return: The size of the data buffer.
+ */
+#define GET_GUID_HOB_DATA_SIZE(hob) \
+ (u16)(GET_HOB_LENGTH(hob) - sizeof(struct hob_guid_t))
+
+/* FSP specific GUID HOB definitions */
+#define FSP_HEADER_GUID \
+ { \
+ 0x912740be, 0x2284, 0x4734, \
+ {0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c} \
+ }
+
+#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
+ { \
+ 0x721acf02, 0x4d77, 0x4c2a, \
+ { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \
+ }
+
+#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \
+ { \
+ 0xbbcff46c, 0xc8d3, 0x4113, \
+ { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \
+ }
+
+#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
+ { \
+ 0x69a79759, 0x1373, 0x4367, \
+ { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \
+ }
+
+#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
+ { \
+ 0xd038747c, 0xd00c, 0x4980, \
+ { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \
+ }
+
+#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
+ { \
+ 0x9c7c3aa7, 0x5332, 0x4917, \
+ { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
+ }
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef _FSP_HEADER_H_
+#define _FSP_HEADER_H_
+
+#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
+
+#pragma pack(1)
+
+struct fsp_header_t {
+ u32 sign; /* 'FSPH' */
+ u32 hdr_len; /* header length */
+ u8 reserved1[3];
+ u8 hdr_rev; /* header rev */
+ u32 img_rev; /* image rev */
+ char img_id[8]; /* signature string */
+ u32 img_size; /* image size */
+ u32 img_base; /* image base */
+ u32 img_attr; /* image attribute */
+ u32 cfg_region_off; /* configuration region offset */
+ u32 cfg_region_size; /* configuration region size */
+ u32 api_num; /* number of API entries */
+ u32 fsp_tempram_init; /* tempram_init offset */
+ u32 fsp_init; /* fsp_init offset */
+ u32 fsp_notify; /* fsp_notify offset */
+ u32 reserved2;
+};
+
+#pragma pack()
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_PLATFORM_H__
+#define __FSP_PLATFORM_H__
+
+#pragma pack(1)
+
+struct fspinit_rtbuf_t {
+ struct common_buf_t common; /* FSP common runtime data structure */
+};
+
+#pragma pack()
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_SUPPORT_H__
+#define __FSP_SUPPORT_H__
+
+#include "fsp_types.h"
+#include "fsp_fv.h"
+#include "fsp_ffs.h"
+#include "fsp_api.h"
+#include "fsp_hob.h"
+#include "fsp_platform.h"
+#include "fsp_infoheader.h"
+#include "fsp_bootmode.h"
+#include "fsp_vpd.h"
+
+struct shared_data_t {
+ struct fsp_header_t *fsp_hdr;
+ u32 *stack_top;
+ struct upd_region_t fsp_upd;
+};
+
+void asm_continuation(void);
+
+void fsp_init_done(void *hob_list);
+
+/**
+ * FSP Continuation function
+ *
+ * @shared_data: Shared data base before stack migration
+ * @status: Always 0
+ * @hob_list: HOB list pointer
+ *
+ * @retval: Never returns
+ */
+void fsp_continue(struct shared_data_t *shared_data, u32 status,
+ void *hob_list);
+
+/**
+ * Find FSP header offset in FSP image
+ *
+ * If this function is called before the a stack is established, special care
+ * must be taken. First, it cannot declare any local variable using stack.
+ * Only register variable can be used here. Secondly, some compiler version
+ * will add prolog or epilog code for the C function. If so the function call
+ * may not work before stack is ready. GCC 4.8.1 has been verified to be
+ * working for the following code.
+ *
+ * @retval: the offset of FSP header. If signature is invalid, returns 0.
+ */
+u32 find_fsp_header(void);
+
+/**
+ * FSP initialization wrapper function.
+ *
+ * @stack_top: bootloader stack top address
+ * @boot_mode: boot mode defined in fsp_bootmode.h
+ * @nvs_buf: Non-volatile memory buffer pointer
+ */
+void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf);
+
+/**
+ * FSP notification wrapper function
+ *
+ * @fsp_hdr: Pointer to FSP information header
+ * @phase: FSP initialization phase defined in enum fsp_phase_t
+ *
+ * @retval: compatible status code with EFI_STATUS defined in PI spec
+ */
+u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase);
+
+/**
+ * This function retrieves the top of usable low memory.
+ *
+ * @hob_list: A HOB list pointer.
+ *
+ * @retval: Usable low memory top.
+ */
+u32 get_usable_lowmem_top(const void *hob_list);
+
+/**
+ * This function retrieves the top of usable high memory.
+ *
+ * @hob_list: A HOB list pointer.
+ *
+ * @retval: Usable high memory top.
+ */
+u64 get_usable_highmem_top(const void *hob_list);
+
+/**
+ * This function retrieves a special reserved memory region.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the GUID HOB data buffer length.
+ * If the GUID HOB is located, the length will be updated.
+ * @guid: A pointer to the owner guild.
+ *
+ * @retval: Reserved region start address.
+ * 0 if this region does not exist.
+ */
+u64 get_fsp_reserved_mem_from_guid(const void *hob_list,
+ u64 *len, struct efi_guid_t *guid);
+
+/**
+ * This function retrieves the FSP reserved normal memory.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the FSP reserved memory length buffer.
+ * If the GUID HOB is located, the length will be updated.
+ * @retval: FSP reserved memory base
+ * 0 if this region does not exist.
+ */
+u32 get_fsp_reserved_mem(const void *hob_list, u32 *len);
+
+/**
+ * This function retrieves the TSEG reserved normal memory.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the TSEG reserved memory length buffer.
+ * If the GUID HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the TSEG reserved memory.
+ * @retval others: TSEG reserved memory base.
+ */
+u32 get_tseg_reserved_mem(const void *hob_list, u32 *len);
+
+/**
+ * Returns the next instance of a HOB type from the starting HOB.
+ *
+ * @type: HOB type to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @retval: A HOB object with matching type; Otherwise NULL.
+ */
+void *get_next_hob(u16 type, const void *hob_list);
+
+/**
+ * Returns the next instance of the matched GUID HOB from the starting HOB.
+ *
+ * @guid: GUID to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @retval: A HOB object with matching GUID; Otherwise NULL.
+ */
+void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list);
+
+/**
+ * This function retrieves a GUID HOB data buffer and size.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the GUID HOB data buffer length.
+ * If the GUID HOB is located, the length will be updated.
+ * @guid A pointer to HOB GUID.
+ *
+ * @retval NULL: Failed to find the GUID HOB.
+ * @retval others: GUID HOB data buffer pointer.
+ */
+void *get_guid_hob_data(const void *hob_list, u32 *len,
+ struct efi_guid_t *guid);
+
+/**
+ * This function retrieves FSP Non-volatile Storage HOB buffer and size.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the NVS data buffer length.
+ * If the HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the NVS HOB.
+ * @retval others: FSP NVS data buffer pointer.
+ */
+void *get_fsp_nvs_data(const void *hob_list, u32 *len);
+
+/**
+ * This function retrieves Bootloader temporary stack buffer and size.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the bootloader temporary stack length.
+ * If the HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the bootloader temporary stack HOB.
+ * @retval others: Bootloader temporary stackbuffer pointer.
+ */
+void *get_bootloader_tmp_mem(const void *hob_list, u32 *len);
+
+/**
+ * This function overrides the default configurations in the UPD data region.
+ *
+ * @fsp_upd: A pointer to the upd_region_t data strcture
+ *
+ * @return: None
+ */
+void update_fsp_upd(struct upd_region_t *fsp_upd);
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_TYPES_H__
+#define __FSP_TYPES_H__
+
+/*
+ * Boolean true value. UEFI Specification defines this value to be 1,
+ * but this form is more portable.
+ */
+#define TRUE ((unsigned char)(1 == 1))
+
+/*
+ * Boolean false value. UEFI Specification defines this value to be 0,
+ * but this form is more portable.
+ */
+#define FALSE ((unsigned char)(0 == 1))
+
+/* 128 bit buffer containing a unique identifier value */
+struct efi_guid_t {
+ u32 data1;
+ u16 data2;
+ u16 data3;
+ u8 data4[8];
+};
+
+/**
+ * Returns a 16-bit signature built from 2 ASCII characters.
+ *
+ * This macro returns a 16-bit value built from the two ASCII characters
+ * specified by A and B.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ *
+ * @return: A 16-bit value built from the two ASCII characters specified by
+ * A and B.
+ */
+#define SIGNATURE_16(A, B) ((A) | (B << 8))
+
+/**
+ * Returns a 32-bit signature built from 4 ASCII characters.
+ *
+ * This macro returns a 32-bit value built from the four ASCII characters
+ * specified by A, B, C, and D.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ * @C: The third ASCII character.
+ * @D: The fourth ASCII character.
+ *
+ * @return: A 32-bit value built from the two ASCII characters specified by
+ * A, B, C and D.
+ */
+#define SIGNATURE_32(A, B, C, D) \
+ (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
+
+/**
+ * Returns a 64-bit signature built from 8 ASCII characters.
+ *
+ * This macro returns a 64-bit value built from the eight ASCII characters
+ * specified by A, B, C, D, E, F, G,and H.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ * @C: The third ASCII character.
+ * @D: The fourth ASCII character.
+ * @E: The fifth ASCII character.
+ * @F: The sixth ASCII character.
+ * @G: The seventh ASCII character.
+ * @H: The eighth ASCII character.
+ *
+ * @return: A 64-bit value built from the two ASCII characters specified by
+ * A, B, C, D, E, F, G and H.
+ */
+#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
+ (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
+
+/* Assertion for debug */
+#define ASSERT(exp) do { if (!(exp)) for (;;); } while (FALSE)
+
+/*
+ * Define FSP API return status code.
+ * Compatiable with EFI_STATUS defined in PI Spec.
+ */
+#define FSP_SUCCESS 0
+#define FSP_INVALID_PARAM 0x80000002
+#define FSP_UNSUPPORTED 0x80000003
+#define FSP_DEVICE_ERROR 0x80000007
+#define FSP_NOT_FOUND 0x8000000E
+#define FSP_ALREADY_STARTED 0x80000014
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * This file is automatically generated. Please do NOT modify !!!
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __VPDHEADER_H__
+#define __VPDHEADER_H__
+
+#pragma pack(1)
+
+struct upd_region_t {
+ u64 sign; /* Offset 0x0000 */
+ u64 reserved; /* Offset 0x0008 */
+ u8 dummy[240]; /* Offset 0x0010 */
+ u8 hda_verb_header[12]; /* Offset 0x0100 */
+ u32 hda_verb_length; /* Offset 0x010C */
+ u8 hda_verb_data0[16]; /* Offset 0x0110 */
+ u8 hda_verb_data1[16]; /* Offset 0x0120 */
+ u8 hda_verb_data2[16]; /* Offset 0x0130 */
+ u8 hda_verb_data3[16]; /* Offset 0x0140 */
+ u8 hda_verb_data4[16]; /* Offset 0x0150 */
+ u8 hda_verb_data5[16]; /* Offset 0x0160 */
+ u8 hda_verb_data6[16]; /* Offset 0x0170 */
+ u8 hda_verb_data7[16]; /* Offset 0x0180 */
+ u8 hda_verb_data8[16]; /* Offset 0x0190 */
+ u8 hda_verb_data9[16]; /* Offset 0x01A0 */
+ u8 hda_verb_data10[16]; /* Offset 0x01B0 */
+ u8 hda_verb_data11[16]; /* Offset 0x01C0 */
+ u8 hda_verb_data12[16]; /* Offset 0x01D0 */
+ u8 hda_verb_data13[16]; /* Offset 0x01E0 */
+ u8 hda_verb_pad[47]; /* Offset 0x01F0 */
+ u16 terminator; /* Offset 0x021F */
+};
+
+#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */
+#define VPD_IMAGE_REV 0x00000301
+
+struct vpd_region_t {
+ u64 sign; /* Offset 0x0000 */
+ u32 img_rev; /* Offset 0x0008 */
+ u32 upd_offset; /* Offset 0x000C */
+ u8 unused[16]; /* Offset 0x0010 */
+ u32 fsp_res_memlen; /* Offset 0x0020 */
+ u8 disable_pcie1; /* Offset 0x0024 */
+ u8 disable_pcie2; /* Offset 0x0025 */
+ u8 disable_pcie3; /* Offset 0x0026 */
+ u8 enable_azalia; /* Offset 0x0027 */
+ u8 legacy_seg_decode; /* Offset 0x0028 */
+ u8 pcie_port_ioh; /* Offset 0x0029 */
+};
+
+#pragma pack()
+
+#endif
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#define asmlinkage __attribute__((regparm(0)))
#endif
enum pei_boot_mode_t pei_boot_mode;
const struct pch_gpio_map *gpio_map; /* board GPIO map */
struct memory_info meminfo; /* Memory information */
+#ifdef CONFIG_HAVE_FSP
+ void *hob_list; /* FSP HOB list */
+#endif
};
#endif
} set3;
};
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
#endif /* _X86_GPIO_H_ */
--- /dev/null
+#ifndef _ASM_X86_LINKAGE_H
+#define _ASM_X86_LINKAGE_H
+
+#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
+
+#endif /* _ASM_X86_LINKAGE_H */
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/include/device/pnp_def.h
+ * and arch/x86/include/arch/io.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_PNP_DEF_H_
+#define _ASM_PNP_DEF_H_
+
+#include <asm/io.h>
+
+#define PNP_IDX_EN 0x30
+#define PNP_IDX_IO0 0x60
+#define PNP_IDX_IO1 0x62
+#define PNP_IDX_IO2 0x64
+#define PNP_IDX_IO3 0x66
+#define PNP_IDX_IRQ0 0x70
+#define PNP_IDX_IRQ1 0x72
+#define PNP_IDX_DRQ0 0x74
+#define PNP_IDX_DRQ1 0x75
+#define PNP_IDX_MSC0 0xf0
+#define PNP_IDX_MSC1 0xf1
+
+/* Generic functions for pnp devices */
+
+/*
+ * pnp device is a 16-bit integer composed of its i/o port address at high byte
+ * and logic function number at low byte.
+ */
+#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
+
+static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value)
+{
+ uint8_t port = dev >> 8;
+
+ outb(reg, port);
+ outb(value, port + 1);
+}
+
+static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg)
+{
+ uint8_t port = dev >> 8;
+
+ outb(reg, port);
+ return inb(port + 1);
+}
+
+static inline void pnp_set_logical_device(uint16_t dev)
+{
+ uint8_t device = dev & 0xff;
+
+ pnp_write_config(dev, 0x07, device);
+}
+
+static inline void pnp_set_enable(uint16_t dev, int enable)
+{
+ pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0);
+}
+
+static inline int pnp_read_enable(uint16_t dev)
+{
+ return !!pnp_read_config(dev, PNP_IDX_EN);
+}
+
+static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase)
+{
+ pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
+ pnp_write_config(dev, index + 1, iobase & 0xff);
+}
+
+static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index)
+{
+ return ((uint16_t)(pnp_read_config(dev, index)) << 8) |
+ pnp_read_config(dev, index + 1);
+}
+
+static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq)
+{
+ pnp_write_config(dev, index, irq);
+}
+
+static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq)
+{
+ pnp_write_config(dev, index, drq & 0xff);
+}
+
+#endif /* _ASM_PNP_DEF_H_ */
#define POST_LAPIC 0x30
#define POST_RAM_FAILURE 0xea
+#define POST_BIST_FAILURE 0xeb
+#define POST_CAR_FAILURE 0xec
/* Output a post code using al - value must be 0 to 0xff */
#ifdef __ASSEMBLY__
obj-y += bios_interrupts.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cmd_boot.o
+obj-$(CONFIG_HAVE_FSP) += cmd_hob.o
obj-y += gcc.o
obj-y += init_helpers.o
obj-y += interrupts.o
int main(void)
{
- DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
+ DEFINE(GD_BIST, offsetof(gd_t, arch.bist));
+#ifdef CONFIG_HAVE_FSP
+ DEFINE(GD_HOB_LIST, offsetof(gd_t, arch.hob_list));
+#endif
return 0;
}
#include <common.h>
#include <bios_emul.h>
#include <vbe.h>
+#include <linux/linkage.h>
#include <asm/cache.h>
#include <asm/processor.h>
#include <asm/i8259.h>
#ifndef _X86_LIB_BIOS_H
#define _X86_LIB_BIOS_H
+#include <linux/linkage.h>
+
#define REALMODE_BASE 0x600
#ifdef __ASSEMBLY__
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/compiler.h>
+#include <asm/arch/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char *hob_type[] = {
+ "reserved",
+ "Hand-off",
+ "Memory Allocation",
+ "Resource Descriptor",
+ "GUID Extension",
+ "Firmware Volumn",
+ "CPU",
+ "Memory Pool",
+ "reserved",
+ "Firmware Volumn 2",
+ "Load PEIM Unused",
+ "UEFI Capsule",
+};
+
+int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ union hob_pointers_t hob;
+ u16 type;
+ char *desc;
+ int i = 0;
+
+ hob.raw = (u8 *)gd->arch.hob_list;
+
+ printf("HOB list address: 0x%08x\n\n", (unsigned int)hob.raw);
+
+ printf("No. | Address | Type | Length in Bytes\n");
+ printf("----|----------|---------------------|----------------\n");
+ while (!END_OF_HOB(hob)) {
+ printf("%-3d | %08x | ", i, (unsigned int)hob.raw);
+ type = hob.hdr->type;
+ if (type == HOB_TYPE_UNUSED)
+ desc = "*Unused*";
+ else if (type == HOB_TYPE_EOH)
+ desc = "**END OF HOB**";
+ else if (type >= 0 && type <= ARRAY_SIZE(hob_type))
+ desc = hob_type[type];
+ else
+ desc = "!!!Invalid Type!!!";
+ printf("%-19s | %-15d\n", desc, hob.hdr->len);
+ hob.raw = GET_NEXT_HOB(hob);
+ i++;
+ }
+
+ return 0;
+}
+
+/* -------------------------------------------------------------------- */
+
+U_BOOT_CMD(
+ hob, 1, 1, do_hob,
+ "print FSP Hand-Off Block information",
+ ""
+);
F: board/altera/socfpga/
F: include/configs/socfpga_cyclone5.h
F: configs/socfpga_cyclone5_defconfig
+
+SOCRATES BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: configs/socfpga_socrates_defconfig
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
+#include <micrel.h>
#include <netdev.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
*/
#include <common.h>
+#include <dm.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/gpio.h>
void pmu_write(uchar reg, uchar data)
{
- i2c_set_bus_num(4); /* PMU is on bus 4 */
- i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1);
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
+ i2c_write(dev, reg, &data, 1);
}
/*
#include <common.h>
#include <cros_ec.h>
+#include <asm/gpio.h>
int arch_early_init_r(void)
{
return 0;
}
+
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
select SOUTHBRIDGE_INTEL_C216
select HAVE_ACPI_RESUME
select MARK_GRAPHICS_MEM_WRCOMB
+ select BOARD_ROMSIZE_KB_8192
config MMCONF_BASE_ADDRESS
hex
#include <common.h>
#include <cros_ec.h>
#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
int arch_early_init_r(void)
{
return 0;
}
+
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+{
+ /* GPIO Set 1 */
+ if (gpio->set1.level)
+ outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
+ if (gpio->set1.mode)
+ outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio->set1.direction)
+ outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio->set1.reset)
+ outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio->set1.invert)
+ outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
+ if (gpio->set1.blink)
+ outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio->set2.level)
+ outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
+ if (gpio->set2.mode)
+ outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio->set2.direction)
+ outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio->set2.reset)
+ outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio->set3.level)
+ outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
+ if (gpio->set3.mode)
+ outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio->set3.direction)
+ outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio->set3.reset)
+ outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
*/
#include <common.h>
+#include <dm.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include "pinmux-config-cardhu.h"
*/
void board_sdmmc_voltage_init(void)
{
+ struct udevice *dev;
uchar reg, data_buffer[1];
+ int ret;
int i;
- i2c_set_bus_num(0); /* PMU is on bus 0 */
+ ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
/* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
data_buffer[0] = 0x65;
reg = 0x32;
for (i = 0; i < MAX_I2C_RETRY; ++i) {
- if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+ if (i2c_write(dev, reg, data_buffer, 1))
udelay(100);
}
reg = 0x67;
for (i = 0; i < MAX_I2C_RETRY; ++i) {
- if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+ if (i2c_write(dev, reg, data_buffer, 1))
udelay(100);
}
}
power_det_init();
#ifdef CONFIG_SYS_I2C_TEGRA
-#ifndef CONFIG_SYS_I2C_INIT_BOARD
-#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
-#endif
- i2c_init_board();
# ifdef CONFIG_TEGRA_PMU
if (pmu_set_nominal())
debug("Failed to select nominal voltages\n");
*/
#include <common.h>
+#include <dm.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include "pinmux-config-dalmore.h"
*/
void board_sdmmc_voltage_init(void)
{
+ struct udevice *dev;
uchar reg, data_buffer[1];
int ret;
- ret = i2c_set_bus_num(0);/* PMU is on bus 0 */
- if (ret)
- printf("%s: i2c_set_bus_num returned %d\n", __func__, ret);
+ ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
/* TPS65913: LDO9_VOLTAGE = 3.3V */
data_buffer[0] = 0x31;
reg = 0x61;
- ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1);
+ ret = i2c_write(dev, reg, data_buffer, 1);
if (ret)
printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
__func__, reg, data_buffer[0], ret);
data_buffer[0] = 0x01;
reg = 0x60;
- ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1);
+ ret = i2c_write(dev, reg, data_buffer, 1);
if (ret)
printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
__func__, reg, data_buffer[0], ret);
data_buffer[0] = 0x03;
reg = 0x14;
- ret = i2c_write(BAT_I2C_ADDRESS, reg, 1, data_buffer, 1);
+ ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find charger I2C chip\n", __func__);
+ return;
+ }
+ ret = i2c_write(dev, reg, data_buffer, 1);
if (ret)
printf("%s: BAT i2c_write %02X<-%02X returned %d\n",
__func__, reg, data_buffer[0], ret);
--- /dev/null
+if TARGET_NYAN_BIG
+
+config SYS_CPU
+ string
+ default "arm720t" if SPL_BUILD
+ default "armv7" if !SPL_BUILD
+
+config SYS_BOARD
+ string
+ default "nyan-big"
+
+config SYS_VENDOR
+ string
+ default "nvidia"
+
+config SYS_SOC
+ string
+ default "tegra124"
+
+config SYS_CONFIG_NAME
+ string
+ default "nyan-big"
+
+endif
--- /dev/null
+NORRIN BOARD
+M: Allen Martin <amartin@nvidia.com>
+S: Maintained
+F: board/nvidia/nyan-big/
+F: include/configs/nyan-big.h
+F: configs/nyan-big_defconfig
--- /dev/null
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../venice2/as3722_init.o
+obj-y += nyan-big.o
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-nyan-big.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ gpio_config_table(nyan_big_gpio_inits,
+ ARRAY_SIZE(nyan_big_gpio_inits));
+
+ pinmux_config_pingrp_table(nyan_big_pingrps,
+ ARRAY_SIZE(nyan_big_pingrps));
+
+ pinmux_config_drvgrp_table(nyan_big_drvgrps,
+ ARRAY_SIZE(nyan_big_drvgrps));
+}
--- /dev/null
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
+#define _PINMUX_CONFIG_NYAN_BIG_H_
+
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(A0, IN),
+ GPIO_INIT(C7, IN),
+ GPIO_INIT(G0, IN),
+ GPIO_INIT(G1, IN),
+ GPIO_INIT(G2, IN),
+ GPIO_INIT(G3, IN),
+ GPIO_INIT(H2, IN),
+ GPIO_INIT(H4, IN),
+ GPIO_INIT(H6, IN),
+ GPIO_INIT(H7, OUT1),
+ GPIO_INIT(I0, IN),
+ GPIO_INIT(I1, IN),
+ GPIO_INIT(I5, OUT1),
+ GPIO_INIT(I6, IN),
+ GPIO_INIT(I7, IN),
+ GPIO_INIT(J0, IN),
+ GPIO_INIT(J7, IN),
+ GPIO_INIT(K1, OUT0),
+ GPIO_INIT(K2, IN),
+ GPIO_INIT(K4, OUT0),
+ GPIO_INIT(K6, OUT0),
+ GPIO_INIT(K7, IN),
+ GPIO_INIT(N7, IN),
+ GPIO_INIT(P2, OUT0),
+ GPIO_INIT(Q0, IN),
+ GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q3, IN),
+ GPIO_INIT(Q6, IN),
+ GPIO_INIT(Q7, IN),
+ GPIO_INIT(R0, OUT0),
+ GPIO_INIT(R1, IN),
+ GPIO_INIT(R4, IN),
+ GPIO_INIT(R7, IN),
+ GPIO_INIT(S3, OUT0),
+ GPIO_INIT(S4, OUT0),
+ GPIO_INIT(S7, IN),
+ GPIO_INIT(T1, IN),
+ GPIO_INIT(U4, IN),
+ GPIO_INIT(U5, IN),
+ GPIO_INIT(U6, IN),
+ GPIO_INIT(V0, IN),
+ GPIO_INIT(W3, IN),
+ GPIO_INIT(X1, IN),
+ GPIO_INIT(X4, IN),
+ GPIO_INIT(X7, OUT0),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config nyan_big_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
+ PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config nyan_big_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_NYAN_BIG_H */
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
#define AS3722_LDCONTROL_REG 0x4E
-#ifdef CONFIG_TARGET_JETSON_TK1
+#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN_BIG)
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
#else
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch/clock.h>
*/
void pin_mux_mmc(void)
{
+ struct udevice *dev;
uchar val;
int ret;
/* Turn on MAX8907B LDO12 to 2.8V for J40 power */
- ret = i2c_set_bus_num(0);
- if (ret)
- printf("i2c_set_bus_num failed: %d\n", ret);
+ ret = i2c_get_chip_for_busnum(0, 0x3c, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX8907B I2C chip\n", __func__);
+ return;
+ }
val = 0x29;
- ret = i2c_write(0x3c, 0x46, 1, &val, 1);
+ ret = i2c_write(dev, 0x46, &val, 1);
if (ret)
printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret);
val = 0x00;
- ret = i2c_write(0x3c, 0x45, 1, &val, 1);
+ ret = i2c_write(dev, 0x45, &val, 1);
if (ret)
printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret);
val = 0x1f;
- ret = i2c_write(0x3c, 0x44, 1, &val, 1);
+ ret = i2c_write(dev, 0x44, &val, 1);
if (ret)
printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
/* this is a weak define that we are overriding */
void pin_mux_usb(void)
{
+ struct udevice *dev;
uchar val;
int ret;
*/
/* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
- ret = i2c_set_bus_num(0);
- if (ret)
- printf("i2c_set_bus_num failed: %d\n", ret);
+ ret = i2c_get_chip_for_busnum(0, 0x20, &dev);
+ if (ret) {
+ printf("%s: Cannot find TAC6416 I2C chip\n", __func__);
+ return;
+ }
val = 0x03;
- ret = i2c_write(0x20, 2, 1, &val, 1);
+ ret = i2c_write(dev, 2, &val, 1);
if (ret)
printf("i2c_write 0 0x20 2 failed: %d\n", ret);
val = 0xfc;
- ret = i2c_write(0x20, 6, 1, &val, 1);
+ ret = i2c_write(dev, 6, &val, 1);
if (ret)
printf("i2c_write 0 0x20 6 failed: %d\n", ret);
}
#include <asm/arch/mbox.h>
#include <asm/arch/sdhci.h>
#include <asm/global_data.h>
+#include <dm/platform_data/serial_pl01x.h>
DECLARE_GLOBAL_DATA_PTR;
.platdata = &gpio_platdata,
};
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = 0x20201000,
+ .type = TYPE_PL011,
+ .clock = 3000000,
+};
+
+U_BOOT_DEVICE(bcm2835_serials) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
struct msg_get_arm_mem {
struct bcm2835_mbox_hdr hdr;
struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
*/
#include <common.h>
-
+#include <dm.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
- unsigned int old_bus;
+ struct udevice *dev;
u8 addr, data[1];
int err;
- old_bus = i2c_get_bus_num();
-
- err = i2c_set_bus_num(0);
+ err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
if (err) {
- debug("failed to set I2C bus\n");
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
return err;
}
-
/* TPS659110: VDD2_OP_REG = 1.05V */
data[0] = 0x27;
addr = 0x25;
- err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
+ err = i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to set VDD supply\n");
return err;
data[0] = 0x0D;
addr = 0x24;
- err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
+ err = i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to enable VDD supply\n");
return err;
data[0] = 0x0D;
addr = 0x35;
- err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
+ err = i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to set AVDD supply\n");
return err;
}
- i2c_set_bus_num(old_bus);
-
return 0;
}
#include <bootretry.h>
#include <cli.h>
#include <command.h>
+#include <dm.h>
#include <edid.h>
#include <environment.h>
+#include <errno.h>
#include <i2c.h>
#include <malloc.h>
#include <asm/byteorder.h>
#define DISP_LINE_LEN 16
+/*
+ * Default for driver model is to use the chip's existing address length.
+ * For legacy code, this is not stored, so we need to use a suitable
+ * default.
+ */
+#ifdef CONFIG_DM_I2C
+#define DEFAULT_ADDR_LEN (-1)
+#else
+#define DEFAULT_ADDR_LEN 1
+#endif
+
+#ifdef CONFIG_DM_I2C
+static struct udevice *i2c_cur_bus;
+
+static int i2c_set_bus_num(unsigned int busnum)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, busnum);
+ return ret;
+ }
+ i2c_cur_bus = bus;
+
+ return 0;
+}
+
+static int i2c_get_cur_bus(struct udevice **busp)
+{
+ if (!i2c_cur_bus) {
+ puts("No I2C bus selected\n");
+ return -ENODEV;
+ }
+ *busp = i2c_cur_bus;
+
+ return 0;
+}
+
+static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = i2c_get_cur_bus(&bus);
+ if (ret)
+ return ret;
+
+ return i2c_get_chip(bus, chip_addr, devp);
+}
+
+#endif
+
/**
* i2c_init_board() - Board-specific I2C bus init
*
*
* Returns I2C bus speed in Hz.
*/
-#if !defined(CONFIG_SYS_I2C)
+#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
/*
* TODO: Implement architecture-specific get/set functions
* Should go away, if we switched completely to new multibus support
*
* Returns the address length.
*/
-static uint get_alen(char *arg)
+static uint get_alen(char *arg, int default_len)
{
int j;
int alen;
- alen = 1;
+ alen = default_len;
for (j = 0; j < 8; j++) {
if (arg[j] == '.') {
alen = arg[j+1] - '0';
static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
- uint devaddr, alen, length;
+ uint devaddr, length;
+ int alen;
u_char *memaddr;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc != 5)
return CMD_RET_USAGE;
* 2 bytes long. Some day it might be 3 bytes long :-).
*/
devaddr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen > 3)
return CMD_RET_USAGE;
*/
memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
- if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
- i2c_report_err(-1, I2C_ERR_READ);
- return 1;
- }
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret && alen != -1)
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (!ret)
+ ret = i2c_read(dev, devaddr, memaddr, length);
+#else
+ ret = i2c_read(chip, devaddr, alen, memaddr, length);
+#endif
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
+
return 0;
}
static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
- uint devaddr, alen, length;
+ uint devaddr, length;
+ int alen;
u_char *memaddr;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc != 5)
return cmd_usage(cmdtp);
* 2 bytes long. Some day it might be 3 bytes long :-).
*/
devaddr = simple_strtoul(argv[3], NULL, 16);
- alen = get_alen(argv[3]);
+ alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
if (alen > 3)
return cmd_usage(cmdtp);
*/
length = simple_strtoul(argv[4], NULL, 16);
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret && alen != -1)
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_WRITE);
+#endif
+
while (length-- > 0) {
- if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
- return i2c_report_err(-1, I2C_ERR_WRITE);
- }
+#ifdef CONFIG_DM_I2C
+ ret = i2c_write(dev, devaddr++, memaddr++, 1);
+#else
+ ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
+#endif
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_WRITE);
/*
* No write delay with FRAM devices.
*/
return 0;
}
+#ifdef CONFIG_DM_I2C
+static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ uint flags;
+ int chip;
+ int ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ chip = simple_strtoul(argv[1], NULL, 16);
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
+
+ if (argc > 2) {
+ flags = simple_strtoul(argv[2], NULL, 16);
+ ret = i2c_set_chip_flags(dev, flags);
+ } else {
+ ret = i2c_get_chip_flags(dev, &flags);
+ if (!ret)
+ printf("%x\n", flags);
+ }
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
+
+ return 0;
+}
+#endif
+
/**
* do_i2c_md() - Handle the "i2c md" command-line command
* @cmdtp: Command data struct pointer
static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
- uint addr, alen, length;
+ uint addr, length;
+ int alen;
int j, nbytes, linebytes;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
/* We use the last specified parameters, unless new ones are
* entered.
* 2 bytes long. Some day it might be 3 bytes long :-).
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen > 3)
return CMD_RET_USAGE;
length = simple_strtoul(argv[3], NULL, 16);
}
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret && alen != -1)
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
+#endif
+
/*
* Print the lines.
*
linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
- if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
- i2c_report_err(-1, I2C_ERR_READ);
+#ifdef CONFIG_DM_I2C
+ ret = i2c_read(dev, addr, linebuf, linebytes);
+#else
+ ret = i2c_read(chip, addr, alen, linebuf, linebytes);
+#endif
+ if (ret)
+ i2c_report_err(ret, I2C_ERR_READ);
else {
printf("%04x:", addr);
cp = linebuf;
{
uchar chip;
ulong addr;
- uint alen;
+ int alen;
uchar byte;
int count;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if ((argc < 4) || (argc > 5))
return CMD_RET_USAGE;
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen > 3)
return CMD_RET_USAGE;
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret && alen != -1)
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_WRITE);
+#endif
/*
* Value to write is always specified.
*/
count = 1;
while (count-- > 0) {
- if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
- i2c_report_err(-1, I2C_ERR_WRITE);
+#ifdef CONFIG_DM_I2C
+ ret = i2c_write(dev, addr++, &byte, 1);
+#else
+ ret = i2c_write(chip, addr++, alen, &byte, 1);
+#endif
+ if (ret)
+ i2c_report_err(ret, I2C_ERR_WRITE);
/*
* Wait for the write to complete. The write can take
* up to 10mSec (we allow a little more time).
{
uchar chip;
ulong addr;
- uint alen;
+ int alen;
int count;
uchar byte;
ulong crc;
ulong err;
+ int ret = 0;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc < 4)
return CMD_RET_USAGE;
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen > 3)
return CMD_RET_USAGE;
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret && alen != -1)
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
+#endif
/*
* Count is always specified
*/
crc = 0;
err = 0;
while (count-- > 0) {
- if (i2c_read(chip, addr, alen, &byte, 1) != 0)
+#ifdef CONFIG_DM_I2C
+ ret = i2c_read(dev, addr, &byte, 1);
+#else
+ ret = i2c_read(chip, addr, alen, &byte, 1);
+#endif
+ if (ret)
err++;
crc = crc32 (crc, &byte, 1);
addr++;
}
if (err > 0)
- i2c_report_err(-1, I2C_ERR_READ);
+ i2c_report_err(ret, I2C_ERR_READ);
else
printf ("%08lx\n", crc);
{
uchar chip;
ulong addr;
- uint alen;
+ int alen;
ulong data;
int size = 1;
int nbytes;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc != 3)
return CMD_RET_USAGE;
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen > 3)
return CMD_RET_USAGE;
}
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret && alen != -1)
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_WRITE);
+#endif
+
/*
* Print the address, followed by value. Then accept input for
* the next value. A non-converted value exits.
*/
do {
printf("%08lx:", addr);
- if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
- i2c_report_err(-1, I2C_ERR_READ);
+#ifdef CONFIG_DM_I2C
+ ret = i2c_read(dev, addr, (uchar *)&data, size);
+#else
+ ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
+#endif
+ if (ret)
+ i2c_report_err(ret, I2C_ERR_READ);
else {
data = cpu_to_be32(data);
if (size == 1)
* good enough to not time out
*/
bootretry_reset_cmd_timeout();
- if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
- i2c_report_err(-1, I2C_ERR_WRITE);
+#ifdef CONFIG_DM_I2C
+ ret = i2c_write(dev, addr, (uchar *)&data,
+ size);
+#else
+ ret = i2c_write(chip, addr, alen,
+ (uchar *)&data, size);
+#endif
+ if (ret)
+ i2c_report_err(ret, I2C_ERR_WRITE);
#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
int k, skip;
unsigned int bus = GET_BUS_NUM;
#endif /* NOPROBES */
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *bus, *dev;
+
+ if (i2c_get_cur_bus(&bus))
+ return CMD_RET_FAILURE;
+#endif
if (argc == 2)
addr = simple_strtol(argv[1], 0, 16);
if (skip)
continue;
#endif
- if (i2c_probe(j) == 0) {
+#ifdef CONFIG_DM_I2C
+ ret = i2c_probe(bus, j, 0, &dev);
+#else
+ ret = i2c_probe(j);
+#endif
+ if (ret == 0) {
printf(" %02X", j);
found++;
}
static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
- ulong alen;
+ int alen;
uint addr;
uint length;
u_char bytes[16];
int delay;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc < 3)
return CMD_RET_USAGE;
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen > 3)
return CMD_RET_USAGE;
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret && alen != -1)
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_WRITE);
+#endif
/*
* Length is the number of objects, not number of bytes.
* Run the loop...
*/
while (1) {
- if (i2c_read(chip, addr, alen, bytes, length) != 0)
- i2c_report_err(-1, I2C_ERR_READ);
+#ifdef CONFIG_DM_I2C
+ ret = i2c_read(dev, addr, bytes, length);
+#else
+ ret = i2c_read(chip, addr, alen, bytes, length);
+#endif
+ if (ret)
+ i2c_report_err(ret, I2C_ERR_READ);
udelay(delay);
}
{
u_char chip;
struct edid1_info edid;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc < 2) {
cmd_usage(cmdtp);
}
chip = simple_strtoul(argv[1], NULL, 16);
- if (i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid)) != 0) {
- i2c_report_err(-1, I2C_ERR_READ);
- return 1;
- }
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret)
+ ret = i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
+#else
+ ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
+#endif
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
if (edid_check_info(&edid)) {
puts("Content isn't valid EDID.\n");
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
-#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
+ defined(CONFIG_DM_I2C)
static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret = 0;
- unsigned int bus_no;
+ int bus_no;
- if (argc == 1)
+ if (argc == 1) {
/* querying current setting */
- printf("Current bus is %d\n", i2c_get_bus_num());
- else {
+#ifdef CONFIG_DM_I2C
+ struct udevice *bus;
+
+ if (!i2c_get_cur_bus(&bus))
+ bus_no = bus->seq;
+ else
+ bus_no = -1;
+#else
+ bus_no = i2c_get_bus_num();
+#endif
+ printf("Current bus is %d\n", bus_no);
+ } else {
bus_no = simple_strtoul(argv[1], NULL, 10);
#if defined(CONFIG_SYS_I2C)
if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
{
int speed, ret=0;
- if (argc == 1)
+#ifdef CONFIG_DM_I2C
+ struct udevice *bus;
+
+ if (i2c_get_cur_bus(&bus))
+ return 1;
+#endif
+ if (argc == 1) {
+#ifdef CONFIG_DM_I2C
+ speed = i2c_get_bus_speed(bus);
+#else
+ speed = i2c_get_bus_speed();
+#endif
/* querying current speed */
- printf("Current bus speed=%d\n", i2c_get_bus_speed());
- else {
+ printf("Current bus speed=%d\n", speed);
+ } else {
speed = simple_strtoul(argv[1], NULL, 10);
printf("Setting bus speed to %d Hz\n", speed);
+#ifdef CONFIG_DM_I2C
+ ret = i2c_set_bus_speed(bus, speed);
+#else
ret = i2c_set_bus_speed(speed);
+#endif
if (ret)
printf("Failure changing bus speed (%d)\n", ret);
}
*/
static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
-#if defined(CONFIG_SYS_I2C)
+#if defined(CONFIG_DM_I2C)
+ struct udevice *bus;
+
+ if (i2c_get_cur_bus(&bus))
+ return CMD_RET_FAILURE;
+ if (i2c_deblock(bus)) {
+ printf("Error: Not supported by the driver\n");
+ return CMD_RET_FAILURE;
+ }
+#elif defined(CONFIG_SYS_I2C)
i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
#if defined(CONFIG_SYS_I2C) || \
- defined(CONFIG_I2C_MULTI_BUS)
+ defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
#endif /* CONFIG_I2C_MULTI_BUS */
#if defined(CONFIG_I2C_EDID)
U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
+#ifdef CONFIG_DM_I2C
+ U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
+#endif
U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
#if defined(CONFIG_CMD_SDRAM)
U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
#endif
"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
#if defined(CONFIG_SYS_I2C) || \
- defined(CONFIG_I2C_MULTI_BUS)
+ defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
"i2c dev [dev] - show or set current I2C bus\n"
#endif /* CONFIG_I2C_MULTI_BUS */
#if defined(CONFIG_I2C_EDID)
"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
"i2c probe [address] - test for and show device(s) on the I2C bus\n"
- "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
+ "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
"i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
+#ifdef CONFIG_DM_I2C
+ "i2c flags chip [flags] - set or get chip flags\n"
+#endif
"i2c reset - re-init the I2C Controller\n"
#if defined(CONFIG_CMD_SDRAM)
"i2c sdram chip - print SDRAM configuration information\n"
puts("Capacity: ");
print_size(mmc->capacity, "\n");
- printf("Bus Width: %d-bit\n", mmc->bus_width);
+ printf("Bus Width: %d-bit%s\n", mmc->bus_width,
+ mmc->ddr_mode ? " DDR" : "");
}
static struct mmc *init_mmc_device(int dev, bool force_init)
{
--- /dev/null
++S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA124=y
++S:CONFIG_TARGET_NYAN_BIG=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
****************************************************************************/
#define __io
-#include <asm/io.h>
#include <common.h>
+#include <asm/io.h>
#include "biosemui.h"
/*------------------------- Global Variables ------------------------------*/
****************************************************************************/
#define __io
-#include <asm/io.h>
#include <common.h>
+#include <asm/io.h>
#include "biosemui.h"
/*----------------------------- Implementation ----------------------------*/
void *dev_get_platdata(struct udevice *dev)
{
if (!dev) {
- dm_warn("%s: null device", __func__);
+ dm_warn("%s: null device\n", __func__);
return NULL;
}
void *dev_get_priv(struct udevice *dev)
{
if (!dev) {
- dm_warn("%s: null device", __func__);
+ dm_warn("%s: null device\n", __func__);
return NULL;
}
void *dev_get_parentdata(struct udevice *dev)
{
if (!dev) {
- dm_warn("%s: null device", __func__);
+ dm_warn("%s: null device\n", __func__);
return NULL;
}
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>
-#ifdef CONFIG_X86_RESET_VECTOR
-#include <asm/arch/pch.h>
-#define SUPPORT_GPIO_SETUP
-#endif
#define GPIO_PER_BANK 32
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
struct ich6_bank_priv {
/* These are I/O addresses */
uint32_t use_sel;
uint32_t lvl;
};
-#ifdef SUPPORT_GPIO_SETUP
-static void setup_pch_gpios(const struct pch_gpio_map *gpio)
-{
- u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
-
- /* GPIO Set 1 */
- if (gpio->set1.level)
- outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
- if (gpio->set1.mode)
- outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
- if (gpio->set1.direction)
- outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
- if (gpio->set1.reset)
- outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
- if (gpio->set1.invert)
- outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
- if (gpio->set1.blink)
- outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
-
- /* GPIO Set 2 */
- if (gpio->set2.level)
- outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
- if (gpio->set2.mode)
- outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
- if (gpio->set2.direction)
- outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
- if (gpio->set2.reset)
- outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
-
- /* GPIO Set 3 */
- if (gpio->set3.level)
- outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
- if (gpio->set3.mode)
- outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
- if (gpio->set3.direction)
- outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
- if (gpio->set3.reset)
- outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
-}
-
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd->arch.gpio_map = map;
}
-#endif /* SUPPORT_GPIO_SETUP */
static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
struct ich6_bank_priv *bank = dev_get_priv(dev);
-#ifdef SUPPORT_GPIO_SETUP
if (gd->arch.gpio_map) {
- setup_pch_gpios(gd->arch.gpio_map);
+ setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
gd->arch.gpio_map = NULL;
}
-#endif
+
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
bank->use_sel = plat->base_addr;
struct ich6_bank_priv *bank = dev_get_priv(dev);
u32 tmplong;
+ gpio_set_value(offset, value);
+
tmplong = inl(bank->io_sel);
tmplong &= ~(1UL << offset);
outl(bank->io_sel, tmplong);
#
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DM_I2C) += i2c-uclass.o
obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
+obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+
+UCLASS_DRIVER(i2c_emul) = {
+ .id = UCLASS_I2C_EMUL,
+ .name = "i2c_emul",
+};
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_MAX_OFFSET_LEN 4
+
+/**
+ * i2c_setup_offset() - Set up a new message with a chip offset
+ *
+ * @chip: Chip to use
+ * @offset: Byte offset within chip
+ * @offset_buf: Place to put byte offset
+ * @msg: Message buffer
+ * @return 0 if OK, -EADDRNOTAVAIL if the offset length is 0. In that case the
+ * message is still set up but will not contain an offset.
+ */
+static int i2c_setup_offset(struct dm_i2c_chip *chip, uint offset,
+ uint8_t offset_buf[], struct i2c_msg *msg)
+{
+ int offset_len;
+
+ msg->addr = chip->chip_addr;
+ msg->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0;
+ msg->len = chip->offset_len;
+ msg->buf = offset_buf;
+ if (!chip->offset_len)
+ return -EADDRNOTAVAIL;
+ assert(chip->offset_len <= I2C_MAX_OFFSET_LEN);
+ offset_len = chip->offset_len;
+ while (offset_len--)
+ *offset_buf++ = offset >> (8 * offset_len);
+
+ return 0;
+}
+
+static int i2c_read_bytewise(struct udevice *dev, uint offset,
+ uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct i2c_msg msg[2], *ptr;
+ uint8_t offset_buf[I2C_MAX_OFFSET_LEN];
+ int ret;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (i2c_setup_offset(chip, offset + i, offset_buf, msg))
+ return -EINVAL;
+ ptr = msg + 1;
+ ptr->addr = chip->chip_addr;
+ ptr->flags = msg->flags | I2C_M_RD;
+ ptr->len = 1;
+ ptr->buf = &buffer[i];
+ ptr++;
+
+ ret = ops->xfer(bus, msg, ptr - msg);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int i2c_write_bytewise(struct udevice *dev, uint offset,
+ const uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct i2c_msg msg[1];
+ uint8_t buf[I2C_MAX_OFFSET_LEN + 1];
+ int ret;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (i2c_setup_offset(chip, offset + i, buf, msg))
+ return -EINVAL;
+ buf[msg->len++] = buffer[i];
+
+ ret = ops->xfer(bus, msg, 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct i2c_msg msg[2], *ptr;
+ uint8_t offset_buf[I2C_MAX_OFFSET_LEN];
+ int msg_count;
+
+ if (!ops->xfer)
+ return -ENOSYS;
+ if (chip->flags & DM_I2C_CHIP_RD_ADDRESS)
+ return i2c_read_bytewise(dev, offset, buffer, len);
+ ptr = msg;
+ if (!i2c_setup_offset(chip, offset, offset_buf, ptr))
+ ptr++;
+
+ if (len) {
+ ptr->addr = chip->chip_addr;
+ ptr->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0;
+ ptr->flags |= I2C_M_RD;
+ ptr->len = len;
+ ptr->buf = buffer;
+ ptr++;
+ }
+ msg_count = ptr - msg;
+
+ return ops->xfer(bus, msg, msg_count);
+}
+
+int i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct i2c_msg msg[1];
+
+ if (!ops->xfer)
+ return -ENOSYS;
+
+ if (chip->flags & DM_I2C_CHIP_WR_ADDRESS)
+ return i2c_write_bytewise(dev, offset, buffer, len);
+ /*
+ * The simple approach would be to send two messages here: one to
+ * set the offset and one to write the bytes. However some drivers
+ * will not be expecting this, and some chips won't like how the
+ * driver presents this on the I2C bus.
+ *
+ * The API does not support separate offset and data. We could extend
+ * it with a flag indicating that there is data in the next message
+ * that needs to be processed in the same transaction. We could
+ * instead add an additional buffer to each message. For now, handle
+ * this in the uclass since it isn't clear what the impact on drivers
+ * would be with this extra complication. Unfortunately this means
+ * copying the message.
+ *
+ * Use the stack for small messages, malloc() for larger ones. We
+ * need to allow space for the offset (up to 4 bytes) and the message
+ * itself.
+ */
+ if (len < 64) {
+ uint8_t buf[I2C_MAX_OFFSET_LEN + len];
+
+ i2c_setup_offset(chip, offset, buf, msg);
+ msg->len += len;
+ memcpy(buf + chip->offset_len, buffer, len);
+
+ return ops->xfer(bus, msg, 1);
+ } else {
+ uint8_t *buf;
+ int ret;
+
+ buf = malloc(I2C_MAX_OFFSET_LEN + len);
+ if (!buf)
+ return -ENOMEM;
+ i2c_setup_offset(chip, offset, buf, msg);
+ msg->len += len;
+ memcpy(buf + chip->offset_len, buffer, len);
+
+ ret = ops->xfer(bus, msg, 1);
+ free(buf);
+ return ret;
+ }
+}
+
+/**
+ * i2c_probe_chip() - probe for a chip on a bus
+ *
+ * @bus: Bus to probe
+ * @chip_addr: Chip address to probe
+ * @flags: Flags for the chip
+ * @return 0 if found, -ENOSYS if the driver is invalid, -EREMOTEIO if the chip
+ * does not respond to probe
+ */
+static int i2c_probe_chip(struct udevice *bus, uint chip_addr,
+ enum dm_i2c_chip_flags chip_flags)
+{
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct i2c_msg msg[1];
+ int ret;
+
+ if (ops->probe_chip) {
+ ret = ops->probe_chip(bus, chip_addr, chip_flags);
+ if (!ret || ret != -ENOSYS)
+ return ret;
+ }
+
+ if (!ops->xfer)
+ return -ENOSYS;
+
+ /* Probe with a zero-length message */
+ msg->addr = chip_addr;
+ msg->flags = chip_flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0;
+ msg->len = 0;
+ msg->buf = NULL;
+
+ return ops->xfer(bus, msg, 1);
+}
+
+static int i2c_bind_driver(struct udevice *bus, uint chip_addr,
+ struct udevice **devp)
+{
+ struct dm_i2c_chip chip;
+ char name[30], *str;
+ struct udevice *dev;
+ int ret;
+
+ snprintf(name, sizeof(name), "generic_%x", chip_addr);
+ str = strdup(name);
+ ret = device_bind_driver(bus, "i2c_generic_chip_drv", str, &dev);
+ debug("%s: device_bind_driver: ret=%d\n", __func__, ret);
+ if (ret)
+ goto err_bind;
+
+ /* Tell the device what we know about it */
+ memset(&chip, '\0', sizeof(chip));
+ chip.chip_addr = chip_addr;
+ chip.offset_len = 1; /* we assume */
+ ret = device_probe_child(dev, &chip);
+ debug("%s: device_probe_child: ret=%d\n", __func__, ret);
+ if (ret)
+ goto err_probe;
+
+ *devp = dev;
+ return 0;
+
+err_probe:
+ device_unbind(dev);
+err_bind:
+ free(str);
+ return ret;
+}
+
+int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ debug("%s: Searching bus '%s' for address %02x: ", __func__,
+ bus->name, chip_addr);
+ for (device_find_first_child(bus, &dev); dev;
+ device_find_next_child(&dev)) {
+ struct dm_i2c_chip store;
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ int ret;
+
+ if (!chip) {
+ chip = &store;
+ i2c_chip_ofdata_to_platdata(gd->fdt_blob,
+ dev->of_offset, chip);
+ }
+ if (chip->chip_addr == chip_addr) {
+ ret = device_probe(dev);
+ debug("found, ret=%d\n", ret);
+ if (ret)
+ return ret;
+ *devp = dev;
+ return 0;
+ }
+ }
+ debug("not found\n");
+ return i2c_bind_driver(bus, chip_addr, devp);
+}
+
+int i2c_get_chip_for_busnum(int busnum, int chip_addr, struct udevice **devp)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
+ if (ret) {
+ debug("Cannot find I2C bus %d\n", busnum);
+ return ret;
+ }
+ ret = i2c_get_chip(bus, chip_addr, devp);
+ if (ret) {
+ debug("Cannot find I2C chip %02x on bus %d\n", chip_addr,
+ busnum);
+ return ret;
+ }
+
+ return 0;
+}
+
+int i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
+ struct udevice **devp)
+{
+ int ret;
+
+ *devp = NULL;
+
+ /* First probe that chip */
+ ret = i2c_probe_chip(bus, chip_addr, chip_flags);
+ debug("%s: bus='%s', address %02x, ret=%d\n", __func__, bus->name,
+ chip_addr, ret);
+ if (ret)
+ return ret;
+
+ /* The chip was found, see if we have a driver, and probe it */
+ ret = i2c_get_chip(bus, chip_addr, devp);
+ debug("%s: i2c_get_chip: ret=%d\n", __func__, ret);
+
+ return ret;
+}
+
+int i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct dm_i2c_bus *i2c = bus->uclass_priv;
+ int ret;
+
+ /*
+ * If we have a method, call it. If not then the driver probably wants
+ * to deal with speed changes on the next transfer. It can easily read
+ * the current speed from this uclass
+ */
+ if (ops->set_bus_speed) {
+ ret = ops->set_bus_speed(bus, speed);
+ if (ret)
+ return ret;
+ }
+ i2c->speed_hz = speed;
+
+ return 0;
+}
+
+/*
+ * i2c_get_bus_speed:
+ *
+ * Returns speed of selected I2C bus in Hz
+ */
+int i2c_get_bus_speed(struct udevice *bus)
+{
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct dm_i2c_bus *i2c = bus->uclass_priv;
+
+ if (!ops->get_bus_speed)
+ return i2c->speed_hz;
+
+ return ops->get_bus_speed(bus);
+}
+
+int i2c_set_chip_flags(struct udevice *dev, uint flags)
+{
+ struct udevice *bus = dev->parent;
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ int ret;
+
+ if (ops->set_flags) {
+ ret = ops->set_flags(dev, flags);
+ if (ret)
+ return ret;
+ }
+ chip->flags = flags;
+
+ return 0;
+}
+
+int i2c_get_chip_flags(struct udevice *dev, uint *flagsp)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+
+ *flagsp = chip->flags;
+
+ return 0;
+}
+
+int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+
+ if (offset_len > I2C_MAX_OFFSET_LEN)
+ return -EINVAL;
+ chip->offset_len = offset_len;
+
+ return 0;
+}
+
+int i2c_deblock(struct udevice *bus)
+{
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+
+ /*
+ * We could implement a software deblocking here if we could get
+ * access to the GPIOs used by I2C, and switch them to GPIO mode
+ * and then back to I2C. This is somewhat beyond our powers in
+ * driver model at present, so for now just fail.
+ *
+ * See https://patchwork.ozlabs.org/patch/399040/
+ */
+ if (!ops->deblock)
+ return -ENOSYS;
+
+ return ops->deblock(bus);
+}
+
+int i2c_chip_ofdata_to_platdata(const void *blob, int node,
+ struct dm_i2c_chip *chip)
+{
+ chip->offset_len = 1; /* default */
+ chip->flags = 0;
+ chip->chip_addr = fdtdec_get_int(gd->fdt_blob, node, "reg", -1);
+ if (chip->chip_addr == -1) {
+ debug("%s: I2C Node '%s' has no 'reg' property\n", __func__,
+ fdt_get_name(blob, node, NULL));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int i2c_post_probe(struct udevice *dev)
+{
+ struct dm_i2c_bus *i2c = dev->uclass_priv;
+
+ i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 100000);
+
+ return i2c_set_bus_speed(dev, i2c->speed_hz);
+}
+
+int i2c_post_bind(struct udevice *dev)
+{
+ /* Scan the bus for devices */
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+UCLASS_DRIVER(i2c) = {
+ .id = UCLASS_I2C,
+ .name = "i2c",
+ .per_device_auto_alloc_size = sizeof(struct dm_i2c_bus),
+ .post_bind = i2c_post_bind,
+ .post_probe = i2c_post_probe,
+};
+
+UCLASS_DRIVER(i2c_generic) = {
+ .id = UCLASS_I2C_GENERIC,
+ .name = "i2c_generic",
+};
+
+U_BOOT_DRIVER(i2c_generic_chip_drv) = {
+ .name = "i2c_generic_chip_drv",
+ .id = UCLASS_I2C_GENERIC,
+};
--- /dev/null
+/*
+ * Simulate an I2C port
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <asm/test.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dm_sandbox_i2c_emul_priv {
+ struct udevice *emul;
+};
+
+static int get_emul(struct udevice *dev, struct udevice **devp,
+ struct dm_i2c_ops **opsp)
+{
+ struct dm_i2c_chip *priv;
+ int ret;
+
+ *devp = NULL;
+ *opsp = NULL;
+ priv = dev_get_parentdata(dev);
+ if (!priv->emul) {
+ ret = dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset,
+ false);
+ if (ret)
+ return ret;
+
+ ret = device_get_child(dev, 0, &priv->emul);
+ if (ret)
+ return ret;
+ }
+ *devp = priv->emul;
+ *opsp = i2c_get_ops(priv->emul);
+
+ return 0;
+}
+
+static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct dm_i2c_bus *i2c = bus->uclass_priv;
+ struct dm_i2c_ops *ops;
+ struct udevice *emul, *dev;
+ bool is_read;
+ int ret;
+
+ /* Special test code to return success but with no emulation */
+ if (msg->addr == SANDBOX_I2C_TEST_ADDR)
+ return 0;
+
+ ret = i2c_get_chip(bus, msg->addr, &dev);
+ if (ret)
+ return ret;
+
+ ret = get_emul(dev, &emul, &ops);
+ if (ret)
+ return ret;
+
+ /*
+ * For testing, don't allow writing above 100KHz for writes and
+ * 400KHz for reads
+ */
+ is_read = nmsgs > 1;
+ if (i2c->speed_hz > (is_read ? 400000 : 100000))
+ return -EINVAL;
+ return ops->xfer(emul, msg, nmsgs);
+}
+
+static const struct dm_i2c_ops sandbox_i2c_ops = {
+ .xfer = sandbox_i2c_xfer,
+};
+
+static int sandbox_i2c_child_pre_probe(struct udevice *dev)
+{
+ struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
+
+ /* Ignore our test address */
+ if (i2c_chip->chip_addr == SANDBOX_I2C_TEST_ADDR)
+ return 0;
+ if (dev->of_offset == -1)
+ return 0;
+
+ return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
+ i2c_chip);
+}
+
+static const struct udevice_id sandbox_i2c_ids[] = {
+ { .compatible = "sandbox,i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_sandbox) = {
+ .name = "i2c_sandbox",
+ .id = UCLASS_I2C,
+ .of_match = sandbox_i2c_ids,
+ .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+ .child_pre_probe = sandbox_i2c_child_pre_probe,
+ .ops = &sandbox_i2c_ops,
+};
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
+enum i2c_type {
+ TYPE_114,
+ TYPE_STD,
+ TYPE_DVC,
+};
+
/* Information about i2c controller */
struct i2c_bus {
int id;
int pinmux_config;
struct i2c_control *control;
struct i2c_ctlr *regs;
- int is_dvc; /* DVC type, rather than I2C */
- int is_scs; /* single clock source (T114+) */
+ enum i2c_type type;
int inited; /* bus is inited */
};
-static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
-
static void set_packet_mode(struct i2c_bus *i2c_bus)
{
u32 config;
config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
- if (i2c_bus->is_dvc) {
+ if (i2c_bus->type == TYPE_DVC) {
struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
writel(config, &dvc->cnfg);
static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
+ if (!i2c_bus->speed)
+ return;
+ debug("%s: speed=%d\n", __func__, i2c_bus->speed);
/*
* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
* here, in section 23.3.1, but in fact we seem to need a factor of
clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
i2c_bus->speed * 2 * 8);
- if (i2c_bus->is_scs) {
+ if (i2c_bus->type == TYPE_114) {
/*
* T114 I2C went to a single clock source for standard/fast and
* HS clock speeds. The new clock rate setting calculation is:
i2c_reset_controller(i2c_bus);
/* Configure I2C controller. */
- if (i2c_bus->is_dvc) { /* only for DVC I2C */
+ if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
return error;
}
-static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
+static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
u32 len, bool end_with_repeated_start)
{
int error;
trans_info.num_bytes = len;
trans_info.is_10bit_address = 0;
- error = send_recv_packets(bus, &trans_info);
+ error = send_recv_packets(i2c_bus, &trans_info);
if (error)
debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
return error;
}
-static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data,
+static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
u32 len)
{
int error;
trans_info.num_bytes = len;
trans_info.is_10bit_address = 0;
- error = send_recv_packets(bus, &trans_info);
+ error = send_recv_packets(i2c_bus, &trans_info);
if (error)
debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
return error;
}
-#ifndef CONFIG_OF_CONTROL
-#error "Please enable device tree support to use this driver"
-#endif
-
-/**
- * Check that a bus number is valid and return a pointer to it
- *
- * @param bus_num Bus number to check / return
- * @return pointer to bus, if valid, else NULL
- */
-static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap)
+static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
- struct i2c_bus *bus;
+ struct i2c_bus *i2c_bus = dev_get_priv(dev);
- bus = &i2c_controllers[adap->hwadapnr];
- if (!bus->inited) {
- debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
- return NULL;
- }
-
- return bus;
-}
-
-static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-{
- struct i2c_bus *bus;
-
- bus = tegra_i2c_get_bus(adap);
- if (!bus)
- return 0;
- bus->speed = speed;
- i2c_init_controller(bus);
+ i2c_bus->speed = speed;
+ i2c_init_controller(i2c_bus);
return 0;
}
-static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
+static int tegra_i2c_probe(struct udevice *dev)
{
+ struct i2c_bus *i2c_bus = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ bool is_dvc;
+
+ i2c_bus->id = dev->seq;
+ i2c_bus->type = dev_get_of_data(dev);
i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
/*
* far no one needs anything other than the default.
*/
i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
- i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
i2c_bus->periph_id = clock_decode_periph_id(blob, node);
/*
* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
*/
if (i2c_bus->periph_id == -1)
- return -FDT_ERR_NOTFOUND;
+ return -EINVAL;
- return 0;
-}
-
-/*
- * Process a list of nodes, adding them to our list of I2C ports.
- *
- * @param blob fdt blob
- * @param node_list list of nodes to process (any <=0 are ignored)
- * @param count number of nodes to process
- * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
- * @param is_scs 1 if this HW uses a single clock source (T114+)
- * @return 0 if ok, -1 on error
- */
-static int process_nodes(const void *blob, int node_list[], int count,
- int is_dvc, int is_scs)
-{
- struct i2c_bus *i2c_bus;
- int i;
-
- /* build the i2c_controllers[] for each controller */
- for (i = 0; i < count; i++) {
- int node = node_list[i];
-
- if (node <= 0)
- continue;
-
- i2c_bus = &i2c_controllers[i];
- i2c_bus->id = i;
-
- if (i2c_get_config(blob, node, i2c_bus)) {
- printf("i2c_init_board: failed to decode bus %d\n", i);
- return -1;
- }
-
- i2c_bus->is_scs = is_scs;
-
- i2c_bus->is_dvc = is_dvc;
- if (is_dvc) {
- i2c_bus->control =
- &((struct dvc_ctlr *)i2c_bus->regs)->control;
- } else {
- i2c_bus->control = &i2c_bus->regs->control;
- }
- debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
- is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
- i2c_bus->periph_id, i2c_bus->speed);
- i2c_init_controller(i2c_bus);
- debug("ok\n");
- i2c_bus->inited = 1;
-
- /* Mark position as used */
- node_list[i] = -1;
+ is_dvc = dev_get_of_data(dev) == TYPE_DVC;
+ if (is_dvc) {
+ i2c_bus->control =
+ &((struct dvc_ctlr *)i2c_bus->regs)->control;
+ } else {
+ i2c_bus->control = &i2c_bus->regs->control;
}
+ i2c_init_controller(i2c_bus);
+ debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
+ is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
+ i2c_bus->periph_id, i2c_bus->speed);
return 0;
}
-/* Sadly there is no error return from this function */
-void i2c_init_board(void)
-{
- int node_list[TEGRA_I2C_NUM_CONTROLLERS];
- const void *blob = gd->fdt_blob;
- int count;
-
- /* First check for newer (T114+) I2C ports */
- count = fdtdec_find_aliases_for_id(blob, "i2c",
- COMPAT_NVIDIA_TEGRA114_I2C, node_list,
- TEGRA_I2C_NUM_CONTROLLERS);
- if (process_nodes(blob, node_list, count, 0, 1))
- return;
-
- /* Now get the older (T20/T30) normal I2C ports */
- count = fdtdec_find_aliases_for_id(blob, "i2c",
- COMPAT_NVIDIA_TEGRA20_I2C, node_list,
- TEGRA_I2C_NUM_CONTROLLERS);
- if (process_nodes(blob, node_list, count, 0, 0))
- return;
-
- /* Now look for dvc ports */
- count = fdtdec_add_aliases_for_id(blob, "i2c",
- COMPAT_NVIDIA_TEGRA20_DVC, node_list,
- TEGRA_I2C_NUM_CONTROLLERS);
- if (process_nodes(blob, node_list, count, 1, 0))
- return;
-}
-
-static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- /* No i2c support prior to relocation */
- if (!(gd->flags & GD_FLG_RELOC))
- return;
-
- /* This will override the speed selected in the fdt for that port */
- debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
- i2c_set_bus_speed(speed);
-}
-
/* i2c write version without the register address */
-static int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
+static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
int len, bool end_with_repeated_start)
{
int rc;
debug("\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra_i2c_write_data(bus, chip << 1, buffer, len,
+ rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
end_with_repeated_start);
if (rc)
debug("i2c_write_data(): rc=%d\n", rc);
}
/* i2c read version without the register address */
-static int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
- int len)
+static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
+ int len)
{
int rc;
debug("inside i2c_read_data():\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
+ rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
if (rc) {
debug("i2c_read_data(): rc=%d\n", rc);
return rc;
}
/* Probe to see if a chip is present. */
-static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
+static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
{
- struct i2c_bus *bus;
+ struct i2c_bus *i2c_bus = dev_get_priv(bus);
int rc;
- uchar reg;
-
- debug("i2c_probe: addr=0x%x\n", chip);
- bus = tegra_i2c_get_bus(adap);
- if (!bus)
- return 1;
- reg = 0;
- rc = i2c_write_data(bus, chip, ®, 1, false);
- if (rc) {
- debug("Error probing 0x%x.\n", chip);
- return 1;
- }
- return 0;
-}
+ u8 reg;
-static int i2c_addr_ok(const uint addr, const int alen)
-{
- /* We support 7 or 10 bit addresses, so one or two bytes each */
- return alen == 1 || alen == 2;
+ /* Shift 7-bit address over for lower-level i2c functions */
+ rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg),
+ false);
+
+ return rc;
}
-/* Read bytes */
-static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
+static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+ int nmsgs)
{
- struct i2c_bus *bus;
- uint offset;
- int i;
-
- debug("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
- chip, addr, alen, len);
- bus = tegra_i2c_get_bus(adap);
- if (!bus)
- return 1;
- if (!i2c_addr_ok(addr, alen)) {
- debug("i2c_read: Bad address %x.%d.\n", addr, alen);
- return 1;
- }
- for (offset = 0; offset < len; offset++) {
- if (alen) {
- uchar data[alen];
- for (i = 0; i < alen; i++) {
- data[alen - i - 1] =
- (addr + offset) >> (8 * i);
- }
- if (i2c_write_data(bus, chip, data, alen, true)) {
- debug("i2c_read: error sending (0x%x)\n",
- addr);
- return 1;
- }
+ struct i2c_bus *i2c_bus = dev_get_priv(bus);
+ int ret;
+
+ debug("i2c_xfer: %d messages\n", nmsgs);
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
+
+ debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
+ if (msg->flags & I2C_M_RD) {
+ ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
+ msg->len);
+ } else {
+ ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
+ msg->len, next_is_read);
}
- if (i2c_read_data(bus, chip, buffer + offset, 1)) {
- debug("i2c_read: error reading (0x%x)\n", addr);
- return 1;
+ if (ret) {
+ debug("i2c_write: error sending\n");
+ return -EREMOTEIO;
}
}
return 0;
}
-/* Write bytes */
-static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
+int tegra_i2c_get_dvc_bus(struct udevice **busp)
{
- struct i2c_bus *bus;
- uint offset;
- int i;
-
- debug("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
- chip, addr, alen, len);
- bus = tegra_i2c_get_bus(adap);
- if (!bus)
- return 1;
- if (!i2c_addr_ok(addr, alen)) {
- debug("i2c_write: Bad address %x.%d.\n", addr, alen);
- return 1;
- }
- for (offset = 0; offset < len; offset++) {
- uchar data[alen + 1];
- for (i = 0; i < alen; i++)
- data[alen - i - 1] = (addr + offset) >> (8 * i);
- data[alen] = buffer[offset];
- if (i2c_write_data(bus, chip, data, alen + 1, false)) {
- debug("i2c_write: error sending (0x%x)\n", addr);
- return 1;
+ struct udevice *bus;
+
+ for (uclass_first_device(UCLASS_I2C, &bus);
+ bus;
+ uclass_next_device(&bus)) {
+ if (dev_get_of_data(bus) == TYPE_DVC) {
+ *busp = bus;
+ return 0;
}
}
- return 0;
+ return -ENODEV;
}
-int tegra_i2c_get_dvc_bus_num(void)
-{
- int i;
+static const struct dm_i2c_ops tegra_i2c_ops = {
+ .xfer = tegra_i2c_xfer,
+ .probe_chip = tegra_i2c_probe_chip,
+ .set_bus_speed = tegra_i2c_set_bus_speed,
+};
- for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
- struct i2c_bus *bus = &i2c_controllers[i];
+static int tegra_i2c_child_pre_probe(struct udevice *dev)
+{
+ struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
- if (bus->inited && bus->is_dvc)
- return i;
- }
+ if (dev->of_offset == -1)
+ return 0;
+ return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
+ i2c_chip);
+}
- return -1;
+static int tegra_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ return 0;
}
-/*
- * Register soft i2c adapters
- */
-U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
- tegra_i2c_read, tegra_i2c_write,
- tegra_i2c_set_bus_speed, 100000, 0, 0)
-U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
- tegra_i2c_read, tegra_i2c_write,
- tegra_i2c_set_bus_speed, 100000, 0, 1)
-U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
- tegra_i2c_read, tegra_i2c_write,
- tegra_i2c_set_bus_speed, 100000, 0, 2)
-U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
- tegra_i2c_read, tegra_i2c_write,
- tegra_i2c_set_bus_speed, 100000, 0, 3)
-#if TEGRA_I2C_NUM_CONTROLLERS > 4
-U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
- tegra_i2c_read, tegra_i2c_write,
- tegra_i2c_set_bus_speed, 100000, 0, 4)
-#endif
+static const struct udevice_id tegra_i2c_ids[] = {
+ { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
+ { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
+ { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_tegra) = {
+ .name = "i2c_tegra",
+ .id = UCLASS_I2C,
+ .of_match = tegra_i2c_ids,
+ .ofdata_to_platdata = tegra_i2c_ofdata_to_platdata,
+ .probe = tegra_i2c_probe,
+ .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+ .child_pre_probe = tegra_i2c_child_pre_probe,
+ .priv_auto_alloc_size = sizeof(struct i2c_bus),
+ .ops = &tegra_i2c_ops,
+};
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_GPIO_LED) += gpio_led.o
+obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_PDSP188x) += pdsp188x.o
+ifdef CONFIG_DM_I2C
+obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
+endif
+obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <i2c_eeprom.h>
+
+static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf,
+ int size)
+{
+ return -ENODEV;
+}
+
+static int i2c_eeprom_write(struct udevice *dev, int offset,
+ const uint8_t *buf, int size)
+{
+ return -ENODEV;
+}
+
+struct i2c_eeprom_ops i2c_eeprom_std_ops = {
+ .read = i2c_eeprom_read,
+ .write = i2c_eeprom_write,
+};
+
+int i2c_eeprom_std_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct udevice_id i2c_eeprom_std_ids[] = {
+ { .compatible = "i2c-eeprom" },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_eeprom_std) = {
+ .name = "i2c_eeprom",
+ .id = UCLASS_I2C_EEPROM,
+ .of_match = i2c_eeprom_std_ids,
+ .probe = i2c_eeprom_std_probe,
+ .priv_auto_alloc_size = sizeof(struct i2c_eeprom),
+ .ops = &i2c_eeprom_std_ops,
+};
+
+UCLASS_DRIVER(i2c_eeprom) = {
+ .id = UCLASS_I2C_EEPROM,
+ .name = "i2c_eeprom",
+};
--- /dev/null
+/*
+ * Simulate an I2C eeprom
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <asm/test.h>
+
+#ifdef DEBUG
+#define debug_buffer print_buffer
+#else
+#define debug_buffer(x, ...)
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sandbox_i2c_flash_plat_data {
+ enum sandbox_i2c_eeprom_test_mode test_mode;
+ const char *filename;
+ int offset_len; /* Length of an offset in bytes */
+ int size; /* Size of data buffer */
+};
+
+struct sandbox_i2c_flash {
+ uint8_t *data;
+};
+
+void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
+ enum sandbox_i2c_eeprom_test_mode mode)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+
+ plat->test_mode = mode;
+}
+
+void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+
+ plat->offset_len = offset_len;
+}
+
+static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct sandbox_i2c_flash *priv = dev_get_priv(emul);
+ uint offset = 0;
+
+ debug("\n%s\n", __func__);
+ debug_buffer(0, priv->data, 1, 16, 0);
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ struct sandbox_i2c_flash_plat_data *plat =
+ dev_get_platdata(emul);
+ int len;
+ u8 *ptr;
+
+ if (!plat->size)
+ return -ENODEV;
+ if (msg->addr + msg->len > plat->size) {
+ debug("%s: Address %x, len %x is outside range 0..%x\n",
+ __func__, msg->addr, msg->len, plat->size);
+ return -EINVAL;
+ }
+ len = msg->len;
+ debug(" %s: msg->len=%d",
+ msg->flags & I2C_M_RD ? "read" : "write",
+ msg->len);
+ if (msg->flags & I2C_M_RD) {
+ if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE)
+ len = 1;
+ debug(", offset %x, len %x: ", offset, len);
+ memcpy(msg->buf, priv->data + offset, len);
+ memset(msg->buf + len, '\xff', msg->len - len);
+ debug_buffer(0, msg->buf, 1, msg->len, 0);
+ } else if (len >= plat->offset_len) {
+ int i;
+
+ ptr = msg->buf;
+ for (i = 0; i < plat->offset_len; i++, len--)
+ offset = (offset << 8) | *ptr++;
+ debug(", set offset %x: ", offset);
+ debug_buffer(0, msg->buf, 1, msg->len, 0);
+ if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE)
+ len = min(len, 1);
+
+ /* For testing, map offsets into our limited buffer */
+ for (i = 24; i > 0; i -= 8) {
+ if (offset > (1 << i)) {
+ offset = (offset >> i) |
+ (offset & ((1 << i) - 1));
+ offset += i;
+ }
+ }
+ memcpy(priv->data + offset, ptr, len);
+ }
+ }
+ debug_buffer(0, priv->data, 1, 16, 0);
+
+ return 0;
+}
+
+struct dm_i2c_ops sandbox_i2c_emul_ops = {
+ .xfer = sandbox_i2c_eeprom_xfer,
+};
+
+static int sandbox_i2c_eeprom_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+
+ plat->size = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "sandbox,size", 32);
+ plat->filename = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ "sandbox,filename", NULL);
+ if (!plat->filename) {
+ debug("%s: No filename for device '%s'\n", __func__,
+ dev->name);
+ return -EINVAL;
+ }
+ plat->test_mode = SIE_TEST_MODE_NONE;
+ plat->offset_len = 1;
+
+ return 0;
+}
+
+static int sandbox_i2c_eeprom_probe(struct udevice *dev)
+{
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash *priv = dev_get_priv(dev);
+
+ priv->data = calloc(1, plat->size);
+ if (!priv->data)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int sandbox_i2c_eeprom_remove(struct udevice *dev)
+{
+ struct sandbox_i2c_flash *priv = dev_get_priv(dev);
+
+ free(priv->data);
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_i2c_ids[] = {
+ { .compatible = "sandbox,i2c-eeprom" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_i2c_emul) = {
+ .name = "sandbox_i2c_eeprom_emul",
+ .id = UCLASS_I2C_EMUL,
+ .of_match = sandbox_i2c_ids,
+ .ofdata_to_platdata = sandbox_i2c_eeprom_ofdata_to_platdata,
+ .probe = sandbox_i2c_eeprom_probe,
+ .remove = sandbox_i2c_eeprom_remove,
+ .priv_auto_alloc_size = sizeof(struct sandbox_i2c_flash),
+ .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_flash_plat_data),
+ .ops = &sandbox_i2c_emul_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pnp_def.h>
+
+static void pnp_enter_conf_state(u16 dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(u16 dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0xaa, port);
+}
+
+void lpc47m_enable_serial(u16 dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
dwmci_writel(host, DWMCI_CTYPE, ctype);
regs = dwmci_readl(host, DWMCI_UHS_REG);
- if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ if (mmc->ddr_mode)
regs |= DWMCI_DDR_MODE;
else
regs &= DWMCI_DDR_MODE;
host->get_mmc_clk = exynos_dwmci_get_clk;
/* Add the mmc channel to be registered with mmc core */
if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
- debug("dwmmc%d registration failed\n", index);
+ printf("DWMMC%d registration failed\n", index);
return -1;
}
return 0;
flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
err = exynos_pinmux_config(host->dev_id, flag);
if (err) {
- debug("DWMMC not configure\n");
+ printf("DWMMC%d not configure\n", index);
return err;
}
/* Extract device id for each mmc channel */
host->dev_id = pinmux_decode_periph_id(blob, node);
+ host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
+ if (host->dev_index == host->dev_id)
+ host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
+
+
/* Get the bus width from the device node */
host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (host->buswidth <= 0) {
- debug("DWMMC: Can't get bus-width\n");
+ printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
return -EINVAL;
}
- host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
- if (host->dev_index == host->dev_id)
- host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
-
/* Set the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
- debug("DWMMC: Can't get base address\n");
+ printf("DWMMC%d: Can't get base address\n", host->dev_index);
return -EINVAL;
}
host->ioaddr = (void *)base;
/* Extract the timing info from the node */
err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
if (err) {
- debug("Can't get sdr-timings for devider\n");
+ printf("DWMMC%d: Can't get sdr-timings for devider\n",
+ host->dev_index);
return -EINVAL;
}
host = &dwmci_host[i];
err = exynos_dwmci_get_config(blob, node, host);
if (err) {
- debug("%s: failed to decode dev %d\n", __func__, i);
+ printf("%s: failed to decode dev %d\n", __func__, i);
return err;
}
{
struct mmc_cmd cmd;
- if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ if (mmc->ddr_mode)
return 0;
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
char cardtype;
int err;
- mmc->card_caps = 0;
+ mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
if (mmc_host_is_spi(mmc))
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
if (cardtype & EXT_CSD_CARD_TYPE_52) {
- if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
mmc->card_caps |= MMC_MODE_DDR_52MHz;
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
} else {
case 6:
mmc->version = MMC_VERSION_4_5;
break;
+ case 7:
+ mmc->version = MMC_VERSION_5_0;
+ break;
}
/*
mmc->erase_grp_size =
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
MMC_MAX_BLOCK_LEN * 1024;
+ /*
+ * if high capacity and partition setting completed
+ * SEC_COUNT is valid even if it is smaller than 2 GiB
+ * JEDEC Standard JESD84-B45, 6.2.4
+ */
+ if (mmc->high_capacity &&
+ (ext_csd[EXT_CSD_PARTITION_SETTING] &
+ EXT_CSD_PARTITION_SETTING_COMPLETED)) {
+ capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
+ (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
+ (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
+ (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
+ capacity *= MMC_MAX_BLOCK_LEN;
+ mmc->capacity_user = capacity;
+ }
} else {
/* Calculate the group size from the csd value. */
int erase_gsz, erase_gmul;
/* An array to map CSD bus widths to host cap bits */
static unsigned ext_to_hostcaps[] = {
- [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
- [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
+ [EXT_CSD_DDR_BUS_WIDTH_4] =
+ MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
+ [EXT_CSD_DDR_BUS_WIDTH_8] =
+ MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
};
for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
unsigned int extw = ext_csd_bits[idx];
+ unsigned int caps = ext_to_hostcaps[extw];
/*
- * Check to make sure the controller supports
- * this bus width, if it's more than 1
+ * Check to make sure the card and controller support
+ * these capabilities
*/
- if (extw != EXT_CSD_BUS_WIDTH_1 &&
- !(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
+ if ((mmc->card_caps & caps) != caps)
continue;
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
if (err)
continue;
+ mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
mmc_set_bus_width(mmc, widths[idx]);
err = mmc_send_ext_csd(mmc, test_csd);
+
+ if (err)
+ continue;
+
/* Only compare read only fields */
- if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
- == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
- && ext_csd[EXT_CSD_HC_WP_GRP_SIZE] \
- == test_csd[EXT_CSD_HC_WP_GRP_SIZE] \
- && ext_csd[EXT_CSD_REV] \
- == test_csd[EXT_CSD_REV]
- && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
- == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
- && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
- &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
-
- mmc->card_caps |= ext_to_hostcaps[extw];
+ if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
+ == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
+ ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
+ ext_csd[EXT_CSD_REV]
+ == test_csd[EXT_CSD_REV] &&
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
+ memcmp(&ext_csd[EXT_CSD_SEC_CNT],
+ &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
break;
- }
+ else
+ err = SWITCH_ERR;
}
+ if (err)
+ return err;
+
if (mmc->card_caps & MMC_MODE_HS) {
if (mmc->card_caps & MMC_MODE_HS_52MHz)
mmc->tran_speed = 52000000;
mmc_set_clock(mmc, mmc->tran_speed);
+ /* Fix the block length for DDR mode */
+ if (mmc->ddr_mode) {
+ mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+ mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
+ }
+
/* fill in device description */
mmc->block_dev.lun = 0;
mmc->block_dev.type = 0;
if (err)
return err;
+ mmc->ddr_mode = 0;
mmc_set_bus_width(mmc, 1);
mmc_set_clock(mmc, 1);
printf("%s: %d", m->cfg->name, m->block_dev.dev);
- if (entry->next != &mmc_devices)
- printf("%c ", separator);
+ if (entry->next != &mmc_devices) {
+ printf("%c", separator);
+ if (separator != '\n')
+ puts (" ");
+ }
}
printf("\n");
/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = 1 << 0,
- DUAL_OUTPUT_FAST = 1 << 1,
- DUAL_IO_FAST = 1 << 2,
- QUAD_OUTPUT_FAST = 1 << 3,
- QUAD_IO_FAST = 1 << 4,
+ ARRAY_FAST = 1 << 1,
+ DUAL_OUTPUT_FAST = 1 << 2,
+ DUAL_IO_FAST = 1 << 3,
+ QUAD_OUTPUT_FAST = 1 << 4,
+ QUAD_IO_FAST = 1 << 5,
};
-#define RD_EXTN (ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+/* Normal - Extended - Full command set */
+#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
SECT_4K = 1 << 0,
SECT_32K = 1 << 1,
E_FSR = 1 << 2,
- WR_QPP = 1 << 3,
+ SST_BP = 1 << 3,
+ SST_WP = 1 << 4,
+ WR_QPP = 1 << 5,
};
+#define SST_WR (SST_BP | SST_WP)
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x1000000
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP 0x01 /* Supports AAI word program */
# define CMD_SST_BP 0x02 /* Byte Program */
# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf);
#endif
/**
spi_release_bus(flash->spi);
return ret;
}
+
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf)
+{
+ size_t actual;
+ int ret;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ for (actual = 0; actual < len; actual++) {
+ ret = sst_byte_write(flash, offset, buf + actual);
+ if (ret) {
+ debug("SF: sst byte program failed\n");
+ break;
+ }
+ offset++;
+ }
+
+ if (!ret)
+ ret = spi_flash_cmd_write_disable(flash);
+
+ debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
+ ret ? "failure" : "success", len, offset - actual);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
#endif
/* SPI/QSPI flash device params structure */
const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
+ {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0},
+ {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
+ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0},
{"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
{"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
{"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
{"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0},
{"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
{"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
- {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0, 0},
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0},
+ {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0},
{"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
- {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0},
+ {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
{"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
{"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
{"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
{"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
{"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
{"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
/* Read commands array */
static u8 spi_read_cmds_array[] = {
CMD_READ_ARRAY_SLOW,
+ CMD_READ_ARRAY_FAST,
CMD_READ_DUAL_OUTPUT_FAST,
CMD_READ_DUAL_IO_FAST,
CMD_READ_QUAD_OUTPUT_FAST,
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
- if (params->flags & SST_WP)
- flash->write = sst_write_wp;
+ if (params->flags & SST_WR) {
+ if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ flash->write = sst_write_bp;
+ else
+ flash->write = sst_write_wp;
+ }
#endif
flash->erase = spi_flash_cmd_erase_ops;
flash->read = spi_flash_cmd_read_ops;
#include <asm/io.h>
#include <i2c.h>
-static int bus_num; /* I2C bus we are on */
-#define I2C_ADDRESS 0x34 /* chip requires this address */
-static char inited; /* 1 if we have been inited */
+static struct udevice *tps6586x_dev;
enum {
/* Registers that we access */
int i;
uchar data;
int retval = -1;
- int old_bus_num;
-
- old_bus_num = i2c_get_bus_num();
- i2c_set_bus_num(bus_num);
for (i = 0; i < MAX_I2C_RETRY; ++i) {
- if (!i2c_read(I2C_ADDRESS, reg, 1, &data, 1)) {
+ if (!i2c_read(tps6586x_dev, reg, &data, 1)) {
retval = (int)data;
goto exit;
}
}
exit:
- i2c_set_bus_num(old_bus_num);
debug("pmu_read %x=%x\n", reg, retval);
if (retval < 0)
debug("%s: failed to read register %#x: %d\n", __func__, reg,
{
int i;
int retval = -1;
- int old_bus_num;
-
- old_bus_num = i2c_get_bus_num();
- i2c_set_bus_num(bus_num);
for (i = 0; i < MAX_I2C_RETRY; ++i) {
- if (!i2c_write(I2C_ADDRESS, reg, 1, data, len)) {
+ if (!i2c_write(tps6586x_dev, reg, data, len)) {
retval = 0;
goto exit;
}
}
exit:
- i2c_set_bus_num(old_bus_num);
debug("pmu_write %x=%x: ", reg, retval);
for (i = 0; i < len; i++)
debug("%x ", data[i]);
uchar val;
int ret;
- assert(inited);
+ assert(tps6586x_dev);
ret = tps6586x_read(PFM_MODE);
if (ret != -1) {
val = (uchar)ret;
int sm0, sm1;
int bad;
- assert(inited);
+ assert(tps6586x_dev);
/* get current voltage settings */
if (read_voltages(&sm0, &sm1)) {
return bad ? -1 : 0;
}
-int tps6586x_init(int bus)
+int tps6586x_init(struct udevice *dev)
{
- bus_num = bus;
- inited = 1;
+ tps6586x_dev = dev;
return 0;
}
.probe = pl01x_serial_probe,
.ops = &pl01x_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
+ .priv_auto_alloc_size = sizeof(struct pl01x_priv),
};
#endif
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
--- /dev/null
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include "cadence_qspi.h"
+
+#define CQSPI_STIG_READ 0
+#define CQSPI_STIG_WRITE 1
+#define CQSPI_INDIRECT_READ 2
+#define CQSPI_INDIRECT_WRITE 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cadence_spi_write_speed(struct udevice *bus, uint hz)
+{
+ struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+
+ cadence_qspi_apb_config_baudrate_div(priv->regbase,
+ CONFIG_CQSPI_REF_CLK, hz);
+
+ /* Reconfigure delay timing if speed is changed. */
+ cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
+ plat->tshsl_ns, plat->tsd2d_ns,
+ plat->tchsh_ns, plat->tslch_ns);
+
+ return 0;
+}
+
+/* Calibration sequence to determine the read data capture delay register */
+static int spi_calibration(struct udevice *bus)
+{
+ struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ void *base = priv->regbase;
+ u8 opcode_rdid = 0x9F;
+ unsigned int idcode = 0, temp = 0;
+ int err = 0, i, range_lo = -1, range_hi = -1;
+
+ /* start with slowest clock (1 MHz) */
+ cadence_spi_write_speed(bus, 1000000);
+
+ /* configure the read data capture delay register to 0 */
+ cadence_qspi_apb_readdata_capture(base, 1, 0);
+
+ /* Enable QSPI */
+ cadence_qspi_apb_controller_enable(base);
+
+ /* read the ID which will be our golden value */
+ err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+ 3, (u8 *)&idcode);
+ if (err) {
+ puts("SF: Calibration failed (read)\n");
+ return err;
+ }
+
+ /* use back the intended clock and find low range */
+ cadence_spi_write_speed(bus, plat->max_hz);
+ for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
+ /* Disable QSPI */
+ cadence_qspi_apb_controller_disable(base);
+
+ /* reconfigure the read data capture delay register */
+ cadence_qspi_apb_readdata_capture(base, 1, i);
+
+ /* Enable back QSPI */
+ cadence_qspi_apb_controller_enable(base);
+
+ /* issue a RDID to get the ID value */
+ err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+ 3, (u8 *)&temp);
+ if (err) {
+ puts("SF: Calibration failed (read)\n");
+ return err;
+ }
+
+ /* search for range lo */
+ if (range_lo == -1 && temp == idcode) {
+ range_lo = i;
+ continue;
+ }
+
+ /* search for range hi */
+ if (range_lo != -1 && temp != idcode) {
+ range_hi = i - 1;
+ break;
+ }
+ range_hi = i;
+ }
+
+ if (range_lo == -1) {
+ puts("SF: Calibration failed (low range)\n");
+ return err;
+ }
+
+ /* Disable QSPI for subsequent initialization */
+ cadence_qspi_apb_controller_disable(base);
+
+ /* configure the final value for read data capture delay register */
+ cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
+ debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
+ (range_hi + range_lo) / 2, range_lo, range_hi);
+
+ /* just to ensure we do once only when speed or chip select change */
+ priv->qspi_calibrated_hz = plat->max_hz;
+ priv->qspi_calibrated_cs = spi_chip_select(bus);
+
+ return 0;
+}
+
+static int cadence_spi_set_speed(struct udevice *bus, uint hz)
+{
+ struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ int err;
+
+ /* Disable QSPI */
+ cadence_qspi_apb_controller_disable(priv->regbase);
+
+ cadence_spi_write_speed(bus, hz);
+
+ /* Calibration required for different SCLK speed or chip select */
+ if (priv->qspi_calibrated_hz != plat->max_hz ||
+ priv->qspi_calibrated_cs != spi_chip_select(bus)) {
+ err = spi_calibration(bus);
+ if (err)
+ return err;
+ }
+
+ /* Enable QSPI */
+ cadence_qspi_apb_controller_enable(priv->regbase);
+
+ debug("%s: speed=%d\n", __func__, hz);
+
+ return 0;
+}
+
+static int cadence_spi_probe(struct udevice *bus)
+{
+ struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+
+ priv->regbase = plat->regbase;
+ priv->ahbbase = plat->ahbbase;
+
+ if (!priv->qspi_is_init) {
+ cadence_qspi_apb_controller_init(plat);
+ priv->qspi_is_init = 1;
+ }
+
+ return 0;
+}
+
+static int cadence_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
+ unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
+
+ /* Disable QSPI */
+ cadence_qspi_apb_controller_disable(priv->regbase);
+
+ /* Set SPI mode */
+ cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
+
+ /* Enable QSPI */
+ cadence_qspi_apb_controller_enable(priv->regbase);
+
+ return 0;
+}
+
+static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ void *base = priv->regbase;
+ u8 *cmd_buf = priv->cmd_buf;
+ size_t data_bytes;
+ int err = 0;
+ u32 mode = CQSPI_STIG_WRITE;
+
+ if (flags & SPI_XFER_BEGIN) {
+ /* copy command to local buffer */
+ priv->cmd_len = bitlen / 8;
+ memcpy(cmd_buf, dout, priv->cmd_len);
+ }
+
+ if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
+ /* if start and end bit are set, the data bytes is 0. */
+ data_bytes = 0;
+ } else {
+ data_bytes = bitlen / 8;
+ }
+ debug("%s: len=%d [bytes]\n", __func__, data_bytes);
+
+ /* Set Chip select */
+ cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
+ CONFIG_CQSPI_DECODER);
+
+ if ((flags & SPI_XFER_END) || (flags == 0)) {
+ if (priv->cmd_len == 0) {
+ printf("QSPI: Error, command is empty.\n");
+ return -1;
+ }
+
+ if (din && data_bytes) {
+ /* read */
+ /* Use STIG if no address. */
+ if (!CQSPI_IS_ADDR(priv->cmd_len))
+ mode = CQSPI_STIG_READ;
+ else
+ mode = CQSPI_INDIRECT_READ;
+ } else if (dout && !(flags & SPI_XFER_BEGIN)) {
+ /* write */
+ if (!CQSPI_IS_ADDR(priv->cmd_len))
+ mode = CQSPI_STIG_WRITE;
+ else
+ mode = CQSPI_INDIRECT_WRITE;
+ }
+
+ switch (mode) {
+ case CQSPI_STIG_READ:
+ err = cadence_qspi_apb_command_read(
+ base, priv->cmd_len, cmd_buf,
+ data_bytes, din);
+
+ break;
+ case CQSPI_STIG_WRITE:
+ err = cadence_qspi_apb_command_write(base,
+ priv->cmd_len, cmd_buf,
+ data_bytes, dout);
+ break;
+ case CQSPI_INDIRECT_READ:
+ err = cadence_qspi_apb_indirect_read_setup(plat,
+ priv->cmd_len, cmd_buf);
+ if (!err) {
+ err = cadence_qspi_apb_indirect_read_execute
+ (plat, data_bytes, din);
+ }
+ break;
+ case CQSPI_INDIRECT_WRITE:
+ err = cadence_qspi_apb_indirect_write_setup
+ (plat, priv->cmd_len, cmd_buf);
+ if (!err) {
+ err = cadence_qspi_apb_indirect_write_execute
+ (plat, data_bytes, dout);
+ }
+ break;
+ default:
+ err = -1;
+ break;
+ }
+
+ if (flags & SPI_XFER_END) {
+ /* clear command buffer */
+ memset(cmd_buf, 0, sizeof(priv->cmd_buf));
+ priv->cmd_len = 0;
+ }
+ }
+
+ return err;
+}
+
+static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct cadence_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
+ int subnode;
+ u32 data[4];
+ int ret;
+
+ /* 2 base addresses are needed, lets get them from the DT */
+ ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
+ if (ret) {
+ printf("Error: Can't get base addresses (ret=%d)!\n", ret);
+ return -ENODEV;
+ }
+
+ plat->regbase = (void *)data[0];
+ plat->ahbbase = (void *)data[2];
+
+ /* Use 500KHz as a suitable default */
+ plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+
+ /* All other paramters are embedded in the child node */
+ subnode = fdt_first_subnode(blob, node);
+ if (!subnode) {
+ printf("Error: subnode with SPI flash config missing!\n");
+ return -ENODEV;
+ }
+
+ /* Read other parameters from DT */
+ plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
+ plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
+ plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
+ plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
+ plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
+ plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
+
+ debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
+ __func__, plat->regbase, plat->ahbbase, plat->max_hz,
+ plat->page_size);
+
+ return 0;
+}
+
+static const struct dm_spi_ops cadence_spi_ops = {
+ .xfer = cadence_spi_xfer,
+ .set_speed = cadence_spi_set_speed,
+ .set_mode = cadence_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id cadence_spi_ids[] = {
+ { .compatible = "cadence,qspi" },
+ { }
+};
+
+U_BOOT_DRIVER(cadence_spi) = {
+ .name = "cadence_spi",
+ .id = UCLASS_SPI,
+ .of_match = cadence_spi_ids,
+ .ops = &cadence_spi_ops,
+ .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = cadence_spi_probe,
+};
--- /dev/null
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CADENCE_QSPI_H__
+#define __CADENCE_QSPI_H__
+
+#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
+
+#define CQSPI_NO_DECODER_MAX_CS 4
+#define CQSPI_DECODER_MAX_CS 16
+#define CQSPI_READ_CAPTURE_MAX_DELAY 16
+
+struct cadence_spi_platdata {
+ unsigned int max_hz;
+ void *regbase;
+ void *ahbbase;
+
+ u32 page_size;
+ u32 block_size;
+ u32 tshsl_ns;
+ u32 tsd2d_ns;
+ u32 tchsh_ns;
+ u32 tslch_ns;
+};
+
+struct cadence_spi_priv {
+ void *regbase;
+ void *ahbbase;
+ size_t cmd_len;
+ u8 cmd_buf[32];
+ size_t data_len;
+
+ int qspi_is_init;
+ unsigned int qspi_calibrated_hz;
+ unsigned int qspi_calibrated_cs;
+};
+
+/* Functions call declaration */
+void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
+void cadence_qspi_apb_controller_enable(void *reg_base_addr);
+void cadence_qspi_apb_controller_disable(void *reg_base_addr);
+
+int cadence_qspi_apb_command_read(void *reg_base_addr,
+ unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
+int cadence_qspi_apb_command_write(void *reg_base_addr,
+ unsigned int cmdlen, const u8 *cmdbuf,
+ unsigned int txlen, const u8 *txbuf);
+
+int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
+ unsigned int cmdlen, const u8 *cmdbuf);
+int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
+ unsigned int rxlen, u8 *rxbuf);
+int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
+ unsigned int cmdlen, const u8 *cmdbuf);
+int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
+ unsigned int txlen, const u8 *txbuf);
+
+void cadence_qspi_apb_chipselect(void *reg_base,
+ unsigned int chip_select, unsigned int decoder_enable);
+void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
+ unsigned int clk_pol, unsigned int clk_pha);
+void cadence_qspi_apb_config_baudrate_div(void *reg_base,
+ unsigned int ref_clk_hz, unsigned int sclk_hz);
+void cadence_qspi_apb_delay(void *reg_base,
+ unsigned int ref_clk, unsigned int sclk_hz,
+ unsigned int tshsl_ns, unsigned int tsd2d_ns,
+ unsigned int tchsh_ns, unsigned int tslch_ns);
+void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
+void cadence_qspi_apb_readdata_capture(void *reg_base,
+ unsigned int bypass, unsigned int delay);
+
+#endif /* __CADENCE_QSPI_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of the Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "cadence_qspi.h"
+
+#define CQSPI_REG_POLL_US (1) /* 1us */
+#define CQSPI_REG_RETRY (10000)
+#define CQSPI_POLL_IDLE_RETRY (3)
+
+#define CQSPI_FIFO_WIDTH (4)
+
+/* Controller sram size in word */
+#define CQSPI_REG_SRAM_SIZE_WORD (128)
+#define CQSPI_REG_SRAM_RESV_WORDS (2)
+#define CQSPI_REG_SRAM_PARTITION_WR (1)
+#define CQSPI_REG_SRAM_PARTITION_RD \
+ (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
+#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
+
+/* Transfer mode */
+#define CQSPI_INST_TYPE_SINGLE (0)
+#define CQSPI_INST_TYPE_DUAL (1)
+#define CQSPI_INST_TYPE_QUAD (2)
+
+#define CQSPI_STIG_DATA_LEN_MAX (8)
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF)
+
+#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
+#define CQSPI_DUMMY_BYTES_MAX (4)
+
+
+#define CQSPI_REG_SRAM_FILL_THRESHOLD \
+ ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
+/****************************************************************************
+ * Controller's configuration and status register (offset from QSPI_BASE)
+ ****************************************************************************/
+#define CQSPI_REG_CONFIG 0x00
+#define CQSPI_REG_CONFIG_CLK_POL_LSB 1
+#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
+#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0)
+#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7)
+#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9)
+#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18)
+#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
+#define CQSPI_REG_CONFIG_BAUD_LSB 19
+#define CQSPI_REG_CONFIG_IDLE_LSB 31
+#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
+#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
+
+#define CQSPI_REG_RD_INSTR 0x04
+#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
+#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
+#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
+#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
+#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
+#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
+#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
+#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
+#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
+#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
+
+#define CQSPI_REG_WR_INSTR 0x08
+#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
+
+#define CQSPI_REG_DELAY 0x0C
+#define CQSPI_REG_DELAY_TSLCH_LSB 0
+#define CQSPI_REG_DELAY_TCHSH_LSB 8
+#define CQSPI_REG_DELAY_TSD2D_LSB 16
+#define CQSPI_REG_DELAY_TSHSL_LSB 24
+#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
+#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
+#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
+#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
+
+#define CQSPI_READLCAPTURE 0x10
+#define CQSPI_READLCAPTURE_BYPASS_LSB 0
+#define CQSPI_READLCAPTURE_DELAY_LSB 1
+#define CQSPI_READLCAPTURE_DELAY_MASK 0xF
+
+#define CQSPI_REG_SIZE 0x14
+#define CQSPI_REG_SIZE_ADDRESS_LSB 0
+#define CQSPI_REG_SIZE_PAGE_LSB 4
+#define CQSPI_REG_SIZE_BLOCK_LSB 16
+#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
+#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
+#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
+
+#define CQSPI_REG_SRAMPARTITION 0x18
+#define CQSPI_REG_INDIRECTTRIGGER 0x1C
+
+#define CQSPI_REG_REMAP 0x24
+#define CQSPI_REG_MODE_BIT 0x28
+
+#define CQSPI_REG_SDRAMLEVEL 0x2C
+#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
+#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
+#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
+#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
+
+#define CQSPI_REG_IRQSTATUS 0x40
+#define CQSPI_REG_IRQMASK 0x44
+
+#define CQSPI_REG_INDIRECTRD 0x60
+#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
+#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1)
+#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2)
+#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5)
+
+#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
+#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
+#define CQSPI_REG_INDIRECTRDBYTES 0x6C
+
+#define CQSPI_REG_CMDCTRL 0x90
+#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0)
+#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1)
+#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
+#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
+#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
+#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
+#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
+#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
+#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
+#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
+#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
+#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
+#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
+#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
+#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
+
+#define CQSPI_REG_INDIRECTWR 0x70
+#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
+#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1)
+#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2)
+#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5)
+
+#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
+#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
+#define CQSPI_REG_INDIRECTWRBYTES 0x7C
+
+#define CQSPI_REG_CMDADDRESS 0x94
+#define CQSPI_REG_CMDREADDATALOWER 0xA0
+#define CQSPI_REG_CMDREADDATAUPPER 0xA4
+#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
+#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
+
+#define CQSPI_REG_IS_IDLE(base) \
+ ((readl(base + CQSPI_REG_CONFIG) >> \
+ CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
+
+#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
+ ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
+
+#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
+ (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
+ CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
+
+#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
+ (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
+ CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
+
+static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
+ unsigned int addr_width)
+{
+ unsigned int addr;
+
+ addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
+
+ if (addr_width == 4)
+ addr = (addr << 8) | addr_buf[3];
+
+ return addr;
+}
+
+static void cadence_qspi_apb_read_fifo_data(void *dest,
+ const void *src_ahb_addr, unsigned int bytes)
+{
+ unsigned int temp;
+ int remaining = bytes;
+ unsigned int *dest_ptr = (unsigned int *)dest;
+ unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
+
+ while (remaining > 0) {
+ if (remaining >= CQSPI_FIFO_WIDTH) {
+ *dest_ptr = readl(src_ptr);
+ remaining -= CQSPI_FIFO_WIDTH;
+ } else {
+ /* dangling bytes */
+ temp = readl(src_ptr);
+ memcpy(dest_ptr, &temp, remaining);
+ break;
+ }
+ dest_ptr++;
+ }
+
+ return;
+}
+
+static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
+ const void *src, unsigned int bytes)
+{
+ unsigned int temp;
+ int remaining = bytes;
+ unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
+ unsigned int *src_ptr = (unsigned int *)src;
+
+ while (remaining > 0) {
+ if (remaining >= CQSPI_FIFO_WIDTH) {
+ writel(*src_ptr, dest_ptr);
+ remaining -= sizeof(unsigned int);
+ } else {
+ /* dangling bytes */
+ memcpy(&temp, src_ptr, remaining);
+ writel(temp, dest_ptr);
+ break;
+ }
+ src_ptr++;
+ }
+
+ return;
+}
+
+/* Read from SRAM FIFO with polling SRAM fill level. */
+static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
+ const void *src_addr, unsigned int num_bytes)
+{
+ unsigned int remaining = num_bytes;
+ unsigned int retry;
+ unsigned int sram_level = 0;
+ unsigned char *dest = (unsigned char *)dest_addr;
+
+ while (remaining > 0) {
+ retry = CQSPI_REG_RETRY;
+ while (retry--) {
+ sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
+ if (sram_level)
+ break;
+ udelay(1);
+ }
+
+ if (!retry) {
+ printf("QSPI: No receive data after polling for %d times\n",
+ CQSPI_REG_RETRY);
+ return -1;
+ }
+
+ sram_level *= CQSPI_FIFO_WIDTH;
+ sram_level = sram_level > remaining ? remaining : sram_level;
+
+ /* Read data from FIFO. */
+ cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
+ dest += sram_level;
+ remaining -= sram_level;
+ udelay(1);
+ }
+ return 0;
+}
+
+/* Write to SRAM FIFO with polling SRAM fill level. */
+static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
+ const void *src_addr, unsigned int num_bytes)
+{
+ const void *reg_base = plat->regbase;
+ void *dest_addr = plat->ahbbase;
+ unsigned int retry = CQSPI_REG_RETRY;
+ unsigned int sram_level;
+ unsigned int wr_bytes;
+ unsigned char *src = (unsigned char *)src_addr;
+ int remaining = num_bytes;
+ unsigned int page_size = plat->page_size;
+ unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
+
+ while (remaining > 0) {
+ retry = CQSPI_REG_RETRY;
+ while (retry--) {
+ sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
+ if (sram_level <= sram_threshold_words)
+ break;
+ }
+ if (!retry) {
+ printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
+ sram_level, sram_threshold_words);
+ return -1;
+ }
+ /* Write a page or remaining bytes. */
+ wr_bytes = (remaining > page_size) ?
+ page_size : remaining;
+
+ cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
+ src += wr_bytes;
+ remaining -= wr_bytes;
+ }
+
+ return 0;
+}
+
+void cadence_qspi_apb_controller_enable(void *reg_base)
+{
+ unsigned int reg;
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+ return;
+}
+
+void cadence_qspi_apb_controller_disable(void *reg_base)
+{
+ unsigned int reg;
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+ return;
+}
+
+/* Return 1 if idle, otherwise return 0 (busy). */
+static unsigned int cadence_qspi_wait_idle(void *reg_base)
+{
+ unsigned int start, count = 0;
+ /* timeout in unit of ms */
+ unsigned int timeout = 5000;
+
+ start = get_timer(0);
+ for ( ; get_timer(start) < timeout ; ) {
+ if (CQSPI_REG_IS_IDLE(reg_base))
+ count++;
+ else
+ count = 0;
+ /*
+ * Ensure the QSPI controller is in true idle state after
+ * reading back the same idle status consecutively
+ */
+ if (count >= CQSPI_POLL_IDLE_RETRY)
+ return 1;
+ }
+
+ /* Timeout, still in busy mode. */
+ printf("QSPI: QSPI is still busy after poll for %d times.\n",
+ CQSPI_REG_RETRY);
+ return 0;
+}
+
+void cadence_qspi_apb_readdata_capture(void *reg_base,
+ unsigned int bypass, unsigned int delay)
+{
+ unsigned int reg;
+ cadence_qspi_apb_controller_disable(reg_base);
+
+ reg = readl(reg_base + CQSPI_READLCAPTURE);
+
+ if (bypass)
+ reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+ else
+ reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+
+ reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
+ << CQSPI_READLCAPTURE_DELAY_LSB);
+
+ reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
+ << CQSPI_READLCAPTURE_DELAY_LSB);
+
+ writel(reg, reg_base + CQSPI_READLCAPTURE);
+
+ cadence_qspi_apb_controller_enable(reg_base);
+ return;
+}
+
+void cadence_qspi_apb_config_baudrate_div(void *reg_base,
+ unsigned int ref_clk_hz, unsigned int sclk_hz)
+{
+ unsigned int reg;
+ unsigned int div;
+
+ cadence_qspi_apb_controller_disable(reg_base);
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
+
+ div = ref_clk_hz / sclk_hz;
+
+ if (div > 32)
+ div = 32;
+
+ /* Check if even number. */
+ if ((div & 1)) {
+ div = (div / 2);
+ } else {
+ if (ref_clk_hz % sclk_hz)
+ /* ensure generated SCLK doesn't exceed user
+ specified sclk_hz */
+ div = (div / 2);
+ else
+ div = (div / 2) - 1;
+ }
+
+ debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
+ ref_clk_hz, sclk_hz, div);
+
+ div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
+ reg |= div;
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+ cadence_qspi_apb_controller_enable(reg_base);
+ return;
+}
+
+void cadence_qspi_apb_set_clk_mode(void *reg_base,
+ unsigned int clk_pol, unsigned int clk_pha)
+{
+ unsigned int reg;
+
+ cadence_qspi_apb_controller_disable(reg_base);
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ reg &= ~(1 <<
+ (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
+
+ reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
+ reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
+
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+ cadence_qspi_apb_controller_enable(reg_base);
+ return;
+}
+
+void cadence_qspi_apb_chipselect(void *reg_base,
+ unsigned int chip_select, unsigned int decoder_enable)
+{
+ unsigned int reg;
+
+ cadence_qspi_apb_controller_disable(reg_base);
+
+ debug("%s : chipselect %d decode %d\n", __func__, chip_select,
+ decoder_enable);
+
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ /* docoder */
+ if (decoder_enable) {
+ reg |= CQSPI_REG_CONFIG_DECODE_MASK;
+ } else {
+ reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
+ /* Convert CS if without decoder.
+ * CS0 to 4b'1110
+ * CS1 to 4b'1101
+ * CS2 to 4b'1011
+ * CS3 to 4b'0111
+ */
+ chip_select = 0xF & ~(1 << chip_select);
+ }
+
+ reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
+ << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
+ reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
+ << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+ cadence_qspi_apb_controller_enable(reg_base);
+ return;
+}
+
+void cadence_qspi_apb_delay(void *reg_base,
+ unsigned int ref_clk, unsigned int sclk_hz,
+ unsigned int tshsl_ns, unsigned int tsd2d_ns,
+ unsigned int tchsh_ns, unsigned int tslch_ns)
+{
+ unsigned int ref_clk_ns;
+ unsigned int sclk_ns;
+ unsigned int tshsl, tchsh, tslch, tsd2d;
+ unsigned int reg;
+
+ cadence_qspi_apb_controller_disable(reg_base);
+
+ /* Convert to ns. */
+ ref_clk_ns = (1000000000) / ref_clk;
+
+ /* Convert to ns. */
+ sclk_ns = (1000000000) / sclk_hz;
+
+ /* Plus 1 to round up 1 clock cycle. */
+ tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
+ tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
+ tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
+ tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
+
+ reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
+ << CQSPI_REG_DELAY_TSHSL_LSB);
+ reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
+ << CQSPI_REG_DELAY_TCHSH_LSB);
+ reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
+ << CQSPI_REG_DELAY_TSLCH_LSB);
+ reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
+ << CQSPI_REG_DELAY_TSD2D_LSB);
+ writel(reg, reg_base + CQSPI_REG_DELAY);
+
+ cadence_qspi_apb_controller_enable(reg_base);
+ return;
+}
+
+void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
+{
+ unsigned reg;
+
+ cadence_qspi_apb_controller_disable(plat->regbase);
+
+ /* Configure the device size and address bytes */
+ reg = readl(plat->regbase + CQSPI_REG_SIZE);
+ /* Clear the previous value */
+ reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
+ reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
+ reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
+ reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
+ writel(reg, plat->regbase + CQSPI_REG_SIZE);
+
+ /* Configure the remap address register, no remap */
+ writel(0, plat->regbase + CQSPI_REG_REMAP);
+
+ /* Disable all interrupts */
+ writel(0, plat->regbase + CQSPI_REG_IRQMASK);
+
+ cadence_qspi_apb_controller_enable(plat->regbase);
+ return;
+}
+
+static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
+ unsigned int reg)
+{
+ unsigned int retry = CQSPI_REG_RETRY;
+
+ /* Write the CMDCTRL without start execution. */
+ writel(reg, reg_base + CQSPI_REG_CMDCTRL);
+ /* Start execute */
+ reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
+ writel(reg, reg_base + CQSPI_REG_CMDCTRL);
+
+ while (retry--) {
+ reg = readl(reg_base + CQSPI_REG_CMDCTRL);
+ if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
+ break;
+ udelay(1);
+ }
+
+ if (!retry) {
+ printf("QSPI: flash command execution timeout\n");
+ return -EIO;
+ }
+
+ /* Polling QSPI idle status. */
+ if (!cadence_qspi_wait_idle(reg_base))
+ return -EIO;
+
+ return 0;
+}
+
+/* For command RDID, RDSR. */
+int cadence_qspi_apb_command_read(void *reg_base,
+ unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
+ u8 *rxbuf)
+{
+ unsigned int reg;
+ unsigned int read_len;
+ int status;
+
+ if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
+ printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
+ cmdlen, rxlen);
+ return -EINVAL;
+ }
+
+ reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+
+ reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
+
+ /* 0 means 1 byte. */
+ reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
+ << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
+ status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
+ if (status != 0)
+ return status;
+
+ reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
+
+ /* Put the read value into rx_buf */
+ read_len = (rxlen > 4) ? 4 : rxlen;
+ memcpy(rxbuf, ®, read_len);
+ rxbuf += read_len;
+
+ if (rxlen > 4) {
+ reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
+
+ read_len = rxlen - read_len;
+ memcpy(rxbuf, ®, read_len);
+ }
+ return 0;
+}
+
+/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
+int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
+ const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
+{
+ unsigned int reg = 0;
+ unsigned int addr_value;
+ unsigned int wr_data;
+ unsigned int wr_len;
+
+ if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
+ printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
+ cmdlen, txlen);
+ return -EINVAL;
+ }
+
+ reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+
+ if (cmdlen == 4 || cmdlen == 5) {
+ /* Command with address */
+ reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
+ /* Number of bytes to write. */
+ reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
+ << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
+ /* Get address */
+ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
+ cmdlen >= 5 ? 4 : 3);
+
+ writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
+ }
+
+ if (txlen) {
+ /* writing data = yes */
+ reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
+ reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
+ << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
+
+ wr_len = txlen > 4 ? 4 : txlen;
+ memcpy(&wr_data, txbuf, wr_len);
+ writel(wr_data, reg_base +
+ CQSPI_REG_CMDWRITEDATALOWER);
+
+ if (txlen > 4) {
+ txbuf += wr_len;
+ wr_len = txlen - wr_len;
+ memcpy(&wr_data, txbuf, wr_len);
+ writel(wr_data, reg_base +
+ CQSPI_REG_CMDWRITEDATAUPPER);
+ }
+ }
+
+ /* Execute the command */
+ return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
+}
+
+/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
+int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
+ unsigned int cmdlen, const u8 *cmdbuf)
+{
+ unsigned int reg;
+ unsigned int rd_reg;
+ unsigned int addr_value;
+ unsigned int dummy_clk;
+ unsigned int dummy_bytes;
+ unsigned int addr_bytes;
+
+ /*
+ * Identify addr_byte. All NOR flash device drivers are using fast read
+ * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
+ * With that, the length is in value of 5 or 6. Only FRAM chip from
+ * ramtron using normal read (which won't need dummy byte).
+ * Unlikely NOR flash using normal read due to performance issue.
+ */
+ if (cmdlen >= 5)
+ /* to cater fast read where cmd + addr + dummy */
+ addr_bytes = cmdlen - 2;
+ else
+ /* for normal read (only ramtron as of now) */
+ addr_bytes = cmdlen - 1;
+
+ /* Setup the indirect trigger address */
+ writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
+ plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
+
+ /* Configure SRAM partition for read. */
+ writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
+ CQSPI_REG_SRAMPARTITION);
+
+ /* Configure the opcode */
+ rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
+
+#if (CONFIG_SPI_FLASH_QUAD == 1)
+ /* Instruction and address at DQ0, data at DQ0-3. */
+ rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
+#endif
+
+ /* Get address */
+ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
+ writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+
+ /* The remaining lenght is dummy bytes. */
+ dummy_bytes = cmdlen - addr_bytes - 1;
+ if (dummy_bytes) {
+ if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
+ dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
+
+ rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
+#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
+ writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
+#else
+ writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
+#endif
+
+ /* Convert to clock cycles. */
+ dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
+ /* Need to minus the mode byte (8 clocks). */
+ dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
+
+ if (dummy_clk)
+ rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
+ << CQSPI_REG_RD_INSTR_DUMMY_LSB;
+ }
+
+ writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
+
+ /* set device size */
+ reg = readl(plat->regbase + CQSPI_REG_SIZE);
+ reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
+ reg |= (addr_bytes - 1);
+ writel(reg, plat->regbase + CQSPI_REG_SIZE);
+ return 0;
+}
+
+int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
+ unsigned int rxlen, u8 *rxbuf)
+{
+ unsigned int reg;
+
+ writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
+
+ /* Start the indirect read transfer */
+ writel(CQSPI_REG_INDIRECTRD_START_MASK,
+ plat->regbase + CQSPI_REG_INDIRECTRD);
+
+ if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
+ (const void *)plat->ahbbase, rxlen))
+ goto failrd;
+
+ /* Check flash indirect controller */
+ reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
+ if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
+ reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
+ printf("QSPI: indirect completion status error with reg 0x%08x\n",
+ reg);
+ goto failrd;
+ }
+
+ /* Clear indirect completion status */
+ writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
+ plat->regbase + CQSPI_REG_INDIRECTRD);
+ return 0;
+
+failrd:
+ /* Cancel the indirect read */
+ writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
+ plat->regbase + CQSPI_REG_INDIRECTRD);
+ return -1;
+}
+
+/* Opcode + Address (3/4 bytes) */
+int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
+ unsigned int cmdlen, const u8 *cmdbuf)
+{
+ unsigned int reg;
+ unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
+
+ if (cmdlen < 4 || cmdbuf == NULL) {
+ printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
+ cmdlen, (unsigned int)cmdbuf);
+ return -EINVAL;
+ }
+ /* Setup the indirect trigger address */
+ writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
+ plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
+
+ writel(CQSPI_REG_SRAM_PARTITION_WR,
+ plat->regbase + CQSPI_REG_SRAMPARTITION);
+
+ /* Configure the opcode */
+ reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
+ writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
+
+ /* Setup write address. */
+ reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
+ writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
+
+ reg = readl(plat->regbase + CQSPI_REG_SIZE);
+ reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
+ reg |= (addr_bytes - 1);
+ writel(reg, plat->regbase + CQSPI_REG_SIZE);
+ return 0;
+}
+
+int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
+ unsigned int txlen, const u8 *txbuf)
+{
+ unsigned int reg = 0;
+ unsigned int retry;
+
+ /* Configure the indirect read transfer bytes */
+ writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
+
+ /* Start the indirect write transfer */
+ writel(CQSPI_REG_INDIRECTWR_START_MASK,
+ plat->regbase + CQSPI_REG_INDIRECTWR);
+
+ if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
+ goto failwr;
+
+ /* Wait until last write is completed (FIFO empty) */
+ retry = CQSPI_REG_RETRY;
+ while (retry--) {
+ reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
+ if (reg == 0)
+ break;
+
+ udelay(1);
+ }
+
+ if (reg != 0) {
+ printf("QSPI: timeout for indirect write\n");
+ goto failwr;
+ }
+
+ /* Check flash indirect controller status */
+ retry = CQSPI_REG_RETRY;
+ while (retry--) {
+ reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
+ if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
+ break;
+ udelay(1);
+ }
+
+ if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
+ printf("QSPI: indirect completion status error with reg 0x%08x\n",
+ reg);
+ goto failwr;
+ }
+
+ /* Clear indirect completion status */
+ writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
+ plat->regbase + CQSPI_REG_INDIRECTWR);
+ return 0;
+
+failwr:
+ /* Cancel the indirect write */
+ writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
+ plat->regbase + CQSPI_REG_INDIRECTWR);
+ return -1;
+}
+
+void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
+{
+ unsigned int reg;
+
+ /* enter XiP mode immediately and enable direct mode */
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
+ reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
+ reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+ /* keep the XiP mode */
+ writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
+
+ /* Enable mode bit at devrd */
+ reg = readl(reg_base + CQSPI_REG_RD_INSTR);
+ reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
+ writel(reg, reg_base + CQSPI_REG_RD_INSTR);
+}
--- /dev/null
+/*
+ * Designware master SPI core controller driver
+ *
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * Very loosely based on the Linux driver:
+ * drivers/spi/spi-dw.c, which is:
+ * Copyright (c) 2009, Intel Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <spi.h>
+#include <fdtdec.h>
+#include <linux/compat.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define DW_SPI_CTRL0 0x00
+#define DW_SPI_CTRL1 0x04
+#define DW_SPI_SSIENR 0x08
+#define DW_SPI_MWCR 0x0c
+#define DW_SPI_SER 0x10
+#define DW_SPI_BAUDR 0x14
+#define DW_SPI_TXFLTR 0x18
+#define DW_SPI_RXFLTR 0x1c
+#define DW_SPI_TXFLR 0x20
+#define DW_SPI_RXFLR 0x24
+#define DW_SPI_SR 0x28
+#define DW_SPI_IMR 0x2c
+#define DW_SPI_ISR 0x30
+#define DW_SPI_RISR 0x34
+#define DW_SPI_TXOICR 0x38
+#define DW_SPI_RXOICR 0x3c
+#define DW_SPI_RXUICR 0x40
+#define DW_SPI_MSTICR 0x44
+#define DW_SPI_ICR 0x48
+#define DW_SPI_DMACR 0x4c
+#define DW_SPI_DMATDLR 0x50
+#define DW_SPI_DMARDLR 0x54
+#define DW_SPI_IDR 0x58
+#define DW_SPI_VERSION 0x5c
+#define DW_SPI_DR 0x60
+
+/* Bit fields in CTRLR0 */
+#define SPI_DFS_OFFSET 0
+
+#define SPI_FRF_OFFSET 4
+#define SPI_FRF_SPI 0x0
+#define SPI_FRF_SSP 0x1
+#define SPI_FRF_MICROWIRE 0x2
+#define SPI_FRF_RESV 0x3
+
+#define SPI_MODE_OFFSET 6
+#define SPI_SCPH_OFFSET 6
+#define SPI_SCOL_OFFSET 7
+
+#define SPI_TMOD_OFFSET 8
+#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
+#define SPI_TMOD_TR 0x0 /* xmit & recv */
+#define SPI_TMOD_TO 0x1 /* xmit only */
+#define SPI_TMOD_RO 0x2 /* recv only */
+#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
+
+#define SPI_SLVOE_OFFSET 10
+#define SPI_SRL_OFFSET 11
+#define SPI_CFS_OFFSET 12
+
+/* Bit fields in SR, 7 bits */
+#define SR_MASK 0x7f /* cover 7 bits */
+#define SR_BUSY (1 << 0)
+#define SR_TF_NOT_FULL (1 << 1)
+#define SR_TF_EMPT (1 << 2)
+#define SR_RF_NOT_EMPT (1 << 3)
+#define SR_RF_FULL (1 << 4)
+#define SR_TX_ERR (1 << 5)
+#define SR_DCOL (1 << 6)
+
+#define RX_TIMEOUT 1000 /* timeout in ms */
+
+struct dw_spi_platdata {
+ s32 frequency; /* Default clock frequency, -1 for none */
+ void __iomem *regs;
+};
+
+struct dw_spi_priv {
+ void __iomem *regs;
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
+
+ int bits_per_word;
+ u8 cs; /* chip select pin */
+ u8 tmode; /* TR/TO/RO/EEPROM */
+ u8 type; /* SPI/SSP/MicroWire */
+ int len;
+
+ u32 fifo_len; /* depth of the FIFO buffer */
+ void *tx;
+ void *tx_end;
+ void *rx;
+ void *rx_end;
+};
+
+static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
+{
+ return __raw_readl(priv->regs + offset);
+}
+
+static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val)
+{
+ __raw_writel(val, priv->regs + offset);
+}
+
+static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset)
+{
+ return __raw_readw(priv->regs + offset);
+}
+
+static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val)
+{
+ __raw_writew(val, priv->regs + offset);
+}
+
+static int dw_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct dw_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
+
+ plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg");
+
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
+ plat->frequency);
+
+ return 0;
+}
+
+static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
+{
+ dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
+}
+
+/* Restart the controller, disable all interrupts, clean rx fifo */
+static void spi_hw_init(struct dw_spi_priv *priv)
+{
+ spi_enable_chip(priv, 0);
+ dw_writel(priv, DW_SPI_IMR, 0xff);
+ spi_enable_chip(priv, 1);
+
+ /*
+ * Try to detect the FIFO depth if not set by interface driver,
+ * the depth could be from 2 to 256 from HW spec
+ */
+ if (!priv->fifo_len) {
+ u32 fifo;
+
+ for (fifo = 2; fifo <= 257; fifo++) {
+ dw_writew(priv, DW_SPI_TXFLTR, fifo);
+ if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
+ break;
+ }
+
+ priv->fifo_len = (fifo == 257) ? 0 : fifo;
+ dw_writew(priv, DW_SPI_TXFLTR, 0);
+ }
+ debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
+}
+
+static int dw_spi_probe(struct udevice *bus)
+{
+ struct dw_spi_platdata *plat = dev_get_platdata(bus);
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+
+ priv->regs = plat->regs;
+ priv->freq = plat->frequency;
+
+ /* Currently only bits_per_word == 8 supported */
+ priv->bits_per_word = 8;
+
+ priv->tmode = 0; /* Tx & Rx */
+
+ /* Basic HW init */
+ spi_hw_init(priv);
+
+ return 0;
+}
+
+/* Return the max entries we can fill into tx fifo */
+static inline u32 tx_max(struct dw_spi_priv *priv)
+{
+ u32 tx_left, tx_room, rxtx_gap;
+
+ tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
+ tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR);
+
+ /*
+ * Another concern is about the tx/rx mismatch, we
+ * thought about using (priv->fifo_len - rxflr - txflr) as
+ * one maximum value for tx, but it doesn't cover the
+ * data which is out of tx/rx fifo and inside the
+ * shift registers. So a control from sw point of
+ * view is taken.
+ */
+ rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
+ (priv->bits_per_word >> 3);
+
+ return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
+}
+
+/* Return the max entries we should read out of rx fifo */
+static inline u32 rx_max(struct dw_spi_priv *priv)
+{
+ u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
+
+ return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR));
+}
+
+static void dw_writer(struct dw_spi_priv *priv)
+{
+ u32 max = tx_max(priv);
+ u16 txw = 0;
+
+ while (max--) {
+ /* Set the tx word if the transfer's original "tx" is not null */
+ if (priv->tx_end - priv->len) {
+ if (priv->bits_per_word == 8)
+ txw = *(u8 *)(priv->tx);
+ else
+ txw = *(u16 *)(priv->tx);
+ }
+ dw_writew(priv, DW_SPI_DR, txw);
+ debug("%s: tx=0x%02x\n", __func__, txw);
+ priv->tx += priv->bits_per_word >> 3;
+ }
+}
+
+static int dw_reader(struct dw_spi_priv *priv)
+{
+ unsigned start = get_timer(0);
+ u32 max;
+ u16 rxw;
+
+ /* Wait for rx data to be ready */
+ while (rx_max(priv) == 0) {
+ if (get_timer(start) > RX_TIMEOUT)
+ return -ETIMEDOUT;
+ }
+
+ max = rx_max(priv);
+
+ while (max--) {
+ rxw = dw_readw(priv, DW_SPI_DR);
+ debug("%s: rx=0x%02x\n", __func__, rxw);
+
+ /*
+ * Care about rx only if the transfer's original "rx" is
+ * not null
+ */
+ if (priv->rx_end - priv->len) {
+ if (priv->bits_per_word == 8)
+ *(u8 *)(priv->rx) = rxw;
+ else
+ *(u16 *)(priv->rx) = rxw;
+ }
+ priv->rx += priv->bits_per_word >> 3;
+ }
+
+ return 0;
+}
+
+static int poll_transfer(struct dw_spi_priv *priv)
+{
+ int ret;
+
+ do {
+ dw_writer(priv);
+ ret = dw_reader(priv);
+ if (ret < 0)
+ return ret;
+ } while (priv->rx_end > priv->rx);
+
+ return 0;
+}
+
+static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ const u8 *tx = dout;
+ u8 *rx = din;
+ int ret = 0;
+ u32 cr0 = 0;
+ u32 cs;
+
+ /* spi core configured to do 8 bit transfers */
+ if (bitlen % 8) {
+ debug("Non byte aligned SPI transfer.\n");
+ return -1;
+ }
+
+ cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
+ (priv->mode << SPI_MODE_OFFSET) |
+ (priv->tmode << SPI_TMOD_OFFSET);
+
+ if (rx && tx)
+ priv->tmode = SPI_TMOD_TR;
+ else if (rx)
+ priv->tmode = SPI_TMOD_RO;
+ else
+ priv->tmode = SPI_TMOD_TO;
+
+ cr0 &= ~SPI_TMOD_MASK;
+ cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
+
+ priv->len = bitlen >> 3;
+ debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
+
+ priv->tx = (void *)tx;
+ priv->tx_end = priv->tx + priv->len;
+ priv->rx = rx;
+ priv->rx_end = priv->rx + priv->len;
+
+ /* Disable controller before writing control registers */
+ spi_enable_chip(priv, 0);
+
+ debug("%s: cr0=%08x\n", __func__, cr0);
+ /* Reprogram cr0 only if changed */
+ if (dw_readw(priv, DW_SPI_CTRL0) != cr0)
+ dw_writew(priv, DW_SPI_CTRL0, cr0);
+
+ /*
+ * Configure the desired SS (slave select 0...3) in the controller
+ * The DW SPI controller will activate and deactivate this CS
+ * automatically. So no cs_activate() etc is needed in this driver.
+ */
+ cs = spi_chip_select(dev);
+ dw_writel(priv, DW_SPI_SER, 1 << cs);
+
+ /* Enable controller after writing control registers */
+ spi_enable_chip(priv, 1);
+
+ /* Start transfer in a polling loop */
+ ret = poll_transfer(priv);
+
+ return ret;
+}
+
+static int dw_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct dw_spi_platdata *plat = bus->platdata;
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ u16 clk_div;
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+
+ /* Disable controller before writing control registers */
+ spi_enable_chip(priv, 0);
+
+ /* clk_div doesn't support odd number */
+ clk_div = cm_get_spi_controller_clk_hz() / speed;
+ clk_div = (clk_div + 1) & 0xfffe;
+ dw_writel(priv, DW_SPI_BAUDR, clk_div);
+
+ /* Enable controller after writing control registers */
+ spi_enable_chip(priv, 1);
+
+ priv->freq = speed;
+ debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
+ priv->freq, clk_div);
+
+ return 0;
+}
+
+static int dw_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+
+ /*
+ * Can't set mode yet. Since this depends on if rx, tx, or
+ * rx & tx is requested. So we have to defer this to the
+ * real transfer function.
+ */
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops dw_spi_ops = {
+ .xfer = dw_spi_xfer,
+ .set_speed = dw_spi_set_speed,
+ .set_mode = dw_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id dw_spi_ids[] = {
+ { .compatible = "snps,dw-spi-mmio" },
+ { }
+};
+
+U_BOOT_DRIVER(dw_spi) = {
+ .name = "dw_spi",
+ .id = UCLASS_SPI,
+ .of_match = dw_spi_ids,
+ .ops = &dw_spi_ops,
+ .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = dw_spi_probe,
+};
ich->slave.max_write_size = ctlr.databytes;
ich->speed = max_hz;
+ /*
+ * ICH 7 SPI controller only supports array read command
+ * and byte program command for SST flash
+ */
+ if (ctlr.ich_version == 7) {
+ ich->slave.op_mode_rx = SPI_OPM_RX_AS;
+ ich->slave.op_mode_tx = SPI_OPM_TX_BP;
+ }
+
return &ich->slave;
}
*/
static int get_ich_version(uint16_t device_id)
{
- if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
+ if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
+ device_id == PCI_DEVICE_ID_INTEL_ITC_LPC)
return 7;
if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
struct spi_trans *trans = &ich->trans;
unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
int using_cmd = 0;
- /* Align read transactions to 64-byte boundaries */
- char buff[ctlr.databytes];
/* Ee don't support writing partial bytes. */
if (bitlen % 8) {
*/
while (trans->bytesout || trans->bytesin) {
uint32_t data_length;
- uint32_t aligned_offset;
- uint32_t diff;
-
- aligned_offset = trans->offset & ~(ctlr.databytes - 1);
- diff = trans->offset - aligned_offset;
/* SPI addresses are 24 bit only */
- ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr);
+ ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr);
if (trans->bytesout)
data_length = min(trans->bytesout, ctlr.databytes);
}
if (trans->bytesin) {
- if (diff) {
- data_length -= diff;
- read_reg(ctlr.data, buff, ctlr.databytes);
- memcpy(trans->in, buff + diff, data_length);
- } else {
- read_reg(ctlr.data, trans->in, data_length);
- }
+ read_reg(ctlr.data, trans->in, data_length);
spi_use_in(trans, data_length);
if (with_address)
trans->offset += data_length;
DEFINE_CACHE_ALIGN_BUFFER(u8, status_req, STATUS_BYTECOUNT);
#endif
-
-/**
- * strlcpy - Copy a %NUL terminated string into a sized buffer
- * @dest: Where to copy the string to
- * @src: Where to copy the string from
- * @size: size of destination buffer
- *
- * Compatible with *BSD: the result is always a valid
- * NUL-terminated string that fits in the buffer (unless,
- * of course, the buffer size is zero). It does not pad
- * out the result like strncpy() does.
- */
-size_t strlcpy(char *dest, const char *src, size_t size)
-{
- size_t ret = strlen(src);
-
- if (size) {
- size_t len = (ret >= size) ? size - 1 : ret;
- memcpy(dest, src, len);
- dest[len] = '\0';
- }
- return ret;
-}
-
/*============================================================================*/
/*
#ifdef CONFIG_4xx
#include <asm/ppc4xx.h>
#endif
-#ifdef CONFIG_ARM
-#define asmlinkage /* nothing */
-#endif
-#ifdef CONFIG_X86
-#define asmlinkage __attribute__((regparm(0)))
-#endif
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
#undef CONFIG_IMAGE_FORMAT_LEGACY
#endif
+#ifdef CONFIG_DM_I2C
+# ifdef CONFIG_SYS_I2C
+# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
+# endif
+#endif
+
#endif /* __CONFIG_FALLBACKS_H */
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra124 (Nyan-big) # "
+#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_CMD_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS 6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
#define CONFIG_DM
#define CONFIG_CMD_DM
#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
/* Memory layout */
#define CONFIG_NR_DRAM_BANKS 1
CONFIG_SYS_SDRAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END 0x00200000
#define CONFIG_LOADADDR 0x00200000
#endif
/* Console UART */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 3000000
-#define CONFIG_PL01x_PORTS { (void *)0x20201000 }
+#define CONFIG_PL01X_SERIAL
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DM_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SANDBOX
+#define CONFIG_I2C_EDID
+#define CONFIG_I2C_EEPROM
+
/* Memory things - we don't really want a memory test */
#define CONFIG_SYS_LOAD_ADDR 0x00000000
#define CONFIG_SYS_MEMTEST_START 0x00100000
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
#endif
- /*
+/*
* I2C support
*/
#define CONFIG_SYS_I2C
#endif
#define CONFIG_CMD_I2C
+/*
+ * QSPI support
+ */
+#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_CADENCE_QSPI
+/* Enable multiple SPI NOR flash manufacturers */
+#define CONFIG_SPI_FLASH /* SPI flash subsystem */
+#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
+#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
+#define CONFIG_SPI_FLASH_MTD
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
+#endif
+#define CONFIG_CQSPI_DECODER 0
+#define CONFIG_CMD_SF
+#endif
+
+#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#define CONFIG_CMD_SPI
+#endif
+
/*
* Serial Driver
*/
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
#endif
#define CONFIG_DM_SPI
#define CONFIG_DM_SPI_FLASH
+#define CONFIG_DM_I2C
#define CONFIG_SYS_TIMER_RATE 1000000
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
#define CONFIG_SPL_STACK 0x800ffffc
-/* Total I2C ports on Tegra114 */
-#define TEGRA_I2C_NUM_CONTROLLERS 5
-
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
#define CONFIG_SPL_STACK 0x800ffffc
-/* Total I2C ports on Tegra124 */
-#define TEGRA_I2C_NUM_CONTROLLERS 5
-
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
-/* Total I2C ports on Tegra20 */
-#define TEGRA_I2C_NUM_CONTROLLERS 4
-
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
#define CONFIG_SPL_STACK 0x800ffffc
-/* Total I2C ports on Tegra30 */
-#define TEGRA_I2C_NUM_CONTROLLERS 5
-
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
UCLASS_TEST_FDT,
UCLASS_TEST_BUS,
UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
+ UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
UCLASS_SIMPLE_BUS,
/* U-Boot uclasses start here */
UCLASS_SPI_FLASH, /* SPI flash */
UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_THERMAL, /* Thermal sensor */
+ UCLASS_I2C, /* I2C bus */
+ UCLASS_I2C_GENERIC, /* Generic I2C device */
+ UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_COUNT,
UCLASS_INVALID = -1,
} \
}
+/* Assert that a pointer is not NULL */
+#define ut_assertnonnull(expr) { \
+ const void *val = (expr); \
+ \
+ if (val == NULL) { \
+ ut_failf(dms, __FILE__, __LINE__, __func__, \
+ #expr " = NULL", \
+ "Expected non-null, got NULL"); \
+ return -1; \
+ } \
+}
+
/* Assert that an operation succeeds (returns 0) */
#define ut_assertok(cond) ut_asserteq(0, cond)
--- /dev/null
+/*
+ * This header provides constants for Tegra pinctrl bindings.
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_H
+
+/*
+ * Enable/disable for diffeent dt properties. This is applicable for
+ * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
+ * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
+ */
+#define TEGRA_PIN_DISABLE 0
+#define TEGRA_PIN_ENABLE 1
+
+#define TEGRA_PIN_PULL_NONE 0
+#define TEGRA_PIN_PULL_DOWN 1
+#define TEGRA_PIN_PULL_UP 2
+
+/* Low power mode driver */
+#define TEGRA_PIN_LP_DRIVE_DIV_8 0
+#define TEGRA_PIN_LP_DRIVE_DIV_4 1
+#define TEGRA_PIN_LP_DRIVE_DIV_2 2
+#define TEGRA_PIN_LP_DRIVE_DIV_1 3
+
+/* Rising/Falling slew rate */
+#define TEGRA_PIN_SLEW_RATE_FASTEST 0
+#define TEGRA_PIN_SLEW_RATE_FAST 1
+#define TEGRA_PIN_SLEW_RATE_SLOW 2
+#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
+
+#endif
/*
* Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
#define __set_errno(val) do { errno = val; } while (0)
+#ifdef CONFIG_ERRNO_STR
+const char *errno_str(int errno);
+#endif
#endif /* _ERRNO_H */
#ifndef _I2C_H_
#define _I2C_H_
+/*
+ * For now there are essentially two parts to this file - driver model
+ * here at the top, and the older code below (with CONFIG_SYS_I2C being
+ * most recent). The plan is to migrate everything to driver model.
+ * The driver model structures and API are separate as they are different
+ * enough as to be incompatible for compilation purposes.
+ */
+
+#ifdef CONFIG_DM_I2C
+
+enum dm_i2c_chip_flags {
+ DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */
+ DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */
+ DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */
+};
+
+/**
+ * struct dm_i2c_chip - information about an i2c chip
+ *
+ * An I2C chip is a device on the I2C bus. It sits at a particular address
+ * and normally supports 7-bit or 10-bit addressing.
+ *
+ * To obtain this structure, use dev_get_parentdata(dev) where dev is the
+ * chip to examine.
+ *
+ * @chip_addr: Chip address on bus
+ * @offset_len: Length of offset in bytes. A single byte offset can
+ * represent up to 256 bytes. A value larger than 1 may be
+ * needed for larger devices.
+ * @flags: Flags for this chip (dm_i2c_chip_flags)
+ * @emul: Emulator for this chip address (only used for emulation)
+ */
+struct dm_i2c_chip {
+ uint chip_addr;
+ uint offset_len;
+ uint flags;
+#ifdef CONFIG_SANDBOX
+ struct udevice *emul;
+#endif
+};
+
+/**
+ * struct dm_i2c_bus- information about an i2c bus
+ *
+ * An I2C bus contains 0 or more chips on it, each at its own address. The
+ * bus can operate at different speeds (measured in Hz, typically 100KHz
+ * or 400KHz).
+ *
+ * To obtain this structure, use bus->uclass_priv where bus is the I2C
+ * bus udevice.
+ *
+ * @speed_hz: Bus speed in hertz (typically 100000)
+ */
+struct dm_i2c_bus {
+ int speed_hz;
+};
+
+/**
+ * i2c_read() - read bytes from an I2C chip
+ *
+ * To obtain an I2C device (called a 'chip') given the I2C bus address you
+ * can use i2c_get_chip(). To obtain a bus by bus number use
+ * uclass_get_device_by_seq(UCLASS_I2C, <bus number>).
+ *
+ * To set the address length of a devce use i2c_set_addr_len(). It
+ * defaults to 1.
+ *
+ * @dev: Chip to read from
+ * @offset: Offset within chip to start reading
+ * @buffer: Place to put data
+ * @len: Number of bytes to read
+ *
+ * @return 0 on success, -ve on failure
+ */
+int i2c_read(struct udevice *dev, uint offset, uint8_t *buffer,
+ int len);
+
+/**
+ * i2c_write() - write bytes to an I2C chip
+ *
+ * See notes for i2c_read() above.
+ *
+ * @dev: Chip to write to
+ * @offset: Offset within chip to start writing
+ * @buffer: Buffer containing data to write
+ * @len: Number of bytes to write
+ *
+ * @return 0 on success, -ve on failure
+ */
+int i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
+ int len);
+
+/**
+ * i2c_probe() - probe a particular chip address
+ *
+ * This can be useful to check for the existence of a chip on the bus.
+ * It is typically implemented by writing the chip address to the bus
+ * and checking that the chip replies with an ACK.
+ *
+ * @bus: Bus to probe
+ * @chip_addr: 7-bit address to probe (10-bit and others are not supported)
+ * @chip_flags: Flags for the probe (see enum dm_i2c_chip_flags)
+ * @devp: Returns the device found, or NULL if none
+ * @return 0 if a chip was found at that address, -ve if not
+ */
+int i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
+ struct udevice **devp);
+
+/**
+ * i2c_set_bus_speed() - set the speed of a bus
+ *
+ * @bus: Bus to adjust
+ * @speed: Requested speed in Hz
+ * @return 0 if OK, -EINVAL for invalid values
+ */
+int i2c_set_bus_speed(struct udevice *bus, unsigned int speed);
+
+/**
+ * i2c_get_bus_speed() - get the speed of a bus
+ *
+ * @bus: Bus to check
+ * @return speed of selected I2C bus in Hz, -ve on error
+ */
+int i2c_get_bus_speed(struct udevice *bus);
+
+/**
+ * i2c_set_chip_flags() - set flags for a chip
+ *
+ * Typically addresses are 7 bits, but for 10-bit addresses you should set
+ * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing.
+ *
+ * @dev: Chip to adjust
+ * @flags: New flags
+ * @return 0 if OK, -EINVAL if value is unsupported, other -ve value on error
+ */
+int i2c_set_chip_flags(struct udevice *dev, uint flags);
+
+/**
+ * i2c_get_chip_flags() - get flags for a chip
+ *
+ * @dev: Chip to check
+ * @flagsp: Place to put flags
+ * @return 0 if OK, other -ve value on error
+ */
+int i2c_get_chip_flags(struct udevice *dev, uint *flagsp);
+
+/**
+ * i2c_set_offset_len() - set the offset length for a chip
+ *
+ * The offset used to access a chip may be up to 4 bytes long. Typically it
+ * is only 1 byte, which is enough for chips with 256 bytes of memory or
+ * registers. The default value is 1, but you can call this function to
+ * change it.
+ *
+ * @offset_len: New offset length value (typically 1 or 2)
+ */
+
+int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len);
+/**
+ * i2c_deblock() - recover a bus that is in an unknown state
+ *
+ * See the deblock() method in 'struct dm_i2c_ops' for full information
+ *
+ * @bus: Bus to recover
+ * @return 0 if OK, -ve on error
+ */
+int i2c_deblock(struct udevice *bus);
+
+/*
+ * Not all of these flags are implemented in the U-Boot API
+ */
+enum dm_i2c_msg_flags {
+ I2C_M_TEN = 0x0010, /* ten-bit chip address */
+ I2C_M_RD = 0x0001, /* read data, from slave to master */
+ I2C_M_STOP = 0x8000, /* send stop after this message */
+ I2C_M_NOSTART = 0x4000, /* no start before this message */
+ I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */
+ I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */
+ I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */
+ I2C_M_RECV_LEN = 0x0400, /* length is first received byte */
+};
+
+/**
+ * struct i2c_msg - an I2C message
+ *
+ * @addr: Slave address
+ * @flags: Flags (see enum dm_i2c_msg_flags)
+ * @len: Length of buffer in bytes, may be 0 for a probe
+ * @buf: Buffer to send/receive, or NULL if no data
+ */
+struct i2c_msg {
+ uint addr;
+ uint flags;
+ uint len;
+ u8 *buf;
+};
+
+/**
+ * struct i2c_msg_list - a list of I2C messages
+ *
+ * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem
+ * appropriate in U-Boot.
+ *
+ * @msg: Pointer to i2c_msg array
+ * @nmsgs: Number of elements in the array
+ */
+struct i2c_msg_list {
+ struct i2c_msg *msgs;
+ uint nmsgs;
+};
+
+/**
+ * struct dm_i2c_ops - driver operations for I2C uclass
+ *
+ * Drivers should support these operations unless otherwise noted. These
+ * operations are intended to be used by uclass code, not directly from
+ * other code.
+ */
+struct dm_i2c_ops {
+ /**
+ * xfer() - transfer a list of I2C messages
+ *
+ * @bus: Bus to read from
+ * @msg: List of messages to transfer
+ * @nmsgs: Number of messages in the list
+ * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte,
+ * -ECOMM if the speed cannot be supported, -EPROTO if the chip
+ * flags cannot be supported, other -ve value on some other error
+ */
+ int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs);
+
+ /**
+ * probe_chip() - probe for the presense of a chip address
+ *
+ * This function is optional. If omitted, the uclass will send a zero
+ * length message instead.
+ *
+ * @bus: Bus to probe
+ * @chip_addr: Chip address to probe
+ * @chip_flags: Probe flags (enum dm_i2c_chip_flags)
+ * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back
+ * to default probem other -ve value on error
+ */
+ int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags);
+
+ /**
+ * set_bus_speed() - set the speed of a bus (optional)
+ *
+ * The bus speed value will be updated by the uclass if this function
+ * does not return an error. This method is optional - if it is not
+ * provided then the driver can read the speed from
+ * bus->uclass_priv->speed_hz
+ *
+ * @bus: Bus to adjust
+ * @speed: Requested speed in Hz
+ * @return 0 if OK, -EINVAL for invalid values
+ */
+ int (*set_bus_speed)(struct udevice *bus, unsigned int speed);
+
+ /**
+ * get_bus_speed() - get the speed of a bus (optional)
+ *
+ * Normally this can be provided by the uclass, but if you want your
+ * driver to check the bus speed by looking at the hardware, you can
+ * implement that here. This method is optional. This method would
+ * normally be expected to return bus->uclass_priv->speed_hz.
+ *
+ * @bus: Bus to check
+ * @return speed of selected I2C bus in Hz, -ve on error
+ */
+ int (*get_bus_speed)(struct udevice *bus);
+
+ /**
+ * set_flags() - set the flags for a chip (optional)
+ *
+ * This is generally implemented by the uclass, but drivers can
+ * check the value to ensure that unsupported options are not used.
+ * This method is optional. If provided, this method will always be
+ * called when the flags change.
+ *
+ * @dev: Chip to adjust
+ * @flags: New flags value
+ * @return 0 if OK, -EINVAL if value is unsupported
+ */
+ int (*set_flags)(struct udevice *dev, uint flags);
+
+ /**
+ * deblock() - recover a bus that is in an unknown state
+ *
+ * I2C is a synchronous protocol and resets of the processor in the
+ * middle of an access can block the I2C Bus until a powerdown of
+ * the full unit is done. This is because slaves can be stuck
+ * waiting for addition bus transitions for a transaction that will
+ * never complete. Resetting the I2C master does not help. The only
+ * way is to force the bus through a series of transitions to make
+ * sure that all slaves are done with the transaction. This method
+ * performs this 'deblocking' if support by the driver.
+ *
+ * This method is optional.
+ */
+ int (*deblock)(struct udevice *bus);
+};
+
+#define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops)
+
+/**
+ * i2c_get_chip() - get a device to use to access a chip on a bus
+ *
+ * This returns the device for the given chip address. The device can then
+ * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc.
+ *
+ * @bus: Bus to examine
+ * @chip_addr: Chip address for the new device
+ * @devp: Returns pointer to new device if found or -ENODEV if not
+ * found
+ */
+int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp);
+
+/**
+ * i2c_get_chip() - get a device to use to access a chip on a bus number
+ *
+ * This returns the device for the given chip address on a particular bus
+ * number.
+ *
+ * @busnum: Bus number to examine
+ * @chip_addr: Chip address for the new device
+ * @devp: Returns pointer to new device if found or -ENODEV if not
+ * found
+ */
+int i2c_get_chip_for_busnum(int busnum, int chip_addr, struct udevice **devp);
+
+/**
+ * i2c_chip_ofdata_to_platdata() - Decode standard I2C platform data
+ *
+ * This decodes the chip address from a device tree node and puts it into
+ * its dm_i2c_chip structure. This should be called in your driver's
+ * ofdata_to_platdata() method.
+ *
+ * @blob: Device tree blob
+ * @node: Node offset to read from
+ * @spi: Place to put the decoded information
+ */
+int i2c_chip_ofdata_to_platdata(const void *blob, int node,
+ struct dm_i2c_chip *chip);
+
+#endif
+
+#ifndef CONFIG_DM_I2C
+
/*
* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
*
* @return 0 if port was reset, -1 if not found
*/
int i2c_reset_port_fdt(const void *blob, int node);
+
+#endif /* !CONFIG_DM_I2C */
+
#endif /* _I2C_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __I2C_EEPROM
+#define __I2C_EEPROM
+
+struct i2c_eeprom_ops {
+ int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size);
+ int (*write)(struct udevice *dev, int offset, const uint8_t *buf,
+ int size);
+};
+
+struct i2c_eeprom {
+};
+
+#endif
#define CPP_ASMLINKAGE
#endif
+#ifndef asmlinkage
#define asmlinkage CPP_ASMLINKAGE
+#endif
#define SYMBOL_NAME_STR(X) #X
#define SYMBOL_NAME(X) X
#ifndef __HAVE_ARCH_STRNCPY
extern char * strncpy(char *,const char *, __kernel_size_t);
#endif
+#ifndef __HAVE_ARCH_STRLCPY
+size_t strlcpy(char *, const char *, size_t);
+#endif
#ifndef __HAVE_ARCH_STRCAT
extern char * strcat(char *, const char *);
#endif
#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
+#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500)
#define MMC_MODE_HS (1 << 0)
#define MMC_MODE_HS_52MHz (1 << 1)
* EXT_CSD fields
*/
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
+#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
+#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
+
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
char init_in_progress; /* 1 if we have done mmc_start_init() */
char preinit; /* start init as early as possible */
uint op_cond_response; /* the response byte from the last op_cond */
+ int ddr_mode;
};
int mmc_register(struct mmc *mmc);
#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb
#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea
#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500
+#define PCI_DEVICE_ID_INTEL_TCF_GBE 0x8802
+#define PCI_DEVICE_ID_INTEL_TCF_SDIO_0 0x8809
+#define PCI_DEVICE_ID_INTEL_TCF_SDIO_1 0x880a
+#define PCI_DEVICE_ID_INTEL_TCF_SATA 0x880b
+#define PCI_DEVICE_ID_INTEL_TCF_UART_0 0x8811
+#define PCI_DEVICE_ID_INTEL_TCF_UART_1 0x8812
+#define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813
+#define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814
#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004
#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
--- /dev/null
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SMSC_LPC47M_H_
+#define _SMSC_LPC47M_H_
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @dev: High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @iobase: Processor I/O port address to assign to this serial device.
+ */
+void lpc47m_enable_serial(u16 dev, u16 iobase);
+
+#endif /* _SMSC_LPC47M_H_ */
/* SPI TX operation modes */
#define SPI_OPM_TX_QPP (1 << 0)
+#define SPI_OPM_TX_BP (1 << 1)
/* SPI RX operation modes */
#define SPI_OPM_RX_AS (1 << 0)
* Set up the TPS6586X I2C bus number. This will be used for all operations
* on the device. This function must be called before using other functions.
*
- * @param bus I2C bus number containing the TPS6586X chip
+ * @param bus I2C bus containing the TPS6586X chip
* @return 0 (always succeeds)
*/
-int tps6586x_init(int bus);
+int tps6586x_init(struct udevice *bus);
#endif /* _TPS6586X_H_ */
obj-$(CONFIG_ADDR_MAP) += addr_map.o
obj-y += hashtable.o
obj-y += errno.o
+obj-$(CONFIG_ERRNO_STR) += errno_str.o
obj-y += display_options.o
obj-$(CONFIG_BCH) += bch.o
obj-y += crc32.o
#ifdef CONFIG_SYS_MALLOC_F_LEN
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
-#ifdef CONFIG_X86
- DEFINE(GD_BIST, offsetof(struct global_data, arch.bist));
-#endif
#if defined(CONFIG_ARM)
--- /dev/null
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SDPX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+
+#define ERRNO_MSG(errno, msg) msg
+#define SAME_AS(x) (const char *)&errno_message[x]
+
+static const char * const errno_message[] = {
+ ERRNO_MSG(0, "Success"),
+ ERRNO_MSG(EPERM, "Operation not permitted"),
+ ERRNO_MSG(ENOEN, "No such file or directory"),
+ ERRNO_MSG(ESRCH, "No such process"),
+ ERRNO_MSG(EINTR, "Interrupted system call"),
+ ERRNO_MSG(EIO, "I/O error"),
+ ERRNO_MSG(ENXIO, "No such device or address"),
+ ERRNO_MSG(E2BIG, "Argument list too long"),
+ ERRNO_MSG(ENOEXEC, "Exec format error"),
+ ERRNO_MSG(EBADF, "Bad file number"),
+ ERRNO_MSG(ECHILD, "No child processes"),
+ ERRNO_MSG(EAGAIN, "Try again"),
+ ERRNO_MSG(ENOMEM, "Out of memory"),
+ ERRNO_MSG(EACCES, "Permission denied"),
+ ERRNO_MSG(EFAULT, "Bad address"),
+ ERRNO_MSG(ENOTBL, "Block device required"),
+ ERRNO_MSG(EBUSY, "Device or resource busy"),
+ ERRNO_MSG(EEXIST, "File exists"),
+ ERRNO_MSG(EXDEV, "Cross-device link"),
+ ERRNO_MSG(ENODEV, "No such device"),
+ ERRNO_MSG(ENOTDIR, "Not a directory"),
+ ERRNO_MSG(EISDIR, "Is a directory"),
+ ERRNO_MSG(EINVAL, "Invalid argument"),
+ ERRNO_MSG(ENFILE, "File table overflow"),
+ ERRNO_MSG(EMFILE, "Too many open files"),
+ ERRNO_MSG(ENOTTY, "Not a typewriter"),
+ ERRNO_MSG(ETXTBSY, "Text file busy"),
+ ERRNO_MSG(EFBIG, "File too large"),
+ ERRNO_MSG(ENOSPC, "No space left on device"),
+ ERRNO_MSG(ESPIPE, "Illegal seek"),
+ ERRNO_MSG(EROFS, "Read-only file system"),
+ ERRNO_MSG(EMLINK, "Too many links"),
+ ERRNO_MSG(EPIPE, "Broken pipe"),
+ ERRNO_MSG(EDOM, "Math argument out of domain of func"),
+ ERRNO_MSG(ERANGE, "Math result not representable"),
+ ERRNO_MSG(EDEADLK, "Resource deadlock would occur"),
+ ERRNO_MSG(ENAMETOOLONG, "File name too long"),
+ ERRNO_MSG(ENOLCK, "No record locks available"),
+ ERRNO_MSG(ENOSYS, "Function not implemented"),
+ ERRNO_MSG(ENOTEMPTY, "Directory not empty"),
+ ERRNO_MSG(ELOOP, "Too many symbolic links encountered"),
+ ERRNO_MSG(EWOULDBLOCK, SAME_AS(EAGAIN)),
+ ERRNO_MSG(ENOMSG, "No message of desired type"),
+ ERRNO_MSG(EIDRM, "Identifier removed"),
+ ERRNO_MSG(ECHRNG, "Channel number out of range"),
+ ERRNO_MSG(EL2NSYNC, "Level 2 not synchronized"),
+ ERRNO_MSG(EL3HLT, "Level 3 halted"),
+ ERRNO_MSG(EL3RST, "Level 3 reset"),
+ ERRNO_MSG(ELNRNG, "Link number out of range"),
+ ERRNO_MSG(EUNATCH, "Protocol driver not attached"),
+ ERRNO_MSG(ENOCSI, "No CSI structure available"),
+ ERRNO_MSG(EL2HLT, "Level 2 halted"),
+ ERRNO_MSG(EBADE, "Invalid exchange"),
+ ERRNO_MSG(EBADR, "Invalid request descriptor"),
+ ERRNO_MSG(EXFULL, "Exchange full"),
+ ERRNO_MSG(ENOANO, "No anode"),
+ ERRNO_MSG(EBADRQC, "Invalid request code"),
+ ERRNO_MSG(EBADSLT, "Invalid slot"),
+ ERRNO_MSG(EDEADLOCK, SAME_AS(EDEADLK)),
+ ERRNO_MSG(EBFONT, "Bad font file format"),
+ ERRNO_MSG(ENOSTR, "Device not a stream"),
+ ERRNO_MSG(ENODATA, "No data available"),
+ ERRNO_MSG(ETIME, "Timer expired"),
+ ERRNO_MSG(ENOSR, "Out of streams resources"),
+ ERRNO_MSG(ENONET, "Machine is not on the network"),
+ ERRNO_MSG(ENOPKG, "Package not installed"),
+ ERRNO_MSG(EREMOTE, "Object is remote"),
+ ERRNO_MSG(ENOLINK, "Link has been severed"),
+ ERRNO_MSG(EADV, "Advertise error"),
+ ERRNO_MSG(ESRMNT, "Srmount error"),
+ ERRNO_MSG(ECOMM, "Communication error on send"),
+ ERRNO_MSG(EPROTO, "Protocol error"),
+ ERRNO_MSG(EMULTIHOP, "Multihop attempted"),
+ ERRNO_MSG(EDOTDOT, "RFS specific error"),
+ ERRNO_MSG(EBADMSG, "Not a data message"),
+ ERRNO_MSG(EOVERFLOW, "Value too large for defined data type"),
+ ERRNO_MSG(ENOTUNIQ, "Name not unique on network"),
+ ERRNO_MSG(EBADFD, "File descriptor in bad state"),
+ ERRNO_MSG(EREMCHG, "Remote address changed"),
+ ERRNO_MSG(ELIBACC, "Can not access a needed shared library"),
+ ERRNO_MSG(ELIBBAD, "Accessing a corrupted shared library"),
+ ERRNO_MSG(ELIBSCN, ".lib section in a.out corrupted"),
+ ERRNO_MSG(ELIBMAX, "Attempting to link in too many shared libraries"),
+ ERRNO_MSG(ELIBEXEC, "Cannot exec a shared library directly"),
+ ERRNO_MSG(EILSEQ, "Illegal byte sequence"),
+ ERRNO_MSG(ERESTART, "Interrupted system call should be restarted"),
+ ERRNO_MSG(ESTRPIPE, "Streams pipe error"),
+ ERRNO_MSG(EUSERS, "Too many users"),
+ ERRNO_MSG(ENOTSOCK, "Socket operation on non-socket"),
+ ERRNO_MSG(EDESTADDRREQ, "Destination address required"),
+ ERRNO_MSG(EMSGSIZE, "Message too long"),
+ ERRNO_MSG(EPROTOTYPE, "Protocol wrong type for socket"),
+ ERRNO_MSG(ENOPROTOOPT, "Protocol not available"),
+ ERRNO_MSG(EPROTONOSUPPORT, "Protocol not supported"),
+ ERRNO_MSG(ESOCKTNOSUPPORT, "Socket type not supported"),
+ ERRNO_MSG(EOPNOTSUPP, "Operation not supported on transport endpoint"),
+ ERRNO_MSG(EPFNOSUPPORT, "Protocol family not supported"),
+ ERRNO_MSG(AFNOSUPPORT, "Address family not supported by protocol"),
+ ERRNO_MSG(EADDRINUSE, "Address already in use"),
+ ERRNO_MSG(EADDRNOTAVAIL, "Cannot assign requested address"),
+ ERRNO_MSG(ENETDOWN, "Network is down"),
+ ERRNO_MSG(ENETUNREACH, "Network is unreachable"),
+ ERRNO_MSG(ENETRESET, "Network dropped connection because of reset"),
+ ERRNO_MSG(ECONNABORTED, "Software caused connection abort"),
+ ERRNO_MSG(ECONNRESET, "Connection reset by peer"),
+ ERRNO_MSG(ENOBUFS, "No buffer space available"),
+ ERRNO_MSG(EISCONN, "Transport endpoint is already connected"),
+ ERRNO_MSG(ENOTCONN, "Transport endpoint is not connected"),
+ ERRNO_MSG(ESHUTDOWN, "Cannot send after transport endpoint shutdown"),
+ ERRNO_MSG(ETOOMANYREFS, "Too many references: cannot splice"),
+ ERRNO_MSG(ETIMEDOUT, "Connection timed out"),
+ ERRNO_MSG(ECONNREFUSED, "Connection refused"),
+ ERRNO_MSG(EHOSTDOWN, "Host is down"),
+ ERRNO_MSG(EHOSTUNREACH, "No route to host"),
+ ERRNO_MSG(EALREADY, "Operation already in progress"),
+ ERRNO_MSG(EINPROGRESS, "Operation now in progress"),
+ ERRNO_MSG(ESTALE, "Stale NFS file handle"),
+ ERRNO_MSG(EUCLEAN, "Structure needs cleaning"),
+ ERRNO_MSG(ENOTNAM, "Not a XENIX named type file"),
+ ERRNO_MSG(ENAVAIL, "No XENIX semaphores available"),
+ ERRNO_MSG(EISNAM, "Is a named type file"),
+ ERRNO_MSG(EREMOTEIO, "Remote I/O error"),
+ ERRNO_MSG(EDQUOT, "Quota exceeded"),
+ ERRNO_MSG(ENOMEDIUM, "No medium found"),
+ ERRNO_MSG(EMEDIUMTYPE, "Wrong medium type"),
+};
+
+const char *errno_str(int errno)
+{
+ if (errno >= 0)
+ return errno_message[0];
+
+ return errno_message[abs(errno)];
+}
}
#endif
+#ifndef __HAVE_ARCH_STRLCPY
+/**
+ * strlcpy - Copy a C-string into a sized buffer
+ * @dest: Where to copy the string to
+ * @src: Where to copy the string from
+ * @size: size of destination buffer
+ *
+ * Compatible with *BSD: the result is always a valid
+ * NUL-terminated string that fits in the buffer (unless,
+ * of course, the buffer size is zero). It does not pad
+ * out the result like strncpy() does.
+ */
+size_t strlcpy(char *dest, const char *src, size_t size)
+{
+ size_t ret = strlen(src);
+
+ if (size) {
+ size_t len = (ret >= size) ? size - 1 : ret;
+ memcpy(dest, src, len);
+ dest[len] = '\0';
+ }
+ return ret;
+}
+#endif
+
#ifndef __HAVE_ARCH_STRCAT
/**
* strcat - Append one %NUL-terminated string to another
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_SPI) += spi.o
obj-$(CONFIG_DM_SPI_FLASH) += sf.o
+obj-$(CONFIG_DM_I2C) += i2c.o
endif
#include <dm/test.h>
#include <dm/uclass-internal.h>
+static void show_devices(struct udevice *dev, int depth, int last_flag)
+{
+ int i, is_last;
+ struct udevice *child;
+ char class_name[12];
+
+ /* print the first 11 characters to not break the tree-format. */
+ strlcpy(class_name, dev->uclass->uc_drv->name, sizeof(class_name));
+ printf(" %-11s [ %c ] ", class_name,
+ dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ');
+
+ for (i = depth; i >= 0; i--) {
+ is_last = (last_flag >> i) & 1;
+ if (i) {
+ if (is_last)
+ printf(" ");
+ else
+ printf("| ");
+ } else {
+ if (is_last)
+ printf("`-- ");
+ else
+ printf("|-- ");
+ }
+ }
+
+ printf("%s\n", dev->name);
+
+ list_for_each_entry(child, &dev->child_head, sibling_node) {
+ is_last = list_is_last(&child->sibling_node, &dev->child_head);
+ show_devices(child, depth + 1, (last_flag << 1) | is_last);
+ }
+}
+
+static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *root;
+
+ root = dm_root();
+ if (root) {
+ printf(" Class Probed Name\n");
+ printf("----------------------------------------\n");
+ show_devices(root, -1, 0);
+ }
+
+ return 0;
+}
+
/**
* dm_display_line() - Display information about a single device
*
* Displays a single line of information with an option prefix
*
* @dev: Device to display
- * @buf: Prefix to display at the start of the line
*/
-static void dm_display_line(struct udevice *dev, char *buf)
+static void dm_display_line(struct udevice *dev)
{
- printf("%s- %c %s @ %08lx", buf,
+ printf("- %c %s @ %08lx",
dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
dev->name, (ulong)map_to_sysmem(dev));
if (dev->req_seq != -1)
puts("\n");
}
-static int display_succ(struct udevice *in, char *buf)
-{
- int len;
- int ip = 0;
- char local[16];
- struct udevice *pos, *n, *prev = NULL;
-
- dm_display_line(in, buf);
-
- if (list_empty(&in->child_head))
- return 0;
-
- len = strlen(buf);
- strncpy(local, buf, sizeof(local));
- snprintf(local + len, 2, "|");
- if (len && local[len - 1] == '`')
- local[len - 1] = ' ';
-
- list_for_each_entry_safe(pos, n, &in->child_head, sibling_node) {
- if (ip++)
- display_succ(prev, local);
- prev = pos;
- }
-
- snprintf(local + len, 2, "`");
- display_succ(prev, local);
-
- return 0;
-}
-
-static int dm_dump(struct udevice *dev)
-{
- if (!dev)
- return -EINVAL;
- return display_succ(dev, "");
-}
-
-static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- struct udevice *root;
-
- root = dm_root();
- printf("ROOT %08lx\n", (ulong)map_to_sysmem(root));
- return dm_dump(root);
-}
-
static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (list_empty(&uc->dev_head))
continue;
list_for_each_entry(dev, &uc->dev_head, uclass_node) {
- dm_display_line(dev, "");
+ dm_display_line(dev);
}
puts("\n");
}
--- /dev/null
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Note: Test coverage does not include 10-bit addressing
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <dm/device-internal.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+#include <dm/ut.h>
+#include <dm/util.h>
+#include <asm/state.h>
+#include <asm/test.h>
+
+static const int busnum;
+static const int chip = 0x2c;
+
+/* Test that we can find buses and chips */
+static int dm_test_i2c_find(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ const int no_chip = 0x10;
+
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_I2C, busnum,
+ false, &bus));
+
+ /*
+ * i2c_post_bind() will bind devices to chip selects. Check this then
+ * remove the emulation and the slave device.
+ */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
+ ut_assertok(i2c_probe(bus, chip, 0, &dev));
+ ut_asserteq(-ENODEV, i2c_probe(bus, no_chip, 0, &dev));
+ ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, &bus));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_find, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_read_write(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ uint8_t buf[5];
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
+ ut_assertok(i2c_get_chip(bus, chip, &dev));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
+ ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\0AB\0", sizeof(buf)));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_speed(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ uint8_t buf[5];
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
+ ut_assertok(i2c_get_chip(bus, chip, &dev));
+ ut_assertok(i2c_set_bus_speed(bus, 100000));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(i2c_set_bus_speed(bus, 400000));
+ ut_asserteq(400000, i2c_get_bus_speed(bus));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_asserteq(-EINVAL, i2c_write(dev, 0, buf, 5));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_speed, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_offset_len(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ uint8_t buf[5];
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
+ ut_assertok(i2c_get_chip(bus, chip, &dev));
+ ut_assertok(i2c_set_chip_offset_len(dev, 1));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+
+ /* This is not supported by the uclass */
+ ut_asserteq(-EINVAL, i2c_set_chip_offset_len(dev, 5));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_offset_len, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_probe_empty(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
+ ut_assertok(i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_probe_empty, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_bytewise(struct dm_test_state *dms)
+{
+ struct udevice *bus, *dev;
+ struct udevice *eeprom;
+ uint8_t buf[5];
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
+ ut_assertok(i2c_get_chip(bus, chip, &dev));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
+
+ /* Tell the EEPROM to only read/write one register at a time */
+ ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
+ ut_assertnonnull(eeprom);
+ sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_SINGLE_BYTE);
+
+ /* Now we only get the first byte - the rest will be 0xff */
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
+
+ /* If we do a separate transaction for each byte, it works */
+ ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
+
+ /* This will only write A */
+ ut_assertok(i2c_set_chip_flags(dev, 0));
+ ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
+
+ /* Check that the B was ignored */
+ ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\0A\0\0\0", sizeof(buf)));
+
+ /* Now write it again with the new flags, it should work */
+ ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS));
+ ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
+
+ ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS |
+ DM_I2C_CHIP_RD_ADDRESS));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "\0\0AB\0\0", sizeof(buf)));
+
+ /* Restore defaults */
+ sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE);
+ ut_assertok(i2c_set_chip_flags(dev, 0));
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_bytewise, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_i2c_offset(struct dm_test_state *dms)
+{
+ struct udevice *eeprom;
+ struct udevice *dev;
+ uint8_t buf[5];
+
+ ut_assertok(i2c_get_chip_for_busnum(busnum, chip, &dev));
+
+ /* Do a transfer so we can find the emulator */
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
+
+ /* Offset length 0 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
+ ut_assertok(i2c_set_chip_offset_len(dev, 0));
+ ut_assertok(i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "AB\0\0\0\0", sizeof(buf)));
+
+ /* Offset length 1 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
+ ut_assertok(i2c_set_chip_offset_len(dev, 1));
+ ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0, buf, 5));
+ ut_assertok(memcmp(buf, "ABAB\0", sizeof(buf)));
+
+ /* Offset length 2 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
+ ut_assertok(i2c_set_chip_offset_len(dev, 2));
+ ut_assertok(i2c_write(dev, 0x210, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0x210, buf, 5));
+ ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
+
+ /* Offset length 3 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
+ ut_assertok(i2c_set_chip_offset_len(dev, 2));
+ ut_assertok(i2c_write(dev, 0x410, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0x410, buf, 5));
+ ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
+
+ /* Offset length 4 */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
+ ut_assertok(i2c_set_chip_offset_len(dev, 2));
+ ut_assertok(i2c_write(dev, 0x420, (uint8_t *)"AB", 2));
+ ut_assertok(i2c_read(dev, 0x420, buf, 5));
+ ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
+
+ /* Restore defaults */
+ sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
+
+ return 0;
+}
+DM_TEST(dm_test_i2c_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
num-gpios = <10>;
};
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ compatible = "sandbox,i2c";
+ clock-frequency = <100000>;
+ eeprom@2c {
+ reg = <0x2c>;
+ compatible = "i2c-eeprom";
+ emul {
+ compatible = "sandbox,i2c-eeprom";
+ sandbox,filename = "i2c.bin";
+ sandbox,size = <256>;
+ };
+ };
+ };
+
spi@0 {
#address-cells = <1>;
#size-cells = <0>;
" -x | --extract: extract intel fd modules\n"
" -i | --inject <region>:<module> inject file <module> into region <region>\n"
" -w | --write <addr>:<file> write file to appear at memory address <addr>\n"
+ " multiple files can be written simultaneously\n"
" -s | --spifreq <20|33|50> set the SPI frequency\n"
" -e | --em100 set SPI frequency to 20MHz and disable\n"
" Dual Output Fast Read Support\n"
int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0;
int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0;
int create = 0;
- char *region_type_string = NULL, *src_fname = NULL;
- char *addr_str = NULL;
+ char *region_type_string = NULL, *inject_fname = NULL;
+ char *desc_fname = NULL, *addr_str = NULL;
int region_type = -1, inputfreq = 0;
enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
- unsigned int addr = 0;
+ unsigned int addr[WRITE_MAX];
+ char *wr_fname[WRITE_MAX];
+ unsigned char wr_idx, wr_num = 0;
int rom_size = -1;
bool write_it;
char *filename;
break;
case 'D':
mode_write_descriptor = 1;
- src_fname = optarg;
+ desc_fname = optarg;
break;
case 'e':
mode_em100 = 1;
break;
case 'i':
if (get_two_words(optarg, ®ion_type_string,
- &src_fname)) {
+ &inject_fname)) {
print_usage(argv[0]);
exit(EXIT_FAILURE);
}
break;
case 'w':
mode_write = 1;
- if (get_two_words(optarg, &addr_str, &src_fname)) {
- print_usage(argv[0]);
- exit(EXIT_FAILURE);
+ if (wr_num < WRITE_MAX) {
+ if (get_two_words(optarg, &addr_str,
+ &wr_fname[wr_num])) {
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ addr[wr_num] = strtol(optarg, NULL, 0);
+ wr_num++;
+ } else {
+ fprintf(stderr,
+ "The number of files to write simultaneously exceeds the limitation (%d)\n",
+ WRITE_MAX);
}
- addr = strtol(optarg, NULL, 0);
break;
case 'x':
mode_extract = 1;
}
if (mode_write_descriptor)
- ret = write_data(image, size, -size, src_fname);
+ ret = write_data(image, size, -size, desc_fname);
if (mode_inject)
- ret = inject_region(image, size, region_type, src_fname);
+ ret = inject_region(image, size, region_type, inject_fname);
- if (mode_write)
- ret = write_data(image, size, addr, src_fname);
+ if (mode_write) {
+ for (wr_idx = 0; wr_idx < wr_num; wr_idx++) {
+ ret = write_data(image, size,
+ addr[wr_idx], wr_fname[wr_idx]);
+ if (ret)
+ break;
+ }
+ }
if (mode_spifreq)
set_spi_frequency(image, size, spifreq);
#define IFDTOOL_VERSION "1.1-U-Boot"
+#define WRITE_MAX 16
+
enum spi_frequency {
SPI_FREQUENCY_20MHZ = 0,
SPI_FREQUENCY_33MHZ = 1,
projects / karo-tx-uboot.git / commitdiff