/ctags
/etags
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
# spl ais files
/spl/*.ais
E: jfd@GigabitNetworks.COM
D: Port to the MOUSSE board
+N: Mike Dunn
+E: mikedunn@newsguy.com
+D: Palmtreo680 board, docg4 nand flash driver
+
N: Dave Ellis
E: DGE@sixnetio.com
D: EEPROM Speedup, SXNI855T port
imx27lite i.MX27
qong i.MX31
+Mike Dunn <mikedunn@newsguy.com>
+ palmtreo680 pxa270
+
Kristoffer Ericson <kristoffer.ericson@gmail.com>
jornada SA1110
omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
omap5_evm ARM ARMV7 (OMAP5xx Soc)
+Suriyan Ramasami <suriyan.r@gmail.com>
+
+ goflexhome ARM926EJS (Kirkwood SoC)
+
Thierry Reding <thierry.reding@avionic-design.de>
plutux Tegra20 (ARM7 & A9 Dual Core)
Bo Shen <voice.shen@atmel.com>
at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+ sama5d3xek ARMV7 (SAMA5D31, D33, D34, D35 SoC)
Rajeshwari Shinde <rajeshwari.s@samsung.com>
SFFSDR ARM926EJS
+Lokesh Vutla <lokeshvutla@ti.com>
+
+ dra7xx_evm ARM ARMV7 (DRA7xx Soc)
+
Matt Waddel <matt.waddel@linaro.org>
- ca9x4_ct_vxp ARM ARMV7 (Quad Core)
+ vexpress_ca9x4 ARM ARMV7 (Quad Core)
+ vexpress_ca5x2 ARM ARMV7 (Dual Core)
Otavio Salvador <otavio@ossystems.com.br>
jadecpu ARM926EJS (MB86R01 SoC)
zmx25 ARM926EJS (imx25 SoC)
-Richard Woodruff <r-woodruff2@ti.com>
-
- omap2420h4 ARM1136EJS
+Josh Wu <josh.wu@atmel.com>
+ at91sam9n12ek ARM926EJS (AT91SAM9N12 SoC)
Ilya Yanok <yanok@emcraft.com>
vf610twr VF610
+Sergey Yanovich <ynvich@gmail.com>
+
+ lp8x4x xscale/pxa
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
# Board CPU #
#########################################################################
-Graeme Russ <graeme.russ@gmail.com>
+Simon Glass <sjg@chromium.org>
+
+ chromebook-x86 Coreboot runs first, then U-Boot
+ Supports Intel Sandy Bridge / Ivy Bridge so far
- eNET AMD SC520
+ Chromebooks for x86, including:
+ Samsung Series 5 Chromebook
+ Acer AC700 Chromebook
+ Acer C7 Chromebook
+ Samsung Chromebook 550
+ HP Pavillion Chromebook
+ Acer C710 Chromebook
+ Chromebook Pixel
#########################################################################
# MIPS Systems: #
openrisc-generic OpenRISC
+#########################################################################
+# Sandbox: #
+# #
+# Maintainer Name, Email Address #
+# Board CPU #
+#########################################################################
+
+Simon Glass <sjg@chromium.org>
+
+ sandbox sandbox
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
LIST_4xx="$(boards_by_cpu ppc4xx)"
-#########################################################################
-## MPC8220 Systems
-#########################################################################
-
-LIST_8220="$(boards_by_cpu mpc8220)"
-
#########################################################################
## MPC824x Systems
#########################################################################
${LIST_512x} \
${LIST_5xxx} \
${LIST_8xx} \
- ${LIST_8220} \
${LIST_824x} \
${LIST_8260} \
${LIST_83xx} \
cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
ifneq ($(CONFIG_TEGRA),)
-ifeq ($(CONFIG_OF_SEPARATE),y)
-nodtb=dtb
-dtbfile=$(obj)u-boot.dtb
-else
-nodtb=nodtb
-dtbfile=
-endif
-
-$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
+ cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+endif
endif
$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
$(MAKE) -C $@ all
endif # config.mk
+# ARM relocations should all be R_ARM_RELATIVE.
+checkarmreloc: $(obj)u-boot
+ @if test "R_ARM_RELATIVE" != \
+ "`readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
+ then echo "$< contains relocations other than \
+ R_ARM_RELATIVE"; false; fi
+
$(VERSION_FILE):
@mkdir -p $(dir $(VERSION_FILE))
@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
/mpc5xx Files specific to Freescale MPC5xx CPUs
/mpc5xxx Files specific to Freescale MPC5xxx CPUs
/mpc8xx Files specific to Freescale MPC8xx CPUs
- /mpc8220 Files specific to Freescale MPC8220 CPUs
/mpc824x Files specific to Freescale MPC824x CPUs
/mpc8260 Files specific to Freescale MPC8260 CPUs
/mpc85xx Files specific to Freescale MPC85xx CPUs
CONFIG_CMD_SF * Read/write/erase SPI NOR flash
CONFIG_CMD_SHA1SUM print sha1 memory digest
(requires CONFIG_CMD_MEMORY)
+ CONFIG_CMD_SOFTSWITCH * Soft switch setting command for BF60x
CONFIG_CMD_SOURCE "source" command Support
CONFIG_CMD_SPI * SPI serial bus support
CONFIG_CMD_TFTPSRV * TFTP transfer in server mode
use an arch-specific makefile fragment instead, for
example if more than one image needs to be produced.
+ CONFIG_FIT_SPL_PRINT
+ Printing information about a FIT image adds quite a bit of
+ code to SPL. So this is normally disabled in SPL. Use this
+ option to re-enable it. This will affect the output of the
+ bootm command when booting a FIT image.
+
Modem Support:
--------------
using the "bootz" command. The syntax of "bootz" command is the same
as the syntax of "bootm" command.
-Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
+Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
kernel with raw initrd images. The syntax is slightly different, the
address of the initrd must be augmented by it's size, in the following
format: "<initrd addres>:<initrd size>".
#define bi_bar bi_mbar_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
-#elif defined(CONFIG_MPC8220)
-#define bi_bar bi_mbar_base
#endif
#if defined(bi_bar)
endif
endif
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
endif
endif
+
+# check that only R_ARM_RELATIVE relocations are generated
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y += checkarmreloc
+endif
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
orr r0,r0,#0xd3
msr cpsr,r0
-#ifdef CONFIG_OMAP2420H4
- /* Copy vectors to mask ROM indirect addr */
- adr r0, _start /* r0 <- current position of code */
- add r0, r0, #4 /* skip reset vector */
- mov r2, #64 /* r2 <- size to copy */
- add r2, r0, r2 /* r2 <- source end address */
- mov r1, #SRAM_OFFSET0 /* build vect addr */
- mov r3, #SRAM_OFFSET1
- add r1, r1, r3
- mov r3, #SRAM_OFFSET2
- add r1, r1, r3
-next:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next /* loop until equal */
- bl cpy_clk_code /* put dpll adjust code behind vectors */
-#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- bx lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
-#endif
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- bx lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- mov pc, lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
*************************************************************************
*/
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
-#if !defined(CONFIG_TEGRA)
mov ip, lr
/*
* before relocating, we have to setup RAM timing
*/
bl lowlevel_init
mov lr, ip
-#endif
mov pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD
. = ALIGN(4);
.text :
{
+ *(.__image_copy_start)
arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
. = ALIGN(4);
- __image_copy_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
__bss_start = .;
.bss : { *(.bss*) }
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- mov pc, lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- mov pc, lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
COBJS-$(CONFIG_AT91_EFLASH) += eflash.o
COBJS-$(CONFIG_AT91_LED) += led.o
#if defined(CONFIG_GENERIC_ATMEL_MCI)
void at91_mci_hw_init(void)
{
+ /* Enable mci clock */
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ writel(1 << ATMEL_ID_MCI, &pmc->pcer);
+
at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
#if defined(CONFIG_ATMEL_MCI_PORTB)
at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
--- /dev/null
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+unsigned int has_lcdc()
+{
+ return 1;
+}
+
+void at91_serial0_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
+ writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
+ writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_serial3_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
+ writel(1 << ATMEL_ID_USART3, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+ if (cs_mask & (1 << 0))
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+ if (cs_mask & (1 << 1))
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+ if (cs_mask & (1 << 2))
+ at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
+ if (cs_mask & (1 << 3))
+ at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
+ at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
+ at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+ if (cs_mask & (1 << 0))
+ at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
+ if (cs_mask & (1 << 1))
+ at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
+ if (cs_mask & (1 << 2))
+ at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
+ if (cs_mask & (1 << 3))
+ at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
+}
+#endif
+
+void at91_mci_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
+
+ writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
+ at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
+ at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
+ at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+#endif
*/
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9X5)
+ || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */
gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9X5)
+ || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
/* mdiv <==> divisor
* 0 <==> 1
* 1 <==> 2
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
+COBJS-$(CONFIG_SOC_DA830) += da830_pinmux.o
COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
--- /dev/null
+/*
+ * Pinmux configurations for the DA830 SoCs
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI0 pin muxer settings */
+const struct pinmux_config spi0_pins_base[] = {
+ { pinmux(7), 1, 3 }, /* SPI0_SOMI */
+ { pinmux(7), 1, 4 }, /* SPI0_SIMO */
+ { pinmux(7), 1, 6 } /* SPI0_CLK */
+};
+
+const struct pinmux_config spi0_pins_scs0[] = {
+ { pinmux(7), 1, 7 } /* SPI0_SCS[0] */
+};
+
+const struct pinmux_config spi0_pins_ena[] = {
+ { pinmux(7), 1, 5 } /* SPI0_ENA */
+};
+
+/* NAND pin muxer settings */
+const struct pinmux_config emifa_pins_cs0[] = {
+ { pinmux(18), 1, 2 } /* EMA_CS[0] */
+};
+
+const struct pinmux_config emifa_pins_cs2[] = {
+ { pinmux(18), 1, 3 } /* EMA_CS[2] */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+ { pinmux(18), 1, 4 } /* EMA_CS[3] */
+};
+
+#ifdef CONFIG_USE_NAND
+const struct pinmux_config emifa_pins[] = {
+ { pinmux(13), 1, 6 }, /* EMA_D[0] */
+ { pinmux(13), 1, 7 }, /* EMA_D[1] */
+ { pinmux(14), 1, 0 }, /* EMA_D[2] */
+ { pinmux(14), 1, 1 }, /* EMA_D[3] */
+ { pinmux(14), 1, 2 }, /* EMA_D[4] */
+ { pinmux(14), 1, 3 }, /* EMA_D[5] */
+ { pinmux(14), 1, 4 }, /* EMA_D[6] */
+ { pinmux(14), 1, 5 }, /* EMA_D[7] */
+ { pinmux(14), 1, 6 }, /* EMA_D[8] */
+ { pinmux(14), 1, 7 }, /* EMA_D[9] */
+ { pinmux(15), 1, 0 }, /* EMA_D[10] */
+ { pinmux(15), 1, 1 }, /* EMA_D[11] */
+ { pinmux(15), 1, 2 }, /* EMA_D[12] */
+ { pinmux(15), 1, 3 }, /* EMA_D[13] */
+ { pinmux(15), 1, 4 }, /* EMA_D[14] */
+ { pinmux(15), 1, 5 }, /* EMA_D[15] */
+ { pinmux(15), 1, 6 }, /* EMA_A[0] */
+ { pinmux(15), 1, 7 }, /* EMA_A[1] */
+ { pinmux(16), 1, 0 }, /* EMA_A[2] */
+ { pinmux(16), 1, 1 }, /* EMA_A[3] */
+ { pinmux(16), 1, 2 }, /* EMA_A[4] */
+ { pinmux(16), 1, 3 }, /* EMA_A[5] */
+ { pinmux(16), 1, 4 }, /* EMA_A[6] */
+ { pinmux(16), 1, 5 }, /* EMA_A[7] */
+ { pinmux(16), 1, 6 }, /* EMA_A[8] */
+ { pinmux(16), 1, 7 }, /* EMA_A[9] */
+ { pinmux(17), 1, 0 }, /* EMA_A[10] */
+ { pinmux(17), 1, 1 }, /* EMA_A[11] */
+ { pinmux(17), 1, 2 }, /* EMA_A[12] */
+ { pinmux(17), 1, 3 }, /* EMA_BA[1] */
+ { pinmux(17), 1, 4 }, /* EMA_BA[0] */
+ { pinmux(17), 1, 5 }, /* EMA_CLK */
+ { pinmux(17), 1, 6 }, /* EMA_SDCKE */
+ { pinmux(17), 1, 7 }, /* EMA_CAS */
+ { pinmux(18), 1, 0 }, /* EMA_CAS */
+ { pinmux(18), 1, 1 }, /* EMA_WE */
+ { pinmux(18), 1, 5 }, /* EMA_OE */
+ { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */
+ { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */
+ { pinmux(10), 1, 0 } /* Tristate */
+};
+#endif
+
+/* EMAC PHY interface pins */
+const struct pinmux_config emac_pins_rmii[] = {
+ { pinmux(10), 2, 1 }, /* RMII_TXD[0] */
+ { pinmux(10), 2, 2 }, /* RMII_TXD[1] */
+ { pinmux(10), 2, 3 }, /* RMII_TXEN */
+ { pinmux(10), 2, 4 }, /* RMII_CRS_DV */
+ { pinmux(10), 2, 5 }, /* RMII_RXD[0] */
+ { pinmux(10), 2, 6 }, /* RMII_RXD[1] */
+ { pinmux(10), 2, 7 } /* RMII_RXER */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+ { pinmux(11), 2, 0 }, /* MDIO_CLK */
+ { pinmux(11), 2, 1 } /* MDIO_D */
+};
+
+const struct pinmux_config emac_pins_rmii_clk_source[] = {
+ { pinmux(9), 0, 5 } /* ref.clk from external source */
+};
+
+/* UART2 pin muxer settings */
+const struct pinmux_config uart2_pins_txrx[] = {
+ { pinmux(8), 2, 7 }, /* UART2_RXD */
+ { pinmux(9), 2, 0 } /* UART2_TXD */
+};
+
+/* I2C0 pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+ { pinmux(8), 2, 3 }, /* I2C0_SDA */
+ { pinmux(8), 2, 4 } /* I2C0_SCL */
+};
+
+/* USB0_DRVVBUS pin muxer settings */
+const struct pinmux_config usb_pins[] = {
+ { pinmux(9), 1, 1 } /* USB0_DRVVBUS */
+};
+
+#ifdef CONFIG_DAVINCI_MMC
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins_8bit[] = {
+ { pinmux(15), 2, 7 }, /* MMCSD0_CLK */
+ { pinmux(16), 2, 0 }, /* MMCSD0_CMD */
+ { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
+ { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
+ { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
+ { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
+ { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
+ { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
+ { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
+ { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */
+ /* DA830 supports 8-bit mode */
+};
+#endif
__rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
.bss : {
. = ALIGN(4);
__bss_start = .;
__rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
.bss : {
. = ALIGN(4);
__bss_start = .;
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- bx lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
-#endif
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- mov pc, lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- bx lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+ struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(0x83e70b13, &rtc->kick0r);
+ writel(0x95a4f1e0, &rtc->kick1r);
+
+ /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+ writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+void uart_soft_reset(void)
+{
+ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ u32 regval;
+
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_RESET;
+ writel(regval, &uart_base->uartsyscfg);
+ while ((readl(&uart_base->uartsyssts) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_SMART_IDLE_EN;
+ writel(regval, &uart_base->uartsyscfg);
+}
+#endif
;
}
-static void mpu_pll_config(void)
+void mpu_pll_config_val(int mpull_m)
{
u32 clkmode, clksel, div_m2;
;
clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+ clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
writel(clksel, &cmwkup->clkseldpllmpu);
div_m2 = div_m2 & ~CLK_DIV_MASK;
;
}
+static void mpu_pll_config(void)
+{
+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+}
+
static void core_pll_config(void)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
#
-# (C) Copyright 2003-2006
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
# See file CREDITS for list of people who contributed to this
# project.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_SAMA5D3) += sama5d3_devices.o
+COBJS-y += clock.o
+COBJS-y += cpu.o
+COBJS-y += reset.o
+COBJS-y += timer.o
-COBJS := $(BOARD).o flash.o
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
--- /dev/null
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+ switch (css) {
+ case AT91_PMC_MCKR_CSS_SLOW:
+ return CONFIG_SYS_AT91_SLOW_CLOCK;
+ case AT91_PMC_MCKR_CSS_MAIN:
+ return gd->arch.main_clk_rate_hz;
+ case AT91_PMC_MCKR_CSS_PLLA:
+ return gd->arch.plla_rate_hz;
+ }
+
+ return 0;
+}
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+ unsigned mul, div;
+
+ div = reg & 0xff;
+ mul = (reg >> 18) & 0x7f;
+ if (div && mul) {
+ freq /= div;
+ freq *= mul + 1;
+ } else {
+ freq = 0;
+ }
+
+ return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+ unsigned freq, mckr;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+ unsigned tmp;
+ /*
+ * When the bootloader initialized the main oscillator correctly,
+ * there's no problem using the cycle counter. But if it didn't,
+ * or when using oscillator bypass mode, we must be told the speed
+ * of the main clock.
+ */
+ if (!main_clock) {
+ do {
+ tmp = readl(&pmc->mcfr);
+ } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+ tmp &= AT91_PMC_MCFR_MAINF_MASK;
+ main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ }
+#endif
+ gd->arch.main_clk_rate_hz = main_clock;
+
+ /* report if PLLA is more than mildly overclocked */
+ gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+ /*
+ * MCK and CPU derive from one of those primary clocks.
+ * For now, assume this parentage won't change.
+ */
+ mckr = readl(&pmc->mckr);
+
+ /* plla divisor by 2 */
+ if (mckr & (1 << 12))
+ gd->arch.plla_rate_hz >>= 1;
+
+ gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+ freq = gd->arch.mck_rate_hz;
+
+ /* prescale */
+ freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
+
+ switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
+ case AT91_PMC_MCKR_MDIV_2:
+ gd->arch.mck_rate_hz = freq / 2;
+ break;
+ case AT91_PMC_MCKR_MDIV_3:
+ gd->arch.mck_rate_hz = freq / 3;
+ break;
+ case AT91_PMC_MCKR_MDIV_4:
+ gd->arch.mck_rate_hz = freq / 4;
+ break;
+ default:
+ break;
+ }
+
+ gd->arch.cpu_clk_rate_hz = freq;
+
+ return 0;
+}
+
+void at91_periph_clk_enable(int id)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ if (id > 31)
+ writel(1 << (id - 32), &pmc->pcer1);
+ else
+ writel(1 << id, &pmc->pcer);
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_dbu.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+ return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
+
+void arch_preboot_os(void)
+{
+ ulong cpiv;
+ at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+ cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+ /*
+ * Disable PITC
+ * Add 0x1000 to current counter to stop it faster
+ * without waiting for wrapping back to 0
+ */
+ writel(cpiv + 0x1000, &pit->mr);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ char buf[32];
+
+ printf("CPU: %s\n", get_cpu_name());
+ printf("Crystal frequency: %8s MHz\n",
+ strmhz(buf, get_main_clk_rate()));
+ printf("CPU clock : %8s MHz\n",
+ strmhz(buf, get_cpu_clk_rate()));
+ printf("Master clock : %8s MHz\n",
+ strmhz(buf, get_mck_clk_rate()));
+
+ return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+}
+
+unsigned int get_chip_id(void)
+{
+ return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+}
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
+
+/* Reset the cpu by telling the reset controller to do so */
+void reset_cpu(ulong ignored)
+{
+ at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+ writel(AT91_RSTC_KEY
+ | AT91_RSTC_CR_PROCRST /* Processor Reset */
+ | AT91_RSTC_CR_PERRST /* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+ | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
+#endif
+ , &rstc->cr);
+ /* never reached */
+ do { } while (1);
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sama5d3.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int has_emac()
+{
+ return cpu_is_sama5d31() || cpu_is_sama5d35();
+}
+
+unsigned int has_gmac()
+{
+ return !cpu_is_sama5d31();
+}
+
+unsigned int has_lcdc()
+{
+ return !cpu_is_sama5d35();
+}
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama5d3())
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D31:
+ return "SAMA5D31";
+ case ARCH_EXID_SAMA5D33:
+ return "SAMA5D33";
+ case ARCH_EXID_SAMA5D34:
+ return "SAMA5D34";
+ case ARCH_EXID_SAMA5D35:
+ return "SAMA5D35";
+ default:
+ return "Unknown CPU type";
+ }
+ else
+ return "Unknown CPU type";
+}
+
+void at91_serial0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART0);
+}
+
+void at91_serial1_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+void at91_serial2_hw_init(void)
+{
+ at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
+ at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART2);
+}
+
+void at91_seriald_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
+ at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SYS);
+}
+
+#if defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+ at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
+
+ if (cs_mask & (1 << 0))
+ at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+ if (cs_mask & (1 << 1))
+ at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+ if (cs_mask & (1 << 2))
+ at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+ if (cs_mask & (1 << 3))
+ at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
+ at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
+#ifdef CONFIG_ATMEL_MCI_8BIT
+ at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
+ at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
+ at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
+ at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
+#endif
+ at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC);
+}
+#endif
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
+ at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
+
+ /* The lower 16-bit of LCD only available on Port A */
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <div64.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * We're using the SAMA5D3x PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
+ */
+
+#define TIMER_LOAD_VAL 0xfffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, gd->arch.timer_rate_hz);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= gd->arch.timer_rate_hz;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
+int timer_init(void)
+{
+ at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+ /* Enable PITC Clock */
+ at91_periph_clk_enable(ATMEL_ID_SYS);
+
+ /* Enable PITC */
+ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
+
+ gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+ gd->arch.tbu = 0;
+ gd->arch.tbl = 0;
+
+ return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+ at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+ ulong now = readl(&pit->piir);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long start;
+ ulong tmo;
+
+ start = get_ticks(); /* get current timestamp */
+ tmo = usec_to_tick(usec); /* convert usecs to ticks */
+ while ((get_ticks() - start) < tmo)
+ ; /* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+ return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return gd->arch.timer_rate_hz;
+}
LIB = $(obj)lib$(SOC).o
-COBJS += clock.o power.o soc.o system.o pinmux.o
+COBJS += clock.o power.o soc.o system.o pinmux.o tzpc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 1024) * (freq / (p * (1 << s)));
} else {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
}
return fout;
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
- int shift;
+ int shift = 0;
sel = readl(&clk->src_fsys);
sel = (sel >> (dev_index << 2)) & 0xf;
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
- int shift;
+ int shift = 0;
sel = readl(&clk->src_fsys);
sel = (sel >> (dev_index << 2)) & 0xf;
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm/arch/tzpc.h>
-#include"setup.h"
+#include <asm/io.h>
/* Setting TZPC[TrustZone Protection Controller] */
void tzpc_init(void)
{
struct exynos_tzpc *tzpc;
- unsigned int addr;
+ unsigned int addr, start = 0, end = 0;
- for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+ start = samsung_get_base_tzpc();
+
+ if (cpu_is_exynos5())
+ end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+ else if (cpu_is_exynos4())
+ end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+
+ for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
tzpc = (struct exynos_tzpc *)addr;
- if (addr == TZPC0_BASE)
+ if (addr == start)
writel(R0SIZE, &tzpc->r0size);
writel(DECPROTXSET, &tzpc->decprot0set);
writel(DECPROTXSET, &tzpc->decprot1set);
- if (addr != TZPC9_BASE) {
- writel(DECPROTXSET, &tzpc->decprot2set);
- writel(DECPROTXSET, &tzpc->decprot3set);
- }
+ if (cpu_is_exynos5() && (addr == end))
+ break;
+
+ writel(DECPROTXSET, &tzpc->decprot2set);
+ writel(DECPROTXSET, &tzpc->decprot3set);
}
}
COBJS += clocks-common.o
COBJS += emif-common.o
COBJS += vc.o
+COBJS += abb.o
endif
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
--- /dev/null
+/*
+ *
+ * Adaptive Body Bias programming sequence for OMAP family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+ return -1;
+}
+
+static void abb_setup_timings(u32 setup)
+{
+ u32 sys_rate, sr2_cnt, clk_cycles;
+
+ /*
+ * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
+ * transition and must be programmed with the correct time at boot.
+ * The value programmed into the register is the number of SYS_CLK
+ * clock cycles that match a given wall time profiled for the ldo.
+ * This value depends on:
+ * settling time of ldo in micro-seconds (varies per OMAP family),
+ * of clock cycles per SYS_CLK period (varies per OMAP family),
+ * the SYS_CLK frequency in MHz (varies per board)
+ * The formula is:
+ *
+ * ldo settling time (in micro-seconds)
+ * SR2_WTCNT_VALUE = ------------------------------------------
+ * (# system clock cycles) * (sys_clk period)
+ *
+ * Put another way:
+ *
+ * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
+ *
+ * To avoid dividing by zero multiply both "# clock cycles" and
+ * "settling time" by 10 such that the final result is the one we want.
+ */
+
+ /* calculate SR2_WTCNT_VALUE */
+ sys_rate = DIV_ROUND(V_OSCK, 1000000);
+ clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
+ sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
+
+ setbits_le32(setup,
+ sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
+}
+
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+ u32 txdone, u32 txdone_mask, u32 opp)
+{
+ u32 abb_type_mask, opp_sel_mask;
+
+ /* sanity check */
+ if (!setup || !control || !txdone)
+ return;
+
+ /* setup ABB only in case of Fast or Slow OPP */
+ switch (opp) {
+ case OMAP_ABB_FAST_OPP:
+ abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK;
+ opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK;
+ break;
+ case OMAP_ABB_SLOW_OPP:
+ abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK;
+ opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK;
+ break;
+ default:
+ return;
+ }
+
+ /*
+ * For some OMAP silicons additional setup for LDOVBB register is
+ * required. This is determined by data retrieved from corresponding
+ * OPP EFUSE register. Data, which is retrieved from EFUSE - is
+ * ABB enable/disable flag and VSET value, which must be copied
+ * to LDOVBB register. If function call fails - return quietly,
+ * it means no ABB is required for such silicon.
+ *
+ * For silicons, which don't require LDOVBB setup "fuse" and
+ * "ldovbb" offsets are not defined. ABB will be initialized in
+ * the common way for them.
+ */
+ if (fuse && ldovbb) {
+ if (abb_setup_ldovbb(fuse, ldovbb))
+ return;
+ }
+
+ /* clear ABB registers */
+ writel(0, setup);
+ writel(0, control);
+
+ /* configure timings, based on oscillator value */
+ abb_setup_timings(setup);
+
+ /* clear pending interrupts before setup */
+ setbits_le32(txdone, txdone_mask);
+
+ /* select ABB type */
+ setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK);
+
+ /* initiate ABB ldo change */
+ setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
+
+ /* wait until transition complete */
+ if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY))
+ puts("Error: ABB txdone is not set\n");
+
+ /* clear ABB tranxdone */
+ setbits_le32(txdone, txdone_mask);
+}
DECLARE_GLOBAL_DATA_PTR;
+void save_omap_boot_params(void)
+{
+ u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+ u8 boot_device;
+ u32 dev_desc, dev_data;
+
+ if ((rom_params < NON_SECURE_SRAM_START) ||
+ (rom_params > NON_SECURE_SRAM_END))
+ return;
+
+ /*
+ * rom_params can be type casted to omap_boot_parameters and
+ * used. But it not correct to assume that romcode structure
+ * encoding would be same as u-boot. So use the defined offsets.
+ */
+ gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+ *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+ gd->arch.omap_boot_params.ch_flags =
+ *((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+ if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+ (boot_device <= MMC_BOOT_DEVICES_END)) {
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX)
+ if ((omap_hw_init_context() ==
+ OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u8 *)(rom_params + BOOT_MODE_OFFSET));
+ } else
+#endif
+ {
+ dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+ dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u32 *)(dev_data + BOOT_MODE_OFFSET));
+ }
+ }
+}
+
#ifdef CONFIG_SPL_BUILD
u32 spl_boot_device(void)
{
* MA 02111-1307 USA
*/
#include <common.h>
+#include <i2c.h>
#include <asm/omap_common.h>
#include <asm/gpio.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
- 13000000, /* 13 MHz */
+ 20000000, /* 20 MHz */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
27000000, /* 27 MHz */
38400000, /* 38.4 MHz */
- 20000000, /* 20 MHz */
};
static inline u32 __get_sys_clk_index(void)
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl((*prcm)->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
- /*
- * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
- * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
- * NUM_SYS_CLK. So considering the last 3 bits as the index
- * for the dpll param array.
- */
- ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+
+ if (omap_revision() == DRA752_ES1_0)
+ /* Select the sys clk for dpll_abe */
+ clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
+ CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
+ CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
#else
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
/*
u32 offset = volt_mv;
int ret = 0;
+ if (!volt_mv)
+ return;
+
+ pmic->pmic_bus_init();
/* See if we can first get the GPIO if needed */
if (pmic->gpio_en)
ret = gpio_request(pmic->gpio, "PMIC_GPIO");
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
- if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
- vcore_reg, offset_code))
+ if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 1);
}
+static u32 optimize_vcore_voltage(struct volts const *v)
+{
+ u32 val;
+ if (!v->value)
+ return 0;
+ if (!v->efuse.reg)
+ return v->value;
+
+ switch (v->efuse.reg_bits) {
+ case 16:
+ val = readw(v->efuse.reg);
+ break;
+ case 32:
+ val = readl(v->efuse.reg);
+ break;
+ default:
+ printf("Error: efuse 0x%08x bits=%d unknown\n",
+ v->efuse.reg, v->efuse.reg_bits);
+ return v->value;
+ }
+
+ if (!val) {
+ printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
+ v->efuse.reg, v->efuse.reg_bits, v->value);
+ return v->value;
+ }
+
+ debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
+ __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
+ return val;
+}
+
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
*/
void scale_vcores(struct vcores_data const *vcores)
{
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+ u32 val;
+
+ val = optimize_vcore_voltage(&vcores->core);
+ do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
+
+ val = optimize_vcore_voltage(&vcores->mpu);
+ do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
+
+ /* Configure MPU ABB LDO after scale */
+ abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+ (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
+ (*prcm)->prm_abbldo_mpu_setup,
+ (*prcm)->prm_abbldo_mpu_ctrl,
+ (*prcm)->prm_irqstatus_mpu_2,
+ OMAP_ABB_MPU_TXDONE_MASK,
+ OMAP_ABB_FAST_OPP);
- do_scale_vcore(vcores->core.addr, vcores->core.value,
- vcores->core.pmic);
+ val = optimize_vcore_voltage(&vcores->mm);
+ do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
- do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
- vcores->mpu.pmic);
+ val = optimize_vcore_voltage(&vcores->gpu);
+ do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
- do_scale_vcore(vcores->mm.addr, vcores->mm.value,
- vcores->mm.pmic);
+ val = optimize_vcore_voltage(&vcores->eve);
+ do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
+
+ val = optimize_vcore_voltage(&vcores->iva);
+ do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
+ timer_init();
scale_vcores(*omap_vcores);
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
enable_basic_uboot_clocks();
}
+
+void gpi2c_init(void)
+{
+ static int gpi2c = 1;
+
+ if (gpi2c) {
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ gpi2c = 0;
+ }
+}
#include <common.h>
#include <asm/emif.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/utils.h>
writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() >= OMAP5430_ES1_0) {
+ if ((omap_revision() >= OMAP5430_ES1_0) ||
+ (omap_revision() == DRA752_ES1_0)) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
&emif->emif_l3_config);
} else if (omap_revision() >= OMAP4460_ES1_0) {
__udelay(130);
}
+static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+ config_data_eye_leveling_samples(base);
+
+ writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+ writel(regs->sdram_config, &emif->emif_sdram_config);
+}
+
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
return rev;
}
-void omap_rev_string(void)
+static void omap_rev_string(void)
{
u32 omap_rev = omap_revision();
u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
{
}
-static void save_omap_boot_params(void)
-{
- u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
- u8 boot_device;
- u32 dev_desc, dev_data;
-
- if ((rom_params < NON_SECURE_SRAM_START) ||
- (rom_params > NON_SECURE_SRAM_END))
- return;
-
- /*
- * rom_params can be type casted to omap_boot_parameters and
- * used. But it not correct to assume that romcode structure
- * encoding would be same as u-boot. So use the defined offsets.
- */
- gd->arch.omap_boot_params.omap_bootdevice = boot_device =
- *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
-
- gd->arch.omap_boot_params.ch_flags =
- *((u8 *)(rom_params + CH_FLAGS_OFFSET));
-
- if ((boot_device >= MMC_BOOT_DEVICES_START) &&
- (boot_device <= MMC_BOOT_DEVICES_END)) {
- if ((omap_hw_init_context() ==
- OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
- gd->arch.omap_boot_params.omap_bootmode =
- *((u8 *)(rom_params + BOOT_MODE_OFFSET));
- } else {
- dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
- dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
- gd->arch.omap_boot_params.omap_bootmode =
- *((u32 *)(dev_data + BOOT_MODE_OFFSET));
- }
- }
-}
-
#ifdef CONFIG_ARCH_CPU_INIT
/*
* SOC specific cpu init
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
- timer_init();
-
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <asm/omap_common.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
/*
* Define Master code if there are multiple masters on the I2C_SR bus.
* omap_vc_init() - Initialization for Voltage controller
* @speed_khz: I2C buspeed in KHz
*/
-void omap_vc_init(u16 speed_khz)
+static void omap_vc_init(u16 speed_khz)
{
u32 val;
u32 sys_clk_khz, cycles_hi, cycles_low;
/* All good.. */
return 0;
}
+
+void sri2c_init(void)
+{
+ static int sri2c = 1;
+
+ if (sri2c) {
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+ sri2c = 0;
+ }
+ return;
+}
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/clocks_omap3.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data twl6030 = {
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data tps62361 = {
.step = 10000, /* 10 mV represented in uV */
.start_code = 0,
.gpio = TPS62361_VSEL0_GPIO,
- .gpio_en = 1
+ .gpio_en = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct vcores_data omap4430_volts_es1 = {
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
.control_ldosram_core_voltage_ctrl = 0x4A002328,
+ .control_usbotghs_ctrl = 0x4A00233C,
+ .control_padconf_core_base = 0x4A100000,
.control_pbiaslite = 0x4A100600,
.control_lpddr2io1_0 = 0x4A100638,
.control_lpddr2io1_1 = 0x4A10063C,
.control_lpddr2io2_3 = 0x4A100654,
.control_efuse_1 = 0x4A100700,
.control_efuse_2 = 0x4A100704,
+ .control_padconf_wkup_base = 0x4A31E000,
};
COBJS += sdram.o
COBJS += prcm-regs.o
COBJS += hw_data.o
+COBJS += abb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
--- /dev/null
+/*
+ *
+ * Adaptive Body Bias programming sequence for OMAP5 family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+
+/*
+ * Setup LDOVBB for OMAP5.
+ * On OMAP5+ some ABB settings are fused. They are handled
+ * in the following way:
+ *
+ * 1. corresponding EFUSE register contains ABB enable bit
+ * and VSET value
+ * 2. If ABB enable bit is set to 1, than ABB should be
+ * enabled, otherwise ABB should be disabled
+ * 3. If ABB is enabled, than VSET value should be copied
+ * to corresponding MUX control register
+ */
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+ u32 vset;
+
+ /*
+ * ABB parameters must be properly fused
+ * otherwise ABB should be disabled
+ */
+ vset = readl(fuse);
+ if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK))
+ return -1;
+
+ /* prepare VSET value for LDOVBB mux register */
+ vset &= OMAP5_ABB_FUSE_VSET_MASK;
+ vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1;
+ vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
+ vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
+
+ /* setup LDOVBB using fused value */
+ clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
+
+ return 0;
+}
* MA 02111-1307 USA
*/
#include <common.h>
+#include <palmas.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/emif.h>
};
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
- {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+ {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params
};
static const struct dpll_params
- core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
- {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
- {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
- {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
+ core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
+ {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
+ {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
+ {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
+ {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
- {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
+ {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
};
static const struct dpll_params
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
- {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
- {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
+ {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
+ {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */
+static const struct dpll_params
+ abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
-static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
- {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+ {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
struct dplls omap5_dplls_es1 = {
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_ddr532_dra7xx,
+ .core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
+ .abe = abe_dpll_params_sysclk2_361267khz,
+ .iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
- .ddr = ddr_dpll_params_1066mhz,
+ .ddr = ddr_dpll_params_2128mhz,
};
struct pmic_data palmas = {
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
+};
+
+struct pmic_data tps659038 = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 10000, /* 10 mV represented in uV */
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ .start_code = 6,
+ .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
};
struct vcores_data omap5430_volts = {
.mm.pmic = &palmas,
};
+struct vcores_data dra752_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
+ .mpu.pmic = &tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
+ .eve.pmic = &tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
+ .gpu.pmic = &tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
+ .iva.pmic = &tps659038,
+};
+
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
clk_modules_explicit_en_essential,
1);
- /* Select 384Mhz for GPU as its the POR for ES1.0 */
- setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_HYD_GCLK_MASK);
- setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_CORE_GCLK_MASK);
-
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
+const struct ctrl_ioregs ioregs_dra7xx_es1 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x80808080,
+ .ctrl_ddrio_0 = 0xbae8c631,
+ .ctrl_ddrio_1 = 0xb46318d8,
+ .ctrl_ddrio_2 = 0x84210000,
+ .ctrl_emif_sdram_config_ext = 0xb2c00000,
+ .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
case DRA752_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
- *omap_vcores = &omap5430_volts_es2;
+ *omap_vcores = &dra752_volts;
*ctrl = &dra7xx_ctrl;
break;
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = &ioregs_omap5430;
- break;
+ break;
case OMAP5432_ES1_0:
*regs = &ioregs_omap5432_es1;
- break;
+ break;
case OMAP5432_ES2_0:
- case DRA752_ES1_0:
*regs = &ioregs_omap5432_es2;
- break;
+ break;
+ case DRA752_ES1_0:
+ *regs = &ioregs_dra7xx_es1;
+ break;
default:
printf("\n INVALID OMAP REVISION ");
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif2_sdram_config_ext);
- /* Disable DLL select */
- io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
+ if (is_omap54xx()) {
+ /* Disable DLL select */
+ io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif1_sdram_config);
+ writel(io_settings,
+ (*ctrl)->control_port_emif1_sdram_config);
- io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
+ io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif2_sdram_config);
+ writel(io_settings,
+ (*ctrl)->control_port_emif2_sdram_config);
+ } else {
+ writel(ioregs->ctrl_ddr_ctrl_ext_0,
+ (*ctrl)->control_ddr_control_ext_0);
+ }
}
/*
u32 sysclk_ind = get_sys_clk_index();
u32 omap_rev = omap_revision();
+ if (!is_omap54xx())
+ return;
+
mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
div_factor = srcomp_parameters[sysclk_ind].divide_factor;
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
.prm_rstctrl = 0x4ae07b00,
.prm_rstst = 0x4ae07b04,
+ .prm_rsttime = 0x4ae07b08,
.prm_vc_val_bypass = 0x4ae07ba0,
.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
.prm_sldo_mpu_ctrl = 0x4ae07bd0,
.prm_sldo_mm_setup = 0x4ae07bd4,
.prm_sldo_mm_ctrl = 0x4ae07bd8,
+
+ /* SCRM stuff, used by some boards */
+ .scrm_auxclk0 = 0x4ae0a310,
+ .scrm_auxclk1 = 0x4ae0a314,
};
struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
+ .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
+ .control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
.control_port_emif2_sdram_config = 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318,
+ .control_padconf_wkup_base = 0x4AE0C800,
.control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
.control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
.control_padconf_mode = 0x4AE0CDA8,
.control_srcomp_east_side = 0x4A002E7C,
.control_srcomp_west_side = 0x4A002E80,
.control_srcomp_code_latch = 0x4A002E84,
+ .control_ddr_control_ext_0 = 0x4A002E88,
.control_padconf_core_base = 0x4A003400,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+ /* prm irqstatus regs */
+ .prm_irqstatus_mpu_2 = 0x4ae06014,
+
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
.prm_sldo_mpu_ctrl = 0x4ae07cd0,
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
+ .prm_abbldo_mpu_setup = 0x4ae07cdc,
+ .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+
+ /* SCRM stuff, used by some boards */
+ .scrm_auxclk0 = 0x4ae0a310,
+ .scrm_auxclk1 = 0x4ae0a314,
};
struct prcm_regs const dra7xx_prcm = {
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
+ .cm_abe_pll_sys_clksel = 0x4ae06118,
.cm_wkup_clkstctrl = 0x4ae07800,
.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
+ .sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
+ .sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.emif_rd_wr_exec_thresh = 0x40000305
};
+const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
+ .sdram_config_init = 0x61851ab2,
+ .sdram_config = 0x61851ab2,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0E20400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_3 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0020400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_3 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009D009D,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.is_ma_present = 0x1
};
-const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
+/*
+ * DRA752 EVM board has 1.5 GB of memory
+ * EMIF1 --> 2Gb * 2 = 512MB
+ * EMIF2 --> 2Gb * 4 = 1GB
+ * so mapping 1GB interleaved and 512MB non-interleaved
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x80640300,
+ .dmm_lisa_map_2 = 0xC0500220,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF1 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x0,
- .dmm_lisa_map_3 = 0x80500100,
+ .dmm_lisa_map_2 = 0x80500100,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF2 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80600200,
+ .dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
*regs = &emif_regs_532_mhz_2cs_es2;
break;
case OMAP5432_ES2_0:
+ *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+ break;
case DRA752_ES1_0:
+ switch (emif_nr) {
+ case 1:
+ *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
+ break;
+ case 2:
+ *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
+ break;
+ }
+ break;
default:
- *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+ *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
}
}
break;
case DRA752_ES1_0:
default:
- *dmm_lisa_regs = &lisa_map_512M_x_1;
+ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
}
}
0x00000000,
0x00000000,
0x00000000,
- 0x00000077
+ 0x00000077,
+ 0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000000,
0x00000000,
0x00000000,
- 0x00000057
+ 0x00000057,
+ 0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000000,
0x00000000,
0x00000000,
- 0x00000057
+ 0x00000057,
+ 0x0
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x009E009E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x0,
+ 0x600020,
+ 0x40010080,
+ 0x8102040
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x009D009D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x0,
+ 0x600020,
+ 0x40010080,
+ 0x8102040
};
const struct lpddr2_mr_regs mr_regs = {
.mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
*regs = ddr3_ext_phy_ctrl_const_base_es1;
break;
case OMAP5432_ES2_0:
+ *regs = ddr3_ext_phy_ctrl_const_base_es2;
+ break;
case DRA752_ES1_0:
+ if (emif_nr == 1)
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
+ else
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+ break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
+ u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
+ emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
* external phy 6-24 registers do not change with
* ddr frequency
*/
- emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
+ emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
LIB = $(obj)libs5p-common.o
COBJS-y += cpu_info.o
+ifndef CONFIG_SPL_BUILD
COBJS-y += timer.o
COBJS-y += sromc.o
COBJS-$(CONFIG_PWM) += pwm.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-#ifndef CONFIG_SPL_BUILD
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-ENTRY(relocate_code)
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-
-relocate_done:
-
- bx lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-ENDPROC(relocate_code)
-
-#endif
-
ENTRY(c_runtime_cpu_setup)
/*
* If I-cache is enabled invalidate it
PLATFORM_LDFLAGS += -EB
USE_PRIVATE_LIBGCC = yes
-# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
-PLATFORM_RELFLAGS += -ffunction-sections
-LDFLAGS_u-boot += --gc-sections
-
# =========================================================================
#
# Supply options according to compiler version
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- bx lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
. = ALIGN(4);
.text :
{
+ *(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
*(.text*)
}
. = ALIGN(4);
- __image_copy_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
KEEP(*(.__bss_end));
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
+PLATFORM_CPPFLAGS += -mcpu=xscale
# =========================================================================
#
# Supply options according to compiler version
{
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
- asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2));
+ asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
bl _main
/*------------------------------------------------------------------------------*/
-#ifndef CONFIG_SPL_BUILD
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
-/* Disable the Dcache RAM lock for stack now */
-#ifdef CONFIG_CPU_PXA25X
- mov r12, lr
- bl cpu_init_crit
- mov lr, r12
-#endif
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_CPU_PXA25X
/*
- * fix .rel.dyn relocations
+ * Unlock (actually, disable) the cache now that board_init_f
+ * is done. We could do this earlier but we would need to add
+ * a new C runtime hook, whereas c_runtime_cpu_setup already
+ * exists.
+ * As this routine is just a call to cpu_init_crit, let us
+ * tail-optimize and do a simple branch here.
*/
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
+ b cpu_init_crit
+#else
bx lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
#endif
- .globl c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
- bx lr
-
/*
*************************************************************************
*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
- orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- bx lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
- .globl relocate_code
-relocate_code:
- mov r6, r0 /* save addr of destination */
-
- adr r0, _start
- subs r9, r6, r0 /* r9 <- relocation offset */
- beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _image_copy_end_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-relocate_done:
-
- mov pc, lr
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
switch (chip_id) {
case CHIPID_TEGRA20:
switch (sku_id) {
+ case SKU_ID_T20_7:
case SKU_ID_T20:
return TEGRA_SOC_T20;
case SKU_ID_T25SE:
case CHIPID_TEGRA114:
switch (sku_id) {
case SKU_ID_T114_ENG:
+ case SKU_ID_T114_1:
return TEGRA_SOC_T114;
}
break;
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
u32 reg;
+ /* Only enable the SCU on T20/T25 */
+ if (tegra_get_chip() != CHIPID_TEGRA20)
+ return;
+
/* If SCU already setup/enabled, return */
if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
return;
unsigned effective_rate;
int mux_bits, divider_bits, source;
int divider;
+ int xdiv = 0;
/* work out the source clock and set it */
source = get_periph_clock_source(periph_id, parent, &mux_bits,
÷r_bits);
+ divider = find_best_divider(divider_bits, pll_rate[parent],
+ rate, &xdiv);
if (extra_div)
- divider = find_best_divider(divider_bits, pll_rate[parent],
- rate, extra_div);
- else
- divider = clk_get_divider(divider_bits, pll_rate[parent],
- rate);
+ *extra_div = xdiv;
+
assert(divider >= 0);
if (adjust_periph_pll(periph_id, source, mux_bits, divider))
return -1U;
__rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_end = .;
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
projects / karo-tx-uboot.git / commitdiff