ddr: altera: sequencer: Wrap misc remaining macros
authorMarek Vasut <marex@denx.de>
Sun, 2 Aug 2015 17:18:47 +0000 (19:18 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:17:37 +0000 (08:17 +0200)
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
arch/arm/mach-socfpga/include/mach/sdram.h
board/altera/socfpga/wrap_sdram_config.c
drivers/ddr/altera/sequencer.c

index 9d0e083..f12bb84 100644 (file)
@@ -18,6 +18,7 @@ void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
 
 #define SDR_CTRLGRP_ADDRESS    (SOCFPGA_SDR_ADDRESS | 0x5000)
 
@@ -199,6 +200,22 @@ struct socfpga_sdram_io_config {
        u8      shift_dqs_en_when_shift_dqs;
 };
 
+struct socfpga_sdram_misc_config {
+       u32     reg_file_init_seq_signature;
+       u8      afi_rate_ratio;
+       u8      calib_lfifo_offset;
+       u8      calib_vfifo_offset;
+       u8      enable_super_quick_calibration;
+       u8      max_latency_count_width;
+       u8      read_valid_fifo_size;
+       u8      tinit_cntr0_val;
+       u8      tinit_cntr1_val;
+       u8      tinit_cntr2_val;
+       u8      treset_cntr0_val;
+       u8      treset_cntr1_val;
+       u8      treset_cntr2_val;
+};
+
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
index 2697867..cd97cc5 100644 (file)
@@ -267,6 +267,22 @@ struct socfpga_sdram_io_config io_config = {
        .shift_dqs_en_when_shift_dqs    = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
 };
 
+struct socfpga_sdram_misc_config misc_config = {
+       .afi_rate_ratio                 = AFI_RATE_RATIO,
+       .calib_lfifo_offset             = CALIB_LFIFO_OFFSET,
+       .calib_vfifo_offset             = CALIB_VFIFO_OFFSET,
+       .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
+       .max_latency_count_width        = MAX_LATENCY_COUNT_WIDTH,
+       .read_valid_fifo_size           = READ_VALID_FIFO_SIZE,
+       .reg_file_init_seq_signature    = REG_FILE_INIT_SEQ_SIGNATURE,
+       .tinit_cntr0_val                = TINIT_CNTR0_VAL,
+       .tinit_cntr1_val                = TINIT_CNTR1_VAL,
+       .tinit_cntr2_val                = TINIT_CNTR2_VAL,
+       .treset_cntr0_val               = TRESET_CNTR0_VAL,
+       .treset_cntr1_val               = TRESET_CNTR1_VAL,
+       .treset_cntr2_val               = TRESET_CNTR2_VAL,
+};
+
 const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
 {
        return &sdram_config;
@@ -293,3 +309,8 @@ const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
 {
        return &io_config;
 }
+
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
+{
+       return &misc_config;
+}
index 4596f55..70956fa 100644 (file)
@@ -43,6 +43,7 @@ static struct socfpga_sdr_ctrl *sdr_ctrl =
 
 const struct socfpga_sdram_rw_mgr_config *rwcfg;
 const struct socfpga_sdram_io_config *iocfg;
+const struct socfpga_sdram_misc_config *misccfg;
 
 #define DELTA_D                1
 
@@ -3700,6 +3701,7 @@ int sdram_calibration_full(void)
 
        rwcfg = socfpga_get_sdram_rwmgr_config();
        iocfg = socfpga_get_sdram_io_config();
+       misccfg = socfpga_get_sdram_misc_config();
 
        /* Set the calibration enabled by default */
        gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;